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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_hal_i2c.c |
3 | * @file stm32f1xx_hal_i2c.c |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief I2C HAL module driver. |
5 | * @brief I2C HAL module driver. |
| 6 | * This file provides firmware functions to manage the following |
6 | * This file provides firmware functions to manage the following |
| 7 | * functionalities of the Inter Integrated Circuit (I2C) peripheral: |
7 | * functionalities of the Inter Integrated Circuit (I2C) peripheral: |
| 8 | * + Initialization and de-initialization functions |
8 | * + Initialization and de-initialization functions |
| 9 | * + IO operation functions |
9 | * + IO operation functions |
| 10 | * + Peripheral State, Mode and Error functions |
10 | * + Peripheral State, Mode and Error functions |
| 11 | * |
11 | * |
| 12 | @verbatim |
12 | ****************************************************************************** |
| 13 | ============================================================================== |
13 | * @attention |
| 14 | ##### How to use this driver ##### |
14 | * |
| 15 | ============================================================================== |
15 | * Copyright (c) 2016 STMicroelectronics. |
| 16 | [..] |
16 | * All rights reserved. |
| 17 | The I2C HAL driver can be used as follows: |
17 | * |
| 18 | 18 | * This software is licensed under terms that can be found in the LICENSE file |
|
| 19 | (#) Declare a I2C_HandleTypeDef handle structure, for example: |
19 | * in the root directory of this software component. |
| 20 | I2C_HandleTypeDef hi2c; |
20 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 21 | 21 | * |
|
| 22 | (#)Initialize the I2C low level resources by implementing the @ref HAL_I2C_MspInit() API: |
22 | ****************************************************************************** |
| 23 | (##) Enable the I2Cx interface clock |
23 | @verbatim |
| 24 | (##) I2C pins configuration |
24 | ============================================================================== |
| 25 | (+++) Enable the clock for the I2C GPIOs |
25 | ##### How to use this driver ##### |
| 26 | (+++) Configure I2C pins as alternate function open-drain |
26 | ============================================================================== |
| 27 | (##) NVIC configuration if you need to use interrupt process |
27 | [..] |
| 28 | (+++) Configure the I2Cx interrupt priority |
28 | The I2C HAL driver can be used as follows: |
| 29 | (+++) Enable the NVIC I2C IRQ Channel |
29 | |
| 30 | (##) DMA Configuration if you need to use DMA process |
30 | (#) Declare a I2C_HandleTypeDef handle structure, for example: |
| 31 | (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel |
31 | I2C_HandleTypeDef hi2c; |
| 32 | (+++) Enable the DMAx interface clock using |
32 | |
| 33 | (+++) Configure the DMA handle parameters |
33 | (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: |
| 34 | (+++) Configure the DMA Tx or Rx channel |
34 | (##) Enable the I2Cx interface clock |
| 35 | (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle |
35 | (##) I2C pins configuration |
| 36 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on |
36 | (+++) Enable the clock for the I2C GPIOs |
| 37 | the DMA Tx or Rx channel |
37 | (+++) Configure I2C pins as alternate function open-drain |
| 38 | 38 | (##) NVIC configuration if you need to use interrupt process |
|
| 39 | (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, |
39 | (+++) Configure the I2Cx interrupt priority |
| 40 | Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. |
40 | (+++) Enable the NVIC I2C IRQ Channel |
| 41 | 41 | (##) DMA Configuration if you need to use DMA process |
|
| 42 | (#) Initialize the I2C registers by calling the @ref HAL_I2C_Init(), configures also the low level Hardware |
42 | (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel |
| 43 | (GPIO, CLOCK, NVIC...etc) by calling the customized @ref HAL_I2C_MspInit() API. |
43 | (+++) Enable the DMAx interface clock using |
| 44 | 44 | (+++) Configure the DMA handle parameters |
|
| 45 | (#) To check if target device is ready for communication, use the function @ref HAL_I2C_IsDeviceReady() |
45 | (+++) Configure the DMA Tx or Rx channel |
| 46 | 46 | (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle |
|
| 47 | (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : |
47 | (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on |
| 48 | 48 | the DMA Tx or Rx channel |
|
| 49 | *** Polling mode IO operation *** |
49 | |
| 50 | ================================= |
50 | (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1, |
| 51 | [..] |
51 | Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure. |
| 52 | (+) Transmit in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Transmit() |
52 | |
| 53 | (+) Receive in master mode an amount of data in blocking mode using @ref HAL_I2C_Master_Receive() |
53 | (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware |
| 54 | (+) Transmit in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Transmit() |
54 | (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit() API. |
| 55 | (+) Receive in slave mode an amount of data in blocking mode using @ref HAL_I2C_Slave_Receive() |
55 | |
| 56 | 56 | (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() |
|
| 57 | *** Polling mode IO MEM operation *** |
57 | |
| 58 | ===================================== |
58 | (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : |
| 59 | [..] |
59 | |
| 60 | (+) Write an amount of data in blocking mode to a specific memory address using @ref HAL_I2C_Mem_Write() |
60 | *** Polling mode IO operation *** |
| 61 | (+) Read an amount of data in blocking mode from a specific memory address using @ref HAL_I2C_Mem_Read() |
61 | ================================= |
| 62 | 62 | [..] |
|
| 63 | 63 | (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() |
|
| 64 | *** Interrupt mode IO operation *** |
64 | (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() |
| 65 | =================================== |
65 | (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() |
| 66 | [..] |
66 | (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() |
| 67 | (+) Transmit in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Transmit_IT() |
67 | |
| 68 | (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can |
68 | *** Polling mode IO MEM operation *** |
| 69 | add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() |
69 | ===================================== |
| 70 | (+) Receive in master mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Receive_IT() |
70 | [..] |
| 71 | (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can |
71 | (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() |
| 72 | add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() |
72 | (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() |
| 73 | (+) Transmit in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Transmit_IT() |
73 | |
| 74 | (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can |
74 | |
| 75 | add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() |
75 | *** Interrupt mode IO operation *** |
| 76 | (+) Receive in slave mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Receive_IT() |
76 | =================================== |
| 77 | (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can |
77 | [..] |
| 78 | add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() |
78 | (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() |
| 79 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
79 | (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can |
| 80 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
80 | add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() |
| 81 | (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() |
81 | (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() |
| 82 | (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can |
82 | (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can |
| 83 | add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() |
83 | add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() |
| 84 | 84 | (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() |
|
| 85 | *** Interrupt mode or DMA mode IO sequential operation *** |
85 | (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can |
| 86 | ========================================================== |
86 | add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() |
| 87 | [..] |
87 | (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() |
| 88 | (@) These interfaces allow to manage a sequential transfer with a repeated start condition |
88 | (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can |
| 89 | when a direction change during transfer |
89 | add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() |
| 90 | [..] |
90 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
| 91 | (+) A specific option field manage the different steps of a sequential transfer |
91 | add his own code by customization of function pointer HAL_I2C_ErrorCallback() |
| 92 | (+) Option field values are defined through @ref I2C_XferOptions_definition and are listed below: |
92 | (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() |
| 93 | (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode |
93 | (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can |
| 94 | (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address |
94 | add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() |
| 95 | and data to transfer without a final stop condition |
95 | |
| 96 | (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address |
96 | *** Interrupt mode or DMA mode IO sequential operation *** |
| 97 | and data to transfer without a final stop condition, an then permit a call the same master sequential interface |
97 | ========================================================== |
| 98 | several times (like @ref HAL_I2C_Master_Seq_Transmit_IT() then @ref HAL_I2C_Master_Seq_Transmit_IT() |
98 | [..] |
| 99 | or @ref HAL_I2C_Master_Seq_Transmit_DMA() then @ref HAL_I2C_Master_Seq_Transmit_DMA()) |
99 | (@) These interfaces allow to manage a sequential transfer with a repeated start condition |
| 100 | (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address |
100 | when a direction change during transfer |
| 101 | and with new data to transfer if the direction change or manage only the new data to transfer |
101 | [..] |
| 102 | if no direction change and without a final stop condition in both cases |
102 | (+) A specific option field manage the different steps of a sequential transfer |
| 103 | (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address |
103 | (+) Option field values are defined through I2C_XferOptions_definition and are listed below: |
| 104 | and with new data to transfer if the direction change or manage only the new data to transfer |
104 | (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in no sequential mode |
| 105 | if no direction change and with a final stop condition in both cases |
105 | (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address |
| 106 | (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential |
106 | and data to transfer without a final stop condition |
| 107 | interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). |
107 | (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address |
| 108 | Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
108 | and data to transfer without a final stop condition, an then permit a call the same master sequential interface |
| 109 | or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
109 | several times (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() |
| 110 | or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
110 | or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) |
| 111 | or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). |
111 | (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address |
| 112 | Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit |
112 | and with new data to transfer if the direction change or manage only the new data to transfer |
| 113 | without stopping the communication and so generate a restart condition. |
113 | if no direction change and without a final stop condition in both cases |
| 114 | (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential |
114 | (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address |
| 115 | interface. |
115 | and with new data to transfer if the direction change or manage only the new data to transfer |
| 116 | Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
116 | if no direction change and with a final stop condition in both cases |
| 117 | or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
117 | (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential |
| 118 | or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
118 | interface several times (link with option I2C_FIRST_AND_NEXT_FRAME). |
| 119 | or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). |
119 | Usage can, transfer several bytes one by one using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
| 120 | Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. |
120 | or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
| 121 | 121 | or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME) |
|
| 122 | (+) Different sequential I2C interfaces are listed below: |
122 | or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME). |
| 123 | (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Transmit_IT() |
123 | Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the opposite interface Receive or Transmit |
| 124 | or using @ref HAL_I2C_Master_Seq_Transmit_DMA() |
124 | without stopping the communication and so generate a restart condition. |
| 125 | (+++) At transmission end of current frame transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can |
125 | (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after each call of the same master sequential |
| 126 | add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() |
126 | interface. |
| 127 | (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Master_Seq_Receive_IT() |
127 | Usage can, transfer several bytes one by one with a restart with slave address between each bytes using HAL_I2C_Master_Seq_Transmit_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
| 128 | or using @ref HAL_I2C_Master_Seq_Receive_DMA() |
128 | or HAL_I2C_Master_Seq_Receive_IT(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
| 129 | (+++) At reception end of current frame transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can |
129 | or HAL_I2C_Master_Seq_Transmit_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME) |
| 130 | add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() |
130 | or HAL_I2C_Master_Seq_Receive_DMA(option I2C_FIRST_FRAME then I2C_OTHER_FRAME). |
| 131 | (++) Abort a master IT or DMA I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() |
131 | Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic generation of STOP condition. |
| 132 | (+++) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can |
132 | |
| 133 | add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() |
133 | (+) Different sequential I2C interfaces are listed below: |
| 134 | (++) Enable/disable the Address listen mode in slave I2C mode using @ref HAL_I2C_EnableListen_IT() @ref HAL_I2C_DisableListen_IT() |
134 | (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Transmit_IT() |
| 135 | (+++) When address slave I2C match, @ref HAL_I2C_AddrCallback() is executed and user can |
135 | or using HAL_I2C_Master_Seq_Transmit_DMA() |
| 136 | add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). |
136 | (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can |
| 137 | (+++) At Listen mode end @ref HAL_I2C_ListenCpltCallback() is executed and user can |
137 | add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() |
| 138 | add his own code by customization of function pointer @ref HAL_I2C_ListenCpltCallback() |
138 | (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Seq_Receive_IT() |
| 139 | (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Transmit_IT() |
139 | or using HAL_I2C_Master_Seq_Receive_DMA() |
| 140 | or using @ref HAL_I2C_Slave_Seq_Transmit_DMA() |
140 | (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can |
| 141 | (+++) At transmission end of current frame transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can |
141 | add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() |
| 142 | add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() |
142 | (++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() |
| 143 | (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using @ref HAL_I2C_Slave_Seq_Receive_IT() |
143 | (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can |
| 144 | or using @ref HAL_I2C_Slave_Seq_Receive_DMA() |
144 | add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() |
| 145 | (+++) At reception end of current frame transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can |
145 | (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT() |
| 146 | add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() |
146 | (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can |
| 147 | (++) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
147 | add his own code to check the Address Match Code and the transmission direction request by master (Write/Read). |
| 148 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
148 | (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can |
| 149 | 149 | add his own code by customization of function pointer HAL_I2C_ListenCpltCallback() |
|
| 150 | *** Interrupt mode IO MEM operation *** |
150 | (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Transmit_IT() |
| 151 | ======================================= |
151 | or using HAL_I2C_Slave_Seq_Transmit_DMA() |
| 152 | [..] |
152 | (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can |
| 153 | (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using |
153 | add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() |
| 154 | @ref HAL_I2C_Mem_Write_IT() |
154 | (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Seq_Receive_IT() |
| 155 | (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can |
155 | or using HAL_I2C_Slave_Seq_Receive_DMA() |
| 156 | add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() |
156 | (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can |
| 157 | (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using |
157 | add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() |
| 158 | @ref HAL_I2C_Mem_Read_IT() |
158 | (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
| 159 | (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can |
159 | add his own code by customization of function pointer HAL_I2C_ErrorCallback() |
| 160 | add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() |
160 | |
| 161 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
161 | *** Interrupt mode IO MEM operation *** |
| 162 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
162 | ======================================= |
| 163 | 163 | [..] |
|
| 164 | *** DMA mode IO operation *** |
164 | (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using |
| 165 | ============================== |
165 | HAL_I2C_Mem_Write_IT() |
| 166 | [..] |
166 | (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can |
| 167 | (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using |
167 | add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() |
| 168 | @ref HAL_I2C_Master_Transmit_DMA() |
168 | (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using |
| 169 | (+) At transmission end of transfer, @ref HAL_I2C_MasterTxCpltCallback() is executed and user can |
169 | HAL_I2C_Mem_Read_IT() |
| 170 | add his own code by customization of function pointer @ref HAL_I2C_MasterTxCpltCallback() |
170 | (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can |
| 171 | (+) Receive in master mode an amount of data in non-blocking mode (DMA) using |
171 | add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() |
| 172 | @ref HAL_I2C_Master_Receive_DMA() |
172 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
| 173 | (+) At reception end of transfer, @ref HAL_I2C_MasterRxCpltCallback() is executed and user can |
173 | add his own code by customization of function pointer HAL_I2C_ErrorCallback() |
| 174 | add his own code by customization of function pointer @ref HAL_I2C_MasterRxCpltCallback() |
174 | |
| 175 | (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using |
175 | *** DMA mode IO operation *** |
| 176 | @ref HAL_I2C_Slave_Transmit_DMA() |
176 | ============================== |
| 177 | (+) At transmission end of transfer, @ref HAL_I2C_SlaveTxCpltCallback() is executed and user can |
177 | [..] |
| 178 | add his own code by customization of function pointer @ref HAL_I2C_SlaveTxCpltCallback() |
178 | (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using |
| 179 | (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using |
179 | HAL_I2C_Master_Transmit_DMA() |
| 180 | @ref HAL_I2C_Slave_Receive_DMA() |
180 | (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can |
| 181 | (+) At reception end of transfer, @ref HAL_I2C_SlaveRxCpltCallback() is executed and user can |
181 | add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() |
| 182 | add his own code by customization of function pointer @ref HAL_I2C_SlaveRxCpltCallback() |
182 | (+) Receive in master mode an amount of data in non-blocking mode (DMA) using |
| 183 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
183 | HAL_I2C_Master_Receive_DMA() |
| 184 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
184 | (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can |
| 185 | (+) Abort a master I2C process communication with Interrupt using @ref HAL_I2C_Master_Abort_IT() |
185 | add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() |
| 186 | (+) End of abort process, @ref HAL_I2C_AbortCpltCallback() is executed and user can |
186 | (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using |
| 187 | add his own code by customization of function pointer @ref HAL_I2C_AbortCpltCallback() |
187 | HAL_I2C_Slave_Transmit_DMA() |
| 188 | 188 | (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can |
|
| 189 | *** DMA mode IO MEM operation *** |
189 | add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() |
| 190 | ================================= |
190 | (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using |
| 191 | [..] |
191 | HAL_I2C_Slave_Receive_DMA() |
| 192 | (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using |
192 | (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can |
| 193 | @ref HAL_I2C_Mem_Write_DMA() |
193 | add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() |
| 194 | (+) At Memory end of write transfer, @ref HAL_I2C_MemTxCpltCallback() is executed and user can |
194 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
| 195 | add his own code by customization of function pointer @ref HAL_I2C_MemTxCpltCallback() |
195 | add his own code by customization of function pointer HAL_I2C_ErrorCallback() |
| 196 | (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using |
196 | (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() |
| 197 | @ref HAL_I2C_Mem_Read_DMA() |
197 | (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can |
| 198 | (+) At Memory end of read transfer, @ref HAL_I2C_MemRxCpltCallback() is executed and user can |
198 | add his own code by customization of function pointer HAL_I2C_AbortCpltCallback() |
| 199 | add his own code by customization of function pointer @ref HAL_I2C_MemRxCpltCallback() |
199 | |
| 200 | (+) In case of transfer Error, @ref HAL_I2C_ErrorCallback() function is executed and user can |
200 | *** DMA mode IO MEM operation *** |
| 201 | add his own code by customization of function pointer @ref HAL_I2C_ErrorCallback() |
201 | ================================= |
| 202 | 202 | [..] |
|
| 203 | 203 | (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using |
|
| 204 | *** I2C HAL driver macros list *** |
204 | HAL_I2C_Mem_Write_DMA() |
| 205 | ================================== |
205 | (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can |
| 206 | [..] |
206 | add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback() |
| 207 | Below the list of most used macros in I2C HAL driver. |
207 | (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using |
| 208 | 208 | HAL_I2C_Mem_Read_DMA() |
|
| 209 | (+) @ref __HAL_I2C_ENABLE: Enable the I2C peripheral |
209 | (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can |
| 210 | (+) @ref __HAL_I2C_DISABLE: Disable the I2C peripheral |
210 | add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback() |
| 211 | (+) @ref __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not |
211 | (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can |
| 212 | (+) @ref __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag |
212 | add his own code by customization of function pointer HAL_I2C_ErrorCallback() |
| 213 | (+) @ref __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt |
213 | |
| 214 | (+) @ref __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt |
214 | |
| 215 | 215 | *** I2C HAL driver macros list *** |
|
| 216 | *** Callback registration *** |
216 | ================================== |
| 217 | ============================================= |
217 | [..] |
| 218 | [..] |
218 | Below the list of most used macros in I2C HAL driver. |
| 219 | The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 |
219 | |
| 220 | allows the user to configure dynamically the driver callbacks. |
220 | (+) __HAL_I2C_ENABLE: Enable the I2C peripheral |
| 221 | Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() |
221 | (+) __HAL_I2C_DISABLE: Disable the I2C peripheral |
| 222 | to register an interrupt callback. |
222 | (+) __HAL_I2C_GET_FLAG: Checks whether the specified I2C flag is set or not |
| 223 | [..] |
223 | (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag |
| 224 | Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: |
224 | (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt |
| 225 | (+) MasterTxCpltCallback : callback for Master transmission end of transfer. |
225 | (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt |
| 226 | (+) MasterRxCpltCallback : callback for Master reception end of transfer. |
226 | |
| 227 | (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. |
227 | *** Callback registration *** |
| 228 | (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. |
228 | ============================================= |
| 229 | (+) ListenCpltCallback : callback for end of listen mode. |
229 | [..] |
| 230 | (+) MemTxCpltCallback : callback for Memory transmission end of transfer. |
230 | The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 |
| 231 | (+) MemRxCpltCallback : callback for Memory reception end of transfer. |
231 | allows the user to configure dynamically the driver callbacks. |
| 232 | (+) ErrorCallback : callback for error detection. |
232 | Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() |
| 233 | (+) AbortCpltCallback : callback for abort completion process. |
233 | to register an interrupt callback. |
| 234 | (+) MspInitCallback : callback for Msp Init. |
234 | [..] |
| 235 | (+) MspDeInitCallback : callback for Msp DeInit. |
235 | Function HAL_I2C_RegisterCallback() allows to register following callbacks: |
| 236 | This function takes as parameters the HAL peripheral handle, the Callback ID |
236 | (+) MasterTxCpltCallback : callback for Master transmission end of transfer. |
| 237 | and a pointer to the user callback function. |
237 | (+) MasterRxCpltCallback : callback for Master reception end of transfer. |
| 238 | [..] |
238 | (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. |
| 239 | For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). |
239 | (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. |
| 240 | [..] |
240 | (+) ListenCpltCallback : callback for end of listen mode. |
| 241 | Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default |
241 | (+) MemTxCpltCallback : callback for Memory transmission end of transfer. |
| 242 | weak function. |
242 | (+) MemRxCpltCallback : callback for Memory reception end of transfer. |
| 243 | @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, |
243 | (+) ErrorCallback : callback for error detection. |
| 244 | and the Callback ID. |
244 | (+) AbortCpltCallback : callback for abort completion process. |
| 245 | This function allows to reset following callbacks: |
245 | (+) MspInitCallback : callback for Msp Init. |
| 246 | (+) MasterTxCpltCallback : callback for Master transmission end of transfer. |
246 | (+) MspDeInitCallback : callback for Msp DeInit. |
| 247 | (+) MasterRxCpltCallback : callback for Master reception end of transfer. |
247 | This function takes as parameters the HAL peripheral handle, the Callback ID |
| 248 | (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. |
248 | and a pointer to the user callback function. |
| 249 | (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. |
249 | [..] |
| 250 | (+) ListenCpltCallback : callback for end of listen mode. |
250 | For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). |
| 251 | (+) MemTxCpltCallback : callback for Memory transmission end of transfer. |
251 | [..] |
| 252 | (+) MemRxCpltCallback : callback for Memory reception end of transfer. |
252 | Use function HAL_I2C_UnRegisterCallback to reset a callback to the default |
| 253 | (+) ErrorCallback : callback for error detection. |
253 | weak function. |
| 254 | (+) AbortCpltCallback : callback for abort completion process. |
254 | HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, |
| 255 | (+) MspInitCallback : callback for Msp Init. |
255 | and the Callback ID. |
| 256 | (+) MspDeInitCallback : callback for Msp DeInit. |
256 | This function allows to reset following callbacks: |
| 257 | [..] |
257 | (+) MasterTxCpltCallback : callback for Master transmission end of transfer. |
| 258 | For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). |
258 | (+) MasterRxCpltCallback : callback for Master reception end of transfer. |
| 259 | [..] |
259 | (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. |
| 260 | By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET |
260 | (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. |
| 261 | all callbacks are set to the corresponding weak functions: |
261 | (+) ListenCpltCallback : callback for end of listen mode. |
| 262 | examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). |
262 | (+) MemTxCpltCallback : callback for Memory transmission end of transfer. |
| 263 | Exception done for MspInit and MspDeInit functions that are |
263 | (+) MemRxCpltCallback : callback for Memory reception end of transfer. |
| 264 | reset to the legacy weak functions in the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() only when |
264 | (+) ErrorCallback : callback for error detection. |
| 265 | these callbacks are null (not registered beforehand). |
265 | (+) AbortCpltCallback : callback for abort completion process. |
| 266 | If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() |
266 | (+) MspInitCallback : callback for Msp Init. |
| 267 | keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. |
267 | (+) MspDeInitCallback : callback for Msp DeInit. |
| 268 | [..] |
268 | [..] |
| 269 | Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. |
269 | For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). |
| 270 | Exception done MspInit/MspDeInit functions that can be registered/unregistered |
270 | [..] |
| 271 | in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, |
271 | By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET |
| 272 | thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. |
272 | all callbacks are set to the corresponding weak functions: |
| 273 | Then, the user first registers the MspInit/MspDeInit user callbacks |
273 | examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). |
| 274 | using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() |
274 | Exception done for MspInit and MspDeInit functions that are |
| 275 | or @ref HAL_I2C_Init() function. |
275 | reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when |
| 276 | [..] |
276 | these callbacks are null (not registered beforehand). |
| 277 | When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or |
277 | If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() |
| 278 | not defined, the callback registration feature is not available and all callbacks |
278 | keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. |
| 279 | are set to the corresponding weak functions. |
279 | [..] |
| 280 | 280 | Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. |
|
| 281 | 281 | Exception done MspInit/MspDeInit functions that can be registered/unregistered |
|
| 282 | *** I2C Workarounds linked to Silicon Limitation *** |
282 | in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, |
| 283 | ==================================================== |
283 | thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. |
| 284 | [..] |
284 | Then, the user first registers the MspInit/MspDeInit user callbacks |
| 285 | Below the list of all silicon limitations implemented for HAL on STM32F1xx product. |
285 | using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() |
| 286 | (@) See ErrataSheet to know full silicon limitation list of your product. |
286 | or HAL_I2C_Init() function. |
| 287 | 287 | [..] |
|
| 288 | (+) Workarounds Implemented inside I2C HAL Driver |
288 | When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or |
| 289 | (++) Wrong data read into data register (Polling and Interrupt mode) |
289 | not defined, the callback registration feature is not available and all callbacks |
| 290 | (++) Start cannot be generated after a misplaced Stop |
290 | are set to the corresponding weak functions. |
| 291 | (++) Some software events must be managed before the current byte is being transferred: |
291 | |
| 292 | Workaround: Use DMA in general, except when the Master is receiving a single byte. |
292 | |
| 293 | For Interupt mode, I2C should have the highest priority in the application. |
293 | *** I2C Workarounds linked to Silicon Limitation *** |
| 294 | (++) Mismatch on the "Setup time for a repeated Start condition" timing parameter: |
294 | ==================================================== |
| 295 | Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if |
295 | [..] |
| 296 | supported by the slave. |
296 | Below the list of all silicon limitations implemented for HAL on STM32F1xx product. |
| 297 | (++) Data valid time (tVD;DAT) violated without the OVR flag being set: |
297 | (@) See ErrataSheet to know full silicon limitation list of your product. |
| 298 | Workaround: If the slave device allows it, use the clock stretching mechanism |
298 | |
| 299 | by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in @ref HAL_I2C_Init. |
299 | (+) Workarounds Implemented inside I2C HAL Driver |
| 300 | 300 | (++) Wrong data read into data register (Polling and Interrupt mode) |
|
| 301 | [..] |
301 | (++) Start cannot be generated after a misplaced Stop |
| 302 | (@) You can refer to the I2C HAL driver header file for more useful macros |
302 | (++) Some software events must be managed before the current byte is being transferred: |
| 303 | 303 | Workaround: Use DMA in general, except when the Master is receiving a single byte. |
|
| 304 | @endverbatim |
304 | For Interrupt mode, I2C should have the highest priority in the application. |
| 305 | ****************************************************************************** |
305 | (++) Mismatch on the "Setup time for a repeated Start condition" timing parameter: |
| 306 | * @attention |
306 | Workaround: Reduce the frequency down to 88 kHz or use the I2C Fast-mode if |
| 307 | * |
307 | supported by the slave. |
| 308 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
308 | (++) Data valid time (tVD;DAT) violated without the OVR flag being set: |
| 309 | * All rights reserved.</center></h2> |
309 | Workaround: If the slave device allows it, use the clock stretching mechanism |
| 310 | * |
310 | by programming NoStretchMode = I2C_NOSTRETCH_DISABLE in HAL_I2C_Init. |
| 311 | * This software component is licensed by ST under BSD 3-Clause license, |
311 | |
| 312 | * the "License"; You may not use this file except in compliance with the |
312 | [..] |
| 313 | * License. You may obtain a copy of the License at: |
313 | (@) You can refer to the I2C HAL driver header file for more useful macros |
| 314 | * opensource.org/licenses/BSD-3-Clause |
314 | |
| 315 | * |
315 | @endverbatim |
| 316 | ****************************************************************************** |
316 | */ |
| 317 | */ |
317 | |
| 318 | 318 | /* Includes ------------------------------------------------------------------*/ |
|
| 319 | /* Includes ------------------------------------------------------------------*/ |
319 | #include "stm32f1xx_hal.h" |
| 320 | #include "stm32f1xx_hal.h" |
320 | |
| 321 | 321 | /** @addtogroup STM32F1xx_HAL_Driver |
|
| 322 | /** @addtogroup STM32F1xx_HAL_Driver |
322 | * @{ |
| 323 | * @{ |
323 | */ |
| 324 | */ |
324 | |
| 325 | 325 | /** @defgroup I2C I2C |
|
| 326 | /** @defgroup I2C I2C |
326 | * @brief I2C HAL module driver |
| 327 | * @brief I2C HAL module driver |
327 | * @{ |
| 328 | * @{ |
328 | */ |
| 329 | */ |
329 | |
| 330 | 330 | #ifdef HAL_I2C_MODULE_ENABLED |
|
| 331 | #ifdef HAL_I2C_MODULE_ENABLED |
331 | |
| 332 | 332 | /* Private typedef -----------------------------------------------------------*/ |
|
| 333 | /* Private typedef -----------------------------------------------------------*/ |
333 | /* Private define ------------------------------------------------------------*/ |
| 334 | /* Private define ------------------------------------------------------------*/ |
334 | /** @defgroup I2C_Private_Define I2C Private Define |
| 335 | /** @addtogroup I2C_Private_Define |
335 | * @{ |
| 336 | * @{ |
336 | */ |
| 337 | */ |
337 | #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ |
| 338 | #define I2C_TIMEOUT_FLAG 35U /*!< Timeout 35 ms */ |
338 | #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ |
| 339 | #define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */ |
339 | #define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */ |
| 340 | #define I2C_TIMEOUT_STOP_FLAG 5U /*!< Timeout 5 ms */ |
340 | #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ |
| 341 | #define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */ |
341 | |
| 342 | 342 | /* Private define for @ref PreviousState usage */ |
|
| 343 | /* Private define for @ref PreviousState usage */ |
343 | #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ |
| 344 | #define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | (uint32_t)HAL_I2C_STATE_BUSY_RX) & (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */ |
344 | #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ |
| 345 | #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */ |
345 | #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ |
| 346 | #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */ |
346 | #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ |
| 347 | #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */ |
347 | #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ |
| 348 | #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */ |
348 | #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ |
| 349 | #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | (uint32_t)HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */ |
349 | |
| 350 | 350 | /** |
|
| 351 | /** |
351 | * @} |
| 352 | * @} |
352 | */ |
| 353 | */ |
353 | |
| 354 | 354 | /* Private macro -------------------------------------------------------------*/ |
|
| 355 | /* Private macro -------------------------------------------------------------*/ |
355 | /** @addtogroup I2C_Private_Macros |
| 356 | /* Private variables ---------------------------------------------------------*/ |
356 | * @{ |
| 357 | /* Private function prototypes -----------------------------------------------*/ |
357 | */ |
| 358 | 358 | /* Macro to get remaining data to transfer on DMA side */ |
|
| 359 | /** @defgroup I2C_Private_Functions I2C Private Functions |
359 | #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__) |
| 360 | * @{ |
360 | /** |
| 361 | */ |
361 | * @} |
| 362 | /* Private functions to handle DMA transfer */ |
362 | */ |
| 363 | static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); |
363 | /* Private variables ---------------------------------------------------------*/ |
| 364 | static void I2C_DMAError(DMA_HandleTypeDef *hdma); |
364 | /* Private function prototypes -----------------------------------------------*/ |
| 365 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); |
365 | |
| 366 | 366 | /** @defgroup I2C_Private_Functions I2C Private Functions |
|
| 367 | static void I2C_ITError(I2C_HandleTypeDef *hi2c); |
367 | * @{ |
| 368 | 368 | */ |
|
| 369 | static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); |
369 | /* Private functions to handle DMA transfer */ |
| 370 | static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); |
370 | static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma); |
| 371 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
371 | static void I2C_DMAError(DMA_HandleTypeDef *hdma); |
| 372 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
372 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); |
| 373 | 373 | ||
| 374 | /* Private functions to handle flags during polling transfer */ |
374 | static void I2C_ITError(I2C_HandleTypeDef *hi2c); |
| 375 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); |
375 | |
| 376 | static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); |
376 | static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); |
| 377 | static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
377 | static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart); |
| 378 | static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
378 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
| 379 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
379 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart); |
| 380 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
380 | |
| 381 | static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c); |
381 | /* Private functions to handle flags during polling transfer */ |
| 382 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); |
382 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart); |
| 383 | 383 | static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart); |
|
| 384 | /* Private functions for I2C transfer IRQ handler */ |
384 | static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
| 385 | static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); |
385 | static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
| 386 | static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); |
386 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
| 387 | static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); |
387 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart); |
| 388 | static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); |
388 | static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c); |
| 389 | static void I2C_Master_SB(I2C_HandleTypeDef *hi2c); |
389 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c); |
| 390 | static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); |
390 | |
| 391 | static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); |
391 | /* Private functions for I2C transfer IRQ handler */ |
| 392 | 392 | static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c); |
|
| 393 | static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); |
393 | static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c); |
| 394 | static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); |
394 | static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c); |
| 395 | static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); |
395 | static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c); |
| 396 | static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); |
396 | static void I2C_Master_SB(I2C_HandleTypeDef *hi2c); |
| 397 | static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags); |
397 | static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c); |
| 398 | static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); |
398 | static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c); |
| 399 | static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c); |
399 | |
| 400 | 400 | static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c); |
|
| 401 | static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); |
401 | static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c); |
| 402 | 402 | static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c); |
|
| 403 | /* Private function to Convert Specific options */ |
403 | static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c); |
| 404 | static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); |
404 | static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags); |
| 405 | /** |
405 | static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c); |
| 406 | * @} |
406 | static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c); |
| 407 | */ |
407 | |
| 408 | 408 | static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c); |
|
| 409 | /* Exported functions --------------------------------------------------------*/ |
409 | |
| 410 | 410 | /* Private function to Convert Specific options */ |
|
| 411 | /** @defgroup I2C_Exported_Functions I2C Exported Functions |
411 | static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); |
| 412 | * @{ |
412 | |
| 413 | */ |
413 | /* Private function to flush DR register */ |
| 414 | 414 | static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c); |
|
| 415 | /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions |
415 | /** |
| 416 | * @brief Initialization and Configuration functions |
416 | * @} |
| 417 | * |
417 | */ |
| 418 | @verbatim |
418 | |
| 419 | =============================================================================== |
419 | /* Exported functions --------------------------------------------------------*/ |
| 420 | ##### Initialization and de-initialization functions ##### |
420 | |
| 421 | =============================================================================== |
421 | /** @defgroup I2C_Exported_Functions I2C Exported Functions |
| 422 | [..] This subsection provides a set of functions allowing to initialize and |
422 | * @{ |
| 423 | deinitialize the I2Cx peripheral: |
423 | */ |
| 424 | 424 | ||
| 425 | (+) User must Implement HAL_I2C_MspInit() function in which he configures |
425 | /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions |
| 426 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). |
426 | * @brief Initialization and Configuration functions |
| 427 | 427 | * |
|
| 428 | (+) Call the function HAL_I2C_Init() to configure the selected device with |
428 | @verbatim |
| 429 | the selected configuration: |
429 | =============================================================================== |
| 430 | (++) Communication Speed |
430 | ##### Initialization and de-initialization functions ##### |
| 431 | (++) Duty cycle |
431 | =============================================================================== |
| 432 | (++) Addressing mode |
432 | [..] This subsection provides a set of functions allowing to initialize and |
| 433 | (++) Own Address 1 |
433 | deinitialize the I2Cx peripheral: |
| 434 | (++) Dual Addressing mode |
434 | |
| 435 | (++) Own Address 2 |
435 | (+) User must Implement HAL_I2C_MspInit() function in which he configures |
| 436 | (++) General call mode |
436 | all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC). |
| 437 | (++) Nostretch mode |
437 | |
| 438 | 438 | (+) Call the function HAL_I2C_Init() to configure the selected device with |
|
| 439 | (+) Call the function HAL_I2C_DeInit() to restore the default configuration |
439 | the selected configuration: |
| 440 | of the selected I2Cx peripheral. |
440 | (++) Communication Speed |
| 441 | 441 | (++) Duty cycle |
|
| 442 | @endverbatim |
442 | (++) Addressing mode |
| 443 | * @{ |
443 | (++) Own Address 1 |
| 444 | */ |
444 | (++) Dual Addressing mode |
| 445 | 445 | (++) Own Address 2 |
|
| 446 | /** |
446 | (++) General call mode |
| 447 | * @brief Initializes the I2C according to the specified parameters |
447 | (++) Nostretch mode |
| 448 | * in the I2C_InitTypeDef and initialize the associated handle. |
448 | |
| 449 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
449 | (+) Call the function HAL_I2C_DeInit() to restore the default configuration |
| 450 | * the configuration information for the specified I2C. |
450 | of the selected I2Cx peripheral. |
| 451 | * @retval HAL status |
451 | |
| 452 | */ |
452 | @endverbatim |
| 453 | HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) |
453 | * @{ |
| 454 | { |
454 | */ |
| 455 | uint32_t freqrange; |
455 | |
| 456 | uint32_t pclk1; |
456 | /** |
| 457 | 457 | * @brief Initializes the I2C according to the specified parameters |
|
| 458 | /* Check the I2C handle allocation */ |
458 | * in the I2C_InitTypeDef and initialize the associated handle. |
| 459 | if (hi2c == NULL) |
459 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 460 | { |
460 | * the configuration information for the specified I2C. |
| 461 | return HAL_ERROR; |
461 | * @retval HAL status |
| 462 | } |
462 | */ |
| 463 | 463 | HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) |
|
| 464 | /* Check the parameters */ |
464 | { |
| 465 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
465 | uint32_t freqrange; |
| 466 | assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); |
466 | uint32_t pclk1; |
| 467 | assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); |
467 | |
| 468 | assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); |
468 | /* Check the I2C handle allocation */ |
| 469 | assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); |
469 | if (hi2c == NULL) |
| 470 | assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); |
470 | { |
| 471 | assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); |
471 | return HAL_ERROR; |
| 472 | assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); |
472 | } |
| 473 | assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); |
473 | |
| 474 | 474 | /* Check the parameters */ |
|
| 475 | if (hi2c->State == HAL_I2C_STATE_RESET) |
475 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
| 476 | { |
476 | assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed)); |
| 477 | /* Allocate lock resource and initialize it */ |
477 | assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle)); |
| 478 | hi2c->Lock = HAL_UNLOCKED; |
478 | assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); |
| 479 | 479 | assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); |
|
| 480 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
480 | assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); |
| 481 | /* Init the I2C Callback settings */ |
481 | assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); |
| 482 | hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ |
482 | assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); |
| 483 | hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ |
483 | assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); |
| 484 | hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ |
484 | |
| 485 | hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ |
485 | if (hi2c->State == HAL_I2C_STATE_RESET) |
| 486 | hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ |
486 | { |
| 487 | hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ |
487 | /* Allocate lock resource and initialize it */ |
| 488 | hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ |
488 | hi2c->Lock = HAL_UNLOCKED; |
| 489 | hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ |
489 | |
| 490 | hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ |
490 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 491 | hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ |
491 | /* Init the I2C Callback settings */ |
| 492 | 492 | hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ |
|
| 493 | if (hi2c->MspInitCallback == NULL) |
493 | hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ |
| 494 | { |
494 | hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ |
| 495 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
495 | hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ |
| 496 | } |
496 | hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ |
| 497 | 497 | hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ |
|
| 498 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
498 | hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ |
| 499 | hi2c->MspInitCallback(hi2c); |
499 | hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ |
| 500 | #else |
500 | hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ |
| 501 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
501 | hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ |
| 502 | HAL_I2C_MspInit(hi2c); |
502 | |
| 503 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
503 | if (hi2c->MspInitCallback == NULL) |
| 504 | } |
504 | { |
| 505 | 505 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
|
| 506 | hi2c->State = HAL_I2C_STATE_BUSY; |
506 | } |
| 507 | 507 | ||
| 508 | /* Disable the selected I2C peripheral */ |
508 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
| 509 | __HAL_I2C_DISABLE(hi2c); |
509 | hi2c->MspInitCallback(hi2c); |
| 510 | 510 | #else |
|
| 511 | /*Reset I2C*/ |
511 | /* Init the low level hardware : GPIO, CLOCK, NVIC */ |
| 512 | hi2c->Instance->CR1 |= I2C_CR1_SWRST; |
512 | HAL_I2C_MspInit(hi2c); |
| 513 | hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; |
513 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 514 | 514 | } |
|
| 515 | /* Get PCLK1 frequency */ |
515 | |
| 516 | pclk1 = HAL_RCC_GetPCLK1Freq(); |
516 | hi2c->State = HAL_I2C_STATE_BUSY; |
| 517 | 517 | ||
| 518 | /* Check the minimum allowed PCLK1 frequency */ |
518 | /* Disable the selected I2C peripheral */ |
| 519 | if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) |
519 | __HAL_I2C_DISABLE(hi2c); |
| 520 | { |
520 | |
| 521 | return HAL_ERROR; |
521 | /*Reset I2C*/ |
| 522 | } |
522 | hi2c->Instance->CR1 |= I2C_CR1_SWRST; |
| 523 | 523 | hi2c->Instance->CR1 &= ~I2C_CR1_SWRST; |
|
| 524 | /* Calculate frequency range */ |
524 | |
| 525 | freqrange = I2C_FREQRANGE(pclk1); |
525 | /* Get PCLK1 frequency */ |
| 526 | 526 | pclk1 = HAL_RCC_GetPCLK1Freq(); |
|
| 527 | /*---------------------------- I2Cx CR2 Configuration ----------------------*/ |
527 | |
| 528 | /* Configure I2Cx: Frequency range */ |
528 | /* Check the minimum allowed PCLK1 frequency */ |
| 529 | MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); |
529 | if (I2C_MIN_PCLK_FREQ(pclk1, hi2c->Init.ClockSpeed) == 1U) |
| 530 | 530 | { |
|
| 531 | /*---------------------------- I2Cx TRISE Configuration --------------------*/ |
531 | return HAL_ERROR; |
| 532 | /* Configure I2Cx: Rise Time */ |
532 | } |
| 533 | MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); |
533 | |
| 534 | 534 | /* Calculate frequency range */ |
|
| 535 | /*---------------------------- I2Cx CCR Configuration ----------------------*/ |
535 | freqrange = I2C_FREQRANGE(pclk1); |
| 536 | /* Configure I2Cx: Speed */ |
536 | |
| 537 | MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); |
537 | /*---------------------------- I2Cx CR2 Configuration ----------------------*/ |
| 538 | 538 | /* Configure I2Cx: Frequency range */ |
|
| 539 | /*---------------------------- I2Cx CR1 Configuration ----------------------*/ |
539 | MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange); |
| 540 | /* Configure I2Cx: Generalcall and NoStretch mode */ |
540 | |
| 541 | MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); |
541 | /*---------------------------- I2Cx TRISE Configuration --------------------*/ |
| 542 | 542 | /* Configure I2Cx: Rise Time */ |
|
| 543 | /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ |
543 | MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed)); |
| 544 | /* Configure I2Cx: Own Address1 and addressing mode */ |
544 | |
| 545 | MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); |
545 | /*---------------------------- I2Cx CCR Configuration ----------------------*/ |
| 546 | 546 | /* Configure I2Cx: Speed */ |
|
| 547 | /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ |
547 | MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle)); |
| 548 | /* Configure I2Cx: Dual mode and Own Address2 */ |
548 | |
| 549 | MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); |
549 | /*---------------------------- I2Cx CR1 Configuration ----------------------*/ |
| 550 | 550 | /* Configure I2Cx: Generalcall and NoStretch mode */ |
|
| 551 | /* Enable the selected I2C peripheral */ |
551 | MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode)); |
| 552 | __HAL_I2C_ENABLE(hi2c); |
552 | |
| 553 | 553 | /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ |
|
| 554 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
554 | /* Configure I2Cx: Own Address1 and addressing mode */ |
| 555 | hi2c->State = HAL_I2C_STATE_READY; |
555 | MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1)); |
| 556 | hi2c->PreviousState = I2C_STATE_NONE; |
556 | |
| 557 | hi2c->Mode = HAL_I2C_MODE_NONE; |
557 | /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ |
| 558 | 558 | /* Configure I2Cx: Dual mode and Own Address2 */ |
|
| 559 | return HAL_OK; |
559 | MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2)); |
| 560 | } |
560 | |
| 561 | 561 | /* Enable the selected I2C peripheral */ |
|
| 562 | /** |
562 | __HAL_I2C_ENABLE(hi2c); |
| 563 | * @brief DeInitialize the I2C peripheral. |
563 | |
| 564 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
564 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 565 | * the configuration information for the specified I2C. |
565 | hi2c->State = HAL_I2C_STATE_READY; |
| 566 | * @retval HAL status |
566 | hi2c->PreviousState = I2C_STATE_NONE; |
| 567 | */ |
567 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 568 | HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) |
568 | |
| 569 | { |
569 | return HAL_OK; |
| 570 | /* Check the I2C handle allocation */ |
570 | } |
| 571 | if (hi2c == NULL) |
571 | |
| 572 | { |
572 | /** |
| 573 | return HAL_ERROR; |
573 | * @brief DeInitialize the I2C peripheral. |
| 574 | } |
574 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 575 | 575 | * the configuration information for the specified I2C. |
|
| 576 | /* Check the parameters */ |
576 | * @retval HAL status |
| 577 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
577 | */ |
| 578 | 578 | HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) |
|
| 579 | hi2c->State = HAL_I2C_STATE_BUSY; |
579 | { |
| 580 | 580 | /* Check the I2C handle allocation */ |
|
| 581 | /* Disable the I2C Peripheral Clock */ |
581 | if (hi2c == NULL) |
| 582 | __HAL_I2C_DISABLE(hi2c); |
582 | { |
| 583 | 583 | return HAL_ERROR; |
|
| 584 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
584 | } |
| 585 | if (hi2c->MspDeInitCallback == NULL) |
585 | |
| 586 | { |
586 | /* Check the parameters */ |
| 587 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
587 | assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); |
| 588 | } |
588 | |
| 589 | 589 | hi2c->State = HAL_I2C_STATE_BUSY; |
|
| 590 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
590 | |
| 591 | hi2c->MspDeInitCallback(hi2c); |
591 | /* Disable the I2C Peripheral Clock */ |
| 592 | #else |
592 | __HAL_I2C_DISABLE(hi2c); |
| 593 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
593 | |
| 594 | HAL_I2C_MspDeInit(hi2c); |
594 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 595 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
595 | if (hi2c->MspDeInitCallback == NULL) |
| 596 | 596 | { |
|
| 597 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
597 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
| 598 | hi2c->State = HAL_I2C_STATE_RESET; |
598 | } |
| 599 | hi2c->PreviousState = I2C_STATE_NONE; |
599 | |
| 600 | hi2c->Mode = HAL_I2C_MODE_NONE; |
600 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| 601 | 601 | hi2c->MspDeInitCallback(hi2c); |
|
| 602 | /* Release Lock */ |
602 | #else |
| 603 | __HAL_UNLOCK(hi2c); |
603 | /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ |
| 604 | 604 | HAL_I2C_MspDeInit(hi2c); |
|
| 605 | return HAL_OK; |
605 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 606 | } |
606 | |
| 607 | 607 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
|
| 608 | /** |
608 | hi2c->State = HAL_I2C_STATE_RESET; |
| 609 | * @brief Initialize the I2C MSP. |
609 | hi2c->PreviousState = I2C_STATE_NONE; |
| 610 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
610 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 611 | * the configuration information for the specified I2C. |
611 | |
| 612 | * @retval None |
612 | /* Release Lock */ |
| 613 | */ |
613 | __HAL_UNLOCK(hi2c); |
| 614 | __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) |
614 | |
| 615 | { |
615 | return HAL_OK; |
| 616 | /* Prevent unused argument(s) compilation warning */ |
616 | } |
| 617 | UNUSED(hi2c); |
617 | |
| 618 | 618 | /** |
|
| 619 | /* NOTE : This function should not be modified, when the callback is needed, |
619 | * @brief Initialize the I2C MSP. |
| 620 | the HAL_I2C_MspInit could be implemented in the user file |
620 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 621 | */ |
621 | * the configuration information for the specified I2C. |
| 622 | } |
622 | * @retval None |
| 623 | 623 | */ |
|
| 624 | /** |
624 | __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) |
| 625 | * @brief DeInitialize the I2C MSP. |
625 | { |
| 626 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
626 | /* Prevent unused argument(s) compilation warning */ |
| 627 | * the configuration information for the specified I2C. |
627 | UNUSED(hi2c); |
| 628 | * @retval None |
628 | |
| 629 | */ |
629 | /* NOTE : This function should not be modified, when the callback is needed, |
| 630 | __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) |
630 | the HAL_I2C_MspInit could be implemented in the user file |
| 631 | { |
631 | */ |
| 632 | /* Prevent unused argument(s) compilation warning */ |
632 | } |
| 633 | UNUSED(hi2c); |
633 | |
| 634 | 634 | /** |
|
| 635 | /* NOTE : This function should not be modified, when the callback is needed, |
635 | * @brief DeInitialize the I2C MSP. |
| 636 | the HAL_I2C_MspDeInit could be implemented in the user file |
636 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 637 | */ |
637 | * the configuration information for the specified I2C. |
| 638 | } |
638 | * @retval None |
| 639 | 639 | */ |
|
| 640 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
640 | __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) |
| 641 | /** |
641 | { |
| 642 | * @brief Register a User I2C Callback |
642 | /* Prevent unused argument(s) compilation warning */ |
| 643 | * To be used instead of the weak predefined callback |
643 | UNUSED(hi2c); |
| 644 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
644 | |
| 645 | * the configuration information for the specified I2C. |
645 | /* NOTE : This function should not be modified, when the callback is needed, |
| 646 | * @param CallbackID ID of the callback to be registered |
646 | the HAL_I2C_MspDeInit could be implemented in the user file |
| 647 | * This parameter can be one of the following values: |
647 | */ |
| 648 | * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID |
648 | } |
| 649 | * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID |
649 | |
| 650 | * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID |
650 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 651 | * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID |
651 | /** |
| 652 | * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID |
652 | * @brief Register a User I2C Callback |
| 653 | * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID |
653 | * To be used instead of the weak predefined callback |
| 654 | * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID |
654 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 655 | * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID |
655 | * the configuration information for the specified I2C. |
| 656 | * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID |
656 | * @param CallbackID ID of the callback to be registered |
| 657 | * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID |
657 | * This parameter can be one of the following values: |
| 658 | * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID |
658 | * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID |
| 659 | * @param pCallback pointer to the Callback function |
659 | * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID |
| 660 | * @retval HAL status |
660 | * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID |
| 661 | */ |
661 | * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID |
| 662 | HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) |
662 | * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID |
| 663 | { |
663 | * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID |
| 664 | HAL_StatusTypeDef status = HAL_OK; |
664 | * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID |
| 665 | 665 | * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID |
|
| 666 | if (pCallback == NULL) |
666 | * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID |
| 667 | { |
667 | * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID |
| 668 | /* Update the error code */ |
668 | * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID |
| 669 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
669 | * @param pCallback pointer to the Callback function |
| 670 | 670 | * @retval HAL status |
|
| 671 | return HAL_ERROR; |
671 | */ |
| 672 | } |
672 | HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback) |
| 673 | /* Process locked */ |
673 | { |
| 674 | __HAL_LOCK(hi2c); |
674 | HAL_StatusTypeDef status = HAL_OK; |
| 675 | 675 | ||
| 676 | if (HAL_I2C_STATE_READY == hi2c->State) |
676 | if (pCallback == NULL) |
| 677 | { |
677 | { |
| 678 | switch (CallbackID) |
678 | /* Update the error code */ |
| 679 | { |
679 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
| 680 | case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : |
680 | |
| 681 | hi2c->MasterTxCpltCallback = pCallback; |
681 | return HAL_ERROR; |
| 682 | break; |
682 | } |
| 683 | 683 | /* Process locked */ |
|
| 684 | case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : |
684 | __HAL_LOCK(hi2c); |
| 685 | hi2c->MasterRxCpltCallback = pCallback; |
685 | |
| 686 | break; |
686 | if (HAL_I2C_STATE_READY == hi2c->State) |
| 687 | 687 | { |
|
| 688 | case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : |
688 | switch (CallbackID) |
| 689 | hi2c->SlaveTxCpltCallback = pCallback; |
689 | { |
| 690 | break; |
690 | case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : |
| 691 | 691 | hi2c->MasterTxCpltCallback = pCallback; |
|
| 692 | case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : |
692 | break; |
| 693 | hi2c->SlaveRxCpltCallback = pCallback; |
693 | |
| 694 | break; |
694 | case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : |
| 695 | 695 | hi2c->MasterRxCpltCallback = pCallback; |
|
| 696 | case HAL_I2C_LISTEN_COMPLETE_CB_ID : |
696 | break; |
| 697 | hi2c->ListenCpltCallback = pCallback; |
697 | |
| 698 | break; |
698 | case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : |
| 699 | 699 | hi2c->SlaveTxCpltCallback = pCallback; |
|
| 700 | case HAL_I2C_MEM_TX_COMPLETE_CB_ID : |
700 | break; |
| 701 | hi2c->MemTxCpltCallback = pCallback; |
701 | |
| 702 | break; |
702 | case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : |
| 703 | 703 | hi2c->SlaveRxCpltCallback = pCallback; |
|
| 704 | case HAL_I2C_MEM_RX_COMPLETE_CB_ID : |
704 | break; |
| 705 | hi2c->MemRxCpltCallback = pCallback; |
705 | |
| 706 | break; |
706 | case HAL_I2C_LISTEN_COMPLETE_CB_ID : |
| 707 | 707 | hi2c->ListenCpltCallback = pCallback; |
|
| 708 | case HAL_I2C_ERROR_CB_ID : |
708 | break; |
| 709 | hi2c->ErrorCallback = pCallback; |
709 | |
| 710 | break; |
710 | case HAL_I2C_MEM_TX_COMPLETE_CB_ID : |
| 711 | 711 | hi2c->MemTxCpltCallback = pCallback; |
|
| 712 | case HAL_I2C_ABORT_CB_ID : |
712 | break; |
| 713 | hi2c->AbortCpltCallback = pCallback; |
713 | |
| 714 | break; |
714 | case HAL_I2C_MEM_RX_COMPLETE_CB_ID : |
| 715 | 715 | hi2c->MemRxCpltCallback = pCallback; |
|
| 716 | case HAL_I2C_MSPINIT_CB_ID : |
716 | break; |
| 717 | hi2c->MspInitCallback = pCallback; |
717 | |
| 718 | break; |
718 | case HAL_I2C_ERROR_CB_ID : |
| 719 | 719 | hi2c->ErrorCallback = pCallback; |
|
| 720 | case HAL_I2C_MSPDEINIT_CB_ID : |
720 | break; |
| 721 | hi2c->MspDeInitCallback = pCallback; |
721 | |
| 722 | break; |
722 | case HAL_I2C_ABORT_CB_ID : |
| 723 | 723 | hi2c->AbortCpltCallback = pCallback; |
|
| 724 | default : |
724 | break; |
| 725 | /* Update the error code */ |
725 | |
| 726 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
726 | case HAL_I2C_MSPINIT_CB_ID : |
| 727 | 727 | hi2c->MspInitCallback = pCallback; |
|
| 728 | /* Return error status */ |
728 | break; |
| 729 | status = HAL_ERROR; |
729 | |
| 730 | break; |
730 | case HAL_I2C_MSPDEINIT_CB_ID : |
| 731 | } |
731 | hi2c->MspDeInitCallback = pCallback; |
| 732 | } |
732 | break; |
| 733 | else if (HAL_I2C_STATE_RESET == hi2c->State) |
733 | |
| 734 | { |
734 | default : |
| 735 | switch (CallbackID) |
735 | /* Update the error code */ |
| 736 | { |
736 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
| 737 | case HAL_I2C_MSPINIT_CB_ID : |
737 | |
| 738 | hi2c->MspInitCallback = pCallback; |
738 | /* Return error status */ |
| 739 | break; |
739 | status = HAL_ERROR; |
| 740 | 740 | break; |
|
| 741 | case HAL_I2C_MSPDEINIT_CB_ID : |
741 | } |
| 742 | hi2c->MspDeInitCallback = pCallback; |
742 | } |
| 743 | break; |
743 | else if (HAL_I2C_STATE_RESET == hi2c->State) |
| 744 | 744 | { |
|
| 745 | default : |
745 | switch (CallbackID) |
| 746 | /* Update the error code */ |
746 | { |
| 747 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
747 | case HAL_I2C_MSPINIT_CB_ID : |
| 748 | 748 | hi2c->MspInitCallback = pCallback; |
|
| 749 | /* Return error status */ |
749 | break; |
| 750 | status = HAL_ERROR; |
750 | |
| 751 | break; |
751 | case HAL_I2C_MSPDEINIT_CB_ID : |
| 752 | } |
752 | hi2c->MspDeInitCallback = pCallback; |
| 753 | } |
753 | break; |
| 754 | else |
754 | |
| 755 | { |
755 | default : |
| 756 | /* Update the error code */ |
756 | /* Update the error code */ |
| 757 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
757 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
| 758 | 758 | ||
| 759 | /* Return error status */ |
759 | /* Return error status */ |
| 760 | status = HAL_ERROR; |
760 | status = HAL_ERROR; |
| 761 | } |
761 | break; |
| 762 | 762 | } |
|
| 763 | /* Release Lock */ |
763 | } |
| 764 | __HAL_UNLOCK(hi2c); |
764 | else |
| 765 | return status; |
765 | { |
| 766 | } |
766 | /* Update the error code */ |
| 767 | 767 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
|
| 768 | /** |
768 | |
| 769 | * @brief Unregister an I2C Callback |
769 | /* Return error status */ |
| 770 | * I2C callback is redirected to the weak predefined callback |
770 | status = HAL_ERROR; |
| 771 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
771 | } |
| 772 | * the configuration information for the specified I2C. |
772 | |
| 773 | * @param CallbackID ID of the callback to be unregistered |
773 | /* Release Lock */ |
| 774 | * This parameter can be one of the following values: |
774 | __HAL_UNLOCK(hi2c); |
| 775 | * This parameter can be one of the following values: |
775 | return status; |
| 776 | * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID |
776 | } |
| 777 | * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID |
777 | |
| 778 | * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID |
778 | /** |
| 779 | * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID |
779 | * @brief Unregister an I2C Callback |
| 780 | * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID |
780 | * I2C callback is redirected to the weak predefined callback |
| 781 | * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID |
781 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 782 | * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID |
782 | * the configuration information for the specified I2C. |
| 783 | * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID |
783 | * @param CallbackID ID of the callback to be unregistered |
| 784 | * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID |
784 | * This parameter can be one of the following values: |
| 785 | * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID |
785 | * This parameter can be one of the following values: |
| 786 | * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID |
786 | * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID |
| 787 | * @retval HAL status |
787 | * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID |
| 788 | */ |
788 | * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID |
| 789 | HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) |
789 | * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID |
| 790 | { |
790 | * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID |
| 791 | HAL_StatusTypeDef status = HAL_OK; |
791 | * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID |
| 792 | 792 | * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID |
|
| 793 | /* Process locked */ |
793 | * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID |
| 794 | __HAL_LOCK(hi2c); |
794 | * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID |
| 795 | 795 | * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID |
|
| 796 | if (HAL_I2C_STATE_READY == hi2c->State) |
796 | * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID |
| 797 | { |
797 | * @retval HAL status |
| 798 | switch (CallbackID) |
798 | */ |
| 799 | { |
799 | HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) |
| 800 | case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : |
800 | { |
| 801 | hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ |
801 | HAL_StatusTypeDef status = HAL_OK; |
| 802 | break; |
802 | |
| 803 | 803 | /* Process locked */ |
|
| 804 | case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : |
804 | __HAL_LOCK(hi2c); |
| 805 | hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ |
805 | |
| 806 | break; |
806 | if (HAL_I2C_STATE_READY == hi2c->State) |
| 807 | 807 | { |
|
| 808 | case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : |
808 | switch (CallbackID) |
| 809 | hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ |
809 | { |
| 810 | break; |
810 | case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : |
| 811 | 811 | hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ |
|
| 812 | case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : |
812 | break; |
| 813 | hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ |
813 | |
| 814 | break; |
814 | case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : |
| 815 | 815 | hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ |
|
| 816 | case HAL_I2C_LISTEN_COMPLETE_CB_ID : |
816 | break; |
| 817 | hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ |
817 | |
| 818 | break; |
818 | case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : |
| 819 | 819 | hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ |
|
| 820 | case HAL_I2C_MEM_TX_COMPLETE_CB_ID : |
820 | break; |
| 821 | hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ |
821 | |
| 822 | break; |
822 | case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : |
| 823 | 823 | hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ |
|
| 824 | case HAL_I2C_MEM_RX_COMPLETE_CB_ID : |
824 | break; |
| 825 | hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ |
825 | |
| 826 | break; |
826 | case HAL_I2C_LISTEN_COMPLETE_CB_ID : |
| 827 | 827 | hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ |
|
| 828 | case HAL_I2C_ERROR_CB_ID : |
828 | break; |
| 829 | hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ |
829 | |
| 830 | break; |
830 | case HAL_I2C_MEM_TX_COMPLETE_CB_ID : |
| 831 | 831 | hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ |
|
| 832 | case HAL_I2C_ABORT_CB_ID : |
832 | break; |
| 833 | hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ |
833 | |
| 834 | break; |
834 | case HAL_I2C_MEM_RX_COMPLETE_CB_ID : |
| 835 | 835 | hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ |
|
| 836 | case HAL_I2C_MSPINIT_CB_ID : |
836 | break; |
| 837 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
837 | |
| 838 | break; |
838 | case HAL_I2C_ERROR_CB_ID : |
| 839 | 839 | hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ |
|
| 840 | case HAL_I2C_MSPDEINIT_CB_ID : |
840 | break; |
| 841 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
841 | |
| 842 | break; |
842 | case HAL_I2C_ABORT_CB_ID : |
| 843 | 843 | hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ |
|
| 844 | default : |
844 | break; |
| 845 | /* Update the error code */ |
845 | |
| 846 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
846 | case HAL_I2C_MSPINIT_CB_ID : |
| 847 | 847 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
|
| 848 | /* Return error status */ |
848 | break; |
| 849 | status = HAL_ERROR; |
849 | |
| 850 | break; |
850 | case HAL_I2C_MSPDEINIT_CB_ID : |
| 851 | } |
851 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
| 852 | } |
852 | break; |
| 853 | else if (HAL_I2C_STATE_RESET == hi2c->State) |
853 | |
| 854 | { |
854 | default : |
| 855 | switch (CallbackID) |
855 | /* Update the error code */ |
| 856 | { |
856 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
| 857 | case HAL_I2C_MSPINIT_CB_ID : |
857 | |
| 858 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
858 | /* Return error status */ |
| 859 | break; |
859 | status = HAL_ERROR; |
| 860 | 860 | break; |
|
| 861 | case HAL_I2C_MSPDEINIT_CB_ID : |
861 | } |
| 862 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
862 | } |
| 863 | break; |
863 | else if (HAL_I2C_STATE_RESET == hi2c->State) |
| 864 | 864 | { |
|
| 865 | default : |
865 | switch (CallbackID) |
| 866 | /* Update the error code */ |
866 | { |
| 867 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
867 | case HAL_I2C_MSPINIT_CB_ID : |
| 868 | 868 | hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ |
|
| 869 | /* Return error status */ |
869 | break; |
| 870 | status = HAL_ERROR; |
870 | |
| 871 | break; |
871 | case HAL_I2C_MSPDEINIT_CB_ID : |
| 872 | } |
872 | hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ |
| 873 | } |
873 | break; |
| 874 | else |
874 | |
| 875 | { |
875 | default : |
| 876 | /* Update the error code */ |
876 | /* Update the error code */ |
| 877 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
877 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
| 878 | 878 | ||
| 879 | /* Return error status */ |
879 | /* Return error status */ |
| 880 | status = HAL_ERROR; |
880 | status = HAL_ERROR; |
| 881 | } |
881 | break; |
| 882 | 882 | } |
|
| 883 | /* Release Lock */ |
883 | } |
| 884 | __HAL_UNLOCK(hi2c); |
884 | else |
| 885 | return status; |
885 | { |
| 886 | } |
886 | /* Update the error code */ |
| 887 | 887 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
|
| 888 | /** |
888 | |
| 889 | * @brief Register the Slave Address Match I2C Callback |
889 | /* Return error status */ |
| 890 | * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback |
890 | status = HAL_ERROR; |
| 891 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
891 | } |
| 892 | * the configuration information for the specified I2C. |
892 | |
| 893 | * @param pCallback pointer to the Address Match Callback function |
893 | /* Release Lock */ |
| 894 | * @retval HAL status |
894 | __HAL_UNLOCK(hi2c); |
| 895 | */ |
895 | return status; |
| 896 | HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) |
896 | } |
| 897 | { |
897 | |
| 898 | HAL_StatusTypeDef status = HAL_OK; |
898 | /** |
| 899 | 899 | * @brief Register the Slave Address Match I2C Callback |
|
| 900 | if (pCallback == NULL) |
900 | * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback |
| 901 | { |
901 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 902 | /* Update the error code */ |
902 | * the configuration information for the specified I2C. |
| 903 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
903 | * @param pCallback pointer to the Address Match Callback function |
| 904 | 904 | * @retval HAL status |
|
| 905 | return HAL_ERROR; |
905 | */ |
| 906 | } |
906 | HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) |
| 907 | /* Process locked */ |
907 | { |
| 908 | __HAL_LOCK(hi2c); |
908 | HAL_StatusTypeDef status = HAL_OK; |
| 909 | 909 | ||
| 910 | if (HAL_I2C_STATE_READY == hi2c->State) |
910 | if (pCallback == NULL) |
| 911 | { |
911 | { |
| 912 | hi2c->AddrCallback = pCallback; |
912 | /* Update the error code */ |
| 913 | } |
913 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
| 914 | else |
914 | |
| 915 | { |
915 | return HAL_ERROR; |
| 916 | /* Update the error code */ |
916 | } |
| 917 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
917 | /* Process locked */ |
| 918 | 918 | __HAL_LOCK(hi2c); |
|
| 919 | /* Return error status */ |
919 | |
| 920 | status = HAL_ERROR; |
920 | if (HAL_I2C_STATE_READY == hi2c->State) |
| 921 | } |
921 | { |
| 922 | 922 | hi2c->AddrCallback = pCallback; |
|
| 923 | /* Release Lock */ |
923 | } |
| 924 | __HAL_UNLOCK(hi2c); |
924 | else |
| 925 | return status; |
925 | { |
| 926 | } |
926 | /* Update the error code */ |
| 927 | 927 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
|
| 928 | /** |
928 | |
| 929 | * @brief UnRegister the Slave Address Match I2C Callback |
929 | /* Return error status */ |
| 930 | * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback |
930 | status = HAL_ERROR; |
| 931 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
931 | } |
| 932 | * the configuration information for the specified I2C. |
932 | |
| 933 | * @retval HAL status |
933 | /* Release Lock */ |
| 934 | */ |
934 | __HAL_UNLOCK(hi2c); |
| 935 | HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) |
935 | return status; |
| 936 | { |
936 | } |
| 937 | HAL_StatusTypeDef status = HAL_OK; |
937 | |
| 938 | 938 | /** |
|
| 939 | /* Process locked */ |
939 | * @brief UnRegister the Slave Address Match I2C Callback |
| 940 | __HAL_LOCK(hi2c); |
940 | * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback |
| 941 | 941 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 942 | if (HAL_I2C_STATE_READY == hi2c->State) |
942 | * the configuration information for the specified I2C. |
| 943 | { |
943 | * @retval HAL status |
| 944 | hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ |
944 | */ |
| 945 | } |
945 | HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) |
| 946 | else |
946 | { |
| 947 | { |
947 | HAL_StatusTypeDef status = HAL_OK; |
| 948 | /* Update the error code */ |
948 | |
| 949 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
949 | /* Process locked */ |
| 950 | 950 | __HAL_LOCK(hi2c); |
|
| 951 | /* Return error status */ |
951 | |
| 952 | status = HAL_ERROR; |
952 | if (HAL_I2C_STATE_READY == hi2c->State) |
| 953 | } |
953 | { |
| 954 | 954 | hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ |
|
| 955 | /* Release Lock */ |
955 | } |
| 956 | __HAL_UNLOCK(hi2c); |
956 | else |
| 957 | return status; |
957 | { |
| 958 | } |
958 | /* Update the error code */ |
| 959 | 959 | hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; |
|
| 960 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
960 | |
| 961 | 961 | /* Return error status */ |
|
| 962 | /** |
962 | status = HAL_ERROR; |
| 963 | * @} |
963 | } |
| 964 | */ |
964 | |
| 965 | 965 | /* Release Lock */ |
|
| 966 | /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions |
966 | __HAL_UNLOCK(hi2c); |
| 967 | * @brief Data transfers functions |
967 | return status; |
| 968 | * |
968 | } |
| 969 | @verbatim |
969 | |
| 970 | =============================================================================== |
970 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 971 | ##### IO operation functions ##### |
971 | |
| 972 | =============================================================================== |
972 | /** |
| 973 | [..] |
973 | * @brief I2C data register flush process. |
| 974 | This subsection provides a set of functions allowing to manage the I2C data |
974 | * @param hi2c I2C handle. |
| 975 | transfers. |
975 | * @retval None |
| 976 | 976 | */ |
|
| 977 | (#) There are two modes of transfer: |
977 | static void I2C_Flush_DR(I2C_HandleTypeDef *hi2c) |
| 978 | (++) Blocking mode : The communication is performed in the polling mode. |
978 | { |
| 979 | The status of all data processing is returned by the same function |
979 | /* Write a dummy data in DR to clear TXE flag */ |
| 980 | after finishing transfer. |
980 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) != RESET) |
| 981 | (++) No-Blocking mode : The communication is performed using Interrupts |
981 | { |
| 982 | or DMA. These functions return the status of the transfer startup. |
982 | hi2c->Instance->DR = 0x00U; |
| 983 | The end of the data processing will be indicated through the |
983 | } |
| 984 | dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when |
984 | } |
| 985 | using DMA mode. |
985 | |
| 986 | 986 | /** |
|
| 987 | (#) Blocking mode functions are : |
987 | * @} |
| 988 | (++) HAL_I2C_Master_Transmit() |
988 | */ |
| 989 | (++) HAL_I2C_Master_Receive() |
989 | |
| 990 | (++) HAL_I2C_Slave_Transmit() |
990 | /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions |
| 991 | (++) HAL_I2C_Slave_Receive() |
991 | * @brief Data transfers functions |
| 992 | (++) HAL_I2C_Mem_Write() |
992 | * |
| 993 | (++) HAL_I2C_Mem_Read() |
993 | @verbatim |
| 994 | (++) HAL_I2C_IsDeviceReady() |
994 | =============================================================================== |
| 995 | 995 | ##### IO operation functions ##### |
|
| 996 | (#) No-Blocking mode functions with Interrupt are : |
996 | =============================================================================== |
| 997 | (++) HAL_I2C_Master_Transmit_IT() |
997 | [..] |
| 998 | (++) HAL_I2C_Master_Receive_IT() |
998 | This subsection provides a set of functions allowing to manage the I2C data |
| 999 | (++) HAL_I2C_Slave_Transmit_IT() |
999 | transfers. |
| 1000 | (++) HAL_I2C_Slave_Receive_IT() |
1000 | |
| 1001 | (++) HAL_I2C_Mem_Write_IT() |
1001 | (#) There are two modes of transfer: |
| 1002 | (++) HAL_I2C_Mem_Read_IT() |
1002 | (++) Blocking mode : The communication is performed in the polling mode. |
| 1003 | (++) HAL_I2C_Master_Seq_Transmit_IT() |
1003 | The status of all data processing is returned by the same function |
| 1004 | (++) HAL_I2C_Master_Seq_Receive_IT() |
1004 | after finishing transfer. |
| 1005 | (++) HAL_I2C_Slave_Seq_Transmit_IT() |
1005 | (++) No-Blocking mode : The communication is performed using Interrupts |
| 1006 | (++) HAL_I2C_Slave_Seq_Receive_IT() |
1006 | or DMA. These functions return the status of the transfer startup. |
| 1007 | (++) HAL_I2C_EnableListen_IT() |
1007 | The end of the data processing will be indicated through the |
| 1008 | (++) HAL_I2C_DisableListen_IT() |
1008 | dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when |
| 1009 | (++) HAL_I2C_Master_Abort_IT() |
1009 | using DMA mode. |
| 1010 | 1010 | ||
| 1011 | (#) No-Blocking mode functions with DMA are : |
1011 | (#) Blocking mode functions are : |
| 1012 | (++) HAL_I2C_Master_Transmit_DMA() |
1012 | (++) HAL_I2C_Master_Transmit() |
| 1013 | (++) HAL_I2C_Master_Receive_DMA() |
1013 | (++) HAL_I2C_Master_Receive() |
| 1014 | (++) HAL_I2C_Slave_Transmit_DMA() |
1014 | (++) HAL_I2C_Slave_Transmit() |
| 1015 | (++) HAL_I2C_Slave_Receive_DMA() |
1015 | (++) HAL_I2C_Slave_Receive() |
| 1016 | (++) HAL_I2C_Mem_Write_DMA() |
1016 | (++) HAL_I2C_Mem_Write() |
| 1017 | (++) HAL_I2C_Mem_Read_DMA() |
1017 | (++) HAL_I2C_Mem_Read() |
| 1018 | (++) HAL_I2C_Master_Seq_Transmit_DMA() |
1018 | (++) HAL_I2C_IsDeviceReady() |
| 1019 | (++) HAL_I2C_Master_Seq_Receive_DMA() |
1019 | |
| 1020 | (++) HAL_I2C_Slave_Seq_Transmit_DMA() |
1020 | (#) No-Blocking mode functions with Interrupt are : |
| 1021 | (++) HAL_I2C_Slave_Seq_Receive_DMA() |
1021 | (++) HAL_I2C_Master_Transmit_IT() |
| 1022 | 1022 | (++) HAL_I2C_Master_Receive_IT() |
|
| 1023 | (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: |
1023 | (++) HAL_I2C_Slave_Transmit_IT() |
| 1024 | (++) HAL_I2C_MasterTxCpltCallback() |
1024 | (++) HAL_I2C_Slave_Receive_IT() |
| 1025 | (++) HAL_I2C_MasterRxCpltCallback() |
1025 | (++) HAL_I2C_Mem_Write_IT() |
| 1026 | (++) HAL_I2C_SlaveTxCpltCallback() |
1026 | (++) HAL_I2C_Mem_Read_IT() |
| 1027 | (++) HAL_I2C_SlaveRxCpltCallback() |
1027 | (++) HAL_I2C_Master_Seq_Transmit_IT() |
| 1028 | (++) HAL_I2C_MemTxCpltCallback() |
1028 | (++) HAL_I2C_Master_Seq_Receive_IT() |
| 1029 | (++) HAL_I2C_MemRxCpltCallback() |
1029 | (++) HAL_I2C_Slave_Seq_Transmit_IT() |
| 1030 | (++) HAL_I2C_AddrCallback() |
1030 | (++) HAL_I2C_Slave_Seq_Receive_IT() |
| 1031 | (++) HAL_I2C_ListenCpltCallback() |
1031 | (++) HAL_I2C_EnableListen_IT() |
| 1032 | (++) HAL_I2C_ErrorCallback() |
1032 | (++) HAL_I2C_DisableListen_IT() |
| 1033 | (++) HAL_I2C_AbortCpltCallback() |
1033 | (++) HAL_I2C_Master_Abort_IT() |
| 1034 | 1034 | ||
| 1035 | @endverbatim |
1035 | (#) No-Blocking mode functions with DMA are : |
| 1036 | * @{ |
1036 | (++) HAL_I2C_Master_Transmit_DMA() |
| 1037 | */ |
1037 | (++) HAL_I2C_Master_Receive_DMA() |
| 1038 | 1038 | (++) HAL_I2C_Slave_Transmit_DMA() |
|
| 1039 | /** |
1039 | (++) HAL_I2C_Slave_Receive_DMA() |
| 1040 | * @brief Transmits in master mode an amount of data in blocking mode. |
1040 | (++) HAL_I2C_Mem_Write_DMA() |
| 1041 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
1041 | (++) HAL_I2C_Mem_Read_DMA() |
| 1042 | * the configuration information for the specified I2C. |
1042 | (++) HAL_I2C_Master_Seq_Transmit_DMA() |
| 1043 | * @param DevAddress Target device address: The device 7 bits address value |
1043 | (++) HAL_I2C_Master_Seq_Receive_DMA() |
| 1044 | * in datasheet must be shifted to the left before calling the interface |
1044 | (++) HAL_I2C_Slave_Seq_Transmit_DMA() |
| 1045 | * @param pData Pointer to data buffer |
1045 | (++) HAL_I2C_Slave_Seq_Receive_DMA() |
| 1046 | * @param Size Amount of data to be sent |
1046 | |
| 1047 | * @param Timeout Timeout duration |
1047 | (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: |
| 1048 | * @retval HAL status |
1048 | (++) HAL_I2C_MasterTxCpltCallback() |
| 1049 | */ |
1049 | (++) HAL_I2C_MasterRxCpltCallback() |
| 1050 | HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
1050 | (++) HAL_I2C_SlaveTxCpltCallback() |
| 1051 | { |
1051 | (++) HAL_I2C_SlaveRxCpltCallback() |
| 1052 | /* Init tickstart for timeout management*/ |
1052 | (++) HAL_I2C_MemTxCpltCallback() |
| 1053 | uint32_t tickstart = HAL_GetTick(); |
1053 | (++) HAL_I2C_MemRxCpltCallback() |
| 1054 | 1054 | (++) HAL_I2C_AddrCallback() |
|
| 1055 | if (hi2c->State == HAL_I2C_STATE_READY) |
1055 | (++) HAL_I2C_ListenCpltCallback() |
| 1056 | { |
1056 | (++) HAL_I2C_ErrorCallback() |
| 1057 | /* Wait until BUSY flag is reset */ |
1057 | (++) HAL_I2C_AbortCpltCallback() |
| 1058 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
1058 | |
| 1059 | { |
1059 | @endverbatim |
| 1060 | return HAL_BUSY; |
1060 | * @{ |
| 1061 | } |
1061 | */ |
| 1062 | 1062 | ||
| 1063 | /* Process Locked */ |
1063 | /** |
| 1064 | __HAL_LOCK(hi2c); |
1064 | * @brief Transmits in master mode an amount of data in blocking mode. |
| 1065 | 1065 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 1066 | /* Check if the I2C is already enabled */ |
1066 | * the configuration information for the specified I2C. |
| 1067 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
1067 | * @param DevAddress Target device address: The device 7 bits address value |
| 1068 | { |
1068 | * in datasheet must be shifted to the left before calling the interface |
| 1069 | /* Enable I2C peripheral */ |
1069 | * @param pData Pointer to data buffer |
| 1070 | __HAL_I2C_ENABLE(hi2c); |
1070 | * @param Size Amount of data to be sent |
| 1071 | } |
1071 | * @param Timeout Timeout duration |
| 1072 | 1072 | * @retval HAL status |
|
| 1073 | /* Disable Pos */ |
1073 | */ |
| 1074 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
1074 | HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
| 1075 | 1075 | { |
|
| 1076 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
1076 | /* Init tickstart for timeout management*/ |
| 1077 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
1077 | uint32_t tickstart = HAL_GetTick(); |
| 1078 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
1078 | |
| 1079 | 1079 | if (hi2c->State == HAL_I2C_STATE_READY) |
|
| 1080 | /* Prepare transfer parameters */ |
1080 | { |
| 1081 | hi2c->pBuffPtr = pData; |
1081 | /* Wait until BUSY flag is reset */ |
| 1082 | hi2c->XferCount = Size; |
1082 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
| 1083 | hi2c->XferSize = hi2c->XferCount; |
1083 | { |
| 1084 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
1084 | return HAL_BUSY; |
| 1085 | 1085 | } |
|
| 1086 | /* Send Slave Address */ |
1086 | |
| 1087 | if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) |
1087 | /* Process Locked */ |
| 1088 | { |
1088 | __HAL_LOCK(hi2c); |
| 1089 | return HAL_ERROR; |
1089 | |
| 1090 | } |
1090 | /* Check if the I2C is already enabled */ |
| 1091 | 1091 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
|
| 1092 | /* Clear ADDR flag */ |
1092 | { |
| 1093 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
1093 | /* Enable I2C peripheral */ |
| 1094 | 1094 | __HAL_I2C_ENABLE(hi2c); |
|
| 1095 | while (hi2c->XferSize > 0U) |
1095 | } |
| 1096 | { |
1096 | |
| 1097 | /* Wait until TXE flag is set */ |
1097 | /* Disable Pos */ |
| 1098 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
1098 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 1099 | { |
1099 | |
| 1100 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
1100 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
| 1101 | { |
1101 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
| 1102 | /* Generate Stop */ |
1102 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 1103 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
1103 | |
| 1104 | } |
1104 | /* Prepare transfer parameters */ |
| 1105 | return HAL_ERROR; |
1105 | hi2c->pBuffPtr = pData; |
| 1106 | } |
1106 | hi2c->XferCount = Size; |
| 1107 | 1107 | hi2c->XferSize = hi2c->XferCount; |
|
| 1108 | /* Write data to DR */ |
1108 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 1109 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
1109 | |
| 1110 | 1110 | /* Send Slave Address */ |
|
| 1111 | /* Increment Buffer pointer */ |
1111 | if (I2C_MasterRequestWrite(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) |
| 1112 | hi2c->pBuffPtr++; |
1112 | { |
| 1113 | 1113 | return HAL_ERROR; |
|
| 1114 | /* Update counter */ |
1114 | } |
| 1115 | hi2c->XferCount--; |
1115 | |
| 1116 | hi2c->XferSize--; |
1116 | /* Clear ADDR flag */ |
| 1117 | 1117 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
|
| 1118 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
1118 | |
| 1119 | { |
1119 | while (hi2c->XferSize > 0U) |
| 1120 | /* Write data to DR */ |
1120 | { |
| 1121 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
1121 | /* Wait until TXE flag is set */ |
| 1122 | 1122 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
|
| 1123 | /* Increment Buffer pointer */ |
1123 | { |
| 1124 | hi2c->pBuffPtr++; |
1124 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
| 1125 | 1125 | { |
|
| 1126 | /* Update counter */ |
1126 | /* Generate Stop */ |
| 1127 | hi2c->XferCount--; |
1127 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 1128 | hi2c->XferSize--; |
1128 | } |
| 1129 | } |
1129 | return HAL_ERROR; |
| 1130 | 1130 | } |
|
| 1131 | /* Wait until BTF flag is set */ |
1131 | |
| 1132 | if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
1132 | /* Write data to DR */ |
| 1133 | { |
1133 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
| 1134 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
1134 | |
| 1135 | { |
1135 | /* Increment Buffer pointer */ |
| 1136 | /* Generate Stop */ |
1136 | hi2c->pBuffPtr++; |
| 1137 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
1137 | |
| 1138 | } |
1138 | /* Update counter */ |
| 1139 | return HAL_ERROR; |
1139 | hi2c->XferCount--; |
| 1140 | } |
1140 | hi2c->XferSize--; |
| 1141 | } |
1141 | |
| 1142 | 1142 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
|
| 1143 | /* Generate Stop */ |
1143 | { |
| 1144 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
1144 | /* Write data to DR */ |
| 1145 | 1145 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
|
| 1146 | hi2c->State = HAL_I2C_STATE_READY; |
1146 | |
| 1147 | hi2c->Mode = HAL_I2C_MODE_NONE; |
1147 | /* Increment Buffer pointer */ |
| 1148 | 1148 | hi2c->pBuffPtr++; |
|
| 1149 | /* Process Unlocked */ |
1149 | |
| 1150 | __HAL_UNLOCK(hi2c); |
1150 | /* Update counter */ |
| 1151 | 1151 | hi2c->XferCount--; |
|
| 1152 | return HAL_OK; |
1152 | hi2c->XferSize--; |
| 1153 | } |
1153 | } |
| 1154 | else |
1154 | |
| 1155 | { |
1155 | /* Wait until BTF flag is set */ |
| 1156 | return HAL_BUSY; |
1156 | if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
| 1157 | } |
1157 | { |
| 1158 | } |
1158 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
| 1159 | 1159 | { |
|
| 1160 | /** |
1160 | /* Generate Stop */ |
| 1161 | * @brief Receives in master mode an amount of data in blocking mode. |
1161 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 1162 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
1162 | } |
| 1163 | * the configuration information for the specified I2C. |
1163 | return HAL_ERROR; |
| 1164 | * @param DevAddress Target device address: The device 7 bits address value |
1164 | } |
| 1165 | * in datasheet must be shifted to the left before calling the interface |
1165 | } |
| 1166 | * @param pData Pointer to data buffer |
1166 | |
| 1167 | * @param Size Amount of data to be sent |
1167 | /* Generate Stop */ |
| 1168 | * @param Timeout Timeout duration |
1168 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 1169 | * @retval HAL status |
1169 | |
| 1170 | */ |
1170 | hi2c->State = HAL_I2C_STATE_READY; |
| 1171 | HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
1171 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 1172 | { |
1172 | |
| 1173 | __IO uint32_t count = 0U; |
1173 | /* Process Unlocked */ |
| 1174 | 1174 | __HAL_UNLOCK(hi2c); |
|
| 1175 | /* Init tickstart for timeout management*/ |
1175 | |
| 1176 | uint32_t tickstart = HAL_GetTick(); |
1176 | return HAL_OK; |
| 1177 | 1177 | } |
|
| 1178 | if (hi2c->State == HAL_I2C_STATE_READY) |
1178 | else |
| 1179 | { |
1179 | { |
| 1180 | /* Wait until BUSY flag is reset */ |
1180 | return HAL_BUSY; |
| 1181 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
1181 | } |
| 1182 | { |
1182 | } |
| 1183 | return HAL_BUSY; |
1183 | |
| 1184 | } |
1184 | /** |
| 1185 | 1185 | * @brief Receives in master mode an amount of data in blocking mode. |
|
| 1186 | /* Process Locked */ |
1186 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 1187 | __HAL_LOCK(hi2c); |
1187 | * the configuration information for the specified I2C. |
| 1188 | 1188 | * @param DevAddress Target device address: The device 7 bits address value |
|
| 1189 | /* Check if the I2C is already enabled */ |
1189 | * in datasheet must be shifted to the left before calling the interface |
| 1190 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
1190 | * @param pData Pointer to data buffer |
| 1191 | { |
1191 | * @param Size Amount of data to be sent |
| 1192 | /* Enable I2C peripheral */ |
1192 | * @param Timeout Timeout duration |
| 1193 | __HAL_I2C_ENABLE(hi2c); |
1193 | * @retval HAL status |
| 1194 | } |
1194 | */ |
| 1195 | 1195 | HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
|
| 1196 | /* Disable Pos */ |
1196 | { |
| 1197 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
1197 | __IO uint32_t count = 0U; |
| 1198 | 1198 | ||
| 1199 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
1199 | /* Init tickstart for timeout management*/ |
| 1200 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
1200 | uint32_t tickstart = HAL_GetTick(); |
| 1201 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
1201 | |
| 1202 | 1202 | if (hi2c->State == HAL_I2C_STATE_READY) |
|
| 1203 | /* Prepare transfer parameters */ |
1203 | { |
| 1204 | hi2c->pBuffPtr = pData; |
1204 | /* Wait until BUSY flag is reset */ |
| 1205 | hi2c->XferCount = Size; |
1205 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
| 1206 | hi2c->XferSize = hi2c->XferCount; |
1206 | { |
| 1207 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
1207 | return HAL_BUSY; |
| 1208 | 1208 | } |
|
| 1209 | /* Send Slave Address */ |
1209 | |
| 1210 | if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) |
1210 | /* Process Locked */ |
| 1211 | { |
1211 | __HAL_LOCK(hi2c); |
| 1212 | return HAL_ERROR; |
1212 | |
| 1213 | } |
1213 | /* Check if the I2C is already enabled */ |
| 1214 | 1214 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
|
| 1215 | if (hi2c->XferSize == 0U) |
1215 | { |
| 1216 | { |
1216 | /* Enable I2C peripheral */ |
| 1217 | /* Clear ADDR flag */ |
1217 | __HAL_I2C_ENABLE(hi2c); |
| 1218 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
1218 | } |
| 1219 | 1219 | ||
| 1220 | /* Generate Stop */ |
1220 | /* Disable Pos */ |
| 1221 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
1221 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 1222 | } |
1222 | |
| 1223 | else if (hi2c->XferSize == 1U) |
1223 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
| 1224 | { |
1224 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
| 1225 | /* Disable Acknowledge */ |
1225 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 1226 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1226 | |
| 1227 | 1227 | /* Prepare transfer parameters */ |
|
| 1228 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
1228 | hi2c->pBuffPtr = pData; |
| 1229 | software sequence must complete before the current byte end of transfer */ |
1229 | hi2c->XferCount = Size; |
| 1230 | __disable_irq(); |
1230 | hi2c->XferSize = hi2c->XferCount; |
| 1231 | 1231 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
|
| 1232 | /* Clear ADDR flag */ |
1232 | |
| 1233 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
1233 | /* Send Slave Address */ |
| 1234 | 1234 | if (I2C_MasterRequestRead(hi2c, DevAddress, Timeout, tickstart) != HAL_OK) |
|
| 1235 | /* Generate Stop */ |
1235 | { |
| 1236 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
1236 | return HAL_ERROR; |
| 1237 | 1237 | } |
|
| 1238 | /* Re-enable IRQs */ |
1238 | |
| 1239 | __enable_irq(); |
1239 | if (hi2c->XferSize == 0U) |
| 1240 | } |
1240 | { |
| 1241 | else if (hi2c->XferSize == 2U) |
1241 | /* Clear ADDR flag */ |
| 1242 | { |
1242 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 1243 | /* Enable Pos */ |
1243 | |
| 1244 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
1244 | /* Generate Stop */ |
| 1245 | 1245 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
|
| 1246 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
1246 | } |
| 1247 | software sequence must complete before the current byte end of transfer */ |
1247 | else if (hi2c->XferSize == 1U) |
| 1248 | __disable_irq(); |
1248 | { |
| 1249 | 1249 | /* Disable Acknowledge */ |
|
| 1250 | /* Clear ADDR flag */ |
1250 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1251 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
1251 | |
| 1252 | 1252 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
|
| 1253 | /* Disable Acknowledge */ |
1253 | software sequence must complete before the current byte end of transfer */ |
| 1254 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1254 | __disable_irq(); |
| 1255 | 1255 | ||
| 1256 | /* Re-enable IRQs */ |
1256 | /* Clear ADDR flag */ |
| 1257 | __enable_irq(); |
1257 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 1258 | } |
1258 | |
| 1259 | else |
1259 | /* Generate Stop */ |
| 1260 | { |
1260 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 1261 | /* Enable Acknowledge */ |
1261 | |
| 1262 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1262 | /* Re-enable IRQs */ |
| 1263 | 1263 | __enable_irq(); |
|
| 1264 | /* Clear ADDR flag */ |
1264 | } |
| 1265 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
1265 | else if (hi2c->XferSize == 2U) |
| 1266 | } |
1266 | { |
| 1267 | 1267 | /* Enable Pos */ |
|
| 1268 | while (hi2c->XferSize > 0U) |
1268 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 1269 | { |
1269 | |
| 1270 | if (hi2c->XferSize <= 3U) |
1270 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
| 1271 | { |
1271 | software sequence must complete before the current byte end of transfer */ |
| 1272 | /* One byte */ |
1272 | __disable_irq(); |
| 1273 | if (hi2c->XferSize == 1U) |
1273 | |
| 1274 | { |
1274 | /* Clear ADDR flag */ |
| 1275 | /* Wait until RXNE flag is set */ |
1275 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 1276 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
1276 | |
| 1277 | { |
1277 | /* Disable Acknowledge */ |
| 1278 | return HAL_ERROR; |
1278 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1279 | } |
1279 | |
| 1280 | 1280 | /* Re-enable IRQs */ |
|
| 1281 | /* Read data from DR */ |
1281 | __enable_irq(); |
| 1282 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
1282 | } |
| 1283 | 1283 | else |
|
| 1284 | /* Increment Buffer pointer */ |
1284 | { |
| 1285 | hi2c->pBuffPtr++; |
1285 | /* Enable Acknowledge */ |
| 1286 | 1286 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
|
| 1287 | /* Update counter */ |
1287 | |
| 1288 | hi2c->XferSize--; |
1288 | /* Clear ADDR flag */ |
| 1289 | hi2c->XferCount--; |
1289 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 1290 | } |
1290 | } |
| 1291 | /* Two bytes */ |
1291 | |
| 1292 | else if (hi2c->XferSize == 2U) |
1292 | while (hi2c->XferSize > 0U) |
| 1293 | { |
1293 | { |
| 1294 | /* Wait until BTF flag is set */ |
1294 | if (hi2c->XferSize <= 3U) |
| 1295 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
1295 | { |
| 1296 | { |
1296 | /* One byte */ |
| 1297 | return HAL_ERROR; |
1297 | if (hi2c->XferSize == 1U) |
| 1298 | } |
1298 | { |
| 1299 | 1299 | /* Wait until RXNE flag is set */ |
|
| 1300 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
1300 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
| 1301 | software sequence must complete before the current byte end of transfer */ |
1301 | { |
| 1302 | __disable_irq(); |
1302 | return HAL_ERROR; |
| 1303 | 1303 | } |
|
| 1304 | /* Generate Stop */ |
1304 | |
| 1305 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
1305 | /* Read data from DR */ |
| 1306 | 1306 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
|
| 1307 | /* Read data from DR */ |
1307 | |
| 1308 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
1308 | /* Increment Buffer pointer */ |
| 1309 | 1309 | hi2c->pBuffPtr++; |
|
| 1310 | /* Increment Buffer pointer */ |
1310 | |
| 1311 | hi2c->pBuffPtr++; |
1311 | /* Update counter */ |
| 1312 | 1312 | hi2c->XferSize--; |
|
| 1313 | /* Update counter */ |
1313 | hi2c->XferCount--; |
| 1314 | hi2c->XferSize--; |
1314 | } |
| 1315 | hi2c->XferCount--; |
1315 | /* Two bytes */ |
| 1316 | 1316 | else if (hi2c->XferSize == 2U) |
|
| 1317 | /* Re-enable IRQs */ |
1317 | { |
| 1318 | __enable_irq(); |
1318 | /* Wait until BTF flag is set */ |
| 1319 | 1319 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
|
| 1320 | /* Read data from DR */ |
1320 | { |
| 1321 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
1321 | return HAL_ERROR; |
| 1322 | 1322 | } |
|
| 1323 | /* Increment Buffer pointer */ |
1323 | |
| 1324 | hi2c->pBuffPtr++; |
1324 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
| 1325 | 1325 | software sequence must complete before the current byte end of transfer */ |
|
| 1326 | /* Update counter */ |
1326 | __disable_irq(); |
| 1327 | hi2c->XferSize--; |
1327 | |
| 1328 | hi2c->XferCount--; |
1328 | /* Generate Stop */ |
| 1329 | } |
1329 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 1330 | /* 3 Last bytes */ |
1330 | |
| 1331 | else |
1331 | /* Read data from DR */ |
| 1332 | { |
1332 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 1333 | /* Wait until BTF flag is set */ |
1333 | |
| 1334 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
1334 | /* Increment Buffer pointer */ |
| 1335 | { |
1335 | hi2c->pBuffPtr++; |
| 1336 | return HAL_ERROR; |
1336 | |
| 1337 | } |
1337 | /* Update counter */ |
| 1338 | 1338 | hi2c->XferSize--; |
|
| 1339 | /* Disable Acknowledge */ |
1339 | hi2c->XferCount--; |
| 1340 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1340 | |
| 1341 | 1341 | /* Re-enable IRQs */ |
|
| 1342 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
1342 | __enable_irq(); |
| 1343 | software sequence must complete before the current byte end of transfer */ |
1343 | |
| 1344 | __disable_irq(); |
1344 | /* Read data from DR */ |
| 1345 | 1345 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
|
| 1346 | /* Read data from DR */ |
1346 | |
| 1347 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
1347 | /* Increment Buffer pointer */ |
| 1348 | 1348 | hi2c->pBuffPtr++; |
|
| 1349 | /* Increment Buffer pointer */ |
1349 | |
| 1350 | hi2c->pBuffPtr++; |
1350 | /* Update counter */ |
| 1351 | 1351 | hi2c->XferSize--; |
|
| 1352 | /* Update counter */ |
1352 | hi2c->XferCount--; |
| 1353 | hi2c->XferSize--; |
1353 | } |
| 1354 | hi2c->XferCount--; |
1354 | /* 3 Last bytes */ |
| 1355 | 1355 | else |
|
| 1356 | /* Wait until BTF flag is set */ |
1356 | { |
| 1357 | count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); |
1357 | /* Wait until BTF flag is set */ |
| 1358 | do |
1358 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
| 1359 | { |
1359 | { |
| 1360 | count--; |
1360 | return HAL_ERROR; |
| 1361 | if (count == 0U) |
1361 | } |
| 1362 | { |
1362 | |
| 1363 | hi2c->PreviousState = I2C_STATE_NONE; |
1363 | /* Disable Acknowledge */ |
| 1364 | hi2c->State = HAL_I2C_STATE_READY; |
1364 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1365 | hi2c->Mode = HAL_I2C_MODE_NONE; |
1365 | |
| 1366 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
1366 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
| 1367 | 1367 | software sequence must complete before the current byte end of transfer */ |
|
| 1368 | /* Re-enable IRQs */ |
1368 | __disable_irq(); |
| 1369 | __enable_irq(); |
1369 | |
| 1370 | 1370 | /* Read data from DR */ |
|
| 1371 | /* Process Unlocked */ |
1371 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 1372 | __HAL_UNLOCK(hi2c); |
1372 | |
| 1373 | 1373 | /* Increment Buffer pointer */ |
|
| 1374 | return HAL_ERROR; |
1374 | hi2c->pBuffPtr++; |
| 1375 | } |
1375 | |
| 1376 | } |
1376 | /* Update counter */ |
| 1377 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); |
1377 | hi2c->XferSize--; |
| 1378 | 1378 | hi2c->XferCount--; |
|
| 1379 | /* Generate Stop */ |
1379 | |
| 1380 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
1380 | /* Wait until BTF flag is set */ |
| 1381 | 1381 | count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); |
|
| 1382 | /* Read data from DR */ |
1382 | do |
| 1383 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
1383 | { |
| 1384 | 1384 | count--; |
|
| 1385 | /* Increment Buffer pointer */ |
1385 | if (count == 0U) |
| 1386 | hi2c->pBuffPtr++; |
1386 | { |
| 1387 | 1387 | hi2c->PreviousState = I2C_STATE_NONE; |
|
| 1388 | /* Update counter */ |
1388 | hi2c->State = HAL_I2C_STATE_READY; |
| 1389 | hi2c->XferSize--; |
1389 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 1390 | hi2c->XferCount--; |
1390 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 1391 | 1391 | ||
| 1392 | /* Re-enable IRQs */ |
1392 | /* Re-enable IRQs */ |
| 1393 | __enable_irq(); |
1393 | __enable_irq(); |
| 1394 | 1394 | ||
| 1395 | /* Read data from DR */ |
1395 | /* Process Unlocked */ |
| 1396 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
1396 | __HAL_UNLOCK(hi2c); |
| 1397 | 1397 | ||
| 1398 | /* Increment Buffer pointer */ |
1398 | return HAL_ERROR; |
| 1399 | hi2c->pBuffPtr++; |
1399 | } |
| 1400 | 1400 | } |
|
| 1401 | /* Update counter */ |
1401 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); |
| 1402 | hi2c->XferSize--; |
1402 | |
| 1403 | hi2c->XferCount--; |
1403 | /* Generate Stop */ |
| 1404 | } |
1404 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 1405 | } |
1405 | |
| 1406 | else |
1406 | /* Read data from DR */ |
| 1407 | { |
1407 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 1408 | /* Wait until RXNE flag is set */ |
1408 | |
| 1409 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
1409 | /* Increment Buffer pointer */ |
| 1410 | { |
1410 | hi2c->pBuffPtr++; |
| 1411 | return HAL_ERROR; |
1411 | |
| 1412 | } |
1412 | /* Update counter */ |
| 1413 | 1413 | hi2c->XferSize--; |
|
| 1414 | /* Read data from DR */ |
1414 | hi2c->XferCount--; |
| 1415 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
1415 | |
| 1416 | 1416 | /* Re-enable IRQs */ |
|
| 1417 | /* Increment Buffer pointer */ |
1417 | __enable_irq(); |
| 1418 | hi2c->pBuffPtr++; |
1418 | |
| 1419 | 1419 | /* Read data from DR */ |
|
| 1420 | /* Update counter */ |
1420 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 1421 | hi2c->XferSize--; |
1421 | |
| 1422 | hi2c->XferCount--; |
1422 | /* Increment Buffer pointer */ |
| 1423 | 1423 | hi2c->pBuffPtr++; |
|
| 1424 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
1424 | |
| 1425 | { |
1425 | /* Update counter */ |
| 1426 | /* Read data from DR */ |
1426 | hi2c->XferSize--; |
| 1427 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
1427 | hi2c->XferCount--; |
| 1428 | 1428 | } |
|
| 1429 | /* Increment Buffer pointer */ |
1429 | } |
| 1430 | hi2c->pBuffPtr++; |
1430 | else |
| 1431 | 1431 | { |
|
| 1432 | /* Update counter */ |
1432 | /* Wait until RXNE flag is set */ |
| 1433 | hi2c->XferSize--; |
1433 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
| 1434 | hi2c->XferCount--; |
1434 | { |
| 1435 | } |
1435 | return HAL_ERROR; |
| 1436 | } |
1436 | } |
| 1437 | } |
1437 | |
| 1438 | 1438 | /* Read data from DR */ |
|
| 1439 | hi2c->State = HAL_I2C_STATE_READY; |
1439 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 1440 | hi2c->Mode = HAL_I2C_MODE_NONE; |
1440 | |
| 1441 | 1441 | /* Increment Buffer pointer */ |
|
| 1442 | /* Process Unlocked */ |
1442 | hi2c->pBuffPtr++; |
| 1443 | __HAL_UNLOCK(hi2c); |
1443 | |
| 1444 | 1444 | /* Update counter */ |
|
| 1445 | return HAL_OK; |
1445 | hi2c->XferSize--; |
| 1446 | } |
1446 | hi2c->XferCount--; |
| 1447 | else |
1447 | |
| 1448 | { |
1448 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
| 1449 | return HAL_BUSY; |
1449 | { |
| 1450 | } |
1450 | |
| 1451 | } |
1451 | if (hi2c->XferSize == 3U) |
| 1452 | 1452 | { |
|
| 1453 | /** |
1453 | /* Disable Acknowledge */ |
| 1454 | * @brief Transmits in slave mode an amount of data in blocking mode. |
1454 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1455 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
1455 | } |
| 1456 | * the configuration information for the specified I2C. |
1456 | |
| 1457 | * @param pData Pointer to data buffer |
1457 | /* Read data from DR */ |
| 1458 | * @param Size Amount of data to be sent |
1458 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 1459 | * @param Timeout Timeout duration |
1459 | |
| 1460 | * @retval HAL status |
1460 | /* Increment Buffer pointer */ |
| 1461 | */ |
1461 | hi2c->pBuffPtr++; |
| 1462 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
1462 | |
| 1463 | { |
1463 | /* Update counter */ |
| 1464 | /* Init tickstart for timeout management*/ |
1464 | hi2c->XferSize--; |
| 1465 | uint32_t tickstart = HAL_GetTick(); |
1465 | hi2c->XferCount--; |
| 1466 | 1466 | } |
|
| 1467 | if (hi2c->State == HAL_I2C_STATE_READY) |
1467 | } |
| 1468 | { |
1468 | } |
| 1469 | if ((pData == NULL) || (Size == 0U)) |
1469 | |
| 1470 | { |
1470 | hi2c->State = HAL_I2C_STATE_READY; |
| 1471 | return HAL_ERROR; |
1471 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 1472 | } |
1472 | |
| 1473 | 1473 | /* Process Unlocked */ |
|
| 1474 | /* Process Locked */ |
1474 | __HAL_UNLOCK(hi2c); |
| 1475 | __HAL_LOCK(hi2c); |
1475 | |
| 1476 | 1476 | return HAL_OK; |
|
| 1477 | /* Check if the I2C is already enabled */ |
1477 | } |
| 1478 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
1478 | else |
| 1479 | { |
1479 | { |
| 1480 | /* Enable I2C peripheral */ |
1480 | return HAL_BUSY; |
| 1481 | __HAL_I2C_ENABLE(hi2c); |
1481 | } |
| 1482 | } |
1482 | } |
| 1483 | 1483 | ||
| 1484 | /* Disable Pos */ |
1484 | /** |
| 1485 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
1485 | * @brief Transmits in slave mode an amount of data in blocking mode. |
| 1486 | 1486 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 1487 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
1487 | * the configuration information for the specified I2C. |
| 1488 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
1488 | * @param pData Pointer to data buffer |
| 1489 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
1489 | * @param Size Amount of data to be sent |
| 1490 | 1490 | * @param Timeout Timeout duration |
|
| 1491 | /* Prepare transfer parameters */ |
1491 | * @retval HAL status |
| 1492 | hi2c->pBuffPtr = pData; |
1492 | */ |
| 1493 | hi2c->XferCount = Size; |
1493 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
| 1494 | hi2c->XferSize = hi2c->XferCount; |
1494 | { |
| 1495 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
1495 | /* Init tickstart for timeout management*/ |
| 1496 | 1496 | uint32_t tickstart = HAL_GetTick(); |
|
| 1497 | /* Enable Address Acknowledge */ |
1497 | |
| 1498 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1498 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 1499 | 1499 | { |
|
| 1500 | /* Wait until ADDR flag is set */ |
1500 | if ((pData == NULL) || (Size == 0U)) |
| 1501 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
1501 | { |
| 1502 | { |
1502 | return HAL_ERROR; |
| 1503 | return HAL_ERROR; |
1503 | } |
| 1504 | } |
1504 | |
| 1505 | 1505 | /* Process Locked */ |
|
| 1506 | /* Clear ADDR flag */ |
1506 | __HAL_LOCK(hi2c); |
| 1507 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
1507 | |
| 1508 | 1508 | /* Check if the I2C is already enabled */ |
|
| 1509 | /* If 10bit addressing mode is selected */ |
1509 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 1510 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) |
1510 | { |
| 1511 | { |
1511 | /* Enable I2C peripheral */ |
| 1512 | /* Wait until ADDR flag is set */ |
1512 | __HAL_I2C_ENABLE(hi2c); |
| 1513 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
1513 | } |
| 1514 | { |
1514 | |
| 1515 | return HAL_ERROR; |
1515 | /* Disable Pos */ |
| 1516 | } |
1516 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 1517 | 1517 | ||
| 1518 | /* Clear ADDR flag */ |
1518 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
| 1519 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
1519 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
| 1520 | } |
1520 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 1521 | 1521 | ||
| 1522 | while (hi2c->XferSize > 0U) |
1522 | /* Prepare transfer parameters */ |
| 1523 | { |
1523 | hi2c->pBuffPtr = pData; |
| 1524 | /* Wait until TXE flag is set */ |
1524 | hi2c->XferCount = Size; |
| 1525 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
1525 | hi2c->XferSize = hi2c->XferCount; |
| 1526 | { |
1526 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 1527 | /* Disable Address Acknowledge */ |
1527 | |
| 1528 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1528 | /* Enable Address Acknowledge */ |
| 1529 | 1529 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
|
| 1530 | return HAL_ERROR; |
1530 | |
| 1531 | } |
1531 | /* Wait until ADDR flag is set */ |
| 1532 | 1532 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
|
| 1533 | /* Write data to DR */ |
1533 | { |
| 1534 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
1534 | return HAL_ERROR; |
| 1535 | 1535 | } |
|
| 1536 | /* Increment Buffer pointer */ |
1536 | |
| 1537 | hi2c->pBuffPtr++; |
1537 | /* Clear ADDR flag */ |
| 1538 | 1538 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
|
| 1539 | /* Update counter */ |
1539 | |
| 1540 | hi2c->XferCount--; |
1540 | /* If 10bit addressing mode is selected */ |
| 1541 | hi2c->XferSize--; |
1541 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) |
| 1542 | 1542 | { |
|
| 1543 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
1543 | /* Wait until ADDR flag is set */ |
| 1544 | { |
1544 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
| 1545 | /* Write data to DR */ |
1545 | { |
| 1546 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
1546 | return HAL_ERROR; |
| 1547 | 1547 | } |
|
| 1548 | /* Increment Buffer pointer */ |
1548 | |
| 1549 | hi2c->pBuffPtr++; |
1549 | /* Clear ADDR flag */ |
| 1550 | 1550 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
|
| 1551 | /* Update counter */ |
1551 | } |
| 1552 | hi2c->XferCount--; |
1552 | |
| 1553 | hi2c->XferSize--; |
1553 | while (hi2c->XferSize > 0U) |
| 1554 | } |
1554 | { |
| 1555 | } |
1555 | /* Wait until TXE flag is set */ |
| 1556 | 1556 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
|
| 1557 | /* Wait until AF flag is set */ |
1557 | { |
| 1558 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) |
1558 | /* Disable Address Acknowledge */ |
| 1559 | { |
1559 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1560 | return HAL_ERROR; |
1560 | |
| 1561 | } |
1561 | return HAL_ERROR; |
| 1562 | 1562 | } |
|
| 1563 | /* Clear AF flag */ |
1563 | |
| 1564 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
1564 | /* Write data to DR */ |
| 1565 | 1565 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
|
| 1566 | /* Disable Address Acknowledge */ |
1566 | |
| 1567 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1567 | /* Increment Buffer pointer */ |
| 1568 | 1568 | hi2c->pBuffPtr++; |
|
| 1569 | hi2c->State = HAL_I2C_STATE_READY; |
1569 | |
| 1570 | hi2c->Mode = HAL_I2C_MODE_NONE; |
1570 | /* Update counter */ |
| 1571 | 1571 | hi2c->XferCount--; |
|
| 1572 | /* Process Unlocked */ |
1572 | hi2c->XferSize--; |
| 1573 | __HAL_UNLOCK(hi2c); |
1573 | |
| 1574 | 1574 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
|
| 1575 | return HAL_OK; |
1575 | { |
| 1576 | } |
1576 | /* Write data to DR */ |
| 1577 | else |
1577 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
| 1578 | { |
1578 | |
| 1579 | return HAL_BUSY; |
1579 | /* Increment Buffer pointer */ |
| 1580 | } |
1580 | hi2c->pBuffPtr++; |
| 1581 | } |
1581 | |
| 1582 | 1582 | /* Update counter */ |
|
| 1583 | /** |
1583 | hi2c->XferCount--; |
| 1584 | * @brief Receive in slave mode an amount of data in blocking mode |
1584 | hi2c->XferSize--; |
| 1585 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
1585 | } |
| 1586 | * the configuration information for the specified I2C. |
1586 | } |
| 1587 | * @param pData Pointer to data buffer |
1587 | |
| 1588 | * @param Size Amount of data to be sent |
1588 | /* Wait until AF flag is set */ |
| 1589 | * @param Timeout Timeout duration |
1589 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK) |
| 1590 | * @retval HAL status |
1590 | { |
| 1591 | */ |
1591 | return HAL_ERROR; |
| 1592 | HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
1592 | } |
| 1593 | { |
1593 | |
| 1594 | /* Init tickstart for timeout management*/ |
1594 | /* Clear AF flag */ |
| 1595 | uint32_t tickstart = HAL_GetTick(); |
1595 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
| 1596 | 1596 | ||
| 1597 | if (hi2c->State == HAL_I2C_STATE_READY) |
1597 | /* Disable Address Acknowledge */ |
| 1598 | { |
1598 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1599 | if ((pData == NULL) || (Size == (uint16_t)0)) |
1599 | |
| 1600 | { |
1600 | hi2c->State = HAL_I2C_STATE_READY; |
| 1601 | return HAL_ERROR; |
1601 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 1602 | } |
1602 | |
| 1603 | 1603 | /* Process Unlocked */ |
|
| 1604 | /* Process Locked */ |
1604 | __HAL_UNLOCK(hi2c); |
| 1605 | __HAL_LOCK(hi2c); |
1605 | |
| 1606 | 1606 | return HAL_OK; |
|
| 1607 | /* Check if the I2C is already enabled */ |
1607 | } |
| 1608 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
1608 | else |
| 1609 | { |
1609 | { |
| 1610 | /* Enable I2C peripheral */ |
1610 | return HAL_BUSY; |
| 1611 | __HAL_I2C_ENABLE(hi2c); |
1611 | } |
| 1612 | } |
1612 | } |
| 1613 | 1613 | ||
| 1614 | /* Disable Pos */ |
1614 | /** |
| 1615 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
1615 | * @brief Receive in slave mode an amount of data in blocking mode |
| 1616 | 1616 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 1617 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
1617 | * the configuration information for the specified I2C. |
| 1618 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
1618 | * @param pData Pointer to data buffer |
| 1619 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
1619 | * @param Size Amount of data to be sent |
| 1620 | 1620 | * @param Timeout Timeout duration |
|
| 1621 | /* Prepare transfer parameters */ |
1621 | * @retval HAL status |
| 1622 | hi2c->pBuffPtr = pData; |
1622 | */ |
| 1623 | hi2c->XferCount = Size; |
1623 | HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
| 1624 | hi2c->XferSize = hi2c->XferCount; |
1624 | { |
| 1625 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
1625 | /* Init tickstart for timeout management*/ |
| 1626 | 1626 | uint32_t tickstart = HAL_GetTick(); |
|
| 1627 | /* Enable Address Acknowledge */ |
1627 | |
| 1628 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1628 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 1629 | 1629 | { |
|
| 1630 | /* Wait until ADDR flag is set */ |
1630 | if ((pData == NULL) || (Size == (uint16_t)0)) |
| 1631 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
1631 | { |
| 1632 | { |
1632 | return HAL_ERROR; |
| 1633 | return HAL_ERROR; |
1633 | } |
| 1634 | } |
1634 | |
| 1635 | 1635 | /* Process Locked */ |
|
| 1636 | /* Clear ADDR flag */ |
1636 | __HAL_LOCK(hi2c); |
| 1637 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
1637 | |
| 1638 | 1638 | /* Check if the I2C is already enabled */ |
|
| 1639 | while (hi2c->XferSize > 0U) |
1639 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 1640 | { |
1640 | { |
| 1641 | /* Wait until RXNE flag is set */ |
1641 | /* Enable I2C peripheral */ |
| 1642 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
1642 | __HAL_I2C_ENABLE(hi2c); |
| 1643 | { |
1643 | } |
| 1644 | /* Disable Address Acknowledge */ |
1644 | |
| 1645 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1645 | /* Disable Pos */ |
| 1646 | 1646 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
|
| 1647 | return HAL_ERROR; |
1647 | |
| 1648 | } |
1648 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
| 1649 | 1649 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
|
| 1650 | /* Read data from DR */ |
1650 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 1651 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
1651 | |
| 1652 | 1652 | /* Prepare transfer parameters */ |
|
| 1653 | /* Increment Buffer pointer */ |
1653 | hi2c->pBuffPtr = pData; |
| 1654 | hi2c->pBuffPtr++; |
1654 | hi2c->XferCount = Size; |
| 1655 | 1655 | hi2c->XferSize = hi2c->XferCount; |
|
| 1656 | /* Update counter */ |
1656 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 1657 | hi2c->XferSize--; |
1657 | |
| 1658 | hi2c->XferCount--; |
1658 | /* Enable Address Acknowledge */ |
| 1659 | 1659 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
|
| 1660 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
1660 | |
| 1661 | { |
1661 | /* Wait until ADDR flag is set */ |
| 1662 | /* Read data from DR */ |
1662 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) |
| 1663 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
1663 | { |
| 1664 | 1664 | return HAL_ERROR; |
|
| 1665 | /* Increment Buffer pointer */ |
1665 | } |
| 1666 | hi2c->pBuffPtr++; |
1666 | |
| 1667 | 1667 | /* Clear ADDR flag */ |
|
| 1668 | /* Update counter */ |
1668 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 1669 | hi2c->XferSize--; |
1669 | |
| 1670 | hi2c->XferCount--; |
1670 | while (hi2c->XferSize > 0U) |
| 1671 | } |
1671 | { |
| 1672 | } |
1672 | /* Wait until RXNE flag is set */ |
| 1673 | 1673 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
|
| 1674 | /* Wait until STOP flag is set */ |
1674 | { |
| 1675 | if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
1675 | /* Disable Address Acknowledge */ |
| 1676 | { |
1676 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1677 | /* Disable Address Acknowledge */ |
1677 | |
| 1678 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1678 | return HAL_ERROR; |
| 1679 | 1679 | } |
|
| 1680 | return HAL_ERROR; |
1680 | |
| 1681 | } |
1681 | /* Read data from DR */ |
| 1682 | 1682 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
|
| 1683 | /* Clear STOP flag */ |
1683 | |
| 1684 | __HAL_I2C_CLEAR_STOPFLAG(hi2c); |
1684 | /* Increment Buffer pointer */ |
| 1685 | 1685 | hi2c->pBuffPtr++; |
|
| 1686 | /* Disable Address Acknowledge */ |
1686 | |
| 1687 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1687 | /* Update counter */ |
| 1688 | 1688 | hi2c->XferSize--; |
|
| 1689 | hi2c->State = HAL_I2C_STATE_READY; |
1689 | hi2c->XferCount--; |
| 1690 | hi2c->Mode = HAL_I2C_MODE_NONE; |
1690 | |
| 1691 | 1691 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
|
| 1692 | /* Process Unlocked */ |
1692 | { |
| 1693 | __HAL_UNLOCK(hi2c); |
1693 | /* Read data from DR */ |
| 1694 | 1694 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
|
| 1695 | return HAL_OK; |
1695 | |
| 1696 | } |
1696 | /* Increment Buffer pointer */ |
| 1697 | else |
1697 | hi2c->pBuffPtr++; |
| 1698 | { |
1698 | |
| 1699 | return HAL_BUSY; |
1699 | /* Update counter */ |
| 1700 | } |
1700 | hi2c->XferSize--; |
| 1701 | } |
1701 | hi2c->XferCount--; |
| 1702 | 1702 | } |
|
| 1703 | /** |
1703 | } |
| 1704 | * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt |
1704 | |
| 1705 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
1705 | /* Wait until STOP flag is set */ |
| 1706 | * the configuration information for the specified I2C. |
1706 | if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
| 1707 | * @param DevAddress Target device address: The device 7 bits address value |
1707 | { |
| 1708 | * in datasheet must be shifted to the left before calling the interface |
1708 | /* Disable Address Acknowledge */ |
| 1709 | * @param pData Pointer to data buffer |
1709 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1710 | * @param Size Amount of data to be sent |
1710 | |
| 1711 | * @retval HAL status |
1711 | return HAL_ERROR; |
| 1712 | */ |
1712 | } |
| 1713 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
1713 | |
| 1714 | { |
1714 | /* Clear STOP flag */ |
| 1715 | __IO uint32_t count = 0U; |
1715 | __HAL_I2C_CLEAR_STOPFLAG(hi2c); |
| 1716 | 1716 | ||
| 1717 | if (hi2c->State == HAL_I2C_STATE_READY) |
1717 | /* Disable Address Acknowledge */ |
| 1718 | { |
1718 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1719 | /* Wait until BUSY flag is reset */ |
1719 | |
| 1720 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
1720 | hi2c->State = HAL_I2C_STATE_READY; |
| 1721 | do |
1721 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 1722 | { |
1722 | |
| 1723 | count--; |
1723 | /* Process Unlocked */ |
| 1724 | if (count == 0U) |
1724 | __HAL_UNLOCK(hi2c); |
| 1725 | { |
1725 | |
| 1726 | hi2c->PreviousState = I2C_STATE_NONE; |
1726 | return HAL_OK; |
| 1727 | hi2c->State = HAL_I2C_STATE_READY; |
1727 | } |
| 1728 | hi2c->Mode = HAL_I2C_MODE_NONE; |
1728 | else |
| 1729 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
1729 | { |
| 1730 | 1730 | return HAL_BUSY; |
|
| 1731 | /* Process Unlocked */ |
1731 | } |
| 1732 | __HAL_UNLOCK(hi2c); |
1732 | } |
| 1733 | 1733 | ||
| 1734 | return HAL_ERROR; |
1734 | /** |
| 1735 | } |
1735 | * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt |
| 1736 | } |
1736 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 1737 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
1737 | * the configuration information for the specified I2C. |
| 1738 | 1738 | * @param DevAddress Target device address: The device 7 bits address value |
|
| 1739 | /* Process Locked */ |
1739 | * in datasheet must be shifted to the left before calling the interface |
| 1740 | __HAL_LOCK(hi2c); |
1740 | * @param pData Pointer to data buffer |
| 1741 | 1741 | * @param Size Amount of data to be sent |
|
| 1742 | /* Check if the I2C is already enabled */ |
1742 | * @retval HAL status |
| 1743 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
1743 | */ |
| 1744 | { |
1744 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
| 1745 | /* Enable I2C peripheral */ |
1745 | { |
| 1746 | __HAL_I2C_ENABLE(hi2c); |
1746 | __IO uint32_t count = 0U; |
| 1747 | } |
1747 | |
| 1748 | 1748 | if (hi2c->State == HAL_I2C_STATE_READY) |
|
| 1749 | /* Disable Pos */ |
1749 | { |
| 1750 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
1750 | /* Wait until BUSY flag is reset */ |
| 1751 | 1751 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
|
| 1752 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
1752 | do |
| 1753 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
1753 | { |
| 1754 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
1754 | count--; |
| 1755 | 1755 | if (count == 0U) |
|
| 1756 | /* Prepare transfer parameters */ |
1756 | { |
| 1757 | hi2c->pBuffPtr = pData; |
1757 | hi2c->PreviousState = I2C_STATE_NONE; |
| 1758 | hi2c->XferCount = Size; |
1758 | hi2c->State = HAL_I2C_STATE_READY; |
| 1759 | hi2c->XferSize = hi2c->XferCount; |
1759 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 1760 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
1760 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 1761 | hi2c->Devaddress = DevAddress; |
1761 | |
| 1762 | 1762 | return HAL_BUSY; |
|
| 1763 | /* Process Unlocked */ |
1763 | } |
| 1764 | __HAL_UNLOCK(hi2c); |
1764 | } |
| 1765 | 1765 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
|
| 1766 | /* Note : The I2C interrupts must be enabled after unlocking current process |
1766 | |
| 1767 | to avoid the risk of I2C interrupt handle execution before current |
1767 | /* Process Locked */ |
| 1768 | process unlock */ |
1768 | __HAL_LOCK(hi2c); |
| 1769 | /* Enable EVT, BUF and ERR interrupt */ |
1769 | |
| 1770 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
1770 | /* Check if the I2C is already enabled */ |
| 1771 | 1771 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
|
| 1772 | /* Generate Start */ |
1772 | { |
| 1773 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
1773 | /* Enable I2C peripheral */ |
| 1774 | 1774 | __HAL_I2C_ENABLE(hi2c); |
|
| 1775 | return HAL_OK; |
1775 | } |
| 1776 | } |
1776 | |
| 1777 | else |
1777 | /* Disable Pos */ |
| 1778 | { |
1778 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 1779 | return HAL_BUSY; |
1779 | |
| 1780 | } |
1780 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
| 1781 | } |
1781 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
| 1782 | 1782 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
|
| 1783 | /** |
1783 | |
| 1784 | * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt |
1784 | /* Prepare transfer parameters */ |
| 1785 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
1785 | hi2c->pBuffPtr = pData; |
| 1786 | * the configuration information for the specified I2C. |
1786 | hi2c->XferCount = Size; |
| 1787 | * @param DevAddress Target device address: The device 7 bits address value |
1787 | hi2c->XferSize = hi2c->XferCount; |
| 1788 | * in datasheet must be shifted to the left before calling the interface |
1788 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 1789 | * @param pData Pointer to data buffer |
1789 | hi2c->Devaddress = DevAddress; |
| 1790 | * @param Size Amount of data to be sent |
1790 | |
| 1791 | * @retval HAL status |
1791 | /* Process Unlocked */ |
| 1792 | */ |
1792 | __HAL_UNLOCK(hi2c); |
| 1793 | HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
1793 | |
| 1794 | { |
1794 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 1795 | __IO uint32_t count = 0U; |
1795 | to avoid the risk of I2C interrupt handle execution before current |
| 1796 | 1796 | process unlock */ |
|
| 1797 | if (hi2c->State == HAL_I2C_STATE_READY) |
1797 | /* Enable EVT, BUF and ERR interrupt */ |
| 1798 | { |
1798 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 1799 | /* Wait until BUSY flag is reset */ |
1799 | |
| 1800 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
1800 | /* Generate Start */ |
| 1801 | do |
1801 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 1802 | { |
1802 | |
| 1803 | count--; |
1803 | return HAL_OK; |
| 1804 | if (count == 0U) |
1804 | } |
| 1805 | { |
1805 | else |
| 1806 | hi2c->PreviousState = I2C_STATE_NONE; |
1806 | { |
| 1807 | hi2c->State = HAL_I2C_STATE_READY; |
1807 | return HAL_BUSY; |
| 1808 | hi2c->Mode = HAL_I2C_MODE_NONE; |
1808 | } |
| 1809 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
1809 | } |
| 1810 | 1810 | ||
| 1811 | /* Process Unlocked */ |
1811 | /** |
| 1812 | __HAL_UNLOCK(hi2c); |
1812 | * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt |
| 1813 | 1813 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 1814 | return HAL_ERROR; |
1814 | * the configuration information for the specified I2C. |
| 1815 | } |
1815 | * @param DevAddress Target device address: The device 7 bits address value |
| 1816 | } |
1816 | * in datasheet must be shifted to the left before calling the interface |
| 1817 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
1817 | * @param pData Pointer to data buffer |
| 1818 | 1818 | * @param Size Amount of data to be sent |
|
| 1819 | /* Process Locked */ |
1819 | * @retval HAL status |
| 1820 | __HAL_LOCK(hi2c); |
1820 | */ |
| 1821 | 1821 | HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
|
| 1822 | /* Check if the I2C is already enabled */ |
1822 | { |
| 1823 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
1823 | __IO uint32_t count = 0U; |
| 1824 | { |
1824 | |
| 1825 | /* Enable I2C peripheral */ |
1825 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 1826 | __HAL_I2C_ENABLE(hi2c); |
1826 | { |
| 1827 | } |
1827 | /* Wait until BUSY flag is reset */ |
| 1828 | 1828 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
|
| 1829 | /* Disable Pos */ |
1829 | do |
| 1830 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
1830 | { |
| 1831 | 1831 | count--; |
|
| 1832 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
1832 | if (count == 0U) |
| 1833 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
1833 | { |
| 1834 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
1834 | hi2c->PreviousState = I2C_STATE_NONE; |
| 1835 | 1835 | hi2c->State = HAL_I2C_STATE_READY; |
|
| 1836 | /* Prepare transfer parameters */ |
1836 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 1837 | hi2c->pBuffPtr = pData; |
1837 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 1838 | hi2c->XferCount = Size; |
1838 | |
| 1839 | hi2c->XferSize = hi2c->XferCount; |
1839 | return HAL_BUSY; |
| 1840 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
1840 | } |
| 1841 | hi2c->Devaddress = DevAddress; |
1841 | } |
| 1842 | 1842 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
|
| 1843 | 1843 | ||
| 1844 | /* Process Unlocked */ |
1844 | /* Process Locked */ |
| 1845 | __HAL_UNLOCK(hi2c); |
1845 | __HAL_LOCK(hi2c); |
| 1846 | 1846 | ||
| 1847 | /* Note : The I2C interrupts must be enabled after unlocking current process |
1847 | /* Check if the I2C is already enabled */ |
| 1848 | to avoid the risk of I2C interrupt handle execution before current |
1848 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 1849 | process unlock */ |
1849 | { |
| 1850 | 1850 | /* Enable I2C peripheral */ |
|
| 1851 | /* Enable EVT, BUF and ERR interrupt */ |
1851 | __HAL_I2C_ENABLE(hi2c); |
| 1852 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
1852 | } |
| 1853 | 1853 | ||
| 1854 | /* Enable Acknowledge */ |
1854 | /* Disable Pos */ |
| 1855 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1855 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 1856 | 1856 | ||
| 1857 | /* Generate Start */ |
1857 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
| 1858 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
1858 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
| 1859 | 1859 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
|
| 1860 | return HAL_OK; |
1860 | |
| 1861 | } |
1861 | /* Prepare transfer parameters */ |
| 1862 | else |
1862 | hi2c->pBuffPtr = pData; |
| 1863 | { |
1863 | hi2c->XferCount = Size; |
| 1864 | return HAL_BUSY; |
1864 | hi2c->XferSize = hi2c->XferCount; |
| 1865 | } |
1865 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 1866 | } |
1866 | hi2c->Devaddress = DevAddress; |
| 1867 | 1867 | ||
| 1868 | /** |
1868 | |
| 1869 | * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt |
1869 | /* Process Unlocked */ |
| 1870 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
1870 | __HAL_UNLOCK(hi2c); |
| 1871 | * the configuration information for the specified I2C. |
1871 | |
| 1872 | * @param pData Pointer to data buffer |
1872 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 1873 | * @param Size Amount of data to be sent |
1873 | to avoid the risk of I2C interrupt handle execution before current |
| 1874 | * @retval HAL status |
1874 | process unlock */ |
| 1875 | */ |
1875 | |
| 1876 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
1876 | /* Enable EVT, BUF and ERR interrupt */ |
| 1877 | { |
1877 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 1878 | 1878 | ||
| 1879 | if (hi2c->State == HAL_I2C_STATE_READY) |
1879 | /* Enable Acknowledge */ |
| 1880 | { |
1880 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1881 | if ((pData == NULL) || (Size == 0U)) |
1881 | |
| 1882 | { |
1882 | /* Generate Start */ |
| 1883 | return HAL_ERROR; |
1883 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 1884 | } |
1884 | |
| 1885 | 1885 | return HAL_OK; |
|
| 1886 | /* Process Locked */ |
1886 | } |
| 1887 | __HAL_LOCK(hi2c); |
1887 | else |
| 1888 | 1888 | { |
|
| 1889 | /* Check if the I2C is already enabled */ |
1889 | return HAL_BUSY; |
| 1890 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
1890 | } |
| 1891 | { |
1891 | } |
| 1892 | /* Enable I2C peripheral */ |
1892 | |
| 1893 | __HAL_I2C_ENABLE(hi2c); |
1893 | /** |
| 1894 | } |
1894 | * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt |
| 1895 | 1895 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 1896 | /* Disable Pos */ |
1896 | * the configuration information for the specified I2C. |
| 1897 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
1897 | * @param pData Pointer to data buffer |
| 1898 | 1898 | * @param Size Amount of data to be sent |
|
| 1899 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
1899 | * @retval HAL status |
| 1900 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
1900 | */ |
| 1901 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
1901 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
| 1902 | 1902 | { |
|
| 1903 | /* Prepare transfer parameters */ |
1903 | |
| 1904 | hi2c->pBuffPtr = pData; |
1904 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 1905 | hi2c->XferCount = Size; |
1905 | { |
| 1906 | hi2c->XferSize = hi2c->XferCount; |
1906 | if ((pData == NULL) || (Size == 0U)) |
| 1907 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
1907 | { |
| 1908 | 1908 | return HAL_ERROR; |
|
| 1909 | /* Enable Address Acknowledge */ |
1909 | } |
| 1910 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1910 | |
| 1911 | 1911 | /* Process Locked */ |
|
| 1912 | /* Process Unlocked */ |
1912 | __HAL_LOCK(hi2c); |
| 1913 | __HAL_UNLOCK(hi2c); |
1913 | |
| 1914 | 1914 | /* Check if the I2C is already enabled */ |
|
| 1915 | /* Note : The I2C interrupts must be enabled after unlocking current process |
1915 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 1916 | to avoid the risk of I2C interrupt handle execution before current |
1916 | { |
| 1917 | process unlock */ |
1917 | /* Enable I2C peripheral */ |
| 1918 | 1918 | __HAL_I2C_ENABLE(hi2c); |
|
| 1919 | /* Enable EVT, BUF and ERR interrupt */ |
1919 | } |
| 1920 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
1920 | |
| 1921 | 1921 | /* Disable Pos */ |
|
| 1922 | return HAL_OK; |
1922 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 1923 | } |
1923 | |
| 1924 | else |
1924 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
| 1925 | { |
1925 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
| 1926 | return HAL_BUSY; |
1926 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 1927 | } |
1927 | |
| 1928 | } |
1928 | /* Prepare transfer parameters */ |
| 1929 | 1929 | hi2c->pBuffPtr = pData; |
|
| 1930 | /** |
1930 | hi2c->XferCount = Size; |
| 1931 | * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt |
1931 | hi2c->XferSize = hi2c->XferCount; |
| 1932 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
1932 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 1933 | * the configuration information for the specified I2C. |
1933 | |
| 1934 | * @param pData Pointer to data buffer |
1934 | /* Enable Address Acknowledge */ |
| 1935 | * @param Size Amount of data to be sent |
1935 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1936 | * @retval HAL status |
1936 | |
| 1937 | */ |
1937 | /* Process Unlocked */ |
| 1938 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
1938 | __HAL_UNLOCK(hi2c); |
| 1939 | { |
1939 | |
| 1940 | 1940 | /* Note : The I2C interrupts must be enabled after unlocking current process |
|
| 1941 | if (hi2c->State == HAL_I2C_STATE_READY) |
1941 | to avoid the risk of I2C interrupt handle execution before current |
| 1942 | { |
1942 | process unlock */ |
| 1943 | if ((pData == NULL) || (Size == 0U)) |
1943 | |
| 1944 | { |
1944 | /* Enable EVT, BUF and ERR interrupt */ |
| 1945 | return HAL_ERROR; |
1945 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 1946 | } |
1946 | |
| 1947 | 1947 | return HAL_OK; |
|
| 1948 | /* Process Locked */ |
1948 | } |
| 1949 | __HAL_LOCK(hi2c); |
1949 | else |
| 1950 | 1950 | { |
|
| 1951 | /* Check if the I2C is already enabled */ |
1951 | return HAL_BUSY; |
| 1952 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
1952 | } |
| 1953 | { |
1953 | } |
| 1954 | /* Enable I2C peripheral */ |
1954 | |
| 1955 | __HAL_I2C_ENABLE(hi2c); |
1955 | /** |
| 1956 | } |
1956 | * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt |
| 1957 | 1957 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 1958 | /* Disable Pos */ |
1958 | * the configuration information for the specified I2C. |
| 1959 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
1959 | * @param pData Pointer to data buffer |
| 1960 | 1960 | * @param Size Amount of data to be sent |
|
| 1961 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
1961 | * @retval HAL status |
| 1962 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
1962 | */ |
| 1963 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
1963 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
| 1964 | 1964 | { |
|
| 1965 | /* Prepare transfer parameters */ |
1965 | |
| 1966 | hi2c->pBuffPtr = pData; |
1966 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 1967 | hi2c->XferCount = Size; |
1967 | { |
| 1968 | hi2c->XferSize = hi2c->XferCount; |
1968 | if ((pData == NULL) || (Size == 0U)) |
| 1969 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
1969 | { |
| 1970 | 1970 | return HAL_ERROR; |
|
| 1971 | /* Enable Address Acknowledge */ |
1971 | } |
| 1972 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
1972 | |
| 1973 | 1973 | /* Process Locked */ |
|
| 1974 | /* Process Unlocked */ |
1974 | __HAL_LOCK(hi2c); |
| 1975 | __HAL_UNLOCK(hi2c); |
1975 | |
| 1976 | 1976 | /* Check if the I2C is already enabled */ |
|
| 1977 | /* Note : The I2C interrupts must be enabled after unlocking current process |
1977 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 1978 | to avoid the risk of I2C interrupt handle execution before current |
1978 | { |
| 1979 | process unlock */ |
1979 | /* Enable I2C peripheral */ |
| 1980 | 1980 | __HAL_I2C_ENABLE(hi2c); |
|
| 1981 | /* Enable EVT, BUF and ERR interrupt */ |
1981 | } |
| 1982 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
1982 | |
| 1983 | 1983 | /* Disable Pos */ |
|
| 1984 | return HAL_OK; |
1984 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 1985 | } |
1985 | |
| 1986 | else |
1986 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
| 1987 | { |
1987 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
| 1988 | return HAL_BUSY; |
1988 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 1989 | } |
1989 | |
| 1990 | } |
1990 | /* Prepare transfer parameters */ |
| 1991 | 1991 | hi2c->pBuffPtr = pData; |
|
| 1992 | /** |
1992 | hi2c->XferCount = Size; |
| 1993 | * @brief Transmit in master mode an amount of data in non-blocking mode with DMA |
1993 | hi2c->XferSize = hi2c->XferCount; |
| 1994 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
1994 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 1995 | * the configuration information for the specified I2C. |
1995 | |
| 1996 | * @param DevAddress Target device address: The device 7 bits address value |
1996 | /* Enable Address Acknowledge */ |
| 1997 | * in datasheet must be shifted to the left before calling the interface |
1997 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 1998 | * @param pData Pointer to data buffer |
1998 | |
| 1999 | * @param Size Amount of data to be sent |
1999 | /* Process Unlocked */ |
| 2000 | * @retval HAL status |
2000 | __HAL_UNLOCK(hi2c); |
| 2001 | */ |
2001 | |
| 2002 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
2002 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 2003 | { |
2003 | to avoid the risk of I2C interrupt handle execution before current |
| 2004 | __IO uint32_t count = 0U; |
2004 | process unlock */ |
| 2005 | HAL_StatusTypeDef dmaxferstatus; |
2005 | |
| 2006 | 2006 | /* Enable EVT, BUF and ERR interrupt */ |
|
| 2007 | if (hi2c->State == HAL_I2C_STATE_READY) |
2007 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 2008 | { |
2008 | |
| 2009 | /* Wait until BUSY flag is reset */ |
2009 | return HAL_OK; |
| 2010 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
2010 | } |
| 2011 | do |
2011 | else |
| 2012 | { |
2012 | { |
| 2013 | count--; |
2013 | return HAL_BUSY; |
| 2014 | if (count == 0U) |
2014 | } |
| 2015 | { |
2015 | } |
| 2016 | hi2c->PreviousState = I2C_STATE_NONE; |
2016 | |
| 2017 | hi2c->State = HAL_I2C_STATE_READY; |
2017 | /** |
| 2018 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2018 | * @brief Transmit in master mode an amount of data in non-blocking mode with DMA |
| 2019 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
2019 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 2020 | 2020 | * the configuration information for the specified I2C. |
|
| 2021 | /* Process Unlocked */ |
2021 | * @param DevAddress Target device address: The device 7 bits address value |
| 2022 | __HAL_UNLOCK(hi2c); |
2022 | * in datasheet must be shifted to the left before calling the interface |
| 2023 | 2023 | * @param pData Pointer to data buffer |
|
| 2024 | return HAL_ERROR; |
2024 | * @param Size Amount of data to be sent |
| 2025 | } |
2025 | * @retval HAL status |
| 2026 | } |
2026 | */ |
| 2027 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
2027 | HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
| 2028 | 2028 | { |
|
| 2029 | /* Process Locked */ |
2029 | __IO uint32_t count = 0U; |
| 2030 | __HAL_LOCK(hi2c); |
2030 | HAL_StatusTypeDef dmaxferstatus; |
| 2031 | 2031 | ||
| 2032 | /* Check if the I2C is already enabled */ |
2032 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 2033 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
2033 | { |
| 2034 | { |
2034 | /* Wait until BUSY flag is reset */ |
| 2035 | /* Enable I2C peripheral */ |
2035 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
| 2036 | __HAL_I2C_ENABLE(hi2c); |
2036 | do |
| 2037 | } |
2037 | { |
| 2038 | 2038 | count--; |
|
| 2039 | /* Disable Pos */ |
2039 | if (count == 0U) |
| 2040 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
2040 | { |
| 2041 | 2041 | hi2c->PreviousState = I2C_STATE_NONE; |
|
| 2042 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
2042 | hi2c->State = HAL_I2C_STATE_READY; |
| 2043 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
2043 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 2044 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
2044 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 2045 | 2045 | ||
| 2046 | /* Prepare transfer parameters */ |
2046 | return HAL_BUSY; |
| 2047 | hi2c->pBuffPtr = pData; |
2047 | } |
| 2048 | hi2c->XferCount = Size; |
2048 | } |
| 2049 | hi2c->XferSize = hi2c->XferCount; |
2049 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
| 2050 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
2050 | |
| 2051 | hi2c->Devaddress = DevAddress; |
2051 | /* Process Locked */ |
| 2052 | 2052 | __HAL_LOCK(hi2c); |
|
| 2053 | if (hi2c->XferSize > 0U) |
2053 | |
| 2054 | { |
2054 | /* Check if the I2C is already enabled */ |
| 2055 | if (hi2c->hdmatx != NULL) |
2055 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 2056 | { |
2056 | { |
| 2057 | /* Set the I2C DMA transfer complete callback */ |
2057 | /* Enable I2C peripheral */ |
| 2058 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
2058 | __HAL_I2C_ENABLE(hi2c); |
| 2059 | 2059 | } |
|
| 2060 | /* Set the DMA error callback */ |
2060 | |
| 2061 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
2061 | /* Disable Pos */ |
| 2062 | 2062 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
|
| 2063 | /* Set the unused DMA callbacks to NULL */ |
2063 | |
| 2064 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
2064 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
| 2065 | hi2c->hdmatx->XferAbortCallback = NULL; |
2065 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
| 2066 | 2066 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
|
| 2067 | /* Enable the DMA channel */ |
2067 | |
| 2068 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
2068 | /* Prepare transfer parameters */ |
| 2069 | } |
2069 | hi2c->pBuffPtr = pData; |
| 2070 | else |
2070 | hi2c->XferCount = Size; |
| 2071 | { |
2071 | hi2c->XferSize = hi2c->XferCount; |
| 2072 | /* Update I2C state */ |
2072 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 2073 | hi2c->State = HAL_I2C_STATE_READY; |
2073 | hi2c->Devaddress = DevAddress; |
| 2074 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2074 | |
| 2075 | 2075 | if (hi2c->XferSize > 0U) |
|
| 2076 | /* Update I2C error code */ |
2076 | { |
| 2077 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
2077 | if (hi2c->hdmatx != NULL) |
| 2078 | 2078 | { |
|
| 2079 | /* Process Unlocked */ |
2079 | /* Set the I2C DMA transfer complete callback */ |
| 2080 | __HAL_UNLOCK(hi2c); |
2080 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
| 2081 | 2081 | ||
| 2082 | return HAL_ERROR; |
2082 | /* Set the DMA error callback */ |
| 2083 | } |
2083 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
| 2084 | 2084 | ||
| 2085 | if (dmaxferstatus == HAL_OK) |
2085 | /* Set the unused DMA callbacks to NULL */ |
| 2086 | { |
2086 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
| 2087 | /* Process Unlocked */ |
2087 | hi2c->hdmatx->XferAbortCallback = NULL; |
| 2088 | __HAL_UNLOCK(hi2c); |
2088 | |
| 2089 | 2089 | /* Enable the DMA channel */ |
|
| 2090 | /* Note : The I2C interrupts must be enabled after unlocking current process |
2090 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
| 2091 | to avoid the risk of I2C interrupt handle execution before current |
2091 | } |
| 2092 | process unlock */ |
2092 | else |
| 2093 | 2093 | { |
|
| 2094 | /* Enable EVT and ERR interrupt */ |
2094 | /* Update I2C state */ |
| 2095 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
2095 | hi2c->State = HAL_I2C_STATE_READY; |
| 2096 | 2096 | hi2c->Mode = HAL_I2C_MODE_NONE; |
|
| 2097 | /* Enable DMA Request */ |
2097 | |
| 2098 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
2098 | /* Update I2C error code */ |
| 2099 | 2099 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
|
| 2100 | /* Enable Acknowledge */ |
2100 | |
| 2101 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
2101 | /* Process Unlocked */ |
| 2102 | 2102 | __HAL_UNLOCK(hi2c); |
|
| 2103 | /* Generate Start */ |
2103 | |
| 2104 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
2104 | return HAL_ERROR; |
| 2105 | } |
2105 | } |
| 2106 | else |
2106 | |
| 2107 | { |
2107 | if (dmaxferstatus == HAL_OK) |
| 2108 | /* Update I2C state */ |
2108 | { |
| 2109 | hi2c->State = HAL_I2C_STATE_READY; |
2109 | /* Process Unlocked */ |
| 2110 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2110 | __HAL_UNLOCK(hi2c); |
| 2111 | 2111 | ||
| 2112 | /* Update I2C error code */ |
2112 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 2113 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
2113 | to avoid the risk of I2C interrupt handle execution before current |
| 2114 | 2114 | process unlock */ |
|
| 2115 | /* Process Unlocked */ |
2115 | |
| 2116 | __HAL_UNLOCK(hi2c); |
2116 | /* Enable EVT and ERR interrupt */ |
| 2117 | 2117 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
|
| 2118 | return HAL_ERROR; |
2118 | |
| 2119 | } |
2119 | /* Enable DMA Request */ |
| 2120 | } |
2120 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 2121 | else |
2121 | |
| 2122 | { |
2122 | /* Enable Acknowledge */ |
| 2123 | /* Enable Acknowledge */ |
2123 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 2124 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
2124 | |
| 2125 | 2125 | /* Generate Start */ |
|
| 2126 | /* Generate Start */ |
2126 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 2127 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
2127 | } |
| 2128 | 2128 | else |
|
| 2129 | /* Process Unlocked */ |
2129 | { |
| 2130 | __HAL_UNLOCK(hi2c); |
2130 | /* Update I2C state */ |
| 2131 | 2131 | hi2c->State = HAL_I2C_STATE_READY; |
|
| 2132 | /* Note : The I2C interrupts must be enabled after unlocking current process |
2132 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 2133 | to avoid the risk of I2C interrupt handle execution before current |
2133 | |
| 2134 | process unlock */ |
2134 | /* Update I2C error code */ |
| 2135 | 2135 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
|
| 2136 | /* Enable EVT, BUF and ERR interrupt */ |
2136 | |
| 2137 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
2137 | /* Process Unlocked */ |
| 2138 | } |
2138 | __HAL_UNLOCK(hi2c); |
| 2139 | 2139 | ||
| 2140 | return HAL_OK; |
2140 | return HAL_ERROR; |
| 2141 | } |
2141 | } |
| 2142 | else |
2142 | } |
| 2143 | { |
2143 | else |
| 2144 | return HAL_BUSY; |
2144 | { |
| 2145 | } |
2145 | /* Enable Acknowledge */ |
| 2146 | } |
2146 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 2147 | 2147 | ||
| 2148 | /** |
2148 | /* Generate Start */ |
| 2149 | * @brief Receive in master mode an amount of data in non-blocking mode with DMA |
2149 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 2150 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
2150 | |
| 2151 | * the configuration information for the specified I2C. |
2151 | /* Process Unlocked */ |
| 2152 | * @param DevAddress Target device address: The device 7 bits address value |
2152 | __HAL_UNLOCK(hi2c); |
| 2153 | * in datasheet must be shifted to the left before calling the interface |
2153 | |
| 2154 | * @param pData Pointer to data buffer |
2154 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 2155 | * @param Size Amount of data to be sent |
2155 | to avoid the risk of I2C interrupt handle execution before current |
| 2156 | * @retval HAL status |
2156 | process unlock */ |
| 2157 | */ |
2157 | |
| 2158 | HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
2158 | /* Enable EVT, BUF and ERR interrupt */ |
| 2159 | { |
2159 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 2160 | __IO uint32_t count = 0U; |
2160 | } |
| 2161 | HAL_StatusTypeDef dmaxferstatus; |
2161 | |
| 2162 | 2162 | return HAL_OK; |
|
| 2163 | if (hi2c->State == HAL_I2C_STATE_READY) |
2163 | } |
| 2164 | { |
2164 | else |
| 2165 | /* Wait until BUSY flag is reset */ |
2165 | { |
| 2166 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
2166 | return HAL_BUSY; |
| 2167 | do |
2167 | } |
| 2168 | { |
2168 | } |
| 2169 | count--; |
2169 | |
| 2170 | if (count == 0U) |
2170 | /** |
| 2171 | { |
2171 | * @brief Receive in master mode an amount of data in non-blocking mode with DMA |
| 2172 | hi2c->PreviousState = I2C_STATE_NONE; |
2172 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 2173 | hi2c->State = HAL_I2C_STATE_READY; |
2173 | * the configuration information for the specified I2C. |
| 2174 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2174 | * @param DevAddress Target device address: The device 7 bits address value |
| 2175 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
2175 | * in datasheet must be shifted to the left before calling the interface |
| 2176 | 2176 | * @param pData Pointer to data buffer |
|
| 2177 | /* Process Unlocked */ |
2177 | * @param Size Amount of data to be sent |
| 2178 | __HAL_UNLOCK(hi2c); |
2178 | * @retval HAL status |
| 2179 | 2179 | */ |
|
| 2180 | return HAL_ERROR; |
2180 | HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size) |
| 2181 | } |
2181 | { |
| 2182 | } |
2182 | __IO uint32_t count = 0U; |
| 2183 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
2183 | HAL_StatusTypeDef dmaxferstatus; |
| 2184 | 2184 | ||
| 2185 | /* Process Locked */ |
2185 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 2186 | __HAL_LOCK(hi2c); |
2186 | { |
| 2187 | 2187 | /* Wait until BUSY flag is reset */ |
|
| 2188 | /* Check if the I2C is already enabled */ |
2188 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
| 2189 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
2189 | do |
| 2190 | { |
2190 | { |
| 2191 | /* Enable I2C peripheral */ |
2191 | count--; |
| 2192 | __HAL_I2C_ENABLE(hi2c); |
2192 | if (count == 0U) |
| 2193 | } |
2193 | { |
| 2194 | 2194 | hi2c->PreviousState = I2C_STATE_NONE; |
|
| 2195 | /* Disable Pos */ |
2195 | hi2c->State = HAL_I2C_STATE_READY; |
| 2196 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
2196 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 2197 | 2197 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
|
| 2198 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
2198 | |
| 2199 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
2199 | return HAL_BUSY; |
| 2200 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
2200 | } |
| 2201 | 2201 | } |
|
| 2202 | /* Prepare transfer parameters */ |
2202 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
| 2203 | hi2c->pBuffPtr = pData; |
2203 | |
| 2204 | hi2c->XferCount = Size; |
2204 | /* Process Locked */ |
| 2205 | hi2c->XferSize = hi2c->XferCount; |
2205 | __HAL_LOCK(hi2c); |
| 2206 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
2206 | |
| 2207 | hi2c->Devaddress = DevAddress; |
2207 | /* Check if the I2C is already enabled */ |
| 2208 | 2208 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
|
| 2209 | if (hi2c->XferSize > 0U) |
2209 | { |
| 2210 | { |
2210 | /* Enable I2C peripheral */ |
| 2211 | if (hi2c->hdmarx != NULL) |
2211 | __HAL_I2C_ENABLE(hi2c); |
| 2212 | { |
2212 | } |
| 2213 | /* Set the I2C DMA transfer complete callback */ |
2213 | |
| 2214 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
2214 | /* Disable Pos */ |
| 2215 | 2215 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
|
| 2216 | /* Set the DMA error callback */ |
2216 | |
| 2217 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
2217 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
| 2218 | 2218 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
|
| 2219 | /* Set the unused DMA callbacks to NULL */ |
2219 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 2220 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
2220 | |
| 2221 | hi2c->hdmarx->XferAbortCallback = NULL; |
2221 | /* Prepare transfer parameters */ |
| 2222 | 2222 | hi2c->pBuffPtr = pData; |
|
| 2223 | /* Enable the DMA channel */ |
2223 | hi2c->XferCount = Size; |
| 2224 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
2224 | hi2c->XferSize = hi2c->XferCount; |
| 2225 | } |
2225 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 2226 | else |
2226 | hi2c->Devaddress = DevAddress; |
| 2227 | { |
2227 | |
| 2228 | /* Update I2C state */ |
2228 | if (hi2c->XferSize > 0U) |
| 2229 | hi2c->State = HAL_I2C_STATE_READY; |
2229 | { |
| 2230 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2230 | if (hi2c->hdmarx != NULL) |
| 2231 | 2231 | { |
|
| 2232 | /* Update I2C error code */ |
2232 | /* Set the I2C DMA transfer complete callback */ |
| 2233 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
2233 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
| 2234 | 2234 | ||
| 2235 | /* Process Unlocked */ |
2235 | /* Set the DMA error callback */ |
| 2236 | __HAL_UNLOCK(hi2c); |
2236 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
| 2237 | 2237 | ||
| 2238 | return HAL_ERROR; |
2238 | /* Set the unused DMA callbacks to NULL */ |
| 2239 | } |
2239 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
| 2240 | 2240 | hi2c->hdmarx->XferAbortCallback = NULL; |
|
| 2241 | if (dmaxferstatus == HAL_OK) |
2241 | |
| 2242 | { |
2242 | /* Enable the DMA channel */ |
| 2243 | /* Enable Acknowledge */ |
2243 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
| 2244 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
2244 | } |
| 2245 | 2245 | else |
|
| 2246 | /* Generate Start */ |
2246 | { |
| 2247 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
2247 | /* Update I2C state */ |
| 2248 | 2248 | hi2c->State = HAL_I2C_STATE_READY; |
|
| 2249 | /* Process Unlocked */ |
2249 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 2250 | __HAL_UNLOCK(hi2c); |
2250 | |
| 2251 | 2251 | /* Update I2C error code */ |
|
| 2252 | /* Note : The I2C interrupts must be enabled after unlocking current process |
2252 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
| 2253 | to avoid the risk of I2C interrupt handle execution before current |
2253 | |
| 2254 | process unlock */ |
2254 | /* Process Unlocked */ |
| 2255 | 2255 | __HAL_UNLOCK(hi2c); |
|
| 2256 | /* Enable EVT and ERR interrupt */ |
2256 | |
| 2257 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
2257 | return HAL_ERROR; |
| 2258 | 2258 | } |
|
| 2259 | /* Enable DMA Request */ |
2259 | |
| 2260 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
2260 | if (dmaxferstatus == HAL_OK) |
| 2261 | } |
2261 | { |
| 2262 | else |
2262 | /* Enable Acknowledge */ |
| 2263 | { |
2263 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 2264 | /* Update I2C state */ |
2264 | |
| 2265 | hi2c->State = HAL_I2C_STATE_READY; |
2265 | /* Generate Start */ |
| 2266 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2266 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 2267 | 2267 | ||
| 2268 | /* Update I2C error code */ |
2268 | /* Process Unlocked */ |
| 2269 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
2269 | __HAL_UNLOCK(hi2c); |
| 2270 | 2270 | ||
| 2271 | /* Process Unlocked */ |
2271 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 2272 | __HAL_UNLOCK(hi2c); |
2272 | to avoid the risk of I2C interrupt handle execution before current |
| 2273 | 2273 | process unlock */ |
|
| 2274 | return HAL_ERROR; |
2274 | |
| 2275 | } |
2275 | /* Enable EVT and ERR interrupt */ |
| 2276 | } |
2276 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 2277 | else |
2277 | |
| 2278 | { |
2278 | /* Enable DMA Request */ |
| 2279 | /* Process Unlocked */ |
2279 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 2280 | __HAL_UNLOCK(hi2c); |
2280 | } |
| 2281 | 2281 | else |
|
| 2282 | /* Note : The I2C interrupts must be enabled after unlocking current process |
2282 | { |
| 2283 | to avoid the risk of I2C interrupt handle execution before current |
2283 | /* Update I2C state */ |
| 2284 | process unlock */ |
2284 | hi2c->State = HAL_I2C_STATE_READY; |
| 2285 | 2285 | hi2c->Mode = HAL_I2C_MODE_NONE; |
|
| 2286 | /* Enable EVT, BUF and ERR interrupt */ |
2286 | |
| 2287 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
2287 | /* Update I2C error code */ |
| 2288 | 2288 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
|
| 2289 | /* Enable Acknowledge */ |
2289 | |
| 2290 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
2290 | /* Process Unlocked */ |
| 2291 | 2291 | __HAL_UNLOCK(hi2c); |
|
| 2292 | /* Generate Start */ |
2292 | |
| 2293 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
2293 | return HAL_ERROR; |
| 2294 | } |
2294 | } |
| 2295 | 2295 | } |
|
| 2296 | return HAL_OK; |
2296 | else |
| 2297 | } |
2297 | { |
| 2298 | else |
2298 | /* Process Unlocked */ |
| 2299 | { |
2299 | __HAL_UNLOCK(hi2c); |
| 2300 | return HAL_BUSY; |
2300 | |
| 2301 | } |
2301 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 2302 | } |
2302 | to avoid the risk of I2C interrupt handle execution before current |
| 2303 | 2303 | process unlock */ |
|
| 2304 | /** |
2304 | |
| 2305 | * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA |
2305 | /* Enable EVT, BUF and ERR interrupt */ |
| 2306 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
2306 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 2307 | * the configuration information for the specified I2C. |
2307 | |
| 2308 | * @param pData Pointer to data buffer |
2308 | /* Enable Acknowledge */ |
| 2309 | * @param Size Amount of data to be sent |
2309 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 2310 | * @retval HAL status |
2310 | |
| 2311 | */ |
2311 | /* Generate Start */ |
| 2312 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
2312 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 2313 | { |
2313 | } |
| 2314 | HAL_StatusTypeDef dmaxferstatus; |
2314 | |
| 2315 | 2315 | return HAL_OK; |
|
| 2316 | if (hi2c->State == HAL_I2C_STATE_READY) |
2316 | } |
| 2317 | { |
2317 | else |
| 2318 | if ((pData == NULL) || (Size == 0U)) |
2318 | { |
| 2319 | { |
2319 | return HAL_BUSY; |
| 2320 | return HAL_ERROR; |
2320 | } |
| 2321 | } |
2321 | } |
| 2322 | 2322 | ||
| 2323 | /* Process Locked */ |
2323 | /** |
| 2324 | __HAL_LOCK(hi2c); |
2324 | * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA |
| 2325 | 2325 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 2326 | /* Check if the I2C is already enabled */ |
2326 | * the configuration information for the specified I2C. |
| 2327 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
2327 | * @param pData Pointer to data buffer |
| 2328 | { |
2328 | * @param Size Amount of data to be sent |
| 2329 | /* Enable I2C peripheral */ |
2329 | * @retval HAL status |
| 2330 | __HAL_I2C_ENABLE(hi2c); |
2330 | */ |
| 2331 | } |
2331 | HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
| 2332 | 2332 | { |
|
| 2333 | /* Disable Pos */ |
2333 | HAL_StatusTypeDef dmaxferstatus; |
| 2334 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
2334 | |
| 2335 | 2335 | if (hi2c->State == HAL_I2C_STATE_READY) |
|
| 2336 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
2336 | { |
| 2337 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
2337 | if ((pData == NULL) || (Size == 0U)) |
| 2338 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
2338 | { |
| 2339 | 2339 | return HAL_ERROR; |
|
| 2340 | /* Prepare transfer parameters */ |
2340 | } |
| 2341 | hi2c->pBuffPtr = pData; |
2341 | |
| 2342 | hi2c->XferCount = Size; |
2342 | /* Process Locked */ |
| 2343 | hi2c->XferSize = hi2c->XferCount; |
2343 | __HAL_LOCK(hi2c); |
| 2344 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
2344 | |
| 2345 | 2345 | /* Check if the I2C is already enabled */ |
|
| 2346 | if (hi2c->hdmatx != NULL) |
2346 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 2347 | { |
2347 | { |
| 2348 | /* Set the I2C DMA transfer complete callback */ |
2348 | /* Enable I2C peripheral */ |
| 2349 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
2349 | __HAL_I2C_ENABLE(hi2c); |
| 2350 | 2350 | } |
|
| 2351 | /* Set the DMA error callback */ |
2351 | |
| 2352 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
2352 | /* Disable Pos */ |
| 2353 | 2353 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
|
| 2354 | /* Set the unused DMA callbacks to NULL */ |
2354 | |
| 2355 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
2355 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
| 2356 | hi2c->hdmatx->XferAbortCallback = NULL; |
2356 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
| 2357 | 2357 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
|
| 2358 | /* Enable the DMA channel */ |
2358 | |
| 2359 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
2359 | /* Prepare transfer parameters */ |
| 2360 | } |
2360 | hi2c->pBuffPtr = pData; |
| 2361 | else |
2361 | hi2c->XferCount = Size; |
| 2362 | { |
2362 | hi2c->XferSize = hi2c->XferCount; |
| 2363 | /* Update I2C state */ |
2363 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 2364 | hi2c->State = HAL_I2C_STATE_LISTEN; |
2364 | |
| 2365 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2365 | if (hi2c->hdmatx != NULL) |
| 2366 | 2366 | { |
|
| 2367 | /* Update I2C error code */ |
2367 | /* Set the I2C DMA transfer complete callback */ |
| 2368 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
2368 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
| 2369 | 2369 | ||
| 2370 | /* Process Unlocked */ |
2370 | /* Set the DMA error callback */ |
| 2371 | __HAL_UNLOCK(hi2c); |
2371 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
| 2372 | 2372 | ||
| 2373 | return HAL_ERROR; |
2373 | /* Set the unused DMA callbacks to NULL */ |
| 2374 | } |
2374 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
| 2375 | 2375 | hi2c->hdmatx->XferAbortCallback = NULL; |
|
| 2376 | if (dmaxferstatus == HAL_OK) |
2376 | |
| 2377 | { |
2377 | /* Enable the DMA channel */ |
| 2378 | /* Enable Address Acknowledge */ |
2378 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
| 2379 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
2379 | } |
| 2380 | 2380 | else |
|
| 2381 | /* Process Unlocked */ |
2381 | { |
| 2382 | __HAL_UNLOCK(hi2c); |
2382 | /* Update I2C state */ |
| 2383 | 2383 | hi2c->State = HAL_I2C_STATE_LISTEN; |
|
| 2384 | /* Note : The I2C interrupts must be enabled after unlocking current process |
2384 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 2385 | to avoid the risk of I2C interrupt handle execution before current |
2385 | |
| 2386 | process unlock */ |
2386 | /* Update I2C error code */ |
| 2387 | /* Enable EVT and ERR interrupt */ |
2387 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
| 2388 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
2388 | |
| 2389 | 2389 | /* Process Unlocked */ |
|
| 2390 | /* Enable DMA Request */ |
2390 | __HAL_UNLOCK(hi2c); |
| 2391 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
2391 | |
| 2392 | 2392 | return HAL_ERROR; |
|
| 2393 | return HAL_OK; |
2393 | } |
| 2394 | } |
2394 | |
| 2395 | else |
2395 | if (dmaxferstatus == HAL_OK) |
| 2396 | { |
2396 | { |
| 2397 | /* Update I2C state */ |
2397 | /* Enable Address Acknowledge */ |
| 2398 | hi2c->State = HAL_I2C_STATE_READY; |
2398 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 2399 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2399 | |
| 2400 | 2400 | /* Process Unlocked */ |
|
| 2401 | /* Update I2C error code */ |
2401 | __HAL_UNLOCK(hi2c); |
| 2402 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
2402 | |
| 2403 | 2403 | /* Note : The I2C interrupts must be enabled after unlocking current process |
|
| 2404 | /* Process Unlocked */ |
2404 | to avoid the risk of I2C interrupt handle execution before current |
| 2405 | __HAL_UNLOCK(hi2c); |
2405 | process unlock */ |
| 2406 | 2406 | /* Enable EVT and ERR interrupt */ |
|
| 2407 | return HAL_ERROR; |
2407 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 2408 | } |
2408 | |
| 2409 | } |
2409 | /* Enable DMA Request */ |
| 2410 | else |
2410 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
| 2411 | { |
2411 | |
| 2412 | return HAL_BUSY; |
2412 | return HAL_OK; |
| 2413 | } |
2413 | } |
| 2414 | } |
2414 | else |
| 2415 | 2415 | { |
|
| 2416 | /** |
2416 | /* Update I2C state */ |
| 2417 | * @brief Receive in slave mode an amount of data in non-blocking mode with DMA |
2417 | hi2c->State = HAL_I2C_STATE_READY; |
| 2418 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
2418 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 2419 | * the configuration information for the specified I2C. |
2419 | |
| 2420 | * @param pData Pointer to data buffer |
2420 | /* Update I2C error code */ |
| 2421 | * @param Size Amount of data to be sent |
2421 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
| 2422 | * @retval HAL status |
2422 | |
| 2423 | */ |
2423 | /* Process Unlocked */ |
| 2424 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
2424 | __HAL_UNLOCK(hi2c); |
| 2425 | { |
2425 | |
| 2426 | HAL_StatusTypeDef dmaxferstatus; |
2426 | return HAL_ERROR; |
| 2427 | 2427 | } |
|
| 2428 | if (hi2c->State == HAL_I2C_STATE_READY) |
2428 | } |
| 2429 | { |
2429 | else |
| 2430 | if ((pData == NULL) || (Size == 0U)) |
2430 | { |
| 2431 | { |
2431 | return HAL_BUSY; |
| 2432 | return HAL_ERROR; |
2432 | } |
| 2433 | } |
2433 | } |
| 2434 | 2434 | ||
| 2435 | /* Process Locked */ |
2435 | /** |
| 2436 | __HAL_LOCK(hi2c); |
2436 | * @brief Receive in slave mode an amount of data in non-blocking mode with DMA |
| 2437 | 2437 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 2438 | /* Check if the I2C is already enabled */ |
2438 | * the configuration information for the specified I2C. |
| 2439 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
2439 | * @param pData Pointer to data buffer |
| 2440 | { |
2440 | * @param Size Amount of data to be sent |
| 2441 | /* Enable I2C peripheral */ |
2441 | * @retval HAL status |
| 2442 | __HAL_I2C_ENABLE(hi2c); |
2442 | */ |
| 2443 | } |
2443 | HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) |
| 2444 | 2444 | { |
|
| 2445 | /* Disable Pos */ |
2445 | HAL_StatusTypeDef dmaxferstatus; |
| 2446 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
2446 | |
| 2447 | 2447 | if (hi2c->State == HAL_I2C_STATE_READY) |
|
| 2448 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
2448 | { |
| 2449 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
2449 | if ((pData == NULL) || (Size == 0U)) |
| 2450 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
2450 | { |
| 2451 | 2451 | return HAL_ERROR; |
|
| 2452 | /* Prepare transfer parameters */ |
2452 | } |
| 2453 | hi2c->pBuffPtr = pData; |
2453 | |
| 2454 | hi2c->XferCount = Size; |
2454 | /* Process Locked */ |
| 2455 | hi2c->XferSize = hi2c->XferCount; |
2455 | __HAL_LOCK(hi2c); |
| 2456 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
2456 | |
| 2457 | 2457 | /* Check if the I2C is already enabled */ |
|
| 2458 | if (hi2c->hdmarx != NULL) |
2458 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 2459 | { |
2459 | { |
| 2460 | /* Set the I2C DMA transfer complete callback */ |
2460 | /* Enable I2C peripheral */ |
| 2461 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
2461 | __HAL_I2C_ENABLE(hi2c); |
| 2462 | 2462 | } |
|
| 2463 | /* Set the DMA error callback */ |
2463 | |
| 2464 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
2464 | /* Disable Pos */ |
| 2465 | 2465 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
|
| 2466 | /* Set the unused DMA callbacks to NULL */ |
2466 | |
| 2467 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
2467 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
| 2468 | hi2c->hdmarx->XferAbortCallback = NULL; |
2468 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
| 2469 | 2469 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
|
| 2470 | /* Enable the DMA channel */ |
2470 | |
| 2471 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
2471 | /* Prepare transfer parameters */ |
| 2472 | } |
2472 | hi2c->pBuffPtr = pData; |
| 2473 | else |
2473 | hi2c->XferCount = Size; |
| 2474 | { |
2474 | hi2c->XferSize = hi2c->XferCount; |
| 2475 | /* Update I2C state */ |
2475 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 2476 | hi2c->State = HAL_I2C_STATE_LISTEN; |
2476 | |
| 2477 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2477 | if (hi2c->hdmarx != NULL) |
| 2478 | 2478 | { |
|
| 2479 | /* Update I2C error code */ |
2479 | /* Set the I2C DMA transfer complete callback */ |
| 2480 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
2480 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
| 2481 | 2481 | ||
| 2482 | /* Process Unlocked */ |
2482 | /* Set the DMA error callback */ |
| 2483 | __HAL_UNLOCK(hi2c); |
2483 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
| 2484 | 2484 | ||
| 2485 | return HAL_ERROR; |
2485 | /* Set the unused DMA callbacks to NULL */ |
| 2486 | } |
2486 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
| 2487 | 2487 | hi2c->hdmarx->XferAbortCallback = NULL; |
|
| 2488 | if (dmaxferstatus == HAL_OK) |
2488 | |
| 2489 | { |
2489 | /* Enable the DMA channel */ |
| 2490 | /* Enable Address Acknowledge */ |
2490 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
| 2491 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
2491 | } |
| 2492 | 2492 | else |
|
| 2493 | /* Process Unlocked */ |
2493 | { |
| 2494 | __HAL_UNLOCK(hi2c); |
2494 | /* Update I2C state */ |
| 2495 | 2495 | hi2c->State = HAL_I2C_STATE_LISTEN; |
|
| 2496 | /* Note : The I2C interrupts must be enabled after unlocking current process |
2496 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 2497 | to avoid the risk of I2C interrupt handle execution before current |
2497 | |
| 2498 | process unlock */ |
2498 | /* Update I2C error code */ |
| 2499 | /* Enable EVT and ERR interrupt */ |
2499 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
| 2500 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
2500 | |
| 2501 | 2501 | /* Process Unlocked */ |
|
| 2502 | /* Enable DMA Request */ |
2502 | __HAL_UNLOCK(hi2c); |
| 2503 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
2503 | |
| 2504 | 2504 | return HAL_ERROR; |
|
| 2505 | return HAL_OK; |
2505 | } |
| 2506 | } |
2506 | |
| 2507 | else |
2507 | if (dmaxferstatus == HAL_OK) |
| 2508 | { |
2508 | { |
| 2509 | /* Update I2C state */ |
2509 | /* Enable Address Acknowledge */ |
| 2510 | hi2c->State = HAL_I2C_STATE_READY; |
2510 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 2511 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2511 | |
| 2512 | 2512 | /* Process Unlocked */ |
|
| 2513 | /* Update I2C error code */ |
2513 | __HAL_UNLOCK(hi2c); |
| 2514 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
2514 | |
| 2515 | 2515 | /* Note : The I2C interrupts must be enabled after unlocking current process |
|
| 2516 | /* Process Unlocked */ |
2516 | to avoid the risk of I2C interrupt handle execution before current |
| 2517 | __HAL_UNLOCK(hi2c); |
2517 | process unlock */ |
| 2518 | 2518 | /* Enable EVT and ERR interrupt */ |
|
| 2519 | return HAL_ERROR; |
2519 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 2520 | } |
2520 | |
| 2521 | } |
2521 | /* Enable DMA Request */ |
| 2522 | else |
2522 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 2523 | { |
2523 | |
| 2524 | return HAL_BUSY; |
2524 | return HAL_OK; |
| 2525 | } |
2525 | } |
| 2526 | } |
2526 | else |
| 2527 | 2527 | { |
|
| 2528 | /** |
2528 | /* Update I2C state */ |
| 2529 | * @brief Write an amount of data in blocking mode to a specific memory address |
2529 | hi2c->State = HAL_I2C_STATE_READY; |
| 2530 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
2530 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 2531 | * the configuration information for the specified I2C. |
2531 | |
| 2532 | * @param DevAddress Target device address: The device 7 bits address value |
2532 | /* Update I2C error code */ |
| 2533 | * in datasheet must be shifted to the left before calling the interface |
2533 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
| 2534 | * @param MemAddress Internal memory address |
2534 | |
| 2535 | * @param MemAddSize Size of internal memory address |
2535 | /* Process Unlocked */ |
| 2536 | * @param pData Pointer to data buffer |
2536 | __HAL_UNLOCK(hi2c); |
| 2537 | * @param Size Amount of data to be sent |
2537 | |
| 2538 | * @param Timeout Timeout duration |
2538 | return HAL_ERROR; |
| 2539 | * @retval HAL status |
2539 | } |
| 2540 | */ |
2540 | } |
| 2541 | HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
2541 | else |
| 2542 | { |
2542 | { |
| 2543 | /* Init tickstart for timeout management*/ |
2543 | return HAL_BUSY; |
| 2544 | uint32_t tickstart = HAL_GetTick(); |
2544 | } |
| 2545 | 2545 | } |
|
| 2546 | /* Check the parameters */ |
2546 | |
| 2547 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
2547 | /** |
| 2548 | 2548 | * @brief Write an amount of data in blocking mode to a specific memory address |
|
| 2549 | if (hi2c->State == HAL_I2C_STATE_READY) |
2549 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 2550 | { |
2550 | * the configuration information for the specified I2C. |
| 2551 | /* Wait until BUSY flag is reset */ |
2551 | * @param DevAddress Target device address: The device 7 bits address value |
| 2552 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
2552 | * in datasheet must be shifted to the left before calling the interface |
| 2553 | { |
2553 | * @param MemAddress Internal memory address |
| 2554 | return HAL_BUSY; |
2554 | * @param MemAddSize Size of internal memory address |
| 2555 | } |
2555 | * @param pData Pointer to data buffer |
| 2556 | 2556 | * @param Size Amount of data to be sent |
|
| 2557 | /* Process Locked */ |
2557 | * @param Timeout Timeout duration |
| 2558 | __HAL_LOCK(hi2c); |
2558 | * @retval HAL status |
| 2559 | 2559 | */ |
|
| 2560 | /* Check if the I2C is already enabled */ |
2560 | HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
| 2561 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
2561 | { |
| 2562 | { |
2562 | /* Init tickstart for timeout management*/ |
| 2563 | /* Enable I2C peripheral */ |
2563 | uint32_t tickstart = HAL_GetTick(); |
| 2564 | __HAL_I2C_ENABLE(hi2c); |
2564 | |
| 2565 | } |
2565 | /* Check the parameters */ |
| 2566 | 2566 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
|
| 2567 | /* Disable Pos */ |
2567 | |
| 2568 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
2568 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 2569 | 2569 | { |
|
| 2570 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
2570 | /* Wait until BUSY flag is reset */ |
| 2571 | hi2c->Mode = HAL_I2C_MODE_MEM; |
2571 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
| 2572 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
2572 | { |
| 2573 | 2573 | return HAL_BUSY; |
|
| 2574 | /* Prepare transfer parameters */ |
2574 | } |
| 2575 | hi2c->pBuffPtr = pData; |
2575 | |
| 2576 | hi2c->XferCount = Size; |
2576 | /* Process Locked */ |
| 2577 | hi2c->XferSize = hi2c->XferCount; |
2577 | __HAL_LOCK(hi2c); |
| 2578 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
2578 | |
| 2579 | 2579 | /* Check if the I2C is already enabled */ |
|
| 2580 | /* Send Slave Address and Memory Address */ |
2580 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 2581 | if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
2581 | { |
| 2582 | { |
2582 | /* Enable I2C peripheral */ |
| 2583 | return HAL_ERROR; |
2583 | __HAL_I2C_ENABLE(hi2c); |
| 2584 | } |
2584 | } |
| 2585 | 2585 | ||
| 2586 | while (hi2c->XferSize > 0U) |
2586 | /* Disable Pos */ |
| 2587 | { |
2587 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 2588 | /* Wait until TXE flag is set */ |
2588 | |
| 2589 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
2589 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
| 2590 | { |
2590 | hi2c->Mode = HAL_I2C_MODE_MEM; |
| 2591 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
2591 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 2592 | { |
2592 | |
| 2593 | /* Generate Stop */ |
2593 | /* Prepare transfer parameters */ |
| 2594 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
2594 | hi2c->pBuffPtr = pData; |
| 2595 | } |
2595 | hi2c->XferCount = Size; |
| 2596 | return HAL_ERROR; |
2596 | hi2c->XferSize = hi2c->XferCount; |
| 2597 | } |
2597 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 2598 | 2598 | ||
| 2599 | /* Write data to DR */ |
2599 | /* Send Slave Address and Memory Address */ |
| 2600 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
2600 | if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
| 2601 | 2601 | { |
|
| 2602 | /* Increment Buffer pointer */ |
2602 | return HAL_ERROR; |
| 2603 | hi2c->pBuffPtr++; |
2603 | } |
| 2604 | 2604 | ||
| 2605 | /* Update counter */ |
2605 | while (hi2c->XferSize > 0U) |
| 2606 | hi2c->XferSize--; |
2606 | { |
| 2607 | hi2c->XferCount--; |
2607 | /* Wait until TXE flag is set */ |
| 2608 | 2608 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
|
| 2609 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
2609 | { |
| 2610 | { |
2610 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
| 2611 | /* Write data to DR */ |
2611 | { |
| 2612 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
2612 | /* Generate Stop */ |
| 2613 | 2613 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
|
| 2614 | /* Increment Buffer pointer */ |
2614 | } |
| 2615 | hi2c->pBuffPtr++; |
2615 | return HAL_ERROR; |
| 2616 | 2616 | } |
|
| 2617 | /* Update counter */ |
2617 | |
| 2618 | hi2c->XferSize--; |
2618 | /* Write data to DR */ |
| 2619 | hi2c->XferCount--; |
2619 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
| 2620 | } |
2620 | |
| 2621 | } |
2621 | /* Increment Buffer pointer */ |
| 2622 | 2622 | hi2c->pBuffPtr++; |
|
| 2623 | /* Wait until BTF flag is set */ |
2623 | |
| 2624 | if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
2624 | /* Update counter */ |
| 2625 | { |
2625 | hi2c->XferSize--; |
| 2626 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
2626 | hi2c->XferCount--; |
| 2627 | { |
2627 | |
| 2628 | /* Generate Stop */ |
2628 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (hi2c->XferSize != 0U)) |
| 2629 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
2629 | { |
| 2630 | } |
2630 | /* Write data to DR */ |
| 2631 | return HAL_ERROR; |
2631 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
| 2632 | } |
2632 | |
| 2633 | 2633 | /* Increment Buffer pointer */ |
|
| 2634 | /* Generate Stop */ |
2634 | hi2c->pBuffPtr++; |
| 2635 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
2635 | |
| 2636 | 2636 | /* Update counter */ |
|
| 2637 | hi2c->State = HAL_I2C_STATE_READY; |
2637 | hi2c->XferSize--; |
| 2638 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2638 | hi2c->XferCount--; |
| 2639 | 2639 | } |
|
| 2640 | /* Process Unlocked */ |
2640 | } |
| 2641 | __HAL_UNLOCK(hi2c); |
2641 | |
| 2642 | 2642 | /* Wait until BTF flag is set */ |
|
| 2643 | return HAL_OK; |
2643 | if (I2C_WaitOnBTFFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
| 2644 | } |
2644 | { |
| 2645 | else |
2645 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
| 2646 | { |
2646 | { |
| 2647 | return HAL_BUSY; |
2647 | /* Generate Stop */ |
| 2648 | } |
2648 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 2649 | } |
2649 | } |
| 2650 | 2650 | return HAL_ERROR; |
|
| 2651 | /** |
2651 | } |
| 2652 | * @brief Read an amount of data in blocking mode from a specific memory address |
2652 | |
| 2653 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
2653 | /* Generate Stop */ |
| 2654 | * the configuration information for the specified I2C. |
2654 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 2655 | * @param DevAddress Target device address: The device 7 bits address value |
2655 | |
| 2656 | * in datasheet must be shifted to the left before calling the interface |
2656 | hi2c->State = HAL_I2C_STATE_READY; |
| 2657 | * @param MemAddress Internal memory address |
2657 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 2658 | * @param MemAddSize Size of internal memory address |
2658 | |
| 2659 | * @param pData Pointer to data buffer |
2659 | /* Process Unlocked */ |
| 2660 | * @param Size Amount of data to be sent |
2660 | __HAL_UNLOCK(hi2c); |
| 2661 | * @param Timeout Timeout duration |
2661 | |
| 2662 | * @retval HAL status |
2662 | return HAL_OK; |
| 2663 | */ |
2663 | } |
| 2664 | HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
2664 | else |
| 2665 | { |
2665 | { |
| 2666 | __IO uint32_t count = 0U; |
2666 | return HAL_BUSY; |
| 2667 | 2667 | } |
|
| 2668 | /* Init tickstart for timeout management*/ |
2668 | } |
| 2669 | uint32_t tickstart = HAL_GetTick(); |
2669 | |
| 2670 | 2670 | /** |
|
| 2671 | /* Check the parameters */ |
2671 | * @brief Read an amount of data in blocking mode from a specific memory address |
| 2672 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
2672 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 2673 | 2673 | * the configuration information for the specified I2C. |
|
| 2674 | if (hi2c->State == HAL_I2C_STATE_READY) |
2674 | * @param DevAddress Target device address: The device 7 bits address value |
| 2675 | { |
2675 | * in datasheet must be shifted to the left before calling the interface |
| 2676 | /* Wait until BUSY flag is reset */ |
2676 | * @param MemAddress Internal memory address |
| 2677 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
2677 | * @param MemAddSize Size of internal memory address |
| 2678 | { |
2678 | * @param pData Pointer to data buffer |
| 2679 | return HAL_BUSY; |
2679 | * @param Size Amount of data to be sent |
| 2680 | } |
2680 | * @param Timeout Timeout duration |
| 2681 | 2681 | * @retval HAL status |
|
| 2682 | /* Process Locked */ |
2682 | */ |
| 2683 | __HAL_LOCK(hi2c); |
2683 | HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) |
| 2684 | 2684 | { |
|
| 2685 | /* Check if the I2C is already enabled */ |
2685 | __IO uint32_t count = 0U; |
| 2686 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
2686 | |
| 2687 | { |
2687 | /* Init tickstart for timeout management*/ |
| 2688 | /* Enable I2C peripheral */ |
2688 | uint32_t tickstart = HAL_GetTick(); |
| 2689 | __HAL_I2C_ENABLE(hi2c); |
2689 | |
| 2690 | } |
2690 | /* Check the parameters */ |
| 2691 | 2691 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
|
| 2692 | /* Disable Pos */ |
2692 | |
| 2693 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
2693 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 2694 | 2694 | { |
|
| 2695 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
2695 | /* Wait until BUSY flag is reset */ |
| 2696 | hi2c->Mode = HAL_I2C_MODE_MEM; |
2696 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
| 2697 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
2697 | { |
| 2698 | 2698 | return HAL_BUSY; |
|
| 2699 | /* Prepare transfer parameters */ |
2699 | } |
| 2700 | hi2c->pBuffPtr = pData; |
2700 | |
| 2701 | hi2c->XferCount = Size; |
2701 | /* Process Locked */ |
| 2702 | hi2c->XferSize = hi2c->XferCount; |
2702 | __HAL_LOCK(hi2c); |
| 2703 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
2703 | |
| 2704 | 2704 | /* Check if the I2C is already enabled */ |
|
| 2705 | /* Send Slave Address and Memory Address */ |
2705 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 2706 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
2706 | { |
| 2707 | { |
2707 | /* Enable I2C peripheral */ |
| 2708 | return HAL_ERROR; |
2708 | __HAL_I2C_ENABLE(hi2c); |
| 2709 | } |
2709 | } |
| 2710 | 2710 | ||
| 2711 | if (hi2c->XferSize == 0U) |
2711 | /* Disable Pos */ |
| 2712 | { |
2712 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 2713 | /* Clear ADDR flag */ |
2713 | |
| 2714 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
2714 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
| 2715 | 2715 | hi2c->Mode = HAL_I2C_MODE_MEM; |
|
| 2716 | /* Generate Stop */ |
2716 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 2717 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
2717 | |
| 2718 | } |
2718 | /* Prepare transfer parameters */ |
| 2719 | else if (hi2c->XferSize == 1U) |
2719 | hi2c->pBuffPtr = pData; |
| 2720 | { |
2720 | hi2c->XferCount = Size; |
| 2721 | /* Disable Acknowledge */ |
2721 | hi2c->XferSize = hi2c->XferCount; |
| 2722 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
2722 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 2723 | 2723 | ||
| 2724 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
2724 | /* Send Slave Address and Memory Address */ |
| 2725 | software sequence must complete before the current byte end of transfer */ |
2725 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) |
| 2726 | __disable_irq(); |
2726 | { |
| 2727 | 2727 | return HAL_ERROR; |
|
| 2728 | /* Clear ADDR flag */ |
2728 | } |
| 2729 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
2729 | |
| 2730 | 2730 | if (hi2c->XferSize == 0U) |
|
| 2731 | /* Generate Stop */ |
2731 | { |
| 2732 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
2732 | /* Clear ADDR flag */ |
| 2733 | 2733 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
|
| 2734 | /* Re-enable IRQs */ |
2734 | |
| 2735 | __enable_irq(); |
2735 | /* Generate Stop */ |
| 2736 | } |
2736 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 2737 | else if (hi2c->XferSize == 2U) |
2737 | } |
| 2738 | { |
2738 | else if (hi2c->XferSize == 1U) |
| 2739 | /* Enable Pos */ |
2739 | { |
| 2740 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
2740 | /* Disable Acknowledge */ |
| 2741 | 2741 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
|
| 2742 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
2742 | |
| 2743 | software sequence must complete before the current byte end of transfer */ |
2743 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
| 2744 | __disable_irq(); |
2744 | software sequence must complete before the current byte end of transfer */ |
| 2745 | 2745 | __disable_irq(); |
|
| 2746 | /* Clear ADDR flag */ |
2746 | |
| 2747 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
2747 | /* Clear ADDR flag */ |
| 2748 | 2748 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
|
| 2749 | /* Disable Acknowledge */ |
2749 | |
| 2750 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
2750 | /* Generate Stop */ |
| 2751 | 2751 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
|
| 2752 | /* Re-enable IRQs */ |
2752 | |
| 2753 | __enable_irq(); |
2753 | /* Re-enable IRQs */ |
| 2754 | } |
2754 | __enable_irq(); |
| 2755 | else |
2755 | } |
| 2756 | { |
2756 | else if (hi2c->XferSize == 2U) |
| 2757 | /* Enable Acknowledge */ |
2757 | { |
| 2758 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
2758 | /* Enable Pos */ |
| 2759 | /* Clear ADDR flag */ |
2759 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 2760 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
2760 | |
| 2761 | } |
2761 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
| 2762 | 2762 | software sequence must complete before the current byte end of transfer */ |
|
| 2763 | while (hi2c->XferSize > 0U) |
2763 | __disable_irq(); |
| 2764 | { |
2764 | |
| 2765 | if (hi2c->XferSize <= 3U) |
2765 | /* Clear ADDR flag */ |
| 2766 | { |
2766 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 2767 | /* One byte */ |
2767 | |
| 2768 | if (hi2c->XferSize == 1U) |
2768 | /* Disable Acknowledge */ |
| 2769 | { |
2769 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 2770 | /* Wait until RXNE flag is set */ |
2770 | |
| 2771 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
2771 | /* Re-enable IRQs */ |
| 2772 | { |
2772 | __enable_irq(); |
| 2773 | return HAL_ERROR; |
2773 | } |
| 2774 | } |
2774 | else |
| 2775 | 2775 | { |
|
| 2776 | /* Read data from DR */ |
2776 | /* Enable Acknowledge */ |
| 2777 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
2777 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 2778 | 2778 | /* Clear ADDR flag */ |
|
| 2779 | /* Increment Buffer pointer */ |
2779 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 2780 | hi2c->pBuffPtr++; |
2780 | } |
| 2781 | 2781 | ||
| 2782 | /* Update counter */ |
2782 | while (hi2c->XferSize > 0U) |
| 2783 | hi2c->XferSize--; |
2783 | { |
| 2784 | hi2c->XferCount--; |
2784 | if (hi2c->XferSize <= 3U) |
| 2785 | } |
2785 | { |
| 2786 | /* Two bytes */ |
2786 | /* One byte */ |
| 2787 | else if (hi2c->XferSize == 2U) |
2787 | if (hi2c->XferSize == 1U) |
| 2788 | { |
2788 | { |
| 2789 | /* Wait until BTF flag is set */ |
2789 | /* Wait until RXNE flag is set */ |
| 2790 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
2790 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
| 2791 | { |
2791 | { |
| 2792 | return HAL_ERROR; |
2792 | return HAL_ERROR; |
| 2793 | } |
2793 | } |
| 2794 | 2794 | ||
| 2795 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
2795 | /* Read data from DR */ |
| 2796 | software sequence must complete before the current byte end of transfer */ |
2796 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 2797 | __disable_irq(); |
2797 | |
| 2798 | 2798 | /* Increment Buffer pointer */ |
|
| 2799 | /* Generate Stop */ |
2799 | hi2c->pBuffPtr++; |
| 2800 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
2800 | |
| 2801 | 2801 | /* Update counter */ |
|
| 2802 | /* Read data from DR */ |
2802 | hi2c->XferSize--; |
| 2803 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
2803 | hi2c->XferCount--; |
| 2804 | 2804 | } |
|
| 2805 | /* Increment Buffer pointer */ |
2805 | /* Two bytes */ |
| 2806 | hi2c->pBuffPtr++; |
2806 | else if (hi2c->XferSize == 2U) |
| 2807 | 2807 | { |
|
| 2808 | /* Update counter */ |
2808 | /* Wait until BTF flag is set */ |
| 2809 | hi2c->XferSize--; |
2809 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
| 2810 | hi2c->XferCount--; |
2810 | { |
| 2811 | 2811 | return HAL_ERROR; |
|
| 2812 | /* Re-enable IRQs */ |
2812 | } |
| 2813 | __enable_irq(); |
2813 | |
| 2814 | 2814 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
|
| 2815 | /* Read data from DR */ |
2815 | software sequence must complete before the current byte end of transfer */ |
| 2816 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
2816 | __disable_irq(); |
| 2817 | 2817 | ||
| 2818 | /* Increment Buffer pointer */ |
2818 | /* Generate Stop */ |
| 2819 | hi2c->pBuffPtr++; |
2819 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 2820 | 2820 | ||
| 2821 | /* Update counter */ |
2821 | /* Read data from DR */ |
| 2822 | hi2c->XferSize--; |
2822 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 2823 | hi2c->XferCount--; |
2823 | |
| 2824 | } |
2824 | /* Increment Buffer pointer */ |
| 2825 | /* 3 Last bytes */ |
2825 | hi2c->pBuffPtr++; |
| 2826 | else |
2826 | |
| 2827 | { |
2827 | /* Update counter */ |
| 2828 | /* Wait until BTF flag is set */ |
2828 | hi2c->XferSize--; |
| 2829 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
2829 | hi2c->XferCount--; |
| 2830 | { |
2830 | |
| 2831 | return HAL_ERROR; |
2831 | /* Re-enable IRQs */ |
| 2832 | } |
2832 | __enable_irq(); |
| 2833 | 2833 | ||
| 2834 | /* Disable Acknowledge */ |
2834 | /* Read data from DR */ |
| 2835 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
2835 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 2836 | 2836 | ||
| 2837 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
2837 | /* Increment Buffer pointer */ |
| 2838 | software sequence must complete before the current byte end of transfer */ |
2838 | hi2c->pBuffPtr++; |
| 2839 | __disable_irq(); |
2839 | |
| 2840 | 2840 | /* Update counter */ |
|
| 2841 | /* Read data from DR */ |
2841 | hi2c->XferSize--; |
| 2842 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
2842 | hi2c->XferCount--; |
| 2843 | 2843 | } |
|
| 2844 | /* Increment Buffer pointer */ |
2844 | /* 3 Last bytes */ |
| 2845 | hi2c->pBuffPtr++; |
2845 | else |
| 2846 | 2846 | { |
|
| 2847 | /* Update counter */ |
2847 | /* Wait until BTF flag is set */ |
| 2848 | hi2c->XferSize--; |
2848 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout, tickstart) != HAL_OK) |
| 2849 | hi2c->XferCount--; |
2849 | { |
| 2850 | 2850 | return HAL_ERROR; |
|
| 2851 | /* Wait until BTF flag is set */ |
2851 | } |
| 2852 | count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); |
2852 | |
| 2853 | do |
2853 | /* Disable Acknowledge */ |
| 2854 | { |
2854 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 2855 | count--; |
2855 | |
| 2856 | if (count == 0U) |
2856 | /* Disable all active IRQs around ADDR clearing and STOP programming because the EV6_3 |
| 2857 | { |
2857 | software sequence must complete before the current byte end of transfer */ |
| 2858 | hi2c->PreviousState = I2C_STATE_NONE; |
2858 | __disable_irq(); |
| 2859 | hi2c->State = HAL_I2C_STATE_READY; |
2859 | |
| 2860 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2860 | /* Read data from DR */ |
| 2861 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
2861 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 2862 | 2862 | ||
| 2863 | /* Re-enable IRQs */ |
2863 | /* Increment Buffer pointer */ |
| 2864 | __enable_irq(); |
2864 | hi2c->pBuffPtr++; |
| 2865 | 2865 | ||
| 2866 | /* Process Unlocked */ |
2866 | /* Update counter */ |
| 2867 | __HAL_UNLOCK(hi2c); |
2867 | hi2c->XferSize--; |
| 2868 | 2868 | hi2c->XferCount--; |
|
| 2869 | return HAL_ERROR; |
2869 | |
| 2870 | } |
2870 | /* Wait until BTF flag is set */ |
| 2871 | } |
2871 | count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); |
| 2872 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); |
2872 | do |
| 2873 | 2873 | { |
|
| 2874 | /* Generate Stop */ |
2874 | count--; |
| 2875 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
2875 | if (count == 0U) |
| 2876 | 2876 | { |
|
| 2877 | /* Read data from DR */ |
2877 | hi2c->PreviousState = I2C_STATE_NONE; |
| 2878 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
2878 | hi2c->State = HAL_I2C_STATE_READY; |
| 2879 | 2879 | hi2c->Mode = HAL_I2C_MODE_NONE; |
|
| 2880 | /* Increment Buffer pointer */ |
2880 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 2881 | hi2c->pBuffPtr++; |
2881 | |
| 2882 | 2882 | /* Re-enable IRQs */ |
|
| 2883 | /* Update counter */ |
2883 | __enable_irq(); |
| 2884 | hi2c->XferSize--; |
2884 | |
| 2885 | hi2c->XferCount--; |
2885 | /* Process Unlocked */ |
| 2886 | 2886 | __HAL_UNLOCK(hi2c); |
|
| 2887 | /* Re-enable IRQs */ |
2887 | |
| 2888 | __enable_irq(); |
2888 | return HAL_ERROR; |
| 2889 | 2889 | } |
|
| 2890 | /* Read data from DR */ |
2890 | } |
| 2891 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
2891 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET); |
| 2892 | 2892 | ||
| 2893 | /* Increment Buffer pointer */ |
2893 | /* Generate Stop */ |
| 2894 | hi2c->pBuffPtr++; |
2894 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 2895 | 2895 | ||
| 2896 | /* Update counter */ |
2896 | /* Read data from DR */ |
| 2897 | hi2c->XferSize--; |
2897 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 2898 | hi2c->XferCount--; |
2898 | |
| 2899 | } |
2899 | /* Increment Buffer pointer */ |
| 2900 | } |
2900 | hi2c->pBuffPtr++; |
| 2901 | else |
2901 | |
| 2902 | { |
2902 | /* Update counter */ |
| 2903 | /* Wait until RXNE flag is set */ |
2903 | hi2c->XferSize--; |
| 2904 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
2904 | hi2c->XferCount--; |
| 2905 | { |
2905 | |
| 2906 | return HAL_ERROR; |
2906 | /* Re-enable IRQs */ |
| 2907 | } |
2907 | __enable_irq(); |
| 2908 | 2908 | ||
| 2909 | /* Read data from DR */ |
2909 | /* Read data from DR */ |
| 2910 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
2910 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 2911 | 2911 | ||
| 2912 | /* Increment Buffer pointer */ |
2912 | /* Increment Buffer pointer */ |
| 2913 | hi2c->pBuffPtr++; |
2913 | hi2c->pBuffPtr++; |
| 2914 | 2914 | ||
| 2915 | /* Update counter */ |
2915 | /* Update counter */ |
| 2916 | hi2c->XferSize--; |
2916 | hi2c->XferSize--; |
| 2917 | hi2c->XferCount--; |
2917 | hi2c->XferCount--; |
| 2918 | 2918 | } |
|
| 2919 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
2919 | } |
| 2920 | { |
2920 | else |
| 2921 | /* Read data from DR */ |
2921 | { |
| 2922 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
2922 | /* Wait until RXNE flag is set */ |
| 2923 | 2923 | if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) |
|
| 2924 | /* Increment Buffer pointer */ |
2924 | { |
| 2925 | hi2c->pBuffPtr++; |
2925 | return HAL_ERROR; |
| 2926 | 2926 | } |
|
| 2927 | /* Update counter */ |
2927 | |
| 2928 | hi2c->XferSize--; |
2928 | /* Read data from DR */ |
| 2929 | hi2c->XferCount--; |
2929 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 2930 | } |
2930 | |
| 2931 | } |
2931 | /* Increment Buffer pointer */ |
| 2932 | } |
2932 | hi2c->pBuffPtr++; |
| 2933 | 2933 | ||
| 2934 | hi2c->State = HAL_I2C_STATE_READY; |
2934 | /* Update counter */ |
| 2935 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2935 | hi2c->XferSize--; |
| 2936 | 2936 | hi2c->XferCount--; |
|
| 2937 | /* Process Unlocked */ |
2937 | |
| 2938 | __HAL_UNLOCK(hi2c); |
2938 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
| 2939 | 2939 | { |
|
| 2940 | return HAL_OK; |
2940 | /* Read data from DR */ |
| 2941 | } |
2941 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 2942 | else |
2942 | |
| 2943 | { |
2943 | /* Increment Buffer pointer */ |
| 2944 | return HAL_BUSY; |
2944 | hi2c->pBuffPtr++; |
| 2945 | } |
2945 | |
| 2946 | } |
2946 | /* Update counter */ |
| 2947 | 2947 | hi2c->XferSize--; |
|
| 2948 | /** |
2948 | hi2c->XferCount--; |
| 2949 | * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address |
2949 | } |
| 2950 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
2950 | } |
| 2951 | * the configuration information for the specified I2C. |
2951 | } |
| 2952 | * @param DevAddress Target device address: The device 7 bits address value |
2952 | |
| 2953 | * in datasheet must be shifted to the left before calling the interface |
2953 | hi2c->State = HAL_I2C_STATE_READY; |
| 2954 | * @param MemAddress Internal memory address |
2954 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 2955 | * @param MemAddSize Size of internal memory address |
2955 | |
| 2956 | * @param pData Pointer to data buffer |
2956 | /* Process Unlocked */ |
| 2957 | * @param Size Amount of data to be sent |
2957 | __HAL_UNLOCK(hi2c); |
| 2958 | * @retval HAL status |
2958 | |
| 2959 | */ |
2959 | return HAL_OK; |
| 2960 | HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
2960 | } |
| 2961 | { |
2961 | else |
| 2962 | __IO uint32_t count = 0U; |
2962 | { |
| 2963 | 2963 | return HAL_BUSY; |
|
| 2964 | /* Check the parameters */ |
2964 | } |
| 2965 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
2965 | } |
| 2966 | 2966 | ||
| 2967 | if (hi2c->State == HAL_I2C_STATE_READY) |
2967 | /** |
| 2968 | { |
2968 | * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address |
| 2969 | /* Wait until BUSY flag is reset */ |
2969 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 2970 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
2970 | * the configuration information for the specified I2C. |
| 2971 | do |
2971 | * @param DevAddress Target device address: The device 7 bits address value |
| 2972 | { |
2972 | * in datasheet must be shifted to the left before calling the interface |
| 2973 | count--; |
2973 | * @param MemAddress Internal memory address |
| 2974 | if (count == 0U) |
2974 | * @param MemAddSize Size of internal memory address |
| 2975 | { |
2975 | * @param pData Pointer to data buffer |
| 2976 | hi2c->PreviousState = I2C_STATE_NONE; |
2976 | * @param Size Amount of data to be sent |
| 2977 | hi2c->State = HAL_I2C_STATE_READY; |
2977 | * @retval HAL status |
| 2978 | hi2c->Mode = HAL_I2C_MODE_NONE; |
2978 | */ |
| 2979 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
2979 | HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
| 2980 | 2980 | { |
|
| 2981 | /* Process Unlocked */ |
2981 | __IO uint32_t count = 0U; |
| 2982 | __HAL_UNLOCK(hi2c); |
2982 | |
| 2983 | 2983 | /* Check the parameters */ |
|
| 2984 | return HAL_ERROR; |
2984 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
| 2985 | } |
2985 | |
| 2986 | } |
2986 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 2987 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
2987 | { |
| 2988 | 2988 | /* Wait until BUSY flag is reset */ |
|
| 2989 | /* Process Locked */ |
2989 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
| 2990 | __HAL_LOCK(hi2c); |
2990 | do |
| 2991 | 2991 | { |
|
| 2992 | /* Check if the I2C is already enabled */ |
2992 | count--; |
| 2993 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
2993 | if (count == 0U) |
| 2994 | { |
2994 | { |
| 2995 | /* Enable I2C peripheral */ |
2995 | hi2c->PreviousState = I2C_STATE_NONE; |
| 2996 | __HAL_I2C_ENABLE(hi2c); |
2996 | hi2c->State = HAL_I2C_STATE_READY; |
| 2997 | } |
2997 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 2998 | 2998 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
|
| 2999 | /* Disable Pos */ |
2999 | |
| 3000 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
3000 | return HAL_BUSY; |
| 3001 | 3001 | } |
|
| 3002 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
3002 | } |
| 3003 | hi2c->Mode = HAL_I2C_MODE_MEM; |
3003 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
| 3004 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
3004 | |
| 3005 | 3005 | /* Process Locked */ |
|
| 3006 | /* Prepare transfer parameters */ |
3006 | __HAL_LOCK(hi2c); |
| 3007 | hi2c->pBuffPtr = pData; |
3007 | |
| 3008 | hi2c->XferCount = Size; |
3008 | /* Check if the I2C is already enabled */ |
| 3009 | hi2c->XferSize = hi2c->XferCount; |
3009 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 3010 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
3010 | { |
| 3011 | hi2c->Devaddress = DevAddress; |
3011 | /* Enable I2C peripheral */ |
| 3012 | hi2c->Memaddress = MemAddress; |
3012 | __HAL_I2C_ENABLE(hi2c); |
| 3013 | hi2c->MemaddSize = MemAddSize; |
3013 | } |
| 3014 | hi2c->EventCount = 0U; |
3014 | |
| 3015 | 3015 | /* Disable Pos */ |
|
| 3016 | /* Generate Start */ |
3016 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 3017 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
3017 | |
| 3018 | 3018 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
|
| 3019 | /* Process Unlocked */ |
3019 | hi2c->Mode = HAL_I2C_MODE_MEM; |
| 3020 | __HAL_UNLOCK(hi2c); |
3020 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 3021 | 3021 | ||
| 3022 | /* Note : The I2C interrupts must be enabled after unlocking current process |
3022 | /* Prepare transfer parameters */ |
| 3023 | to avoid the risk of I2C interrupt handle execution before current |
3023 | hi2c->pBuffPtr = pData; |
| 3024 | process unlock */ |
3024 | hi2c->XferCount = Size; |
| 3025 | 3025 | hi2c->XferSize = hi2c->XferCount; |
|
| 3026 | /* Enable EVT, BUF and ERR interrupt */ |
3026 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 3027 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
3027 | hi2c->Devaddress = DevAddress; |
| 3028 | 3028 | hi2c->Memaddress = MemAddress; |
|
| 3029 | return HAL_OK; |
3029 | hi2c->MemaddSize = MemAddSize; |
| 3030 | } |
3030 | hi2c->EventCount = 0U; |
| 3031 | else |
3031 | |
| 3032 | { |
3032 | /* Generate Start */ |
| 3033 | return HAL_BUSY; |
3033 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 3034 | } |
3034 | |
| 3035 | } |
3035 | /* Process Unlocked */ |
| 3036 | 3036 | __HAL_UNLOCK(hi2c); |
|
| 3037 | /** |
3037 | |
| 3038 | * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address |
3038 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 3039 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
3039 | to avoid the risk of I2C interrupt handle execution before current |
| 3040 | * the configuration information for the specified I2C. |
3040 | process unlock */ |
| 3041 | * @param DevAddress Target device address |
3041 | |
| 3042 | * @param MemAddress Internal memory address |
3042 | /* Enable EVT, BUF and ERR interrupt */ |
| 3043 | * @param MemAddSize Size of internal memory address |
3043 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 3044 | * @param pData Pointer to data buffer |
3044 | |
| 3045 | * @param Size Amount of data to be sent |
3045 | return HAL_OK; |
| 3046 | * @retval HAL status |
3046 | } |
| 3047 | */ |
3047 | else |
| 3048 | HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
3048 | { |
| 3049 | { |
3049 | return HAL_BUSY; |
| 3050 | __IO uint32_t count = 0U; |
3050 | } |
| 3051 | 3051 | } |
|
| 3052 | /* Check the parameters */ |
3052 | |
| 3053 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
3053 | /** |
| 3054 | 3054 | * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address |
|
| 3055 | if (hi2c->State == HAL_I2C_STATE_READY) |
3055 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 3056 | { |
3056 | * the configuration information for the specified I2C. |
| 3057 | /* Wait until BUSY flag is reset */ |
3057 | * @param DevAddress Target device address |
| 3058 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
3058 | * @param MemAddress Internal memory address |
| 3059 | do |
3059 | * @param MemAddSize Size of internal memory address |
| 3060 | { |
3060 | * @param pData Pointer to data buffer |
| 3061 | count--; |
3061 | * @param Size Amount of data to be sent |
| 3062 | if (count == 0U) |
3062 | * @retval HAL status |
| 3063 | { |
3063 | */ |
| 3064 | hi2c->PreviousState = I2C_STATE_NONE; |
3064 | HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
| 3065 | hi2c->State = HAL_I2C_STATE_READY; |
3065 | { |
| 3066 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3066 | __IO uint32_t count = 0U; |
| 3067 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
3067 | |
| 3068 | 3068 | /* Check the parameters */ |
|
| 3069 | /* Process Unlocked */ |
3069 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
| 3070 | __HAL_UNLOCK(hi2c); |
3070 | |
| 3071 | 3071 | if (hi2c->State == HAL_I2C_STATE_READY) |
|
| 3072 | return HAL_ERROR; |
3072 | { |
| 3073 | } |
3073 | /* Wait until BUSY flag is reset */ |
| 3074 | } |
3074 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
| 3075 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
3075 | do |
| 3076 | 3076 | { |
|
| 3077 | /* Process Locked */ |
3077 | count--; |
| 3078 | __HAL_LOCK(hi2c); |
3078 | if (count == 0U) |
| 3079 | 3079 | { |
|
| 3080 | /* Check if the I2C is already enabled */ |
3080 | hi2c->PreviousState = I2C_STATE_NONE; |
| 3081 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
3081 | hi2c->State = HAL_I2C_STATE_READY; |
| 3082 | { |
3082 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3083 | /* Enable I2C peripheral */ |
3083 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 3084 | __HAL_I2C_ENABLE(hi2c); |
3084 | |
| 3085 | } |
3085 | return HAL_BUSY; |
| 3086 | 3086 | } |
|
| 3087 | /* Disable Pos */ |
3087 | } |
| 3088 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
3088 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
| 3089 | 3089 | ||
| 3090 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
3090 | /* Process Locked */ |
| 3091 | hi2c->Mode = HAL_I2C_MODE_MEM; |
3091 | __HAL_LOCK(hi2c); |
| 3092 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
3092 | |
| 3093 | 3093 | /* Check if the I2C is already enabled */ |
|
| 3094 | /* Prepare transfer parameters */ |
3094 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 3095 | hi2c->pBuffPtr = pData; |
3095 | { |
| 3096 | hi2c->XferCount = Size; |
3096 | /* Enable I2C peripheral */ |
| 3097 | hi2c->XferSize = hi2c->XferCount; |
3097 | __HAL_I2C_ENABLE(hi2c); |
| 3098 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
3098 | } |
| 3099 | hi2c->Devaddress = DevAddress; |
3099 | |
| 3100 | hi2c->Memaddress = MemAddress; |
3100 | /* Disable Pos */ |
| 3101 | hi2c->MemaddSize = MemAddSize; |
3101 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 3102 | hi2c->EventCount = 0U; |
3102 | |
| 3103 | 3103 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
|
| 3104 | /* Enable Acknowledge */ |
3104 | hi2c->Mode = HAL_I2C_MODE_MEM; |
| 3105 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
3105 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 3106 | 3106 | ||
| 3107 | /* Generate Start */ |
3107 | /* Prepare transfer parameters */ |
| 3108 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
3108 | hi2c->pBuffPtr = pData; |
| 3109 | 3109 | hi2c->XferCount = Size; |
|
| 3110 | /* Process Unlocked */ |
3110 | hi2c->XferSize = hi2c->XferCount; |
| 3111 | __HAL_UNLOCK(hi2c); |
3111 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 3112 | 3112 | hi2c->Devaddress = DevAddress; |
|
| 3113 | if (hi2c->XferSize > 0U) |
3113 | hi2c->Memaddress = MemAddress; |
| 3114 | { |
3114 | hi2c->MemaddSize = MemAddSize; |
| 3115 | /* Note : The I2C interrupts must be enabled after unlocking current process |
3115 | hi2c->EventCount = 0U; |
| 3116 | to avoid the risk of I2C interrupt handle execution before current |
3116 | |
| 3117 | process unlock */ |
3117 | /* Enable Acknowledge */ |
| 3118 | 3118 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
|
| 3119 | /* Enable EVT, BUF and ERR interrupt */ |
3119 | |
| 3120 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
3120 | /* Generate Start */ |
| 3121 | } |
3121 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 3122 | return HAL_OK; |
3122 | |
| 3123 | } |
3123 | /* Process Unlocked */ |
| 3124 | else |
3124 | __HAL_UNLOCK(hi2c); |
| 3125 | { |
3125 | |
| 3126 | return HAL_BUSY; |
3126 | if (hi2c->XferSize > 0U) |
| 3127 | } |
3127 | { |
| 3128 | } |
3128 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 3129 | 3129 | to avoid the risk of I2C interrupt handle execution before current |
|
| 3130 | /** |
3130 | process unlock */ |
| 3131 | * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address |
3131 | |
| 3132 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
3132 | /* Enable EVT, BUF and ERR interrupt */ |
| 3133 | * the configuration information for the specified I2C. |
3133 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 3134 | * @param DevAddress Target device address: The device 7 bits address value |
3134 | } |
| 3135 | * in datasheet must be shifted to the left before calling the interface |
3135 | return HAL_OK; |
| 3136 | * @param MemAddress Internal memory address |
3136 | } |
| 3137 | * @param MemAddSize Size of internal memory address |
3137 | else |
| 3138 | * @param pData Pointer to data buffer |
3138 | { |
| 3139 | * @param Size Amount of data to be sent |
3139 | return HAL_BUSY; |
| 3140 | * @retval HAL status |
3140 | } |
| 3141 | */ |
3141 | } |
| 3142 | HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
3142 | |
| 3143 | { |
3143 | /** |
| 3144 | __IO uint32_t count = 0U; |
3144 | * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address |
| 3145 | HAL_StatusTypeDef dmaxferstatus; |
3145 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 3146 | 3146 | * the configuration information for the specified I2C. |
|
| 3147 | /* Init tickstart for timeout management*/ |
3147 | * @param DevAddress Target device address: The device 7 bits address value |
| 3148 | uint32_t tickstart = HAL_GetTick(); |
3148 | * in datasheet must be shifted to the left before calling the interface |
| 3149 | 3149 | * @param MemAddress Internal memory address |
|
| 3150 | /* Check the parameters */ |
3150 | * @param MemAddSize Size of internal memory address |
| 3151 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
3151 | * @param pData Pointer to data buffer |
| 3152 | 3152 | * @param Size Amount of data to be sent |
|
| 3153 | if (hi2c->State == HAL_I2C_STATE_READY) |
3153 | * @retval HAL status |
| 3154 | { |
3154 | */ |
| 3155 | /* Wait until BUSY flag is reset */ |
3155 | HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
| 3156 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
3156 | { |
| 3157 | do |
3157 | __IO uint32_t count = 0U; |
| 3158 | { |
3158 | HAL_StatusTypeDef dmaxferstatus; |
| 3159 | count--; |
3159 | |
| 3160 | if (count == 0U) |
3160 | /* Init tickstart for timeout management*/ |
| 3161 | { |
3161 | uint32_t tickstart = HAL_GetTick(); |
| 3162 | hi2c->PreviousState = I2C_STATE_NONE; |
3162 | |
| 3163 | hi2c->State = HAL_I2C_STATE_READY; |
3163 | /* Check the parameters */ |
| 3164 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3164 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
| 3165 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
3165 | |
| 3166 | 3166 | if (hi2c->State == HAL_I2C_STATE_READY) |
|
| 3167 | /* Process Unlocked */ |
3167 | { |
| 3168 | __HAL_UNLOCK(hi2c); |
3168 | /* Wait until BUSY flag is reset */ |
| 3169 | 3169 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
|
| 3170 | return HAL_ERROR; |
3170 | do |
| 3171 | } |
3171 | { |
| 3172 | } |
3172 | count--; |
| 3173 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
3173 | if (count == 0U) |
| 3174 | 3174 | { |
|
| 3175 | /* Process Locked */ |
3175 | hi2c->PreviousState = I2C_STATE_NONE; |
| 3176 | __HAL_LOCK(hi2c); |
3176 | hi2c->State = HAL_I2C_STATE_READY; |
| 3177 | 3177 | hi2c->Mode = HAL_I2C_MODE_NONE; |
|
| 3178 | /* Check if the I2C is already enabled */ |
3178 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 3179 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
3179 | |
| 3180 | { |
3180 | return HAL_BUSY; |
| 3181 | /* Enable I2C peripheral */ |
3181 | } |
| 3182 | __HAL_I2C_ENABLE(hi2c); |
3182 | } |
| 3183 | } |
3183 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
| 3184 | 3184 | ||
| 3185 | /* Disable Pos */ |
3185 | /* Process Locked */ |
| 3186 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
3186 | __HAL_LOCK(hi2c); |
| 3187 | 3187 | ||
| 3188 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
3188 | /* Check if the I2C is already enabled */ |
| 3189 | hi2c->Mode = HAL_I2C_MODE_MEM; |
3189 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 3190 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
3190 | { |
| 3191 | 3191 | /* Enable I2C peripheral */ |
|
| 3192 | /* Prepare transfer parameters */ |
3192 | __HAL_I2C_ENABLE(hi2c); |
| 3193 | hi2c->pBuffPtr = pData; |
3193 | } |
| 3194 | hi2c->XferCount = Size; |
3194 | |
| 3195 | hi2c->XferSize = hi2c->XferCount; |
3195 | /* Disable Pos */ |
| 3196 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
3196 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 3197 | 3197 | ||
| 3198 | if (hi2c->XferSize > 0U) |
3198 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
| 3199 | { |
3199 | hi2c->Mode = HAL_I2C_MODE_MEM; |
| 3200 | if (hi2c->hdmatx != NULL) |
3200 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 3201 | { |
3201 | |
| 3202 | /* Set the I2C DMA transfer complete callback */ |
3202 | /* Prepare transfer parameters */ |
| 3203 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
3203 | hi2c->pBuffPtr = pData; |
| 3204 | 3204 | hi2c->XferCount = Size; |
|
| 3205 | /* Set the DMA error callback */ |
3205 | hi2c->XferSize = hi2c->XferCount; |
| 3206 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
3206 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 3207 | 3207 | hi2c->Devaddress = DevAddress; |
|
| 3208 | /* Set the unused DMA callbacks to NULL */ |
3208 | hi2c->Memaddress = MemAddress; |
| 3209 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
3209 | hi2c->MemaddSize = MemAddSize; |
| 3210 | hi2c->hdmatx->XferAbortCallback = NULL; |
3210 | hi2c->EventCount = 0U; |
| 3211 | 3211 | ||
| 3212 | /* Enable the DMA channel */ |
3212 | if (hi2c->XferSize > 0U) |
| 3213 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
3213 | { |
| 3214 | } |
3214 | if (hi2c->hdmatx != NULL) |
| 3215 | else |
3215 | { |
| 3216 | { |
3216 | /* Set the I2C DMA transfer complete callback */ |
| 3217 | /* Update I2C state */ |
3217 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
| 3218 | hi2c->State = HAL_I2C_STATE_READY; |
3218 | |
| 3219 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3219 | /* Set the DMA error callback */ |
| 3220 | 3220 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
|
| 3221 | /* Update I2C error code */ |
3221 | |
| 3222 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
3222 | /* Set the unused DMA callbacks to NULL */ |
| 3223 | 3223 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
|
| 3224 | /* Process Unlocked */ |
3224 | hi2c->hdmatx->XferAbortCallback = NULL; |
| 3225 | __HAL_UNLOCK(hi2c); |
3225 | |
| 3226 | 3226 | /* Enable the DMA channel */ |
|
| 3227 | return HAL_ERROR; |
3227 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
| 3228 | } |
3228 | } |
| 3229 | 3229 | else |
|
| 3230 | if (dmaxferstatus == HAL_OK) |
3230 | { |
| 3231 | { |
3231 | /* Update I2C state */ |
| 3232 | /* Send Slave Address and Memory Address */ |
3232 | hi2c->State = HAL_I2C_STATE_READY; |
| 3233 | if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
3233 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3234 | { |
3234 | |
| 3235 | /* Abort the ongoing DMA */ |
3235 | /* Update I2C error code */ |
| 3236 | dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx); |
3236 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
| 3237 | 3237 | ||
| 3238 | /* Prevent unused argument(s) compilation and MISRA warning */ |
3238 | /* Process Unlocked */ |
| 3239 | UNUSED(dmaxferstatus); |
3239 | __HAL_UNLOCK(hi2c); |
| 3240 | 3240 | ||
| 3241 | /* Set the unused I2C DMA transfer complete callback to NULL */ |
3241 | return HAL_ERROR; |
| 3242 | hi2c->hdmatx->XferCpltCallback = NULL; |
3242 | } |
| 3243 | 3243 | ||
| 3244 | /* Disable Acknowledge */ |
3244 | if (dmaxferstatus == HAL_OK) |
| 3245 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
3245 | { |
| 3246 | 3246 | /* Send Slave Address and Memory Address */ |
|
| 3247 | hi2c->XferSize = 0U; |
3247 | if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
| 3248 | hi2c->XferCount = 0U; |
3248 | { |
| 3249 | 3249 | /* Abort the ongoing DMA */ |
|
| 3250 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
3250 | dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmatx); |
| 3251 | __HAL_I2C_DISABLE(hi2c); |
3251 | |
| 3252 | 3252 | /* Prevent unused argument(s) compilation and MISRA warning */ |
|
| 3253 | return HAL_ERROR; |
3253 | UNUSED(dmaxferstatus); |
| 3254 | } |
3254 | |
| 3255 | 3255 | /* Set the unused I2C DMA transfer complete callback to NULL */ |
|
| 3256 | /* Clear ADDR flag */ |
3256 | hi2c->hdmatx->XferCpltCallback = NULL; |
| 3257 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
3257 | |
| 3258 | 3258 | /* Disable Acknowledge */ |
|
| 3259 | /* Process Unlocked */ |
3259 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 3260 | __HAL_UNLOCK(hi2c); |
3260 | |
| 3261 | 3261 | hi2c->XferSize = 0U; |
|
| 3262 | /* Note : The I2C interrupts must be enabled after unlocking current process |
3262 | hi2c->XferCount = 0U; |
| 3263 | to avoid the risk of I2C interrupt handle execution before current |
3263 | |
| 3264 | process unlock */ |
3264 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
| 3265 | /* Enable ERR interrupt */ |
3265 | __HAL_I2C_DISABLE(hi2c); |
| 3266 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); |
3266 | |
| 3267 | 3267 | return HAL_ERROR; |
|
| 3268 | /* Enable DMA Request */ |
3268 | } |
| 3269 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
3269 | |
| 3270 | 3270 | /* Clear ADDR flag */ |
|
| 3271 | return HAL_OK; |
3271 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 3272 | } |
3272 | |
| 3273 | else |
3273 | /* Process Unlocked */ |
| 3274 | { |
3274 | __HAL_UNLOCK(hi2c); |
| 3275 | /* Update I2C state */ |
3275 | |
| 3276 | hi2c->State = HAL_I2C_STATE_READY; |
3276 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 3277 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3277 | to avoid the risk of I2C interrupt handle execution before current |
| 3278 | 3278 | process unlock */ |
|
| 3279 | /* Update I2C error code */ |
3279 | /* Enable ERR interrupt */ |
| 3280 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
3280 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); |
| 3281 | 3281 | ||
| 3282 | /* Process Unlocked */ |
3282 | /* Enable DMA Request */ |
| 3283 | __HAL_UNLOCK(hi2c); |
3283 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 3284 | 3284 | ||
| 3285 | return HAL_ERROR; |
3285 | return HAL_OK; |
| 3286 | } |
3286 | } |
| 3287 | } |
3287 | else |
| 3288 | else |
3288 | { |
| 3289 | { |
3289 | /* Update I2C state */ |
| 3290 | /* Update I2C state */ |
3290 | hi2c->State = HAL_I2C_STATE_READY; |
| 3291 | hi2c->State = HAL_I2C_STATE_READY; |
3291 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3292 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3292 | |
| 3293 | 3293 | /* Update I2C error code */ |
|
| 3294 | /* Update I2C error code */ |
3294 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
| 3295 | hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; |
3295 | |
| 3296 | 3296 | /* Process Unlocked */ |
|
| 3297 | /* Process Unlocked */ |
3297 | __HAL_UNLOCK(hi2c); |
| 3298 | __HAL_UNLOCK(hi2c); |
3298 | |
| 3299 | 3299 | return HAL_ERROR; |
|
| 3300 | return HAL_ERROR; |
3300 | } |
| 3301 | } |
3301 | } |
| 3302 | } |
3302 | else |
| 3303 | else |
3303 | { |
| 3304 | { |
3304 | /* Update I2C state */ |
| 3305 | return HAL_BUSY; |
3305 | hi2c->State = HAL_I2C_STATE_READY; |
| 3306 | } |
3306 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3307 | } |
3307 | |
| 3308 | 3308 | /* Update I2C error code */ |
|
| 3309 | /** |
3309 | hi2c->ErrorCode |= HAL_I2C_ERROR_SIZE; |
| 3310 | * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. |
3310 | |
| 3311 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
3311 | /* Process Unlocked */ |
| 3312 | * the configuration information for the specified I2C. |
3312 | __HAL_UNLOCK(hi2c); |
| 3313 | * @param DevAddress Target device address: The device 7 bits address value |
3313 | |
| 3314 | * in datasheet must be shifted to the left before calling the interface |
3314 | return HAL_ERROR; |
| 3315 | * @param MemAddress Internal memory address |
3315 | } |
| 3316 | * @param MemAddSize Size of internal memory address |
3316 | } |
| 3317 | * @param pData Pointer to data buffer |
3317 | else |
| 3318 | * @param Size Amount of data to be read |
3318 | { |
| 3319 | * @retval HAL status |
3319 | return HAL_BUSY; |
| 3320 | */ |
3320 | } |
| 3321 | HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
3321 | } |
| 3322 | { |
3322 | |
| 3323 | /* Init tickstart for timeout management*/ |
3323 | /** |
| 3324 | uint32_t tickstart = HAL_GetTick(); |
3324 | * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. |
| 3325 | __IO uint32_t count = 0U; |
3325 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 3326 | HAL_StatusTypeDef dmaxferstatus; |
3326 | * the configuration information for the specified I2C. |
| 3327 | 3327 | * @param DevAddress Target device address: The device 7 bits address value |
|
| 3328 | /* Check the parameters */ |
3328 | * in datasheet must be shifted to the left before calling the interface |
| 3329 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
3329 | * @param MemAddress Internal memory address |
| 3330 | 3330 | * @param MemAddSize Size of internal memory address |
|
| 3331 | if (hi2c->State == HAL_I2C_STATE_READY) |
3331 | * @param pData Pointer to data buffer |
| 3332 | { |
3332 | * @param Size Amount of data to be read |
| 3333 | /* Wait until BUSY flag is reset */ |
3333 | * @retval HAL status |
| 3334 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
3334 | */ |
| 3335 | do |
3335 | HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size) |
| 3336 | { |
3336 | { |
| 3337 | count--; |
3337 | /* Init tickstart for timeout management*/ |
| 3338 | if (count == 0U) |
3338 | uint32_t tickstart = HAL_GetTick(); |
| 3339 | { |
3339 | __IO uint32_t count = 0U; |
| 3340 | hi2c->PreviousState = I2C_STATE_NONE; |
3340 | HAL_StatusTypeDef dmaxferstatus; |
| 3341 | hi2c->State = HAL_I2C_STATE_READY; |
3341 | |
| 3342 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3342 | /* Check the parameters */ |
| 3343 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
3343 | assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); |
| 3344 | 3344 | ||
| 3345 | /* Process Unlocked */ |
3345 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 3346 | __HAL_UNLOCK(hi2c); |
3346 | { |
| 3347 | 3347 | /* Wait until BUSY flag is reset */ |
|
| 3348 | return HAL_ERROR; |
3348 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
| 3349 | } |
3349 | do |
| 3350 | } |
3350 | { |
| 3351 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
3351 | count--; |
| 3352 | 3352 | if (count == 0U) |
|
| 3353 | /* Process Locked */ |
3353 | { |
| 3354 | __HAL_LOCK(hi2c); |
3354 | hi2c->PreviousState = I2C_STATE_NONE; |
| 3355 | 3355 | hi2c->State = HAL_I2C_STATE_READY; |
|
| 3356 | /* Check if the I2C is already enabled */ |
3356 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3357 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
3357 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 3358 | { |
3358 | |
| 3359 | /* Enable I2C peripheral */ |
3359 | return HAL_BUSY; |
| 3360 | __HAL_I2C_ENABLE(hi2c); |
3360 | } |
| 3361 | } |
3361 | } |
| 3362 | 3362 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
|
| 3363 | /* Disable Pos */ |
3363 | |
| 3364 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
3364 | /* Process Locked */ |
| 3365 | 3365 | __HAL_LOCK(hi2c); |
|
| 3366 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
3366 | |
| 3367 | hi2c->Mode = HAL_I2C_MODE_MEM; |
3367 | /* Check if the I2C is already enabled */ |
| 3368 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
3368 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 3369 | 3369 | { |
|
| 3370 | /* Prepare transfer parameters */ |
3370 | /* Enable I2C peripheral */ |
| 3371 | hi2c->pBuffPtr = pData; |
3371 | __HAL_I2C_ENABLE(hi2c); |
| 3372 | hi2c->XferCount = Size; |
3372 | } |
| 3373 | hi2c->XferSize = hi2c->XferCount; |
3373 | |
| 3374 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
3374 | /* Disable Pos */ |
| 3375 | 3375 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
|
| 3376 | if (hi2c->XferSize > 0U) |
3376 | |
| 3377 | { |
3377 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
| 3378 | if (hi2c->hdmarx != NULL) |
3378 | hi2c->Mode = HAL_I2C_MODE_MEM; |
| 3379 | { |
3379 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 3380 | /* Set the I2C DMA transfer complete callback */ |
3380 | |
| 3381 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
3381 | /* Prepare transfer parameters */ |
| 3382 | 3382 | hi2c->pBuffPtr = pData; |
|
| 3383 | /* Set the DMA error callback */ |
3383 | hi2c->XferCount = Size; |
| 3384 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
3384 | hi2c->XferSize = hi2c->XferCount; |
| 3385 | 3385 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
|
| 3386 | /* Set the unused DMA callbacks to NULL */ |
3386 | hi2c->Devaddress = DevAddress; |
| 3387 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
3387 | hi2c->Memaddress = MemAddress; |
| 3388 | hi2c->hdmarx->XferAbortCallback = NULL; |
3388 | hi2c->MemaddSize = MemAddSize; |
| 3389 | 3389 | hi2c->EventCount = 0U; |
|
| 3390 | /* Enable the DMA channel */ |
3390 | |
| 3391 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
3391 | if (hi2c->XferSize > 0U) |
| 3392 | } |
3392 | { |
| 3393 | else |
3393 | if (hi2c->hdmarx != NULL) |
| 3394 | { |
3394 | { |
| 3395 | /* Update I2C state */ |
3395 | /* Set the I2C DMA transfer complete callback */ |
| 3396 | hi2c->State = HAL_I2C_STATE_READY; |
3396 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
| 3397 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3397 | |
| 3398 | 3398 | /* Set the DMA error callback */ |
|
| 3399 | /* Update I2C error code */ |
3399 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
| 3400 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
3400 | |
| 3401 | 3401 | /* Set the unused DMA callbacks to NULL */ |
|
| 3402 | /* Process Unlocked */ |
3402 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
| 3403 | __HAL_UNLOCK(hi2c); |
3403 | hi2c->hdmarx->XferAbortCallback = NULL; |
| 3404 | 3404 | ||
| 3405 | return HAL_ERROR; |
3405 | /* Enable the DMA channel */ |
| 3406 | } |
3406 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
| 3407 | 3407 | } |
|
| 3408 | if (dmaxferstatus == HAL_OK) |
3408 | else |
| 3409 | { |
3409 | { |
| 3410 | /* Send Slave Address and Memory Address */ |
3410 | /* Update I2C state */ |
| 3411 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
3411 | hi2c->State = HAL_I2C_STATE_READY; |
| 3412 | { |
3412 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3413 | /* Abort the ongoing DMA */ |
3413 | |
| 3414 | dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx); |
3414 | /* Update I2C error code */ |
| 3415 | 3415 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
|
| 3416 | /* Prevent unused argument(s) compilation and MISRA warning */ |
3416 | |
| 3417 | UNUSED(dmaxferstatus); |
3417 | /* Process Unlocked */ |
| 3418 | 3418 | __HAL_UNLOCK(hi2c); |
|
| 3419 | /* Set the unused I2C DMA transfer complete callback to NULL */ |
3419 | |
| 3420 | hi2c->hdmarx->XferCpltCallback = NULL; |
3420 | return HAL_ERROR; |
| 3421 | 3421 | } |
|
| 3422 | /* Disable Acknowledge */ |
3422 | |
| 3423 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
3423 | if (dmaxferstatus == HAL_OK) |
| 3424 | 3424 | { |
|
| 3425 | hi2c->XferSize = 0U; |
3425 | /* Send Slave Address and Memory Address */ |
| 3426 | hi2c->XferCount = 0U; |
3426 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
| 3427 | 3427 | { |
|
| 3428 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
3428 | /* Abort the ongoing DMA */ |
| 3429 | __HAL_I2C_DISABLE(hi2c); |
3429 | dmaxferstatus = HAL_DMA_Abort_IT(hi2c->hdmarx); |
| 3430 | 3430 | ||
| 3431 | return HAL_ERROR; |
3431 | /* Prevent unused argument(s) compilation and MISRA warning */ |
| 3432 | } |
3432 | UNUSED(dmaxferstatus); |
| 3433 | 3433 | ||
| 3434 | if (hi2c->XferSize == 1U) |
3434 | /* Set the unused I2C DMA transfer complete callback to NULL */ |
| 3435 | { |
3435 | hi2c->hdmarx->XferCpltCallback = NULL; |
| 3436 | /* Disable Acknowledge */ |
3436 | |
| 3437 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
3437 | /* Disable Acknowledge */ |
| 3438 | } |
3438 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 3439 | else |
3439 | |
| 3440 | { |
3440 | hi2c->XferSize = 0U; |
| 3441 | /* Enable Last DMA bit */ |
3441 | hi2c->XferCount = 0U; |
| 3442 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
3442 | |
| 3443 | } |
3443 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
| 3444 | 3444 | __HAL_I2C_DISABLE(hi2c); |
|
| 3445 | /* Clear ADDR flag */ |
3445 | |
| 3446 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
3446 | return HAL_ERROR; |
| 3447 | 3447 | } |
|
| 3448 | /* Process Unlocked */ |
3448 | |
| 3449 | __HAL_UNLOCK(hi2c); |
3449 | if (hi2c->XferSize == 1U) |
| 3450 | 3450 | { |
|
| 3451 | /* Note : The I2C interrupts must be enabled after unlocking current process |
3451 | /* Disable Acknowledge */ |
| 3452 | to avoid the risk of I2C interrupt handle execution before current |
3452 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 3453 | process unlock */ |
3453 | } |
| 3454 | /* Enable ERR interrupt */ |
3454 | else |
| 3455 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); |
3455 | { |
| 3456 | 3456 | /* Enable Last DMA bit */ |
|
| 3457 | /* Enable DMA Request */ |
3457 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
| 3458 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
3458 | } |
| 3459 | } |
3459 | |
| 3460 | else |
3460 | /* Clear ADDR flag */ |
| 3461 | { |
3461 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 3462 | /* Update I2C state */ |
3462 | |
| 3463 | hi2c->State = HAL_I2C_STATE_READY; |
3463 | /* Process Unlocked */ |
| 3464 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3464 | __HAL_UNLOCK(hi2c); |
| 3465 | 3465 | ||
| 3466 | /* Update I2C error code */ |
3466 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 3467 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
3467 | to avoid the risk of I2C interrupt handle execution before current |
| 3468 | 3468 | process unlock */ |
|
| 3469 | /* Process Unlocked */ |
3469 | /* Enable ERR interrupt */ |
| 3470 | __HAL_UNLOCK(hi2c); |
3470 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_ERR); |
| 3471 | 3471 | ||
| 3472 | return HAL_ERROR; |
3472 | /* Enable DMA Request */ |
| 3473 | } |
3473 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
| 3474 | } |
3474 | } |
| 3475 | else |
3475 | else |
| 3476 | { |
3476 | { |
| 3477 | /* Send Slave Address and Memory Address */ |
3477 | /* Update I2C state */ |
| 3478 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
3478 | hi2c->State = HAL_I2C_STATE_READY; |
| 3479 | { |
3479 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3480 | return HAL_ERROR; |
3480 | |
| 3481 | } |
3481 | /* Update I2C error code */ |
| 3482 | 3482 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
|
| 3483 | /* Clear ADDR flag */ |
3483 | |
| 3484 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
3484 | /* Process Unlocked */ |
| 3485 | 3485 | __HAL_UNLOCK(hi2c); |
|
| 3486 | /* Generate Stop */ |
3486 | |
| 3487 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
3487 | return HAL_ERROR; |
| 3488 | 3488 | } |
|
| 3489 | hi2c->State = HAL_I2C_STATE_READY; |
3489 | } |
| 3490 | 3490 | else |
|
| 3491 | /* Process Unlocked */ |
3491 | { |
| 3492 | __HAL_UNLOCK(hi2c); |
3492 | /* Send Slave Address and Memory Address */ |
| 3493 | } |
3493 | if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK) |
| 3494 | 3494 | { |
|
| 3495 | return HAL_OK; |
3495 | return HAL_ERROR; |
| 3496 | } |
3496 | } |
| 3497 | else |
3497 | |
| 3498 | { |
3498 | /* Clear ADDR flag */ |
| 3499 | return HAL_BUSY; |
3499 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 3500 | } |
3500 | |
| 3501 | } |
3501 | /* Generate Stop */ |
| 3502 | 3502 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
|
| 3503 | /** |
3503 | |
| 3504 | * @brief Checks if target device is ready for communication. |
3504 | hi2c->State = HAL_I2C_STATE_READY; |
| 3505 | * @note This function is used with Memory devices |
3505 | |
| 3506 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
3506 | /* Process Unlocked */ |
| 3507 | * the configuration information for the specified I2C. |
3507 | __HAL_UNLOCK(hi2c); |
| 3508 | * @param DevAddress Target device address: The device 7 bits address value |
3508 | } |
| 3509 | * in datasheet must be shifted to the left before calling the interface |
3509 | |
| 3510 | * @param Trials Number of trials |
3510 | return HAL_OK; |
| 3511 | * @param Timeout Timeout duration |
3511 | } |
| 3512 | * @retval HAL status |
3512 | else |
| 3513 | */ |
3513 | { |
| 3514 | HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) |
3514 | return HAL_BUSY; |
| 3515 | { |
3515 | } |
| 3516 | /* Get tick */ |
3516 | } |
| 3517 | uint32_t tickstart = HAL_GetTick(); |
3517 | |
| 3518 | uint32_t I2C_Trials = 1U; |
3518 | /** |
| 3519 | FlagStatus tmp1; |
3519 | * @brief Checks if target device is ready for communication. |
| 3520 | FlagStatus tmp2; |
3520 | * @note This function is used with Memory devices |
| 3521 | 3521 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 3522 | if (hi2c->State == HAL_I2C_STATE_READY) |
3522 | * the configuration information for the specified I2C. |
| 3523 | { |
3523 | * @param DevAddress Target device address: The device 7 bits address value |
| 3524 | /* Wait until BUSY flag is reset */ |
3524 | * in datasheet must be shifted to the left before calling the interface |
| 3525 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
3525 | * @param Trials Number of trials |
| 3526 | { |
3526 | * @param Timeout Timeout duration |
| 3527 | return HAL_BUSY; |
3527 | * @retval HAL status |
| 3528 | } |
3528 | */ |
| 3529 | 3529 | HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout) |
|
| 3530 | /* Process Locked */ |
3530 | { |
| 3531 | __HAL_LOCK(hi2c); |
3531 | /* Get tick */ |
| 3532 | 3532 | uint32_t tickstart = HAL_GetTick(); |
|
| 3533 | /* Check if the I2C is already enabled */ |
3533 | uint32_t I2C_Trials = 0U; |
| 3534 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
3534 | FlagStatus tmp1; |
| 3535 | { |
3535 | FlagStatus tmp2; |
| 3536 | /* Enable I2C peripheral */ |
3536 | |
| 3537 | __HAL_I2C_ENABLE(hi2c); |
3537 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 3538 | } |
3538 | { |
| 3539 | 3539 | /* Wait until BUSY flag is reset */ |
|
| 3540 | /* Disable Pos */ |
3540 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
| 3541 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
3541 | { |
| 3542 | 3542 | return HAL_BUSY; |
|
| 3543 | hi2c->State = HAL_I2C_STATE_BUSY; |
3543 | } |
| 3544 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
3544 | |
| 3545 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
3545 | /* Process Locked */ |
| 3546 | 3546 | __HAL_LOCK(hi2c); |
|
| 3547 | do |
3547 | |
| 3548 | { |
3548 | /* Check if the I2C is already enabled */ |
| 3549 | /* Generate Start */ |
3549 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 3550 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
3550 | { |
| 3551 | 3551 | /* Enable I2C peripheral */ |
|
| 3552 | /* Wait until SB flag is set */ |
3552 | __HAL_I2C_ENABLE(hi2c); |
| 3553 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) |
3553 | } |
| 3554 | { |
3554 | |
| 3555 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
3555 | /* Disable Pos */ |
| 3556 | { |
3556 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 3557 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
3557 | |
| 3558 | } |
3558 | hi2c->State = HAL_I2C_STATE_BUSY; |
| 3559 | return HAL_TIMEOUT; |
3559 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 3560 | } |
3560 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 3561 | 3561 | ||
| 3562 | /* Send slave address */ |
3562 | do |
| 3563 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
3563 | { |
| 3564 | 3564 | /* Generate Start */ |
|
| 3565 | /* Wait until ADDR or AF flag are set */ |
3565 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 3566 | /* Get tick */ |
3566 | |
| 3567 | tickstart = HAL_GetTick(); |
3567 | /* Wait until SB flag is set */ |
| 3568 | 3568 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, tickstart) != HAL_OK) |
|
| 3569 | tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); |
3569 | { |
| 3570 | tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); |
3570 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
| 3571 | while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET)) |
3571 | { |
| 3572 | { |
3572 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
| 3573 | if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) |
3573 | } |
| 3574 | { |
3574 | return HAL_TIMEOUT; |
| 3575 | hi2c->State = HAL_I2C_STATE_TIMEOUT; |
3575 | } |
| 3576 | } |
3576 | |
| 3577 | tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); |
3577 | /* Send slave address */ |
| 3578 | tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); |
3578 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
| 3579 | } |
3579 | |
| 3580 | 3580 | /* Wait until ADDR or AF flag are set */ |
|
| 3581 | hi2c->State = HAL_I2C_STATE_READY; |
3581 | /* Get tick */ |
| 3582 | 3582 | tickstart = HAL_GetTick(); |
|
| 3583 | /* Check if the ADDR flag has been set */ |
3583 | |
| 3584 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) |
3584 | tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); |
| 3585 | { |
3585 | tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); |
| 3586 | /* Generate Stop */ |
3586 | while ((hi2c->State != HAL_I2C_STATE_TIMEOUT) && (tmp1 == RESET) && (tmp2 == RESET)) |
| 3587 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
3587 | { |
| 3588 | 3588 | if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) |
|
| 3589 | /* Clear ADDR Flag */ |
3589 | { |
| 3590 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
3590 | hi2c->State = HAL_I2C_STATE_TIMEOUT; |
| 3591 | 3591 | } |
|
| 3592 | /* Wait until BUSY flag is reset */ |
3592 | tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); |
| 3593 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
3593 | tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); |
| 3594 | { |
3594 | } |
| 3595 | return HAL_ERROR; |
3595 | |
| 3596 | } |
3596 | hi2c->State = HAL_I2C_STATE_READY; |
| 3597 | 3597 | ||
| 3598 | hi2c->State = HAL_I2C_STATE_READY; |
3598 | /* Check if the ADDR flag has been set */ |
| 3599 | 3599 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) |
|
| 3600 | /* Process Unlocked */ |
3600 | { |
| 3601 | __HAL_UNLOCK(hi2c); |
3601 | /* Generate Stop */ |
| 3602 | 3602 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
|
| 3603 | return HAL_OK; |
3603 | |
| 3604 | } |
3604 | /* Clear ADDR Flag */ |
| 3605 | else |
3605 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 3606 | { |
3606 | |
| 3607 | /* Generate Stop */ |
3607 | /* Wait until BUSY flag is reset */ |
| 3608 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
3608 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
| 3609 | 3609 | { |
|
| 3610 | /* Clear AF Flag */ |
3610 | return HAL_ERROR; |
| 3611 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
3611 | } |
| 3612 | 3612 | ||
| 3613 | /* Wait until BUSY flag is reset */ |
3613 | hi2c->State = HAL_I2C_STATE_READY; |
| 3614 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
3614 | |
| 3615 | { |
3615 | /* Process Unlocked */ |
| 3616 | return HAL_ERROR; |
3616 | __HAL_UNLOCK(hi2c); |
| 3617 | } |
3617 | |
| 3618 | } |
3618 | return HAL_OK; |
| 3619 | 3619 | } |
|
| 3620 | /* Increment Trials */ |
3620 | else |
| 3621 | I2C_Trials++; |
3621 | { |
| 3622 | } |
3622 | /* Generate Stop */ |
| 3623 | while (I2C_Trials < Trials); |
3623 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 3624 | 3624 | ||
| 3625 | hi2c->State = HAL_I2C_STATE_READY; |
3625 | /* Clear AF Flag */ |
| 3626 | 3626 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
|
| 3627 | /* Process Unlocked */ |
3627 | |
| 3628 | __HAL_UNLOCK(hi2c); |
3628 | /* Wait until BUSY flag is reset */ |
| 3629 | 3629 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY_FLAG, tickstart) != HAL_OK) |
|
| 3630 | return HAL_ERROR; |
3630 | { |
| 3631 | } |
3631 | return HAL_ERROR; |
| 3632 | else |
3632 | } |
| 3633 | { |
3633 | } |
| 3634 | return HAL_BUSY; |
3634 | |
| 3635 | } |
3635 | /* Increment Trials */ |
| 3636 | } |
3636 | I2C_Trials++; |
| 3637 | 3637 | } |
|
| 3638 | /** |
3638 | while (I2C_Trials < Trials); |
| 3639 | * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. |
3639 | |
| 3640 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
3640 | hi2c->State = HAL_I2C_STATE_READY; |
| 3641 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
3641 | |
| 3642 | * the configuration information for the specified I2C. |
3642 | /* Process Unlocked */ |
| 3643 | * @param DevAddress Target device address: The device 7 bits address value |
3643 | __HAL_UNLOCK(hi2c); |
| 3644 | * in datasheet must be shifted to the left before calling the interface |
3644 | |
| 3645 | * @param pData Pointer to data buffer |
3645 | return HAL_ERROR; |
| 3646 | * @param Size Amount of data to be sent |
3646 | } |
| 3647 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
3647 | else |
| 3648 | * @retval HAL status |
3648 | { |
| 3649 | */ |
3649 | return HAL_BUSY; |
| 3650 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
3650 | } |
| 3651 | { |
3651 | } |
| 3652 | __IO uint32_t Prev_State = 0x00U; |
3652 | |
| 3653 | __IO uint32_t count = 0x00U; |
3653 | /** |
| 3654 | 3654 | * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. |
|
| 3655 | /* Check the parameters */ |
3655 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
| 3656 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
3656 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 3657 | 3657 | * the configuration information for the specified I2C. |
|
| 3658 | if (hi2c->State == HAL_I2C_STATE_READY) |
3658 | * @param DevAddress Target device address: The device 7 bits address value |
| 3659 | { |
3659 | * in datasheet must be shifted to the left before calling the interface |
| 3660 | /* Check Busy Flag only if FIRST call of Master interface */ |
3660 | * @param pData Pointer to data buffer |
| 3661 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
3661 | * @param Size Amount of data to be sent |
| 3662 | { |
3662 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
| 3663 | /* Wait until BUSY flag is reset */ |
3663 | * @retval HAL status |
| 3664 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
3664 | */ |
| 3665 | do |
3665 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
| 3666 | { |
3666 | { |
| 3667 | count--; |
3667 | __IO uint32_t Prev_State = 0x00U; |
| 3668 | if (count == 0U) |
3668 | __IO uint32_t count = 0x00U; |
| 3669 | { |
3669 | |
| 3670 | hi2c->PreviousState = I2C_STATE_NONE; |
3670 | /* Check the parameters */ |
| 3671 | hi2c->State = HAL_I2C_STATE_READY; |
3671 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
| 3672 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3672 | |
| 3673 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
3673 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 3674 | 3674 | { |
|
| 3675 | /* Process Unlocked */ |
3675 | /* Check Busy Flag only if FIRST call of Master interface */ |
| 3676 | __HAL_UNLOCK(hi2c); |
3676 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
| 3677 | 3677 | { |
|
| 3678 | return HAL_ERROR; |
3678 | /* Wait until BUSY flag is reset */ |
| 3679 | } |
3679 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
| 3680 | } |
3680 | do |
| 3681 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
3681 | { |
| 3682 | } |
3682 | count--; |
| 3683 | 3683 | if (count == 0U) |
|
| 3684 | /* Process Locked */ |
3684 | { |
| 3685 | __HAL_LOCK(hi2c); |
3685 | hi2c->PreviousState = I2C_STATE_NONE; |
| 3686 | 3686 | hi2c->State = HAL_I2C_STATE_READY; |
|
| 3687 | /* Check if the I2C is already enabled */ |
3687 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3688 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
3688 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 3689 | { |
3689 | |
| 3690 | /* Enable I2C peripheral */ |
3690 | return HAL_BUSY; |
| 3691 | __HAL_I2C_ENABLE(hi2c); |
3691 | } |
| 3692 | } |
3692 | } |
| 3693 | 3693 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
|
| 3694 | /* Disable Pos */ |
3694 | } |
| 3695 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
3695 | |
| 3696 | 3696 | /* Process Locked */ |
|
| 3697 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
3697 | __HAL_LOCK(hi2c); |
| 3698 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
3698 | |
| 3699 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
3699 | /* Check if the I2C is already enabled */ |
| 3700 | 3700 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
|
| 3701 | /* Prepare transfer parameters */ |
3701 | { |
| 3702 | hi2c->pBuffPtr = pData; |
3702 | /* Enable I2C peripheral */ |
| 3703 | hi2c->XferCount = Size; |
3703 | __HAL_I2C_ENABLE(hi2c); |
| 3704 | hi2c->XferSize = hi2c->XferCount; |
3704 | } |
| 3705 | hi2c->XferOptions = XferOptions; |
3705 | |
| 3706 | hi2c->Devaddress = DevAddress; |
3706 | /* Disable Pos */ |
| 3707 | 3707 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
|
| 3708 | Prev_State = hi2c->PreviousState; |
3708 | |
| 3709 | 3709 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
|
| 3710 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
3710 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
| 3711 | /* Mean Previous state is same as current state */ |
3711 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 3712 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
3712 | |
| 3713 | { |
3713 | /* Prepare transfer parameters */ |
| 3714 | /* Generate Start */ |
3714 | hi2c->pBuffPtr = pData; |
| 3715 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
3715 | hi2c->XferCount = Size; |
| 3716 | } |
3716 | hi2c->XferSize = hi2c->XferCount; |
| 3717 | 3717 | hi2c->XferOptions = XferOptions; |
|
| 3718 | /* Process Unlocked */ |
3718 | hi2c->Devaddress = DevAddress; |
| 3719 | __HAL_UNLOCK(hi2c); |
3719 | |
| 3720 | 3720 | Prev_State = hi2c->PreviousState; |
|
| 3721 | /* Note : The I2C interrupts must be enabled after unlocking current process |
3721 | |
| 3722 | to avoid the risk of I2C interrupt handle execution before current |
3722 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
| 3723 | process unlock */ |
3723 | /* Mean Previous state is same as current state */ |
| 3724 | 3724 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
|
| 3725 | /* Enable EVT, BUF and ERR interrupt */ |
3725 | { |
| 3726 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
3726 | /* Generate Start */ |
| 3727 | 3727 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
|
| 3728 | return HAL_OK; |
3728 | } |
| 3729 | } |
3729 | |
| 3730 | else |
3730 | /* Process Unlocked */ |
| 3731 | { |
3731 | __HAL_UNLOCK(hi2c); |
| 3732 | return HAL_BUSY; |
3732 | |
| 3733 | } |
3733 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 3734 | } |
3734 | to avoid the risk of I2C interrupt handle execution before current |
| 3735 | 3735 | process unlock */ |
|
| 3736 | /** |
3736 | |
| 3737 | * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. |
3737 | /* Enable EVT, BUF and ERR interrupt */ |
| 3738 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
3738 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 3739 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
3739 | |
| 3740 | * the configuration information for the specified I2C. |
3740 | return HAL_OK; |
| 3741 | * @param DevAddress Target device address: The device 7 bits address value |
3741 | } |
| 3742 | * in datasheet must be shifted to the left before calling the interface |
3742 | else |
| 3743 | * @param pData Pointer to data buffer |
3743 | { |
| 3744 | * @param Size Amount of data to be sent |
3744 | return HAL_BUSY; |
| 3745 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
3745 | } |
| 3746 | * @retval HAL status |
3746 | } |
| 3747 | */ |
3747 | |
| 3748 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
3748 | /** |
| 3749 | { |
3749 | * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. |
| 3750 | __IO uint32_t Prev_State = 0x00U; |
3750 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
| 3751 | __IO uint32_t count = 0x00U; |
3751 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 3752 | HAL_StatusTypeDef dmaxferstatus; |
3752 | * the configuration information for the specified I2C. |
| 3753 | 3753 | * @param DevAddress Target device address: The device 7 bits address value |
|
| 3754 | /* Check the parameters */ |
3754 | * in datasheet must be shifted to the left before calling the interface |
| 3755 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
3755 | * @param pData Pointer to data buffer |
| 3756 | 3756 | * @param Size Amount of data to be sent |
|
| 3757 | if (hi2c->State == HAL_I2C_STATE_READY) |
3757 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
| 3758 | { |
3758 | * @retval HAL status |
| 3759 | /* Check Busy Flag only if FIRST call of Master interface */ |
3759 | */ |
| 3760 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
3760 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
| 3761 | { |
3761 | { |
| 3762 | /* Wait until BUSY flag is reset */ |
3762 | __IO uint32_t Prev_State = 0x00U; |
| 3763 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
3763 | __IO uint32_t count = 0x00U; |
| 3764 | do |
3764 | HAL_StatusTypeDef dmaxferstatus; |
| 3765 | { |
3765 | |
| 3766 | count--; |
3766 | /* Check the parameters */ |
| 3767 | if (count == 0U) |
3767 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
| 3768 | { |
3768 | |
| 3769 | hi2c->PreviousState = I2C_STATE_NONE; |
3769 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 3770 | hi2c->State = HAL_I2C_STATE_READY; |
3770 | { |
| 3771 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3771 | /* Check Busy Flag only if FIRST call of Master interface */ |
| 3772 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
3772 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
| 3773 | 3773 | { |
|
| 3774 | /* Process Unlocked */ |
3774 | /* Wait until BUSY flag is reset */ |
| 3775 | __HAL_UNLOCK(hi2c); |
3775 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
| 3776 | 3776 | do |
|
| 3777 | return HAL_ERROR; |
3777 | { |
| 3778 | } |
3778 | count--; |
| 3779 | } |
3779 | if (count == 0U) |
| 3780 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
3780 | { |
| 3781 | } |
3781 | hi2c->PreviousState = I2C_STATE_NONE; |
| 3782 | 3782 | hi2c->State = HAL_I2C_STATE_READY; |
|
| 3783 | /* Process Locked */ |
3783 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3784 | __HAL_LOCK(hi2c); |
3784 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 3785 | 3785 | ||
| 3786 | /* Check if the I2C is already enabled */ |
3786 | return HAL_BUSY; |
| 3787 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
3787 | } |
| 3788 | { |
3788 | } |
| 3789 | /* Enable I2C peripheral */ |
3789 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
| 3790 | __HAL_I2C_ENABLE(hi2c); |
3790 | } |
| 3791 | } |
3791 | |
| 3792 | 3792 | /* Process Locked */ |
|
| 3793 | /* Disable Pos */ |
3793 | __HAL_LOCK(hi2c); |
| 3794 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
3794 | |
| 3795 | 3795 | /* Check if the I2C is already enabled */ |
|
| 3796 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
3796 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 3797 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
3797 | { |
| 3798 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
3798 | /* Enable I2C peripheral */ |
| 3799 | 3799 | __HAL_I2C_ENABLE(hi2c); |
|
| 3800 | /* Prepare transfer parameters */ |
3800 | } |
| 3801 | hi2c->pBuffPtr = pData; |
3801 | |
| 3802 | hi2c->XferCount = Size; |
3802 | /* Disable Pos */ |
| 3803 | hi2c->XferSize = hi2c->XferCount; |
3803 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 3804 | hi2c->XferOptions = XferOptions; |
3804 | |
| 3805 | hi2c->Devaddress = DevAddress; |
3805 | hi2c->State = HAL_I2C_STATE_BUSY_TX; |
| 3806 | 3806 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
|
| 3807 | Prev_State = hi2c->PreviousState; |
3807 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 3808 | 3808 | ||
| 3809 | if (hi2c->XferSize > 0U) |
3809 | /* Prepare transfer parameters */ |
| 3810 | { |
3810 | hi2c->pBuffPtr = pData; |
| 3811 | if (hi2c->hdmatx != NULL) |
3811 | hi2c->XferCount = Size; |
| 3812 | { |
3812 | hi2c->XferSize = hi2c->XferCount; |
| 3813 | /* Set the I2C DMA transfer complete callback */ |
3813 | hi2c->XferOptions = XferOptions; |
| 3814 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
3814 | hi2c->Devaddress = DevAddress; |
| 3815 | 3815 | ||
| 3816 | /* Set the DMA error callback */ |
3816 | Prev_State = hi2c->PreviousState; |
| 3817 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
3817 | |
| 3818 | 3818 | if (hi2c->XferSize > 0U) |
|
| 3819 | /* Set the unused DMA callbacks to NULL */ |
3819 | { |
| 3820 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
3820 | if (hi2c->hdmatx != NULL) |
| 3821 | hi2c->hdmatx->XferAbortCallback = NULL; |
3821 | { |
| 3822 | 3822 | /* Set the I2C DMA transfer complete callback */ |
|
| 3823 | /* Enable the DMA channel */ |
3823 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
| 3824 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
3824 | |
| 3825 | } |
3825 | /* Set the DMA error callback */ |
| 3826 | else |
3826 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
| 3827 | { |
3827 | |
| 3828 | /* Update I2C state */ |
3828 | /* Set the unused DMA callbacks to NULL */ |
| 3829 | hi2c->State = HAL_I2C_STATE_READY; |
3829 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
| 3830 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3830 | hi2c->hdmatx->XferAbortCallback = NULL; |
| 3831 | 3831 | ||
| 3832 | /* Update I2C error code */ |
3832 | /* Enable the DMA channel */ |
| 3833 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
3833 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
| 3834 | 3834 | } |
|
| 3835 | /* Process Unlocked */ |
3835 | else |
| 3836 | __HAL_UNLOCK(hi2c); |
3836 | { |
| 3837 | 3837 | /* Update I2C state */ |
|
| 3838 | return HAL_ERROR; |
3838 | hi2c->State = HAL_I2C_STATE_READY; |
| 3839 | } |
3839 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3840 | 3840 | ||
| 3841 | if (dmaxferstatus == HAL_OK) |
3841 | /* Update I2C error code */ |
| 3842 | { |
3842 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
| 3843 | /* Enable Acknowledge */ |
3843 | |
| 3844 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
3844 | /* Process Unlocked */ |
| 3845 | 3845 | __HAL_UNLOCK(hi2c); |
|
| 3846 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
3846 | |
| 3847 | /* Mean Previous state is same as current state */ |
3847 | return HAL_ERROR; |
| 3848 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
3848 | } |
| 3849 | { |
3849 | |
| 3850 | /* Generate Start */ |
3850 | if (dmaxferstatus == HAL_OK) |
| 3851 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
3851 | { |
| 3852 | } |
3852 | /* Enable Acknowledge */ |
| 3853 | 3853 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
|
| 3854 | /* Process Unlocked */ |
3854 | |
| 3855 | __HAL_UNLOCK(hi2c); |
3855 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
| 3856 | 3856 | /* Mean Previous state is same as current state */ |
|
| 3857 | /* Note : The I2C interrupts must be enabled after unlocking current process |
3857 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
| 3858 | to avoid the risk of I2C interrupt handle execution before current |
3858 | { |
| 3859 | process unlock */ |
3859 | /* Generate Start */ |
| 3860 | 3860 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
|
| 3861 | /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ |
3861 | } |
| 3862 | /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ |
3862 | |
| 3863 | if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
3863 | /* Process Unlocked */ |
| 3864 | { |
3864 | __HAL_UNLOCK(hi2c); |
| 3865 | /* Enable DMA Request */ |
3865 | |
| 3866 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
3866 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 3867 | } |
3867 | to avoid the risk of I2C interrupt handle execution before current |
| 3868 | 3868 | process unlock */ |
|
| 3869 | /* Enable EVT and ERR interrupt */ |
3869 | |
| 3870 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
3870 | /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ |
| 3871 | } |
3871 | /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ |
| 3872 | else |
3872 | if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
| 3873 | { |
3873 | { |
| 3874 | /* Update I2C state */ |
3874 | /* Enable DMA Request */ |
| 3875 | hi2c->State = HAL_I2C_STATE_READY; |
3875 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 3876 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3876 | } |
| 3877 | 3877 | ||
| 3878 | /* Update I2C error code */ |
3878 | /* Enable EVT and ERR interrupt */ |
| 3879 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
3879 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 3880 | 3880 | } |
|
| 3881 | /* Process Unlocked */ |
3881 | else |
| 3882 | __HAL_UNLOCK(hi2c); |
3882 | { |
| 3883 | 3883 | /* Update I2C state */ |
|
| 3884 | return HAL_ERROR; |
3884 | hi2c->State = HAL_I2C_STATE_READY; |
| 3885 | } |
3885 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3886 | } |
3886 | |
| 3887 | else |
3887 | /* Update I2C error code */ |
| 3888 | { |
3888 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
| 3889 | /* Enable Acknowledge */ |
3889 | |
| 3890 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
3890 | /* Process Unlocked */ |
| 3891 | 3891 | __HAL_UNLOCK(hi2c); |
|
| 3892 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
3892 | |
| 3893 | /* Mean Previous state is same as current state */ |
3893 | return HAL_ERROR; |
| 3894 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
3894 | } |
| 3895 | { |
3895 | } |
| 3896 | /* Generate Start */ |
3896 | else |
| 3897 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
3897 | { |
| 3898 | } |
3898 | /* Enable Acknowledge */ |
| 3899 | 3899 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
|
| 3900 | /* Process Unlocked */ |
3900 | |
| 3901 | __HAL_UNLOCK(hi2c); |
3901 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
| 3902 | 3902 | /* Mean Previous state is same as current state */ |
|
| 3903 | /* Note : The I2C interrupts must be enabled after unlocking current process |
3903 | if ((Prev_State != I2C_STATE_MASTER_BUSY_TX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
| 3904 | to avoid the risk of I2C interrupt handle execution before current |
3904 | { |
| 3905 | process unlock */ |
3905 | /* Generate Start */ |
| 3906 | 3906 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
|
| 3907 | /* Enable EVT, BUF and ERR interrupt */ |
3907 | } |
| 3908 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
3908 | |
| 3909 | } |
3909 | /* Process Unlocked */ |
| 3910 | 3910 | __HAL_UNLOCK(hi2c); |
|
| 3911 | return HAL_OK; |
3911 | |
| 3912 | } |
3912 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 3913 | else |
3913 | to avoid the risk of I2C interrupt handle execution before current |
| 3914 | { |
3914 | process unlock */ |
| 3915 | return HAL_BUSY; |
3915 | |
| 3916 | } |
3916 | /* Enable EVT, BUF and ERR interrupt */ |
| 3917 | } |
3917 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 3918 | 3918 | } |
|
| 3919 | /** |
3919 | |
| 3920 | * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt |
3920 | return HAL_OK; |
| 3921 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
3921 | } |
| 3922 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
3922 | else |
| 3923 | * the configuration information for the specified I2C. |
3923 | { |
| 3924 | * @param DevAddress Target device address: The device 7 bits address value |
3924 | return HAL_BUSY; |
| 3925 | * in datasheet must be shifted to the left before calling the interface |
3925 | } |
| 3926 | * @param pData Pointer to data buffer |
3926 | } |
| 3927 | * @param Size Amount of data to be sent |
3927 | |
| 3928 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
3928 | /** |
| 3929 | * @retval HAL status |
3929 | * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt |
| 3930 | */ |
3930 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
| 3931 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
3931 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 3932 | { |
3932 | * the configuration information for the specified I2C. |
| 3933 | __IO uint32_t Prev_State = 0x00U; |
3933 | * @param DevAddress Target device address: The device 7 bits address value |
| 3934 | __IO uint32_t count = 0U; |
3934 | * in datasheet must be shifted to the left before calling the interface |
| 3935 | uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
3935 | * @param pData Pointer to data buffer |
| 3936 | 3936 | * @param Size Amount of data to be sent |
|
| 3937 | /* Check the parameters */ |
3937 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
| 3938 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
3938 | * @retval HAL status |
| 3939 | 3939 | */ |
|
| 3940 | if (hi2c->State == HAL_I2C_STATE_READY) |
3940 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
| 3941 | { |
3941 | { |
| 3942 | /* Check Busy Flag only if FIRST call of Master interface */ |
3942 | __IO uint32_t Prev_State = 0x00U; |
| 3943 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
3943 | __IO uint32_t count = 0U; |
| 3944 | { |
3944 | uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 3945 | /* Wait until BUSY flag is reset */ |
3945 | |
| 3946 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
3946 | /* Check the parameters */ |
| 3947 | do |
3947 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
| 3948 | { |
3948 | |
| 3949 | count--; |
3949 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 3950 | if (count == 0U) |
3950 | { |
| 3951 | { |
3951 | /* Check Busy Flag only if FIRST call of Master interface */ |
| 3952 | hi2c->PreviousState = I2C_STATE_NONE; |
3952 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
| 3953 | hi2c->State = HAL_I2C_STATE_READY; |
3953 | { |
| 3954 | hi2c->Mode = HAL_I2C_MODE_NONE; |
3954 | /* Wait until BUSY flag is reset */ |
| 3955 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
3955 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
| 3956 | 3956 | do |
|
| 3957 | /* Process Unlocked */ |
3957 | { |
| 3958 | __HAL_UNLOCK(hi2c); |
3958 | count--; |
| 3959 | 3959 | if (count == 0U) |
|
| 3960 | return HAL_ERROR; |
3960 | { |
| 3961 | } |
3961 | hi2c->PreviousState = I2C_STATE_NONE; |
| 3962 | } |
3962 | hi2c->State = HAL_I2C_STATE_READY; |
| 3963 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
3963 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 3964 | } |
3964 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 3965 | 3965 | ||
| 3966 | /* Process Locked */ |
3966 | return HAL_BUSY; |
| 3967 | __HAL_LOCK(hi2c); |
3967 | } |
| 3968 | 3968 | } |
|
| 3969 | /* Check if the I2C is already enabled */ |
3969 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
| 3970 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
3970 | } |
| 3971 | { |
3971 | |
| 3972 | /* Enable I2C peripheral */ |
3972 | /* Process Locked */ |
| 3973 | __HAL_I2C_ENABLE(hi2c); |
3973 | __HAL_LOCK(hi2c); |
| 3974 | } |
3974 | |
| 3975 | 3975 | /* Check if the I2C is already enabled */ |
|
| 3976 | /* Disable Pos */ |
3976 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 3977 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
3977 | { |
| 3978 | 3978 | /* Enable I2C peripheral */ |
|
| 3979 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
3979 | __HAL_I2C_ENABLE(hi2c); |
| 3980 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
3980 | } |
| 3981 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
3981 | |
| 3982 | 3982 | /* Disable Pos */ |
|
| 3983 | /* Prepare transfer parameters */ |
3983 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 3984 | hi2c->pBuffPtr = pData; |
3984 | |
| 3985 | hi2c->XferCount = Size; |
3985 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
| 3986 | hi2c->XferSize = hi2c->XferCount; |
3986 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
| 3987 | hi2c->XferOptions = XferOptions; |
3987 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 3988 | hi2c->Devaddress = DevAddress; |
3988 | |
| 3989 | 3989 | /* Prepare transfer parameters */ |
|
| 3990 | Prev_State = hi2c->PreviousState; |
3990 | hi2c->pBuffPtr = pData; |
| 3991 | 3991 | hi2c->XferCount = Size; |
|
| 3992 | if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) |
3992 | hi2c->XferSize = hi2c->XferCount; |
| 3993 | { |
3993 | hi2c->XferOptions = XferOptions; |
| 3994 | if (Prev_State == I2C_STATE_MASTER_BUSY_RX) |
3994 | hi2c->Devaddress = DevAddress; |
| 3995 | { |
3995 | |
| 3996 | /* Disable Acknowledge */ |
3996 | Prev_State = hi2c->PreviousState; |
| 3997 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
3997 | |
| 3998 | 3998 | if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) |
|
| 3999 | /* Enable Pos */ |
3999 | { |
| 4000 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
4000 | if (Prev_State == I2C_STATE_MASTER_BUSY_RX) |
| 4001 | 4001 | { |
|
| 4002 | /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */ |
4002 | /* Disable Acknowledge */ |
| 4003 | enableIT &= ~I2C_IT_BUF; |
4003 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4004 | } |
4004 | |
| 4005 | else |
4005 | /* Enable Pos */ |
| 4006 | { |
4006 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 4007 | /* Enable Acknowledge */ |
4007 | |
| 4008 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
4008 | /* Remove Enabling of IT_BUF, mean RXNE treatment, treat the 2 bytes through BTF */ |
| 4009 | } |
4009 | enableIT &= ~I2C_IT_BUF; |
| 4010 | } |
4010 | } |
| 4011 | else |
4011 | else |
| 4012 | { |
4012 | { |
| 4013 | /* Enable Acknowledge */ |
4013 | /* Enable Acknowledge */ |
| 4014 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
4014 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4015 | } |
4015 | } |
| 4016 | 4016 | } |
|
| 4017 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
4017 | else |
| 4018 | /* Mean Previous state is same as current state */ |
4018 | { |
| 4019 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
4019 | /* Enable Acknowledge */ |
| 4020 | { |
4020 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4021 | /* Generate Start */ |
4021 | } |
| 4022 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
4022 | |
| 4023 | } |
4023 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
| 4024 | 4024 | /* Mean Previous state is same as current state */ |
|
| 4025 | /* Process Unlocked */ |
4025 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
| 4026 | __HAL_UNLOCK(hi2c); |
4026 | { |
| 4027 | 4027 | /* Generate Start */ |
|
| 4028 | /* Note : The I2C interrupts must be enabled after unlocking current process |
4028 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 4029 | to avoid the risk of I2C interrupt handle execution before current |
4029 | } |
| 4030 | process unlock */ |
4030 | |
| 4031 | 4031 | /* Process Unlocked */ |
|
| 4032 | /* Enable interrupts */ |
4032 | __HAL_UNLOCK(hi2c); |
| 4033 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
4033 | |
| 4034 | 4034 | /* Note : The I2C interrupts must be enabled after unlocking current process |
|
| 4035 | return HAL_OK; |
4035 | to avoid the risk of I2C interrupt handle execution before current |
| 4036 | } |
4036 | process unlock */ |
| 4037 | else |
4037 | |
| 4038 | { |
4038 | /* Enable interrupts */ |
| 4039 | return HAL_BUSY; |
4039 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
| 4040 | } |
4040 | |
| 4041 | } |
4041 | return HAL_OK; |
| 4042 | 4042 | } |
|
| 4043 | /** |
4043 | else |
| 4044 | * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA |
4044 | { |
| 4045 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
4045 | return HAL_BUSY; |
| 4046 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
4046 | } |
| 4047 | * the configuration information for the specified I2C. |
4047 | } |
| 4048 | * @param DevAddress Target device address: The device 7 bits address value |
4048 | |
| 4049 | * in datasheet must be shifted to the left before calling the interface |
4049 | /** |
| 4050 | * @param pData Pointer to data buffer |
4050 | * @brief Sequential receive in master mode an amount of data in non-blocking mode with DMA |
| 4051 | * @param Size Amount of data to be sent |
4051 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
| 4052 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
4052 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 4053 | * @retval HAL status |
4053 | * the configuration information for the specified I2C. |
| 4054 | */ |
4054 | * @param DevAddress Target device address: The device 7 bits address value |
| 4055 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
4055 | * in datasheet must be shifted to the left before calling the interface |
| 4056 | { |
4056 | * @param pData Pointer to data buffer |
| 4057 | __IO uint32_t Prev_State = 0x00U; |
4057 | * @param Size Amount of data to be sent |
| 4058 | __IO uint32_t count = 0U; |
4058 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
| 4059 | uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
4059 | * @retval HAL status |
| 4060 | HAL_StatusTypeDef dmaxferstatus; |
4060 | */ |
| 4061 | 4061 | HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
|
| 4062 | /* Check the parameters */ |
4062 | { |
| 4063 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
4063 | __IO uint32_t Prev_State = 0x00U; |
| 4064 | 4064 | __IO uint32_t count = 0U; |
|
| 4065 | if (hi2c->State == HAL_I2C_STATE_READY) |
4065 | uint32_t enableIT = (I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 4066 | { |
4066 | HAL_StatusTypeDef dmaxferstatus; |
| 4067 | /* Check Busy Flag only if FIRST call of Master interface */ |
4067 | |
| 4068 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
4068 | /* Check the parameters */ |
| 4069 | { |
4069 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
| 4070 | /* Wait until BUSY flag is reset */ |
4070 | |
| 4071 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
4071 | if (hi2c->State == HAL_I2C_STATE_READY) |
| 4072 | do |
4072 | { |
| 4073 | { |
4073 | /* Check Busy Flag only if FIRST call of Master interface */ |
| 4074 | count--; |
4074 | if ((READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP) || (XferOptions == I2C_FIRST_AND_LAST_FRAME) || (XferOptions == I2C_FIRST_FRAME)) |
| 4075 | if (count == 0U) |
4075 | { |
| 4076 | { |
4076 | /* Wait until BUSY flag is reset */ |
| 4077 | hi2c->PreviousState = I2C_STATE_NONE; |
4077 | count = I2C_TIMEOUT_BUSY_FLAG * (SystemCoreClock / 25U / 1000U); |
| 4078 | hi2c->State = HAL_I2C_STATE_READY; |
4078 | do |
| 4079 | hi2c->Mode = HAL_I2C_MODE_NONE; |
4079 | { |
| 4080 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
4080 | count--; |
| 4081 | 4081 | if (count == 0U) |
|
| 4082 | /* Process Unlocked */ |
4082 | { |
| 4083 | __HAL_UNLOCK(hi2c); |
4083 | hi2c->PreviousState = I2C_STATE_NONE; |
| 4084 | 4084 | hi2c->State = HAL_I2C_STATE_READY; |
|
| 4085 | return HAL_ERROR; |
4085 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 4086 | } |
4086 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 4087 | } |
4087 | |
| 4088 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
4088 | return HAL_BUSY; |
| 4089 | } |
4089 | } |
| 4090 | 4090 | } |
|
| 4091 | /* Process Locked */ |
4091 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET); |
| 4092 | __HAL_LOCK(hi2c); |
4092 | } |
| 4093 | 4093 | ||
| 4094 | /* Check if the I2C is already enabled */ |
4094 | /* Process Locked */ |
| 4095 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
4095 | __HAL_LOCK(hi2c); |
| 4096 | { |
4096 | |
| 4097 | /* Enable I2C peripheral */ |
4097 | /* Check if the I2C is already enabled */ |
| 4098 | __HAL_I2C_ENABLE(hi2c); |
4098 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 4099 | } |
4099 | { |
| 4100 | 4100 | /* Enable I2C peripheral */ |
|
| 4101 | /* Disable Pos */ |
4101 | __HAL_I2C_ENABLE(hi2c); |
| 4102 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
4102 | } |
| 4103 | 4103 | ||
| 4104 | /* Clear Last DMA bit */ |
4104 | /* Disable Pos */ |
| 4105 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
4105 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 4106 | 4106 | ||
| 4107 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
4107 | /* Clear Last DMA bit */ |
| 4108 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
4108 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
| 4109 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
4109 | |
| 4110 | 4110 | hi2c->State = HAL_I2C_STATE_BUSY_RX; |
|
| 4111 | /* Prepare transfer parameters */ |
4111 | hi2c->Mode = HAL_I2C_MODE_MASTER; |
| 4112 | hi2c->pBuffPtr = pData; |
4112 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 4113 | hi2c->XferCount = Size; |
4113 | |
| 4114 | hi2c->XferSize = hi2c->XferCount; |
4114 | /* Prepare transfer parameters */ |
| 4115 | hi2c->XferOptions = XferOptions; |
4115 | hi2c->pBuffPtr = pData; |
| 4116 | hi2c->Devaddress = DevAddress; |
4116 | hi2c->XferCount = Size; |
| 4117 | 4117 | hi2c->XferSize = hi2c->XferCount; |
|
| 4118 | Prev_State = hi2c->PreviousState; |
4118 | hi2c->XferOptions = XferOptions; |
| 4119 | 4119 | hi2c->Devaddress = DevAddress; |
|
| 4120 | if (hi2c->XferSize > 0U) |
4120 | |
| 4121 | { |
4121 | Prev_State = hi2c->PreviousState; |
| 4122 | if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) |
4122 | |
| 4123 | { |
4123 | if (hi2c->XferSize > 0U) |
| 4124 | if (Prev_State == I2C_STATE_MASTER_BUSY_RX) |
4124 | { |
| 4125 | { |
4125 | if ((hi2c->XferCount == 2U) && ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP))) |
| 4126 | /* Disable Acknowledge */ |
4126 | { |
| 4127 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
4127 | if (Prev_State == I2C_STATE_MASTER_BUSY_RX) |
| 4128 | 4128 | { |
|
| 4129 | /* Enable Pos */ |
4129 | /* Disable Acknowledge */ |
| 4130 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
4130 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4131 | 4131 | ||
| 4132 | /* Enable Last DMA bit */ |
4132 | /* Enable Pos */ |
| 4133 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
4133 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 4134 | } |
4134 | |
| 4135 | else |
4135 | /* Enable Last DMA bit */ |
| 4136 | { |
4136 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
| 4137 | /* Enable Acknowledge */ |
4137 | } |
| 4138 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
4138 | else |
| 4139 | } |
4139 | { |
| 4140 | } |
4140 | /* Enable Acknowledge */ |
| 4141 | else |
4141 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4142 | { |
4142 | } |
| 4143 | /* Enable Acknowledge */ |
4143 | } |
| 4144 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
4144 | else |
| 4145 | 4145 | { |
|
| 4146 | if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
4146 | /* Enable Acknowledge */ |
| 4147 | { |
4147 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4148 | /* Enable Last DMA bit */ |
4148 | |
| 4149 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
4149 | if ((XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_OTHER_AND_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
| 4150 | } |
4150 | { |
| 4151 | } |
4151 | /* Enable Last DMA bit */ |
| 4152 | if (hi2c->hdmarx != NULL) |
4152 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
| 4153 | { |
4153 | } |
| 4154 | /* Set the I2C DMA transfer complete callback */ |
4154 | } |
| 4155 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
4155 | if (hi2c->hdmarx != NULL) |
| 4156 | 4156 | { |
|
| 4157 | /* Set the DMA error callback */ |
4157 | /* Set the I2C DMA transfer complete callback */ |
| 4158 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
4158 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
| 4159 | 4159 | ||
| 4160 | /* Set the unused DMA callbacks to NULL */ |
4160 | /* Set the DMA error callback */ |
| 4161 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
4161 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
| 4162 | hi2c->hdmarx->XferAbortCallback = NULL; |
4162 | |
| 4163 | 4163 | /* Set the unused DMA callbacks to NULL */ |
|
| 4164 | /* Enable the DMA channel */ |
4164 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
| 4165 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
4165 | hi2c->hdmarx->XferAbortCallback = NULL; |
| 4166 | } |
4166 | |
| 4167 | else |
4167 | /* Enable the DMA channel */ |
| 4168 | { |
4168 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
| 4169 | /* Update I2C state */ |
4169 | } |
| 4170 | hi2c->State = HAL_I2C_STATE_READY; |
4170 | else |
| 4171 | hi2c->Mode = HAL_I2C_MODE_NONE; |
4171 | { |
| 4172 | 4172 | /* Update I2C state */ |
|
| 4173 | /* Update I2C error code */ |
4173 | hi2c->State = HAL_I2C_STATE_READY; |
| 4174 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
4174 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 4175 | 4175 | ||
| 4176 | /* Process Unlocked */ |
4176 | /* Update I2C error code */ |
| 4177 | __HAL_UNLOCK(hi2c); |
4177 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
| 4178 | 4178 | ||
| 4179 | return HAL_ERROR; |
4179 | /* Process Unlocked */ |
| 4180 | } |
4180 | __HAL_UNLOCK(hi2c); |
| 4181 | if (dmaxferstatus == HAL_OK) |
4181 | |
| 4182 | { |
4182 | return HAL_ERROR; |
| 4183 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
4183 | } |
| 4184 | /* Mean Previous state is same as current state */ |
4184 | if (dmaxferstatus == HAL_OK) |
| 4185 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
4185 | { |
| 4186 | { |
4186 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
| 4187 | /* Generate Start */ |
4187 | /* Mean Previous state is same as current state */ |
| 4188 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
4188 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
| 4189 | 4189 | { |
|
| 4190 | /* Update interrupt for only EVT and ERR */ |
4190 | /* Generate Start */ |
| 4191 | enableIT = (I2C_IT_EVT | I2C_IT_ERR); |
4191 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 4192 | } |
4192 | |
| 4193 | else |
4193 | /* Update interrupt for only EVT and ERR */ |
| 4194 | { |
4194 | enableIT = (I2C_IT_EVT | I2C_IT_ERR); |
| 4195 | /* Update interrupt for only ERR */ |
4195 | } |
| 4196 | enableIT = I2C_IT_ERR; |
4196 | else |
| 4197 | } |
4197 | { |
| 4198 | 4198 | /* Update interrupt for only ERR */ |
|
| 4199 | /* Process Unlocked */ |
4199 | enableIT = I2C_IT_ERR; |
| 4200 | __HAL_UNLOCK(hi2c); |
4200 | } |
| 4201 | 4201 | ||
| 4202 | /* Note : The I2C interrupts must be enabled after unlocking current process |
4202 | /* Process Unlocked */ |
| 4203 | to avoid the risk of I2C interrupt handle execution before current |
4203 | __HAL_UNLOCK(hi2c); |
| 4204 | process unlock */ |
4204 | |
| 4205 | 4205 | /* Note : The I2C interrupts must be enabled after unlocking current process |
|
| 4206 | /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ |
4206 | to avoid the risk of I2C interrupt handle execution before current |
| 4207 | /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ |
4207 | process unlock */ |
| 4208 | if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
4208 | |
| 4209 | { |
4209 | /* If XferOptions is not associated to a new frame, mean no start bit is request, enable directly the DMA request */ |
| 4210 | /* Enable DMA Request */ |
4210 | /* In other cases, DMA request is enabled after Slave address treatment in IRQHandler */ |
| 4211 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
4211 | if ((XferOptions == I2C_NEXT_FRAME) || (XferOptions == I2C_LAST_FRAME) || (XferOptions == I2C_LAST_FRAME_NO_STOP)) |
| 4212 | } |
4212 | { |
| 4213 | 4213 | /* Enable DMA Request */ |
|
| 4214 | /* Enable EVT and ERR interrupt */ |
4214 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 4215 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
4215 | } |
| 4216 | } |
4216 | |
| 4217 | else |
4217 | /* Enable EVT and ERR interrupt */ |
| 4218 | { |
4218 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
| 4219 | /* Update I2C state */ |
4219 | } |
| 4220 | hi2c->State = HAL_I2C_STATE_READY; |
4220 | else |
| 4221 | hi2c->Mode = HAL_I2C_MODE_NONE; |
4221 | { |
| 4222 | 4222 | /* Update I2C state */ |
|
| 4223 | /* Update I2C error code */ |
4223 | hi2c->State = HAL_I2C_STATE_READY; |
| 4224 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
4224 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 4225 | 4225 | ||
| 4226 | /* Process Unlocked */ |
4226 | /* Update I2C error code */ |
| 4227 | __HAL_UNLOCK(hi2c); |
4227 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
| 4228 | 4228 | ||
| 4229 | return HAL_ERROR; |
4229 | /* Process Unlocked */ |
| 4230 | } |
4230 | __HAL_UNLOCK(hi2c); |
| 4231 | } |
4231 | |
| 4232 | else |
4232 | return HAL_ERROR; |
| 4233 | { |
4233 | } |
| 4234 | /* Enable Acknowledge */ |
4234 | } |
| 4235 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
4235 | else |
| 4236 | 4236 | { |
|
| 4237 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
4237 | /* Enable Acknowledge */ |
| 4238 | /* Mean Previous state is same as current state */ |
4238 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4239 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
4239 | |
| 4240 | { |
4240 | /* If transfer direction not change and there is no request to start another frame, do not generate Restart Condition */ |
| 4241 | /* Generate Start */ |
4241 | /* Mean Previous state is same as current state */ |
| 4242 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
4242 | if ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 1)) |
| 4243 | } |
4243 | { |
| 4244 | 4244 | /* Generate Start */ |
|
| 4245 | /* Process Unlocked */ |
4245 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 4246 | __HAL_UNLOCK(hi2c); |
4246 | } |
| 4247 | 4247 | ||
| 4248 | /* Note : The I2C interrupts must be enabled after unlocking current process |
4248 | /* Process Unlocked */ |
| 4249 | to avoid the risk of I2C interrupt handle execution before current |
4249 | __HAL_UNLOCK(hi2c); |
| 4250 | process unlock */ |
4250 | |
| 4251 | 4251 | /* Note : The I2C interrupts must be enabled after unlocking current process |
|
| 4252 | /* Enable interrupts */ |
4252 | to avoid the risk of I2C interrupt handle execution before current |
| 4253 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
4253 | process unlock */ |
| 4254 | } |
4254 | |
| 4255 | return HAL_OK; |
4255 | /* Enable interrupts */ |
| 4256 | } |
4256 | __HAL_I2C_ENABLE_IT(hi2c, enableIT); |
| 4257 | else |
4257 | } |
| 4258 | { |
4258 | return HAL_OK; |
| 4259 | return HAL_BUSY; |
4259 | } |
| 4260 | } |
4260 | else |
| 4261 | } |
4261 | { |
| 4262 | 4262 | return HAL_BUSY; |
|
| 4263 | /** |
4263 | } |
| 4264 | * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt |
4264 | } |
| 4265 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
4265 | |
| 4266 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
4266 | /** |
| 4267 | * the configuration information for the specified I2C. |
4267 | * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with Interrupt |
| 4268 | * @param pData Pointer to data buffer |
4268 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
| 4269 | * @param Size Amount of data to be sent |
4269 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 4270 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
4270 | * the configuration information for the specified I2C. |
| 4271 | * @retval HAL status |
4271 | * @param pData Pointer to data buffer |
| 4272 | */ |
4272 | * @param Size Amount of data to be sent |
| 4273 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
4273 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
| 4274 | { |
4274 | * @retval HAL status |
| 4275 | /* Check the parameters */ |
4275 | */ |
| 4276 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
4276 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
| 4277 | 4277 | { |
|
| 4278 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
4278 | /* Check the parameters */ |
| 4279 | { |
4279 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
| 4280 | if ((pData == NULL) || (Size == 0U)) |
4280 | |
| 4281 | { |
4281 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
| 4282 | return HAL_ERROR; |
4282 | { |
| 4283 | } |
4283 | if ((pData == NULL) || (Size == 0U)) |
| 4284 | 4284 | { |
|
| 4285 | /* Process Locked */ |
4285 | return HAL_ERROR; |
| 4286 | __HAL_LOCK(hi2c); |
4286 | } |
| 4287 | 4287 | ||
| 4288 | /* Check if the I2C is already enabled */ |
4288 | /* Process Locked */ |
| 4289 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
4289 | __HAL_LOCK(hi2c); |
| 4290 | { |
4290 | |
| 4291 | /* Enable I2C peripheral */ |
4291 | /* Check if the I2C is already enabled */ |
| 4292 | __HAL_I2C_ENABLE(hi2c); |
4292 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 4293 | } |
4293 | { |
| 4294 | 4294 | /* Enable I2C peripheral */ |
|
| 4295 | /* Disable Pos */ |
4295 | __HAL_I2C_ENABLE(hi2c); |
| 4296 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
4296 | } |
| 4297 | 4297 | ||
| 4298 | hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; |
4298 | /* Disable Pos */ |
| 4299 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
4299 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 4300 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
4300 | |
| 4301 | 4301 | hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; |
|
| 4302 | /* Prepare transfer parameters */ |
4302 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
| 4303 | hi2c->pBuffPtr = pData; |
4303 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 4304 | hi2c->XferCount = Size; |
4304 | |
| 4305 | hi2c->XferSize = hi2c->XferCount; |
4305 | /* Prepare transfer parameters */ |
| 4306 | hi2c->XferOptions = XferOptions; |
4306 | hi2c->pBuffPtr = pData; |
| 4307 | 4307 | hi2c->XferCount = Size; |
|
| 4308 | /* Clear ADDR flag */ |
4308 | hi2c->XferSize = hi2c->XferCount; |
| 4309 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
4309 | hi2c->XferOptions = XferOptions; |
| 4310 | 4310 | ||
| 4311 | /* Process Unlocked */ |
4311 | /* Clear ADDR flag */ |
| 4312 | __HAL_UNLOCK(hi2c); |
4312 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 4313 | 4313 | ||
| 4314 | /* Note : The I2C interrupts must be enabled after unlocking current process |
4314 | /* Process Unlocked */ |
| 4315 | to avoid the risk of I2C interrupt handle execution before current |
4315 | __HAL_UNLOCK(hi2c); |
| 4316 | process unlock */ |
4316 | |
| 4317 | 4317 | /* Note : The I2C interrupts must be enabled after unlocking current process |
|
| 4318 | /* Enable EVT, BUF and ERR interrupt */ |
4318 | to avoid the risk of I2C interrupt handle execution before current |
| 4319 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
4319 | process unlock */ |
| 4320 | 4320 | ||
| 4321 | return HAL_OK; |
4321 | /* Enable EVT, BUF and ERR interrupt */ |
| 4322 | } |
4322 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 4323 | else |
4323 | |
| 4324 | { |
4324 | return HAL_OK; |
| 4325 | return HAL_BUSY; |
4325 | } |
| 4326 | } |
4326 | else |
| 4327 | } |
4327 | { |
| 4328 | 4328 | return HAL_BUSY; |
|
| 4329 | /** |
4329 | } |
| 4330 | * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA |
4330 | } |
| 4331 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
4331 | |
| 4332 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
4332 | /** |
| 4333 | * the configuration information for the specified I2C. |
4333 | * @brief Sequential transmit in slave mode an amount of data in non-blocking mode with DMA |
| 4334 | * @param pData Pointer to data buffer |
4334 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
| 4335 | * @param Size Amount of data to be sent |
4335 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 4336 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
4336 | * the configuration information for the specified I2C. |
| 4337 | * @retval HAL status |
4337 | * @param pData Pointer to data buffer |
| 4338 | */ |
4338 | * @param Size Amount of data to be sent |
| 4339 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
4339 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
| 4340 | { |
4340 | * @retval HAL status |
| 4341 | HAL_StatusTypeDef dmaxferstatus; |
4341 | */ |
| 4342 | 4342 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
|
| 4343 | /* Check the parameters */ |
4343 | { |
| 4344 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
4344 | HAL_StatusTypeDef dmaxferstatus; |
| 4345 | 4345 | ||
| 4346 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
4346 | /* Check the parameters */ |
| 4347 | { |
4347 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
| 4348 | if ((pData == NULL) || (Size == 0U)) |
4348 | |
| 4349 | { |
4349 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
| 4350 | return HAL_ERROR; |
4350 | { |
| 4351 | } |
4351 | if ((pData == NULL) || (Size == 0U)) |
| 4352 | 4352 | { |
|
| 4353 | /* Process Locked */ |
4353 | return HAL_ERROR; |
| 4354 | __HAL_LOCK(hi2c); |
4354 | } |
| 4355 | 4355 | ||
| 4356 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
4356 | /* Process Locked */ |
| 4357 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
4357 | __HAL_LOCK(hi2c); |
| 4358 | 4358 | ||
| 4359 | /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ |
4359 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
| 4360 | /* and then toggle the HAL slave RX state to TX state */ |
4360 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 4361 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) |
4361 | |
| 4362 | { |
4362 | /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ |
| 4363 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
4363 | /* and then toggle the HAL slave RX state to TX state */ |
| 4364 | { |
4364 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) |
| 4365 | /* Abort DMA Xfer if any */ |
4365 | { |
| 4366 | if (hi2c->hdmarx != NULL) |
4366 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
| 4367 | { |
4367 | { |
| 4368 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
4368 | /* Abort DMA Xfer if any */ |
| 4369 | 4369 | if (hi2c->hdmarx != NULL) |
|
| 4370 | /* Set the I2C DMA Abort callback : |
4370 | { |
| 4371 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
4371 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 4372 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
4372 | |
| 4373 | 4373 | /* Set the I2C DMA Abort callback : |
|
| 4374 | /* Abort DMA RX */ |
4374 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
| 4375 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
4375 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
| 4376 | { |
4376 | |
| 4377 | /* Call Directly XferAbortCallback function in case of error */ |
4377 | /* Abort DMA RX */ |
| 4378 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
4378 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
| 4379 | } |
4379 | { |
| 4380 | } |
4380 | /* Call Directly XferAbortCallback function in case of error */ |
| 4381 | } |
4381 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
| 4382 | } |
4382 | } |
| 4383 | else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) |
4383 | } |
| 4384 | { |
4384 | } |
| 4385 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
4385 | } |
| 4386 | { |
4386 | else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) |
| 4387 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
4387 | { |
| 4388 | 4388 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
|
| 4389 | /* Abort DMA Xfer if any */ |
4389 | { |
| 4390 | if (hi2c->hdmatx != NULL) |
4390 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 4391 | { |
4391 | |
| 4392 | /* Set the I2C DMA Abort callback : |
4392 | /* Abort DMA Xfer if any */ |
| 4393 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
4393 | if (hi2c->hdmatx != NULL) |
| 4394 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
4394 | { |
| 4395 | 4395 | /* Set the I2C DMA Abort callback : |
|
| 4396 | /* Abort DMA TX */ |
4396 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
| 4397 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
4397 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
| 4398 | { |
4398 | |
| 4399 | /* Call Directly XferAbortCallback function in case of error */ |
4399 | /* Abort DMA TX */ |
| 4400 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
4400 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
| 4401 | } |
4401 | { |
| 4402 | } |
4402 | /* Call Directly XferAbortCallback function in case of error */ |
| 4403 | } |
4403 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
| 4404 | } |
4404 | } |
| 4405 | else |
4405 | } |
| 4406 | { |
4406 | } |
| 4407 | /* Nothing to do */ |
4407 | } |
| 4408 | } |
4408 | else |
| 4409 | 4409 | { |
|
| 4410 | /* Check if the I2C is already enabled */ |
4410 | /* Nothing to do */ |
| 4411 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
4411 | } |
| 4412 | { |
4412 | |
| 4413 | /* Enable I2C peripheral */ |
4413 | /* Check if the I2C is already enabled */ |
| 4414 | __HAL_I2C_ENABLE(hi2c); |
4414 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 4415 | } |
4415 | { |
| 4416 | 4416 | /* Enable I2C peripheral */ |
|
| 4417 | /* Disable Pos */ |
4417 | __HAL_I2C_ENABLE(hi2c); |
| 4418 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
4418 | } |
| 4419 | 4419 | ||
| 4420 | hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; |
4420 | /* Disable Pos */ |
| 4421 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
4421 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 4422 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
4422 | |
| 4423 | 4423 | hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; |
|
| 4424 | /* Prepare transfer parameters */ |
4424 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
| 4425 | hi2c->pBuffPtr = pData; |
4425 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 4426 | hi2c->XferCount = Size; |
4426 | |
| 4427 | hi2c->XferSize = hi2c->XferCount; |
4427 | /* Prepare transfer parameters */ |
| 4428 | hi2c->XferOptions = XferOptions; |
4428 | hi2c->pBuffPtr = pData; |
| 4429 | 4429 | hi2c->XferCount = Size; |
|
| 4430 | if (hi2c->hdmatx != NULL) |
4430 | hi2c->XferSize = hi2c->XferCount; |
| 4431 | { |
4431 | hi2c->XferOptions = XferOptions; |
| 4432 | /* Set the I2C DMA transfer complete callback */ |
4432 | |
| 4433 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
4433 | if (hi2c->hdmatx != NULL) |
| 4434 | 4434 | { |
|
| 4435 | /* Set the DMA error callback */ |
4435 | /* Set the I2C DMA transfer complete callback */ |
| 4436 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
4436 | hi2c->hdmatx->XferCpltCallback = I2C_DMAXferCplt; |
| 4437 | 4437 | ||
| 4438 | /* Set the unused DMA callbacks to NULL */ |
4438 | /* Set the DMA error callback */ |
| 4439 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
4439 | hi2c->hdmatx->XferErrorCallback = I2C_DMAError; |
| 4440 | hi2c->hdmatx->XferAbortCallback = NULL; |
4440 | |
| 4441 | 4441 | /* Set the unused DMA callbacks to NULL */ |
|
| 4442 | /* Enable the DMA channel */ |
4442 | hi2c->hdmatx->XferHalfCpltCallback = NULL; |
| 4443 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
4443 | hi2c->hdmatx->XferAbortCallback = NULL; |
| 4444 | } |
4444 | |
| 4445 | else |
4445 | /* Enable the DMA channel */ |
| 4446 | { |
4446 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->DR, hi2c->XferSize); |
| 4447 | /* Update I2C state */ |
4447 | } |
| 4448 | hi2c->State = HAL_I2C_STATE_LISTEN; |
4448 | else |
| 4449 | hi2c->Mode = HAL_I2C_MODE_NONE; |
4449 | { |
| 4450 | 4450 | /* Update I2C state */ |
|
| 4451 | /* Update I2C error code */ |
4451 | hi2c->State = HAL_I2C_STATE_LISTEN; |
| 4452 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
4452 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 4453 | 4453 | ||
| 4454 | /* Process Unlocked */ |
4454 | /* Update I2C error code */ |
| 4455 | __HAL_UNLOCK(hi2c); |
4455 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
| 4456 | 4456 | ||
| 4457 | return HAL_ERROR; |
4457 | /* Process Unlocked */ |
| 4458 | } |
4458 | __HAL_UNLOCK(hi2c); |
| 4459 | 4459 | ||
| 4460 | if (dmaxferstatus == HAL_OK) |
4460 | return HAL_ERROR; |
| 4461 | { |
4461 | } |
| 4462 | /* Enable Address Acknowledge */ |
4462 | |
| 4463 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
4463 | if (dmaxferstatus == HAL_OK) |
| 4464 | 4464 | { |
|
| 4465 | /* Clear ADDR flag */ |
4465 | /* Enable Address Acknowledge */ |
| 4466 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
4466 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4467 | 4467 | ||
| 4468 | /* Process Unlocked */ |
4468 | /* Clear ADDR flag */ |
| 4469 | __HAL_UNLOCK(hi2c); |
4469 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 4470 | 4470 | ||
| 4471 | /* Note : The I2C interrupts must be enabled after unlocking current process |
4471 | /* Process Unlocked */ |
| 4472 | to avoid the risk of I2C interrupt handle execution before current |
4472 | __HAL_UNLOCK(hi2c); |
| 4473 | process unlock */ |
4473 | |
| 4474 | /* Enable EVT and ERR interrupt */ |
4474 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 4475 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
4475 | to avoid the risk of I2C interrupt handle execution before current |
| 4476 | 4476 | process unlock */ |
|
| 4477 | /* Enable DMA Request */ |
4477 | /* Enable EVT and ERR interrupt */ |
| 4478 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
4478 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 4479 | 4479 | ||
| 4480 | return HAL_OK; |
4480 | /* Enable DMA Request */ |
| 4481 | } |
4481 | hi2c->Instance->CR2 |= I2C_CR2_DMAEN; |
| 4482 | else |
4482 | |
| 4483 | { |
4483 | return HAL_OK; |
| 4484 | /* Update I2C state */ |
4484 | } |
| 4485 | hi2c->State = HAL_I2C_STATE_READY; |
4485 | else |
| 4486 | hi2c->Mode = HAL_I2C_MODE_NONE; |
4486 | { |
| 4487 | 4487 | /* Update I2C state */ |
|
| 4488 | /* Update I2C error code */ |
4488 | hi2c->State = HAL_I2C_STATE_READY; |
| 4489 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
4489 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 4490 | 4490 | ||
| 4491 | /* Process Unlocked */ |
4491 | /* Update I2C error code */ |
| 4492 | __HAL_UNLOCK(hi2c); |
4492 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
| 4493 | 4493 | ||
| 4494 | return HAL_ERROR; |
4494 | /* Process Unlocked */ |
| 4495 | } |
4495 | __HAL_UNLOCK(hi2c); |
| 4496 | } |
4496 | |
| 4497 | else |
4497 | return HAL_ERROR; |
| 4498 | { |
4498 | } |
| 4499 | return HAL_BUSY; |
4499 | } |
| 4500 | } |
4500 | else |
| 4501 | } |
4501 | { |
| 4502 | 4502 | return HAL_BUSY; |
|
| 4503 | /** |
4503 | } |
| 4504 | * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt |
4504 | } |
| 4505 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
4505 | |
| 4506 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
4506 | /** |
| 4507 | * the configuration information for the specified I2C. |
4507 | * @brief Sequential receive in slave mode an amount of data in non-blocking mode with Interrupt |
| 4508 | * @param pData Pointer to data buffer |
4508 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
| 4509 | * @param Size Amount of data to be sent |
4509 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 4510 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
4510 | * the configuration information for the specified I2C. |
| 4511 | * @retval HAL status |
4511 | * @param pData Pointer to data buffer |
| 4512 | */ |
4512 | * @param Size Amount of data to be sent |
| 4513 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
4513 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
| 4514 | { |
4514 | * @retval HAL status |
| 4515 | /* Check the parameters */ |
4515 | */ |
| 4516 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
4516 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
| 4517 | 4517 | { |
|
| 4518 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
4518 | /* Check the parameters */ |
| 4519 | { |
4519 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
| 4520 | if ((pData == NULL) || (Size == 0U)) |
4520 | |
| 4521 | { |
4521 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
| 4522 | return HAL_ERROR; |
4522 | { |
| 4523 | } |
4523 | if ((pData == NULL) || (Size == 0U)) |
| 4524 | 4524 | { |
|
| 4525 | /* Process Locked */ |
4525 | return HAL_ERROR; |
| 4526 | __HAL_LOCK(hi2c); |
4526 | } |
| 4527 | 4527 | ||
| 4528 | /* Check if the I2C is already enabled */ |
4528 | /* Process Locked */ |
| 4529 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
4529 | __HAL_LOCK(hi2c); |
| 4530 | { |
4530 | |
| 4531 | /* Enable I2C peripheral */ |
4531 | /* Check if the I2C is already enabled */ |
| 4532 | __HAL_I2C_ENABLE(hi2c); |
4532 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 4533 | } |
4533 | { |
| 4534 | 4534 | /* Enable I2C peripheral */ |
|
| 4535 | /* Disable Pos */ |
4535 | __HAL_I2C_ENABLE(hi2c); |
| 4536 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
4536 | } |
| 4537 | 4537 | ||
| 4538 | hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; |
4538 | /* Disable Pos */ |
| 4539 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
4539 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 4540 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
4540 | |
| 4541 | 4541 | hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; |
|
| 4542 | /* Prepare transfer parameters */ |
4542 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
| 4543 | hi2c->pBuffPtr = pData; |
4543 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 4544 | hi2c->XferCount = Size; |
4544 | |
| 4545 | hi2c->XferSize = hi2c->XferCount; |
4545 | /* Prepare transfer parameters */ |
| 4546 | hi2c->XferOptions = XferOptions; |
4546 | hi2c->pBuffPtr = pData; |
| 4547 | 4547 | hi2c->XferCount = Size; |
|
| 4548 | /* Clear ADDR flag */ |
4548 | hi2c->XferSize = hi2c->XferCount; |
| 4549 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
4549 | hi2c->XferOptions = XferOptions; |
| 4550 | 4550 | ||
| 4551 | /* Process Unlocked */ |
4551 | /* Clear ADDR flag */ |
| 4552 | __HAL_UNLOCK(hi2c); |
4552 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 4553 | 4553 | ||
| 4554 | /* Note : The I2C interrupts must be enabled after unlocking current process |
4554 | /* Process Unlocked */ |
| 4555 | to avoid the risk of I2C interrupt handle execution before current |
4555 | __HAL_UNLOCK(hi2c); |
| 4556 | process unlock */ |
4556 | |
| 4557 | 4557 | /* Note : The I2C interrupts must be enabled after unlocking current process |
|
| 4558 | /* Enable EVT, BUF and ERR interrupt */ |
4558 | to avoid the risk of I2C interrupt handle execution before current |
| 4559 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
4559 | process unlock */ |
| 4560 | 4560 | ||
| 4561 | return HAL_OK; |
4561 | /* Enable EVT, BUF and ERR interrupt */ |
| 4562 | } |
4562 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 4563 | else |
4563 | |
| 4564 | { |
4564 | return HAL_OK; |
| 4565 | return HAL_BUSY; |
4565 | } |
| 4566 | } |
4566 | else |
| 4567 | } |
4567 | { |
| 4568 | 4568 | return HAL_BUSY; |
|
| 4569 | /** |
4569 | } |
| 4570 | * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA |
4570 | } |
| 4571 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
4571 | |
| 4572 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
4572 | /** |
| 4573 | * the configuration information for the specified I2C. |
4573 | * @brief Sequential receive in slave mode an amount of data in non-blocking mode with DMA |
| 4574 | * @param pData Pointer to data buffer |
4574 | * @note This interface allow to manage repeated start condition when a direction change during transfer |
| 4575 | * @param Size Amount of data to be sent |
4575 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 4576 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
4576 | * the configuration information for the specified I2C. |
| 4577 | * @retval HAL status |
4577 | * @param pData Pointer to data buffer |
| 4578 | */ |
4578 | * @param Size Amount of data to be sent |
| 4579 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
4579 | * @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition |
| 4580 | { |
4580 | * @retval HAL status |
| 4581 | HAL_StatusTypeDef dmaxferstatus; |
4581 | */ |
| 4582 | 4582 | HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions) |
|
| 4583 | /* Check the parameters */ |
4583 | { |
| 4584 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
4584 | HAL_StatusTypeDef dmaxferstatus; |
| 4585 | 4585 | ||
| 4586 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
4586 | /* Check the parameters */ |
| 4587 | { |
4587 | assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); |
| 4588 | if ((pData == NULL) || (Size == 0U)) |
4588 | |
| 4589 | { |
4589 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
| 4590 | return HAL_ERROR; |
4590 | { |
| 4591 | } |
4591 | if ((pData == NULL) || (Size == 0U)) |
| 4592 | 4592 | { |
|
| 4593 | /* Process Locked */ |
4593 | return HAL_ERROR; |
| 4594 | __HAL_LOCK(hi2c); |
4594 | } |
| 4595 | 4595 | ||
| 4596 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
4596 | /* Process Locked */ |
| 4597 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
4597 | __HAL_LOCK(hi2c); |
| 4598 | 4598 | ||
| 4599 | /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ |
4599 | /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ |
| 4600 | /* and then toggle the HAL slave RX state to TX state */ |
4600 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 4601 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) |
4601 | |
| 4602 | { |
4602 | /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ |
| 4603 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
4603 | /* and then toggle the HAL slave RX state to TX state */ |
| 4604 | { |
4604 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) |
| 4605 | /* Abort DMA Xfer if any */ |
4605 | { |
| 4606 | if (hi2c->hdmarx != NULL) |
4606 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
| 4607 | { |
4607 | { |
| 4608 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
4608 | /* Abort DMA Xfer if any */ |
| 4609 | 4609 | if (hi2c->hdmarx != NULL) |
|
| 4610 | /* Set the I2C DMA Abort callback : |
4610 | { |
| 4611 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
4611 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 4612 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
4612 | |
| 4613 | 4613 | /* Set the I2C DMA Abort callback : |
|
| 4614 | /* Abort DMA RX */ |
4614 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
| 4615 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
4615 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
| 4616 | { |
4616 | |
| 4617 | /* Call Directly XferAbortCallback function in case of error */ |
4617 | /* Abort DMA RX */ |
| 4618 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
4618 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
| 4619 | } |
4619 | { |
| 4620 | } |
4620 | /* Call Directly XferAbortCallback function in case of error */ |
| 4621 | } |
4621 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
| 4622 | } |
4622 | } |
| 4623 | else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) |
4623 | } |
| 4624 | { |
4624 | } |
| 4625 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
4625 | } |
| 4626 | { |
4626 | else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) |
| 4627 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
4627 | { |
| 4628 | 4628 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
|
| 4629 | /* Abort DMA Xfer if any */ |
4629 | { |
| 4630 | if (hi2c->hdmatx != NULL) |
4630 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 4631 | { |
4631 | |
| 4632 | /* Set the I2C DMA Abort callback : |
4632 | /* Abort DMA Xfer if any */ |
| 4633 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
4633 | if (hi2c->hdmatx != NULL) |
| 4634 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
4634 | { |
| 4635 | 4635 | /* Set the I2C DMA Abort callback : |
|
| 4636 | /* Abort DMA TX */ |
4636 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
| 4637 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
4637 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
| 4638 | { |
4638 | |
| 4639 | /* Call Directly XferAbortCallback function in case of error */ |
4639 | /* Abort DMA TX */ |
| 4640 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
4640 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
| 4641 | } |
4641 | { |
| 4642 | } |
4642 | /* Call Directly XferAbortCallback function in case of error */ |
| 4643 | } |
4643 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
| 4644 | } |
4644 | } |
| 4645 | else |
4645 | } |
| 4646 | { |
4646 | } |
| 4647 | /* Nothing to do */ |
4647 | } |
| 4648 | } |
4648 | else |
| 4649 | 4649 | { |
|
| 4650 | /* Check if the I2C is already enabled */ |
4650 | /* Nothing to do */ |
| 4651 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
4651 | } |
| 4652 | { |
4652 | |
| 4653 | /* Enable I2C peripheral */ |
4653 | /* Check if the I2C is already enabled */ |
| 4654 | __HAL_I2C_ENABLE(hi2c); |
4654 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 4655 | } |
4655 | { |
| 4656 | 4656 | /* Enable I2C peripheral */ |
|
| 4657 | /* Disable Pos */ |
4657 | __HAL_I2C_ENABLE(hi2c); |
| 4658 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
4658 | } |
| 4659 | 4659 | ||
| 4660 | hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; |
4660 | /* Disable Pos */ |
| 4661 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
4661 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 4662 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
4662 | |
| 4663 | 4663 | hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; |
|
| 4664 | /* Prepare transfer parameters */ |
4664 | hi2c->Mode = HAL_I2C_MODE_SLAVE; |
| 4665 | hi2c->pBuffPtr = pData; |
4665 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 4666 | hi2c->XferCount = Size; |
4666 | |
| 4667 | hi2c->XferSize = hi2c->XferCount; |
4667 | /* Prepare transfer parameters */ |
| 4668 | hi2c->XferOptions = XferOptions; |
4668 | hi2c->pBuffPtr = pData; |
| 4669 | 4669 | hi2c->XferCount = Size; |
|
| 4670 | if (hi2c->hdmarx != NULL) |
4670 | hi2c->XferSize = hi2c->XferCount; |
| 4671 | { |
4671 | hi2c->XferOptions = XferOptions; |
| 4672 | /* Set the I2C DMA transfer complete callback */ |
4672 | |
| 4673 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
4673 | if (hi2c->hdmarx != NULL) |
| 4674 | 4674 | { |
|
| 4675 | /* Set the DMA error callback */ |
4675 | /* Set the I2C DMA transfer complete callback */ |
| 4676 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
4676 | hi2c->hdmarx->XferCpltCallback = I2C_DMAXferCplt; |
| 4677 | 4677 | ||
| 4678 | /* Set the unused DMA callbacks to NULL */ |
4678 | /* Set the DMA error callback */ |
| 4679 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
4679 | hi2c->hdmarx->XferErrorCallback = I2C_DMAError; |
| 4680 | hi2c->hdmarx->XferAbortCallback = NULL; |
4680 | |
| 4681 | 4681 | /* Set the unused DMA callbacks to NULL */ |
|
| 4682 | /* Enable the DMA channel */ |
4682 | hi2c->hdmarx->XferHalfCpltCallback = NULL; |
| 4683 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
4683 | hi2c->hdmarx->XferAbortCallback = NULL; |
| 4684 | } |
4684 | |
| 4685 | else |
4685 | /* Enable the DMA channel */ |
| 4686 | { |
4686 | dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize); |
| 4687 | /* Update I2C state */ |
4687 | } |
| 4688 | hi2c->State = HAL_I2C_STATE_LISTEN; |
4688 | else |
| 4689 | hi2c->Mode = HAL_I2C_MODE_NONE; |
4689 | { |
| 4690 | 4690 | /* Update I2C state */ |
|
| 4691 | /* Update I2C error code */ |
4691 | hi2c->State = HAL_I2C_STATE_LISTEN; |
| 4692 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
4692 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 4693 | 4693 | ||
| 4694 | /* Process Unlocked */ |
4694 | /* Update I2C error code */ |
| 4695 | __HAL_UNLOCK(hi2c); |
4695 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; |
| 4696 | 4696 | ||
| 4697 | return HAL_ERROR; |
4697 | /* Process Unlocked */ |
| 4698 | } |
4698 | __HAL_UNLOCK(hi2c); |
| 4699 | 4699 | ||
| 4700 | if (dmaxferstatus == HAL_OK) |
4700 | return HAL_ERROR; |
| 4701 | { |
4701 | } |
| 4702 | /* Enable Address Acknowledge */ |
4702 | |
| 4703 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
4703 | if (dmaxferstatus == HAL_OK) |
| 4704 | 4704 | { |
|
| 4705 | /* Clear ADDR flag */ |
4705 | /* Enable Address Acknowledge */ |
| 4706 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
4706 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4707 | 4707 | ||
| 4708 | /* Process Unlocked */ |
4708 | /* Clear ADDR flag */ |
| 4709 | __HAL_UNLOCK(hi2c); |
4709 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 4710 | 4710 | ||
| 4711 | /* Enable DMA Request */ |
4711 | /* Process Unlocked */ |
| 4712 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
4712 | __HAL_UNLOCK(hi2c); |
| 4713 | 4713 | ||
| 4714 | /* Note : The I2C interrupts must be enabled after unlocking current process |
4714 | /* Enable DMA Request */ |
| 4715 | to avoid the risk of I2C interrupt handle execution before current |
4715 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 4716 | process unlock */ |
4716 | |
| 4717 | /* Enable EVT and ERR interrupt */ |
4717 | /* Note : The I2C interrupts must be enabled after unlocking current process |
| 4718 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
4718 | to avoid the risk of I2C interrupt handle execution before current |
| 4719 | 4719 | process unlock */ |
|
| 4720 | return HAL_OK; |
4720 | /* Enable EVT and ERR interrupt */ |
| 4721 | } |
4721 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 4722 | else |
4722 | |
| 4723 | { |
4723 | return HAL_OK; |
| 4724 | /* Update I2C state */ |
4724 | } |
| 4725 | hi2c->State = HAL_I2C_STATE_READY; |
4725 | else |
| 4726 | hi2c->Mode = HAL_I2C_MODE_NONE; |
4726 | { |
| 4727 | 4727 | /* Update I2C state */ |
|
| 4728 | /* Update I2C error code */ |
4728 | hi2c->State = HAL_I2C_STATE_READY; |
| 4729 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
4729 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 4730 | 4730 | ||
| 4731 | /* Process Unlocked */ |
4731 | /* Update I2C error code */ |
| 4732 | __HAL_UNLOCK(hi2c); |
4732 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
| 4733 | 4733 | ||
| 4734 | return HAL_ERROR; |
4734 | /* Process Unlocked */ |
| 4735 | } |
4735 | __HAL_UNLOCK(hi2c); |
| 4736 | } |
4736 | |
| 4737 | else |
4737 | return HAL_ERROR; |
| 4738 | { |
4738 | } |
| 4739 | return HAL_BUSY; |
4739 | } |
| 4740 | } |
4740 | else |
| 4741 | } |
4741 | { |
| 4742 | 4742 | return HAL_BUSY; |
|
| 4743 | /** |
4743 | } |
| 4744 | * @brief Enable the Address listen mode with Interrupt. |
4744 | } |
| 4745 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
4745 | |
| 4746 | * the configuration information for the specified I2C. |
4746 | /** |
| 4747 | * @retval HAL status |
4747 | * @brief Enable the Address listen mode with Interrupt. |
| 4748 | */ |
4748 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 4749 | HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) |
4749 | * the configuration information for the specified I2C. |
| 4750 | { |
4750 | * @retval HAL status |
| 4751 | if (hi2c->State == HAL_I2C_STATE_READY) |
4751 | */ |
| 4752 | { |
4752 | HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) |
| 4753 | hi2c->State = HAL_I2C_STATE_LISTEN; |
4753 | { |
| 4754 | 4754 | if (hi2c->State == HAL_I2C_STATE_READY) |
|
| 4755 | /* Check if the I2C is already enabled */ |
4755 | { |
| 4756 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
4756 | hi2c->State = HAL_I2C_STATE_LISTEN; |
| 4757 | { |
4757 | |
| 4758 | /* Enable I2C peripheral */ |
4758 | /* Check if the I2C is already enabled */ |
| 4759 | __HAL_I2C_ENABLE(hi2c); |
4759 | if ((hi2c->Instance->CR1 & I2C_CR1_PE) != I2C_CR1_PE) |
| 4760 | } |
4760 | { |
| 4761 | 4761 | /* Enable I2C peripheral */ |
|
| 4762 | /* Enable Address Acknowledge */ |
4762 | __HAL_I2C_ENABLE(hi2c); |
| 4763 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
4763 | } |
| 4764 | 4764 | ||
| 4765 | /* Enable EVT and ERR interrupt */ |
4765 | /* Enable Address Acknowledge */ |
| 4766 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
4766 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4767 | 4767 | ||
| 4768 | return HAL_OK; |
4768 | /* Enable EVT and ERR interrupt */ |
| 4769 | } |
4769 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 4770 | else |
4770 | |
| 4771 | { |
4771 | return HAL_OK; |
| 4772 | return HAL_BUSY; |
4772 | } |
| 4773 | } |
4773 | else |
| 4774 | } |
4774 | { |
| 4775 | 4775 | return HAL_BUSY; |
|
| 4776 | /** |
4776 | } |
| 4777 | * @brief Disable the Address listen mode with Interrupt. |
4777 | } |
| 4778 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
4778 | |
| 4779 | * the configuration information for the specified I2C. |
4779 | /** |
| 4780 | * @retval HAL status |
4780 | * @brief Disable the Address listen mode with Interrupt. |
| 4781 | */ |
4781 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 4782 | HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) |
4782 | * the configuration information for the specified I2C. |
| 4783 | { |
4783 | * @retval HAL status |
| 4784 | /* Declaration of tmp to prevent undefined behavior of volatile usage */ |
4784 | */ |
| 4785 | uint32_t tmp; |
4785 | HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) |
| 4786 | 4786 | { |
|
| 4787 | /* Disable Address listen mode only if a transfer is not ongoing */ |
4787 | /* Declaration of tmp to prevent undefined behavior of volatile usage */ |
| 4788 | if (hi2c->State == HAL_I2C_STATE_LISTEN) |
4788 | uint32_t tmp; |
| 4789 | { |
4789 | |
| 4790 | tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; |
4790 | /* Disable Address listen mode only if a transfer is not ongoing */ |
| 4791 | hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); |
4791 | if (hi2c->State == HAL_I2C_STATE_LISTEN) |
| 4792 | hi2c->State = HAL_I2C_STATE_READY; |
4792 | { |
| 4793 | hi2c->Mode = HAL_I2C_MODE_NONE; |
4793 | tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; |
| 4794 | 4794 | hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); |
|
| 4795 | /* Disable Address Acknowledge */ |
4795 | hi2c->State = HAL_I2C_STATE_READY; |
| 4796 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
4796 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 4797 | 4797 | ||
| 4798 | /* Disable EVT and ERR interrupt */ |
4798 | /* Disable Address Acknowledge */ |
| 4799 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
4799 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4800 | 4800 | ||
| 4801 | return HAL_OK; |
4801 | /* Disable EVT and ERR interrupt */ |
| 4802 | } |
4802 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 4803 | else |
4803 | |
| 4804 | { |
4804 | return HAL_OK; |
| 4805 | return HAL_BUSY; |
4805 | } |
| 4806 | } |
4806 | else |
| 4807 | } |
4807 | { |
| 4808 | 4808 | return HAL_BUSY; |
|
| 4809 | /** |
4809 | } |
| 4810 | * @brief Abort a master I2C IT or DMA process communication with Interrupt. |
4810 | } |
| 4811 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
4811 | |
| 4812 | * the configuration information for the specified I2C. |
4812 | /** |
| 4813 | * @param DevAddress Target device address: The device 7 bits address value |
4813 | * @brief Abort a master I2C IT or DMA process communication with Interrupt. |
| 4814 | * in datasheet must be shifted to the left before calling the interface |
4814 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 4815 | * @retval HAL status |
4815 | * the configuration information for the specified I2C. |
| 4816 | */ |
4816 | * @param DevAddress Target device address: The device 7 bits address value |
| 4817 | HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) |
4817 | * in datasheet must be shifted to the left before calling the interface |
| 4818 | { |
4818 | * @retval HAL status |
| 4819 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
4819 | */ |
| 4820 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
4820 | HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) |
| 4821 | 4821 | { |
|
| 4822 | /* Prevent unused argument(s) compilation warning */ |
4822 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
| 4823 | UNUSED(DevAddress); |
4823 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
| 4824 | 4824 | ||
| 4825 | /* Abort Master transfer during Receive or Transmit process */ |
4825 | /* Prevent unused argument(s) compilation warning */ |
| 4826 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER)) |
4826 | UNUSED(DevAddress); |
| 4827 | { |
4827 | |
| 4828 | /* Process Locked */ |
4828 | /* Abort Master transfer during Receive or Transmit process */ |
| 4829 | __HAL_LOCK(hi2c); |
4829 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && (CurrentMode == HAL_I2C_MODE_MASTER)) |
| 4830 | 4830 | { |
|
| 4831 | hi2c->PreviousState = I2C_STATE_NONE; |
4831 | /* Process Locked */ |
| 4832 | hi2c->State = HAL_I2C_STATE_ABORT; |
4832 | __HAL_LOCK(hi2c); |
| 4833 | 4833 | ||
| 4834 | /* Disable Acknowledge */ |
4834 | hi2c->PreviousState = I2C_STATE_NONE; |
| 4835 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
4835 | hi2c->State = HAL_I2C_STATE_ABORT; |
| 4836 | 4836 | ||
| 4837 | /* Generate Stop */ |
4837 | /* Disable Acknowledge */ |
| 4838 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
4838 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 4839 | 4839 | ||
| 4840 | hi2c->XferCount = 0U; |
4840 | /* Generate Stop */ |
| 4841 | 4841 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
|
| 4842 | /* Disable EVT, BUF and ERR interrupt */ |
4842 | |
| 4843 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
4843 | hi2c->XferCount = 0U; |
| 4844 | 4844 | ||
| 4845 | /* Process Unlocked */ |
4845 | /* Disable EVT, BUF and ERR interrupt */ |
| 4846 | __HAL_UNLOCK(hi2c); |
4846 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 4847 | 4847 | ||
| 4848 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
4848 | /* Process Unlocked */ |
| 4849 | I2C_ITError(hi2c); |
4849 | __HAL_UNLOCK(hi2c); |
| 4850 | 4850 | ||
| 4851 | return HAL_OK; |
4851 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
| 4852 | } |
4852 | I2C_ITError(hi2c); |
| 4853 | else |
4853 | |
| 4854 | { |
4854 | return HAL_OK; |
| 4855 | /* Wrong usage of abort function */ |
4855 | } |
| 4856 | /* This function should be used only in case of abort monitored by master device */ |
4856 | else |
| 4857 | /* Or periphal is not in busy state, mean there is no active sequence to be abort */ |
4857 | { |
| 4858 | return HAL_ERROR; |
4858 | /* Wrong usage of abort function */ |
| 4859 | } |
4859 | /* This function should be used only in case of abort monitored by master device */ |
| 4860 | } |
4860 | /* Or periphal is not in busy state, mean there is no active sequence to be abort */ |
| 4861 | 4861 | return HAL_ERROR; |
|
| 4862 | /** |
4862 | } |
| 4863 | * @} |
4863 | } |
| 4864 | */ |
4864 | |
| 4865 | 4865 | /** |
|
| 4866 | /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
4866 | * @} |
| 4867 | * @{ |
4867 | */ |
| 4868 | */ |
4868 | |
| 4869 | 4869 | /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
|
| 4870 | /** |
4870 | * @{ |
| 4871 | * @brief This function handles I2C event interrupt request. |
4871 | */ |
| 4872 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
4872 | |
| 4873 | * the configuration information for the specified I2C. |
4873 | /** |
| 4874 | * @retval None |
4874 | * @brief This function handles I2C event interrupt request. |
| 4875 | */ |
4875 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 4876 | void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) |
4876 | * the configuration information for the specified I2C. |
| 4877 | { |
4877 | * @retval None |
| 4878 | uint32_t sr1itflags; |
4878 | */ |
| 4879 | uint32_t sr2itflags = 0U; |
4879 | void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) |
| 4880 | uint32_t itsources = READ_REG(hi2c->Instance->CR2); |
4880 | { |
| 4881 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
4881 | uint32_t sr1itflags; |
| 4882 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
4882 | uint32_t sr2itflags = 0U; |
| 4883 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
4883 | uint32_t itsources = READ_REG(hi2c->Instance->CR2); |
| 4884 | 4884 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
|
| 4885 | /* Master or Memory mode selected */ |
4885 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
| 4886 | if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) |
4886 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
| 4887 | { |
4887 | |
| 4888 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
4888 | /* Master or Memory mode selected */ |
| 4889 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
4889 | if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) |
| 4890 | 4890 | { |
|
| 4891 | /* Exit IRQ event until Start Bit detected in case of Other frame requested */ |
4891 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
| 4892 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U)) |
4892 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
| 4893 | { |
4893 | |
| 4894 | return; |
4894 | /* Exit IRQ event until Start Bit detected in case of Other frame requested */ |
| 4895 | } |
4895 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) == RESET) && (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(CurrentXferOptions) == 1U)) |
| 4896 | 4896 | { |
|
| 4897 | /* SB Set ----------------------------------------------------------------*/ |
4897 | return; |
| 4898 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
4898 | } |
| 4899 | { |
4899 | |
| 4900 | /* Convert OTHER_xxx XferOptions if any */ |
4900 | /* SB Set ----------------------------------------------------------------*/ |
| 4901 | I2C_ConvertOtherXferOptions(hi2c); |
4901 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_SB) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
| 4902 | 4902 | { |
|
| 4903 | I2C_Master_SB(hi2c); |
4903 | /* Convert OTHER_xxx XferOptions if any */ |
| 4904 | } |
4904 | I2C_ConvertOtherXferOptions(hi2c); |
| 4905 | /* ADD10 Set -------------------------------------------------------------*/ |
4905 | |
| 4906 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
4906 | I2C_Master_SB(hi2c); |
| 4907 | { |
4907 | } |
| 4908 | I2C_Master_ADD10(hi2c); |
4908 | /* ADD10 Set -------------------------------------------------------------*/ |
| 4909 | } |
4909 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADD10) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
| 4910 | /* ADDR Set --------------------------------------------------------------*/ |
4910 | { |
| 4911 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
4911 | I2C_Master_ADD10(hi2c); |
| 4912 | { |
4912 | } |
| 4913 | I2C_Master_ADDR(hi2c); |
4913 | /* ADDR Set --------------------------------------------------------------*/ |
| 4914 | } |
4914 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
| 4915 | /* I2C in mode Transmitter -----------------------------------------------*/ |
4915 | { |
| 4916 | else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET) |
4916 | I2C_Master_ADDR(hi2c); |
| 4917 | { |
4917 | } |
| 4918 | /* Do not check buffer and BTF flag if a Xfer DMA is on going */ |
4918 | /* I2C in mode Transmitter -----------------------------------------------*/ |
| 4919 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) |
4919 | else if (I2C_CHECK_FLAG(sr2itflags, I2C_FLAG_TRA) != RESET) |
| 4920 | { |
4920 | { |
| 4921 | /* TXE set and BTF reset -----------------------------------------------*/ |
4921 | /* Do not check buffer and BTF flag if a Xfer DMA is on going */ |
| 4922 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
4922 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) |
| 4923 | { |
4923 | { |
| 4924 | I2C_MasterTransmit_TXE(hi2c); |
4924 | /* TXE set and BTF reset -----------------------------------------------*/ |
| 4925 | } |
4925 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
| 4926 | /* BTF set -------------------------------------------------------------*/ |
4926 | { |
| 4927 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
4927 | I2C_MasterTransmit_TXE(hi2c); |
| 4928 | { |
4928 | } |
| 4929 | if (CurrentState == HAL_I2C_STATE_BUSY_TX) |
4929 | /* BTF set -------------------------------------------------------------*/ |
| 4930 | { |
4930 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
| 4931 | I2C_MasterTransmit_BTF(hi2c); |
4931 | { |
| 4932 | } |
4932 | if (CurrentState == HAL_I2C_STATE_BUSY_TX) |
| 4933 | else /* HAL_I2C_MODE_MEM */ |
4933 | { |
| 4934 | { |
4934 | I2C_MasterTransmit_BTF(hi2c); |
| 4935 | if (CurrentMode == HAL_I2C_MODE_MEM) |
4935 | } |
| 4936 | { |
4936 | else /* HAL_I2C_MODE_MEM */ |
| 4937 | I2C_MemoryTransmit_TXE_BTF(hi2c); |
4937 | { |
| 4938 | } |
4938 | if (CurrentMode == HAL_I2C_MODE_MEM) |
| 4939 | } |
4939 | { |
| 4940 | } |
4940 | I2C_MemoryTransmit_TXE_BTF(hi2c); |
| 4941 | else |
4941 | } |
| 4942 | { |
4942 | } |
| 4943 | /* Do nothing */ |
4943 | } |
| 4944 | } |
4944 | else |
| 4945 | } |
4945 | { |
| 4946 | } |
4946 | /* Do nothing */ |
| 4947 | /* I2C in mode Receiver --------------------------------------------------*/ |
4947 | } |
| 4948 | else |
4948 | } |
| 4949 | { |
4949 | } |
| 4950 | /* Do not check buffer and BTF flag if a Xfer DMA is on going */ |
4950 | /* I2C in mode Receiver --------------------------------------------------*/ |
| 4951 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) |
4951 | else |
| 4952 | { |
4952 | { |
| 4953 | /* RXNE set and BTF reset -----------------------------------------------*/ |
4953 | /* Do not check buffer and BTF flag if a Xfer DMA is on going */ |
| 4954 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
4954 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) |
| 4955 | { |
4955 | { |
| 4956 | I2C_MasterReceive_RXNE(hi2c); |
4956 | /* RXNE set and BTF reset -----------------------------------------------*/ |
| 4957 | } |
4957 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
| 4958 | /* BTF set -------------------------------------------------------------*/ |
4958 | { |
| 4959 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
4959 | I2C_MasterReceive_RXNE(hi2c); |
| 4960 | { |
4960 | } |
| 4961 | I2C_MasterReceive_BTF(hi2c); |
4961 | /* BTF set -------------------------------------------------------------*/ |
| 4962 | } |
4962 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
| 4963 | else |
4963 | { |
| 4964 | { |
4964 | I2C_MasterReceive_BTF(hi2c); |
| 4965 | /* Do nothing */ |
4965 | } |
| 4966 | } |
4966 | else |
| 4967 | } |
4967 | { |
| 4968 | } |
4968 | /* Do nothing */ |
| 4969 | } |
4969 | } |
| 4970 | /* Slave mode selected */ |
4970 | } |
| 4971 | else |
4971 | } |
| 4972 | { |
4972 | } |
| 4973 | /* If an error is detected, read only SR1 register to prevent */ |
4973 | /* Slave mode selected */ |
| 4974 | /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */ |
4974 | else |
| 4975 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
4975 | { |
| 4976 | { |
4976 | /* If an error is detected, read only SR1 register to prevent */ |
| 4977 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
4977 | /* a clear of ADDR flags by reading SR2 after reading SR1 in Error treatment */ |
| 4978 | } |
4978 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
| 4979 | else |
4979 | { |
| 4980 | { |
4980 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
| 4981 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
4981 | } |
| 4982 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
4982 | else |
| 4983 | } |
4983 | { |
| 4984 | 4984 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
|
| 4985 | /* ADDR set --------------------------------------------------------------*/ |
4985 | sr1itflags = READ_REG(hi2c->Instance->SR1); |
| 4986 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
4986 | } |
| 4987 | { |
4987 | |
| 4988 | /* Now time to read SR2, this will clear ADDR flag automatically */ |
4988 | /* ADDR set --------------------------------------------------------------*/ |
| 4989 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
4989 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ADDR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
| 4990 | { |
4990 | { |
| 4991 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
4991 | /* Now time to read SR2, this will clear ADDR flag automatically */ |
| 4992 | } |
4992 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
| 4993 | I2C_Slave_ADDR(hi2c, sr2itflags); |
4993 | { |
| 4994 | } |
4994 | sr2itflags = READ_REG(hi2c->Instance->SR2); |
| 4995 | /* STOPF set --------------------------------------------------------------*/ |
4995 | } |
| 4996 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
4996 | I2C_Slave_ADDR(hi2c, sr2itflags); |
| 4997 | { |
4997 | } |
| 4998 | I2C_Slave_STOPF(hi2c); |
4998 | /* STOPF set --------------------------------------------------------------*/ |
| 4999 | } |
4999 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
| 5000 | /* I2C in mode Transmitter -----------------------------------------------*/ |
5000 | { |
| 5001 | else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) |
5001 | I2C_Slave_STOPF(hi2c); |
| 5002 | { |
5002 | } |
| 5003 | /* TXE set and BTF reset -----------------------------------------------*/ |
5003 | /* I2C in mode Transmitter -----------------------------------------------*/ |
| 5004 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
5004 | else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) |
| 5005 | { |
5005 | { |
| 5006 | I2C_SlaveTransmit_TXE(hi2c); |
5006 | /* TXE set and BTF reset -----------------------------------------------*/ |
| 5007 | } |
5007 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_TXE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
| 5008 | /* BTF set -------------------------------------------------------------*/ |
5008 | { |
| 5009 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
5009 | I2C_SlaveTransmit_TXE(hi2c); |
| 5010 | { |
5010 | } |
| 5011 | I2C_SlaveTransmit_BTF(hi2c); |
5011 | /* BTF set -------------------------------------------------------------*/ |
| 5012 | } |
5012 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
| 5013 | else |
5013 | { |
| 5014 | { |
5014 | I2C_SlaveTransmit_BTF(hi2c); |
| 5015 | /* Do nothing */ |
5015 | } |
| 5016 | } |
5016 | else |
| 5017 | } |
5017 | { |
| 5018 | /* I2C in mode Receiver --------------------------------------------------*/ |
5018 | /* Do nothing */ |
| 5019 | else |
5019 | } |
| 5020 | { |
5020 | } |
| 5021 | /* RXNE set and BTF reset ----------------------------------------------*/ |
5021 | /* I2C in mode Receiver --------------------------------------------------*/ |
| 5022 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
5022 | else |
| 5023 | { |
5023 | { |
| 5024 | I2C_SlaveReceive_RXNE(hi2c); |
5024 | /* RXNE set and BTF reset ----------------------------------------------*/ |
| 5025 | } |
5025 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_RXNE) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_BUF) != RESET) && (I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) == RESET)) |
| 5026 | /* BTF set -------------------------------------------------------------*/ |
5026 | { |
| 5027 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
5027 | I2C_SlaveReceive_RXNE(hi2c); |
| 5028 | { |
5028 | } |
| 5029 | I2C_SlaveReceive_BTF(hi2c); |
5029 | /* BTF set -------------------------------------------------------------*/ |
| 5030 | } |
5030 | else if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BTF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_EVT) != RESET)) |
| 5031 | else |
5031 | { |
| 5032 | { |
5032 | I2C_SlaveReceive_BTF(hi2c); |
| 5033 | /* Do nothing */ |
5033 | } |
| 5034 | } |
5034 | else |
| 5035 | } |
5035 | { |
| 5036 | } |
5036 | /* Do nothing */ |
| 5037 | } |
5037 | } |
| 5038 | 5038 | } |
|
| 5039 | /** |
5039 | } |
| 5040 | * @brief This function handles I2C error interrupt request. |
5040 | } |
| 5041 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5041 | |
| 5042 | * the configuration information for the specified I2C. |
5042 | /** |
| 5043 | * @retval None |
5043 | * @brief This function handles I2C error interrupt request. |
| 5044 | */ |
5044 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5045 | void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) |
5045 | * the configuration information for the specified I2C. |
| 5046 | { |
5046 | * @retval None |
| 5047 | HAL_I2C_ModeTypeDef tmp1; |
5047 | */ |
| 5048 | uint32_t tmp2; |
5048 | void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) |
| 5049 | HAL_I2C_StateTypeDef tmp3; |
5049 | { |
| 5050 | uint32_t tmp4; |
5050 | HAL_I2C_ModeTypeDef tmp1; |
| 5051 | uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); |
5051 | uint32_t tmp2; |
| 5052 | uint32_t itsources = READ_REG(hi2c->Instance->CR2); |
5052 | HAL_I2C_StateTypeDef tmp3; |
| 5053 | uint32_t error = HAL_I2C_ERROR_NONE; |
5053 | uint32_t tmp4; |
| 5054 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
5054 | uint32_t sr1itflags = READ_REG(hi2c->Instance->SR1); |
| 5055 | 5055 | uint32_t itsources = READ_REG(hi2c->Instance->CR2); |
|
| 5056 | /* I2C Bus error interrupt occurred ----------------------------------------*/ |
5056 | uint32_t error = HAL_I2C_ERROR_NONE; |
| 5057 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
5057 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
| 5058 | { |
5058 | |
| 5059 | error |= HAL_I2C_ERROR_BERR; |
5059 | /* I2C Bus error interrupt occurred ----------------------------------------*/ |
| 5060 | 5060 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_BERR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
|
| 5061 | /* Clear BERR flag */ |
5061 | { |
| 5062 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); |
5062 | error |= HAL_I2C_ERROR_BERR; |
| 5063 | 5063 | ||
| 5064 | /* Workaround: Start cannot be generated after a misplaced Stop */ |
5064 | /* Clear BERR flag */ |
| 5065 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST); |
5065 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); |
| 5066 | } |
5066 | |
| 5067 | 5067 | /* Workaround: Start cannot be generated after a misplaced Stop */ |
|
| 5068 | /* I2C Arbitration Lost error interrupt occurred ---------------------------*/ |
5068 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_SWRST); |
| 5069 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
5069 | } |
| 5070 | { |
5070 | |
| 5071 | error |= HAL_I2C_ERROR_ARLO; |
5071 | /* I2C Arbitration Lost error interrupt occurred ---------------------------*/ |
| 5072 | 5072 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_ARLO) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
|
| 5073 | /* Clear ARLO flag */ |
5073 | { |
| 5074 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); |
5074 | error |= HAL_I2C_ERROR_ARLO; |
| 5075 | } |
5075 | |
| 5076 | 5076 | /* Clear ARLO flag */ |
|
| 5077 | /* I2C Acknowledge failure error interrupt occurred ------------------------*/ |
5077 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); |
| 5078 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
5078 | } |
| 5079 | { |
5079 | |
| 5080 | tmp1 = CurrentMode; |
5080 | /* I2C Acknowledge failure error interrupt occurred ------------------------*/ |
| 5081 | tmp2 = hi2c->XferCount; |
5081 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
| 5082 | tmp3 = hi2c->State; |
5082 | { |
| 5083 | tmp4 = hi2c->PreviousState; |
5083 | tmp1 = CurrentMode; |
| 5084 | if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ |
5084 | tmp2 = hi2c->XferCount; |
| 5085 | ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ |
5085 | tmp3 = hi2c->State; |
| 5086 | ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) |
5086 | tmp4 = hi2c->PreviousState; |
| 5087 | { |
5087 | if ((tmp1 == HAL_I2C_MODE_SLAVE) && (tmp2 == 0U) && \ |
| 5088 | I2C_Slave_AF(hi2c); |
5088 | ((tmp3 == HAL_I2C_STATE_BUSY_TX) || (tmp3 == HAL_I2C_STATE_BUSY_TX_LISTEN) || \ |
| 5089 | } |
5089 | ((tmp3 == HAL_I2C_STATE_LISTEN) && (tmp4 == I2C_STATE_SLAVE_BUSY_TX)))) |
| 5090 | else |
5090 | { |
| 5091 | { |
5091 | I2C_Slave_AF(hi2c); |
| 5092 | /* Clear AF flag */ |
5092 | } |
| 5093 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
5093 | else |
| 5094 | 5094 | { |
|
| 5095 | error |= HAL_I2C_ERROR_AF; |
5095 | /* Clear AF flag */ |
| 5096 | 5096 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
|
| 5097 | /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ |
5097 | |
| 5098 | if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) |
5098 | error |= HAL_I2C_ERROR_AF; |
| 5099 | { |
5099 | |
| 5100 | /* Generate Stop */ |
5100 | /* Do not generate a STOP in case of Slave receive non acknowledge during transfer (mean not at the end of transfer) */ |
| 5101 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
5101 | if ((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) |
| 5102 | } |
5102 | { |
| 5103 | } |
5103 | /* Generate Stop */ |
| 5104 | } |
5104 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 5105 | 5105 | } |
|
| 5106 | /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ |
5106 | } |
| 5107 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
5107 | } |
| 5108 | { |
5108 | |
| 5109 | error |= HAL_I2C_ERROR_OVR; |
5109 | /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/ |
| 5110 | /* Clear OVR flag */ |
5110 | if ((I2C_CHECK_FLAG(sr1itflags, I2C_FLAG_OVR) != RESET) && (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERR) != RESET)) |
| 5111 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); |
5111 | { |
| 5112 | } |
5112 | error |= HAL_I2C_ERROR_OVR; |
| 5113 | 5113 | /* Clear OVR flag */ |
|
| 5114 | /* Call the Error Callback in case of Error detected -----------------------*/ |
5114 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); |
| 5115 | if (error != HAL_I2C_ERROR_NONE) |
5115 | } |
| 5116 | { |
5116 | |
| 5117 | hi2c->ErrorCode |= error; |
5117 | /* Call the Error Callback in case of Error detected -----------------------*/ |
| 5118 | I2C_ITError(hi2c); |
5118 | if (error != HAL_I2C_ERROR_NONE) |
| 5119 | } |
5119 | { |
| 5120 | } |
5120 | hi2c->ErrorCode |= error; |
| 5121 | 5121 | I2C_ITError(hi2c); |
|
| 5122 | /** |
5122 | } |
| 5123 | * @brief Master Tx Transfer completed callback. |
5123 | } |
| 5124 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5124 | |
| 5125 | * the configuration information for the specified I2C. |
5125 | /** |
| 5126 | * @retval None |
5126 | * @brief Master Tx Transfer completed callback. |
| 5127 | */ |
5127 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5128 | __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) |
5128 | * the configuration information for the specified I2C. |
| 5129 | { |
5129 | * @retval None |
| 5130 | /* Prevent unused argument(s) compilation warning */ |
5130 | */ |
| 5131 | UNUSED(hi2c); |
5131 | __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) |
| 5132 | 5132 | { |
|
| 5133 | /* NOTE : This function should not be modified, when the callback is needed, |
5133 | /* Prevent unused argument(s) compilation warning */ |
| 5134 | the HAL_I2C_MasterTxCpltCallback could be implemented in the user file |
5134 | UNUSED(hi2c); |
| 5135 | */ |
5135 | |
| 5136 | } |
5136 | /* NOTE : This function should not be modified, when the callback is needed, |
| 5137 | 5137 | the HAL_I2C_MasterTxCpltCallback could be implemented in the user file |
|
| 5138 | /** |
5138 | */ |
| 5139 | * @brief Master Rx Transfer completed callback. |
5139 | } |
| 5140 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5140 | |
| 5141 | * the configuration information for the specified I2C. |
5141 | /** |
| 5142 | * @retval None |
5142 | * @brief Master Rx Transfer completed callback. |
| 5143 | */ |
5143 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5144 | __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) |
5144 | * the configuration information for the specified I2C. |
| 5145 | { |
5145 | * @retval None |
| 5146 | /* Prevent unused argument(s) compilation warning */ |
5146 | */ |
| 5147 | UNUSED(hi2c); |
5147 | __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) |
| 5148 | 5148 | { |
|
| 5149 | /* NOTE : This function should not be modified, when the callback is needed, |
5149 | /* Prevent unused argument(s) compilation warning */ |
| 5150 | the HAL_I2C_MasterRxCpltCallback could be implemented in the user file |
5150 | UNUSED(hi2c); |
| 5151 | */ |
5151 | |
| 5152 | } |
5152 | /* NOTE : This function should not be modified, when the callback is needed, |
| 5153 | 5153 | the HAL_I2C_MasterRxCpltCallback could be implemented in the user file |
|
| 5154 | /** @brief Slave Tx Transfer completed callback. |
5154 | */ |
| 5155 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5155 | } |
| 5156 | * the configuration information for the specified I2C. |
5156 | |
| 5157 | * @retval None |
5157 | /** @brief Slave Tx Transfer completed callback. |
| 5158 | */ |
5158 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5159 | __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) |
5159 | * the configuration information for the specified I2C. |
| 5160 | { |
5160 | * @retval None |
| 5161 | /* Prevent unused argument(s) compilation warning */ |
5161 | */ |
| 5162 | UNUSED(hi2c); |
5162 | __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) |
| 5163 | 5163 | { |
|
| 5164 | /* NOTE : This function should not be modified, when the callback is needed, |
5164 | /* Prevent unused argument(s) compilation warning */ |
| 5165 | the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file |
5165 | UNUSED(hi2c); |
| 5166 | */ |
5166 | |
| 5167 | } |
5167 | /* NOTE : This function should not be modified, when the callback is needed, |
| 5168 | 5168 | the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file |
|
| 5169 | /** |
5169 | */ |
| 5170 | * @brief Slave Rx Transfer completed callback. |
5170 | } |
| 5171 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5171 | |
| 5172 | * the configuration information for the specified I2C. |
5172 | /** |
| 5173 | * @retval None |
5173 | * @brief Slave Rx Transfer completed callback. |
| 5174 | */ |
5174 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5175 | __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) |
5175 | * the configuration information for the specified I2C. |
| 5176 | { |
5176 | * @retval None |
| 5177 | /* Prevent unused argument(s) compilation warning */ |
5177 | */ |
| 5178 | UNUSED(hi2c); |
5178 | __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) |
| 5179 | 5179 | { |
|
| 5180 | /* NOTE : This function should not be modified, when the callback is needed, |
5180 | /* Prevent unused argument(s) compilation warning */ |
| 5181 | the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file |
5181 | UNUSED(hi2c); |
| 5182 | */ |
5182 | |
| 5183 | } |
5183 | /* NOTE : This function should not be modified, when the callback is needed, |
| 5184 | 5184 | the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file |
|
| 5185 | /** |
5185 | */ |
| 5186 | * @brief Slave Address Match callback. |
5186 | } |
| 5187 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5187 | |
| 5188 | * the configuration information for the specified I2C. |
5188 | /** |
| 5189 | * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition |
5189 | * @brief Slave Address Match callback. |
| 5190 | * @param AddrMatchCode Address Match Code |
5190 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5191 | * @retval None |
5191 | * the configuration information for the specified I2C. |
| 5192 | */ |
5192 | * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XferDirection_definition |
| 5193 | __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) |
5193 | * @param AddrMatchCode Address Match Code |
| 5194 | { |
5194 | * @retval None |
| 5195 | /* Prevent unused argument(s) compilation warning */ |
5195 | */ |
| 5196 | UNUSED(hi2c); |
5196 | __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) |
| 5197 | UNUSED(TransferDirection); |
5197 | { |
| 5198 | UNUSED(AddrMatchCode); |
5198 | /* Prevent unused argument(s) compilation warning */ |
| 5199 | 5199 | UNUSED(hi2c); |
|
| 5200 | /* NOTE : This function should not be modified, when the callback is needed, |
5200 | UNUSED(TransferDirection); |
| 5201 | the HAL_I2C_AddrCallback() could be implemented in the user file |
5201 | UNUSED(AddrMatchCode); |
| 5202 | */ |
5202 | |
| 5203 | } |
5203 | /* NOTE : This function should not be modified, when the callback is needed, |
| 5204 | 5204 | the HAL_I2C_AddrCallback() could be implemented in the user file |
|
| 5205 | /** |
5205 | */ |
| 5206 | * @brief Listen Complete callback. |
5206 | } |
| 5207 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5207 | |
| 5208 | * the configuration information for the specified I2C. |
5208 | /** |
| 5209 | * @retval None |
5209 | * @brief Listen Complete callback. |
| 5210 | */ |
5210 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5211 | __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) |
5211 | * the configuration information for the specified I2C. |
| 5212 | { |
5212 | * @retval None |
| 5213 | /* Prevent unused argument(s) compilation warning */ |
5213 | */ |
| 5214 | UNUSED(hi2c); |
5214 | __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) |
| 5215 | 5215 | { |
|
| 5216 | /* NOTE : This function should not be modified, when the callback is needed, |
5216 | /* Prevent unused argument(s) compilation warning */ |
| 5217 | the HAL_I2C_ListenCpltCallback() could be implemented in the user file |
5217 | UNUSED(hi2c); |
| 5218 | */ |
5218 | |
| 5219 | } |
5219 | /* NOTE : This function should not be modified, when the callback is needed, |
| 5220 | 5220 | the HAL_I2C_ListenCpltCallback() could be implemented in the user file |
|
| 5221 | /** |
5221 | */ |
| 5222 | * @brief Memory Tx Transfer completed callback. |
5222 | } |
| 5223 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5223 | |
| 5224 | * the configuration information for the specified I2C. |
5224 | /** |
| 5225 | * @retval None |
5225 | * @brief Memory Tx Transfer completed callback. |
| 5226 | */ |
5226 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5227 | __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) |
5227 | * the configuration information for the specified I2C. |
| 5228 | { |
5228 | * @retval None |
| 5229 | /* Prevent unused argument(s) compilation warning */ |
5229 | */ |
| 5230 | UNUSED(hi2c); |
5230 | __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) |
| 5231 | 5231 | { |
|
| 5232 | /* NOTE : This function should not be modified, when the callback is needed, |
5232 | /* Prevent unused argument(s) compilation warning */ |
| 5233 | the HAL_I2C_MemTxCpltCallback could be implemented in the user file |
5233 | UNUSED(hi2c); |
| 5234 | */ |
5234 | |
| 5235 | } |
5235 | /* NOTE : This function should not be modified, when the callback is needed, |
| 5236 | 5236 | the HAL_I2C_MemTxCpltCallback could be implemented in the user file |
|
| 5237 | /** |
5237 | */ |
| 5238 | * @brief Memory Rx Transfer completed callback. |
5238 | } |
| 5239 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5239 | |
| 5240 | * the configuration information for the specified I2C. |
5240 | /** |
| 5241 | * @retval None |
5241 | * @brief Memory Rx Transfer completed callback. |
| 5242 | */ |
5242 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5243 | __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) |
5243 | * the configuration information for the specified I2C. |
| 5244 | { |
5244 | * @retval None |
| 5245 | /* Prevent unused argument(s) compilation warning */ |
5245 | */ |
| 5246 | UNUSED(hi2c); |
5246 | __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) |
| 5247 | 5247 | { |
|
| 5248 | /* NOTE : This function should not be modified, when the callback is needed, |
5248 | /* Prevent unused argument(s) compilation warning */ |
| 5249 | the HAL_I2C_MemRxCpltCallback could be implemented in the user file |
5249 | UNUSED(hi2c); |
| 5250 | */ |
5250 | |
| 5251 | } |
5251 | /* NOTE : This function should not be modified, when the callback is needed, |
| 5252 | 5252 | the HAL_I2C_MemRxCpltCallback could be implemented in the user file |
|
| 5253 | /** |
5253 | */ |
| 5254 | * @brief I2C error callback. |
5254 | } |
| 5255 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5255 | |
| 5256 | * the configuration information for the specified I2C. |
5256 | /** |
| 5257 | * @retval None |
5257 | * @brief I2C error callback. |
| 5258 | */ |
5258 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5259 | __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) |
5259 | * the configuration information for the specified I2C. |
| 5260 | { |
5260 | * @retval None |
| 5261 | /* Prevent unused argument(s) compilation warning */ |
5261 | */ |
| 5262 | UNUSED(hi2c); |
5262 | __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) |
| 5263 | 5263 | { |
|
| 5264 | /* NOTE : This function should not be modified, when the callback is needed, |
5264 | /* Prevent unused argument(s) compilation warning */ |
| 5265 | the HAL_I2C_ErrorCallback could be implemented in the user file |
5265 | UNUSED(hi2c); |
| 5266 | */ |
5266 | |
| 5267 | } |
5267 | /* NOTE : This function should not be modified, when the callback is needed, |
| 5268 | 5268 | the HAL_I2C_ErrorCallback could be implemented in the user file |
|
| 5269 | /** |
5269 | */ |
| 5270 | * @brief I2C abort callback. |
5270 | } |
| 5271 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5271 | |
| 5272 | * the configuration information for the specified I2C. |
5272 | /** |
| 5273 | * @retval None |
5273 | * @brief I2C abort callback. |
| 5274 | */ |
5274 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5275 | __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) |
5275 | * the configuration information for the specified I2C. |
| 5276 | { |
5276 | * @retval None |
| 5277 | /* Prevent unused argument(s) compilation warning */ |
5277 | */ |
| 5278 | UNUSED(hi2c); |
5278 | __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) |
| 5279 | 5279 | { |
|
| 5280 | /* NOTE : This function should not be modified, when the callback is needed, |
5280 | /* Prevent unused argument(s) compilation warning */ |
| 5281 | the HAL_I2C_AbortCpltCallback could be implemented in the user file |
5281 | UNUSED(hi2c); |
| 5282 | */ |
5282 | |
| 5283 | } |
5283 | /* NOTE : This function should not be modified, when the callback is needed, |
| 5284 | 5284 | the HAL_I2C_AbortCpltCallback could be implemented in the user file |
|
| 5285 | /** |
5285 | */ |
| 5286 | * @} |
5286 | } |
| 5287 | */ |
5287 | |
| 5288 | 5288 | /** |
|
| 5289 | /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions |
5289 | * @} |
| 5290 | * @brief Peripheral State, Mode and Error functions |
5290 | */ |
| 5291 | * |
5291 | |
| 5292 | @verbatim |
5292 | /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions |
| 5293 | =============================================================================== |
5293 | * @brief Peripheral State, Mode and Error functions |
| 5294 | ##### Peripheral State, Mode and Error functions ##### |
5294 | * |
| 5295 | =============================================================================== |
5295 | @verbatim |
| 5296 | [..] |
5296 | =============================================================================== |
| 5297 | This subsection permit to get in run-time the status of the peripheral |
5297 | ##### Peripheral State, Mode and Error functions ##### |
| 5298 | and the data flow. |
5298 | =============================================================================== |
| 5299 | 5299 | [..] |
|
| 5300 | @endverbatim |
5300 | This subsection permit to get in run-time the status of the peripheral |
| 5301 | * @{ |
5301 | and the data flow. |
| 5302 | */ |
5302 | |
| 5303 | 5303 | @endverbatim |
|
| 5304 | /** |
5304 | * @{ |
| 5305 | * @brief Return the I2C handle state. |
5305 | */ |
| 5306 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5306 | |
| 5307 | * the configuration information for the specified I2C. |
5307 | /** |
| 5308 | * @retval HAL state |
5308 | * @brief Return the I2C handle state. |
| 5309 | */ |
5309 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5310 | HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) |
5310 | * the configuration information for the specified I2C. |
| 5311 | { |
5311 | * @retval HAL state |
| 5312 | /* Return I2C handle state */ |
5312 | */ |
| 5313 | return hi2c->State; |
5313 | HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c) |
| 5314 | } |
5314 | { |
| 5315 | 5315 | /* Return I2C handle state */ |
|
| 5316 | /** |
5316 | return hi2c->State; |
| 5317 | * @brief Returns the I2C Master, Slave, Memory or no mode. |
5317 | } |
| 5318 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5318 | |
| 5319 | * the configuration information for I2C module |
5319 | /** |
| 5320 | * @retval HAL mode |
5320 | * @brief Returns the I2C Master, Slave, Memory or no mode. |
| 5321 | */ |
5321 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5322 | HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) |
5322 | * the configuration information for I2C module |
| 5323 | { |
5323 | * @retval HAL mode |
| 5324 | return hi2c->Mode; |
5324 | */ |
| 5325 | } |
5325 | HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c) |
| 5326 | 5326 | { |
|
| 5327 | /** |
5327 | return hi2c->Mode; |
| 5328 | * @brief Return the I2C error code. |
5328 | } |
| 5329 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5329 | |
| 5330 | * the configuration information for the specified I2C. |
5330 | /** |
| 5331 | * @retval I2C Error Code |
5331 | * @brief Return the I2C error code. |
| 5332 | */ |
5332 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5333 | uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) |
5333 | * the configuration information for the specified I2C. |
| 5334 | { |
5334 | * @retval I2C Error Code |
| 5335 | return hi2c->ErrorCode; |
5335 | */ |
| 5336 | } |
5336 | uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c) |
| 5337 | 5337 | { |
|
| 5338 | /** |
5338 | return hi2c->ErrorCode; |
| 5339 | * @} |
5339 | } |
| 5340 | */ |
5340 | |
| 5341 | 5341 | /** |
|
| 5342 | /** |
5342 | * @} |
| 5343 | * @} |
5343 | */ |
| 5344 | */ |
5344 | |
| 5345 | 5345 | /** |
|
| 5346 | /** @addtogroup I2C_Private_Functions |
5346 | * @} |
| 5347 | * @{ |
5347 | */ |
| 5348 | */ |
5348 | |
| 5349 | 5349 | /** @addtogroup I2C_Private_Functions |
|
| 5350 | /** |
5350 | * @{ |
| 5351 | * @brief Handle TXE flag for Master |
5351 | */ |
| 5352 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5352 | |
| 5353 | * the configuration information for I2C module |
5353 | /** |
| 5354 | * @retval None |
5354 | * @brief Handle TXE flag for Master |
| 5355 | */ |
5355 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5356 | static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) |
5356 | * the configuration information for I2C module |
| 5357 | { |
5357 | * @retval None |
| 5358 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
5358 | */ |
| 5359 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
5359 | static void I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c) |
| 5360 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
5360 | { |
| 5361 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
5361 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
| 5362 | 5362 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
|
| 5363 | if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
5363 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
| 5364 | { |
5364 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
| 5365 | /* Call TxCpltCallback() directly if no stop mode is set */ |
5365 | |
| 5366 | if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) |
5366 | if ((hi2c->XferSize == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
| 5367 | { |
5367 | { |
| 5368 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
5368 | /* Call TxCpltCallback() directly if no stop mode is set */ |
| 5369 | 5369 | if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) |
|
| 5370 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; |
5370 | { |
| 5371 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5371 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 5372 | hi2c->State = HAL_I2C_STATE_READY; |
5372 | |
| 5373 | 5373 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; |
|
| 5374 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5374 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5375 | hi2c->MasterTxCpltCallback(hi2c); |
5375 | hi2c->State = HAL_I2C_STATE_READY; |
| 5376 | #else |
5376 | |
| 5377 | HAL_I2C_MasterTxCpltCallback(hi2c); |
5377 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5378 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5378 | hi2c->MasterTxCpltCallback(hi2c); |
| 5379 | } |
5379 | #else |
| 5380 | else /* Generate Stop condition then Call TxCpltCallback() */ |
5380 | HAL_I2C_MasterTxCpltCallback(hi2c); |
| 5381 | { |
5381 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5382 | /* Disable EVT, BUF and ERR interrupt */ |
5382 | } |
| 5383 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
5383 | else /* Generate Stop condition then Call TxCpltCallback() */ |
| 5384 | 5384 | { |
|
| 5385 | /* Generate Stop */ |
5385 | /* Disable EVT, BUF and ERR interrupt */ |
| 5386 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
5386 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 5387 | 5387 | ||
| 5388 | hi2c->PreviousState = I2C_STATE_NONE; |
5388 | /* Generate Stop */ |
| 5389 | hi2c->State = HAL_I2C_STATE_READY; |
5389 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 5390 | 5390 | ||
| 5391 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
5391 | hi2c->PreviousState = I2C_STATE_NONE; |
| 5392 | { |
5392 | hi2c->State = HAL_I2C_STATE_READY; |
| 5393 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5393 | |
| 5394 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5394 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
| 5395 | hi2c->MemTxCpltCallback(hi2c); |
5395 | { |
| 5396 | #else |
5396 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5397 | HAL_I2C_MemTxCpltCallback(hi2c); |
5397 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5398 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5398 | hi2c->MemTxCpltCallback(hi2c); |
| 5399 | } |
5399 | #else |
| 5400 | else |
5400 | HAL_I2C_MemTxCpltCallback(hi2c); |
| 5401 | { |
5401 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5402 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5402 | } |
| 5403 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5403 | else |
| 5404 | hi2c->MasterTxCpltCallback(hi2c); |
5404 | { |
| 5405 | #else |
5405 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5406 | HAL_I2C_MasterTxCpltCallback(hi2c); |
5406 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5407 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5407 | hi2c->MasterTxCpltCallback(hi2c); |
| 5408 | } |
5408 | #else |
| 5409 | } |
5409 | HAL_I2C_MasterTxCpltCallback(hi2c); |
| 5410 | } |
5410 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5411 | else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ |
5411 | } |
| 5412 | ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) |
5412 | } |
| 5413 | { |
5413 | } |
| 5414 | if (hi2c->XferCount == 0U) |
5414 | else if ((CurrentState == HAL_I2C_STATE_BUSY_TX) || \ |
| 5415 | { |
5415 | ((CurrentMode == HAL_I2C_MODE_MEM) && (CurrentState == HAL_I2C_STATE_BUSY_RX))) |
| 5416 | /* Disable BUF interrupt */ |
5416 | { |
| 5417 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
5417 | if (hi2c->XferCount == 0U) |
| 5418 | } |
5418 | { |
| 5419 | else |
5419 | /* Disable BUF interrupt */ |
| 5420 | { |
5420 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
| 5421 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
5421 | } |
| 5422 | { |
5422 | else |
| 5423 | I2C_MemoryTransmit_TXE_BTF(hi2c); |
5423 | { |
| 5424 | } |
5424 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
| 5425 | else |
5425 | { |
| 5426 | { |
5426 | I2C_MemoryTransmit_TXE_BTF(hi2c); |
| 5427 | /* Write data to DR */ |
5427 | } |
| 5428 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
5428 | else |
| 5429 | 5429 | { |
|
| 5430 | /* Increment Buffer pointer */ |
5430 | /* Write data to DR */ |
| 5431 | hi2c->pBuffPtr++; |
5431 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
| 5432 | 5432 | ||
| 5433 | /* Update counter */ |
5433 | /* Increment Buffer pointer */ |
| 5434 | hi2c->XferCount--; |
5434 | hi2c->pBuffPtr++; |
| 5435 | } |
5435 | |
| 5436 | } |
5436 | /* Update counter */ |
| 5437 | } |
5437 | hi2c->XferCount--; |
| 5438 | else |
5438 | } |
| 5439 | { |
5439 | } |
| 5440 | /* Do nothing */ |
5440 | } |
| 5441 | } |
5441 | else |
| 5442 | } |
5442 | { |
| 5443 | 5443 | /* Do nothing */ |
|
| 5444 | /** |
5444 | } |
| 5445 | * @brief Handle BTF flag for Master transmitter |
5445 | } |
| 5446 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5446 | |
| 5447 | * the configuration information for I2C module |
5447 | /** |
| 5448 | * @retval None |
5448 | * @brief Handle BTF flag for Master transmitter |
| 5449 | */ |
5449 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5450 | static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) |
5450 | * the configuration information for I2C module |
| 5451 | { |
5451 | * @retval None |
| 5452 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
5452 | */ |
| 5453 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
5453 | static void I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c) |
| 5454 | 5454 | { |
|
| 5455 | if (hi2c->State == HAL_I2C_STATE_BUSY_TX) |
5455 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
| 5456 | { |
5456 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
| 5457 | if (hi2c->XferCount != 0U) |
5457 | |
| 5458 | { |
5458 | if (hi2c->State == HAL_I2C_STATE_BUSY_TX) |
| 5459 | /* Write data to DR */ |
5459 | { |
| 5460 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
5460 | if (hi2c->XferCount != 0U) |
| 5461 | 5461 | { |
|
| 5462 | /* Increment Buffer pointer */ |
5462 | /* Write data to DR */ |
| 5463 | hi2c->pBuffPtr++; |
5463 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
| 5464 | 5464 | ||
| 5465 | /* Update counter */ |
5465 | /* Increment Buffer pointer */ |
| 5466 | hi2c->XferCount--; |
5466 | hi2c->pBuffPtr++; |
| 5467 | } |
5467 | |
| 5468 | else |
5468 | /* Update counter */ |
| 5469 | { |
5469 | hi2c->XferCount--; |
| 5470 | /* Call TxCpltCallback() directly if no stop mode is set */ |
5470 | } |
| 5471 | if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) |
5471 | else |
| 5472 | { |
5472 | { |
| 5473 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
5473 | /* Call TxCpltCallback() directly if no stop mode is set */ |
| 5474 | 5474 | if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME)) |
|
| 5475 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; |
5475 | { |
| 5476 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5476 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 5477 | hi2c->State = HAL_I2C_STATE_READY; |
5477 | |
| 5478 | 5478 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; |
|
| 5479 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5479 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5480 | hi2c->MasterTxCpltCallback(hi2c); |
5480 | hi2c->State = HAL_I2C_STATE_READY; |
| 5481 | #else |
5481 | |
| 5482 | HAL_I2C_MasterTxCpltCallback(hi2c); |
5482 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5483 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5483 | hi2c->MasterTxCpltCallback(hi2c); |
| 5484 | } |
5484 | #else |
| 5485 | else /* Generate Stop condition then Call TxCpltCallback() */ |
5485 | HAL_I2C_MasterTxCpltCallback(hi2c); |
| 5486 | { |
5486 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5487 | /* Disable EVT, BUF and ERR interrupt */ |
5487 | } |
| 5488 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
5488 | else /* Generate Stop condition then Call TxCpltCallback() */ |
| 5489 | 5489 | { |
|
| 5490 | /* Generate Stop */ |
5490 | /* Disable EVT, BUF and ERR interrupt */ |
| 5491 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
5491 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 5492 | 5492 | ||
| 5493 | hi2c->PreviousState = I2C_STATE_NONE; |
5493 | /* Generate Stop */ |
| 5494 | hi2c->State = HAL_I2C_STATE_READY; |
5494 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 5495 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
5495 | |
| 5496 | { |
5496 | hi2c->PreviousState = I2C_STATE_NONE; |
| 5497 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5497 | hi2c->State = HAL_I2C_STATE_READY; |
| 5498 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5498 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
| 5499 | hi2c->MemTxCpltCallback(hi2c); |
5499 | { |
| 5500 | #else |
5500 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5501 | HAL_I2C_MemTxCpltCallback(hi2c); |
5501 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5502 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5502 | hi2c->MemTxCpltCallback(hi2c); |
| 5503 | } |
5503 | #else |
| 5504 | else |
5504 | HAL_I2C_MemTxCpltCallback(hi2c); |
| 5505 | { |
5505 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5506 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5506 | } |
| 5507 | 5507 | else |
|
| 5508 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5508 | { |
| 5509 | hi2c->MasterTxCpltCallback(hi2c); |
5509 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5510 | #else |
5510 | |
| 5511 | HAL_I2C_MasterTxCpltCallback(hi2c); |
5511 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5512 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5512 | hi2c->MasterTxCpltCallback(hi2c); |
| 5513 | } |
5513 | #else |
| 5514 | } |
5514 | HAL_I2C_MasterTxCpltCallback(hi2c); |
| 5515 | } |
5515 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5516 | } |
5516 | } |
| 5517 | else |
5517 | } |
| 5518 | { |
5518 | } |
| 5519 | /* Do nothing */ |
5519 | } |
| 5520 | } |
5520 | else |
| 5521 | } |
5521 | { |
| 5522 | 5522 | /* Do nothing */ |
|
| 5523 | /** |
5523 | } |
| 5524 | * @brief Handle TXE and BTF flag for Memory transmitter |
5524 | } |
| 5525 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5525 | |
| 5526 | * the configuration information for I2C module |
5526 | /** |
| 5527 | * @retval None |
5527 | * @brief Handle TXE and BTF flag for Memory transmitter |
| 5528 | */ |
5528 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5529 | static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) |
5529 | * the configuration information for I2C module |
| 5530 | { |
5530 | * @retval None |
| 5531 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
5531 | */ |
| 5532 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
5532 | static void I2C_MemoryTransmit_TXE_BTF(I2C_HandleTypeDef *hi2c) |
| 5533 | 5533 | { |
|
| 5534 | if (hi2c->EventCount == 0U) |
5534 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
| 5535 | { |
5535 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
| 5536 | /* If Memory address size is 8Bit */ |
5536 | |
| 5537 | if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) |
5537 | if (hi2c->EventCount == 0U) |
| 5538 | { |
5538 | { |
| 5539 | /* Send Memory Address */ |
5539 | /* If Memory address size is 8Bit */ |
| 5540 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); |
5540 | if (hi2c->MemaddSize == I2C_MEMADD_SIZE_8BIT) |
| 5541 | 5541 | { |
|
| 5542 | hi2c->EventCount += 2U; |
5542 | /* Send Memory Address */ |
| 5543 | } |
5543 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); |
| 5544 | /* If Memory address size is 16Bit */ |
5544 | |
| 5545 | else |
5545 | hi2c->EventCount += 2U; |
| 5546 | { |
5546 | } |
| 5547 | /* Send MSB of Memory Address */ |
5547 | /* If Memory address size is 16Bit */ |
| 5548 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); |
5548 | else |
| 5549 | 5549 | { |
|
| 5550 | hi2c->EventCount++; |
5550 | /* Send MSB of Memory Address */ |
| 5551 | } |
5551 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(hi2c->Memaddress); |
| 5552 | } |
5552 | |
| 5553 | else if (hi2c->EventCount == 1U) |
5553 | hi2c->EventCount++; |
| 5554 | { |
5554 | } |
| 5555 | /* Send LSB of Memory Address */ |
5555 | } |
| 5556 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); |
5556 | else if (hi2c->EventCount == 1U) |
| 5557 | 5557 | { |
|
| 5558 | hi2c->EventCount++; |
5558 | /* Send LSB of Memory Address */ |
| 5559 | } |
5559 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(hi2c->Memaddress); |
| 5560 | else if (hi2c->EventCount == 2U) |
5560 | |
| 5561 | { |
5561 | hi2c->EventCount++; |
| 5562 | if (CurrentState == HAL_I2C_STATE_BUSY_RX) |
5562 | } |
| 5563 | { |
5563 | else if (hi2c->EventCount == 2U) |
| 5564 | /* Generate Restart */ |
5564 | { |
| 5565 | hi2c->Instance->CR1 |= I2C_CR1_START; |
5565 | if (CurrentState == HAL_I2C_STATE_BUSY_RX) |
| 5566 | 5566 | { |
|
| 5567 | hi2c->EventCount++; |
5567 | /* Generate Restart */ |
| 5568 | } |
5568 | hi2c->Instance->CR1 |= I2C_CR1_START; |
| 5569 | else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
5569 | |
| 5570 | { |
5570 | hi2c->EventCount++; |
| 5571 | /* Write data to DR */ |
5571 | } |
| 5572 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
5572 | else if ((hi2c->XferCount > 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
| 5573 | 5573 | { |
|
| 5574 | /* Increment Buffer pointer */ |
5574 | /* Write data to DR */ |
| 5575 | hi2c->pBuffPtr++; |
5575 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
| 5576 | 5576 | ||
| 5577 | /* Update counter */ |
5577 | /* Increment Buffer pointer */ |
| 5578 | hi2c->XferCount--; |
5578 | hi2c->pBuffPtr++; |
| 5579 | } |
5579 | |
| 5580 | else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
5580 | /* Update counter */ |
| 5581 | { |
5581 | hi2c->XferCount--; |
| 5582 | /* Generate Stop condition then Call TxCpltCallback() */ |
5582 | } |
| 5583 | /* Disable EVT, BUF and ERR interrupt */ |
5583 | else if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX)) |
| 5584 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
5584 | { |
| 5585 | 5585 | /* Generate Stop condition then Call TxCpltCallback() */ |
|
| 5586 | /* Generate Stop */ |
5586 | /* Disable EVT, BUF and ERR interrupt */ |
| 5587 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
5587 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 5588 | 5588 | ||
| 5589 | hi2c->PreviousState = I2C_STATE_NONE; |
5589 | /* Generate Stop */ |
| 5590 | hi2c->State = HAL_I2C_STATE_READY; |
5590 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 5591 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5591 | |
| 5592 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5592 | hi2c->PreviousState = I2C_STATE_NONE; |
| 5593 | hi2c->MemTxCpltCallback(hi2c); |
5593 | hi2c->State = HAL_I2C_STATE_READY; |
| 5594 | #else |
5594 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5595 | HAL_I2C_MemTxCpltCallback(hi2c); |
5595 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5596 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5596 | hi2c->MemTxCpltCallback(hi2c); |
| 5597 | } |
5597 | #else |
| 5598 | else |
5598 | HAL_I2C_MemTxCpltCallback(hi2c); |
| 5599 | { |
5599 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5600 | /* Do nothing */ |
5600 | } |
| 5601 | } |
5601 | else |
| 5602 | } |
5602 | { |
| 5603 | else |
5603 | /* Do nothing */ |
| 5604 | { |
5604 | } |
| 5605 | /* Do nothing */ |
5605 | } |
| 5606 | } |
5606 | else |
| 5607 | } |
5607 | { |
| 5608 | 5608 | /* Clear TXE and BTF flags */ |
|
| 5609 | /** |
5609 | I2C_Flush_DR(hi2c); |
| 5610 | * @brief Handle RXNE flag for Master |
5610 | } |
| 5611 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5611 | } |
| 5612 | * the configuration information for I2C module |
5612 | |
| 5613 | * @retval None |
5613 | /** |
| 5614 | */ |
5614 | * @brief Handle RXNE flag for Master |
| 5615 | static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) |
5615 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5616 | { |
5616 | * the configuration information for I2C module |
| 5617 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX) |
5617 | * @retval None |
| 5618 | { |
5618 | */ |
| 5619 | uint32_t tmp; |
5619 | static void I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c) |
| 5620 | 5620 | { |
|
| 5621 | tmp = hi2c->XferCount; |
5621 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX) |
| 5622 | if (tmp > 3U) |
5622 | { |
| 5623 | { |
5623 | uint32_t tmp; |
| 5624 | /* Read data from DR */ |
5624 | |
| 5625 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
5625 | tmp = hi2c->XferCount; |
| 5626 | 5626 | if (tmp > 3U) |
|
| 5627 | /* Increment Buffer pointer */ |
5627 | { |
| 5628 | hi2c->pBuffPtr++; |
5628 | /* Read data from DR */ |
| 5629 | 5629 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
|
| 5630 | /* Update counter */ |
5630 | |
| 5631 | hi2c->XferCount--; |
5631 | /* Increment Buffer pointer */ |
| 5632 | 5632 | hi2c->pBuffPtr++; |
|
| 5633 | if (hi2c->XferCount == (uint16_t)3) |
5633 | |
| 5634 | { |
5634 | /* Update counter */ |
| 5635 | /* Disable BUF interrupt, this help to treat correctly the last 4 bytes |
5635 | hi2c->XferCount--; |
| 5636 | on BTF subroutine */ |
5636 | |
| 5637 | /* Disable BUF interrupt */ |
5637 | if (hi2c->XferCount == (uint16_t)3) |
| 5638 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
5638 | { |
| 5639 | } |
5639 | /* Disable BUF interrupt, this help to treat correctly the last 4 bytes |
| 5640 | } |
5640 | on BTF subroutine */ |
| 5641 | else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U))) |
5641 | /* Disable BUF interrupt */ |
| 5642 | { |
5642 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
| 5643 | if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK) |
5643 | } |
| 5644 | { |
5644 | } |
| 5645 | /* Disable Acknowledge */ |
5645 | else if ((hi2c->XferOptions != I2C_FIRST_AND_NEXT_FRAME) && ((tmp == 1U) || (tmp == 0U))) |
| 5646 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
5646 | { |
| 5647 | 5647 | if (I2C_WaitOnSTOPRequestThroughIT(hi2c) == HAL_OK) |
|
| 5648 | /* Disable EVT, BUF and ERR interrupt */ |
5648 | { |
| 5649 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
5649 | /* Disable Acknowledge */ |
| 5650 | 5650 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
|
| 5651 | /* Read data from DR */ |
5651 | |
| 5652 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
5652 | /* Disable EVT, BUF and ERR interrupt */ |
| 5653 | 5653 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
|
| 5654 | /* Increment Buffer pointer */ |
5654 | |
| 5655 | hi2c->pBuffPtr++; |
5655 | /* Read data from DR */ |
| 5656 | 5656 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
|
| 5657 | /* Update counter */ |
5657 | |
| 5658 | hi2c->XferCount--; |
5658 | /* Increment Buffer pointer */ |
| 5659 | 5659 | hi2c->pBuffPtr++; |
|
| 5660 | hi2c->State = HAL_I2C_STATE_READY; |
5660 | |
| 5661 | 5661 | /* Update counter */ |
|
| 5662 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
5662 | hi2c->XferCount--; |
| 5663 | { |
5663 | |
| 5664 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5664 | hi2c->State = HAL_I2C_STATE_READY; |
| 5665 | hi2c->PreviousState = I2C_STATE_NONE; |
5665 | |
| 5666 | 5666 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
|
| 5667 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5667 | { |
| 5668 | hi2c->MemRxCpltCallback(hi2c); |
5668 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5669 | #else |
5669 | hi2c->PreviousState = I2C_STATE_NONE; |
| 5670 | HAL_I2C_MemRxCpltCallback(hi2c); |
5670 | |
| 5671 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5671 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5672 | } |
5672 | hi2c->MemRxCpltCallback(hi2c); |
| 5673 | else |
5673 | #else |
| 5674 | { |
5674 | HAL_I2C_MemRxCpltCallback(hi2c); |
| 5675 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5675 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5676 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
5676 | } |
| 5677 | 5677 | else |
|
| 5678 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5678 | { |
| 5679 | hi2c->MasterRxCpltCallback(hi2c); |
5679 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5680 | #else |
5680 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
| 5681 | HAL_I2C_MasterRxCpltCallback(hi2c); |
5681 | |
| 5682 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5682 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5683 | } |
5683 | hi2c->MasterRxCpltCallback(hi2c); |
| 5684 | } |
5684 | #else |
| 5685 | else |
5685 | HAL_I2C_MasterRxCpltCallback(hi2c); |
| 5686 | { |
5686 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5687 | /* Disable EVT, BUF and ERR interrupt */ |
5687 | } |
| 5688 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
5688 | } |
| 5689 | 5689 | else |
|
| 5690 | /* Read data from DR */ |
5690 | { |
| 5691 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
5691 | /* Disable EVT, BUF and ERR interrupt */ |
| 5692 | 5692 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
|
| 5693 | /* Increment Buffer pointer */ |
5693 | |
| 5694 | hi2c->pBuffPtr++; |
5694 | /* Read data from DR */ |
| 5695 | 5695 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
|
| 5696 | /* Update counter */ |
5696 | |
| 5697 | hi2c->XferCount--; |
5697 | /* Increment Buffer pointer */ |
| 5698 | 5698 | hi2c->pBuffPtr++; |
|
| 5699 | hi2c->State = HAL_I2C_STATE_READY; |
5699 | |
| 5700 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5700 | /* Update counter */ |
| 5701 | 5701 | hi2c->XferCount--; |
|
| 5702 | /* Call user error callback */ |
5702 | |
| 5703 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5703 | hi2c->State = HAL_I2C_STATE_READY; |
| 5704 | hi2c->ErrorCallback(hi2c); |
5704 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5705 | #else |
5705 | |
| 5706 | HAL_I2C_ErrorCallback(hi2c); |
5706 | /* Call user error callback */ |
| 5707 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5707 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5708 | } |
5708 | hi2c->ErrorCallback(hi2c); |
| 5709 | } |
5709 | #else |
| 5710 | else |
5710 | HAL_I2C_ErrorCallback(hi2c); |
| 5711 | { |
5711 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5712 | /* Do nothing */ |
5712 | } |
| 5713 | } |
5713 | } |
| 5714 | } |
5714 | else |
| 5715 | } |
5715 | { |
| 5716 | 5716 | /* Disable BUF interrupt, this help to treat correctly the last 2 bytes |
|
| 5717 | /** |
5717 | on BTF subroutine if there is a reception delay between N-1 and N byte */ |
| 5718 | * @brief Handle BTF flag for Master receiver |
5718 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
| 5719 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5719 | } |
| 5720 | * the configuration information for I2C module |
5720 | } |
| 5721 | * @retval None |
5721 | } |
| 5722 | */ |
5722 | |
| 5723 | static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) |
5723 | /** |
| 5724 | { |
5724 | * @brief Handle BTF flag for Master receiver |
| 5725 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
5725 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5726 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
5726 | * the configuration information for I2C module |
| 5727 | 5727 | * @retval None |
|
| 5728 | if (hi2c->XferCount == 4U) |
5728 | */ |
| 5729 | { |
5729 | static void I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c) |
| 5730 | /* Disable BUF interrupt, this help to treat correctly the last 2 bytes |
5730 | { |
| 5731 | on BTF subroutine if there is a reception delay between N-1 and N byte */ |
5731 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
| 5732 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
5732 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
| 5733 | 5733 | ||
| 5734 | /* Read data from DR */ |
5734 | if (hi2c->XferCount == 4U) |
| 5735 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
5735 | { |
| 5736 | 5736 | /* Disable BUF interrupt, this help to treat correctly the last 2 bytes |
|
| 5737 | /* Increment Buffer pointer */ |
5737 | on BTF subroutine if there is a reception delay between N-1 and N byte */ |
| 5738 | hi2c->pBuffPtr++; |
5738 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
| 5739 | 5739 | ||
| 5740 | /* Update counter */ |
5740 | /* Read data from DR */ |
| 5741 | hi2c->XferCount--; |
5741 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 5742 | } |
5742 | |
| 5743 | else if (hi2c->XferCount == 3U) |
5743 | /* Increment Buffer pointer */ |
| 5744 | { |
5744 | hi2c->pBuffPtr++; |
| 5745 | /* Disable BUF interrupt, this help to treat correctly the last 2 bytes |
5745 | |
| 5746 | on BTF subroutine if there is a reception delay between N-1 and N byte */ |
5746 | /* Update counter */ |
| 5747 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
5747 | hi2c->XferCount--; |
| 5748 | 5748 | } |
|
| 5749 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME)) |
5749 | else if (hi2c->XferCount == 3U) |
| 5750 | { |
5750 | { |
| 5751 | /* Disable Acknowledge */ |
5751 | /* Disable BUF interrupt, this help to treat correctly the last 2 bytes |
| 5752 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
5752 | on BTF subroutine if there is a reception delay between N-1 and N byte */ |
| 5753 | } |
5753 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
| 5754 | 5754 | ||
| 5755 | /* Read data from DR */ |
5755 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME)) |
| 5756 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
5756 | { |
| 5757 | 5757 | /* Disable Acknowledge */ |
|
| 5758 | /* Increment Buffer pointer */ |
5758 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 5759 | hi2c->pBuffPtr++; |
5759 | } |
| 5760 | 5760 | ||
| 5761 | /* Update counter */ |
5761 | /* Read data from DR */ |
| 5762 | hi2c->XferCount--; |
5762 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 5763 | } |
5763 | |
| 5764 | else if (hi2c->XferCount == 2U) |
5764 | /* Increment Buffer pointer */ |
| 5765 | { |
5765 | hi2c->pBuffPtr++; |
| 5766 | /* Prepare next transfer or stop current transfer */ |
5766 | |
| 5767 | if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP)) |
5767 | /* Update counter */ |
| 5768 | { |
5768 | hi2c->XferCount--; |
| 5769 | /* Disable Acknowledge */ |
5769 | } |
| 5770 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
5770 | else if (hi2c->XferCount == 2U) |
| 5771 | } |
5771 | { |
| 5772 | else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME)) |
5772 | /* Prepare next transfer or stop current transfer */ |
| 5773 | { |
5773 | if ((CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP)) |
| 5774 | /* Enable Acknowledge */ |
5774 | { |
| 5775 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
5775 | /* Disable Acknowledge */ |
| 5776 | } |
5776 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 5777 | else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP) |
5777 | } |
| 5778 | { |
5778 | else if ((CurrentXferOptions == I2C_NEXT_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_NEXT_FRAME)) |
| 5779 | /* Generate Stop */ |
5779 | { |
| 5780 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
5780 | /* Enable Acknowledge */ |
| 5781 | } |
5781 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 5782 | else |
5782 | } |
| 5783 | { |
5783 | else if (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP) |
| 5784 | /* Do nothing */ |
5784 | { |
| 5785 | } |
5785 | /* Generate Stop */ |
| 5786 | 5786 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
|
| 5787 | /* Read data from DR */ |
5787 | } |
| 5788 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
5788 | else |
| 5789 | 5789 | { |
|
| 5790 | /* Increment Buffer pointer */ |
5790 | /* Do nothing */ |
| 5791 | hi2c->pBuffPtr++; |
5791 | } |
| 5792 | 5792 | ||
| 5793 | /* Update counter */ |
5793 | /* Read data from DR */ |
| 5794 | hi2c->XferCount--; |
5794 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 5795 | 5795 | ||
| 5796 | /* Read data from DR */ |
5796 | /* Increment Buffer pointer */ |
| 5797 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
5797 | hi2c->pBuffPtr++; |
| 5798 | 5798 | ||
| 5799 | /* Increment Buffer pointer */ |
5799 | /* Update counter */ |
| 5800 | hi2c->pBuffPtr++; |
5800 | hi2c->XferCount--; |
| 5801 | 5801 | ||
| 5802 | /* Update counter */ |
5802 | /* Read data from DR */ |
| 5803 | hi2c->XferCount--; |
5803 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 5804 | 5804 | ||
| 5805 | /* Disable EVT and ERR interrupt */ |
5805 | /* Increment Buffer pointer */ |
| 5806 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
5806 | hi2c->pBuffPtr++; |
| 5807 | 5807 | ||
| 5808 | hi2c->State = HAL_I2C_STATE_READY; |
5808 | /* Update counter */ |
| 5809 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
5809 | hi2c->XferCount--; |
| 5810 | { |
5810 | |
| 5811 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5811 | /* Disable EVT and ERR interrupt */ |
| 5812 | hi2c->PreviousState = I2C_STATE_NONE; |
5812 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 5813 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5813 | |
| 5814 | hi2c->MemRxCpltCallback(hi2c); |
5814 | hi2c->State = HAL_I2C_STATE_READY; |
| 5815 | #else |
5815 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
| 5816 | HAL_I2C_MemRxCpltCallback(hi2c); |
5816 | { |
| 5817 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5817 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5818 | } |
5818 | hi2c->PreviousState = I2C_STATE_NONE; |
| 5819 | else |
5819 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5820 | { |
5820 | hi2c->MemRxCpltCallback(hi2c); |
| 5821 | hi2c->Mode = HAL_I2C_MODE_NONE; |
5821 | #else |
| 5822 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
5822 | HAL_I2C_MemRxCpltCallback(hi2c); |
| 5823 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
5823 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5824 | hi2c->MasterRxCpltCallback(hi2c); |
5824 | } |
| 5825 | #else |
5825 | else |
| 5826 | HAL_I2C_MasterRxCpltCallback(hi2c); |
5826 | { |
| 5827 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
5827 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 5828 | } |
5828 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
| 5829 | } |
5829 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 5830 | else |
5830 | hi2c->MasterRxCpltCallback(hi2c); |
| 5831 | { |
5831 | #else |
| 5832 | /* Read data from DR */ |
5832 | HAL_I2C_MasterRxCpltCallback(hi2c); |
| 5833 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
5833 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 5834 | 5834 | } |
|
| 5835 | /* Increment Buffer pointer */ |
5835 | } |
| 5836 | hi2c->pBuffPtr++; |
5836 | else |
| 5837 | 5837 | { |
|
| 5838 | /* Update counter */ |
5838 | /* Read data from DR */ |
| 5839 | hi2c->XferCount--; |
5839 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 5840 | } |
5840 | |
| 5841 | } |
5841 | /* Increment Buffer pointer */ |
| 5842 | 5842 | hi2c->pBuffPtr++; |
|
| 5843 | /** |
5843 | |
| 5844 | * @brief Handle SB flag for Master |
5844 | /* Update counter */ |
| 5845 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5845 | hi2c->XferCount--; |
| 5846 | * the configuration information for I2C module |
5846 | } |
| 5847 | * @retval None |
5847 | } |
| 5848 | */ |
5848 | |
| 5849 | static void I2C_Master_SB(I2C_HandleTypeDef *hi2c) |
5849 | /** |
| 5850 | { |
5850 | * @brief Handle SB flag for Master |
| 5851 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
5851 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5852 | { |
5852 | * the configuration information for I2C module |
| 5853 | if (hi2c->EventCount == 0U) |
5853 | * @retval None |
| 5854 | { |
5854 | */ |
| 5855 | /* Send slave address */ |
5855 | static void I2C_Master_SB(I2C_HandleTypeDef *hi2c) |
| 5856 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); |
5856 | { |
| 5857 | } |
5857 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
| 5858 | else |
5858 | { |
| 5859 | { |
5859 | if (hi2c->EventCount == 0U) |
| 5860 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); |
5860 | { |
| 5861 | } |
5861 | /* Send slave address */ |
| 5862 | } |
5862 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); |
| 5863 | else |
5863 | } |
| 5864 | { |
5864 | else |
| 5865 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
5865 | { |
| 5866 | { |
5866 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); |
| 5867 | /* Send slave 7 Bits address */ |
5867 | } |
| 5868 | if (hi2c->State == HAL_I2C_STATE_BUSY_TX) |
5868 | } |
| 5869 | { |
5869 | else |
| 5870 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); |
5870 | { |
| 5871 | } |
5871 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
| 5872 | else |
5872 | { |
| 5873 | { |
5873 | /* Send slave 7 Bits address */ |
| 5874 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); |
5874 | if (hi2c->State == HAL_I2C_STATE_BUSY_TX) |
| 5875 | } |
5875 | { |
| 5876 | 5876 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(hi2c->Devaddress); |
|
| 5877 | if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) |
5877 | } |
| 5878 | || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) |
5878 | else |
| 5879 | { |
5879 | { |
| 5880 | /* Enable DMA Request */ |
5880 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(hi2c->Devaddress); |
| 5881 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
5881 | } |
| 5882 | } |
5882 | |
| 5883 | } |
5883 | if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) |
| 5884 | else |
5884 | || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) |
| 5885 | { |
5885 | { |
| 5886 | if (hi2c->EventCount == 0U) |
5886 | /* Enable DMA Request */ |
| 5887 | { |
5887 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 5888 | /* Send header of slave address */ |
5888 | } |
| 5889 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); |
5889 | } |
| 5890 | } |
5890 | else |
| 5891 | else if (hi2c->EventCount == 1U) |
5891 | { |
| 5892 | { |
5892 | if (hi2c->EventCount == 0U) |
| 5893 | /* Send header of slave address */ |
5893 | { |
| 5894 | hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); |
5894 | /* Send header of slave address */ |
| 5895 | } |
5895 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(hi2c->Devaddress); |
| 5896 | else |
5896 | } |
| 5897 | { |
5897 | else if (hi2c->EventCount == 1U) |
| 5898 | /* Do nothing */ |
5898 | { |
| 5899 | } |
5899 | /* Send header of slave address */ |
| 5900 | } |
5900 | hi2c->Instance->DR = I2C_10BIT_HEADER_READ(hi2c->Devaddress); |
| 5901 | } |
5901 | } |
| 5902 | } |
5902 | else |
| 5903 | 5903 | { |
|
| 5904 | /** |
5904 | /* Do nothing */ |
| 5905 | * @brief Handle ADD10 flag for Master |
5905 | } |
| 5906 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5906 | } |
| 5907 | * the configuration information for I2C module |
5907 | } |
| 5908 | * @retval None |
5908 | } |
| 5909 | */ |
5909 | |
| 5910 | static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) |
5910 | /** |
| 5911 | { |
5911 | * @brief Handle ADD10 flag for Master |
| 5912 | /* Send slave address */ |
5912 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5913 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); |
5913 | * the configuration information for I2C module |
| 5914 | 5914 | * @retval None |
|
| 5915 | if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) |
5915 | */ |
| 5916 | || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) |
5916 | static void I2C_Master_ADD10(I2C_HandleTypeDef *hi2c) |
| 5917 | { |
5917 | { |
| 5918 | /* Enable DMA Request */ |
5918 | /* Send slave address */ |
| 5919 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
5919 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(hi2c->Devaddress); |
| 5920 | } |
5920 | |
| 5921 | } |
5921 | if (((hi2c->hdmatx != NULL) && (hi2c->hdmatx->XferCpltCallback != NULL)) |
| 5922 | 5922 | || ((hi2c->hdmarx != NULL) && (hi2c->hdmarx->XferCpltCallback != NULL))) |
|
| 5923 | /** |
5923 | { |
| 5924 | * @brief Handle ADDR flag for Master |
5924 | /* Enable DMA Request */ |
| 5925 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
5925 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 5926 | * the configuration information for I2C module |
5926 | } |
| 5927 | * @retval None |
5927 | } |
| 5928 | */ |
5928 | |
| 5929 | static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) |
5929 | /** |
| 5930 | { |
5930 | * @brief Handle ADDR flag for Master |
| 5931 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
5931 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 5932 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
5932 | * the configuration information for I2C module |
| 5933 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
5933 | * @retval None |
| 5934 | uint32_t Prev_State = hi2c->PreviousState; |
5934 | */ |
| 5935 | 5935 | static void I2C_Master_ADDR(I2C_HandleTypeDef *hi2c) |
|
| 5936 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX) |
5936 | { |
| 5937 | { |
5937 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
| 5938 | if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) |
5938 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
| 5939 | { |
5939 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
| 5940 | /* Clear ADDR flag */ |
5940 | uint32_t Prev_State = hi2c->PreviousState; |
| 5941 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
5941 | |
| 5942 | } |
5942 | if (hi2c->State == HAL_I2C_STATE_BUSY_RX) |
| 5943 | else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) |
5943 | { |
| 5944 | { |
5944 | if ((hi2c->EventCount == 0U) && (CurrentMode == HAL_I2C_MODE_MEM)) |
| 5945 | /* Clear ADDR flag */ |
5945 | { |
| 5946 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
5946 | /* Clear ADDR flag */ |
| 5947 | 5947 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
|
| 5948 | /* Generate Restart */ |
5948 | } |
| 5949 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
5949 | else if ((hi2c->EventCount == 0U) && (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)) |
| 5950 | 5950 | { |
|
| 5951 | hi2c->EventCount++; |
5951 | /* Clear ADDR flag */ |
| 5952 | } |
5952 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 5953 | else |
5953 | |
| 5954 | { |
5954 | /* Generate Restart */ |
| 5955 | if (hi2c->XferCount == 0U) |
5955 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 5956 | { |
5956 | |
| 5957 | /* Clear ADDR flag */ |
5957 | hi2c->EventCount++; |
| 5958 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
5958 | } |
| 5959 | 5959 | else |
|
| 5960 | /* Generate Stop */ |
5960 | { |
| 5961 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
5961 | if (hi2c->XferCount == 0U) |
| 5962 | } |
5962 | { |
| 5963 | else if (hi2c->XferCount == 1U) |
5963 | /* Clear ADDR flag */ |
| 5964 | { |
5964 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 5965 | if (CurrentXferOptions == I2C_NO_OPTION_FRAME) |
5965 | |
| 5966 | { |
5966 | /* Generate Stop */ |
| 5967 | /* Disable Acknowledge */ |
5967 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 5968 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
5968 | } |
| 5969 | 5969 | else if (hi2c->XferCount == 1U) |
|
| 5970 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
5970 | { |
| 5971 | { |
5971 | if (CurrentXferOptions == I2C_NO_OPTION_FRAME) |
| 5972 | /* Disable Acknowledge */ |
5972 | { |
| 5973 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
5973 | /* Disable Acknowledge */ |
| 5974 | 5974 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
|
| 5975 | /* Clear ADDR flag */ |
5975 | |
| 5976 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
5976 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
| 5977 | } |
5977 | { |
| 5978 | else |
5978 | /* Disable Acknowledge */ |
| 5979 | { |
5979 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 5980 | /* Clear ADDR flag */ |
5980 | |
| 5981 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
5981 | /* Clear ADDR flag */ |
| 5982 | 5982 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
|
| 5983 | /* Generate Stop */ |
5983 | } |
| 5984 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
5984 | else |
| 5985 | } |
5985 | { |
| 5986 | } |
5986 | /* Clear ADDR flag */ |
| 5987 | /* Prepare next transfer or stop current transfer */ |
5987 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 5988 | else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ |
5988 | |
| 5989 | && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME))) |
5989 | /* Generate Stop */ |
| 5990 | { |
5990 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 5991 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) |
5991 | } |
| 5992 | { |
5992 | } |
| 5993 | /* Disable Acknowledge */ |
5993 | /* Prepare next transfer or stop current transfer */ |
| 5994 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
5994 | else if ((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) \ |
| 5995 | } |
5995 | && ((Prev_State != I2C_STATE_MASTER_BUSY_RX) || (CurrentXferOptions == I2C_FIRST_FRAME))) |
| 5996 | else |
5996 | { |
| 5997 | { |
5997 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) |
| 5998 | /* Enable Acknowledge */ |
5998 | { |
| 5999 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
5999 | /* Disable Acknowledge */ |
| 6000 | } |
6000 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 6001 | 6001 | } |
|
| 6002 | /* Clear ADDR flag */ |
6002 | else |
| 6003 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
6003 | { |
| 6004 | } |
6004 | /* Enable Acknowledge */ |
| 6005 | else |
6005 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 6006 | { |
6006 | } |
| 6007 | /* Disable Acknowledge */ |
6007 | |
| 6008 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
6008 | /* Clear ADDR flag */ |
| 6009 | 6009 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
|
| 6010 | /* Clear ADDR flag */ |
6010 | } |
| 6011 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
6011 | else |
| 6012 | 6012 | { |
|
| 6013 | /* Generate Stop */ |
6013 | /* Disable Acknowledge */ |
| 6014 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
6014 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 6015 | } |
6015 | |
| 6016 | } |
6016 | /* Clear ADDR flag */ |
| 6017 | else if (hi2c->XferCount == 2U) |
6017 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 6018 | { |
6018 | |
| 6019 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) |
6019 | /* Generate Stop */ |
| 6020 | { |
6020 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 6021 | /* Enable Pos */ |
6021 | } |
| 6022 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
6022 | } |
| 6023 | 6023 | else if (hi2c->XferCount == 2U) |
|
| 6024 | /* Clear ADDR flag */ |
6024 | { |
| 6025 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
6025 | if ((CurrentXferOptions != I2C_NEXT_FRAME) && (CurrentXferOptions != I2C_FIRST_AND_NEXT_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME_NO_STOP)) |
| 6026 | 6026 | { |
|
| 6027 | /* Disable Acknowledge */ |
6027 | /* Enable Pos */ |
| 6028 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
6028 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS); |
| 6029 | } |
6029 | |
| 6030 | else |
6030 | /* Clear ADDR flag */ |
| 6031 | { |
6031 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 6032 | /* Enable Acknowledge */ |
6032 | |
| 6033 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
6033 | /* Disable Acknowledge */ |
| 6034 | 6034 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
|
| 6035 | /* Clear ADDR flag */ |
6035 | } |
| 6036 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
6036 | else |
| 6037 | } |
6037 | { |
| 6038 | 6038 | /* Enable Acknowledge */ |
|
| 6039 | if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) |
6039 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 6040 | { |
6040 | |
| 6041 | /* Enable Last DMA bit */ |
6041 | /* Clear ADDR flag */ |
| 6042 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
6042 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 6043 | } |
6043 | } |
| 6044 | } |
6044 | |
| 6045 | else |
6045 | if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) |
| 6046 | { |
6046 | { |
| 6047 | /* Enable Acknowledge */ |
6047 | /* Enable Last DMA bit */ |
| 6048 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
6048 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
| 6049 | 6049 | } |
|
| 6050 | if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) |
6050 | } |
| 6051 | { |
6051 | else |
| 6052 | /* Enable Last DMA bit */ |
6052 | { |
| 6053 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
6053 | /* Enable Acknowledge */ |
| 6054 | } |
6054 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 6055 | 6055 | ||
| 6056 | /* Clear ADDR flag */ |
6056 | if (((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) && ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME_NO_STOP) || (CurrentXferOptions == I2C_LAST_FRAME))) |
| 6057 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
6057 | { |
| 6058 | } |
6058 | /* Enable Last DMA bit */ |
| 6059 | 6059 | SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
|
| 6060 | /* Reset Event counter */ |
6060 | } |
| 6061 | hi2c->EventCount = 0U; |
6061 | |
| 6062 | } |
6062 | /* Clear ADDR flag */ |
| 6063 | } |
6063 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 6064 | else |
6064 | } |
| 6065 | { |
6065 | |
| 6066 | /* Clear ADDR flag */ |
6066 | /* Reset Event counter */ |
| 6067 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
6067 | hi2c->EventCount = 0U; |
| 6068 | } |
6068 | } |
| 6069 | } |
6069 | } |
| 6070 | 6070 | else |
|
| 6071 | /** |
6071 | { |
| 6072 | * @brief Handle TXE flag for Slave |
6072 | /* Clear ADDR flag */ |
| 6073 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
6073 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 6074 | * the configuration information for I2C module |
6074 | } |
| 6075 | * @retval None |
6075 | } |
| 6076 | */ |
6076 | |
| 6077 | static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) |
6077 | /** |
| 6078 | { |
6078 | * @brief Handle TXE flag for Slave |
| 6079 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
6079 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 6080 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
6080 | * the configuration information for I2C module |
| 6081 | 6081 | * @retval None |
|
| 6082 | if (hi2c->XferCount != 0U) |
6082 | */ |
| 6083 | { |
6083 | static void I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c) |
| 6084 | /* Write data to DR */ |
6084 | { |
| 6085 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
6085 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
| 6086 | 6086 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
|
| 6087 | /* Increment Buffer pointer */ |
6087 | |
| 6088 | hi2c->pBuffPtr++; |
6088 | if (hi2c->XferCount != 0U) |
| 6089 | 6089 | { |
|
| 6090 | /* Update counter */ |
6090 | /* Write data to DR */ |
| 6091 | hi2c->XferCount--; |
6091 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
| 6092 | 6092 | ||
| 6093 | if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) |
6093 | /* Increment Buffer pointer */ |
| 6094 | { |
6094 | hi2c->pBuffPtr++; |
| 6095 | /* Last Byte is received, disable Interrupt */ |
6095 | |
| 6096 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
6096 | /* Update counter */ |
| 6097 | 6097 | hi2c->XferCount--; |
|
| 6098 | /* Set state at HAL_I2C_STATE_LISTEN */ |
6098 | |
| 6099 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
6099 | if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN)) |
| 6100 | hi2c->State = HAL_I2C_STATE_LISTEN; |
6100 | { |
| 6101 | 6101 | /* Last Byte is received, disable Interrupt */ |
|
| 6102 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
6102 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
| 6103 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
6103 | |
| 6104 | hi2c->SlaveTxCpltCallback(hi2c); |
6104 | /* Set state at HAL_I2C_STATE_LISTEN */ |
| 6105 | #else |
6105 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
| 6106 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
6106 | hi2c->State = HAL_I2C_STATE_LISTEN; |
| 6107 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
6107 | |
| 6108 | } |
6108 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
| 6109 | } |
6109 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 6110 | } |
6110 | hi2c->SlaveTxCpltCallback(hi2c); |
| 6111 | 6111 | #else |
|
| 6112 | /** |
6112 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
| 6113 | * @brief Handle BTF flag for Slave transmitter |
6113 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 6114 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
6114 | } |
| 6115 | * the configuration information for I2C module |
6115 | } |
| 6116 | * @retval None |
6116 | } |
| 6117 | */ |
6117 | |
| 6118 | static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) |
6118 | /** |
| 6119 | { |
6119 | * @brief Handle BTF flag for Slave transmitter |
| 6120 | if (hi2c->XferCount != 0U) |
6120 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 6121 | { |
6121 | * the configuration information for I2C module |
| 6122 | /* Write data to DR */ |
6122 | * @retval None |
| 6123 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
6123 | */ |
| 6124 | 6124 | static void I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c) |
|
| 6125 | /* Increment Buffer pointer */ |
6125 | { |
| 6126 | hi2c->pBuffPtr++; |
6126 | if (hi2c->XferCount != 0U) |
| 6127 | 6127 | { |
|
| 6128 | /* Update counter */ |
6128 | /* Write data to DR */ |
| 6129 | hi2c->XferCount--; |
6129 | hi2c->Instance->DR = *hi2c->pBuffPtr; |
| 6130 | } |
6130 | |
| 6131 | } |
6131 | /* Increment Buffer pointer */ |
| 6132 | 6132 | hi2c->pBuffPtr++; |
|
| 6133 | /** |
6133 | |
| 6134 | * @brief Handle RXNE flag for Slave |
6134 | /* Update counter */ |
| 6135 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
6135 | hi2c->XferCount--; |
| 6136 | * the configuration information for I2C module |
6136 | } |
| 6137 | * @retval None |
6137 | } |
| 6138 | */ |
6138 | |
| 6139 | static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) |
6139 | /** |
| 6140 | { |
6140 | * @brief Handle RXNE flag for Slave |
| 6141 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
6141 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 6142 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
6142 | * the configuration information for I2C module |
| 6143 | 6143 | * @retval None |
|
| 6144 | if (hi2c->XferCount != 0U) |
6144 | */ |
| 6145 | { |
6145 | static void I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c) |
| 6146 | /* Read data from DR */ |
6146 | { |
| 6147 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
6147 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
| 6148 | 6148 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
|
| 6149 | /* Increment Buffer pointer */ |
6149 | |
| 6150 | hi2c->pBuffPtr++; |
6150 | if (hi2c->XferCount != 0U) |
| 6151 | 6151 | { |
|
| 6152 | /* Update counter */ |
6152 | /* Read data from DR */ |
| 6153 | hi2c->XferCount--; |
6153 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 6154 | 6154 | ||
| 6155 | if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
6155 | /* Increment Buffer pointer */ |
| 6156 | { |
6156 | hi2c->pBuffPtr++; |
| 6157 | /* Last Byte is received, disable Interrupt */ |
6157 | |
| 6158 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
6158 | /* Update counter */ |
| 6159 | 6159 | hi2c->XferCount--; |
|
| 6160 | /* Set state at HAL_I2C_STATE_LISTEN */ |
6160 | |
| 6161 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; |
6161 | if ((hi2c->XferCount == 0U) && (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
| 6162 | hi2c->State = HAL_I2C_STATE_LISTEN; |
6162 | { |
| 6163 | 6163 | /* Last Byte is received, disable Interrupt */ |
|
| 6164 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
6164 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF); |
| 6165 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
6165 | |
| 6166 | hi2c->SlaveRxCpltCallback(hi2c); |
6166 | /* Set state at HAL_I2C_STATE_LISTEN */ |
| 6167 | #else |
6167 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; |
| 6168 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
6168 | hi2c->State = HAL_I2C_STATE_LISTEN; |
| 6169 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
6169 | |
| 6170 | } |
6170 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
| 6171 | } |
6171 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 6172 | } |
6172 | hi2c->SlaveRxCpltCallback(hi2c); |
| 6173 | 6173 | #else |
|
| 6174 | /** |
6174 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
| 6175 | * @brief Handle BTF flag for Slave receiver |
6175 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 6176 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
6176 | } |
| 6177 | * the configuration information for I2C module |
6177 | } |
| 6178 | * @retval None |
6178 | } |
| 6179 | */ |
6179 | |
| 6180 | static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) |
6180 | /** |
| 6181 | { |
6181 | * @brief Handle BTF flag for Slave receiver |
| 6182 | if (hi2c->XferCount != 0U) |
6182 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 6183 | { |
6183 | * the configuration information for I2C module |
| 6184 | /* Read data from DR */ |
6184 | * @retval None |
| 6185 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
6185 | */ |
| 6186 | 6186 | static void I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c) |
|
| 6187 | /* Increment Buffer pointer */ |
6187 | { |
| 6188 | hi2c->pBuffPtr++; |
6188 | if (hi2c->XferCount != 0U) |
| 6189 | 6189 | { |
|
| 6190 | /* Update counter */ |
6190 | /* Read data from DR */ |
| 6191 | hi2c->XferCount--; |
6191 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 6192 | } |
6192 | |
| 6193 | } |
6193 | /* Increment Buffer pointer */ |
| 6194 | 6194 | hi2c->pBuffPtr++; |
|
| 6195 | /** |
6195 | |
| 6196 | * @brief Handle ADD flag for Slave |
6196 | /* Update counter */ |
| 6197 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
6197 | hi2c->XferCount--; |
| 6198 | * the configuration information for I2C module |
6198 | } |
| 6199 | * @param IT2Flags Interrupt2 flags to handle. |
6199 | } |
| 6200 | * @retval None |
6200 | |
| 6201 | */ |
6201 | /** |
| 6202 | static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) |
6202 | * @brief Handle ADD flag for Slave |
| 6203 | { |
6203 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 6204 | uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; |
6204 | * the configuration information for I2C module |
| 6205 | uint16_t SlaveAddrCode; |
6205 | * @param IT2Flags Interrupt2 flags to handle. |
| 6206 | 6206 | * @retval None |
|
| 6207 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
6207 | */ |
| 6208 | { |
6208 | static void I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c, uint32_t IT2Flags) |
| 6209 | /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */ |
6209 | { |
| 6210 | __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF)); |
6210 | uint8_t TransferDirection = I2C_DIRECTION_RECEIVE; |
| 6211 | 6211 | uint16_t SlaveAddrCode; |
|
| 6212 | /* Transfer Direction requested by Master */ |
6212 | |
| 6213 | if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET) |
6213 | if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
| 6214 | { |
6214 | { |
| 6215 | TransferDirection = I2C_DIRECTION_TRANSMIT; |
6215 | /* Disable BUF interrupt, BUF enabling is manage through slave specific interface */ |
| 6216 | } |
6216 | __HAL_I2C_DISABLE_IT(hi2c, (I2C_IT_BUF)); |
| 6217 | 6217 | ||
| 6218 | if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET) |
6218 | /* Transfer Direction requested by Master */ |
| 6219 | { |
6219 | if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_TRA) == RESET) |
| 6220 | SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1; |
6220 | { |
| 6221 | } |
6221 | TransferDirection = I2C_DIRECTION_TRANSMIT; |
| 6222 | else |
6222 | } |
| 6223 | { |
6223 | |
| 6224 | SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2; |
6224 | if (I2C_CHECK_FLAG(IT2Flags, I2C_FLAG_DUALF) == RESET) |
| 6225 | } |
6225 | { |
| 6226 | 6226 | SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress1; |
|
| 6227 | /* Process Unlocked */ |
6227 | } |
| 6228 | __HAL_UNLOCK(hi2c); |
6228 | else |
| 6229 | 6229 | { |
|
| 6230 | /* Call Slave Addr callback */ |
6230 | SlaveAddrCode = (uint16_t)hi2c->Init.OwnAddress2; |
| 6231 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
6231 | } |
| 6232 | hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode); |
6232 | |
| 6233 | #else |
6233 | /* Process Unlocked */ |
| 6234 | HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); |
6234 | __HAL_UNLOCK(hi2c); |
| 6235 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
6235 | |
| 6236 | } |
6236 | /* Call Slave Addr callback */ |
| 6237 | else |
6237 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 6238 | { |
6238 | hi2c->AddrCallback(hi2c, TransferDirection, SlaveAddrCode); |
| 6239 | /* Clear ADDR flag */ |
6239 | #else |
| 6240 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
6240 | HAL_I2C_AddrCallback(hi2c, TransferDirection, SlaveAddrCode); |
| 6241 | 6241 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|
| 6242 | /* Process Unlocked */ |
6242 | } |
| 6243 | __HAL_UNLOCK(hi2c); |
6243 | else |
| 6244 | } |
6244 | { |
| 6245 | } |
6245 | /* Clear ADDR flag */ |
| 6246 | 6246 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
|
| 6247 | /** |
6247 | |
| 6248 | * @brief Handle STOPF flag for Slave |
6248 | /* Process Unlocked */ |
| 6249 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
6249 | __HAL_UNLOCK(hi2c); |
| 6250 | * the configuration information for I2C module |
6250 | } |
| 6251 | * @retval None |
6251 | } |
| 6252 | */ |
6252 | |
| 6253 | static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) |
6253 | /** |
| 6254 | { |
6254 | * @brief Handle STOPF flag for Slave |
| 6255 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
6255 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 6256 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
6256 | * the configuration information for I2C module |
| 6257 | 6257 | * @retval None |
|
| 6258 | /* Disable EVT, BUF and ERR interrupt */ |
6258 | */ |
| 6259 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
6259 | static void I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c) |
| 6260 | 6260 | { |
|
| 6261 | /* Clear STOPF flag */ |
6261 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
| 6262 | __HAL_I2C_CLEAR_STOPFLAG(hi2c); |
6262 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
| 6263 | 6263 | ||
| 6264 | /* Disable Acknowledge */ |
6264 | /* Disable EVT, BUF and ERR interrupt */ |
| 6265 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
6265 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 6266 | 6266 | ||
| 6267 | /* If a DMA is ongoing, Update handle size context */ |
6267 | /* Clear STOPF flag */ |
| 6268 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
6268 | __HAL_I2C_CLEAR_STOPFLAG(hi2c); |
| 6269 | { |
6269 | |
| 6270 | if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
6270 | /* Disable Acknowledge */ |
| 6271 | { |
6271 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 6272 | hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmarx)); |
6272 | |
| 6273 | 6273 | /* If a DMA is ongoing, Update handle size context */ |
|
| 6274 | if (hi2c->XferCount != 0U) |
6274 | if ((hi2c->Instance->CR2 & I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
| 6275 | { |
6275 | { |
| 6276 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
6276 | if ((CurrentState == HAL_I2C_STATE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN)) |
| 6277 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
6277 | { |
| 6278 | } |
6278 | hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx)); |
| 6279 | 6279 | ||
| 6280 | /* Disable, stop the current DMA */ |
6280 | if (hi2c->XferCount != 0U) |
| 6281 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
6281 | { |
| 6282 | 6282 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
|
| 6283 | /* Abort DMA Xfer if any */ |
6283 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
| 6284 | if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) |
6284 | } |
| 6285 | { |
6285 | |
| 6286 | /* Set the I2C DMA Abort callback : |
6286 | /* Disable, stop the current DMA */ |
| 6287 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
6287 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 6288 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
6288 | |
| 6289 | 6289 | /* Abort DMA Xfer if any */ |
|
| 6290 | /* Abort DMA RX */ |
6290 | if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) |
| 6291 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
6291 | { |
| 6292 | { |
6292 | /* Set the I2C DMA Abort callback : |
| 6293 | /* Call Directly XferAbortCallback function in case of error */ |
6293 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
| 6294 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
6294 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
| 6295 | } |
6295 | |
| 6296 | } |
6296 | /* Abort DMA RX */ |
| 6297 | } |
6297 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
| 6298 | else |
6298 | { |
| 6299 | { |
6299 | /* Call Directly XferAbortCallback function in case of error */ |
| 6300 | hi2c->XferCount = (uint16_t)(__HAL_DMA_GET_COUNTER(hi2c->hdmatx)); |
6300 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
| 6301 | 6301 | } |
|
| 6302 | if (hi2c->XferCount != 0U) |
6302 | } |
| 6303 | { |
6303 | } |
| 6304 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
6304 | else |
| 6305 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
6305 | { |
| 6306 | } |
6306 | hi2c->XferCount = (uint16_t)(I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx)); |
| 6307 | 6307 | ||
| 6308 | /* Disable, stop the current DMA */ |
6308 | if (hi2c->XferCount != 0U) |
| 6309 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
6309 | { |
| 6310 | 6310 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
|
| 6311 | /* Abort DMA Xfer if any */ |
6311 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
| 6312 | if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) |
6312 | } |
| 6313 | { |
6313 | |
| 6314 | /* Set the I2C DMA Abort callback : |
6314 | /* Disable, stop the current DMA */ |
| 6315 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
6315 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 6316 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
6316 | |
| 6317 | 6317 | /* Abort DMA Xfer if any */ |
|
| 6318 | /* Abort DMA TX */ |
6318 | if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) |
| 6319 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
6319 | { |
| 6320 | { |
6320 | /* Set the I2C DMA Abort callback : |
| 6321 | /* Call Directly XferAbortCallback function in case of error */ |
6321 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
| 6322 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
6322 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
| 6323 | } |
6323 | |
| 6324 | } |
6324 | /* Abort DMA TX */ |
| 6325 | } |
6325 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
| 6326 | } |
6326 | { |
| 6327 | 6327 | /* Call Directly XferAbortCallback function in case of error */ |
|
| 6328 | /* All data are not transferred, so set error code accordingly */ |
6328 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
| 6329 | if (hi2c->XferCount != 0U) |
6329 | } |
| 6330 | { |
6330 | } |
| 6331 | /* Store Last receive data if any */ |
6331 | } |
| 6332 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
6332 | } |
| 6333 | { |
6333 | |
| 6334 | /* Read data from DR */ |
6334 | /* All data are not transferred, so set error code accordingly */ |
| 6335 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
6335 | if (hi2c->XferCount != 0U) |
| 6336 | 6336 | { |
|
| 6337 | /* Increment Buffer pointer */ |
6337 | /* Store Last receive data if any */ |
| 6338 | hi2c->pBuffPtr++; |
6338 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) |
| 6339 | 6339 | { |
|
| 6340 | /* Update counter */ |
6340 | /* Read data from DR */ |
| 6341 | hi2c->XferCount--; |
6341 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 6342 | } |
6342 | |
| 6343 | 6343 | /* Increment Buffer pointer */ |
|
| 6344 | /* Store Last receive data if any */ |
6344 | hi2c->pBuffPtr++; |
| 6345 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
6345 | |
| 6346 | { |
6346 | /* Update counter */ |
| 6347 | /* Read data from DR */ |
6347 | hi2c->XferCount--; |
| 6348 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
6348 | } |
| 6349 | 6349 | ||
| 6350 | /* Increment Buffer pointer */ |
6350 | /* Store Last receive data if any */ |
| 6351 | hi2c->pBuffPtr++; |
6351 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
| 6352 | 6352 | { |
|
| 6353 | /* Update counter */ |
6353 | /* Read data from DR */ |
| 6354 | hi2c->XferCount--; |
6354 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 6355 | } |
6355 | |
| 6356 | 6356 | /* Increment Buffer pointer */ |
|
| 6357 | if (hi2c->XferCount != 0U) |
6357 | hi2c->pBuffPtr++; |
| 6358 | { |
6358 | |
| 6359 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
6359 | /* Update counter */ |
| 6360 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
6360 | hi2c->XferCount--; |
| 6361 | } |
6361 | } |
| 6362 | } |
6362 | |
| 6363 | 6363 | if (hi2c->XferCount != 0U) |
|
| 6364 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
6364 | { |
| 6365 | { |
6365 | /* Set ErrorCode corresponding to a Non-Acknowledge */ |
| 6366 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
6366 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
| 6367 | I2C_ITError(hi2c); |
6367 | } |
| 6368 | } |
6368 | } |
| 6369 | else |
6369 | |
| 6370 | { |
6370 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
| 6371 | if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) |
6371 | { |
| 6372 | { |
6372 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
| 6373 | /* Set state at HAL_I2C_STATE_LISTEN */ |
6373 | I2C_ITError(hi2c); |
| 6374 | hi2c->PreviousState = I2C_STATE_NONE; |
6374 | } |
| 6375 | hi2c->State = HAL_I2C_STATE_LISTEN; |
6375 | else |
| 6376 | 6376 | { |
|
| 6377 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
6377 | if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) |
| 6378 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
6378 | { |
| 6379 | hi2c->SlaveRxCpltCallback(hi2c); |
6379 | /* Set state at HAL_I2C_STATE_LISTEN */ |
| 6380 | #else |
6380 | hi2c->PreviousState = I2C_STATE_NONE; |
| 6381 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
6381 | hi2c->State = HAL_I2C_STATE_LISTEN; |
| 6382 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
6382 | |
| 6383 | } |
6383 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
| 6384 | 6384 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|
| 6385 | if (hi2c->State == HAL_I2C_STATE_LISTEN) |
6385 | hi2c->SlaveRxCpltCallback(hi2c); |
| 6386 | { |
6386 | #else |
| 6387 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
6387 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
| 6388 | hi2c->PreviousState = I2C_STATE_NONE; |
6388 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 6389 | hi2c->State = HAL_I2C_STATE_READY; |
6389 | } |
| 6390 | hi2c->Mode = HAL_I2C_MODE_NONE; |
6390 | |
| 6391 | 6391 | if (hi2c->State == HAL_I2C_STATE_LISTEN) |
|
| 6392 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
6392 | { |
| 6393 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
6393 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 6394 | hi2c->ListenCpltCallback(hi2c); |
6394 | hi2c->PreviousState = I2C_STATE_NONE; |
| 6395 | #else |
6395 | hi2c->State = HAL_I2C_STATE_READY; |
| 6396 | HAL_I2C_ListenCpltCallback(hi2c); |
6396 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 6397 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
6397 | |
| 6398 | } |
6398 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
| 6399 | else |
6399 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 6400 | { |
6400 | hi2c->ListenCpltCallback(hi2c); |
| 6401 | if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) |
6401 | #else |
| 6402 | { |
6402 | HAL_I2C_ListenCpltCallback(hi2c); |
| 6403 | hi2c->PreviousState = I2C_STATE_NONE; |
6403 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 6404 | hi2c->State = HAL_I2C_STATE_READY; |
6404 | } |
| 6405 | hi2c->Mode = HAL_I2C_MODE_NONE; |
6405 | else |
| 6406 | 6406 | { |
|
| 6407 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
6407 | if ((hi2c->PreviousState == I2C_STATE_SLAVE_BUSY_RX) || (CurrentState == HAL_I2C_STATE_BUSY_RX)) |
| 6408 | hi2c->SlaveRxCpltCallback(hi2c); |
6408 | { |
| 6409 | #else |
6409 | hi2c->PreviousState = I2C_STATE_NONE; |
| 6410 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
6410 | hi2c->State = HAL_I2C_STATE_READY; |
| 6411 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
6411 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 6412 | } |
6412 | |
| 6413 | } |
6413 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 6414 | } |
6414 | hi2c->SlaveRxCpltCallback(hi2c); |
| 6415 | } |
6415 | #else |
| 6416 | 6416 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
|
| 6417 | /** |
6417 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 6418 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
6418 | } |
| 6419 | * the configuration information for I2C module |
6419 | } |
| 6420 | * @retval None |
6420 | } |
| 6421 | */ |
6421 | } |
| 6422 | static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) |
6422 | |
| 6423 | { |
6423 | /** |
| 6424 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
6424 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 6425 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
6425 | * the configuration information for I2C module |
| 6426 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
6426 | * @retval None |
| 6427 | 6427 | */ |
|
| 6428 | if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ |
6428 | static void I2C_Slave_AF(I2C_HandleTypeDef *hi2c) |
| 6429 | (CurrentState == HAL_I2C_STATE_LISTEN)) |
6429 | { |
| 6430 | { |
6430 | /* Declaration of temporary variables to prevent undefined behavior of volatile usage */ |
| 6431 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
6431 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
| 6432 | 6432 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
|
| 6433 | /* Disable EVT, BUF and ERR interrupt */ |
6433 | |
| 6434 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
6434 | if (((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) && \ |
| 6435 | 6435 | (CurrentState == HAL_I2C_STATE_LISTEN)) |
|
| 6436 | /* Clear AF flag */ |
6436 | { |
| 6437 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
6437 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 6438 | 6438 | ||
| 6439 | /* Disable Acknowledge */ |
6439 | /* Disable EVT, BUF and ERR interrupt */ |
| 6440 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
6440 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 6441 | 6441 | ||
| 6442 | hi2c->PreviousState = I2C_STATE_NONE; |
6442 | /* Clear AF flag */ |
| 6443 | hi2c->State = HAL_I2C_STATE_READY; |
6443 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
| 6444 | hi2c->Mode = HAL_I2C_MODE_NONE; |
6444 | |
| 6445 | 6445 | /* Disable Acknowledge */ |
|
| 6446 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
6446 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 6447 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
6447 | |
| 6448 | hi2c->ListenCpltCallback(hi2c); |
6448 | hi2c->PreviousState = I2C_STATE_NONE; |
| 6449 | #else |
6449 | hi2c->State = HAL_I2C_STATE_READY; |
| 6450 | HAL_I2C_ListenCpltCallback(hi2c); |
6450 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 6451 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
6451 | |
| 6452 | } |
6452 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
| 6453 | else if (CurrentState == HAL_I2C_STATE_BUSY_TX) |
6453 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 6454 | { |
6454 | hi2c->ListenCpltCallback(hi2c); |
| 6455 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
6455 | #else |
| 6456 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
6456 | HAL_I2C_ListenCpltCallback(hi2c); |
| 6457 | hi2c->State = HAL_I2C_STATE_READY; |
6457 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 6458 | hi2c->Mode = HAL_I2C_MODE_NONE; |
6458 | } |
| 6459 | 6459 | else if (CurrentState == HAL_I2C_STATE_BUSY_TX) |
|
| 6460 | /* Disable EVT, BUF and ERR interrupt */ |
6460 | { |
| 6461 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
6461 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 6462 | 6462 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
|
| 6463 | /* Clear AF flag */ |
6463 | hi2c->State = HAL_I2C_STATE_READY; |
| 6464 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
6464 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 6465 | 6465 | ||
| 6466 | /* Disable Acknowledge */ |
6466 | /* Disable EVT, BUF and ERR interrupt */ |
| 6467 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
6467 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 6468 | 6468 | ||
| 6469 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
6469 | /* Clear AF flag */ |
| 6470 | hi2c->SlaveTxCpltCallback(hi2c); |
6470 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
| 6471 | #else |
6471 | |
| 6472 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
6472 | /* Disable Acknowledge */ |
| 6473 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
6473 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 6474 | } |
6474 | |
| 6475 | else |
6475 | /* Clear TXE flag */ |
| 6476 | { |
6476 | I2C_Flush_DR(hi2c); |
| 6477 | /* Clear AF flag only */ |
6477 | |
| 6478 | /* State Listen, but XferOptions == FIRST or NEXT */ |
6478 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 6479 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
6479 | hi2c->SlaveTxCpltCallback(hi2c); |
| 6480 | } |
6480 | #else |
| 6481 | } |
6481 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
| 6482 | 6482 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|
| 6483 | /** |
6483 | } |
| 6484 | * @brief I2C interrupts error process |
6484 | else |
| 6485 | * @param hi2c I2C handle. |
6485 | { |
| 6486 | * @retval None |
6486 | /* Clear AF flag only */ |
| 6487 | */ |
6487 | /* State Listen, but XferOptions == FIRST or NEXT */ |
| 6488 | static void I2C_ITError(I2C_HandleTypeDef *hi2c) |
6488 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
| 6489 | { |
6489 | } |
| 6490 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
6490 | } |
| 6491 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
6491 | |
| 6492 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
6492 | /** |
| 6493 | uint32_t CurrentError; |
6493 | * @brief I2C interrupts error process |
| 6494 | 6494 | * @param hi2c I2C handle. |
|
| 6495 | if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) |
6495 | * @retval None |
| 6496 | { |
6496 | */ |
| 6497 | /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ |
6497 | static void I2C_ITError(I2C_HandleTypeDef *hi2c) |
| 6498 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
6498 | { |
| 6499 | } |
6499 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
| 6500 | 6500 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
|
| 6501 | if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
6501 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
| 6502 | { |
6502 | uint32_t CurrentError; |
| 6503 | /* keep HAL_I2C_STATE_LISTEN */ |
6503 | |
| 6504 | hi2c->PreviousState = I2C_STATE_NONE; |
6504 | if (((CurrentMode == HAL_I2C_MODE_MASTER) || (CurrentMode == HAL_I2C_MODE_MEM)) && (CurrentState == HAL_I2C_STATE_BUSY_RX)) |
| 6505 | hi2c->State = HAL_I2C_STATE_LISTEN; |
6505 | { |
| 6506 | } |
6506 | /* Disable Pos bit in I2C CR1 when error occurred in Master/Mem Receive IT Process */ |
| 6507 | else |
6507 | hi2c->Instance->CR1 &= ~I2C_CR1_POS; |
| 6508 | { |
6508 | } |
| 6509 | /* If state is an abort treatment on going, don't change state */ |
6509 | |
| 6510 | /* This change will be do later */ |
6510 | if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
| 6511 | if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT)) |
6511 | { |
| 6512 | { |
6512 | /* keep HAL_I2C_STATE_LISTEN */ |
| 6513 | hi2c->State = HAL_I2C_STATE_READY; |
6513 | hi2c->PreviousState = I2C_STATE_NONE; |
| 6514 | hi2c->Mode = HAL_I2C_MODE_NONE; |
6514 | hi2c->State = HAL_I2C_STATE_LISTEN; |
| 6515 | } |
6515 | } |
| 6516 | hi2c->PreviousState = I2C_STATE_NONE; |
6516 | else |
| 6517 | } |
6517 | { |
| 6518 | 6518 | /* If state is an abort treatment on going, don't change state */ |
|
| 6519 | /* Abort DMA transfer */ |
6519 | /* This change will be do later */ |
| 6520 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
6520 | if ((READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) != I2C_CR2_DMAEN) && (CurrentState != HAL_I2C_STATE_ABORT)) |
| 6521 | { |
6521 | { |
| 6522 | hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; |
6522 | hi2c->State = HAL_I2C_STATE_READY; |
| 6523 | 6523 | hi2c->Mode = HAL_I2C_MODE_NONE; |
|
| 6524 | if (hi2c->hdmatx->State != HAL_DMA_STATE_READY) |
6524 | } |
| 6525 | { |
6525 | hi2c->PreviousState = I2C_STATE_NONE; |
| 6526 | /* Set the DMA Abort callback : |
6526 | } |
| 6527 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
6527 | |
| 6528 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
6528 | /* Abort DMA transfer */ |
| 6529 | 6529 | if (READ_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN) == I2C_CR2_DMAEN) |
|
| 6530 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
6530 | { |
| 6531 | { |
6531 | hi2c->Instance->CR2 &= ~I2C_CR2_DMAEN; |
| 6532 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
6532 | |
| 6533 | __HAL_I2C_DISABLE(hi2c); |
6533 | if (hi2c->hdmatx->State != HAL_DMA_STATE_READY) |
| 6534 | 6534 | { |
|
| 6535 | hi2c->State = HAL_I2C_STATE_READY; |
6535 | /* Set the DMA Abort callback : |
| 6536 | 6536 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
|
| 6537 | /* Call Directly XferAbortCallback function in case of error */ |
6537 | hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; |
| 6538 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
6538 | |
| 6539 | } |
6539 | if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) |
| 6540 | } |
6540 | { |
| 6541 | else |
6541 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
| 6542 | { |
6542 | __HAL_I2C_DISABLE(hi2c); |
| 6543 | /* Set the DMA Abort callback : |
6543 | |
| 6544 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
6544 | hi2c->State = HAL_I2C_STATE_READY; |
| 6545 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
6545 | |
| 6546 | 6546 | /* Call Directly XferAbortCallback function in case of error */ |
|
| 6547 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
6547 | hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); |
| 6548 | { |
6548 | } |
| 6549 | /* Store Last receive data if any */ |
6549 | } |
| 6550 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
6550 | else |
| 6551 | { |
6551 | { |
| 6552 | /* Read data from DR */ |
6552 | /* Set the DMA Abort callback : |
| 6553 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
6553 | will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ |
| 6554 | 6554 | hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; |
|
| 6555 | /* Increment Buffer pointer */ |
6555 | |
| 6556 | hi2c->pBuffPtr++; |
6556 | if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) |
| 6557 | } |
6557 | { |
| 6558 | 6558 | /* Store Last receive data if any */ |
|
| 6559 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
6559 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
| 6560 | __HAL_I2C_DISABLE(hi2c); |
6560 | { |
| 6561 | 6561 | /* Read data from DR */ |
|
| 6562 | hi2c->State = HAL_I2C_STATE_READY; |
6562 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 6563 | 6563 | ||
| 6564 | /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ |
6564 | /* Increment Buffer pointer */ |
| 6565 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
6565 | hi2c->pBuffPtr++; |
| 6566 | } |
6566 | } |
| 6567 | } |
6567 | |
| 6568 | } |
6568 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
| 6569 | else if (hi2c->State == HAL_I2C_STATE_ABORT) |
6569 | __HAL_I2C_DISABLE(hi2c); |
| 6570 | { |
6570 | |
| 6571 | hi2c->State = HAL_I2C_STATE_READY; |
6571 | hi2c->State = HAL_I2C_STATE_READY; |
| 6572 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
6572 | |
| 6573 | 6573 | /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ |
|
| 6574 | /* Store Last receive data if any */ |
6574 | hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); |
| 6575 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
6575 | } |
| 6576 | { |
6576 | } |
| 6577 | /* Read data from DR */ |
6577 | } |
| 6578 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
6578 | else if (hi2c->State == HAL_I2C_STATE_ABORT) |
| 6579 | 6579 | { |
|
| 6580 | /* Increment Buffer pointer */ |
6580 | hi2c->State = HAL_I2C_STATE_READY; |
| 6581 | hi2c->pBuffPtr++; |
6581 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 6582 | } |
6582 | |
| 6583 | 6583 | /* Store Last receive data if any */ |
|
| 6584 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
6584 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
| 6585 | __HAL_I2C_DISABLE(hi2c); |
6585 | { |
| 6586 | 6586 | /* Read data from DR */ |
|
| 6587 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
6587 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 6588 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
6588 | |
| 6589 | hi2c->AbortCpltCallback(hi2c); |
6589 | /* Increment Buffer pointer */ |
| 6590 | #else |
6590 | hi2c->pBuffPtr++; |
| 6591 | HAL_I2C_AbortCpltCallback(hi2c); |
6591 | } |
| 6592 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
6592 | |
| 6593 | } |
6593 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
| 6594 | else |
6594 | __HAL_I2C_DISABLE(hi2c); |
| 6595 | { |
6595 | |
| 6596 | /* Store Last receive data if any */ |
6596 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
| 6597 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
6597 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 6598 | { |
6598 | hi2c->AbortCpltCallback(hi2c); |
| 6599 | /* Read data from DR */ |
6599 | #else |
| 6600 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
6600 | HAL_I2C_AbortCpltCallback(hi2c); |
| 6601 | 6601 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|
| 6602 | /* Increment Buffer pointer */ |
6602 | } |
| 6603 | hi2c->pBuffPtr++; |
6603 | else |
| 6604 | } |
6604 | { |
| 6605 | 6605 | /* Store Last receive data if any */ |
|
| 6606 | /* Call user error callback */ |
6606 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) |
| 6607 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
6607 | { |
| 6608 | hi2c->ErrorCallback(hi2c); |
6608 | /* Read data from DR */ |
| 6609 | #else |
6609 | *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->DR; |
| 6610 | HAL_I2C_ErrorCallback(hi2c); |
6610 | |
| 6611 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
6611 | /* Increment Buffer pointer */ |
| 6612 | } |
6612 | hi2c->pBuffPtr++; |
| 6613 | 6613 | } |
|
| 6614 | /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */ |
6614 | |
| 6615 | CurrentError = hi2c->ErrorCode; |
6615 | /* Call user error callback */ |
| 6616 | 6616 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|
| 6617 | if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \ |
6617 | hi2c->ErrorCallback(hi2c); |
| 6618 | ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \ |
6618 | #else |
| 6619 | ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \ |
6619 | HAL_I2C_ErrorCallback(hi2c); |
| 6620 | ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR)) |
6620 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 6621 | { |
6621 | } |
| 6622 | /* Disable EVT, BUF and ERR interrupt */ |
6622 | |
| 6623 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
6623 | /* STOP Flag is not set after a NACK reception, BusError, ArbitrationLost, OverRun */ |
| 6624 | } |
6624 | CurrentError = hi2c->ErrorCode; |
| 6625 | 6625 | ||
| 6626 | /* So may inform upper layer that listen phase is stopped */ |
6626 | if (((CurrentError & HAL_I2C_ERROR_BERR) == HAL_I2C_ERROR_BERR) || \ |
| 6627 | /* during NACK error treatment */ |
6627 | ((CurrentError & HAL_I2C_ERROR_ARLO) == HAL_I2C_ERROR_ARLO) || \ |
| 6628 | CurrentState = hi2c->State; |
6628 | ((CurrentError & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) || \ |
| 6629 | if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN)) |
6629 | ((CurrentError & HAL_I2C_ERROR_OVR) == HAL_I2C_ERROR_OVR)) |
| 6630 | { |
6630 | { |
| 6631 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
6631 | /* Disable EVT, BUF and ERR interrupt */ |
| 6632 | hi2c->PreviousState = I2C_STATE_NONE; |
6632 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR); |
| 6633 | hi2c->State = HAL_I2C_STATE_READY; |
6633 | } |
| 6634 | hi2c->Mode = HAL_I2C_MODE_NONE; |
6634 | |
| 6635 | 6635 | /* So may inform upper layer that listen phase is stopped */ |
|
| 6636 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
6636 | /* during NACK error treatment */ |
| 6637 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
6637 | CurrentState = hi2c->State; |
| 6638 | hi2c->ListenCpltCallback(hi2c); |
6638 | if (((hi2c->ErrorCode & HAL_I2C_ERROR_AF) == HAL_I2C_ERROR_AF) && (CurrentState == HAL_I2C_STATE_LISTEN)) |
| 6639 | #else |
6639 | { |
| 6640 | HAL_I2C_ListenCpltCallback(hi2c); |
6640 | hi2c->XferOptions = I2C_NO_OPTION_FRAME; |
| 6641 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
6641 | hi2c->PreviousState = I2C_STATE_NONE; |
| 6642 | } |
6642 | hi2c->State = HAL_I2C_STATE_READY; |
| 6643 | } |
6643 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 6644 | 6644 | ||
| 6645 | /** |
6645 | /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ |
| 6646 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
6646 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 6647 | * the configuration information for I2C module |
6647 | hi2c->ListenCpltCallback(hi2c); |
| 6648 | * @param DevAddress Target device address: The device 7 bits address value |
6648 | #else |
| 6649 | * in datasheet must be shifted to the left before calling the interface |
6649 | HAL_I2C_ListenCpltCallback(hi2c); |
| 6650 | * @param Timeout Timeout duration |
6650 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 6651 | * @param Tickstart Tick start value |
6651 | } |
| 6652 | * @retval HAL status |
6652 | } |
| 6653 | */ |
6653 | |
| 6654 | static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) |
6654 | /** |
| 6655 | { |
6655 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 6656 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
6656 | * the configuration information for I2C module |
| 6657 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
6657 | * @param DevAddress Target device address: The device 7 bits address value |
| 6658 | 6658 | * in datasheet must be shifted to the left before calling the interface |
|
| 6659 | /* Generate Start condition if first transfer */ |
6659 | * @param Timeout Timeout duration |
| 6660 | if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) |
6660 | * @param Tickstart Tick start value |
| 6661 | { |
6661 | * @retval HAL status |
| 6662 | /* Generate Start */ |
6662 | */ |
| 6663 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
6663 | static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) |
| 6664 | } |
6664 | { |
| 6665 | else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) |
6665 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
| 6666 | { |
6666 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
| 6667 | /* Generate ReStart */ |
6667 | |
| 6668 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
6668 | /* Generate Start condition if first transfer */ |
| 6669 | } |
6669 | if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) |
| 6670 | else |
6670 | { |
| 6671 | { |
6671 | /* Generate Start */ |
| 6672 | /* Do nothing */ |
6672 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 6673 | } |
6673 | } |
| 6674 | 6674 | else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) |
|
| 6675 | /* Wait until SB flag is set */ |
6675 | { |
| 6676 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
6676 | /* Generate ReStart */ |
| 6677 | { |
6677 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 6678 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
6678 | } |
| 6679 | { |
6679 | else |
| 6680 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
6680 | { |
| 6681 | } |
6681 | /* Do nothing */ |
| 6682 | return HAL_TIMEOUT; |
6682 | } |
| 6683 | } |
6683 | |
| 6684 | 6684 | /* Wait until SB flag is set */ |
|
| 6685 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
6685 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
| 6686 | { |
6686 | { |
| 6687 | /* Send slave address */ |
6687 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
| 6688 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
6688 | { |
| 6689 | } |
6689 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
| 6690 | else |
6690 | } |
| 6691 | { |
6691 | return HAL_TIMEOUT; |
| 6692 | /* Send header of slave address */ |
6692 | } |
| 6693 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); |
6693 | |
| 6694 | 6694 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
|
| 6695 | /* Wait until ADD10 flag is set */ |
6695 | { |
| 6696 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) |
6696 | /* Send slave address */ |
| 6697 | { |
6697 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
| 6698 | return HAL_ERROR; |
6698 | } |
| 6699 | } |
6699 | else |
| 6700 | 6700 | { |
|
| 6701 | /* Send slave address */ |
6701 | /* Send header of slave address */ |
| 6702 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); |
6702 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); |
| 6703 | } |
6703 | |
| 6704 | 6704 | /* Wait until ADD10 flag is set */ |
|
| 6705 | /* Wait until ADDR flag is set */ |
6705 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) |
| 6706 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
6706 | { |
| 6707 | { |
6707 | return HAL_ERROR; |
| 6708 | return HAL_ERROR; |
6708 | } |
| 6709 | } |
6709 | |
| 6710 | 6710 | /* Send slave address */ |
|
| 6711 | return HAL_OK; |
6711 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); |
| 6712 | } |
6712 | } |
| 6713 | 6713 | ||
| 6714 | /** |
6714 | /* Wait until ADDR flag is set */ |
| 6715 | * @brief Master sends target device address for read request. |
6715 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
| 6716 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
6716 | { |
| 6717 | * the configuration information for I2C module |
6717 | return HAL_ERROR; |
| 6718 | * @param DevAddress Target device address: The device 7 bits address value |
6718 | } |
| 6719 | * in datasheet must be shifted to the left before calling the interface |
6719 | |
| 6720 | * @param Timeout Timeout duration |
6720 | return HAL_OK; |
| 6721 | * @param Tickstart Tick start value |
6721 | } |
| 6722 | * @retval HAL status |
6722 | |
| 6723 | */ |
6723 | /** |
| 6724 | static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) |
6724 | * @brief Master sends target device address for read request. |
| 6725 | { |
6725 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 6726 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
6726 | * the configuration information for I2C module |
| 6727 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
6727 | * @param DevAddress Target device address: The device 7 bits address value |
| 6728 | 6728 | * in datasheet must be shifted to the left before calling the interface |
|
| 6729 | /* Enable Acknowledge */ |
6729 | * @param Timeout Timeout duration |
| 6730 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
6730 | * @param Tickstart Tick start value |
| 6731 | 6731 | * @retval HAL status |
|
| 6732 | /* Generate Start condition if first transfer */ |
6732 | */ |
| 6733 | if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) |
6733 | static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout, uint32_t Tickstart) |
| 6734 | { |
6734 | { |
| 6735 | /* Generate Start */ |
6735 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
| 6736 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
6736 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
| 6737 | } |
6737 | |
| 6738 | else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) |
6738 | /* Enable Acknowledge */ |
| 6739 | { |
6739 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 6740 | /* Generate ReStart */ |
6740 | |
| 6741 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
6741 | /* Generate Start condition if first transfer */ |
| 6742 | } |
6742 | if ((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_FIRST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME)) |
| 6743 | else |
6743 | { |
| 6744 | { |
6744 | /* Generate Start */ |
| 6745 | /* Do nothing */ |
6745 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 6746 | } |
6746 | } |
| 6747 | 6747 | else if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) |
|
| 6748 | /* Wait until SB flag is set */ |
6748 | { |
| 6749 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
6749 | /* Generate ReStart */ |
| 6750 | { |
6750 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 6751 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
6751 | } |
| 6752 | { |
6752 | else |
| 6753 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
6753 | { |
| 6754 | } |
6754 | /* Do nothing */ |
| 6755 | return HAL_TIMEOUT; |
6755 | } |
| 6756 | } |
6756 | |
| 6757 | 6757 | /* Wait until SB flag is set */ |
|
| 6758 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
6758 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
| 6759 | { |
6759 | { |
| 6760 | /* Send slave address */ |
6760 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
| 6761 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); |
6761 | { |
| 6762 | } |
6762 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
| 6763 | else |
6763 | } |
| 6764 | { |
6764 | return HAL_TIMEOUT; |
| 6765 | /* Send header of slave address */ |
6765 | } |
| 6766 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); |
6766 | |
| 6767 | 6767 | if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) |
|
| 6768 | /* Wait until ADD10 flag is set */ |
6768 | { |
| 6769 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) |
6769 | /* Send slave address */ |
| 6770 | { |
6770 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); |
| 6771 | return HAL_ERROR; |
6771 | } |
| 6772 | } |
6772 | else |
| 6773 | 6773 | { |
|
| 6774 | /* Send slave address */ |
6774 | /* Send header of slave address */ |
| 6775 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); |
6775 | hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress); |
| 6776 | 6776 | ||
| 6777 | /* Wait until ADDR flag is set */ |
6777 | /* Wait until ADD10 flag is set */ |
| 6778 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
6778 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout, Tickstart) != HAL_OK) |
| 6779 | { |
6779 | { |
| 6780 | return HAL_ERROR; |
6780 | return HAL_ERROR; |
| 6781 | } |
6781 | } |
| 6782 | 6782 | ||
| 6783 | /* Clear ADDR flag */ |
6783 | /* Send slave address */ |
| 6784 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
6784 | hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress); |
| 6785 | 6785 | ||
| 6786 | /* Generate Restart */ |
6786 | /* Wait until ADDR flag is set */ |
| 6787 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
6787 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
| 6788 | 6788 | { |
|
| 6789 | /* Wait until SB flag is set */ |
6789 | return HAL_ERROR; |
| 6790 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
6790 | } |
| 6791 | { |
6791 | |
| 6792 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
6792 | /* Clear ADDR flag */ |
| 6793 | { |
6793 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 6794 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
6794 | |
| 6795 | } |
6795 | /* Generate Restart */ |
| 6796 | return HAL_TIMEOUT; |
6796 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 6797 | } |
6797 | |
| 6798 | 6798 | /* Wait until SB flag is set */ |
|
| 6799 | /* Send header of slave address */ |
6799 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
| 6800 | hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); |
6800 | { |
| 6801 | } |
6801 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
| 6802 | 6802 | { |
|
| 6803 | /* Wait until ADDR flag is set */ |
6803 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
| 6804 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
6804 | } |
| 6805 | { |
6805 | return HAL_TIMEOUT; |
| 6806 | return HAL_ERROR; |
6806 | } |
| 6807 | } |
6807 | |
| 6808 | 6808 | /* Send header of slave address */ |
|
| 6809 | return HAL_OK; |
6809 | hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress); |
| 6810 | } |
6810 | } |
| 6811 | 6811 | ||
| 6812 | /** |
6812 | /* Wait until ADDR flag is set */ |
| 6813 | * @brief Master sends target device address followed by internal memory address for write request. |
6813 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
| 6814 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
6814 | { |
| 6815 | * the configuration information for I2C module |
6815 | return HAL_ERROR; |
| 6816 | * @param DevAddress Target device address: The device 7 bits address value |
6816 | } |
| 6817 | * in datasheet must be shifted to the left before calling the interface |
6817 | |
| 6818 | * @param MemAddress Internal memory address |
6818 | return HAL_OK; |
| 6819 | * @param MemAddSize Size of internal memory address |
6819 | } |
| 6820 | * @param Timeout Timeout duration |
6820 | |
| 6821 | * @param Tickstart Tick start value |
6821 | /** |
| 6822 | * @retval HAL status |
6822 | * @brief Master sends target device address followed by internal memory address for write request. |
| 6823 | */ |
6823 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 6824 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
6824 | * the configuration information for I2C module |
| 6825 | { |
6825 | * @param DevAddress Target device address: The device 7 bits address value |
| 6826 | /* Generate Start */ |
6826 | * in datasheet must be shifted to the left before calling the interface |
| 6827 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
6827 | * @param MemAddress Internal memory address |
| 6828 | 6828 | * @param MemAddSize Size of internal memory address |
|
| 6829 | /* Wait until SB flag is set */ |
6829 | * @param Timeout Timeout duration |
| 6830 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
6830 | * @param Tickstart Tick start value |
| 6831 | { |
6831 | * @retval HAL status |
| 6832 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
6832 | */ |
| 6833 | { |
6833 | static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
| 6834 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
6834 | { |
| 6835 | } |
6835 | /* Generate Start */ |
| 6836 | return HAL_TIMEOUT; |
6836 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 6837 | } |
6837 | |
| 6838 | 6838 | /* Wait until SB flag is set */ |
|
| 6839 | /* Send slave address */ |
6839 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
| 6840 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
6840 | { |
| 6841 | 6841 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
|
| 6842 | /* Wait until ADDR flag is set */ |
6842 | { |
| 6843 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
6843 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
| 6844 | { |
6844 | } |
| 6845 | return HAL_ERROR; |
6845 | return HAL_TIMEOUT; |
| 6846 | } |
6846 | } |
| 6847 | 6847 | ||
| 6848 | /* Clear ADDR flag */ |
6848 | /* Send slave address */ |
| 6849 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
6849 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
| 6850 | 6850 | ||
| 6851 | /* Wait until TXE flag is set */ |
6851 | /* Wait until ADDR flag is set */ |
| 6852 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
6852 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
| 6853 | { |
6853 | { |
| 6854 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
6854 | return HAL_ERROR; |
| 6855 | { |
6855 | } |
| 6856 | /* Generate Stop */ |
6856 | |
| 6857 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
6857 | /* Clear ADDR flag */ |
| 6858 | } |
6858 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 6859 | return HAL_ERROR; |
6859 | |
| 6860 | } |
6860 | /* Wait until TXE flag is set */ |
| 6861 | 6861 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
|
| 6862 | /* If Memory address size is 8Bit */ |
6862 | { |
| 6863 | if (MemAddSize == I2C_MEMADD_SIZE_8BIT) |
6863 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
| 6864 | { |
6864 | { |
| 6865 | /* Send Memory Address */ |
6865 | /* Generate Stop */ |
| 6866 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
6866 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 6867 | } |
6867 | } |
| 6868 | /* If Memory address size is 16Bit */ |
6868 | return HAL_ERROR; |
| 6869 | else |
6869 | } |
| 6870 | { |
6870 | |
| 6871 | /* Send MSB of Memory Address */ |
6871 | /* If Memory address size is 8Bit */ |
| 6872 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); |
6872 | if (MemAddSize == I2C_MEMADD_SIZE_8BIT) |
| 6873 | 6873 | { |
|
| 6874 | /* Wait until TXE flag is set */ |
6874 | /* Send Memory Address */ |
| 6875 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
6875 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
| 6876 | { |
6876 | } |
| 6877 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
6877 | /* If Memory address size is 16Bit */ |
| 6878 | { |
6878 | else |
| 6879 | /* Generate Stop */ |
6879 | { |
| 6880 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
6880 | /* Send MSB of Memory Address */ |
| 6881 | } |
6881 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); |
| 6882 | return HAL_ERROR; |
6882 | |
| 6883 | } |
6883 | /* Wait until TXE flag is set */ |
| 6884 | 6884 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
|
| 6885 | /* Send LSB of Memory Address */ |
6885 | { |
| 6886 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
6886 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
| 6887 | } |
6887 | { |
| 6888 | 6888 | /* Generate Stop */ |
|
| 6889 | return HAL_OK; |
6889 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 6890 | } |
6890 | } |
| 6891 | 6891 | return HAL_ERROR; |
|
| 6892 | /** |
6892 | } |
| 6893 | * @brief Master sends target device address followed by internal memory address for read request. |
6893 | |
| 6894 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
6894 | /* Send LSB of Memory Address */ |
| 6895 | * the configuration information for I2C module |
6895 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
| 6896 | * @param DevAddress Target device address: The device 7 bits address value |
6896 | } |
| 6897 | * in datasheet must be shifted to the left before calling the interface |
6897 | |
| 6898 | * @param MemAddress Internal memory address |
6898 | return HAL_OK; |
| 6899 | * @param MemAddSize Size of internal memory address |
6899 | } |
| 6900 | * @param Timeout Timeout duration |
6900 | |
| 6901 | * @param Tickstart Tick start value |
6901 | /** |
| 6902 | * @retval HAL status |
6902 | * @brief Master sends target device address followed by internal memory address for read request. |
| 6903 | */ |
6903 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 6904 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
6904 | * the configuration information for I2C module |
| 6905 | { |
6905 | * @param DevAddress Target device address: The device 7 bits address value |
| 6906 | /* Enable Acknowledge */ |
6906 | * in datasheet must be shifted to the left before calling the interface |
| 6907 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
6907 | * @param MemAddress Internal memory address |
| 6908 | 6908 | * @param MemAddSize Size of internal memory address |
|
| 6909 | /* Generate Start */ |
6909 | * @param Timeout Timeout duration |
| 6910 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
6910 | * @param Tickstart Tick start value |
| 6911 | 6911 | * @retval HAL status |
|
| 6912 | /* Wait until SB flag is set */ |
6912 | */ |
| 6913 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
6913 | static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart) |
| 6914 | { |
6914 | { |
| 6915 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
6915 | /* Enable Acknowledge */ |
| 6916 | { |
6916 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 6917 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
6917 | |
| 6918 | } |
6918 | /* Generate Start */ |
| 6919 | return HAL_TIMEOUT; |
6919 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 6920 | } |
6920 | |
| 6921 | 6921 | /* Wait until SB flag is set */ |
|
| 6922 | /* Send slave address */ |
6922 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
| 6923 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
6923 | { |
| 6924 | 6924 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
|
| 6925 | /* Wait until ADDR flag is set */ |
6925 | { |
| 6926 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
6926 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
| 6927 | { |
6927 | } |
| 6928 | return HAL_ERROR; |
6928 | return HAL_TIMEOUT; |
| 6929 | } |
6929 | } |
| 6930 | 6930 | ||
| 6931 | /* Clear ADDR flag */ |
6931 | /* Send slave address */ |
| 6932 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
6932 | hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress); |
| 6933 | 6933 | ||
| 6934 | /* Wait until TXE flag is set */ |
6934 | /* Wait until ADDR flag is set */ |
| 6935 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
6935 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
| 6936 | { |
6936 | { |
| 6937 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
6937 | return HAL_ERROR; |
| 6938 | { |
6938 | } |
| 6939 | /* Generate Stop */ |
6939 | |
| 6940 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
6940 | /* Clear ADDR flag */ |
| 6941 | } |
6941 | __HAL_I2C_CLEAR_ADDRFLAG(hi2c); |
| 6942 | return HAL_ERROR; |
6942 | |
| 6943 | } |
6943 | /* Wait until TXE flag is set */ |
| 6944 | 6944 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
|
| 6945 | /* If Memory address size is 8Bit */ |
6945 | { |
| 6946 | if (MemAddSize == I2C_MEMADD_SIZE_8BIT) |
6946 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
| 6947 | { |
6947 | { |
| 6948 | /* Send Memory Address */ |
6948 | /* Generate Stop */ |
| 6949 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
6949 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 6950 | } |
6950 | } |
| 6951 | /* If Memory address size is 16Bit */ |
6951 | return HAL_ERROR; |
| 6952 | else |
6952 | } |
| 6953 | { |
6953 | |
| 6954 | /* Send MSB of Memory Address */ |
6954 | /* If Memory address size is 8Bit */ |
| 6955 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); |
6955 | if (MemAddSize == I2C_MEMADD_SIZE_8BIT) |
| 6956 | 6956 | { |
|
| 6957 | /* Wait until TXE flag is set */ |
6957 | /* Send Memory Address */ |
| 6958 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
6958 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
| 6959 | { |
6959 | } |
| 6960 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
6960 | /* If Memory address size is 16Bit */ |
| 6961 | { |
6961 | else |
| 6962 | /* Generate Stop */ |
6962 | { |
| 6963 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
6963 | /* Send MSB of Memory Address */ |
| 6964 | } |
6964 | hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress); |
| 6965 | return HAL_ERROR; |
6965 | |
| 6966 | } |
6966 | /* Wait until TXE flag is set */ |
| 6967 | 6967 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
|
| 6968 | /* Send LSB of Memory Address */ |
6968 | { |
| 6969 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
6969 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
| 6970 | } |
6970 | { |
| 6971 | 6971 | /* Generate Stop */ |
|
| 6972 | /* Wait until TXE flag is set */ |
6972 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 6973 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
6973 | } |
| 6974 | { |
6974 | return HAL_ERROR; |
| 6975 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
6975 | } |
| 6976 | { |
6976 | |
| 6977 | /* Generate Stop */ |
6977 | /* Send LSB of Memory Address */ |
| 6978 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
6978 | hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress); |
| 6979 | } |
6979 | } |
| 6980 | return HAL_ERROR; |
6980 | |
| 6981 | } |
6981 | /* Wait until TXE flag is set */ |
| 6982 | 6982 | if (I2C_WaitOnTXEFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) |
|
| 6983 | /* Generate Restart */ |
6983 | { |
| 6984 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
6984 | if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) |
| 6985 | 6985 | { |
|
| 6986 | /* Wait until SB flag is set */ |
6986 | /* Generate Stop */ |
| 6987 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
6987 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 6988 | { |
6988 | } |
| 6989 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
6989 | return HAL_ERROR; |
| 6990 | { |
6990 | } |
| 6991 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
6991 | |
| 6992 | } |
6992 | /* Generate Restart */ |
| 6993 | return HAL_TIMEOUT; |
6993 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_START); |
| 6994 | } |
6994 | |
| 6995 | 6995 | /* Wait until SB flag is set */ |
|
| 6996 | /* Send slave address */ |
6996 | if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout, Tickstart) != HAL_OK) |
| 6997 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); |
6997 | { |
| 6998 | 6998 | if (READ_BIT(hi2c->Instance->CR1, I2C_CR1_START) == I2C_CR1_START) |
|
| 6999 | /* Wait until ADDR flag is set */ |
6999 | { |
| 7000 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
7000 | hi2c->ErrorCode = HAL_I2C_WRONG_START; |
| 7001 | { |
7001 | } |
| 7002 | return HAL_ERROR; |
7002 | return HAL_TIMEOUT; |
| 7003 | } |
7003 | } |
| 7004 | 7004 | ||
| 7005 | return HAL_OK; |
7005 | /* Send slave address */ |
| 7006 | } |
7006 | hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress); |
| 7007 | 7007 | ||
| 7008 | /** |
7008 | /* Wait until ADDR flag is set */ |
| 7009 | * @brief DMA I2C process complete callback. |
7009 | if (I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout, Tickstart) != HAL_OK) |
| 7010 | * @param hdma DMA handle |
7010 | { |
| 7011 | * @retval None |
7011 | return HAL_ERROR; |
| 7012 | */ |
7012 | } |
| 7013 | static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) |
7013 | |
| 7014 | { |
7014 | return HAL_OK; |
| 7015 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
7015 | } |
| 7016 | 7016 | ||
| 7017 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
7017 | /** |
| 7018 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
7018 | * @brief DMA I2C process complete callback. |
| 7019 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
7019 | * @param hdma DMA handle |
| 7020 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
7020 | * @retval None |
| 7021 | 7021 | */ |
|
| 7022 | /* Disable EVT and ERR interrupt */ |
7022 | static void I2C_DMAXferCplt(DMA_HandleTypeDef *hdma) |
| 7023 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
7023 | { |
| 7024 | 7024 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
|
| 7025 | /* Clear Complete callback */ |
7025 | |
| 7026 | if (hi2c->hdmatx != NULL) |
7026 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
| 7027 | { |
7027 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
| 7028 | hi2c->hdmatx->XferCpltCallback = NULL; |
7028 | HAL_I2C_ModeTypeDef CurrentMode = hi2c->Mode; |
| 7029 | } |
7029 | uint32_t CurrentXferOptions = hi2c->XferOptions; |
| 7030 | if (hi2c->hdmarx != NULL) |
7030 | |
| 7031 | { |
7031 | /* Disable EVT and ERR interrupt */ |
| 7032 | hi2c->hdmarx->XferCpltCallback = NULL; |
7032 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 7033 | } |
7033 | |
| 7034 | 7034 | /* Clear Complete callback */ |
|
| 7035 | if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) |
7035 | if (hi2c->hdmatx != NULL) |
| 7036 | { |
7036 | { |
| 7037 | /* Disable DMA Request */ |
7037 | hi2c->hdmatx->XferCpltCallback = NULL; |
| 7038 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
7038 | } |
| 7039 | 7039 | if (hi2c->hdmarx != NULL) |
|
| 7040 | hi2c->XferCount = 0U; |
7040 | { |
| 7041 | 7041 | hi2c->hdmarx->XferCpltCallback = NULL; |
|
| 7042 | if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) |
7042 | } |
| 7043 | { |
7043 | |
| 7044 | /* Set state at HAL_I2C_STATE_LISTEN */ |
7044 | if ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_TX) == (uint32_t)HAL_I2C_STATE_BUSY_TX) || ((((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_BUSY_RX) == (uint32_t)HAL_I2C_STATE_BUSY_RX) && (CurrentMode == HAL_I2C_MODE_SLAVE))) |
| 7045 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
7045 | { |
| 7046 | hi2c->State = HAL_I2C_STATE_LISTEN; |
7046 | /* Disable DMA Request */ |
| 7047 | 7047 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
|
| 7048 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
7048 | |
| 7049 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
7049 | hi2c->XferCount = 0U; |
| 7050 | hi2c->SlaveTxCpltCallback(hi2c); |
7050 | |
| 7051 | #else |
7051 | if (CurrentState == HAL_I2C_STATE_BUSY_TX_LISTEN) |
| 7052 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
7052 | { |
| 7053 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
7053 | /* Set state at HAL_I2C_STATE_LISTEN */ |
| 7054 | } |
7054 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; |
| 7055 | else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) |
7055 | hi2c->State = HAL_I2C_STATE_LISTEN; |
| 7056 | { |
7056 | |
| 7057 | /* Set state at HAL_I2C_STATE_LISTEN */ |
7057 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
| 7058 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; |
7058 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 7059 | hi2c->State = HAL_I2C_STATE_LISTEN; |
7059 | hi2c->SlaveTxCpltCallback(hi2c); |
| 7060 | 7060 | #else |
|
| 7061 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
7061 | HAL_I2C_SlaveTxCpltCallback(hi2c); |
| 7062 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
7062 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 7063 | hi2c->SlaveRxCpltCallback(hi2c); |
7063 | } |
| 7064 | #else |
7064 | else if (CurrentState == HAL_I2C_STATE_BUSY_RX_LISTEN) |
| 7065 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
7065 | { |
| 7066 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
7066 | /* Set state at HAL_I2C_STATE_LISTEN */ |
| 7067 | } |
7067 | hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; |
| 7068 | else |
7068 | hi2c->State = HAL_I2C_STATE_LISTEN; |
| 7069 | { |
7069 | |
| 7070 | /* Do nothing */ |
7070 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
| 7071 | } |
7071 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 7072 | 7072 | hi2c->SlaveRxCpltCallback(hi2c); |
|
| 7073 | /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */ |
7073 | #else |
| 7074 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
7074 | HAL_I2C_SlaveRxCpltCallback(hi2c); |
| 7075 | } |
7075 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 7076 | /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */ |
7076 | } |
| 7077 | else if (hi2c->Mode != HAL_I2C_MODE_NONE) |
7077 | else |
| 7078 | { |
7078 | { |
| 7079 | if (hi2c->XferCount == (uint16_t)1) |
7079 | /* Do nothing */ |
| 7080 | { |
7080 | } |
| 7081 | /* Disable Acknowledge */ |
7081 | |
| 7082 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
7082 | /* Enable EVT and ERR interrupt to treat end of transfer in IRQ handler */ |
| 7083 | } |
7083 | __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 7084 | 7084 | } |
|
| 7085 | /* Disable EVT and ERR interrupt */ |
7085 | /* Check current Mode, in case of treatment DMA handler have been preempted by a prior interrupt */ |
| 7086 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
7086 | else if (hi2c->Mode != HAL_I2C_MODE_NONE) |
| 7087 | 7087 | { |
|
| 7088 | /* Prepare next transfer or stop current transfer */ |
7088 | if (hi2c->XferCount == (uint16_t)1) |
| 7089 | if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) |
7089 | { |
| 7090 | { |
7090 | /* Disable Acknowledge */ |
| 7091 | /* Generate Stop */ |
7091 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 7092 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
7092 | } |
| 7093 | } |
7093 | |
| 7094 | 7094 | /* Disable EVT and ERR interrupt */ |
|
| 7095 | /* Disable Last DMA */ |
7095 | __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR); |
| 7096 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
7096 | |
| 7097 | 7097 | /* Prepare next transfer or stop current transfer */ |
|
| 7098 | /* Disable DMA Request */ |
7098 | if ((CurrentXferOptions == I2C_NO_OPTION_FRAME) || (CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_OTHER_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME)) |
| 7099 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
7099 | { |
| 7100 | 7100 | /* Generate Stop */ |
|
| 7101 | hi2c->XferCount = 0U; |
7101 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
| 7102 | 7102 | } |
|
| 7103 | /* Check if Errors has been detected during transfer */ |
7103 | |
| 7104 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
7104 | /* Disable Last DMA */ |
| 7105 | { |
7105 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST); |
| 7106 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
7106 | |
| 7107 | hi2c->ErrorCallback(hi2c); |
7107 | /* Disable DMA Request */ |
| 7108 | #else |
7108 | CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN); |
| 7109 | HAL_I2C_ErrorCallback(hi2c); |
7109 | |
| 7110 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
7110 | hi2c->XferCount = 0U; |
| 7111 | } |
7111 | |
| 7112 | else |
7112 | /* Check if Errors has been detected during transfer */ |
| 7113 | { |
7113 | if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) |
| 7114 | hi2c->State = HAL_I2C_STATE_READY; |
7114 | { |
| 7115 | 7115 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
|
| 7116 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
7116 | hi2c->ErrorCallback(hi2c); |
| 7117 | { |
7117 | #else |
| 7118 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7118 | HAL_I2C_ErrorCallback(hi2c); |
| 7119 | hi2c->PreviousState = I2C_STATE_NONE; |
7119 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 7120 | 7120 | } |
|
| 7121 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
7121 | else |
| 7122 | hi2c->MemRxCpltCallback(hi2c); |
7122 | { |
| 7123 | #else |
7123 | hi2c->State = HAL_I2C_STATE_READY; |
| 7124 | HAL_I2C_MemRxCpltCallback(hi2c); |
7124 | |
| 7125 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
7125 | if (hi2c->Mode == HAL_I2C_MODE_MEM) |
| 7126 | } |
7126 | { |
| 7127 | else |
7127 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7128 | { |
7128 | hi2c->PreviousState = I2C_STATE_NONE; |
| 7129 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7129 | |
| 7130 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
7130 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 7131 | 7131 | hi2c->MemRxCpltCallback(hi2c); |
|
| 7132 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
7132 | #else |
| 7133 | hi2c->MasterRxCpltCallback(hi2c); |
7133 | HAL_I2C_MemRxCpltCallback(hi2c); |
| 7134 | #else |
7134 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 7135 | HAL_I2C_MasterRxCpltCallback(hi2c); |
7135 | } |
| 7136 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
7136 | else |
| 7137 | } |
7137 | { |
| 7138 | } |
7138 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7139 | } |
7139 | hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; |
| 7140 | else |
7140 | |
| 7141 | { |
7141 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 7142 | /* Do nothing */ |
7142 | hi2c->MasterRxCpltCallback(hi2c); |
| 7143 | } |
7143 | #else |
| 7144 | } |
7144 | HAL_I2C_MasterRxCpltCallback(hi2c); |
| 7145 | 7145 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
|
| 7146 | /** |
7146 | } |
| 7147 | * @brief DMA I2C communication error callback. |
7147 | } |
| 7148 | * @param hdma DMA handle |
7148 | } |
| 7149 | * @retval None |
7149 | else |
| 7150 | */ |
7150 | { |
| 7151 | static void I2C_DMAError(DMA_HandleTypeDef *hdma) |
7151 | /* Do nothing */ |
| 7152 | { |
7152 | } |
| 7153 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
7153 | } |
| 7154 | 7154 | ||
| 7155 | /* Clear Complete callback */ |
7155 | /** |
| 7156 | if (hi2c->hdmatx != NULL) |
7156 | * @brief DMA I2C communication error callback. |
| 7157 | { |
7157 | * @param hdma DMA handle |
| 7158 | hi2c->hdmatx->XferCpltCallback = NULL; |
7158 | * @retval None |
| 7159 | } |
7159 | */ |
| 7160 | if (hi2c->hdmarx != NULL) |
7160 | static void I2C_DMAError(DMA_HandleTypeDef *hdma) |
| 7161 | { |
7161 | { |
| 7162 | hi2c->hdmarx->XferCpltCallback = NULL; |
7162 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
| 7163 | } |
7163 | |
| 7164 | 7164 | /* Clear Complete callback */ |
|
| 7165 | /* Disable Acknowledge */ |
7165 | if (hi2c->hdmatx != NULL) |
| 7166 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
7166 | { |
| 7167 | 7167 | hi2c->hdmatx->XferCpltCallback = NULL; |
|
| 7168 | hi2c->XferCount = 0U; |
7168 | } |
| 7169 | hi2c->State = HAL_I2C_STATE_READY; |
7169 | if (hi2c->hdmarx != NULL) |
| 7170 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7170 | { |
| 7171 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
7171 | hi2c->hdmarx->XferCpltCallback = NULL; |
| 7172 | 7172 | } |
|
| 7173 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
7173 | |
| 7174 | hi2c->ErrorCallback(hi2c); |
7174 | /* Disable Acknowledge */ |
| 7175 | #else |
7175 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 7176 | HAL_I2C_ErrorCallback(hi2c); |
7176 | |
| 7177 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
7177 | hi2c->XferCount = 0U; |
| 7178 | } |
7178 | hi2c->State = HAL_I2C_STATE_READY; |
| 7179 | 7179 | hi2c->Mode = HAL_I2C_MODE_NONE; |
|
| 7180 | /** |
7180 | hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; |
| 7181 | * @brief DMA I2C communication abort callback |
7181 | |
| 7182 | * (To be called at end of DMA Abort procedure). |
7182 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 7183 | * @param hdma DMA handle. |
7183 | hi2c->ErrorCallback(hi2c); |
| 7184 | * @retval None |
7184 | #else |
| 7185 | */ |
7185 | HAL_I2C_ErrorCallback(hi2c); |
| 7186 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) |
7186 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 7187 | { |
7187 | } |
| 7188 | __IO uint32_t count = 0U; |
7188 | |
| 7189 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
7189 | /** |
| 7190 | 7190 | * @brief DMA I2C communication abort callback |
|
| 7191 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
7191 | * (To be called at end of DMA Abort procedure). |
| 7192 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
7192 | * @param hdma DMA handle. |
| 7193 | 7193 | * @retval None |
|
| 7194 | /* During abort treatment, check that there is no pending STOP request */ |
7194 | */ |
| 7195 | /* Wait until STOP flag is reset */ |
7195 | static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) |
| 7196 | count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); |
7196 | { |
| 7197 | do |
7197 | __IO uint32_t count = 0U; |
| 7198 | { |
7198 | I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-11.5 */ |
| 7199 | if (count == 0U) |
7199 | |
| 7200 | { |
7200 | /* Declaration of temporary variable to prevent undefined behavior of volatile usage */ |
| 7201 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
7201 | HAL_I2C_StateTypeDef CurrentState = hi2c->State; |
| 7202 | break; |
7202 | |
| 7203 | } |
7203 | /* During abort treatment, check that there is no pending STOP request */ |
| 7204 | count--; |
7204 | /* Wait until STOP flag is reset */ |
| 7205 | } |
7205 | count = I2C_TIMEOUT_FLAG * (SystemCoreClock / 25U / 1000U); |
| 7206 | while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); |
7206 | do |
| 7207 | 7207 | { |
|
| 7208 | /* Clear Complete callback */ |
7208 | if (count == 0U) |
| 7209 | if (hi2c->hdmatx != NULL) |
7209 | { |
| 7210 | { |
7210 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 7211 | hi2c->hdmatx->XferCpltCallback = NULL; |
7211 | break; |
| 7212 | } |
7212 | } |
| 7213 | if (hi2c->hdmarx != NULL) |
7213 | count--; |
| 7214 | { |
7214 | } |
| 7215 | hi2c->hdmarx->XferCpltCallback = NULL; |
7215 | while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); |
| 7216 | } |
7216 | |
| 7217 | 7217 | /* Clear Complete callback */ |
|
| 7218 | /* Disable Acknowledge */ |
7218 | if (hi2c->hdmatx != NULL) |
| 7219 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
7219 | { |
| 7220 | 7220 | hi2c->hdmatx->XferCpltCallback = NULL; |
|
| 7221 | hi2c->XferCount = 0U; |
7221 | } |
| 7222 | 7222 | if (hi2c->hdmarx != NULL) |
|
| 7223 | /* Reset XferAbortCallback */ |
7223 | { |
| 7224 | if (hi2c->hdmatx != NULL) |
7224 | hi2c->hdmarx->XferCpltCallback = NULL; |
| 7225 | { |
7225 | } |
| 7226 | hi2c->hdmatx->XferAbortCallback = NULL; |
7226 | |
| 7227 | } |
7227 | /* Disable Acknowledge */ |
| 7228 | if (hi2c->hdmarx != NULL) |
7228 | CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 7229 | { |
7229 | |
| 7230 | hi2c->hdmarx->XferAbortCallback = NULL; |
7230 | hi2c->XferCount = 0U; |
| 7231 | } |
7231 | |
| 7232 | 7232 | /* Reset XferAbortCallback */ |
|
| 7233 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
7233 | if (hi2c->hdmatx != NULL) |
| 7234 | __HAL_I2C_DISABLE(hi2c); |
7234 | { |
| 7235 | 7235 | hi2c->hdmatx->XferAbortCallback = NULL; |
|
| 7236 | /* Check if come from abort from user */ |
7236 | } |
| 7237 | if (hi2c->State == HAL_I2C_STATE_ABORT) |
7237 | if (hi2c->hdmarx != NULL) |
| 7238 | { |
7238 | { |
| 7239 | hi2c->State = HAL_I2C_STATE_READY; |
7239 | hi2c->hdmarx->XferAbortCallback = NULL; |
| 7240 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7240 | } |
| 7241 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
7241 | |
| 7242 | 7242 | /* Disable I2C peripheral to prevent dummy data in buffer */ |
|
| 7243 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
7243 | __HAL_I2C_DISABLE(hi2c); |
| 7244 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
7244 | |
| 7245 | hi2c->AbortCpltCallback(hi2c); |
7245 | /* Check if come from abort from user */ |
| 7246 | #else |
7246 | if (hi2c->State == HAL_I2C_STATE_ABORT) |
| 7247 | HAL_I2C_AbortCpltCallback(hi2c); |
7247 | { |
| 7248 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
7248 | hi2c->State = HAL_I2C_STATE_READY; |
| 7249 | } |
7249 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7250 | else |
7250 | hi2c->ErrorCode = HAL_I2C_ERROR_NONE; |
| 7251 | { |
7251 | |
| 7252 | if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
7252 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
| 7253 | { |
7253 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 7254 | /* Renable I2C peripheral */ |
7254 | hi2c->AbortCpltCallback(hi2c); |
| 7255 | __HAL_I2C_ENABLE(hi2c); |
7255 | #else |
| 7256 | 7256 | HAL_I2C_AbortCpltCallback(hi2c); |
|
| 7257 | /* Enable Acknowledge */ |
7257 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 7258 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
7258 | } |
| 7259 | 7259 | else |
|
| 7260 | /* keep HAL_I2C_STATE_LISTEN */ |
7260 | { |
| 7261 | hi2c->PreviousState = I2C_STATE_NONE; |
7261 | if (((uint32_t)CurrentState & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) |
| 7262 | hi2c->State = HAL_I2C_STATE_LISTEN; |
7262 | { |
| 7263 | } |
7263 | /* Renable I2C peripheral */ |
| 7264 | else |
7264 | __HAL_I2C_ENABLE(hi2c); |
| 7265 | { |
7265 | |
| 7266 | hi2c->State = HAL_I2C_STATE_READY; |
7266 | /* Enable Acknowledge */ |
| 7267 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7267 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK); |
| 7268 | } |
7268 | |
| 7269 | 7269 | /* keep HAL_I2C_STATE_LISTEN */ |
|
| 7270 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
7270 | hi2c->PreviousState = I2C_STATE_NONE; |
| 7271 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
7271 | hi2c->State = HAL_I2C_STATE_LISTEN; |
| 7272 | hi2c->ErrorCallback(hi2c); |
7272 | } |
| 7273 | #else |
7273 | else |
| 7274 | HAL_I2C_ErrorCallback(hi2c); |
7274 | { |
| 7275 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
7275 | hi2c->State = HAL_I2C_STATE_READY; |
| 7276 | } |
7276 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7277 | } |
7277 | } |
| 7278 | 7278 | ||
| 7279 | /** |
7279 | /* Call the corresponding callback to inform upper layer of End of Transfer */ |
| 7280 | * @brief This function handles I2C Communication Timeout. |
7280 | #if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) |
| 7281 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
7281 | hi2c->ErrorCallback(hi2c); |
| 7282 | * the configuration information for I2C module |
7282 | #else |
| 7283 | * @param Flag specifies the I2C flag to check. |
7283 | HAL_I2C_ErrorCallback(hi2c); |
| 7284 | * @param Status The new Flag status (SET or RESET). |
7284 | #endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ |
| 7285 | * @param Timeout Timeout duration |
7285 | } |
| 7286 | * @param Tickstart Tick start value |
7286 | } |
| 7287 | * @retval HAL status |
7287 | |
| 7288 | */ |
7288 | /** |
| 7289 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) |
7289 | * @brief This function handles I2C Communication Timeout. |
| 7290 | { |
7290 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 7291 | /* Wait until flag is set */ |
7291 | * the configuration information for I2C module |
| 7292 | while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) |
7292 | * @param Flag specifies the I2C flag to check. |
| 7293 | { |
7293 | * @param Status The new Flag status (SET or RESET). |
| 7294 | /* Check for the Timeout */ |
7294 | * @param Timeout Timeout duration |
| 7295 | if (Timeout != HAL_MAX_DELAY) |
7295 | * @param Tickstart Tick start value |
| 7296 | { |
7296 | * @retval HAL status |
| 7297 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
7297 | */ |
| 7298 | { |
7298 | static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart) |
| 7299 | hi2c->PreviousState = I2C_STATE_NONE; |
7299 | { |
| 7300 | hi2c->State = HAL_I2C_STATE_READY; |
7300 | /* Wait until flag is set */ |
| 7301 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7301 | while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) |
| 7302 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
7302 | { |
| 7303 | 7303 | /* Check for the Timeout */ |
|
| 7304 | /* Process Unlocked */ |
7304 | if (Timeout != HAL_MAX_DELAY) |
| 7305 | __HAL_UNLOCK(hi2c); |
7305 | { |
| 7306 | 7306 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
|
| 7307 | return HAL_ERROR; |
7307 | { |
| 7308 | } |
7308 | if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) |
| 7309 | } |
7309 | { |
| 7310 | } |
7310 | hi2c->PreviousState = I2C_STATE_NONE; |
| 7311 | return HAL_OK; |
7311 | hi2c->State = HAL_I2C_STATE_READY; |
| 7312 | } |
7312 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7313 | 7313 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
|
| 7314 | /** |
7314 | |
| 7315 | * @brief This function handles I2C Communication Timeout for Master addressing phase. |
7315 | /* Process Unlocked */ |
| 7316 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
7316 | __HAL_UNLOCK(hi2c); |
| 7317 | * the configuration information for I2C module |
7317 | |
| 7318 | * @param Flag specifies the I2C flag to check. |
7318 | return HAL_ERROR; |
| 7319 | * @param Timeout Timeout duration |
7319 | } |
| 7320 | * @param Tickstart Tick start value |
7320 | } |
| 7321 | * @retval HAL status |
7321 | } |
| 7322 | */ |
7322 | } |
| 7323 | static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) |
7323 | return HAL_OK; |
| 7324 | { |
7324 | } |
| 7325 | while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) |
7325 | |
| 7326 | { |
7326 | /** |
| 7327 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) |
7327 | * @brief This function handles I2C Communication Timeout for Master addressing phase. |
| 7328 | { |
7328 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 7329 | /* Generate Stop */ |
7329 | * the configuration information for I2C module |
| 7330 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
7330 | * @param Flag specifies the I2C flag to check. |
| 7331 | 7331 | * @param Timeout Timeout duration |
|
| 7332 | /* Clear AF Flag */ |
7332 | * @param Tickstart Tick start value |
| 7333 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
7333 | * @retval HAL status |
| 7334 | 7334 | */ |
|
| 7335 | hi2c->PreviousState = I2C_STATE_NONE; |
7335 | static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout, uint32_t Tickstart) |
| 7336 | hi2c->State = HAL_I2C_STATE_READY; |
7336 | { |
| 7337 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7337 | while (__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET) |
| 7338 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
7338 | { |
| 7339 | 7339 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) |
|
| 7340 | /* Process Unlocked */ |
7340 | { |
| 7341 | __HAL_UNLOCK(hi2c); |
7341 | /* Generate Stop */ |
| 7342 | 7342 | SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP); |
|
| 7343 | return HAL_ERROR; |
7343 | |
| 7344 | } |
7344 | /* Clear AF Flag */ |
| 7345 | 7345 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
|
| 7346 | /* Check for the Timeout */ |
7346 | |
| 7347 | if (Timeout != HAL_MAX_DELAY) |
7347 | hi2c->PreviousState = I2C_STATE_NONE; |
| 7348 | { |
7348 | hi2c->State = HAL_I2C_STATE_READY; |
| 7349 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
7349 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7350 | { |
7350 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
| 7351 | hi2c->PreviousState = I2C_STATE_NONE; |
7351 | |
| 7352 | hi2c->State = HAL_I2C_STATE_READY; |
7352 | /* Process Unlocked */ |
| 7353 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7353 | __HAL_UNLOCK(hi2c); |
| 7354 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
7354 | |
| 7355 | 7355 | return HAL_ERROR; |
|
| 7356 | /* Process Unlocked */ |
7356 | } |
| 7357 | __HAL_UNLOCK(hi2c); |
7357 | |
| 7358 | 7358 | /* Check for the Timeout */ |
|
| 7359 | return HAL_ERROR; |
7359 | if (Timeout != HAL_MAX_DELAY) |
| 7360 | } |
7360 | { |
| 7361 | } |
7361 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
| 7362 | } |
7362 | { |
| 7363 | return HAL_OK; |
7363 | if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)) |
| 7364 | } |
7364 | { |
| 7365 | 7365 | hi2c->PreviousState = I2C_STATE_NONE; |
|
| 7366 | /** |
7366 | hi2c->State = HAL_I2C_STATE_READY; |
| 7367 | * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. |
7367 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7368 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
7368 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 7369 | * the configuration information for the specified I2C. |
7369 | |
| 7370 | * @param Timeout Timeout duration |
7370 | /* Process Unlocked */ |
| 7371 | * @param Tickstart Tick start value |
7371 | __HAL_UNLOCK(hi2c); |
| 7372 | * @retval HAL status |
7372 | |
| 7373 | */ |
7373 | return HAL_ERROR; |
| 7374 | static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
7374 | } |
| 7375 | { |
7375 | } |
| 7376 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) |
7376 | } |
| 7377 | { |
7377 | } |
| 7378 | /* Check if a NACK is detected */ |
7378 | return HAL_OK; |
| 7379 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
7379 | } |
| 7380 | { |
7380 | |
| 7381 | return HAL_ERROR; |
7381 | /** |
| 7382 | } |
7382 | * @brief This function handles I2C Communication Timeout for specific usage of TXE flag. |
| 7383 | 7383 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 7384 | /* Check for the Timeout */ |
7384 | * the configuration information for the specified I2C. |
| 7385 | if (Timeout != HAL_MAX_DELAY) |
7385 | * @param Timeout Timeout duration |
| 7386 | { |
7386 | * @param Tickstart Tick start value |
| 7387 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
7387 | * @retval HAL status |
| 7388 | { |
7388 | */ |
| 7389 | hi2c->PreviousState = I2C_STATE_NONE; |
7389 | static HAL_StatusTypeDef I2C_WaitOnTXEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
| 7390 | hi2c->State = HAL_I2C_STATE_READY; |
7390 | { |
| 7391 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7391 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) |
| 7392 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
7392 | { |
| 7393 | 7393 | /* Check if a NACK is detected */ |
|
| 7394 | /* Process Unlocked */ |
7394 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
| 7395 | __HAL_UNLOCK(hi2c); |
7395 | { |
| 7396 | 7396 | return HAL_ERROR; |
|
| 7397 | return HAL_ERROR; |
7397 | } |
| 7398 | } |
7398 | |
| 7399 | } |
7399 | /* Check for the Timeout */ |
| 7400 | } |
7400 | if (Timeout != HAL_MAX_DELAY) |
| 7401 | return HAL_OK; |
7401 | { |
| 7402 | } |
7402 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
| 7403 | 7403 | { |
|
| 7404 | /** |
7404 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)) |
| 7405 | * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. |
7405 | { |
| 7406 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
7406 | hi2c->PreviousState = I2C_STATE_NONE; |
| 7407 | * the configuration information for the specified I2C. |
7407 | hi2c->State = HAL_I2C_STATE_READY; |
| 7408 | * @param Timeout Timeout duration |
7408 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7409 | * @param Tickstart Tick start value |
7409 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 7410 | * @retval HAL status |
7410 | |
| 7411 | */ |
7411 | /* Process Unlocked */ |
| 7412 | static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
7412 | __HAL_UNLOCK(hi2c); |
| 7413 | { |
7413 | |
| 7414 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) |
7414 | return HAL_ERROR; |
| 7415 | { |
7415 | } |
| 7416 | /* Check if a NACK is detected */ |
7416 | } |
| 7417 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
7417 | } |
| 7418 | { |
7418 | } |
| 7419 | return HAL_ERROR; |
7419 | return HAL_OK; |
| 7420 | } |
7420 | } |
| 7421 | 7421 | ||
| 7422 | /* Check for the Timeout */ |
7422 | /** |
| 7423 | if (Timeout != HAL_MAX_DELAY) |
7423 | * @brief This function handles I2C Communication Timeout for specific usage of BTF flag. |
| 7424 | { |
7424 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 7425 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
7425 | * the configuration information for the specified I2C. |
| 7426 | { |
7426 | * @param Timeout Timeout duration |
| 7427 | hi2c->PreviousState = I2C_STATE_NONE; |
7427 | * @param Tickstart Tick start value |
| 7428 | hi2c->State = HAL_I2C_STATE_READY; |
7428 | * @retval HAL status |
| 7429 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7429 | */ |
| 7430 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
7430 | static HAL_StatusTypeDef I2C_WaitOnBTFFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
| 7431 | 7431 | { |
|
| 7432 | /* Process Unlocked */ |
7432 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET) |
| 7433 | __HAL_UNLOCK(hi2c); |
7433 | { |
| 7434 | 7434 | /* Check if a NACK is detected */ |
|
| 7435 | return HAL_ERROR; |
7435 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
| 7436 | } |
7436 | { |
| 7437 | } |
7437 | return HAL_ERROR; |
| 7438 | } |
7438 | } |
| 7439 | return HAL_OK; |
7439 | |
| 7440 | } |
7440 | /* Check for the Timeout */ |
| 7441 | 7441 | if (Timeout != HAL_MAX_DELAY) |
|
| 7442 | /** |
7442 | { |
| 7443 | * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. |
7443 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
| 7444 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
7444 | { |
| 7445 | * the configuration information for the specified I2C. |
7445 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET)) |
| 7446 | * @param Timeout Timeout duration |
7446 | { |
| 7447 | * @param Tickstart Tick start value |
7447 | hi2c->PreviousState = I2C_STATE_NONE; |
| 7448 | * @retval HAL status |
7448 | hi2c->State = HAL_I2C_STATE_READY; |
| 7449 | */ |
7449 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7450 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
7450 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 7451 | { |
7451 | |
| 7452 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) |
7452 | /* Process Unlocked */ |
| 7453 | { |
7453 | __HAL_UNLOCK(hi2c); |
| 7454 | /* Check if a NACK is detected */ |
7454 | |
| 7455 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
7455 | return HAL_ERROR; |
| 7456 | { |
7456 | } |
| 7457 | return HAL_ERROR; |
7457 | } |
| 7458 | } |
7458 | } |
| 7459 | 7459 | } |
|
| 7460 | /* Check for the Timeout */ |
7460 | return HAL_OK; |
| 7461 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
7461 | } |
| 7462 | { |
7462 | |
| 7463 | hi2c->PreviousState = I2C_STATE_NONE; |
7463 | /** |
| 7464 | hi2c->State = HAL_I2C_STATE_READY; |
7464 | * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. |
| 7465 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7465 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 7466 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
7466 | * the configuration information for the specified I2C. |
| 7467 | 7467 | * @param Timeout Timeout duration |
|
| 7468 | /* Process Unlocked */ |
7468 | * @param Tickstart Tick start value |
| 7469 | __HAL_UNLOCK(hi2c); |
7469 | * @retval HAL status |
| 7470 | 7470 | */ |
|
| 7471 | return HAL_ERROR; |
7471 | static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
| 7472 | } |
7472 | { |
| 7473 | } |
7473 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) |
| 7474 | return HAL_OK; |
7474 | { |
| 7475 | } |
7475 | /* Check if a NACK is detected */ |
| 7476 | 7476 | if (I2C_IsAcknowledgeFailed(hi2c) != HAL_OK) |
|
| 7477 | /** |
7477 | { |
| 7478 | * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt. |
7478 | return HAL_ERROR; |
| 7479 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
7479 | } |
| 7480 | * the configuration information for the specified I2C. |
7480 | |
| 7481 | * @retval HAL status |
7481 | /* Check for the Timeout */ |
| 7482 | */ |
7482 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
| 7483 | static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c) |
7483 | { |
| 7484 | { |
7484 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) |
| 7485 | __IO uint32_t count = 0U; |
7485 | { |
| 7486 | 7486 | hi2c->PreviousState = I2C_STATE_NONE; |
|
| 7487 | /* Wait until STOP flag is reset */ |
7487 | hi2c->State = HAL_I2C_STATE_READY; |
| 7488 | count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U); |
7488 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7489 | do |
7489 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 7490 | { |
7490 | |
| 7491 | count--; |
7491 | /* Process Unlocked */ |
| 7492 | if (count == 0U) |
7492 | __HAL_UNLOCK(hi2c); |
| 7493 | { |
7493 | |
| 7494 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
7494 | return HAL_ERROR; |
| 7495 | 7495 | } |
|
| 7496 | return HAL_ERROR; |
7496 | } |
| 7497 | } |
7497 | } |
| 7498 | } |
7498 | return HAL_OK; |
| 7499 | while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); |
7499 | } |
| 7500 | 7500 | ||
| 7501 | return HAL_OK; |
7501 | /** |
| 7502 | } |
7502 | * @brief This function handles I2C Communication Timeout for specific usage of STOP request through Interrupt. |
| 7503 | 7503 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 7504 | /** |
7504 | * the configuration information for the specified I2C. |
| 7505 | * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. |
7505 | * @retval HAL status |
| 7506 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
7506 | */ |
| 7507 | * the configuration information for the specified I2C. |
7507 | static HAL_StatusTypeDef I2C_WaitOnSTOPRequestThroughIT(I2C_HandleTypeDef *hi2c) |
| 7508 | * @param Timeout Timeout duration |
7508 | { |
| 7509 | * @param Tickstart Tick start value |
7509 | __IO uint32_t count = 0U; |
| 7510 | * @retval HAL status |
7510 | |
| 7511 | */ |
7511 | /* Wait until STOP flag is reset */ |
| 7512 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
7512 | count = I2C_TIMEOUT_STOP_FLAG * (SystemCoreClock / 25U / 1000U); |
| 7513 | { |
7513 | do |
| 7514 | 7514 | { |
|
| 7515 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) |
7515 | count--; |
| 7516 | { |
7516 | if (count == 0U) |
| 7517 | /* Check if a STOPF is detected */ |
7517 | { |
| 7518 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) |
7518 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 7519 | { |
7519 | |
| 7520 | /* Clear STOP Flag */ |
7520 | return HAL_ERROR; |
| 7521 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
7521 | } |
| 7522 | 7522 | } |
|
| 7523 | hi2c->PreviousState = I2C_STATE_NONE; |
7523 | while (READ_BIT(hi2c->Instance->CR1, I2C_CR1_STOP) == I2C_CR1_STOP); |
| 7524 | hi2c->State = HAL_I2C_STATE_READY; |
7524 | |
| 7525 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7525 | return HAL_OK; |
| 7526 | hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; |
7526 | } |
| 7527 | 7527 | ||
| 7528 | /* Process Unlocked */ |
7528 | /** |
| 7529 | __HAL_UNLOCK(hi2c); |
7529 | * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. |
| 7530 | 7530 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
|
| 7531 | return HAL_ERROR; |
7531 | * the configuration information for the specified I2C. |
| 7532 | } |
7532 | * @param Timeout Timeout duration |
| 7533 | 7533 | * @param Tickstart Tick start value |
|
| 7534 | /* Check for the Timeout */ |
7534 | * @retval HAL status |
| 7535 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
7535 | */ |
| 7536 | { |
7536 | static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) |
| 7537 | hi2c->PreviousState = I2C_STATE_NONE; |
7537 | { |
| 7538 | hi2c->State = HAL_I2C_STATE_READY; |
7538 | |
| 7539 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7539 | while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) |
| 7540 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
7540 | { |
| 7541 | 7541 | /* Check if a STOPF is detected */ |
|
| 7542 | /* Process Unlocked */ |
7542 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) |
| 7543 | __HAL_UNLOCK(hi2c); |
7543 | { |
| 7544 | 7544 | /* Clear STOP Flag */ |
|
| 7545 | return HAL_ERROR; |
7545 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); |
| 7546 | } |
7546 | |
| 7547 | } |
7547 | hi2c->PreviousState = I2C_STATE_NONE; |
| 7548 | return HAL_OK; |
7548 | hi2c->State = HAL_I2C_STATE_READY; |
| 7549 | } |
7549 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7550 | 7550 | hi2c->ErrorCode |= HAL_I2C_ERROR_NONE; |
|
| 7551 | /** |
7551 | |
| 7552 | * @brief This function handles Acknowledge failed detection during an I2C Communication. |
7552 | /* Process Unlocked */ |
| 7553 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
7553 | __HAL_UNLOCK(hi2c); |
| 7554 | * the configuration information for the specified I2C. |
7554 | |
| 7555 | * @retval HAL status |
7555 | return HAL_ERROR; |
| 7556 | */ |
7556 | } |
| 7557 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) |
7557 | |
| 7558 | { |
7558 | /* Check for the Timeout */ |
| 7559 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) |
7559 | if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) |
| 7560 | { |
7560 | { |
| 7561 | /* Clear NACKF Flag */ |
7561 | if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) |
| 7562 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
7562 | { |
| 7563 | 7563 | hi2c->PreviousState = I2C_STATE_NONE; |
|
| 7564 | hi2c->PreviousState = I2C_STATE_NONE; |
7564 | hi2c->State = HAL_I2C_STATE_READY; |
| 7565 | hi2c->State = HAL_I2C_STATE_READY; |
7565 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7566 | hi2c->Mode = HAL_I2C_MODE_NONE; |
7566 | hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; |
| 7567 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
7567 | |
| 7568 | 7568 | /* Process Unlocked */ |
|
| 7569 | /* Process Unlocked */ |
7569 | __HAL_UNLOCK(hi2c); |
| 7570 | __HAL_UNLOCK(hi2c); |
7570 | |
| 7571 | 7571 | return HAL_ERROR; |
|
| 7572 | return HAL_ERROR; |
7572 | } |
| 7573 | } |
7573 | } |
| 7574 | return HAL_OK; |
7574 | } |
| 7575 | } |
7575 | return HAL_OK; |
| 7576 | 7576 | } |
|
| 7577 | /** |
7577 | |
| 7578 | * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. |
7578 | /** |
| 7579 | * @param hi2c I2C handle. |
7579 | * @brief This function handles Acknowledge failed detection during an I2C Communication. |
| 7580 | * @retval None |
7580 | * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains |
| 7581 | */ |
7581 | * the configuration information for the specified I2C. |
| 7582 | static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) |
7582 | * @retval HAL status |
| 7583 | { |
7583 | */ |
| 7584 | /* if user set XferOptions to I2C_OTHER_FRAME */ |
7584 | static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c) |
| 7585 | /* it request implicitly to generate a restart condition */ |
7585 | { |
| 7586 | /* set XferOptions to I2C_FIRST_FRAME */ |
7586 | if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) |
| 7587 | if (hi2c->XferOptions == I2C_OTHER_FRAME) |
7587 | { |
| 7588 | { |
7588 | /* Clear NACKF Flag */ |
| 7589 | hi2c->XferOptions = I2C_FIRST_FRAME; |
7589 | __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); |
| 7590 | } |
7590 | |
| 7591 | /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ |
7591 | hi2c->PreviousState = I2C_STATE_NONE; |
| 7592 | /* it request implicitly to generate a restart condition */ |
7592 | hi2c->State = HAL_I2C_STATE_READY; |
| 7593 | /* then generate a stop condition at the end of transfer */ |
7593 | hi2c->Mode = HAL_I2C_MODE_NONE; |
| 7594 | /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ |
7594 | hi2c->ErrorCode |= HAL_I2C_ERROR_AF; |
| 7595 | else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) |
7595 | |
| 7596 | { |
7596 | /* Process Unlocked */ |
| 7597 | hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; |
7597 | __HAL_UNLOCK(hi2c); |
| 7598 | } |
7598 | |
| 7599 | else |
7599 | return HAL_ERROR; |
| 7600 | { |
7600 | } |
| 7601 | /* Nothing to do */ |
7601 | return HAL_OK; |
| 7602 | } |
7602 | } |
| 7603 | } |
7603 | |
| 7604 | 7604 | /** |
|
| 7605 | /** |
7605 | * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. |
| 7606 | * @} |
7606 | * @param hi2c I2C handle. |
| 7607 | */ |
7607 | * @retval None |
| 7608 | 7608 | */ |
|
| 7609 | #endif /* HAL_I2C_MODULE_ENABLED */ |
7609 | static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) |
| 7610 | /** |
7610 | { |
| 7611 | * @} |
7611 | /* if user set XferOptions to I2C_OTHER_FRAME */ |
| 7612 | */ |
7612 | /* it request implicitly to generate a restart condition */ |
| 7613 | 7613 | /* set XferOptions to I2C_FIRST_FRAME */ |
|
| 7614 | /** |
7614 | if (hi2c->XferOptions == I2C_OTHER_FRAME) |
| 7615 | * @} |
7615 | { |
| 7616 | */ |
7616 | hi2c->XferOptions = I2C_FIRST_FRAME; |
| 7617 | 7617 | } |
|
| 7618 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
7618 | /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ |
| - | 7619 | /* it request implicitly to generate a restart condition */ |
|
| - | 7620 | /* then generate a stop condition at the end of transfer */ |
|
| - | 7621 | /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ |
|
| - | 7622 | else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) |
|
| - | 7623 | { |
|
| - | 7624 | hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; |
|
| - | 7625 | } |
|
| - | 7626 | else |
|
| - | 7627 | { |
|
| - | 7628 | /* Nothing to do */ |
|
| - | 7629 | } |
|
| - | 7630 | } |
|
| - | 7631 | ||
| - | 7632 | /** |
|
| - | 7633 | * @} |
|
| - | 7634 | */ |
|
| - | 7635 | ||
| - | 7636 | #endif /* HAL_I2C_MODULE_ENABLED */ |
|
| - | 7637 | /** |
|
| - | 7638 | * @} |
|
| - | 7639 | */ |
|
| - | 7640 | ||
| - | 7641 | /** |
|
| - | 7642 | * @} |
|
| - | 7643 | */ |
|
| - | 7644 | ||