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Line 68... Line 68...
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  @endverbatim
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  @endverbatim
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  ******************************************************************************
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  ******************************************************************************
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  * @attention
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  * @attention
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  *
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  *
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  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
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  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
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  * All rights reserved.</center></h2>
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  *
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  *
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  * Redistribution and use in source and binary forms, with or without modification,
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  * This software component is licensed by ST under BSD 3-Clause license,
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  * are permitted provided that the following conditions are met:
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  * the "License"; You may not use this file except in compliance with the
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  *   1. Redistributions of source code must retain the above copyright notice,
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  *      this list of conditions and the following disclaimer.
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  *   2. Redistributions in binary form must reproduce the above copyright notice,
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  *      this list of conditions and the following disclaimer in the documentation
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  *      and/or other materials provided with the distribution.
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  * License. You may obtain a copy of the License at:
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  *   3. Neither the name of STMicroelectronics nor the names of its contributors
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  *      may be used to endorse or promote products derived from this software
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  *                        opensource.org/licenses/BSD-3-Clause
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  *      without specific prior written permission.
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  *
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  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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  *
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  *
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  ******************************************************************************
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  ******************************************************************************
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  */
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  */
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/* Includes ------------------------------------------------------------------*/
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/* Includes ------------------------------------------------------------------*/
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  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
158
  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
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  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
159
  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
176
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
160
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
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  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
161
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
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162
 
179
#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
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#if defined (DMA2)
180
  /* calculation of the channel index */
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  /* calculation of the channel index */
181
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
165
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
182
  {
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  {
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    /* DMA1 */
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    /* DMA1 */
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    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
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    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
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  }
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  }
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#else
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#else
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  /* DMA1 */
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  /* DMA1 */
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  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
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  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
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  hdma->DmaBaseAddress = DMA1;
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  hdma->DmaBaseAddress = DMA1;
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#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
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#endif /* DMA2 */
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  /* Change DMA peripheral state */
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  /* Change DMA peripheral state */
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  hdma->State = HAL_DMA_STATE_BUSY;
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  hdma->State = HAL_DMA_STATE_BUSY;
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  /* Get the CR register value */
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  /* Get the CR register value */
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  hdma->Instance->CPAR  = 0U;
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  hdma->Instance->CPAR  = 0U;
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259
  /* Reset DMA Channel memory address register */
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  /* Reset DMA Channel memory address register */
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  hdma->Instance->CMAR = 0U;
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  hdma->Instance->CMAR = 0U;
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#if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC)
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#if defined (DMA2)
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  /* calculation of the channel index */
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  /* calculation of the channel index */
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  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
248
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
265
  {
249
  {
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    /* DMA1 */
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    /* DMA1 */
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    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
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    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
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  }
259
  }
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#else
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#else
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  /* DMA1 */
261
  /* DMA1 */
278
  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
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  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
279
  hdma->DmaBaseAddress = DMA1;
263
  hdma->DmaBaseAddress = DMA1;
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#endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */
264
#endif /* DMA2 */
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265
 
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  /* Clear all flags */
266
  /* Clear all flags */
283
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
267
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex));
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  /* Clean all callbacks */
269
  /* Clean all callbacks */
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  * @retval HAL status
414
  * @retval HAL status
431
  */
415
  */
432
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
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HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
433
{
417
{
434
  HAL_StatusTypeDef status = HAL_OK;
418
  HAL_StatusTypeDef status = HAL_OK;
435
 
419
 
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420
  if(hdma->State != HAL_DMA_STATE_BUSY)
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  {
436
  /* Disable DMA IT */
422
    /* no transfer ongoing */
437
  __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
423
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
438
   
424
   
439
  /* Disable the channel */
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    /* Process Unlocked */
440
  __HAL_DMA_DISABLE(hdma);
426
    __HAL_UNLOCK(hdma);
441
   
427
   
442
  /* Clear all flags */
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    return HAL_ERROR;
443
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
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429
  }
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430
  else
444
 
431
 
-
 
432
  {
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433
    /* Disable DMA IT */
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434
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
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435
     
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436
    /* Disable the channel */
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437
    __HAL_DMA_DISABLE(hdma);
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438
     
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439
    /* Clear all flags */
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440
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex);
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441
  }
445
  /* Change the DMA state */
442
  /* Change the DMA state */
446
  hdma->State = HAL_DMA_STATE_READY;
443
  hdma->State = HAL_DMA_STATE_READY;
447
 
444
 
448
  /* Process Unlocked */
445
  /* Process Unlocked */
449
  __HAL_UNLOCK(hdma);      
446
  __HAL_UNLOCK(hdma);