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| 68 | 68 | ||
| 69 | @endverbatim |
69 | @endverbatim |
| 70 | ****************************************************************************** |
70 | ****************************************************************************** |
| 71 | * @attention |
71 | * @attention |
| 72 | * |
72 | * |
| 73 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
73 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
| - | 74 | * All rights reserved.</center></h2> |
|
| 74 | * |
75 | * |
| 75 | * Redistribution and use in source and binary forms, with or without modification, |
76 | * This software component is licensed by ST under BSD 3-Clause license, |
| 76 | * are permitted provided that the following conditions are met: |
77 | * the "License"; You may not use this file except in compliance with the |
| 77 | * 1. Redistributions of source code must retain the above copyright notice, |
- | |
| 78 | * this list of conditions and the following disclaimer. |
- | |
| 79 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
- | |
| 80 | * this list of conditions and the following disclaimer in the documentation |
- | |
| 81 | * and/or other materials provided with the distribution. |
78 | * License. You may obtain a copy of the License at: |
| 82 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
- | |
| 83 | * may be used to endorse or promote products derived from this software |
79 | * opensource.org/licenses/BSD-3-Clause |
| 84 | * without specific prior written permission. |
- | |
| 85 | * |
- | |
| 86 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
- | |
| 87 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
- | |
| 88 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
- | |
| 89 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
- | |
| 90 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
- | |
| 91 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
- | |
| 92 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
- | |
| 93 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
- | |
| 94 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
- | |
| 95 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
- | |
| 96 | * |
80 | * |
| 97 | ****************************************************************************** |
81 | ****************************************************************************** |
| 98 | */ |
82 | */ |
| 99 | 83 | ||
| 100 | /* Includes ------------------------------------------------------------------*/ |
84 | /* Includes ------------------------------------------------------------------*/ |
| Line 174... | Line 158... | ||
| 174 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); |
158 | assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); |
| 175 | assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); |
159 | assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); |
| 176 | assert_param(IS_DMA_MODE(hdma->Init.Mode)); |
160 | assert_param(IS_DMA_MODE(hdma->Init.Mode)); |
| 177 | assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); |
161 | assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); |
| 178 | 162 | ||
| 179 | #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC) |
- | |
| - | 163 | #if defined (DMA2) |
|
| 180 | /* calculation of the channel index */ |
164 | /* calculation of the channel index */ |
| 181 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
165 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
| 182 | { |
166 | { |
| 183 | /* DMA1 */ |
167 | /* DMA1 */ |
| 184 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
168 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
| Line 192... | Line 176... | ||
| 192 | } |
176 | } |
| 193 | #else |
177 | #else |
| 194 | /* DMA1 */ |
178 | /* DMA1 */ |
| 195 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
179 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
| 196 | hdma->DmaBaseAddress = DMA1; |
180 | hdma->DmaBaseAddress = DMA1; |
| 197 | #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */ |
181 | #endif /* DMA2 */ |
| 198 | 182 | ||
| 199 | /* Change DMA peripheral state */ |
183 | /* Change DMA peripheral state */ |
| 200 | hdma->State = HAL_DMA_STATE_BUSY; |
184 | hdma->State = HAL_DMA_STATE_BUSY; |
| 201 | 185 | ||
| 202 | /* Get the CR register value */ |
186 | /* Get the CR register value */ |
| Line 257... | Line 241... | ||
| 257 | hdma->Instance->CPAR = 0U; |
241 | hdma->Instance->CPAR = 0U; |
| 258 | 242 | ||
| 259 | /* Reset DMA Channel memory address register */ |
243 | /* Reset DMA Channel memory address register */ |
| 260 | hdma->Instance->CMAR = 0U; |
244 | hdma->Instance->CMAR = 0U; |
| 261 | 245 | ||
| 262 | #if defined (STM32F101xE) || defined (STM32F101xG) || defined (STM32F103xE) || defined (STM32F103xG) || defined (STM32F100xE) || defined (STM32F105xC) || defined (STM32F107xC) |
- | |
| - | 246 | #if defined (DMA2) |
|
| 263 | /* calculation of the channel index */ |
247 | /* calculation of the channel index */ |
| 264 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
248 | if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) |
| 265 | { |
249 | { |
| 266 | /* DMA1 */ |
250 | /* DMA1 */ |
| 267 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
251 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
| Line 275... | Line 259... | ||
| 275 | } |
259 | } |
| 276 | #else |
260 | #else |
| 277 | /* DMA1 */ |
261 | /* DMA1 */ |
| 278 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
262 | hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; |
| 279 | hdma->DmaBaseAddress = DMA1; |
263 | hdma->DmaBaseAddress = DMA1; |
| 280 | #endif /* STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG || STM32F100xE || STM32F105xC || STM32F107xC */ |
264 | #endif /* DMA2 */ |
| 281 | 265 | ||
| 282 | /* Clear all flags */ |
266 | /* Clear all flags */ |
| 283 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); |
267 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex)); |
| 284 | 268 | ||
| 285 | /* Clean all callbacks */ |
269 | /* Clean all callbacks */ |
| Line 430... | Line 414... | ||
| 430 | * @retval HAL status |
414 | * @retval HAL status |
| 431 | */ |
415 | */ |
| 432 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) |
416 | HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) |
| 433 | { |
417 | { |
| 434 | HAL_StatusTypeDef status = HAL_OK; |
418 | HAL_StatusTypeDef status = HAL_OK; |
| 435 | 419 | ||
| - | 420 | if(hdma->State != HAL_DMA_STATE_BUSY) |
|
| - | 421 | { |
|
| 436 | /* Disable DMA IT */ |
422 | /* no transfer ongoing */ |
| 437 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
423 | hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; |
| 438 | 424 | ||
| 439 | /* Disable the channel */ |
425 | /* Process Unlocked */ |
| 440 | __HAL_DMA_DISABLE(hdma); |
426 | __HAL_UNLOCK(hdma); |
| 441 | 427 | ||
| 442 | /* Clear all flags */ |
428 | return HAL_ERROR; |
| 443 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
- | |
| - | 429 | } |
|
| - | 430 | else |
|
| 444 | 431 | ||
| - | 432 | { |
|
| - | 433 | /* Disable DMA IT */ |
|
| - | 434 | __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); |
|
| - | 435 | ||
| - | 436 | /* Disable the channel */ |
|
| - | 437 | __HAL_DMA_DISABLE(hdma); |
|
| - | 438 | ||
| - | 439 | /* Clear all flags */ |
|
| - | 440 | hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << hdma->ChannelIndex); |
|
| - | 441 | } |
|
| 445 | /* Change the DMA state */ |
442 | /* Change the DMA state */ |
| 446 | hdma->State = HAL_DMA_STATE_READY; |
443 | hdma->State = HAL_DMA_STATE_READY; |
| 447 | 444 | ||
| 448 | /* Process Unlocked */ |
445 | /* Process Unlocked */ |
| 449 | __HAL_UNLOCK(hdma); |
446 | __HAL_UNLOCK(hdma); |