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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_ll_tim.h |
3 | * @file stm32f1xx_ll_tim.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of TIM LL module. |
5 | * @brief Header file of TIM LL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef __STM32F1xx_LL_TIM_H |
| 21 | #ifndef __STM32F1xx_LL_TIM_H |
21 | #define __STM32F1xx_LL_TIM_H |
| 22 | #define __STM32F1xx_LL_TIM_H |
22 | |
| 23 | 23 | #ifdef __cplusplus |
|
| 24 | #ifdef __cplusplus |
24 | extern "C" { |
| 25 | extern "C" { |
25 | #endif |
| 26 | #endif |
26 | |
| 27 | 27 | /* Includes ------------------------------------------------------------------*/ |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | #include "stm32f1xx.h" |
| 29 | #include "stm32f1xx.h" |
29 | |
| 30 | 30 | /** @addtogroup STM32F1xx_LL_Driver |
|
| 31 | /** @addtogroup STM32F1xx_LL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) |
|
| 35 | #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) |
35 | |
| 36 | 36 | /** @defgroup TIM_LL TIM |
|
| 37 | /** @defgroup TIM_LL TIM |
37 | * @{ |
| 38 | * @{ |
38 | */ |
| 39 | */ |
39 | |
| 40 | 40 | /* Private types -------------------------------------------------------------*/ |
|
| 41 | /* Private types -------------------------------------------------------------*/ |
41 | /* Private variables ---------------------------------------------------------*/ |
| 42 | /* Private variables ---------------------------------------------------------*/ |
42 | /** @defgroup TIM_LL_Private_Variables TIM Private Variables |
| 43 | /** @defgroup TIM_LL_Private_Variables TIM Private Variables |
43 | * @{ |
| 44 | * @{ |
44 | */ |
| 45 | */ |
45 | static const uint8_t OFFSET_TAB_CCMRx[] = |
| 46 | static const uint8_t OFFSET_TAB_CCMRx[] = |
46 | { |
| 47 | { |
47 | 0x00U, /* 0: TIMx_CH1 */ |
| 48 | 0x00U, /* 0: TIMx_CH1 */ |
48 | 0x00U, /* 1: TIMx_CH1N */ |
| 49 | 0x00U, /* 1: TIMx_CH1N */ |
49 | 0x00U, /* 2: TIMx_CH2 */ |
| 50 | 0x00U, /* 2: TIMx_CH2 */ |
50 | 0x00U, /* 3: TIMx_CH2N */ |
| 51 | 0x00U, /* 3: TIMx_CH2N */ |
51 | 0x04U, /* 4: TIMx_CH3 */ |
| 52 | 0x04U, /* 4: TIMx_CH3 */ |
52 | 0x04U, /* 5: TIMx_CH3N */ |
| 53 | 0x04U, /* 5: TIMx_CH3N */ |
53 | 0x04U /* 6: TIMx_CH4 */ |
| 54 | 0x04U /* 6: TIMx_CH4 */ |
54 | }; |
| 55 | }; |
55 | |
| 56 | 56 | static const uint8_t SHIFT_TAB_OCxx[] = |
|
| 57 | static const uint8_t SHIFT_TAB_OCxx[] = |
57 | { |
| 58 | { |
58 | 0U, /* 0: OC1M, OC1FE, OC1PE */ |
| 59 | 0U, /* 0: OC1M, OC1FE, OC1PE */ |
59 | 0U, /* 1: - NA */ |
| 60 | 0U, /* 1: - NA */ |
60 | 8U, /* 2: OC2M, OC2FE, OC2PE */ |
| 61 | 8U, /* 2: OC2M, OC2FE, OC2PE */ |
61 | 0U, /* 3: - NA */ |
| 62 | 0U, /* 3: - NA */ |
62 | 0U, /* 4: OC3M, OC3FE, OC3PE */ |
| 63 | 0U, /* 4: OC3M, OC3FE, OC3PE */ |
63 | 0U, /* 5: - NA */ |
| 64 | 0U, /* 5: - NA */ |
64 | 8U /* 6: OC4M, OC4FE, OC4PE */ |
| 65 | 8U /* 6: OC4M, OC4FE, OC4PE */ |
65 | }; |
| 66 | }; |
66 | |
| 67 | 67 | static const uint8_t SHIFT_TAB_ICxx[] = |
|
| 68 | static const uint8_t SHIFT_TAB_ICxx[] = |
68 | { |
| 69 | { |
69 | 0U, /* 0: CC1S, IC1PSC, IC1F */ |
| 70 | 0U, /* 0: CC1S, IC1PSC, IC1F */ |
70 | 0U, /* 1: - NA */ |
| 71 | 0U, /* 1: - NA */ |
71 | 8U, /* 2: CC2S, IC2PSC, IC2F */ |
| 72 | 8U, /* 2: CC2S, IC2PSC, IC2F */ |
72 | 0U, /* 3: - NA */ |
| 73 | 0U, /* 3: - NA */ |
73 | 0U, /* 4: CC3S, IC3PSC, IC3F */ |
| 74 | 0U, /* 4: CC3S, IC3PSC, IC3F */ |
74 | 0U, /* 5: - NA */ |
| 75 | 0U, /* 5: - NA */ |
75 | 8U /* 6: CC4S, IC4PSC, IC4F */ |
| 76 | 8U /* 6: CC4S, IC4PSC, IC4F */ |
76 | }; |
| 77 | }; |
77 | |
| 78 | 78 | static const uint8_t SHIFT_TAB_CCxP[] = |
|
| 79 | static const uint8_t SHIFT_TAB_CCxP[] = |
79 | { |
| 80 | { |
80 | 0U, /* 0: CC1P */ |
| 81 | 0U, /* 0: CC1P */ |
81 | 2U, /* 1: CC1NP */ |
| 82 | 2U, /* 1: CC1NP */ |
82 | 4U, /* 2: CC2P */ |
| 83 | 4U, /* 2: CC2P */ |
83 | 6U, /* 3: CC2NP */ |
| 84 | 6U, /* 3: CC2NP */ |
84 | 8U, /* 4: CC3P */ |
| 85 | 8U, /* 4: CC3P */ |
85 | 10U, /* 5: CC3NP */ |
| 86 | 10U, /* 5: CC3NP */ |
86 | 12U /* 6: CC4P */ |
| 87 | 12U /* 6: CC4P */ |
87 | }; |
| 88 | }; |
88 | |
| 89 | 89 | static const uint8_t SHIFT_TAB_OISx[] = |
|
| 90 | static const uint8_t SHIFT_TAB_OISx[] = |
90 | { |
| 91 | { |
91 | 0U, /* 0: OIS1 */ |
| 92 | 0U, /* 0: OIS1 */ |
92 | 1U, /* 1: OIS1N */ |
| 93 | 1U, /* 1: OIS1N */ |
93 | 2U, /* 2: OIS2 */ |
| 94 | 2U, /* 2: OIS2 */ |
94 | 3U, /* 3: OIS2N */ |
| 95 | 3U, /* 3: OIS2N */ |
95 | 4U, /* 4: OIS3 */ |
| 96 | 4U, /* 4: OIS3 */ |
96 | 5U, /* 5: OIS3N */ |
| 97 | 5U, /* 5: OIS3N */ |
97 | 6U /* 6: OIS4 */ |
| 98 | 6U /* 6: OIS4 */ |
98 | }; |
| 99 | }; |
99 | /** |
| 100 | /** |
100 | * @} |
| 101 | * @} |
101 | */ |
| 102 | */ |
102 | |
| 103 | 103 | /* Private constants ---------------------------------------------------------*/ |
|
| 104 | /* Private constants ---------------------------------------------------------*/ |
104 | /** @defgroup TIM_LL_Private_Constants TIM Private Constants |
| 105 | /** @defgroup TIM_LL_Private_Constants TIM Private Constants |
105 | * @{ |
| 106 | * @{ |
106 | */ |
| 107 | */ |
107 | |
| 108 | 108 | ||
| 109 | 109 | ||
| 110 | 110 | /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ |
|
| 111 | /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ |
111 | #define DT_DELAY_1 ((uint8_t)0x7F) |
| 112 | #define DT_DELAY_1 ((uint8_t)0x7F) |
112 | #define DT_DELAY_2 ((uint8_t)0x3F) |
| 113 | #define DT_DELAY_2 ((uint8_t)0x3F) |
113 | #define DT_DELAY_3 ((uint8_t)0x1F) |
| 114 | #define DT_DELAY_3 ((uint8_t)0x1F) |
114 | #define DT_DELAY_4 ((uint8_t)0x1F) |
| 115 | #define DT_DELAY_4 ((uint8_t)0x1F) |
115 | |
| 116 | 116 | /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ |
|
| 117 | /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ |
117 | #define DT_RANGE_1 ((uint8_t)0x00) |
| 118 | #define DT_RANGE_1 ((uint8_t)0x00) |
118 | #define DT_RANGE_2 ((uint8_t)0x80) |
| 119 | #define DT_RANGE_2 ((uint8_t)0x80) |
119 | #define DT_RANGE_3 ((uint8_t)0xC0) |
| 120 | #define DT_RANGE_3 ((uint8_t)0xC0) |
120 | #define DT_RANGE_4 ((uint8_t)0xE0) |
| 121 | #define DT_RANGE_4 ((uint8_t)0xE0) |
121 | |
| 122 | 122 | ||
| 123 | 123 | /** |
|
| 124 | /** |
124 | * @} |
| 125 | * @} |
125 | */ |
| 126 | */ |
126 | |
| 127 | 127 | /* Private macros ------------------------------------------------------------*/ |
|
| 128 | /* Private macros ------------------------------------------------------------*/ |
128 | /** @defgroup TIM_LL_Private_Macros TIM Private Macros |
| 129 | /** @defgroup TIM_LL_Private_Macros TIM Private Macros |
129 | * @{ |
| 130 | * @{ |
130 | */ |
| 131 | */ |
131 | /** @brief Convert channel id into channel index. |
| 132 | /** @brief Convert channel id into channel index. |
132 | * @param __CHANNEL__ This parameter can be one of the following values: |
| 133 | * @param __CHANNEL__ This parameter can be one of the following values: |
133 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 134 | * @arg @ref LL_TIM_CHANNEL_CH1 |
134 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| 135 | * @arg @ref LL_TIM_CHANNEL_CH1N |
135 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 136 | * @arg @ref LL_TIM_CHANNEL_CH2 |
136 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| 137 | * @arg @ref LL_TIM_CHANNEL_CH2N |
137 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 138 | * @arg @ref LL_TIM_CHANNEL_CH3 |
138 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| 139 | * @arg @ref LL_TIM_CHANNEL_CH3N |
139 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 140 | * @arg @ref LL_TIM_CHANNEL_CH4 |
140 | * @retval none |
| 141 | * @retval none |
141 | */ |
| 142 | */ |
142 | #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ |
| 143 | #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ |
143 | (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ |
| 144 | (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ |
144 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ |
| 145 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ |
145 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ |
| 146 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ |
146 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ |
| 147 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ |
147 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ |
| 148 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ |
148 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) |
| 149 | ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) |
149 | |
| 150 | 150 | /** @brief Calculate the deadtime sampling period(in ps). |
|
| 151 | /** @brief Calculate the deadtime sampling period(in ps). |
151 | * @param __TIMCLK__ timer input clock frequency (in Hz). |
| 152 | * @param __TIMCLK__ timer input clock frequency (in Hz). |
152 | * @param __CKD__ This parameter can be one of the following values: |
| 153 | * @param __CKD__ This parameter can be one of the following values: |
153 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
| 154 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
154 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
| 155 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
155 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
| 156 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
156 | * @retval none |
| 157 | * @retval none |
157 | */ |
| 158 | */ |
158 | #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ |
| 159 | #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ |
159 | (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ |
| 160 | (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ |
160 | ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ |
| 161 | ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ |
161 | ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) |
| 162 | ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) |
162 | /** |
| 163 | /** |
163 | * @} |
| 164 | * @} |
164 | */ |
| 165 | */ |
165 | |
| 166 | 166 | ||
| 167 | 167 | /* Exported types ------------------------------------------------------------*/ |
|
| 168 | /* Exported types ------------------------------------------------------------*/ |
168 | #if defined(USE_FULL_LL_DRIVER) |
| 169 | #if defined(USE_FULL_LL_DRIVER) |
169 | /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure |
| 170 | /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure |
170 | * @{ |
| 171 | * @{ |
171 | */ |
| 172 | */ |
172 | |
| 173 | 173 | /** |
|
| 174 | /** |
174 | * @brief TIM Time Base configuration structure definition. |
| 175 | * @brief TIM Time Base configuration structure definition. |
175 | */ |
| 176 | */ |
176 | typedef struct |
| 177 | typedef struct |
177 | { |
| 178 | { |
178 | uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
| 179 | uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
179 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
| 180 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
180 | |
| 181 | 181 | This feature can be modified afterwards using unitary function |
|
| 182 | This feature can be modified afterwards using unitary function |
182 | @ref LL_TIM_SetPrescaler().*/ |
| 183 | @ref LL_TIM_SetPrescaler().*/ |
183 | |
| 184 | 184 | uint32_t CounterMode; /*!< Specifies the counter mode. |
|
| 185 | uint32_t CounterMode; /*!< Specifies the counter mode. |
185 | This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. |
| 186 | This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. |
186 | |
| 187 | 187 | This feature can be modified afterwards using unitary function |
|
| 188 | This feature can be modified afterwards using unitary function |
188 | @ref LL_TIM_SetCounterMode().*/ |
| 189 | @ref LL_TIM_SetCounterMode().*/ |
189 | |
| 190 | 190 | uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active |
|
| 191 | uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active |
191 | Auto-Reload Register at the next update event. |
| 192 | Auto-Reload Register at the next update event. |
192 | This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
| 193 | This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
193 | Some timer instances may support 32 bits counters. In that case this parameter must |
| 194 | Some timer instances may support 32 bits counters. In that case this parameter must |
194 | be a number between 0x0000 and 0xFFFFFFFF. |
| 195 | be a number between 0x0000 and 0xFFFFFFFF. |
195 | |
| 196 | 196 | This feature can be modified afterwards using unitary function |
|
| 197 | This feature can be modified afterwards using unitary function |
197 | @ref LL_TIM_SetAutoReload().*/ |
| 198 | @ref LL_TIM_SetAutoReload().*/ |
198 | |
| 199 | 199 | uint32_t ClockDivision; /*!< Specifies the clock division. |
|
| 200 | uint32_t ClockDivision; /*!< Specifies the clock division. |
200 | This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. |
| 201 | This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. |
201 | |
| 202 | 202 | This feature can be modified afterwards using unitary function |
|
| 203 | This feature can be modified afterwards using unitary function |
203 | @ref LL_TIM_SetClockDivision().*/ |
| 204 | @ref LL_TIM_SetClockDivision().*/ |
204 | |
| 205 | 205 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
|
| 206 | uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter |
206 | reaches zero, an update event is generated and counting restarts |
| 207 | reaches zero, an update event is generated and counting restarts |
207 | from the RCR value (N). |
| 208 | from the RCR value (N). |
208 | This means in PWM mode that (N+1) corresponds to: |
| 209 | This means in PWM mode that (N+1) corresponds to: |
209 | - the number of PWM periods in edge-aligned mode |
| 210 | - the number of PWM periods in edge-aligned mode |
210 | - the number of half PWM period in center-aligned mode |
| 211 | - the number of half PWM period in center-aligned mode |
211 | GP timers: this parameter must be a number between Min_Data = 0x00 and |
| 212 | GP timers: this parameter must be a number between Min_Data = 0x00 and |
212 | Max_Data = 0xFF. |
| 213 | Max_Data = 0xFF. |
213 | Advanced timers: this parameter must be a number between Min_Data = 0x0000 and |
| 214 | Advanced timers: this parameter must be a number between Min_Data = 0x0000 and |
214 | Max_Data = 0xFFFF. |
| 215 | Max_Data = 0xFFFF. |
215 | |
| 216 | 216 | This feature can be modified afterwards using unitary function |
|
| 217 | This feature can be modified afterwards using unitary function |
217 | @ref LL_TIM_SetRepetitionCounter().*/ |
| 218 | @ref LL_TIM_SetRepetitionCounter().*/ |
218 | } LL_TIM_InitTypeDef; |
| 219 | } LL_TIM_InitTypeDef; |
219 | |
| 220 | 220 | /** |
|
| 221 | /** |
221 | * @brief TIM Output Compare configuration structure definition. |
| 222 | * @brief TIM Output Compare configuration structure definition. |
222 | */ |
| 223 | */ |
223 | typedef struct |
| 224 | typedef struct |
224 | { |
| 225 | { |
225 | uint32_t OCMode; /*!< Specifies the output mode. |
| 226 | uint32_t OCMode; /*!< Specifies the output mode. |
226 | This parameter can be a value of @ref TIM_LL_EC_OCMODE. |
| 227 | This parameter can be a value of @ref TIM_LL_EC_OCMODE. |
227 | |
| 228 | 228 | This feature can be modified afterwards using unitary function |
|
| 229 | This feature can be modified afterwards using unitary function |
229 | @ref LL_TIM_OC_SetMode().*/ |
| 230 | @ref LL_TIM_OC_SetMode().*/ |
230 | |
| 231 | 231 | uint32_t OCState; /*!< Specifies the TIM Output Compare state. |
|
| 232 | uint32_t OCState; /*!< Specifies the TIM Output Compare state. |
232 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
| 233 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
233 | |
| 234 | 234 | This feature can be modified afterwards using unitary functions |
|
| 235 | This feature can be modified afterwards using unitary functions |
235 | @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
| 236 | @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
236 | |
| 237 | 237 | uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. |
|
| 238 | uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. |
238 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
| 239 | This parameter can be a value of @ref TIM_LL_EC_OCSTATE. |
239 | |
| 240 | 240 | This feature can be modified afterwards using unitary functions |
|
| 241 | This feature can be modified afterwards using unitary functions |
241 | @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
| 242 | @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ |
242 | |
| 243 | 243 | uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. |
|
| 244 | uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. |
244 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
| 245 | This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. |
245 | |
| 246 | 246 | This feature can be modified afterwards using unitary function |
|
| 247 | This feature can be modified afterwards using unitary function |
247 | LL_TIM_OC_SetCompareCHx (x=1..6).*/ |
| 248 | LL_TIM_OC_SetCompareCHx (x=1..6).*/ |
248 | |
| 249 | 249 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
|
| 250 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
250 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
| 251 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
251 | |
| 252 | 252 | This feature can be modified afterwards using unitary function |
|
| 253 | This feature can be modified afterwards using unitary function |
253 | @ref LL_TIM_OC_SetPolarity().*/ |
| 254 | @ref LL_TIM_OC_SetPolarity().*/ |
254 | |
| 255 | 255 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
|
| 256 | uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. |
256 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
| 257 | This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. |
257 | |
| 258 | 258 | This feature can be modified afterwards using unitary function |
|
| 259 | This feature can be modified afterwards using unitary function |
259 | @ref LL_TIM_OC_SetPolarity().*/ |
| 260 | @ref LL_TIM_OC_SetPolarity().*/ |
260 | |
| 261 | 261 | ||
| 262 | 262 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
|
| 263 | uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
263 | This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. |
| 264 | This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. |
264 | |
| 265 | 265 | This feature can be modified afterwards using unitary function |
|
| 266 | This feature can be modified afterwards using unitary function |
266 | @ref LL_TIM_OC_SetIdleState().*/ |
| 267 | @ref LL_TIM_OC_SetIdleState().*/ |
267 | |
| 268 | 268 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
|
| 269 | uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. |
269 | This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. |
| 270 | This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. |
270 | |
| 271 | 271 | This feature can be modified afterwards using unitary function |
|
| 272 | This feature can be modified afterwards using unitary function |
272 | @ref LL_TIM_OC_SetIdleState().*/ |
| 273 | @ref LL_TIM_OC_SetIdleState().*/ |
273 | } LL_TIM_OC_InitTypeDef; |
| 274 | } LL_TIM_OC_InitTypeDef; |
274 | |
| 275 | 275 | /** |
|
| 276 | /** |
276 | * @brief TIM Input Capture configuration structure definition. |
| 277 | * @brief TIM Input Capture configuration structure definition. |
277 | */ |
| 278 | */ |
278 | |
| 279 | 279 | typedef struct |
|
| 280 | typedef struct |
280 | { |
| 281 | { |
281 | |
| 282 | 282 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
|
| 283 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
283 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
| 284 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
284 | |
| 285 | 285 | This feature can be modified afterwards using unitary function |
|
| 286 | This feature can be modified afterwards using unitary function |
286 | @ref LL_TIM_IC_SetPolarity().*/ |
| 287 | @ref LL_TIM_IC_SetPolarity().*/ |
287 | |
| 288 | 288 | uint32_t ICActiveInput; /*!< Specifies the input. |
|
| 289 | uint32_t ICActiveInput; /*!< Specifies the input. |
289 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
| 290 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
290 | |
| 291 | 291 | This feature can be modified afterwards using unitary function |
|
| 292 | This feature can be modified afterwards using unitary function |
292 | @ref LL_TIM_IC_SetActiveInput().*/ |
| 293 | @ref LL_TIM_IC_SetActiveInput().*/ |
293 | |
| 294 | 294 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
|
| 295 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
295 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
| 296 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
296 | |
| 297 | 297 | This feature can be modified afterwards using unitary function |
|
| 298 | This feature can be modified afterwards using unitary function |
298 | @ref LL_TIM_IC_SetPrescaler().*/ |
| 299 | @ref LL_TIM_IC_SetPrescaler().*/ |
299 | |
| 300 | 300 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
|
| 301 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
301 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
| 302 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
302 | |
| 303 | 303 | This feature can be modified afterwards using unitary function |
|
| 304 | This feature can be modified afterwards using unitary function |
304 | @ref LL_TIM_IC_SetFilter().*/ |
| 305 | @ref LL_TIM_IC_SetFilter().*/ |
305 | } LL_TIM_IC_InitTypeDef; |
| 306 | } LL_TIM_IC_InitTypeDef; |
306 | |
| 307 | 307 | ||
| 308 | 308 | /** |
|
| 309 | /** |
309 | * @brief TIM Encoder interface configuration structure definition. |
| 310 | * @brief TIM Encoder interface configuration structure definition. |
310 | */ |
| 311 | */ |
311 | typedef struct |
| 312 | typedef struct |
312 | { |
| 313 | { |
313 | uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). |
| 314 | uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). |
314 | This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. |
| 315 | This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. |
315 | |
| 316 | 316 | This feature can be modified afterwards using unitary function |
|
| 317 | This feature can be modified afterwards using unitary function |
317 | @ref LL_TIM_SetEncoderMode().*/ |
| 318 | @ref LL_TIM_SetEncoderMode().*/ |
318 | |
| 319 | 319 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
|
| 320 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
320 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
| 321 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
321 | |
| 322 | 322 | This feature can be modified afterwards using unitary function |
|
| 323 | This feature can be modified afterwards using unitary function |
323 | @ref LL_TIM_IC_SetPolarity().*/ |
| 324 | @ref LL_TIM_IC_SetPolarity().*/ |
324 | |
| 325 | 325 | uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source |
|
| 326 | uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source |
326 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
| 327 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
327 | |
| 328 | 328 | This feature can be modified afterwards using unitary function |
|
| 329 | This feature can be modified afterwards using unitary function |
329 | @ref LL_TIM_IC_SetActiveInput().*/ |
| 330 | @ref LL_TIM_IC_SetActiveInput().*/ |
330 | |
| 331 | 331 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
|
| 332 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
332 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
| 333 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
333 | |
| 334 | 334 | This feature can be modified afterwards using unitary function |
|
| 335 | This feature can be modified afterwards using unitary function |
335 | @ref LL_TIM_IC_SetPrescaler().*/ |
| 336 | @ref LL_TIM_IC_SetPrescaler().*/ |
336 | |
| 337 | 337 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
|
| 338 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
338 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
| 339 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
339 | |
| 340 | 340 | This feature can be modified afterwards using unitary function |
|
| 341 | This feature can be modified afterwards using unitary function |
341 | @ref LL_TIM_IC_SetFilter().*/ |
| 342 | @ref LL_TIM_IC_SetFilter().*/ |
342 | |
| 343 | 343 | uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. |
|
| 344 | uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. |
344 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
| 345 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
345 | |
| 346 | 346 | This feature can be modified afterwards using unitary function |
|
| 347 | This feature can be modified afterwards using unitary function |
347 | @ref LL_TIM_IC_SetPolarity().*/ |
| 348 | @ref LL_TIM_IC_SetPolarity().*/ |
348 | |
| 349 | 349 | uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source |
|
| 350 | uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source |
350 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
| 351 | This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. |
351 | |
| 352 | 352 | This feature can be modified afterwards using unitary function |
|
| 353 | This feature can be modified afterwards using unitary function |
353 | @ref LL_TIM_IC_SetActiveInput().*/ |
| 354 | @ref LL_TIM_IC_SetActiveInput().*/ |
354 | |
| 355 | 355 | uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. |
|
| 356 | uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. |
356 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
| 357 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
357 | |
| 358 | 358 | This feature can be modified afterwards using unitary function |
|
| 359 | This feature can be modified afterwards using unitary function |
359 | @ref LL_TIM_IC_SetPrescaler().*/ |
| 360 | @ref LL_TIM_IC_SetPrescaler().*/ |
360 | |
| 361 | 361 | uint32_t IC2Filter; /*!< Specifies the TI2 input filter. |
|
| 362 | uint32_t IC2Filter; /*!< Specifies the TI2 input filter. |
362 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
| 363 | This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. |
363 | |
| 364 | 364 | This feature can be modified afterwards using unitary function |
|
| 365 | This feature can be modified afterwards using unitary function |
365 | @ref LL_TIM_IC_SetFilter().*/ |
| 366 | @ref LL_TIM_IC_SetFilter().*/ |
366 | |
| 367 | 367 | } LL_TIM_ENCODER_InitTypeDef; |
|
| 368 | } LL_TIM_ENCODER_InitTypeDef; |
368 | |
| 369 | 369 | /** |
|
| 370 | /** |
370 | * @brief TIM Hall sensor interface configuration structure definition. |
| 371 | * @brief TIM Hall sensor interface configuration structure definition. |
371 | */ |
| 372 | */ |
372 | typedef struct |
| 373 | typedef struct |
373 | { |
| 374 | { |
374 | |
| 375 | 375 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
|
| 376 | uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. |
376 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
| 377 | This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. |
377 | |
| 378 | 378 | This feature can be modified afterwards using unitary function |
|
| 379 | This feature can be modified afterwards using unitary function |
379 | @ref LL_TIM_IC_SetPolarity().*/ |
| 380 | @ref LL_TIM_IC_SetPolarity().*/ |
380 | |
| 381 | 381 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
|
| 382 | uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. |
382 | Prescaler must be set to get a maximum counter period longer than the |
| 383 | Prescaler must be set to get a maximum counter period longer than the |
383 | time interval between 2 consecutive changes on the Hall inputs. |
| 384 | time interval between 2 consecutive changes on the Hall inputs. |
384 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
| 385 | This parameter can be a value of @ref TIM_LL_EC_ICPSC. |
385 | |
| 386 | 386 | This feature can be modified afterwards using unitary function |
|
| 387 | This feature can be modified afterwards using unitary function |
387 | @ref LL_TIM_IC_SetPrescaler().*/ |
| 388 | @ref LL_TIM_IC_SetPrescaler().*/ |
388 | |
| 389 | 389 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
|
| 390 | uint32_t IC1Filter; /*!< Specifies the TI1 input filter. |
390 | This parameter can be a value of |
| 391 | This parameter can be a value of |
391 | @ref TIM_LL_EC_IC_FILTER. |
| 392 | @ref TIM_LL_EC_IC_FILTER. |
392 | |
| 393 | 393 | This feature can be modified afterwards using unitary function |
|
| 394 | This feature can be modified afterwards using unitary function |
394 | @ref LL_TIM_IC_SetFilter().*/ |
| 395 | @ref LL_TIM_IC_SetFilter().*/ |
395 | |
| 396 | 396 | uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. |
|
| 397 | uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. |
397 | A positive pulse (TRGO event) is generated with a programmable delay every time |
| 398 | A positive pulse (TRGO event) is generated with a programmable delay every time |
398 | a change occurs on the Hall inputs. |
| 399 | a change occurs on the Hall inputs. |
399 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. |
| 400 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. |
400 | |
| 401 | 401 | This feature can be modified afterwards using unitary function |
|
| 402 | This feature can be modified afterwards using unitary function |
402 | @ref LL_TIM_OC_SetCompareCH2().*/ |
| 403 | @ref LL_TIM_OC_SetCompareCH2().*/ |
403 | } LL_TIM_HALLSENSOR_InitTypeDef; |
| 404 | } LL_TIM_HALLSENSOR_InitTypeDef; |
404 | |
| 405 | 405 | /** |
|
| 406 | /** |
406 | * @brief BDTR (Break and Dead Time) structure definition |
| 407 | * @brief BDTR (Break and Dead Time) structure definition |
407 | */ |
| 408 | */ |
408 | typedef struct |
| 409 | typedef struct |
409 | { |
| 410 | { |
410 | uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. |
| 411 | uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. |
411 | This parameter can be a value of @ref TIM_LL_EC_OSSR |
| 412 | This parameter can be a value of @ref TIM_LL_EC_OSSR |
412 | |
| 413 | 413 | This feature can be modified afterwards using unitary function |
|
| 414 | This feature can be modified afterwards using unitary function |
414 | @ref LL_TIM_SetOffStates() |
| 415 | @ref LL_TIM_SetOffStates() |
415 | |
| 416 | 416 | @note This bit-field cannot be modified as long as LOCK level 2 has been |
|
| 417 | @note This bit-field cannot be modified as long as LOCK level 2 has been |
417 | programmed. */ |
| 418 | programmed. */ |
418 | |
| 419 | 419 | uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. |
|
| 420 | uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. |
420 | This parameter can be a value of @ref TIM_LL_EC_OSSI |
| 421 | This parameter can be a value of @ref TIM_LL_EC_OSSI |
421 | |
| 422 | 422 | This feature can be modified afterwards using unitary function |
|
| 423 | This feature can be modified afterwards using unitary function |
423 | @ref LL_TIM_SetOffStates() |
| 424 | @ref LL_TIM_SetOffStates() |
424 | |
| 425 | 425 | @note This bit-field cannot be modified as long as LOCK level 2 has been |
|
| 426 | @note This bit-field cannot be modified as long as LOCK level 2 has been |
426 | programmed. */ |
| 427 | programmed. */ |
427 | |
| 428 | 428 | uint32_t LockLevel; /*!< Specifies the LOCK level parameters. |
|
| 429 | uint32_t LockLevel; /*!< Specifies the LOCK level parameters. |
429 | This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL |
| 430 | This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL |
430 | |
| 431 | 431 | @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR |
|
| 432 | @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR |
432 | register has been written, their content is frozen until the next reset.*/ |
| 433 | register has been written, their content is frozen until the next reset.*/ |
433 | |
| 434 | 434 | uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the |
|
| 435 | uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the |
435 | switching-on of the outputs. |
| 436 | switching-on of the outputs. |
436 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
| 437 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
437 | |
| 438 | 438 | This feature can be modified afterwards using unitary function |
|
| 439 | This feature can be modified afterwards using unitary function |
439 | @ref LL_TIM_OC_SetDeadTime() |
| 440 | @ref LL_TIM_OC_SetDeadTime() |
440 | |
| 441 | 441 | @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been |
|
| 442 | @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been |
442 | programmed. */ |
| 443 | programmed. */ |
443 | |
| 444 | 444 | uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. |
|
| 445 | uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. |
445 | This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE |
| 446 | This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE |
446 | |
| 447 | 447 | This feature can be modified afterwards using unitary functions |
|
| 448 | This feature can be modified afterwards using unitary functions |
448 | @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() |
| 449 | @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() |
449 | |
| 450 | 450 | @note This bit-field can not be modified as long as LOCK level 1 has been |
|
| 451 | @note This bit-field can not be modified as long as LOCK level 1 has been |
451 | programmed. */ |
| 452 | programmed. */ |
452 | |
| 453 | 453 | uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. |
|
| 454 | uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. |
454 | This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY |
| 455 | This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY |
455 | |
| 456 | 456 | This feature can be modified afterwards using unitary function |
|
| 457 | This feature can be modified afterwards using unitary function |
457 | @ref LL_TIM_ConfigBRK() |
| 458 | @ref LL_TIM_ConfigBRK() |
458 | |
| 459 | 459 | @note This bit-field can not be modified as long as LOCK level 1 has been |
|
| 460 | @note This bit-field can not be modified as long as LOCK level 1 has been |
460 | programmed. */ |
| 461 | programmed. */ |
461 | |
| 462 | 462 | uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. |
|
| 463 | uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. |
463 | This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE |
| 464 | This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE |
464 | |
| 465 | 465 | This feature can be modified afterwards using unitary functions |
|
| 466 | This feature can be modified afterwards using unitary functions |
466 | @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() |
| 467 | @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() |
467 | |
| 468 | 468 | @note This bit-field can not be modified as long as LOCK level 1 has been |
|
| 469 | @note This bit-field can not be modified as long as LOCK level 1 has been |
469 | programmed. */ |
| 470 | programmed. */ |
470 | } LL_TIM_BDTR_InitTypeDef; |
| 471 | } LL_TIM_BDTR_InitTypeDef; |
471 | |
| 472 | 472 | /** |
|
| 473 | /** |
473 | * @} |
| 474 | * @} |
474 | */ |
| 475 | */ |
475 | #endif /* USE_FULL_LL_DRIVER */ |
| 476 | #endif /* USE_FULL_LL_DRIVER */ |
476 | |
| 477 | 477 | /* Exported constants --------------------------------------------------------*/ |
|
| 478 | /* Exported constants --------------------------------------------------------*/ |
478 | /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants |
| 479 | /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants |
479 | * @{ |
| 480 | * @{ |
480 | */ |
| 481 | */ |
481 | |
| 482 | 482 | /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines |
|
| 483 | /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines |
483 | * @brief Flags defines which can be used with LL_TIM_ReadReg function. |
| 484 | * @brief Flags defines which can be used with LL_TIM_ReadReg function. |
484 | * @{ |
| 485 | * @{ |
485 | */ |
| 486 | */ |
486 | #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ |
| 487 | #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ |
487 | #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ |
| 488 | #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ |
488 | #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ |
| 489 | #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ |
489 | #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ |
| 490 | #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ |
490 | #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ |
| 491 | #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ |
491 | #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ |
| 492 | #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ |
492 | #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ |
| 493 | #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ |
493 | #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ |
| 494 | #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ |
494 | #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ |
| 495 | #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ |
495 | #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ |
| 496 | #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ |
496 | #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ |
| 497 | #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ |
497 | #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ |
| 498 | #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ |
498 | /** |
| 499 | /** |
499 | * @} |
| 500 | * @} |
500 | */ |
| 501 | */ |
501 | |
| 502 | 502 | #if defined(USE_FULL_LL_DRIVER) |
|
| 503 | #if defined(USE_FULL_LL_DRIVER) |
503 | /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable |
| 504 | /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable |
504 | * @{ |
| 505 | * @{ |
505 | */ |
| 506 | */ |
506 | #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ |
| 507 | #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ |
507 | #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ |
| 508 | #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ |
508 | /** |
| 509 | /** |
509 | * @} |
| 510 | * @} |
510 | */ |
| 511 | */ |
511 | |
| 512 | 512 | /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable |
|
| 513 | /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable |
513 | * @{ |
| 514 | * @{ |
514 | */ |
| 515 | */ |
515 | #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ |
| 516 | #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ |
516 | #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ |
| 517 | #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ |
517 | /** |
| 518 | /** |
518 | * @} |
| 519 | * @} |
519 | */ |
| 520 | */ |
520 | #endif /* USE_FULL_LL_DRIVER */ |
| 521 | #endif /* USE_FULL_LL_DRIVER */ |
521 | |
| 522 | 522 | /** @defgroup TIM_LL_EC_IT IT Defines |
|
| 523 | /** @defgroup TIM_LL_EC_IT IT Defines |
523 | * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. |
| 524 | * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. |
524 | * @{ |
| 525 | * @{ |
525 | */ |
| 526 | */ |
526 | #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ |
| 527 | #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ |
527 | #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ |
| 528 | #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ |
528 | #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ |
| 529 | #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ |
529 | #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ |
| 530 | #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ |
530 | #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ |
| 531 | #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ |
531 | #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ |
| 532 | #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ |
532 | #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ |
| 533 | #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ |
533 | #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ |
| 534 | #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ |
534 | /** |
| 535 | /** |
535 | * @} |
| 536 | * @} |
536 | */ |
| 537 | */ |
537 | |
| 538 | 538 | /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source |
|
| 539 | /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source |
539 | * @{ |
| 540 | * @{ |
540 | */ |
| 541 | */ |
541 | #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ |
| 542 | #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ |
542 | #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ |
| 543 | #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ |
543 | /** |
| 544 | /** |
544 | * @} |
| 545 | * @} |
545 | */ |
| 546 | */ |
546 | |
| 547 | 547 | /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode |
|
| 548 | /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode |
548 | * @{ |
| 549 | * @{ |
549 | */ |
| 550 | */ |
550 | #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ |
| 551 | #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ |
551 | #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ |
| 552 | #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ |
552 | /** |
| 553 | /** |
553 | * @} |
| 554 | * @} |
554 | */ |
| 555 | */ |
555 | |
| 556 | 556 | /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode |
|
| 557 | /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode |
557 | * @{ |
| 558 | * @{ |
558 | */ |
| 559 | */ |
559 | #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ |
| 560 | #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ |
560 | #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ |
| 561 | #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ |
561 | #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ |
| 562 | #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ |
562 | #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ |
| 563 | #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ |
563 | #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ |
| 564 | #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ |
564 | /** |
| 565 | /** |
565 | * @} |
| 566 | * @} |
566 | */ |
| 567 | */ |
567 | |
| 568 | 568 | /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division |
|
| 569 | /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division |
569 | * @{ |
| 570 | * @{ |
570 | */ |
| 571 | */ |
571 | #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ |
| 572 | #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ |
572 | #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ |
| 573 | #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ |
573 | #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ |
| 574 | #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ |
574 | /** |
| 575 | /** |
575 | * @} |
| 576 | * @} |
576 | */ |
| 577 | */ |
577 | |
| 578 | 578 | /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction |
|
| 579 | /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction |
579 | * @{ |
| 580 | * @{ |
580 | */ |
| 581 | */ |
581 | #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ |
| 582 | #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ |
582 | #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ |
| 583 | #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ |
583 | /** |
| 584 | /** |
584 | * @} |
| 585 | * @} |
585 | */ |
| 586 | */ |
586 | |
| 587 | 587 | /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source |
|
| 588 | /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source |
588 | * @{ |
| 589 | * @{ |
589 | */ |
| 590 | */ |
590 | #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ |
| 591 | #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ |
591 | #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ |
| 592 | #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ |
592 | /** |
| 593 | /** |
593 | * @} |
| 594 | * @} |
594 | */ |
| 595 | */ |
595 | |
| 596 | 596 | /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request |
|
| 597 | /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request |
597 | * @{ |
| 598 | * @{ |
598 | */ |
| 599 | */ |
599 | #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ |
| 600 | #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ |
600 | #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ |
| 601 | #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ |
601 | /** |
| 602 | /** |
602 | * @} |
| 603 | * @} |
603 | */ |
| 604 | */ |
604 | |
| 605 | 605 | /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level |
|
| 606 | /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level |
606 | * @{ |
| 607 | * @{ |
607 | */ |
| 608 | */ |
608 | #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ |
| 609 | #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ |
609 | #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ |
| 610 | #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ |
610 | #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ |
| 611 | #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ |
611 | #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ |
| 612 | #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ |
612 | /** |
| 613 | /** |
613 | * @} |
| 614 | * @} |
614 | */ |
| 615 | */ |
615 | |
| 616 | 616 | /** @defgroup TIM_LL_EC_CHANNEL Channel |
|
| 617 | /** @defgroup TIM_LL_EC_CHANNEL Channel |
617 | * @{ |
| 618 | * @{ |
618 | */ |
| 619 | */ |
619 | #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ |
| 620 | #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ |
620 | #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ |
| 621 | #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ |
621 | #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ |
| 622 | #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ |
622 | #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ |
| 623 | #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ |
623 | #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ |
| 624 | #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ |
624 | #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ |
| 625 | #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ |
625 | #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ |
| 626 | #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ |
626 | /** |
| 627 | /** |
627 | * @} |
| 628 | * @} |
628 | */ |
| 629 | */ |
629 | |
| 630 | 630 | #if defined(USE_FULL_LL_DRIVER) |
|
| 631 | #if defined(USE_FULL_LL_DRIVER) |
631 | /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State |
| 632 | /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State |
632 | * @{ |
| 633 | * @{ |
633 | */ |
| 634 | */ |
634 | #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ |
| 635 | #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ |
635 | #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ |
| 636 | #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ |
636 | /** |
| 637 | /** |
637 | * @} |
| 638 | * @} |
638 | */ |
| 639 | */ |
639 | #endif /* USE_FULL_LL_DRIVER */ |
| 640 | #endif /* USE_FULL_LL_DRIVER */ |
640 | |
| 641 | 641 | /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode |
|
| 642 | /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode |
642 | * @{ |
| 643 | * @{ |
643 | */ |
| 644 | */ |
644 | #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ |
| 645 | #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ |
645 | #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ |
| 646 | #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ |
646 | #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ |
| 647 | #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ |
647 | #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ |
| 648 | #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ |
648 | #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ |
| 649 | #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ |
649 | #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ |
| 650 | #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ |
650 | #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ |
| 651 | #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ |
651 | #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ |
| 652 | #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ |
652 | /** |
| 653 | /** |
653 | * @} |
| 654 | * @} |
654 | */ |
| 655 | */ |
655 | |
| 656 | 656 | /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity |
|
| 657 | /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity |
657 | * @{ |
| 658 | * @{ |
658 | */ |
| 659 | */ |
659 | #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ |
| 660 | #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ |
660 | #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ |
| 661 | #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ |
661 | /** |
| 662 | /** |
662 | * @} |
| 663 | * @} |
663 | */ |
| 664 | */ |
664 | |
| 665 | 665 | /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State |
|
| 666 | /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State |
666 | * @{ |
| 667 | * @{ |
667 | */ |
| 668 | */ |
668 | #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ |
| 669 | #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ |
669 | #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ |
| 670 | #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ |
670 | /** |
| 671 | /** |
671 | * @} |
| 672 | * @} |
672 | */ |
| 673 | */ |
673 | |
| 674 | 674 | ||
| 675 | 675 | /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection |
|
| 676 | /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection |
676 | * @{ |
| 677 | * @{ |
677 | */ |
| 678 | */ |
678 | #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ |
| 679 | #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ |
679 | #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ |
| 680 | #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ |
680 | #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ |
| 681 | #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ |
681 | /** |
| 682 | /** |
682 | * @} |
| 683 | * @} |
683 | */ |
| 684 | */ |
684 | |
| 685 | 685 | /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler |
|
| 686 | /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler |
686 | * @{ |
| 687 | * @{ |
687 | */ |
| 688 | */ |
688 | #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ |
| 689 | #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ |
689 | #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ |
| 690 | #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ |
690 | #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ |
| 691 | #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ |
691 | #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ |
| 692 | #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ |
692 | /** |
| 693 | /** |
693 | * @} |
| 694 | * @} |
694 | */ |
| 695 | */ |
695 | |
| 696 | 696 | /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter |
|
| 697 | /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter |
697 | * @{ |
| 698 | * @{ |
698 | */ |
| 699 | */ |
699 | #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
| 700 | #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
700 | #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ |
| 701 | #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ |
701 | #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ |
| 702 | #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ |
702 | #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ |
| 703 | #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ |
703 | #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ |
| 704 | #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ |
704 | #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ |
| 705 | #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ |
705 | #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ |
| 706 | #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ |
706 | #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ |
| 707 | #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ |
707 | #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ |
| 708 | #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ |
708 | #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ |
| 709 | #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ |
709 | #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ |
| 710 | #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ |
710 | #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ |
| 711 | #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ |
711 | #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ |
| 712 | #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ |
712 | #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ |
| 713 | #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ |
713 | #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ |
| 714 | #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ |
714 | #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ |
| 715 | #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ |
715 | /** |
| 716 | /** |
716 | * @} |
| 717 | * @} |
717 | */ |
| 718 | */ |
718 | |
| 719 | 719 | /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity |
|
| 720 | /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity |
720 | * @{ |
| 721 | * @{ |
721 | */ |
| 722 | */ |
722 | #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ |
| 723 | #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ |
723 | #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ |
| 724 | #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ |
724 | /** |
| 725 | /** |
725 | * @} |
| 726 | * @} |
726 | */ |
| 727 | */ |
727 | |
| 728 | 728 | /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source |
|
| 729 | /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source |
729 | * @{ |
| 730 | * @{ |
730 | */ |
| 731 | */ |
731 | #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ |
| 732 | #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ |
732 | #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ |
| 733 | #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ |
733 | #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ |
| 734 | #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ |
734 | /** |
| 735 | /** |
735 | * @} |
| 736 | * @} |
736 | */ |
| 737 | */ |
737 | |
| 738 | 738 | /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode |
|
| 739 | /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode |
739 | * @{ |
| 740 | * @{ |
740 | */ |
| 741 | */ |
741 | #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
| 742 | #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ |
742 | #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ |
| 743 | #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ |
743 | #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ |
| 744 | #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ |
744 | /** |
| 745 | /** |
745 | * @} |
| 746 | * @} |
746 | */ |
| 747 | */ |
747 | |
| 748 | 748 | /** @defgroup TIM_LL_EC_TRGO Trigger Output |
|
| 749 | /** @defgroup TIM_LL_EC_TRGO Trigger Output |
749 | * @{ |
| 750 | * @{ |
750 | */ |
| 751 | */ |
751 | #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ |
| 752 | #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ |
752 | #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ |
| 753 | #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ |
753 | #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ |
| 754 | #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ |
754 | #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ |
| 755 | #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ |
755 | #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ |
| 756 | #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ |
756 | #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ |
| 757 | #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ |
757 | #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ |
| 758 | #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ |
758 | #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ |
| 759 | #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ |
759 | /** |
| 760 | /** |
760 | * @} |
| 761 | * @} |
761 | */ |
| 762 | */ |
762 | |
| 763 | 763 | ||
| 764 | 764 | /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode |
|
| 765 | /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode |
765 | * @{ |
| 766 | * @{ |
766 | */ |
| 767 | */ |
767 | #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ |
| 768 | #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ |
768 | #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ |
| 769 | #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ |
769 | #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ |
| 770 | #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ |
770 | #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ |
| 771 | #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ |
771 | /** |
| 772 | /** |
772 | * @} |
| 773 | * @} |
773 | */ |
| 774 | */ |
774 | |
| 775 | 775 | /** @defgroup TIM_LL_EC_TS Trigger Selection |
|
| 776 | /** @defgroup TIM_LL_EC_TS Trigger Selection |
776 | * @{ |
| 777 | * @{ |
777 | */ |
| 778 | */ |
778 | #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ |
| 779 | #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ |
779 | #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ |
| 780 | #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ |
780 | #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ |
| 781 | #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ |
781 | #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ |
| 782 | #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ |
782 | #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ |
| 783 | #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ |
783 | #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ |
| 784 | #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ |
784 | #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ |
| 785 | #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ |
785 | #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ |
| 786 | #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ |
786 | /** |
| 787 | /** |
787 | * @} |
| 788 | * @} |
788 | */ |
| 789 | */ |
789 | |
| 790 | 790 | /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity |
|
| 791 | /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity |
791 | * @{ |
| 792 | * @{ |
792 | */ |
| 793 | */ |
793 | #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ |
| 794 | #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ |
794 | #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ |
| 795 | #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ |
795 | /** |
| 796 | /** |
796 | * @} |
| 797 | * @} |
797 | */ |
| 798 | */ |
798 | |
| 799 | 799 | /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler |
|
| 800 | /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler |
800 | * @{ |
| 801 | * @{ |
801 | */ |
| 802 | */ |
802 | #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ |
| 803 | #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ |
803 | #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ |
| 804 | #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ |
804 | #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ |
| 805 | #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ |
805 | #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ |
| 806 | #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ |
806 | /** |
| 807 | /** |
807 | * @} |
| 808 | * @} |
808 | */ |
| 809 | */ |
809 | |
| 810 | 810 | /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter |
|
| 811 | /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter |
811 | * @{ |
| 812 | * @{ |
812 | */ |
| 813 | */ |
813 | #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
| 814 | #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ |
814 | #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ |
| 815 | #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ |
815 | #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ |
| 816 | #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ |
816 | #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ |
| 817 | #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ |
817 | #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ |
| 818 | #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ |
818 | #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ |
| 819 | #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ |
819 | #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ |
| 820 | #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ |
820 | #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ |
| 821 | #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ |
821 | #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ |
| 822 | #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ |
822 | #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ |
| 823 | #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ |
823 | #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ |
| 824 | #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ |
824 | #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ |
| 825 | #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ |
825 | #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ |
| 826 | #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ |
826 | #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ |
| 827 | #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ |
827 | #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ |
| 828 | #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ |
828 | #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ |
| 829 | #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ |
829 | /** |
| 830 | /** |
830 | * @} |
| 831 | * @} |
831 | */ |
| 832 | */ |
832 | |
| 833 | 833 | ||
| 834 | 834 | /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity |
|
| 835 | /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity |
835 | * @{ |
| 836 | * @{ |
836 | */ |
| 837 | */ |
837 | #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ |
| 838 | #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ |
838 | #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ |
| 839 | #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ |
839 | /** |
| 840 | /** |
840 | * @} |
| 841 | * @} |
841 | */ |
| 842 | */ |
842 | |
| 843 | 843 | ||
| 844 | 844 | ||
| 845 | 845 | ||
| 846 | 846 | /** @defgroup TIM_LL_EC_OSSI OSSI |
|
| 847 | /** @defgroup TIM_LL_EC_OSSI OSSI |
847 | * @{ |
| 848 | * @{ |
848 | */ |
| 849 | */ |
849 | #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ |
| 850 | #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ |
850 | #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ |
| 851 | #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ |
851 | /** |
| 852 | /** |
852 | * @} |
| 853 | * @} |
853 | */ |
| 854 | */ |
854 | |
| 855 | 855 | /** @defgroup TIM_LL_EC_OSSR OSSR |
|
| 856 | /** @defgroup TIM_LL_EC_OSSR OSSR |
856 | * @{ |
| 857 | * @{ |
857 | */ |
| 858 | */ |
858 | #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ |
| 859 | #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ |
859 | #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ |
| 860 | #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ |
860 | /** |
| 861 | /** |
861 | * @} |
| 862 | * @} |
862 | */ |
| 863 | */ |
863 | |
| 864 | 864 | ||
| 865 | 865 | /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address |
|
| 866 | /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address |
866 | * @{ |
| 867 | * @{ |
867 | */ |
| 868 | */ |
868 | #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ |
| 869 | #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ |
869 | #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ |
| 870 | #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ |
870 | #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ |
| 871 | #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ |
871 | #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ |
| 872 | #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ |
872 | #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ |
| 873 | #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ |
873 | #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ |
| 874 | #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ |
874 | #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ |
| 875 | #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ |
875 | #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ |
| 876 | #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ |
876 | #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ |
| 877 | #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ |
877 | #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ |
| 878 | #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ |
878 | #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ |
| 879 | #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ |
879 | #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ |
| 880 | #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ |
880 | #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ |
| 881 | #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ |
881 | #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ |
| 882 | #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ |
882 | #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ |
| 883 | #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ |
883 | #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ |
| 884 | #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ |
884 | #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ |
| 885 | #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ |
885 | #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ |
| 886 | #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ |
886 | /** |
| 887 | /** |
887 | * @} |
| 888 | * @} |
888 | */ |
| 889 | */ |
889 | |
| 890 | 890 | /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length |
|
| 891 | /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length |
891 | * @{ |
| 892 | * @{ |
892 | */ |
| 893 | */ |
893 | #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ |
| 894 | #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ |
894 | #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ |
| 895 | #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ |
895 | #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ |
| 896 | #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ |
896 | #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ |
| 897 | #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ |
897 | #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ |
| 898 | #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ |
898 | #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ |
| 899 | #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ |
899 | #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ |
| 900 | #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ |
900 | #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ |
| 901 | #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ |
901 | #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ |
| 902 | #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ |
902 | #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ |
| 903 | #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ |
903 | #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ |
| 904 | #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ |
904 | #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ |
| 905 | #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ |
905 | #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ |
| 906 | #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ |
906 | #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ |
| 907 | #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ |
907 | #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ |
| 908 | #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ |
908 | #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ |
| 909 | #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ |
909 | #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ |
| 910 | #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ |
910 | #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ |
| 911 | #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ |
911 | /** |
| 912 | /** |
912 | * @} |
| 913 | * @} |
913 | */ |
| 914 | */ |
914 | |
| 915 | 915 | ||
| 916 | 916 | ||
| 917 | /** |
917 | /** |
| 918 | * @} |
918 | * @} |
| 919 | */ |
919 | */ |
| 920 | 920 | ||
| 921 | /* Exported macro ------------------------------------------------------------*/ |
921 | /* Exported macro ------------------------------------------------------------*/ |
| 922 | /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros |
922 | /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros |
| 923 | * @{ |
923 | * @{ |
| 924 | */ |
924 | */ |
| 925 | 925 | ||
| 926 | /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros |
926 | /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros |
| 927 | * @{ |
927 | * @{ |
| 928 | */ |
928 | */ |
| 929 | /** |
929 | /** |
| 930 | * @brief Write a value in TIM register. |
930 | * @brief Write a value in TIM register. |
| 931 | * @param __INSTANCE__ TIM Instance |
931 | * @param __INSTANCE__ TIM Instance |
| 932 | * @param __REG__ Register to be written |
932 | * @param __REG__ Register to be written |
| 933 | * @param __VALUE__ Value to be written in the register |
933 | * @param __VALUE__ Value to be written in the register |
| 934 | * @retval None |
934 | * @retval None |
| 935 | */ |
935 | */ |
| 936 | #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) |
936 | #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) |
| 937 | 937 | ||
| 938 | /** |
938 | /** |
| 939 | * @brief Read a value in TIM register. |
939 | * @brief Read a value in TIM register. |
| 940 | * @param __INSTANCE__ TIM Instance |
940 | * @param __INSTANCE__ TIM Instance |
| 941 | * @param __REG__ Register to be read |
941 | * @param __REG__ Register to be read |
| 942 | * @retval Register value |
942 | * @retval Register value |
| 943 | */ |
943 | */ |
| 944 | #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) |
944 | #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) |
| 945 | /** |
945 | /** |
| 946 | * @} |
946 | * @} |
| 947 | */ |
947 | */ |
| 948 | 948 | ||
| 949 | /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros |
949 | /** |
| 950 | * @{ |
950 | * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. |
| 951 | */ |
951 | * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); |
| 952 | 952 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
|
| 953 | /** |
953 | * @param __CKD__ This parameter can be one of the following values: |
| 954 | * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. |
954 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
| 955 | * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); |
955 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
| 956 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
956 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
| 957 | * @param __CKD__ This parameter can be one of the following values: |
957 | * @param __DT__ deadtime duration (in ns) |
| 958 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
958 | * @retval DTG[0:7] |
| 959 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
959 | */ |
| 960 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
960 | #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ |
| 961 | * @param __DT__ deadtime duration (in ns) |
961 | ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ |
| 962 | * @retval DTG[0:7] |
962 | (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ |
| 963 | */ |
963 | (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ |
| 964 | #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ |
964 | (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ |
| 965 | ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ |
965 | (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ |
| 966 | (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ |
966 | (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ |
| 967 | (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ |
967 | (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ |
| 968 | (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ |
968 | (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ |
| 969 | (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ |
969 | (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ |
| 970 | (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ |
970 | (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ |
| 971 | (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ |
971 | (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ |
| 972 | (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ |
972 | 0U) |
| 973 | (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? \ |
973 | |
| 974 | (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), \ |
974 | /** |
| 975 | (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ |
975 | * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. |
| 976 | 0U) |
976 | * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); |
| 977 | 977 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
|
| 978 | /** |
978 | * @param __CNTCLK__ counter clock frequency (in Hz) |
| 979 | * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. |
979 | * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) |
| 980 | * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); |
980 | */ |
| 981 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
981 | #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ |
| 982 | * @param __CNTCLK__ counter clock frequency (in Hz) |
982 | (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U) |
| 983 | * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) |
983 | |
| 984 | */ |
984 | /** |
| 985 | #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ |
985 | * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. |
| 986 | (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) |
986 | * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); |
| 987 | 987 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
|
| 988 | /** |
988 | * @param __PSC__ prescaler |
| 989 | * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. |
989 | * @param __FREQ__ output signal frequency (in Hz) |
| 990 | * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); |
990 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
| 991 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
991 | */ |
| 992 | * @param __PSC__ prescaler |
992 | #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ |
| 993 | * @param __FREQ__ output signal frequency (in Hz) |
993 | ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) |
| 994 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
994 | |
| 995 | */ |
995 | /** |
| 996 | #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ |
996 | * @brief HELPER macro calculating the compare value required to achieve the required timer output compare |
| 997 | ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) |
997 | * active/inactive delay. |
| 998 | 998 | * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); |
|
| 999 | /** |
999 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
| 1000 | * @brief HELPER macro calculating the compare value required to achieve the required timer output compare |
1000 | * @param __PSC__ prescaler |
| 1001 | * active/inactive delay. |
1001 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
| 1002 | * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); |
1002 | * @retval Compare value (between Min_Data=0 and Max_Data=65535) |
| 1003 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
1003 | */ |
| 1004 | * @param __PSC__ prescaler |
1004 | #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ |
| 1005 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
1005 | ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ |
| 1006 | * @retval Compare value (between Min_Data=0 and Max_Data=65535) |
1006 | / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) |
| 1007 | */ |
1007 | |
| 1008 | #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ |
1008 | /** |
| 1009 | ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ |
1009 | * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration |
| 1010 | / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) |
1010 | * (when the timer operates in one pulse mode). |
| 1011 | 1011 | * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); |
|
| 1012 | /** |
1012 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
| 1013 | * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration |
1013 | * @param __PSC__ prescaler |
| 1014 | * (when the timer operates in one pulse mode). |
1014 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
| 1015 | * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); |
1015 | * @param __PULSE__ pulse duration (in us) |
| 1016 | * @param __TIMCLK__ timer input clock frequency (in Hz) |
1016 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
| 1017 | * @param __PSC__ prescaler |
1017 | */ |
| 1018 | * @param __DELAY__ timer output compare active/inactive delay (in us) |
1018 | #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ |
| 1019 | * @param __PULSE__ pulse duration (in us) |
1019 | ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ |
| 1020 | * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) |
1020 | + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) |
| 1021 | */ |
1021 | |
| 1022 | #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ |
1022 | /** |
| 1023 | ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ |
1023 | * @brief HELPER macro retrieving the ratio of the input capture prescaler |
| 1024 | + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) |
1024 | * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); |
| 1025 | 1025 | * @param __ICPSC__ This parameter can be one of the following values: |
|
| 1026 | /** |
1026 | * @arg @ref LL_TIM_ICPSC_DIV1 |
| 1027 | * @brief HELPER macro retrieving the ratio of the input capture prescaler |
1027 | * @arg @ref LL_TIM_ICPSC_DIV2 |
| 1028 | * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); |
1028 | * @arg @ref LL_TIM_ICPSC_DIV4 |
| 1029 | * @param __ICPSC__ This parameter can be one of the following values: |
1029 | * @arg @ref LL_TIM_ICPSC_DIV8 |
| 1030 | * @arg @ref LL_TIM_ICPSC_DIV1 |
1030 | * @retval Input capture prescaler ratio (1, 2, 4 or 8) |
| 1031 | * @arg @ref LL_TIM_ICPSC_DIV2 |
1031 | */ |
| 1032 | * @arg @ref LL_TIM_ICPSC_DIV4 |
1032 | #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ |
| 1033 | * @arg @ref LL_TIM_ICPSC_DIV8 |
1033 | ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) |
| 1034 | * @retval Input capture prescaler ratio (1, 2, 4 or 8) |
1034 | |
| 1035 | */ |
1035 | |
| 1036 | #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ |
1036 | /** |
| 1037 | ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) |
1037 | * @} |
| 1038 | 1038 | */ |
|
| 1039 | 1039 | ||
| 1040 | /** |
1040 | /* Exported functions --------------------------------------------------------*/ |
| 1041 | * @} |
1041 | /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions |
| 1042 | */ |
1042 | * @{ |
| 1043 | 1043 | */ |
|
| 1044 | 1044 | ||
| 1045 | /** |
1045 | /** @defgroup TIM_LL_EF_Time_Base Time Base configuration |
| 1046 | * @} |
1046 | * @{ |
| 1047 | */ |
1047 | */ |
| 1048 | 1048 | /** |
|
| 1049 | /* Exported functions --------------------------------------------------------*/ |
1049 | * @brief Enable timer counter. |
| 1050 | /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions |
1050 | * @rmtoll CR1 CEN LL_TIM_EnableCounter |
| 1051 | * @{ |
1051 | * @param TIMx Timer instance |
| 1052 | */ |
1052 | * @retval None |
| 1053 | 1053 | */ |
|
| 1054 | /** @defgroup TIM_LL_EF_Time_Base Time Base configuration |
1054 | __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) |
| 1055 | * @{ |
1055 | { |
| 1056 | */ |
1056 | SET_BIT(TIMx->CR1, TIM_CR1_CEN); |
| 1057 | /** |
1057 | } |
| 1058 | * @brief Enable timer counter. |
1058 | |
| 1059 | * @rmtoll CR1 CEN LL_TIM_EnableCounter |
1059 | /** |
| 1060 | * @param TIMx Timer instance |
1060 | * @brief Disable timer counter. |
| 1061 | * @retval None |
1061 | * @rmtoll CR1 CEN LL_TIM_DisableCounter |
| 1062 | */ |
1062 | * @param TIMx Timer instance |
| 1063 | __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) |
1063 | * @retval None |
| 1064 | { |
1064 | */ |
| 1065 | SET_BIT(TIMx->CR1, TIM_CR1_CEN); |
1065 | __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) |
| 1066 | } |
1066 | { |
| 1067 | 1067 | CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); |
|
| 1068 | /** |
1068 | } |
| 1069 | * @brief Disable timer counter. |
1069 | |
| 1070 | * @rmtoll CR1 CEN LL_TIM_DisableCounter |
1070 | /** |
| 1071 | * @param TIMx Timer instance |
1071 | * @brief Indicates whether the timer counter is enabled. |
| 1072 | * @retval None |
1072 | * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter |
| 1073 | */ |
1073 | * @param TIMx Timer instance |
| 1074 | __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) |
1074 | * @retval State of bit (1 or 0). |
| 1075 | { |
1075 | */ |
| 1076 | CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); |
1076 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx) |
| 1077 | } |
1077 | { |
| 1078 | 1078 | return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); |
|
| 1079 | /** |
1079 | } |
| 1080 | * @brief Indicates whether the timer counter is enabled. |
1080 | |
| 1081 | * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter |
1081 | /** |
| 1082 | * @param TIMx Timer instance |
1082 | * @brief Enable update event generation. |
| 1083 | * @retval State of bit (1 or 0). |
1083 | * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent |
| 1084 | */ |
1084 | * @param TIMx Timer instance |
| 1085 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) |
1085 | * @retval None |
| 1086 | { |
1086 | */ |
| 1087 | return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); |
1087 | __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) |
| 1088 | } |
1088 | { |
| 1089 | 1089 | CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); |
|
| 1090 | /** |
1090 | } |
| 1091 | * @brief Enable update event generation. |
1091 | |
| 1092 | * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent |
1092 | /** |
| 1093 | * @param TIMx Timer instance |
1093 | * @brief Disable update event generation. |
| 1094 | * @retval None |
1094 | * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent |
| 1095 | */ |
1095 | * @param TIMx Timer instance |
| 1096 | __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) |
1096 | * @retval None |
| 1097 | { |
1097 | */ |
| 1098 | CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); |
1098 | __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) |
| 1099 | } |
1099 | { |
| 1100 | 1100 | SET_BIT(TIMx->CR1, TIM_CR1_UDIS); |
|
| 1101 | /** |
1101 | } |
| 1102 | * @brief Disable update event generation. |
1102 | |
| 1103 | * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent |
1103 | /** |
| 1104 | * @param TIMx Timer instance |
1104 | * @brief Indicates whether update event generation is enabled. |
| 1105 | * @retval None |
1105 | * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent |
| 1106 | */ |
1106 | * @param TIMx Timer instance |
| 1107 | __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) |
1107 | * @retval Inverted state of bit (0 or 1). |
| 1108 | { |
1108 | */ |
| 1109 | SET_BIT(TIMx->CR1, TIM_CR1_UDIS); |
1109 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx) |
| 1110 | } |
1110 | { |
| 1111 | 1111 | return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); |
|
| 1112 | /** |
1112 | } |
| 1113 | * @brief Indicates whether update event generation is enabled. |
1113 | |
| 1114 | * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent |
1114 | /** |
| 1115 | * @param TIMx Timer instance |
1115 | * @brief Set update event source |
| 1116 | * @retval Inverted state of bit (0 or 1). |
1116 | * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events |
| 1117 | */ |
1117 | * generate an update interrupt or DMA request if enabled: |
| 1118 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) |
1118 | * - Counter overflow/underflow |
| 1119 | { |
1119 | * - Setting the UG bit |
| 1120 | return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); |
1120 | * - Update generation through the slave mode controller |
| 1121 | } |
1121 | * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter |
| 1122 | 1122 | * overflow/underflow generates an update interrupt or DMA request if enabled. |
|
| 1123 | /** |
1123 | * @rmtoll CR1 URS LL_TIM_SetUpdateSource |
| 1124 | * @brief Set update event source |
1124 | * @param TIMx Timer instance |
| 1125 | * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events |
1125 | * @param UpdateSource This parameter can be one of the following values: |
| 1126 | * generate an update interrupt or DMA request if enabled: |
1126 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
| 1127 | * - Counter overflow/underflow |
1127 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
| 1128 | * - Setting the UG bit |
1128 | * @retval None |
| 1129 | * - Update generation through the slave mode controller |
1129 | */ |
| 1130 | * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter |
1130 | __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) |
| 1131 | * overflow/underflow generates an update interrupt or DMA request if enabled. |
1131 | { |
| 1132 | * @rmtoll CR1 URS LL_TIM_SetUpdateSource |
1132 | MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); |
| 1133 | * @param TIMx Timer instance |
1133 | } |
| 1134 | * @param UpdateSource This parameter can be one of the following values: |
1134 | |
| 1135 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
1135 | /** |
| 1136 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
1136 | * @brief Get actual event update source |
| 1137 | * @retval None |
1137 | * @rmtoll CR1 URS LL_TIM_GetUpdateSource |
| 1138 | */ |
1138 | * @param TIMx Timer instance |
| 1139 | __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) |
1139 | * @retval Returned value can be one of the following values: |
| 1140 | { |
1140 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
| 1141 | MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); |
1141 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
| 1142 | } |
1142 | */ |
| 1143 | 1143 | __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx) |
|
| 1144 | /** |
1144 | { |
| 1145 | * @brief Get actual event update source |
1145 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); |
| 1146 | * @rmtoll CR1 URS LL_TIM_GetUpdateSource |
1146 | } |
| 1147 | * @param TIMx Timer instance |
1147 | |
| 1148 | * @retval Returned value can be one of the following values: |
1148 | /** |
| 1149 | * @arg @ref LL_TIM_UPDATESOURCE_REGULAR |
1149 | * @brief Set one pulse mode (one shot v.s. repetitive). |
| 1150 | * @arg @ref LL_TIM_UPDATESOURCE_COUNTER |
1150 | * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode |
| 1151 | */ |
1151 | * @param TIMx Timer instance |
| 1152 | __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) |
1152 | * @param OnePulseMode This parameter can be one of the following values: |
| 1153 | { |
1153 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
| 1154 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); |
1154 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
| 1155 | } |
1155 | * @retval None |
| 1156 | 1156 | */ |
|
| 1157 | /** |
1157 | __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) |
| 1158 | * @brief Set one pulse mode (one shot v.s. repetitive). |
1158 | { |
| 1159 | * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode |
1159 | MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); |
| 1160 | * @param TIMx Timer instance |
1160 | } |
| 1161 | * @param OnePulseMode This parameter can be one of the following values: |
1161 | |
| 1162 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
1162 | /** |
| 1163 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
1163 | * @brief Get actual one pulse mode. |
| 1164 | * @retval None |
1164 | * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode |
| 1165 | */ |
1165 | * @param TIMx Timer instance |
| 1166 | __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) |
1166 | * @retval Returned value can be one of the following values: |
| 1167 | { |
1167 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
| 1168 | MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); |
1168 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
| 1169 | } |
1169 | */ |
| 1170 | 1170 | __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx) |
|
| 1171 | /** |
1171 | { |
| 1172 | * @brief Get actual one pulse mode. |
1172 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); |
| 1173 | * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode |
1173 | } |
| 1174 | * @param TIMx Timer instance |
1174 | |
| 1175 | * @retval Returned value can be one of the following values: |
1175 | /** |
| 1176 | * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE |
1176 | * @brief Set the timer counter counting mode. |
| 1177 | * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE |
1177 | * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
| 1178 | */ |
1178 | * check whether or not the counter mode selection feature is supported |
| 1179 | __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) |
1179 | * by a timer instance. |
| 1180 | { |
1180 | * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) |
| 1181 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); |
1181 | * requires a timer reset to avoid unexpected direction |
| 1182 | } |
1182 | * due to DIR bit readonly in center aligned mode. |
| 1183 | 1183 | * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n |
|
| 1184 | /** |
1184 | * CR1 CMS LL_TIM_SetCounterMode |
| 1185 | * @brief Set the timer counter counting mode. |
1185 | * @param TIMx Timer instance |
| 1186 | * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
1186 | * @param CounterMode This parameter can be one of the following values: |
| 1187 | * check whether or not the counter mode selection feature is supported |
1187 | * @arg @ref LL_TIM_COUNTERMODE_UP |
| 1188 | * by a timer instance. |
1188 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
| 1189 | * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) |
1189 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
| 1190 | * requires a timer reset to avoid unexpected direction |
1190 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
| 1191 | * due to DIR bit readonly in center aligned mode. |
1191 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
| 1192 | * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n |
1192 | * @retval None |
| 1193 | * CR1 CMS LL_TIM_SetCounterMode |
1193 | */ |
| 1194 | * @param TIMx Timer instance |
1194 | __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) |
| 1195 | * @param CounterMode This parameter can be one of the following values: |
1195 | { |
| 1196 | * @arg @ref LL_TIM_COUNTERMODE_UP |
1196 | MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); |
| 1197 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
1197 | } |
| 1198 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
1198 | |
| 1199 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
1199 | /** |
| 1200 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
1200 | * @brief Get actual counter mode. |
| 1201 | * @retval None |
1201 | * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
| 1202 | */ |
1202 | * check whether or not the counter mode selection feature is supported |
| 1203 | __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) |
1203 | * by a timer instance. |
| 1204 | { |
1204 | * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n |
| 1205 | MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); |
1205 | * CR1 CMS LL_TIM_GetCounterMode |
| 1206 | } |
1206 | * @param TIMx Timer instance |
| 1207 | 1207 | * @retval Returned value can be one of the following values: |
|
| 1208 | /** |
1208 | * @arg @ref LL_TIM_COUNTERMODE_UP |
| 1209 | * @brief Get actual counter mode. |
1209 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
| 1210 | * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to |
1210 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
| 1211 | * check whether or not the counter mode selection feature is supported |
1211 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
| 1212 | * by a timer instance. |
1212 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
| 1213 | * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n |
1213 | */ |
| 1214 | * CR1 CMS LL_TIM_GetCounterMode |
1214 | __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx) |
| 1215 | * @param TIMx Timer instance |
1215 | { |
| 1216 | * @retval Returned value can be one of the following values: |
1216 | uint32_t counter_mode; |
| 1217 | * @arg @ref LL_TIM_COUNTERMODE_UP |
1217 | |
| 1218 | * @arg @ref LL_TIM_COUNTERMODE_DOWN |
1218 | counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); |
| 1219 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP |
1219 | |
| 1220 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN |
1220 | if (counter_mode == 0U) |
| 1221 | * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN |
1221 | { |
| 1222 | */ |
1222 | counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
| 1223 | __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) |
1223 | } |
| 1224 | { |
1224 | |
| 1225 | uint32_t counter_mode; |
1225 | return counter_mode; |
| 1226 | 1226 | } |
|
| 1227 | counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS)); |
1227 | |
| 1228 | 1228 | /** |
|
| 1229 | if (counter_mode == 0U) |
1229 | * @brief Enable auto-reload (ARR) preload. |
| 1230 | { |
1230 | * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload |
| 1231 | counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
1231 | * @param TIMx Timer instance |
| 1232 | } |
1232 | * @retval None |
| 1233 | 1233 | */ |
|
| 1234 | return counter_mode; |
1234 | __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) |
| 1235 | } |
1235 | { |
| 1236 | 1236 | SET_BIT(TIMx->CR1, TIM_CR1_ARPE); |
|
| 1237 | /** |
1237 | } |
| 1238 | * @brief Enable auto-reload (ARR) preload. |
1238 | |
| 1239 | * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload |
1239 | /** |
| 1240 | * @param TIMx Timer instance |
1240 | * @brief Disable auto-reload (ARR) preload. |
| 1241 | * @retval None |
1241 | * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload |
| 1242 | */ |
1242 | * @param TIMx Timer instance |
| 1243 | __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) |
1243 | * @retval None |
| 1244 | { |
1244 | */ |
| 1245 | SET_BIT(TIMx->CR1, TIM_CR1_ARPE); |
1245 | __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) |
| 1246 | } |
1246 | { |
| 1247 | 1247 | CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); |
|
| 1248 | /** |
1248 | } |
| 1249 | * @brief Disable auto-reload (ARR) preload. |
1249 | |
| 1250 | * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload |
1250 | /** |
| 1251 | * @param TIMx Timer instance |
1251 | * @brief Indicates whether auto-reload (ARR) preload is enabled. |
| 1252 | * @retval None |
1252 | * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload |
| 1253 | */ |
1253 | * @param TIMx Timer instance |
| 1254 | __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) |
1254 | * @retval State of bit (1 or 0). |
| 1255 | { |
1255 | */ |
| 1256 | CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); |
1256 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx) |
| 1257 | } |
1257 | { |
| 1258 | 1258 | return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); |
|
| 1259 | /** |
1259 | } |
| 1260 | * @brief Indicates whether auto-reload (ARR) preload is enabled. |
1260 | |
| 1261 | * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload |
1261 | /** |
| 1262 | * @param TIMx Timer instance |
1262 | * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators |
| 1263 | * @retval State of bit (1 or 0). |
1263 | * (when supported) and the digital filters. |
| 1264 | */ |
1264 | * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
| 1265 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) |
1265 | * whether or not the clock division feature is supported by the timer |
| 1266 | { |
1266 | * instance. |
| 1267 | return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); |
1267 | * @rmtoll CR1 CKD LL_TIM_SetClockDivision |
| 1268 | } |
1268 | * @param TIMx Timer instance |
| 1269 | 1269 | * @param ClockDivision This parameter can be one of the following values: |
|
| 1270 | /** |
1270 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
| 1271 | * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators |
1271 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
| 1272 | * (when supported) and the digital filters. |
1272 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
| 1273 | * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
1273 | * @retval None |
| 1274 | * whether or not the clock division feature is supported by the timer |
1274 | */ |
| 1275 | * instance. |
1275 | __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) |
| 1276 | * @rmtoll CR1 CKD LL_TIM_SetClockDivision |
1276 | { |
| 1277 | * @param TIMx Timer instance |
1277 | MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); |
| 1278 | * @param ClockDivision This parameter can be one of the following values: |
1278 | } |
| 1279 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
1279 | |
| 1280 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
1280 | /** |
| 1281 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
1281 | * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time |
| 1282 | * @retval None |
1282 | * generators (when supported) and the digital filters. |
| 1283 | */ |
1283 | * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
| 1284 | __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) |
1284 | * whether or not the clock division feature is supported by the timer |
| 1285 | { |
1285 | * instance. |
| 1286 | MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); |
1286 | * @rmtoll CR1 CKD LL_TIM_GetClockDivision |
| 1287 | } |
1287 | * @param TIMx Timer instance |
| 1288 | 1288 | * @retval Returned value can be one of the following values: |
|
| 1289 | /** |
1289 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
| 1290 | * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time |
1290 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
| 1291 | * generators (when supported) and the digital filters. |
1291 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
| 1292 | * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check |
1292 | */ |
| 1293 | * whether or not the clock division feature is supported by the timer |
1293 | __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx) |
| 1294 | * instance. |
1294 | { |
| 1295 | * @rmtoll CR1 CKD LL_TIM_GetClockDivision |
1295 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); |
| 1296 | * @param TIMx Timer instance |
1296 | } |
| 1297 | * @retval Returned value can be one of the following values: |
1297 | |
| 1298 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 |
1298 | /** |
| 1299 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 |
1299 | * @brief Set the counter value. |
| 1300 | * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 |
1300 | * @rmtoll CNT CNT LL_TIM_SetCounter |
| 1301 | */ |
1301 | * @param TIMx Timer instance |
| 1302 | __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) |
1302 | * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF) |
| 1303 | { |
1303 | * @retval None |
| 1304 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); |
1304 | */ |
| 1305 | } |
1305 | __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) |
| 1306 | 1306 | { |
|
| 1307 | /** |
1307 | WRITE_REG(TIMx->CNT, Counter); |
| 1308 | * @brief Set the counter value. |
1308 | } |
| 1309 | * @rmtoll CNT CNT LL_TIM_SetCounter |
1309 | |
| 1310 | * @param TIMx Timer instance |
1310 | /** |
| 1311 | * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF) |
1311 | * @brief Get the counter value. |
| 1312 | * @retval None |
1312 | * @rmtoll CNT CNT LL_TIM_GetCounter |
| 1313 | */ |
1313 | * @param TIMx Timer instance |
| 1314 | __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) |
1314 | * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF) |
| 1315 | { |
1315 | */ |
| 1316 | WRITE_REG(TIMx->CNT, Counter); |
1316 | __STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx) |
| 1317 | } |
1317 | { |
| 1318 | 1318 | return (uint32_t)(READ_REG(TIMx->CNT)); |
|
| 1319 | /** |
1319 | } |
| 1320 | * @brief Get the counter value. |
1320 | |
| 1321 | * @rmtoll CNT CNT LL_TIM_GetCounter |
1321 | /** |
| 1322 | * @param TIMx Timer instance |
1322 | * @brief Get the current direction of the counter |
| 1323 | * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF) |
1323 | * @rmtoll CR1 DIR LL_TIM_GetDirection |
| 1324 | */ |
1324 | * @param TIMx Timer instance |
| 1325 | __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) |
1325 | * @retval Returned value can be one of the following values: |
| 1326 | { |
1326 | * @arg @ref LL_TIM_COUNTERDIRECTION_UP |
| 1327 | return (uint32_t)(READ_REG(TIMx->CNT)); |
1327 | * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN |
| 1328 | } |
1328 | */ |
| 1329 | 1329 | __STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx) |
|
| 1330 | /** |
1330 | { |
| 1331 | * @brief Get the current direction of the counter |
1331 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
| 1332 | * @rmtoll CR1 DIR LL_TIM_GetDirection |
1332 | } |
| 1333 | * @param TIMx Timer instance |
1333 | |
| 1334 | * @retval Returned value can be one of the following values: |
1334 | /** |
| 1335 | * @arg @ref LL_TIM_COUNTERDIRECTION_UP |
1335 | * @brief Set the prescaler value. |
| 1336 | * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN |
1336 | * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). |
| 1337 | */ |
1337 | * @note The prescaler can be changed on the fly as this control register is buffered. The new |
| 1338 | __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) |
1338 | * prescaler ratio is taken into account at the next update event. |
| 1339 | { |
1339 | * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter |
| 1340 | return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); |
1340 | * @rmtoll PSC PSC LL_TIM_SetPrescaler |
| 1341 | } |
1341 | * @param TIMx Timer instance |
| 1342 | 1342 | * @param Prescaler between Min_Data=0 and Max_Data=65535 |
|
| 1343 | /** |
1343 | * @retval None |
| 1344 | * @brief Set the prescaler value. |
1344 | */ |
| 1345 | * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). |
1345 | __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) |
| 1346 | * @note The prescaler can be changed on the fly as this control register is buffered. The new |
1346 | { |
| 1347 | * prescaler ratio is taken into account at the next update event. |
1347 | WRITE_REG(TIMx->PSC, Prescaler); |
| 1348 | * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter |
1348 | } |
| 1349 | * @rmtoll PSC PSC LL_TIM_SetPrescaler |
1349 | |
| 1350 | * @param TIMx Timer instance |
1350 | /** |
| 1351 | * @param Prescaler between Min_Data=0 and Max_Data=65535 |
1351 | * @brief Get the prescaler value. |
| 1352 | * @retval None |
1352 | * @rmtoll PSC PSC LL_TIM_GetPrescaler |
| 1353 | */ |
1353 | * @param TIMx Timer instance |
| 1354 | __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) |
1354 | * @retval Prescaler value between Min_Data=0 and Max_Data=65535 |
| 1355 | { |
1355 | */ |
| 1356 | WRITE_REG(TIMx->PSC, Prescaler); |
1356 | __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx) |
| 1357 | } |
1357 | { |
| 1358 | 1358 | return (uint32_t)(READ_REG(TIMx->PSC)); |
|
| 1359 | /** |
1359 | } |
| 1360 | * @brief Get the prescaler value. |
1360 | |
| 1361 | * @rmtoll PSC PSC LL_TIM_GetPrescaler |
1361 | /** |
| 1362 | * @param TIMx Timer instance |
1362 | * @brief Set the auto-reload value. |
| 1363 | * @retval Prescaler value between Min_Data=0 and Max_Data=65535 |
1363 | * @note The counter is blocked while the auto-reload value is null. |
| 1364 | */ |
1364 | * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter |
| 1365 | __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) |
1365 | * @rmtoll ARR ARR LL_TIM_SetAutoReload |
| 1366 | { |
1366 | * @param TIMx Timer instance |
| 1367 | return (uint32_t)(READ_REG(TIMx->PSC)); |
1367 | * @param AutoReload between Min_Data=0 and Max_Data=65535 |
| 1368 | } |
1368 | * @retval None |
| 1369 | 1369 | */ |
|
| 1370 | /** |
1370 | __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) |
| 1371 | * @brief Set the auto-reload value. |
1371 | { |
| 1372 | * @note The counter is blocked while the auto-reload value is null. |
1372 | WRITE_REG(TIMx->ARR, AutoReload); |
| 1373 | * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter |
1373 | } |
| 1374 | * @rmtoll ARR ARR LL_TIM_SetAutoReload |
1374 | |
| 1375 | * @param TIMx Timer instance |
1375 | /** |
| 1376 | * @param AutoReload between Min_Data=0 and Max_Data=65535 |
1376 | * @brief Get the auto-reload value. |
| 1377 | * @retval None |
1377 | * @rmtoll ARR ARR LL_TIM_GetAutoReload |
| 1378 | */ |
1378 | * @param TIMx Timer instance |
| 1379 | __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) |
1379 | * @retval Auto-reload value |
| 1380 | { |
1380 | */ |
| 1381 | WRITE_REG(TIMx->ARR, AutoReload); |
1381 | __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx) |
| 1382 | } |
1382 | { |
| 1383 | 1383 | return (uint32_t)(READ_REG(TIMx->ARR)); |
|
| 1384 | /** |
1384 | } |
| 1385 | * @brief Get the auto-reload value. |
1385 | |
| 1386 | * @rmtoll ARR ARR LL_TIM_GetAutoReload |
1386 | /** |
| 1387 | * @param TIMx Timer instance |
1387 | * @brief Set the repetition counter value. |
| 1388 | * @retval Auto-reload value |
1388 | * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check |
| 1389 | */ |
1389 | * whether or not a timer instance supports a repetition counter. |
| 1390 | __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) |
1390 | * @rmtoll RCR REP LL_TIM_SetRepetitionCounter |
| 1391 | { |
1391 | * @param TIMx Timer instance |
| 1392 | return (uint32_t)(READ_REG(TIMx->ARR)); |
1392 | * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. |
| 1393 | } |
1393 | * @retval None |
| 1394 | 1394 | */ |
|
| 1395 | /** |
1395 | __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) |
| 1396 | * @brief Set the repetition counter value. |
1396 | { |
| 1397 | * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check |
1397 | WRITE_REG(TIMx->RCR, RepetitionCounter); |
| 1398 | * whether or not a timer instance supports a repetition counter. |
1398 | } |
| 1399 | * @rmtoll RCR REP LL_TIM_SetRepetitionCounter |
1399 | |
| 1400 | * @param TIMx Timer instance |
1400 | /** |
| 1401 | * @param RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer. |
1401 | * @brief Get the repetition counter value. |
| 1402 | * @retval None |
1402 | * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check |
| 1403 | */ |
1403 | * whether or not a timer instance supports a repetition counter. |
| 1404 | __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) |
1404 | * @rmtoll RCR REP LL_TIM_GetRepetitionCounter |
| 1405 | { |
1405 | * @param TIMx Timer instance |
| 1406 | WRITE_REG(TIMx->RCR, RepetitionCounter); |
1406 | * @retval Repetition counter value |
| 1407 | } |
1407 | */ |
| 1408 | 1408 | __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx) |
|
| 1409 | /** |
1409 | { |
| 1410 | * @brief Get the repetition counter value. |
1410 | return (uint32_t)(READ_REG(TIMx->RCR)); |
| 1411 | * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check |
1411 | } |
| 1412 | * whether or not a timer instance supports a repetition counter. |
1412 | |
| 1413 | * @rmtoll RCR REP LL_TIM_GetRepetitionCounter |
1413 | /** |
| 1414 | * @param TIMx Timer instance |
1414 | * @} |
| 1415 | * @retval Repetition counter value |
1415 | */ |
| 1416 | */ |
1416 | |
| 1417 | __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) |
1417 | /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration |
| 1418 | { |
1418 | * @{ |
| 1419 | return (uint32_t)(READ_REG(TIMx->RCR)); |
1419 | */ |
| 1420 | } |
1420 | /** |
| 1421 | 1421 | * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. |
|
| 1422 | /** |
1422 | * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, |
| 1423 | * @} |
1423 | * they are updated only when a commutation event (COM) occurs. |
| 1424 | */ |
1424 | * @note Only on channels that have a complementary output. |
| 1425 | 1425 | * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
|
| 1426 | /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration |
1426 | * whether or not a timer instance is able to generate a commutation event. |
| 1427 | * @{ |
1427 | * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload |
| 1428 | */ |
1428 | * @param TIMx Timer instance |
| 1429 | /** |
1429 | * @retval None |
| 1430 | * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. |
1430 | */ |
| 1431 | * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, |
1431 | __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) |
| 1432 | * they are updated only when a commutation event (COM) occurs. |
1432 | { |
| 1433 | * @note Only on channels that have a complementary output. |
1433 | SET_BIT(TIMx->CR2, TIM_CR2_CCPC); |
| 1434 | * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
1434 | } |
| 1435 | * whether or not a timer instance is able to generate a commutation event. |
1435 | |
| 1436 | * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload |
1436 | /** |
| 1437 | * @param TIMx Timer instance |
1437 | * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. |
| 1438 | * @retval None |
1438 | * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
| 1439 | */ |
1439 | * whether or not a timer instance is able to generate a commutation event. |
| 1440 | __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) |
1440 | * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload |
| 1441 | { |
1441 | * @param TIMx Timer instance |
| 1442 | SET_BIT(TIMx->CR2, TIM_CR2_CCPC); |
1442 | * @retval None |
| 1443 | } |
1443 | */ |
| 1444 | 1444 | __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) |
|
| 1445 | /** |
1445 | { |
| 1446 | * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. |
1446 | CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); |
| 1447 | * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
1447 | } |
| 1448 | * whether or not a timer instance is able to generate a commutation event. |
1448 | |
| 1449 | * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload |
1449 | /** |
| 1450 | * @param TIMx Timer instance |
1450 | * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). |
| 1451 | * @retval None |
1451 | * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
| 1452 | */ |
1452 | * whether or not a timer instance is able to generate a commutation event. |
| 1453 | __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) |
1453 | * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate |
| 1454 | { |
1454 | * @param TIMx Timer instance |
| 1455 | CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); |
1455 | * @param CCUpdateSource This parameter can be one of the following values: |
| 1456 | } |
1456 | * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY |
| 1457 | 1457 | * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI |
|
| 1458 | /** |
1458 | * @retval None |
| 1459 | * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). |
1459 | */ |
| 1460 | * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check |
1460 | __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) |
| 1461 | * whether or not a timer instance is able to generate a commutation event. |
1461 | { |
| 1462 | * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate |
1462 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); |
| 1463 | * @param TIMx Timer instance |
1463 | } |
| 1464 | * @param CCUpdateSource This parameter can be one of the following values: |
1464 | |
| 1465 | * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY |
1465 | /** |
| 1466 | * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI |
1466 | * @brief Set the trigger of the capture/compare DMA request. |
| 1467 | * @retval None |
1467 | * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger |
| 1468 | */ |
1468 | * @param TIMx Timer instance |
| 1469 | __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) |
1469 | * @param DMAReqTrigger This parameter can be one of the following values: |
| 1470 | { |
1470 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
| 1471 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); |
1471 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
| 1472 | } |
1472 | * @retval None |
| 1473 | 1473 | */ |
|
| 1474 | /** |
1474 | __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) |
| 1475 | * @brief Set the trigger of the capture/compare DMA request. |
1475 | { |
| 1476 | * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger |
1476 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); |
| 1477 | * @param TIMx Timer instance |
1477 | } |
| 1478 | * @param DMAReqTrigger This parameter can be one of the following values: |
1478 | |
| 1479 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
1479 | /** |
| 1480 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
1480 | * @brief Get actual trigger of the capture/compare DMA request. |
| 1481 | * @retval None |
1481 | * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger |
| 1482 | */ |
1482 | * @param TIMx Timer instance |
| 1483 | __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) |
1483 | * @retval Returned value can be one of the following values: |
| 1484 | { |
1484 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
| 1485 | MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); |
1485 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
| 1486 | } |
1486 | */ |
| 1487 | 1487 | __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx) |
|
| 1488 | /** |
1488 | { |
| 1489 | * @brief Get actual trigger of the capture/compare DMA request. |
1489 | return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); |
| 1490 | * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger |
1490 | } |
| 1491 | * @param TIMx Timer instance |
1491 | |
| 1492 | * @retval Returned value can be one of the following values: |
1492 | /** |
| 1493 | * @arg @ref LL_TIM_CCDMAREQUEST_CC |
1493 | * @brief Set the lock level to freeze the |
| 1494 | * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE |
1494 | * configuration of several capture/compare parameters. |
| 1495 | */ |
1495 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 1496 | __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) |
1496 | * the lock mechanism is supported by a timer instance. |
| 1497 | { |
1497 | * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel |
| 1498 | return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); |
1498 | * @param TIMx Timer instance |
| 1499 | } |
1499 | * @param LockLevel This parameter can be one of the following values: |
| 1500 | 1500 | * @arg @ref LL_TIM_LOCKLEVEL_OFF |
|
| 1501 | /** |
1501 | * @arg @ref LL_TIM_LOCKLEVEL_1 |
| 1502 | * @brief Set the lock level to freeze the |
1502 | * @arg @ref LL_TIM_LOCKLEVEL_2 |
| 1503 | * configuration of several capture/compare parameters. |
1503 | * @arg @ref LL_TIM_LOCKLEVEL_3 |
| 1504 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
1504 | * @retval None |
| 1505 | * the lock mechanism is supported by a timer instance. |
1505 | */ |
| 1506 | * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel |
1506 | __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) |
| 1507 | * @param TIMx Timer instance |
1507 | { |
| 1508 | * @param LockLevel This parameter can be one of the following values: |
1508 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); |
| 1509 | * @arg @ref LL_TIM_LOCKLEVEL_OFF |
1509 | } |
| 1510 | * @arg @ref LL_TIM_LOCKLEVEL_1 |
1510 | |
| 1511 | * @arg @ref LL_TIM_LOCKLEVEL_2 |
1511 | /** |
| 1512 | * @arg @ref LL_TIM_LOCKLEVEL_3 |
1512 | * @brief Enable capture/compare channels. |
| 1513 | * @retval None |
1513 | * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n |
| 1514 | */ |
1514 | * CCER CC1NE LL_TIM_CC_EnableChannel\n |
| 1515 | __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) |
1515 | * CCER CC2E LL_TIM_CC_EnableChannel\n |
| 1516 | { |
1516 | * CCER CC2NE LL_TIM_CC_EnableChannel\n |
| 1517 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); |
1517 | * CCER CC3E LL_TIM_CC_EnableChannel\n |
| 1518 | } |
1518 | * CCER CC3NE LL_TIM_CC_EnableChannel\n |
| 1519 | 1519 | * CCER CC4E LL_TIM_CC_EnableChannel |
|
| 1520 | /** |
1520 | * @param TIMx Timer instance |
| 1521 | * @brief Enable capture/compare channels. |
1521 | * @param Channels This parameter can be a combination of the following values: |
| 1522 | * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n |
1522 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1523 | * CCER CC1NE LL_TIM_CC_EnableChannel\n |
1523 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| 1524 | * CCER CC2E LL_TIM_CC_EnableChannel\n |
1524 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1525 | * CCER CC2NE LL_TIM_CC_EnableChannel\n |
1525 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| 1526 | * CCER CC3E LL_TIM_CC_EnableChannel\n |
1526 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1527 | * CCER CC3NE LL_TIM_CC_EnableChannel\n |
1527 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| 1528 | * CCER CC4E LL_TIM_CC_EnableChannel |
1528 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1529 | * @param TIMx Timer instance |
1529 | * @retval None |
| 1530 | * @param Channels This parameter can be a combination of the following values: |
1530 | */ |
| 1531 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1531 | __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
| 1532 | * @arg @ref LL_TIM_CHANNEL_CH1N |
1532 | { |
| 1533 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1533 | SET_BIT(TIMx->CCER, Channels); |
| 1534 | * @arg @ref LL_TIM_CHANNEL_CH2N |
1534 | } |
| 1535 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1535 | |
| 1536 | * @arg @ref LL_TIM_CHANNEL_CH3N |
1536 | /** |
| 1537 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1537 | * @brief Disable capture/compare channels. |
| 1538 | * @retval None |
1538 | * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n |
| 1539 | */ |
1539 | * CCER CC1NE LL_TIM_CC_DisableChannel\n |
| 1540 | __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
1540 | * CCER CC2E LL_TIM_CC_DisableChannel\n |
| 1541 | { |
1541 | * CCER CC2NE LL_TIM_CC_DisableChannel\n |
| 1542 | SET_BIT(TIMx->CCER, Channels); |
1542 | * CCER CC3E LL_TIM_CC_DisableChannel\n |
| 1543 | } |
1543 | * CCER CC3NE LL_TIM_CC_DisableChannel\n |
| 1544 | 1544 | * CCER CC4E LL_TIM_CC_DisableChannel |
|
| 1545 | /** |
1545 | * @param TIMx Timer instance |
| 1546 | * @brief Disable capture/compare channels. |
1546 | * @param Channels This parameter can be a combination of the following values: |
| 1547 | * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n |
1547 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1548 | * CCER CC1NE LL_TIM_CC_DisableChannel\n |
1548 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| 1549 | * CCER CC2E LL_TIM_CC_DisableChannel\n |
1549 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1550 | * CCER CC2NE LL_TIM_CC_DisableChannel\n |
1550 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| 1551 | * CCER CC3E LL_TIM_CC_DisableChannel\n |
1551 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1552 | * CCER CC3NE LL_TIM_CC_DisableChannel\n |
1552 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| 1553 | * CCER CC4E LL_TIM_CC_DisableChannel |
1553 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1554 | * @param TIMx Timer instance |
1554 | * @retval None |
| 1555 | * @param Channels This parameter can be a combination of the following values: |
1555 | */ |
| 1556 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1556 | __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
| 1557 | * @arg @ref LL_TIM_CHANNEL_CH1N |
1557 | { |
| 1558 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1558 | CLEAR_BIT(TIMx->CCER, Channels); |
| 1559 | * @arg @ref LL_TIM_CHANNEL_CH2N |
1559 | } |
| 1560 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1560 | |
| 1561 | * @arg @ref LL_TIM_CHANNEL_CH3N |
1561 | /** |
| 1562 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1562 | * @brief Indicate whether channel(s) is(are) enabled. |
| 1563 | * @retval None |
1563 | * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n |
| 1564 | */ |
1564 | * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n |
| 1565 | __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
1565 | * CCER CC2E LL_TIM_CC_IsEnabledChannel\n |
| 1566 | { |
1566 | * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n |
| 1567 | CLEAR_BIT(TIMx->CCER, Channels); |
1567 | * CCER CC3E LL_TIM_CC_IsEnabledChannel\n |
| 1568 | } |
1568 | * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n |
| 1569 | 1569 | * CCER CC4E LL_TIM_CC_IsEnabledChannel |
|
| 1570 | /** |
1570 | * @param TIMx Timer instance |
| 1571 | * @brief Indicate whether channel(s) is(are) enabled. |
1571 | * @param Channels This parameter can be a combination of the following values: |
| 1572 | * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n |
1572 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1573 | * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n |
1573 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| 1574 | * CCER CC2E LL_TIM_CC_IsEnabledChannel\n |
1574 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1575 | * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n |
1575 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| 1576 | * CCER CC3E LL_TIM_CC_IsEnabledChannel\n |
1576 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1577 | * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n |
1577 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| 1578 | * CCER CC4E LL_TIM_CC_IsEnabledChannel |
1578 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1579 | * @param TIMx Timer instance |
1579 | * @retval State of bit (1 or 0). |
| 1580 | * @param Channels This parameter can be a combination of the following values: |
1580 | */ |
| 1581 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1581 | __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) |
| 1582 | * @arg @ref LL_TIM_CHANNEL_CH1N |
1582 | { |
| 1583 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1583 | return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); |
| 1584 | * @arg @ref LL_TIM_CHANNEL_CH2N |
1584 | } |
| 1585 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1585 | |
| 1586 | * @arg @ref LL_TIM_CHANNEL_CH3N |
1586 | /** |
| 1587 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1587 | * @} |
| 1588 | * @retval State of bit (1 or 0). |
1588 | */ |
| 1589 | */ |
1589 | |
| 1590 | __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) |
1590 | /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration |
| 1591 | { |
1591 | * @{ |
| 1592 | return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); |
1592 | */ |
| 1593 | } |
1593 | /** |
| 1594 | 1594 | * @brief Configure an output channel. |
|
| 1595 | /** |
1595 | * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n |
| 1596 | * @} |
1596 | * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n |
| 1597 | */ |
1597 | * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n |
| 1598 | 1598 | * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n |
|
| 1599 | /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration |
1599 | * CCER CC1P LL_TIM_OC_ConfigOutput\n |
| 1600 | * @{ |
1600 | * CCER CC2P LL_TIM_OC_ConfigOutput\n |
| 1601 | */ |
1601 | * CCER CC3P LL_TIM_OC_ConfigOutput\n |
| 1602 | /** |
1602 | * CCER CC4P LL_TIM_OC_ConfigOutput\n |
| 1603 | * @brief Configure an output channel. |
1603 | * CR2 OIS1 LL_TIM_OC_ConfigOutput\n |
| 1604 | * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n |
1604 | * CR2 OIS2 LL_TIM_OC_ConfigOutput\n |
| 1605 | * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n |
1605 | * CR2 OIS3 LL_TIM_OC_ConfigOutput\n |
| 1606 | * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n |
1606 | * CR2 OIS4 LL_TIM_OC_ConfigOutput |
| 1607 | * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n |
1607 | * @param TIMx Timer instance |
| 1608 | * CCER CC1P LL_TIM_OC_ConfigOutput\n |
1608 | * @param Channel This parameter can be one of the following values: |
| 1609 | * CCER CC2P LL_TIM_OC_ConfigOutput\n |
1609 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1610 | * CCER CC3P LL_TIM_OC_ConfigOutput\n |
1610 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1611 | * CCER CC4P LL_TIM_OC_ConfigOutput\n |
1611 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1612 | * CR2 OIS1 LL_TIM_OC_ConfigOutput\n |
1612 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1613 | * CR2 OIS2 LL_TIM_OC_ConfigOutput\n |
1613 | * @param Configuration This parameter must be a combination of all the following values: |
| 1614 | * CR2 OIS3 LL_TIM_OC_ConfigOutput\n |
1614 | * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW |
| 1615 | * CR2 OIS4 LL_TIM_OC_ConfigOutput |
1615 | * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH |
| 1616 | * @param TIMx Timer instance |
1616 | * @retval None |
| 1617 | * @param Channel This parameter can be one of the following values: |
1617 | */ |
| 1618 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1618 | __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
| 1619 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1619 | { |
| 1620 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1620 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1621 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1621 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1622 | * @param Configuration This parameter must be a combination of all the following values: |
1622 | CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); |
| 1623 | * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW |
1623 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), |
| 1624 | * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH |
1624 | (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); |
| 1625 | * @retval None |
1625 | MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), |
| 1626 | */ |
1626 | (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); |
| 1627 | __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
1627 | } |
| 1628 | { |
1628 | |
| 1629 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1629 | /** |
| 1630 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1630 | * @brief Define the behavior of the output reference signal OCxREF from which |
| 1631 | CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); |
1631 | * OCx and OCxN (when relevant) are derived. |
| 1632 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), |
1632 | * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n |
| 1633 | (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); |
1633 | * CCMR1 OC2M LL_TIM_OC_SetMode\n |
| 1634 | MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), |
1634 | * CCMR2 OC3M LL_TIM_OC_SetMode\n |
| 1635 | (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); |
1635 | * CCMR2 OC4M LL_TIM_OC_SetMode |
| 1636 | } |
1636 | * @param TIMx Timer instance |
| 1637 | 1637 | * @param Channel This parameter can be one of the following values: |
|
| 1638 | /** |
1638 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1639 | * @brief Define the behavior of the output reference signal OCxREF from which |
1639 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1640 | * OCx and OCxN (when relevant) are derived. |
1640 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1641 | * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n |
1641 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1642 | * CCMR1 OC2M LL_TIM_OC_SetMode\n |
1642 | * @param Mode This parameter can be one of the following values: |
| 1643 | * CCMR2 OC3M LL_TIM_OC_SetMode\n |
1643 | * @arg @ref LL_TIM_OCMODE_FROZEN |
| 1644 | * CCMR2 OC4M LL_TIM_OC_SetMode |
1644 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
| 1645 | * @param TIMx Timer instance |
1645 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
| 1646 | * @param Channel This parameter can be one of the following values: |
1646 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
| 1647 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1647 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
| 1648 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1648 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
| 1649 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1649 | * @arg @ref LL_TIM_OCMODE_PWM1 |
| 1650 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1650 | * @arg @ref LL_TIM_OCMODE_PWM2 |
| 1651 | * @param Mode This parameter can be one of the following values: |
1651 | * @retval None |
| 1652 | * @arg @ref LL_TIM_OCMODE_FROZEN |
1652 | */ |
| 1653 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
1653 | __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) |
| 1654 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
1654 | { |
| 1655 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
1655 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1656 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
1656 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1657 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
1657 | MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); |
| 1658 | * @arg @ref LL_TIM_OCMODE_PWM1 |
1658 | } |
| 1659 | * @arg @ref LL_TIM_OCMODE_PWM2 |
1659 | |
| 1660 | * @retval None |
1660 | /** |
| 1661 | */ |
1661 | * @brief Get the output compare mode of an output channel. |
| 1662 | __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) |
1662 | * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n |
| 1663 | { |
1663 | * CCMR1 OC2M LL_TIM_OC_GetMode\n |
| 1664 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1664 | * CCMR2 OC3M LL_TIM_OC_GetMode\n |
| 1665 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1665 | * CCMR2 OC4M LL_TIM_OC_GetMode |
| 1666 | MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); |
1666 | * @param TIMx Timer instance |
| 1667 | } |
1667 | * @param Channel This parameter can be one of the following values: |
| 1668 | 1668 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1669 | /** |
1669 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1670 | * @brief Get the output compare mode of an output channel. |
1670 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1671 | * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n |
1671 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1672 | * CCMR1 OC2M LL_TIM_OC_GetMode\n |
1672 | * @retval Returned value can be one of the following values: |
| 1673 | * CCMR2 OC3M LL_TIM_OC_GetMode\n |
1673 | * @arg @ref LL_TIM_OCMODE_FROZEN |
| 1674 | * CCMR2 OC4M LL_TIM_OC_GetMode |
1674 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
| 1675 | * @param TIMx Timer instance |
1675 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
| 1676 | * @param Channel This parameter can be one of the following values: |
1676 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
| 1677 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1677 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
| 1678 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1678 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
| 1679 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1679 | * @arg @ref LL_TIM_OCMODE_PWM1 |
| 1680 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1680 | * @arg @ref LL_TIM_OCMODE_PWM2 |
| 1681 | * @retval Returned value can be one of the following values: |
1681 | */ |
| 1682 | * @arg @ref LL_TIM_OCMODE_FROZEN |
1682 | __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1683 | * @arg @ref LL_TIM_OCMODE_ACTIVE |
1683 | { |
| 1684 | * @arg @ref LL_TIM_OCMODE_INACTIVE |
1684 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1685 | * @arg @ref LL_TIM_OCMODE_TOGGLE |
1685 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1686 | * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE |
1686 | return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); |
| 1687 | * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE |
1687 | } |
| 1688 | * @arg @ref LL_TIM_OCMODE_PWM1 |
1688 | |
| 1689 | * @arg @ref LL_TIM_OCMODE_PWM2 |
1689 | /** |
| 1690 | */ |
1690 | * @brief Set the polarity of an output channel. |
| 1691 | __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) |
1691 | * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n |
| 1692 | { |
1692 | * CCER CC1NP LL_TIM_OC_SetPolarity\n |
| 1693 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1693 | * CCER CC2P LL_TIM_OC_SetPolarity\n |
| 1694 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1694 | * CCER CC2NP LL_TIM_OC_SetPolarity\n |
| 1695 | return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); |
1695 | * CCER CC3P LL_TIM_OC_SetPolarity\n |
| 1696 | } |
1696 | * CCER CC3NP LL_TIM_OC_SetPolarity\n |
| 1697 | 1697 | * CCER CC4P LL_TIM_OC_SetPolarity |
|
| 1698 | /** |
1698 | * @param TIMx Timer instance |
| 1699 | * @brief Set the polarity of an output channel. |
1699 | * @param Channel This parameter can be one of the following values: |
| 1700 | * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n |
1700 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1701 | * CCER CC1NP LL_TIM_OC_SetPolarity\n |
1701 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| 1702 | * CCER CC2P LL_TIM_OC_SetPolarity\n |
1702 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1703 | * CCER CC2NP LL_TIM_OC_SetPolarity\n |
1703 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| 1704 | * CCER CC3P LL_TIM_OC_SetPolarity\n |
1704 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1705 | * CCER CC3NP LL_TIM_OC_SetPolarity\n |
1705 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| 1706 | * CCER CC4P LL_TIM_OC_SetPolarity |
1706 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1707 | * @param TIMx Timer instance |
1707 | * @param Polarity This parameter can be one of the following values: |
| 1708 | * @param Channel This parameter can be one of the following values: |
1708 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
| 1709 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1709 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
| 1710 | * @arg @ref LL_TIM_CHANNEL_CH1N |
1710 | * @retval None |
| 1711 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1711 | */ |
| 1712 | * @arg @ref LL_TIM_CHANNEL_CH2N |
1712 | __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) |
| 1713 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1713 | { |
| 1714 | * @arg @ref LL_TIM_CHANNEL_CH3N |
1714 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1715 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1715 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); |
| 1716 | * @param Polarity This parameter can be one of the following values: |
1716 | } |
| 1717 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
1717 | |
| 1718 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
1718 | /** |
| 1719 | * @retval None |
1719 | * @brief Get the polarity of an output channel. |
| 1720 | */ |
1720 | * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n |
| 1721 | __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) |
1721 | * CCER CC1NP LL_TIM_OC_GetPolarity\n |
| 1722 | { |
1722 | * CCER CC2P LL_TIM_OC_GetPolarity\n |
| 1723 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1723 | * CCER CC2NP LL_TIM_OC_GetPolarity\n |
| 1724 | MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); |
1724 | * CCER CC3P LL_TIM_OC_GetPolarity\n |
| 1725 | } |
1725 | * CCER CC3NP LL_TIM_OC_GetPolarity\n |
| 1726 | 1726 | * CCER CC4P LL_TIM_OC_GetPolarity |
|
| 1727 | /** |
1727 | * @param TIMx Timer instance |
| 1728 | * @brief Get the polarity of an output channel. |
1728 | * @param Channel This parameter can be one of the following values: |
| 1729 | * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n |
1729 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1730 | * CCER CC1NP LL_TIM_OC_GetPolarity\n |
1730 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| 1731 | * CCER CC2P LL_TIM_OC_GetPolarity\n |
1731 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1732 | * CCER CC2NP LL_TIM_OC_GetPolarity\n |
1732 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| 1733 | * CCER CC3P LL_TIM_OC_GetPolarity\n |
1733 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1734 | * CCER CC3NP LL_TIM_OC_GetPolarity\n |
1734 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| 1735 | * CCER CC4P LL_TIM_OC_GetPolarity |
1735 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1736 | * @param TIMx Timer instance |
1736 | * @retval Returned value can be one of the following values: |
| 1737 | * @param Channel This parameter can be one of the following values: |
1737 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
| 1738 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1738 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
| 1739 | * @arg @ref LL_TIM_CHANNEL_CH1N |
1739 | */ |
| 1740 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1740 | __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1741 | * @arg @ref LL_TIM_CHANNEL_CH2N |
1741 | { |
| 1742 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1742 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1743 | * @arg @ref LL_TIM_CHANNEL_CH3N |
1743 | return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); |
| 1744 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1744 | } |
| 1745 | * @retval Returned value can be one of the following values: |
1745 | |
| 1746 | * @arg @ref LL_TIM_OCPOLARITY_HIGH |
1746 | /** |
| 1747 | * @arg @ref LL_TIM_OCPOLARITY_LOW |
1747 | * @brief Set the IDLE state of an output channel |
| 1748 | */ |
1748 | * @note This function is significant only for the timer instances |
| 1749 | __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
1749 | * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) |
| 1750 | { |
1750 | * can be used to check whether or not a timer instance provides |
| 1751 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1751 | * a break input. |
| 1752 | return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); |
1752 | * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n |
| 1753 | } |
1753 | * CR2 OIS1N LL_TIM_OC_SetIdleState\n |
| 1754 | 1754 | * CR2 OIS2 LL_TIM_OC_SetIdleState\n |
|
| 1755 | /** |
1755 | * CR2 OIS2N LL_TIM_OC_SetIdleState\n |
| 1756 | * @brief Set the IDLE state of an output channel |
1756 | * CR2 OIS3 LL_TIM_OC_SetIdleState\n |
| 1757 | * @note This function is significant only for the timer instances |
1757 | * CR2 OIS3N LL_TIM_OC_SetIdleState\n |
| 1758 | * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) |
1758 | * CR2 OIS4 LL_TIM_OC_SetIdleState |
| 1759 | * can be used to check whether or not a timer instance provides |
1759 | * @param TIMx Timer instance |
| 1760 | * a break input. |
1760 | * @param Channel This parameter can be one of the following values: |
| 1761 | * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n |
1761 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1762 | * CR2 OIS1N LL_TIM_OC_SetIdleState\n |
1762 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| 1763 | * CR2 OIS2 LL_TIM_OC_SetIdleState\n |
1763 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1764 | * CR2 OIS2N LL_TIM_OC_SetIdleState\n |
1764 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| 1765 | * CR2 OIS3 LL_TIM_OC_SetIdleState\n |
1765 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1766 | * CR2 OIS3N LL_TIM_OC_SetIdleState\n |
1766 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| 1767 | * CR2 OIS4 LL_TIM_OC_SetIdleState |
1767 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1768 | * @param TIMx Timer instance |
1768 | * @param IdleState This parameter can be one of the following values: |
| 1769 | * @param Channel This parameter can be one of the following values: |
1769 | * @arg @ref LL_TIM_OCIDLESTATE_LOW |
| 1770 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1770 | * @arg @ref LL_TIM_OCIDLESTATE_HIGH |
| 1771 | * @arg @ref LL_TIM_CHANNEL_CH1N |
1771 | * @retval None |
| 1772 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1772 | */ |
| 1773 | * @arg @ref LL_TIM_CHANNEL_CH2N |
1773 | __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) |
| 1774 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1774 | { |
| 1775 | * @arg @ref LL_TIM_CHANNEL_CH3N |
1775 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1776 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1776 | MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); |
| 1777 | * @param IdleState This parameter can be one of the following values: |
1777 | } |
| 1778 | * @arg @ref LL_TIM_OCIDLESTATE_LOW |
1778 | |
| 1779 | * @arg @ref LL_TIM_OCIDLESTATE_HIGH |
1779 | /** |
| 1780 | * @retval None |
1780 | * @brief Get the IDLE state of an output channel |
| 1781 | */ |
1781 | * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n |
| 1782 | __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) |
1782 | * CR2 OIS1N LL_TIM_OC_GetIdleState\n |
| 1783 | { |
1783 | * CR2 OIS2 LL_TIM_OC_GetIdleState\n |
| 1784 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1784 | * CR2 OIS2N LL_TIM_OC_GetIdleState\n |
| 1785 | MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); |
1785 | * CR2 OIS3 LL_TIM_OC_GetIdleState\n |
| 1786 | } |
1786 | * CR2 OIS3N LL_TIM_OC_GetIdleState\n |
| 1787 | 1787 | * CR2 OIS4 LL_TIM_OC_GetIdleState |
|
| 1788 | /** |
1788 | * @param TIMx Timer instance |
| 1789 | * @brief Get the IDLE state of an output channel |
1789 | * @param Channel This parameter can be one of the following values: |
| 1790 | * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n |
1790 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1791 | * CR2 OIS1N LL_TIM_OC_GetIdleState\n |
1791 | * @arg @ref LL_TIM_CHANNEL_CH1N |
| 1792 | * CR2 OIS2 LL_TIM_OC_GetIdleState\n |
1792 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1793 | * CR2 OIS2N LL_TIM_OC_GetIdleState\n |
1793 | * @arg @ref LL_TIM_CHANNEL_CH2N |
| 1794 | * CR2 OIS3 LL_TIM_OC_GetIdleState\n |
1794 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1795 | * CR2 OIS3N LL_TIM_OC_GetIdleState\n |
1795 | * @arg @ref LL_TIM_CHANNEL_CH3N |
| 1796 | * CR2 OIS4 LL_TIM_OC_GetIdleState |
1796 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1797 | * @param TIMx Timer instance |
1797 | * @retval Returned value can be one of the following values: |
| 1798 | * @param Channel This parameter can be one of the following values: |
1798 | * @arg @ref LL_TIM_OCIDLESTATE_LOW |
| 1799 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1799 | * @arg @ref LL_TIM_OCIDLESTATE_HIGH |
| 1800 | * @arg @ref LL_TIM_CHANNEL_CH1N |
1800 | */ |
| 1801 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1801 | __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1802 | * @arg @ref LL_TIM_CHANNEL_CH2N |
1802 | { |
| 1803 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1803 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1804 | * @arg @ref LL_TIM_CHANNEL_CH3N |
1804 | return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); |
| 1805 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1805 | } |
| 1806 | * @retval Returned value can be one of the following values: |
1806 | |
| 1807 | * @arg @ref LL_TIM_OCIDLESTATE_LOW |
1807 | /** |
| 1808 | * @arg @ref LL_TIM_OCIDLESTATE_HIGH |
1808 | * @brief Enable fast mode for the output channel. |
| 1809 | */ |
1809 | * @note Acts only if the channel is configured in PWM1 or PWM2 mode. |
| 1810 | __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) |
1810 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n |
| 1811 | { |
1811 | * CCMR1 OC2FE LL_TIM_OC_EnableFast\n |
| 1812 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1812 | * CCMR2 OC3FE LL_TIM_OC_EnableFast\n |
| 1813 | return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); |
1813 | * CCMR2 OC4FE LL_TIM_OC_EnableFast |
| 1814 | } |
1814 | * @param TIMx Timer instance |
| 1815 | 1815 | * @param Channel This parameter can be one of the following values: |
|
| 1816 | /** |
1816 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1817 | * @brief Enable fast mode for the output channel. |
1817 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1818 | * @note Acts only if the channel is configured in PWM1 or PWM2 mode. |
1818 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1819 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n |
1819 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1820 | * CCMR1 OC2FE LL_TIM_OC_EnableFast\n |
1820 | * @retval None |
| 1821 | * CCMR2 OC3FE LL_TIM_OC_EnableFast\n |
1821 | */ |
| 1822 | * CCMR2 OC4FE LL_TIM_OC_EnableFast |
1822 | __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1823 | * @param TIMx Timer instance |
1823 | { |
| 1824 | * @param Channel This parameter can be one of the following values: |
1824 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1825 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1825 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1826 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1826 | SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
| 1827 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1827 | |
| 1828 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1828 | } |
| 1829 | * @retval None |
1829 | |
| 1830 | */ |
1830 | /** |
| 1831 | __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
1831 | * @brief Disable fast mode for the output channel. |
| 1832 | { |
1832 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n |
| 1833 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1833 | * CCMR1 OC2FE LL_TIM_OC_DisableFast\n |
| 1834 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1834 | * CCMR2 OC3FE LL_TIM_OC_DisableFast\n |
| 1835 | SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
1835 | * CCMR2 OC4FE LL_TIM_OC_DisableFast |
| 1836 | 1836 | * @param TIMx Timer instance |
|
| 1837 | } |
1837 | * @param Channel This parameter can be one of the following values: |
| 1838 | 1838 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1839 | /** |
1839 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1840 | * @brief Disable fast mode for the output channel. |
1840 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1841 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n |
1841 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1842 | * CCMR1 OC2FE LL_TIM_OC_DisableFast\n |
1842 | * @retval None |
| 1843 | * CCMR2 OC3FE LL_TIM_OC_DisableFast\n |
1843 | */ |
| 1844 | * CCMR2 OC4FE LL_TIM_OC_DisableFast |
1844 | __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1845 | * @param TIMx Timer instance |
1845 | { |
| 1846 | * @param Channel This parameter can be one of the following values: |
1846 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1847 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1847 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1848 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1848 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
| 1849 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1849 | |
| 1850 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1850 | } |
| 1851 | * @retval None |
1851 | |
| 1852 | */ |
1852 | /** |
| 1853 | __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) |
1853 | * @brief Indicates whether fast mode is enabled for the output channel. |
| 1854 | { |
1854 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n |
| 1855 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1855 | * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n |
| 1856 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1856 | * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n |
| 1857 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); |
1857 | * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n |
| 1858 | 1858 | * @param TIMx Timer instance |
|
| 1859 | } |
1859 | * @param Channel This parameter can be one of the following values: |
| 1860 | 1860 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1861 | /** |
1861 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1862 | * @brief Indicates whether fast mode is enabled for the output channel. |
1862 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1863 | * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n |
1863 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1864 | * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n |
1864 | * @retval State of bit (1 or 0). |
| 1865 | * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n |
1865 | */ |
| 1866 | * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n |
1866 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1867 | * @param TIMx Timer instance |
1867 | { |
| 1868 | * @param Channel This parameter can be one of the following values: |
1868 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1869 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1869 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1870 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1870 | uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; |
| 1871 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1871 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
| 1872 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1872 | } |
| 1873 | * @retval State of bit (1 or 0). |
1873 | |
| 1874 | */ |
1874 | /** |
| 1875 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) |
1875 | * @brief Enable compare register (TIMx_CCRx) preload for the output channel. |
| 1876 | { |
1876 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n |
| 1877 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1877 | * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n |
| 1878 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1878 | * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n |
| 1879 | uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; |
1879 | * CCMR2 OC4PE LL_TIM_OC_EnablePreload |
| 1880 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
1880 | * @param TIMx Timer instance |
| 1881 | } |
1881 | * @param Channel This parameter can be one of the following values: |
| 1882 | 1882 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1883 | /** |
1883 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1884 | * @brief Enable compare register (TIMx_CCRx) preload for the output channel. |
1884 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1885 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n |
1885 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1886 | * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n |
1886 | * @retval None |
| 1887 | * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n |
1887 | */ |
| 1888 | * CCMR2 OC4PE LL_TIM_OC_EnablePreload |
1888 | __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1889 | * @param TIMx Timer instance |
1889 | { |
| 1890 | * @param Channel This parameter can be one of the following values: |
1890 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1891 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1891 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1892 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1892 | SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
| 1893 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1893 | } |
| 1894 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1894 | |
| 1895 | * @retval None |
1895 | /** |
| 1896 | */ |
1896 | * @brief Disable compare register (TIMx_CCRx) preload for the output channel. |
| 1897 | __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
1897 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n |
| 1898 | { |
1898 | * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n |
| 1899 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1899 | * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n |
| 1900 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1900 | * CCMR2 OC4PE LL_TIM_OC_DisablePreload |
| 1901 | SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
1901 | * @param TIMx Timer instance |
| 1902 | } |
1902 | * @param Channel This parameter can be one of the following values: |
| 1903 | 1903 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1904 | /** |
1904 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1905 | * @brief Disable compare register (TIMx_CCRx) preload for the output channel. |
1905 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1906 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n |
1906 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1907 | * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n |
1907 | * @retval None |
| 1908 | * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n |
1908 | */ |
| 1909 | * CCMR2 OC4PE LL_TIM_OC_DisablePreload |
1909 | __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1910 | * @param TIMx Timer instance |
1910 | { |
| 1911 | * @param Channel This parameter can be one of the following values: |
1911 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1912 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1912 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1913 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1913 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
| 1914 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1914 | } |
| 1915 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1915 | |
| 1916 | * @retval None |
1916 | /** |
| 1917 | */ |
1917 | * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. |
| 1918 | __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) |
1918 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n |
| 1919 | { |
1919 | * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n |
| 1920 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1920 | * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n |
| 1921 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1921 | * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n |
| 1922 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); |
1922 | * @param TIMx Timer instance |
| 1923 | } |
1923 | * @param Channel This parameter can be one of the following values: |
| 1924 | 1924 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 1925 | /** |
1925 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1926 | * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. |
1926 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1927 | * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n |
1927 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1928 | * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n |
1928 | * @retval State of bit (1 or 0). |
| 1929 | * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n |
1929 | */ |
| 1930 | * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n |
1930 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 1931 | * @param TIMx Timer instance |
1931 | { |
| 1932 | * @param Channel This parameter can be one of the following values: |
1932 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1933 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1933 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1934 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1934 | uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; |
| 1935 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1935 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
| 1936 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1936 | } |
| 1937 | * @retval State of bit (1 or 0). |
1937 | |
| 1938 | */ |
1938 | /** |
| 1939 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) |
1939 | * @brief Enable clearing the output channel on an external event. |
| 1940 | { |
1940 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
| 1941 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1941 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
| 1942 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1942 | * or not a timer instance can clear the OCxREF signal on an external event. |
| 1943 | uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; |
1943 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n |
| 1944 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
1944 | * CCMR1 OC2CE LL_TIM_OC_EnableClear\n |
| 1945 | } |
1945 | * CCMR2 OC3CE LL_TIM_OC_EnableClear\n |
| 1946 | 1946 | * CCMR2 OC4CE LL_TIM_OC_EnableClear |
|
| 1947 | /** |
1947 | * @param TIMx Timer instance |
| 1948 | * @brief Enable clearing the output channel on an external event. |
1948 | * @param Channel This parameter can be one of the following values: |
| 1949 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
1949 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1950 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
1950 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1951 | * or not a timer instance can clear the OCxREF signal on an external event. |
1951 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1952 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n |
1952 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1953 | * CCMR1 OC2CE LL_TIM_OC_EnableClear\n |
1953 | * @retval None |
| 1954 | * CCMR2 OC3CE LL_TIM_OC_EnableClear\n |
1954 | */ |
| 1955 | * CCMR2 OC4CE LL_TIM_OC_EnableClear |
1955 | __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1956 | * @param TIMx Timer instance |
1956 | { |
| 1957 | * @param Channel This parameter can be one of the following values: |
1957 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1958 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1958 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1959 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1959 | SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
| 1960 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1960 | } |
| 1961 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1961 | |
| 1962 | * @retval None |
1962 | /** |
| 1963 | */ |
1963 | * @brief Disable clearing the output channel on an external event. |
| 1964 | __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
1964 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
| 1965 | { |
1965 | * or not a timer instance can clear the OCxREF signal on an external event. |
| 1966 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1966 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n |
| 1967 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1967 | * CCMR1 OC2CE LL_TIM_OC_DisableClear\n |
| 1968 | SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
1968 | * CCMR2 OC3CE LL_TIM_OC_DisableClear\n |
| 1969 | } |
1969 | * CCMR2 OC4CE LL_TIM_OC_DisableClear |
| 1970 | 1970 | * @param TIMx Timer instance |
|
| 1971 | /** |
1971 | * @param Channel This parameter can be one of the following values: |
| 1972 | * @brief Disable clearing the output channel on an external event. |
1972 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1973 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
1973 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1974 | * or not a timer instance can clear the OCxREF signal on an external event. |
1974 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 1975 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n |
1975 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 1976 | * CCMR1 OC2CE LL_TIM_OC_DisableClear\n |
1976 | * @retval None |
| 1977 | * CCMR2 OC3CE LL_TIM_OC_DisableClear\n |
1977 | */ |
| 1978 | * CCMR2 OC4CE LL_TIM_OC_DisableClear |
1978 | __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
| 1979 | * @param TIMx Timer instance |
1979 | { |
| 1980 | * @param Channel This parameter can be one of the following values: |
1980 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 1981 | * @arg @ref LL_TIM_CHANNEL_CH1 |
1981 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 1982 | * @arg @ref LL_TIM_CHANNEL_CH2 |
1982 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
| 1983 | * @arg @ref LL_TIM_CHANNEL_CH3 |
1983 | } |
| 1984 | * @arg @ref LL_TIM_CHANNEL_CH4 |
1984 | |
| 1985 | * @retval None |
1985 | /** |
| 1986 | */ |
1986 | * @brief Indicates clearing the output channel on an external event is enabled for the output channel. |
| 1987 | __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) |
1987 | * @note This function enables clearing the output channel on an external event. |
| 1988 | { |
1988 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
| 1989 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
1989 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
| 1990 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
1990 | * or not a timer instance can clear the OCxREF signal on an external event. |
| 1991 | CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); |
1991 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n |
| 1992 | } |
1992 | * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n |
| 1993 | 1993 | * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n |
|
| 1994 | /** |
1994 | * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n |
| 1995 | * @brief Indicates clearing the output channel on an external event is enabled for the output channel. |
1995 | * @param TIMx Timer instance |
| 1996 | * @note This function enables clearing the output channel on an external event. |
1996 | * @param Channel This parameter can be one of the following values: |
| 1997 | * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. |
1997 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 1998 | * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether |
1998 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 1999 | * or not a timer instance can clear the OCxREF signal on an external event. |
1999 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2000 | * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n |
2000 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2001 | * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n |
2001 | * @retval State of bit (1 or 0). |
| 2002 | * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n |
2002 | */ |
| 2003 | * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n |
2003 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 2004 | * @param TIMx Timer instance |
2004 | { |
| 2005 | * @param Channel This parameter can be one of the following values: |
2005 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2006 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2006 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 2007 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2007 | uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; |
| 2008 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2008 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
| 2009 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2009 | } |
| 2010 | * @retval State of bit (1 or 0). |
2010 | |
| 2011 | */ |
2011 | /** |
| 2012 | __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) |
2012 | * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of |
| 2013 | { |
2013 | * the Ocx and OCxN signals). |
| 2014 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2014 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 2015 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
2015 | * dead-time insertion feature is supported by a timer instance. |
| 2016 | uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; |
2016 | * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter |
| 2017 | return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); |
2017 | * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime |
| 2018 | } |
2018 | * @param TIMx Timer instance |
| 2019 | 2019 | * @param DeadTime between Min_Data=0 and Max_Data=255 |
|
| 2020 | /** |
2020 | * @retval None |
| 2021 | * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of |
2021 | */ |
| 2022 | * the Ocx and OCxN signals). |
2022 | __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) |
| 2023 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
2023 | { |
| 2024 | * dead-time insertion feature is supported by a timer instance. |
2024 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); |
| 2025 | * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter |
2025 | } |
| 2026 | * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime |
2026 | |
| 2027 | * @param TIMx Timer instance |
2027 | /** |
| 2028 | * @param DeadTime between Min_Data=0 and Max_Data=255 |
2028 | * @brief Set compare value for output channel 1 (TIMx_CCR1). |
| 2029 | * @retval None |
2029 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
| 2030 | */ |
2030 | * output channel 1 is supported by a timer instance. |
| 2031 | __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) |
2031 | * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 |
| 2032 | { |
2032 | * @param TIMx Timer instance |
| 2033 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); |
2033 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| 2034 | } |
2034 | * @retval None |
| 2035 | 2035 | */ |
|
| 2036 | /** |
2036 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| 2037 | * @brief Set compare value for output channel 1 (TIMx_CCR1). |
2037 | { |
| 2038 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
2038 | WRITE_REG(TIMx->CCR1, CompareValue); |
| 2039 | * output channel 1 is supported by a timer instance. |
2039 | } |
| 2040 | * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 |
2040 | |
| 2041 | * @param TIMx Timer instance |
2041 | /** |
| 2042 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
2042 | * @brief Set compare value for output channel 2 (TIMx_CCR2). |
| 2043 | * @retval None |
2043 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
| 2044 | */ |
2044 | * output channel 2 is supported by a timer instance. |
| 2045 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) |
2045 | * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 |
| 2046 | { |
2046 | * @param TIMx Timer instance |
| 2047 | WRITE_REG(TIMx->CCR1, CompareValue); |
2047 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| 2048 | } |
2048 | * @retval None |
| 2049 | 2049 | */ |
|
| 2050 | /** |
2050 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| 2051 | * @brief Set compare value for output channel 2 (TIMx_CCR2). |
2051 | { |
| 2052 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
2052 | WRITE_REG(TIMx->CCR2, CompareValue); |
| 2053 | * output channel 2 is supported by a timer instance. |
2053 | } |
| 2054 | * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 |
2054 | |
| 2055 | * @param TIMx Timer instance |
2055 | /** |
| 2056 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
2056 | * @brief Set compare value for output channel 3 (TIMx_CCR3). |
| 2057 | * @retval None |
2057 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
| 2058 | */ |
2058 | * output channel is supported by a timer instance. |
| 2059 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) |
2059 | * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 |
| 2060 | { |
2060 | * @param TIMx Timer instance |
| 2061 | WRITE_REG(TIMx->CCR2, CompareValue); |
2061 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| 2062 | } |
2062 | * @retval None |
| 2063 | 2063 | */ |
|
| 2064 | /** |
2064 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| 2065 | * @brief Set compare value for output channel 3 (TIMx_CCR3). |
2065 | { |
| 2066 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
2066 | WRITE_REG(TIMx->CCR3, CompareValue); |
| 2067 | * output channel is supported by a timer instance. |
2067 | } |
| 2068 | * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 |
2068 | |
| 2069 | * @param TIMx Timer instance |
2069 | /** |
| 2070 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
2070 | * @brief Set compare value for output channel 4 (TIMx_CCR4). |
| 2071 | * @retval None |
2071 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
| 2072 | */ |
2072 | * output channel 4 is supported by a timer instance. |
| 2073 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) |
2073 | * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 |
| 2074 | { |
2074 | * @param TIMx Timer instance |
| 2075 | WRITE_REG(TIMx->CCR3, CompareValue); |
2075 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
| 2076 | } |
2076 | * @retval None |
| 2077 | 2077 | */ |
|
| 2078 | /** |
2078 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) |
| 2079 | * @brief Set compare value for output channel 4 (TIMx_CCR4). |
2079 | { |
| 2080 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
2080 | WRITE_REG(TIMx->CCR4, CompareValue); |
| 2081 | * output channel 4 is supported by a timer instance. |
2081 | } |
| 2082 | * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 |
2082 | |
| 2083 | * @param TIMx Timer instance |
2083 | /** |
| 2084 | * @param CompareValue between Min_Data=0 and Max_Data=65535 |
2084 | * @brief Get compare value (TIMx_CCR1) set for output channel 1. |
| 2085 | * @retval None |
2085 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
| 2086 | */ |
2086 | * output channel 1 is supported by a timer instance. |
| 2087 | __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) |
2087 | * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 |
| 2088 | { |
2088 | * @param TIMx Timer instance |
| 2089 | WRITE_REG(TIMx->CCR4, CompareValue); |
2089 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| 2090 | } |
2090 | */ |
| 2091 | 2091 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx) |
|
| 2092 | /** |
2092 | { |
| 2093 | * @brief Get compare value (TIMx_CCR1) set for output channel 1. |
2093 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
| 2094 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
2094 | } |
| 2095 | * output channel 1 is supported by a timer instance. |
2095 | |
| 2096 | * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 |
2096 | /** |
| 2097 | * @param TIMx Timer instance |
2097 | * @brief Get compare value (TIMx_CCR2) set for output channel 2. |
| 2098 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
2098 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
| 2099 | */ |
2099 | * output channel 2 is supported by a timer instance. |
| 2100 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) |
2100 | * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 |
| 2101 | { |
2101 | * @param TIMx Timer instance |
| 2102 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
2102 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| 2103 | } |
2103 | */ |
| 2104 | 2104 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx) |
|
| 2105 | /** |
2105 | { |
| 2106 | * @brief Get compare value (TIMx_CCR2) set for output channel 2. |
2106 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
| 2107 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
2107 | } |
| 2108 | * output channel 2 is supported by a timer instance. |
2108 | |
| 2109 | * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 |
2109 | /** |
| 2110 | * @param TIMx Timer instance |
2110 | * @brief Get compare value (TIMx_CCR3) set for output channel 3. |
| 2111 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
2111 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
| 2112 | */ |
2112 | * output channel 3 is supported by a timer instance. |
| 2113 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) |
2113 | * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 |
| 2114 | { |
2114 | * @param TIMx Timer instance |
| 2115 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
2115 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| 2116 | } |
2116 | */ |
| 2117 | 2117 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx) |
|
| 2118 | /** |
2118 | { |
| 2119 | * @brief Get compare value (TIMx_CCR3) set for output channel 3. |
2119 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
| 2120 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
2120 | } |
| 2121 | * output channel 3 is supported by a timer instance. |
2121 | |
| 2122 | * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 |
2122 | /** |
| 2123 | * @param TIMx Timer instance |
2123 | * @brief Get compare value (TIMx_CCR4) set for output channel 4. |
| 2124 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
2124 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
| 2125 | */ |
2125 | * output channel 4 is supported by a timer instance. |
| 2126 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) |
2126 | * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 |
| 2127 | { |
2127 | * @param TIMx Timer instance |
| 2128 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
2128 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
| 2129 | } |
2129 | */ |
| 2130 | 2130 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx) |
|
| 2131 | /** |
2131 | { |
| 2132 | * @brief Get compare value (TIMx_CCR4) set for output channel 4. |
2132 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
| 2133 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
2133 | } |
| 2134 | * output channel 4 is supported by a timer instance. |
2134 | |
| 2135 | * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 |
2135 | /** |
| 2136 | * @param TIMx Timer instance |
2136 | * @} |
| 2137 | * @retval CompareValue (between Min_Data=0 and Max_Data=65535) |
2137 | */ |
| 2138 | */ |
2138 | |
| 2139 | __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) |
2139 | /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration |
| 2140 | { |
2140 | * @{ |
| 2141 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
2141 | */ |
| 2142 | } |
2142 | /** |
| 2143 | 2143 | * @brief Configure input channel. |
|
| 2144 | /** |
2144 | * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n |
| 2145 | * @} |
2145 | * CCMR1 IC1PSC LL_TIM_IC_Config\n |
| 2146 | */ |
2146 | * CCMR1 IC1F LL_TIM_IC_Config\n |
| 2147 | 2147 | * CCMR1 CC2S LL_TIM_IC_Config\n |
|
| 2148 | /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration |
2148 | * CCMR1 IC2PSC LL_TIM_IC_Config\n |
| 2149 | * @{ |
2149 | * CCMR1 IC2F LL_TIM_IC_Config\n |
| 2150 | */ |
2150 | * CCMR2 CC3S LL_TIM_IC_Config\n |
| 2151 | /** |
2151 | * CCMR2 IC3PSC LL_TIM_IC_Config\n |
| 2152 | * @brief Configure input channel. |
2152 | * CCMR2 IC3F LL_TIM_IC_Config\n |
| 2153 | * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n |
2153 | * CCMR2 CC4S LL_TIM_IC_Config\n |
| 2154 | * CCMR1 IC1PSC LL_TIM_IC_Config\n |
2154 | * CCMR2 IC4PSC LL_TIM_IC_Config\n |
| 2155 | * CCMR1 IC1F LL_TIM_IC_Config\n |
2155 | * CCMR2 IC4F LL_TIM_IC_Config\n |
| 2156 | * CCMR1 CC2S LL_TIM_IC_Config\n |
2156 | * CCER CC1P LL_TIM_IC_Config\n |
| 2157 | * CCMR1 IC2PSC LL_TIM_IC_Config\n |
2157 | * CCER CC1NP LL_TIM_IC_Config\n |
| 2158 | * CCMR1 IC2F LL_TIM_IC_Config\n |
2158 | * CCER CC2P LL_TIM_IC_Config\n |
| 2159 | * CCMR2 CC3S LL_TIM_IC_Config\n |
2159 | * CCER CC2NP LL_TIM_IC_Config\n |
| 2160 | * CCMR2 IC3PSC LL_TIM_IC_Config\n |
2160 | * CCER CC3P LL_TIM_IC_Config\n |
| 2161 | * CCMR2 IC3F LL_TIM_IC_Config\n |
2161 | * CCER CC3NP LL_TIM_IC_Config\n |
| 2162 | * CCMR2 CC4S LL_TIM_IC_Config\n |
2162 | * CCER CC4P LL_TIM_IC_Config\n |
| 2163 | * CCMR2 IC4PSC LL_TIM_IC_Config\n |
2163 | * @param TIMx Timer instance |
| 2164 | * CCMR2 IC4F LL_TIM_IC_Config\n |
2164 | * @param Channel This parameter can be one of the following values: |
| 2165 | * CCER CC1P LL_TIM_IC_Config\n |
2165 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 2166 | * CCER CC1NP LL_TIM_IC_Config\n |
2166 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 2167 | * CCER CC2P LL_TIM_IC_Config\n |
2167 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2168 | * CCER CC2NP LL_TIM_IC_Config\n |
2168 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2169 | * CCER CC3P LL_TIM_IC_Config\n |
2169 | * @param Configuration This parameter must be a combination of all the following values: |
| 2170 | * CCER CC3NP LL_TIM_IC_Config\n |
2170 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC |
| 2171 | * CCER CC4P LL_TIM_IC_Config\n |
2171 | * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 |
| 2172 | * @param TIMx Timer instance |
2172 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 |
| 2173 | * @param Channel This parameter can be one of the following values: |
2173 | * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING |
| 2174 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2174 | * @retval None |
| 2175 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2175 | */ |
| 2176 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2176 | __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
| 2177 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2177 | { |
| 2178 | * @param Configuration This parameter must be a combination of all the following values: |
2178 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2179 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC |
2179 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 2180 | * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 |
2180 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), |
| 2181 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 |
2181 | ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ |
| 2182 | * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING |
2182 | << SHIFT_TAB_ICxx[iChannel]); |
| 2183 | * @retval None |
2183 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
| 2184 | */ |
2184 | (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); |
| 2185 | __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) |
2185 | } |
| 2186 | { |
2186 | |
| 2187 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2187 | /** |
| 2188 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
2188 | * @brief Set the active input. |
| 2189 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), |
2189 | * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n |
| 2190 | ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) \ |
2190 | * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n |
| 2191 | << SHIFT_TAB_ICxx[iChannel]); |
2191 | * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n |
| 2192 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
2192 | * CCMR2 CC4S LL_TIM_IC_SetActiveInput |
| 2193 | (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); |
2193 | * @param TIMx Timer instance |
| 2194 | } |
2194 | * @param Channel This parameter can be one of the following values: |
| 2195 | 2195 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 2196 | /** |
2196 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 2197 | * @brief Set the active input. |
2197 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2198 | * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n |
2198 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2199 | * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n |
2199 | * @param ICActiveInput This parameter can be one of the following values: |
| 2200 | * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n |
2200 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
| 2201 | * CCMR2 CC4S LL_TIM_IC_SetActiveInput |
2201 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
| 2202 | * @param TIMx Timer instance |
2202 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
| 2203 | * @param Channel This parameter can be one of the following values: |
2203 | * @retval None |
| 2204 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2204 | */ |
| 2205 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2205 | __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) |
| 2206 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2206 | { |
| 2207 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2207 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2208 | * @param ICActiveInput This parameter can be one of the following values: |
2208 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 2209 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
2209 | MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
| 2210 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
2210 | } |
| 2211 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
2211 | |
| 2212 | * @retval None |
2212 | /** |
| 2213 | */ |
2213 | * @brief Get the current active input. |
| 2214 | __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) |
2214 | * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n |
| 2215 | { |
2215 | * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n |
| 2216 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2216 | * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n |
| 2217 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
2217 | * CCMR2 CC4S LL_TIM_IC_GetActiveInput |
| 2218 | MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
2218 | * @param TIMx Timer instance |
| 2219 | } |
2219 | * @param Channel This parameter can be one of the following values: |
| 2220 | 2220 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 2221 | /** |
2221 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 2222 | * @brief Get the current active input. |
2222 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2223 | * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n |
2223 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2224 | * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n |
2224 | * @retval Returned value can be one of the following values: |
| 2225 | * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n |
2225 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
| 2226 | * CCMR2 CC4S LL_TIM_IC_GetActiveInput |
2226 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
| 2227 | * @param TIMx Timer instance |
2227 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
| 2228 | * @param Channel This parameter can be one of the following values: |
2228 | */ |
| 2229 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2229 | __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 2230 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2230 | { |
| 2231 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2231 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2232 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2232 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 2233 | * @retval Returned value can be one of the following values: |
2233 | return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
| 2234 | * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI |
2234 | } |
| 2235 | * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI |
2235 | |
| 2236 | * @arg @ref LL_TIM_ACTIVEINPUT_TRC |
2236 | /** |
| 2237 | */ |
2237 | * @brief Set the prescaler of input channel. |
| 2238 | __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) |
2238 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n |
| 2239 | { |
2239 | * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n |
| 2240 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2240 | * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n |
| 2241 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
2241 | * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler |
| 2242 | return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
2242 | * @param TIMx Timer instance |
| 2243 | } |
2243 | * @param Channel This parameter can be one of the following values: |
| 2244 | 2244 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 2245 | /** |
2245 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 2246 | * @brief Set the prescaler of input channel. |
2246 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2247 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n |
2247 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2248 | * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n |
2248 | * @param ICPrescaler This parameter can be one of the following values: |
| 2249 | * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n |
2249 | * @arg @ref LL_TIM_ICPSC_DIV1 |
| 2250 | * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler |
2250 | * @arg @ref LL_TIM_ICPSC_DIV2 |
| 2251 | * @param TIMx Timer instance |
2251 | * @arg @ref LL_TIM_ICPSC_DIV4 |
| 2252 | * @param Channel This parameter can be one of the following values: |
2252 | * @arg @ref LL_TIM_ICPSC_DIV8 |
| 2253 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2253 | * @retval None |
| 2254 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2254 | */ |
| 2255 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2255 | __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) |
| 2256 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2256 | { |
| 2257 | * @param ICPrescaler This parameter can be one of the following values: |
2257 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2258 | * @arg @ref LL_TIM_ICPSC_DIV1 |
2258 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 2259 | * @arg @ref LL_TIM_ICPSC_DIV2 |
2259 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
| 2260 | * @arg @ref LL_TIM_ICPSC_DIV4 |
2260 | } |
| 2261 | * @arg @ref LL_TIM_ICPSC_DIV8 |
2261 | |
| 2262 | * @retval None |
2262 | /** |
| 2263 | */ |
2263 | * @brief Get the current prescaler value acting on an input channel. |
| 2264 | __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) |
2264 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n |
| 2265 | { |
2265 | * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n |
| 2266 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2266 | * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n |
| 2267 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
2267 | * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler |
| 2268 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
2268 | * @param TIMx Timer instance |
| 2269 | } |
2269 | * @param Channel This parameter can be one of the following values: |
| 2270 | 2270 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 2271 | /** |
2271 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 2272 | * @brief Get the current prescaler value acting on an input channel. |
2272 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2273 | * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n |
2273 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2274 | * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n |
2274 | * @retval Returned value can be one of the following values: |
| 2275 | * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n |
2275 | * @arg @ref LL_TIM_ICPSC_DIV1 |
| 2276 | * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler |
2276 | * @arg @ref LL_TIM_ICPSC_DIV2 |
| 2277 | * @param TIMx Timer instance |
2277 | * @arg @ref LL_TIM_ICPSC_DIV4 |
| 2278 | * @param Channel This parameter can be one of the following values: |
2278 | * @arg @ref LL_TIM_ICPSC_DIV8 |
| 2279 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2279 | */ |
| 2280 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2280 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 2281 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2281 | { |
| 2282 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2282 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2283 | * @retval Returned value can be one of the following values: |
2283 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 2284 | * @arg @ref LL_TIM_ICPSC_DIV1 |
2284 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
| 2285 | * @arg @ref LL_TIM_ICPSC_DIV2 |
2285 | } |
| 2286 | * @arg @ref LL_TIM_ICPSC_DIV4 |
2286 | |
| 2287 | * @arg @ref LL_TIM_ICPSC_DIV8 |
2287 | /** |
| 2288 | */ |
2288 | * @brief Set the input filter duration. |
| 2289 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) |
2289 | * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n |
| 2290 | { |
2290 | * CCMR1 IC2F LL_TIM_IC_SetFilter\n |
| 2291 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2291 | * CCMR2 IC3F LL_TIM_IC_SetFilter\n |
| 2292 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
2292 | * CCMR2 IC4F LL_TIM_IC_SetFilter |
| 2293 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
2293 | * @param TIMx Timer instance |
| 2294 | } |
2294 | * @param Channel This parameter can be one of the following values: |
| 2295 | 2295 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 2296 | /** |
2296 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 2297 | * @brief Set the input filter duration. |
2297 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2298 | * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n |
2298 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2299 | * CCMR1 IC2F LL_TIM_IC_SetFilter\n |
2299 | * @param ICFilter This parameter can be one of the following values: |
| 2300 | * CCMR2 IC3F LL_TIM_IC_SetFilter\n |
2300 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
| 2301 | * CCMR2 IC4F LL_TIM_IC_SetFilter |
2301 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
| 2302 | * @param TIMx Timer instance |
2302 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
| 2303 | * @param Channel This parameter can be one of the following values: |
2303 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
| 2304 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2304 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
| 2305 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2305 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
| 2306 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2306 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
| 2307 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2307 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
| 2308 | * @param ICFilter This parameter can be one of the following values: |
2308 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
| 2309 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
2309 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
| 2310 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
2310 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
| 2311 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
2311 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
| 2312 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
2312 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
| 2313 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
2313 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
| 2314 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
2314 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
| 2315 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
2315 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
| 2316 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
2316 | * @retval None |
| 2317 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
2317 | */ |
| 2318 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
2318 | __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) |
| 2319 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
2319 | { |
| 2320 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
2320 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2321 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
2321 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 2322 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
2322 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
| 2323 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
2323 | } |
| 2324 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
2324 | |
| 2325 | * @retval None |
2325 | /** |
| 2326 | */ |
2326 | * @brief Get the input filter duration. |
| 2327 | __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) |
2327 | * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n |
| 2328 | { |
2328 | * CCMR1 IC2F LL_TIM_IC_GetFilter\n |
| 2329 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2329 | * CCMR2 IC3F LL_TIM_IC_GetFilter\n |
| 2330 | __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
2330 | * CCMR2 IC4F LL_TIM_IC_GetFilter |
| 2331 | MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); |
2331 | * @param TIMx Timer instance |
| 2332 | } |
2332 | * @param Channel This parameter can be one of the following values: |
| 2333 | 2333 | * @arg @ref LL_TIM_CHANNEL_CH1 |
|
| 2334 | /** |
2334 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 2335 | * @brief Get the input filter duration. |
2335 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2336 | * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n |
2336 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2337 | * CCMR1 IC2F LL_TIM_IC_GetFilter\n |
2337 | * @retval Returned value can be one of the following values: |
| 2338 | * CCMR2 IC3F LL_TIM_IC_GetFilter\n |
2338 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
| 2339 | * CCMR2 IC4F LL_TIM_IC_GetFilter |
2339 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
| 2340 | * @param TIMx Timer instance |
2340 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
| 2341 | * @param Channel This parameter can be one of the following values: |
2341 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
| 2342 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2342 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
| 2343 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2343 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
| 2344 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2344 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
| 2345 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2345 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
| 2346 | * @retval Returned value can be one of the following values: |
2346 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
| 2347 | * @arg @ref LL_TIM_IC_FILTER_FDIV1 |
2347 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
| 2348 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 |
2348 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
| 2349 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 |
2349 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
| 2350 | * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 |
2350 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
| 2351 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 |
2351 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
| 2352 | * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 |
2352 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
| 2353 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 |
2353 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
| 2354 | * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 |
2354 | */ |
| 2355 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 |
2355 | __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 2356 | * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 |
2356 | { |
| 2357 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 |
2357 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2358 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 |
2358 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
| 2359 | * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 |
2359 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
| 2360 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 |
2360 | } |
| 2361 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 |
2361 | |
| 2362 | * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 |
2362 | /** |
| 2363 | */ |
2363 | * @brief Set the input channel polarity. |
| 2364 | __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) |
2364 | * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n |
| 2365 | { |
2365 | * CCER CC1NP LL_TIM_IC_SetPolarity\n |
| 2366 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2366 | * CCER CC2P LL_TIM_IC_SetPolarity\n |
| 2367 | const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); |
2367 | * CCER CC2NP LL_TIM_IC_SetPolarity\n |
| 2368 | return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); |
2368 | * CCER CC3P LL_TIM_IC_SetPolarity\n |
| 2369 | } |
2369 | * CCER CC3NP LL_TIM_IC_SetPolarity\n |
| 2370 | 2370 | * CCER CC4P LL_TIM_IC_SetPolarity\n |
|
| 2371 | /** |
2371 | * @param TIMx Timer instance |
| 2372 | * @brief Set the input channel polarity. |
2372 | * @param Channel This parameter can be one of the following values: |
| 2373 | * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n |
2373 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 2374 | * CCER CC1NP LL_TIM_IC_SetPolarity\n |
2374 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 2375 | * CCER CC2P LL_TIM_IC_SetPolarity\n |
2375 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2376 | * CCER CC2NP LL_TIM_IC_SetPolarity\n |
2376 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2377 | * CCER CC3P LL_TIM_IC_SetPolarity\n |
2377 | * @param ICPolarity This parameter can be one of the following values: |
| 2378 | * CCER CC3NP LL_TIM_IC_SetPolarity\n |
2378 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
| 2379 | * CCER CC4P LL_TIM_IC_SetPolarity\n |
2379 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
| 2380 | * @param TIMx Timer instance |
2380 | * @retval None |
| 2381 | * @param Channel This parameter can be one of the following values: |
2381 | */ |
| 2382 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2382 | __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) |
| 2383 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2383 | { |
| 2384 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2384 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2385 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2385 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
| 2386 | * @param ICPolarity This parameter can be one of the following values: |
2386 | ICPolarity << SHIFT_TAB_CCxP[iChannel]); |
| 2387 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
2387 | } |
| 2388 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
2388 | |
| 2389 | * @retval None |
2389 | /** |
| 2390 | */ |
2390 | * @brief Get the current input channel polarity. |
| 2391 | __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) |
2391 | * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n |
| 2392 | { |
2392 | * CCER CC1NP LL_TIM_IC_GetPolarity\n |
| 2393 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2393 | * CCER CC2P LL_TIM_IC_GetPolarity\n |
| 2394 | MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), |
2394 | * CCER CC2NP LL_TIM_IC_GetPolarity\n |
| 2395 | ICPolarity << SHIFT_TAB_CCxP[iChannel]); |
2395 | * CCER CC3P LL_TIM_IC_GetPolarity\n |
| 2396 | } |
2396 | * CCER CC3NP LL_TIM_IC_GetPolarity\n |
| 2397 | 2397 | * CCER CC4P LL_TIM_IC_GetPolarity\n |
|
| 2398 | /** |
2398 | * @param TIMx Timer instance |
| 2399 | * @brief Get the current input channel polarity. |
2399 | * @param Channel This parameter can be one of the following values: |
| 2400 | * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n |
2400 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 2401 | * CCER CC1NP LL_TIM_IC_GetPolarity\n |
2401 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 2402 | * CCER CC2P LL_TIM_IC_GetPolarity\n |
2402 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 2403 | * CCER CC2NP LL_TIM_IC_GetPolarity\n |
2403 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 2404 | * CCER CC3P LL_TIM_IC_GetPolarity\n |
2404 | * @retval Returned value can be one of the following values: |
| 2405 | * CCER CC3NP LL_TIM_IC_GetPolarity\n |
2405 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
| 2406 | * CCER CC4P LL_TIM_IC_GetPolarity\n |
2406 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
| 2407 | * @param TIMx Timer instance |
2407 | */ |
| 2408 | * @param Channel This parameter can be one of the following values: |
2408 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel) |
| 2409 | * @arg @ref LL_TIM_CHANNEL_CH1 |
2409 | { |
| 2410 | * @arg @ref LL_TIM_CHANNEL_CH2 |
2410 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
| 2411 | * @arg @ref LL_TIM_CHANNEL_CH3 |
2411 | return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> |
| 2412 | * @arg @ref LL_TIM_CHANNEL_CH4 |
2412 | SHIFT_TAB_CCxP[iChannel]); |
| 2413 | * @retval Returned value can be one of the following values: |
2413 | } |
| 2414 | * @arg @ref LL_TIM_IC_POLARITY_RISING |
2414 | |
| 2415 | * @arg @ref LL_TIM_IC_POLARITY_FALLING |
2415 | /** |
| 2416 | */ |
2416 | * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). |
| 2417 | __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) |
2417 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
| 2418 | { |
2418 | * a timer instance provides an XOR input. |
| 2419 | uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); |
2419 | * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination |
| 2420 | return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> |
2420 | * @param TIMx Timer instance |
| 2421 | SHIFT_TAB_CCxP[iChannel]); |
2421 | * @retval None |
| 2422 | } |
2422 | */ |
| 2423 | 2423 | __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) |
|
| 2424 | /** |
2424 | { |
| 2425 | * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). |
2425 | SET_BIT(TIMx->CR2, TIM_CR2_TI1S); |
| 2426 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
2426 | } |
| 2427 | * a timer instance provides an XOR input. |
2427 | |
| 2428 | * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination |
2428 | /** |
| 2429 | * @param TIMx Timer instance |
2429 | * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. |
| 2430 | * @retval None |
2430 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
| 2431 | */ |
2431 | * a timer instance provides an XOR input. |
| 2432 | __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) |
2432 | * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination |
| 2433 | { |
2433 | * @param TIMx Timer instance |
| 2434 | SET_BIT(TIMx->CR2, TIM_CR2_TI1S); |
2434 | * @retval None |
| 2435 | } |
2435 | */ |
| 2436 | 2436 | __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) |
|
| 2437 | /** |
2437 | { |
| 2438 | * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. |
2438 | CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); |
| 2439 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
2439 | } |
| 2440 | * a timer instance provides an XOR input. |
2440 | |
| 2441 | * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination |
2441 | /** |
| 2442 | * @param TIMx Timer instance |
2442 | * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. |
| 2443 | * @retval None |
2443 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
| 2444 | */ |
2444 | * a timer instance provides an XOR input. |
| 2445 | __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) |
2445 | * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination |
| 2446 | { |
2446 | * @param TIMx Timer instance |
| 2447 | CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); |
2447 | * @retval State of bit (1 or 0). |
| 2448 | } |
2448 | */ |
| 2449 | 2449 | __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) |
|
| 2450 | /** |
2450 | { |
| 2451 | * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. |
2451 | return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); |
| 2452 | * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not |
2452 | } |
| 2453 | * a timer instance provides an XOR input. |
2453 | |
| 2454 | * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination |
2454 | /** |
| 2455 | * @param TIMx Timer instance |
2455 | * @brief Get captured value for input channel 1. |
| 2456 | * @retval State of bit (1 or 0). |
2456 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
| 2457 | */ |
2457 | * input channel 1 is supported by a timer instance. |
| 2458 | __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) |
2458 | * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 |
| 2459 | { |
2459 | * @param TIMx Timer instance |
| 2460 | return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); |
2460 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| 2461 | } |
2461 | */ |
| 2462 | 2462 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx) |
|
| 2463 | /** |
2463 | { |
| 2464 | * @brief Get captured value for input channel 1. |
2464 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
| 2465 | * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not |
2465 | } |
| 2466 | * input channel 1 is supported by a timer instance. |
2466 | |
| 2467 | * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 |
2467 | /** |
| 2468 | * @param TIMx Timer instance |
2468 | * @brief Get captured value for input channel 2. |
| 2469 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
2469 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
| 2470 | */ |
2470 | * input channel 2 is supported by a timer instance. |
| 2471 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) |
2471 | * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 |
| 2472 | { |
2472 | * @param TIMx Timer instance |
| 2473 | return (uint32_t)(READ_REG(TIMx->CCR1)); |
2473 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| 2474 | } |
2474 | */ |
| 2475 | 2475 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx) |
|
| 2476 | /** |
2476 | { |
| 2477 | * @brief Get captured value for input channel 2. |
2477 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
| 2478 | * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not |
2478 | } |
| 2479 | * input channel 2 is supported by a timer instance. |
2479 | |
| 2480 | * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 |
2480 | /** |
| 2481 | * @param TIMx Timer instance |
2481 | * @brief Get captured value for input channel 3. |
| 2482 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
2482 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
| 2483 | */ |
2483 | * input channel 3 is supported by a timer instance. |
| 2484 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) |
2484 | * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 |
| 2485 | { |
2485 | * @param TIMx Timer instance |
| 2486 | return (uint32_t)(READ_REG(TIMx->CCR2)); |
2486 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| 2487 | } |
2487 | */ |
| 2488 | 2488 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx) |
|
| 2489 | /** |
2489 | { |
| 2490 | * @brief Get captured value for input channel 3. |
2490 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
| 2491 | * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not |
2491 | } |
| 2492 | * input channel 3 is supported by a timer instance. |
2492 | |
| 2493 | * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 |
2493 | /** |
| 2494 | * @param TIMx Timer instance |
2494 | * @brief Get captured value for input channel 4. |
| 2495 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
2495 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
| 2496 | */ |
2496 | * input channel 4 is supported by a timer instance. |
| 2497 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) |
2497 | * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 |
| 2498 | { |
2498 | * @param TIMx Timer instance |
| 2499 | return (uint32_t)(READ_REG(TIMx->CCR3)); |
2499 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
| 2500 | } |
2500 | */ |
| 2501 | 2501 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx) |
|
| 2502 | /** |
2502 | { |
| 2503 | * @brief Get captured value for input channel 4. |
2503 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
| 2504 | * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not |
2504 | } |
| 2505 | * input channel 4 is supported by a timer instance. |
2505 | |
| 2506 | * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 |
2506 | /** |
| 2507 | * @param TIMx Timer instance |
2507 | * @} |
| 2508 | * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) |
2508 | */ |
| 2509 | */ |
2509 | |
| 2510 | __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) |
2510 | /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection |
| 2511 | { |
2511 | * @{ |
| 2512 | return (uint32_t)(READ_REG(TIMx->CCR4)); |
2512 | */ |
| 2513 | } |
2513 | /** |
| 2514 | 2514 | * @brief Enable external clock mode 2. |
|
| 2515 | /** |
2515 | * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. |
| 2516 | * @} |
2516 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
| 2517 | */ |
2517 | * whether or not a timer instance supports external clock mode2. |
| 2518 | 2518 | * @rmtoll SMCR ECE LL_TIM_EnableExternalClock |
|
| 2519 | /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection |
2519 | * @param TIMx Timer instance |
| 2520 | * @{ |
2520 | * @retval None |
| 2521 | */ |
2521 | */ |
| 2522 | /** |
2522 | __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) |
| 2523 | * @brief Enable external clock mode 2. |
2523 | { |
| 2524 | * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. |
2524 | SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
| 2525 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
2525 | } |
| 2526 | * whether or not a timer instance supports external clock mode2. |
2526 | |
| 2527 | * @rmtoll SMCR ECE LL_TIM_EnableExternalClock |
2527 | /** |
| 2528 | * @param TIMx Timer instance |
2528 | * @brief Disable external clock mode 2. |
| 2529 | * @retval None |
2529 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
| 2530 | */ |
2530 | * whether or not a timer instance supports external clock mode2. |
| 2531 | __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) |
2531 | * @rmtoll SMCR ECE LL_TIM_DisableExternalClock |
| 2532 | { |
2532 | * @param TIMx Timer instance |
| 2533 | SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
2533 | * @retval None |
| 2534 | } |
2534 | */ |
| 2535 | 2535 | __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) |
|
| 2536 | /** |
2536 | { |
| 2537 | * @brief Disable external clock mode 2. |
2537 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
| 2538 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
2538 | } |
| 2539 | * whether or not a timer instance supports external clock mode2. |
2539 | |
| 2540 | * @rmtoll SMCR ECE LL_TIM_DisableExternalClock |
2540 | /** |
| 2541 | * @param TIMx Timer instance |
2541 | * @brief Indicate whether external clock mode 2 is enabled. |
| 2542 | * @retval None |
2542 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
| 2543 | */ |
2543 | * whether or not a timer instance supports external clock mode2. |
| 2544 | __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) |
2544 | * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock |
| 2545 | { |
2545 | * @param TIMx Timer instance |
| 2546 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); |
2546 | * @retval State of bit (1 or 0). |
| 2547 | } |
2547 | */ |
| 2548 | 2548 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx) |
|
| 2549 | /** |
2549 | { |
| 2550 | * @brief Indicate whether external clock mode 2 is enabled. |
2550 | return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); |
| 2551 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
2551 | } |
| 2552 | * whether or not a timer instance supports external clock mode2. |
2552 | |
| 2553 | * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock |
2553 | /** |
| 2554 | * @param TIMx Timer instance |
2554 | * @brief Set the clock source of the counter clock. |
| 2555 | * @retval State of bit (1 or 0). |
2555 | * @note when selected clock source is external clock mode 1, the timer input |
| 2556 | */ |
2556 | * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() |
| 2557 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) |
2557 | * function. This timer input must be configured by calling |
| 2558 | { |
2558 | * the @ref LL_TIM_IC_Config() function. |
| 2559 | return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); |
2559 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check |
| 2560 | } |
2560 | * whether or not a timer instance supports external clock mode1. |
| 2561 | 2561 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
|
| 2562 | /** |
2562 | * whether or not a timer instance supports external clock mode2. |
| 2563 | * @brief Set the clock source of the counter clock. |
2563 | * @rmtoll SMCR SMS LL_TIM_SetClockSource\n |
| 2564 | * @note when selected clock source is external clock mode 1, the timer input |
2564 | * SMCR ECE LL_TIM_SetClockSource |
| 2565 | * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() |
2565 | * @param TIMx Timer instance |
| 2566 | * function. This timer input must be configured by calling |
2566 | * @param ClockSource This parameter can be one of the following values: |
| 2567 | * the @ref LL_TIM_IC_Config() function. |
2567 | * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL |
| 2568 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check |
2568 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 |
| 2569 | * whether or not a timer instance supports external clock mode1. |
2569 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 |
| 2570 | * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check |
2570 | * @retval None |
| 2571 | * whether or not a timer instance supports external clock mode2. |
2571 | */ |
| 2572 | * @rmtoll SMCR SMS LL_TIM_SetClockSource\n |
2572 | __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) |
| 2573 | * SMCR ECE LL_TIM_SetClockSource |
2573 | { |
| 2574 | * @param TIMx Timer instance |
2574 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); |
| 2575 | * @param ClockSource This parameter can be one of the following values: |
2575 | } |
| 2576 | * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL |
2576 | |
| 2577 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 |
2577 | /** |
| 2578 | * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 |
2578 | * @brief Set the encoder interface mode. |
| 2579 | * @retval None |
2579 | * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check |
| 2580 | */ |
2580 | * whether or not a timer instance supports the encoder mode. |
| 2581 | __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) |
2581 | * @rmtoll SMCR SMS LL_TIM_SetEncoderMode |
| 2582 | { |
2582 | * @param TIMx Timer instance |
| 2583 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); |
2583 | * @param EncoderMode This parameter can be one of the following values: |
| 2584 | } |
2584 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 |
| 2585 | 2585 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 |
|
| 2586 | /** |
2586 | * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 |
| 2587 | * @brief Set the encoder interface mode. |
2587 | * @retval None |
| 2588 | * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check |
2588 | */ |
| 2589 | * whether or not a timer instance supports the encoder mode. |
2589 | __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) |
| 2590 | * @rmtoll SMCR SMS LL_TIM_SetEncoderMode |
2590 | { |
| 2591 | * @param TIMx Timer instance |
2591 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); |
| 2592 | * @param EncoderMode This parameter can be one of the following values: |
2592 | } |
| 2593 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 |
2593 | |
| 2594 | * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 |
2594 | /** |
| 2595 | * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 |
2595 | * @} |
| 2596 | * @retval None |
2596 | */ |
| 2597 | */ |
2597 | |
| 2598 | __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) |
2598 | /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration |
| 2599 | { |
2599 | * @{ |
| 2600 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); |
2600 | */ |
| 2601 | } |
2601 | /** |
| 2602 | 2602 | * @brief Set the trigger output (TRGO) used for timer synchronization . |
|
| 2603 | /** |
2603 | * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check |
| 2604 | * @} |
2604 | * whether or not a timer instance can operate as a master timer. |
| 2605 | */ |
2605 | * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput |
| 2606 | 2606 | * @param TIMx Timer instance |
|
| 2607 | /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration |
2607 | * @param TimerSynchronization This parameter can be one of the following values: |
| 2608 | * @{ |
2608 | * @arg @ref LL_TIM_TRGO_RESET |
| 2609 | */ |
2609 | * @arg @ref LL_TIM_TRGO_ENABLE |
| 2610 | /** |
2610 | * @arg @ref LL_TIM_TRGO_UPDATE |
| 2611 | * @brief Set the trigger output (TRGO) used for timer synchronization . |
2611 | * @arg @ref LL_TIM_TRGO_CC1IF |
| 2612 | * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check |
2612 | * @arg @ref LL_TIM_TRGO_OC1REF |
| 2613 | * whether or not a timer instance can operate as a master timer. |
2613 | * @arg @ref LL_TIM_TRGO_OC2REF |
| 2614 | * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput |
2614 | * @arg @ref LL_TIM_TRGO_OC3REF |
| 2615 | * @param TIMx Timer instance |
2615 | * @arg @ref LL_TIM_TRGO_OC4REF |
| 2616 | * @param TimerSynchronization This parameter can be one of the following values: |
2616 | * @retval None |
| 2617 | * @arg @ref LL_TIM_TRGO_RESET |
2617 | */ |
| 2618 | * @arg @ref LL_TIM_TRGO_ENABLE |
2618 | __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) |
| 2619 | * @arg @ref LL_TIM_TRGO_UPDATE |
2619 | { |
| 2620 | * @arg @ref LL_TIM_TRGO_CC1IF |
2620 | MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); |
| 2621 | * @arg @ref LL_TIM_TRGO_OC1REF |
2621 | } |
| 2622 | * @arg @ref LL_TIM_TRGO_OC2REF |
2622 | |
| 2623 | * @arg @ref LL_TIM_TRGO_OC3REF |
2623 | /** |
| 2624 | * @arg @ref LL_TIM_TRGO_OC4REF |
2624 | * @brief Set the synchronization mode of a slave timer. |
| 2625 | * @retval None |
2625 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| 2626 | */ |
2626 | * a timer instance can operate as a slave timer. |
| 2627 | __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) |
2627 | * @rmtoll SMCR SMS LL_TIM_SetSlaveMode |
| 2628 | { |
2628 | * @param TIMx Timer instance |
| 2629 | MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); |
2629 | * @param SlaveMode This parameter can be one of the following values: |
| 2630 | } |
2630 | * @arg @ref LL_TIM_SLAVEMODE_DISABLED |
| 2631 | 2631 | * @arg @ref LL_TIM_SLAVEMODE_RESET |
|
| 2632 | /** |
2632 | * @arg @ref LL_TIM_SLAVEMODE_GATED |
| 2633 | * @brief Set the synchronization mode of a slave timer. |
2633 | * @arg @ref LL_TIM_SLAVEMODE_TRIGGER |
| 2634 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
2634 | * @retval None |
| 2635 | * a timer instance can operate as a slave timer. |
2635 | */ |
| 2636 | * @rmtoll SMCR SMS LL_TIM_SetSlaveMode |
2636 | __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) |
| 2637 | * @param TIMx Timer instance |
2637 | { |
| 2638 | * @param SlaveMode This parameter can be one of the following values: |
2638 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); |
| 2639 | * @arg @ref LL_TIM_SLAVEMODE_DISABLED |
2639 | } |
| 2640 | * @arg @ref LL_TIM_SLAVEMODE_RESET |
2640 | |
| 2641 | * @arg @ref LL_TIM_SLAVEMODE_GATED |
2641 | /** |
| 2642 | * @arg @ref LL_TIM_SLAVEMODE_TRIGGER |
2642 | * @brief Set the selects the trigger input to be used to synchronize the counter. |
| 2643 | * @retval None |
2643 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| 2644 | */ |
2644 | * a timer instance can operate as a slave timer. |
| 2645 | __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) |
2645 | * @rmtoll SMCR TS LL_TIM_SetTriggerInput |
| 2646 | { |
2646 | * @param TIMx Timer instance |
| 2647 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); |
2647 | * @param TriggerInput This parameter can be one of the following values: |
| 2648 | } |
2648 | * @arg @ref LL_TIM_TS_ITR0 |
| 2649 | 2649 | * @arg @ref LL_TIM_TS_ITR1 |
|
| 2650 | /** |
2650 | * @arg @ref LL_TIM_TS_ITR2 |
| 2651 | * @brief Set the selects the trigger input to be used to synchronize the counter. |
2651 | * @arg @ref LL_TIM_TS_ITR3 |
| 2652 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
2652 | * @arg @ref LL_TIM_TS_TI1F_ED |
| 2653 | * a timer instance can operate as a slave timer. |
2653 | * @arg @ref LL_TIM_TS_TI1FP1 |
| 2654 | * @rmtoll SMCR TS LL_TIM_SetTriggerInput |
2654 | * @arg @ref LL_TIM_TS_TI2FP2 |
| 2655 | * @param TIMx Timer instance |
2655 | * @arg @ref LL_TIM_TS_ETRF |
| 2656 | * @param TriggerInput This parameter can be one of the following values: |
2656 | * @retval None |
| 2657 | * @arg @ref LL_TIM_TS_ITR0 |
2657 | */ |
| 2658 | * @arg @ref LL_TIM_TS_ITR1 |
2658 | __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) |
| 2659 | * @arg @ref LL_TIM_TS_ITR2 |
2659 | { |
| 2660 | * @arg @ref LL_TIM_TS_ITR3 |
2660 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); |
| 2661 | * @arg @ref LL_TIM_TS_TI1F_ED |
2661 | } |
| 2662 | * @arg @ref LL_TIM_TS_TI1FP1 |
2662 | |
| 2663 | * @arg @ref LL_TIM_TS_TI2FP2 |
2663 | /** |
| 2664 | * @arg @ref LL_TIM_TS_ETRF |
2664 | * @brief Enable the Master/Slave mode. |
| 2665 | * @retval None |
2665 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| 2666 | */ |
2666 | * a timer instance can operate as a slave timer. |
| 2667 | __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) |
2667 | * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode |
| 2668 | { |
2668 | * @param TIMx Timer instance |
| 2669 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); |
2669 | * @retval None |
| 2670 | } |
2670 | */ |
| 2671 | 2671 | __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) |
|
| 2672 | /** |
2672 | { |
| 2673 | * @brief Enable the Master/Slave mode. |
2673 | SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
| 2674 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
2674 | } |
| 2675 | * a timer instance can operate as a slave timer. |
2675 | |
| 2676 | * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode |
2676 | /** |
| 2677 | * @param TIMx Timer instance |
2677 | * @brief Disable the Master/Slave mode. |
| 2678 | * @retval None |
2678 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| 2679 | */ |
2679 | * a timer instance can operate as a slave timer. |
| 2680 | __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) |
2680 | * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode |
| 2681 | { |
2681 | * @param TIMx Timer instance |
| 2682 | SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
2682 | * @retval None |
| 2683 | } |
2683 | */ |
| 2684 | 2684 | __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) |
|
| 2685 | /** |
2685 | { |
| 2686 | * @brief Disable the Master/Slave mode. |
2686 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
| 2687 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
2687 | } |
| 2688 | * a timer instance can operate as a slave timer. |
2688 | |
| 2689 | * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode |
2689 | /** |
| 2690 | * @param TIMx Timer instance |
2690 | * @brief Indicates whether the Master/Slave mode is enabled. |
| 2691 | * @retval None |
2691 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
| 2692 | */ |
2692 | * a timer instance can operate as a slave timer. |
| 2693 | __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) |
2693 | * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode |
| 2694 | { |
2694 | * @param TIMx Timer instance |
| 2695 | CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); |
2695 | * @retval State of bit (1 or 0). |
| 2696 | } |
2696 | */ |
| 2697 | 2697 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx) |
|
| 2698 | /** |
2698 | { |
| 2699 | * @brief Indicates whether the Master/Slave mode is enabled. |
2699 | return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); |
| 2700 | * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not |
2700 | } |
| 2701 | * a timer instance can operate as a slave timer. |
2701 | |
| 2702 | * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode |
2702 | /** |
| 2703 | * @param TIMx Timer instance |
2703 | * @brief Configure the external trigger (ETR) input. |
| 2704 | * @retval State of bit (1 or 0). |
2704 | * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not |
| 2705 | */ |
2705 | * a timer instance provides an external trigger input. |
| 2706 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) |
2706 | * @rmtoll SMCR ETP LL_TIM_ConfigETR\n |
| 2707 | { |
2707 | * SMCR ETPS LL_TIM_ConfigETR\n |
| 2708 | return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); |
2708 | * SMCR ETF LL_TIM_ConfigETR |
| 2709 | } |
2709 | * @param TIMx Timer instance |
| 2710 | 2710 | * @param ETRPolarity This parameter can be one of the following values: |
|
| 2711 | /** |
2711 | * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED |
| 2712 | * @brief Configure the external trigger (ETR) input. |
2712 | * @arg @ref LL_TIM_ETR_POLARITY_INVERTED |
| 2713 | * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not |
2713 | * @param ETRPrescaler This parameter can be one of the following values: |
| 2714 | * a timer instance provides an external trigger input. |
2714 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 |
| 2715 | * @rmtoll SMCR ETP LL_TIM_ConfigETR\n |
2715 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 |
| 2716 | * SMCR ETPS LL_TIM_ConfigETR\n |
2716 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 |
| 2717 | * SMCR ETF LL_TIM_ConfigETR |
2717 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 |
| 2718 | * @param TIMx Timer instance |
2718 | * @param ETRFilter This parameter can be one of the following values: |
| 2719 | * @param ETRPolarity This parameter can be one of the following values: |
2719 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1 |
| 2720 | * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED |
2720 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 |
| 2721 | * @arg @ref LL_TIM_ETR_POLARITY_INVERTED |
2721 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 |
| 2722 | * @param ETRPrescaler This parameter can be one of the following values: |
2722 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 |
| 2723 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 |
2723 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 |
| 2724 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 |
2724 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 |
| 2725 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 |
2725 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 |
| 2726 | * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 |
2726 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 |
| 2727 | * @param ETRFilter This parameter can be one of the following values: |
2727 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 |
| 2728 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1 |
2728 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 |
| 2729 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 |
2729 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 |
| 2730 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 |
2730 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 |
| 2731 | * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 |
2731 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 |
| 2732 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 |
2732 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 |
| 2733 | * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 |
2733 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 |
| 2734 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 |
2734 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 |
| 2735 | * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 |
2735 | * @retval None |
| 2736 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 |
2736 | */ |
| 2737 | * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 |
2737 | __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, |
| 2738 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 |
2738 | uint32_t ETRFilter) |
| 2739 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 |
2739 | { |
| 2740 | * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 |
2740 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); |
| 2741 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 |
2741 | } |
| 2742 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 |
2742 | |
| 2743 | * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 |
2743 | /** |
| 2744 | * @retval None |
2744 | * @} |
| 2745 | */ |
2745 | */ |
| 2746 | __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, |
2746 | |
| 2747 | uint32_t ETRFilter) |
2747 | /** @defgroup TIM_LL_EF_Break_Function Break function configuration |
| 2748 | { |
2748 | * @{ |
| 2749 | MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); |
2749 | */ |
| 2750 | } |
2750 | /** |
| 2751 | 2751 | * @brief Enable the break function. |
|
| 2752 | /** |
2752 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 2753 | * @} |
2753 | * a timer instance provides a break input. |
| 2754 | */ |
2754 | * @rmtoll BDTR BKE LL_TIM_EnableBRK |
| 2755 | 2755 | * @param TIMx Timer instance |
|
| 2756 | /** @defgroup TIM_LL_EF_Break_Function Break function configuration |
2756 | * @retval None |
| 2757 | * @{ |
2757 | */ |
| 2758 | */ |
2758 | __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) |
| 2759 | /** |
2759 | { |
| 2760 | * @brief Enable the break function. |
2760 | __IO uint32_t tmpreg; |
| 2761 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
2761 | SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); |
| 2762 | * a timer instance provides a break input. |
2762 | /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ |
| 2763 | * @rmtoll BDTR BKE LL_TIM_EnableBRK |
2763 | tmpreg = READ_REG(TIMx->BDTR); |
| 2764 | * @param TIMx Timer instance |
2764 | (void)(tmpreg); |
| 2765 | * @retval None |
2765 | } |
| 2766 | */ |
2766 | |
| 2767 | __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) |
2767 | /** |
| 2768 | { |
2768 | * @brief Disable the break function. |
| 2769 | __IO uint32_t tmpreg; |
2769 | * @rmtoll BDTR BKE LL_TIM_DisableBRK |
| 2770 | SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); |
2770 | * @param TIMx Timer instance |
| 2771 | /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ |
2771 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 2772 | tmpreg = READ_REG(TIMx->BDTR); |
2772 | * a timer instance provides a break input. |
| 2773 | (void)(tmpreg); |
2773 | * @retval None |
| 2774 | } |
2774 | */ |
| 2775 | 2775 | __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) |
|
| 2776 | /** |
2776 | { |
| 2777 | * @brief Disable the break function. |
2777 | __IO uint32_t tmpreg; |
| 2778 | * @rmtoll BDTR BKE LL_TIM_DisableBRK |
2778 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); |
| 2779 | * @param TIMx Timer instance |
2779 | /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ |
| 2780 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
2780 | tmpreg = READ_REG(TIMx->BDTR); |
| 2781 | * a timer instance provides a break input. |
2781 | (void)(tmpreg); |
| 2782 | * @retval None |
2782 | } |
| 2783 | */ |
2783 | |
| 2784 | __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) |
2784 | /** |
| 2785 | { |
2785 | * @brief Configure the break input. |
| 2786 | __IO uint32_t tmpreg; |
2786 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 2787 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); |
2787 | * a timer instance provides a break input. |
| 2788 | /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ |
2788 | * @rmtoll BDTR BKP LL_TIM_ConfigBRK |
| 2789 | tmpreg = READ_REG(TIMx->BDTR); |
2789 | * @param TIMx Timer instance |
| 2790 | (void)(tmpreg); |
2790 | * @param BreakPolarity This parameter can be one of the following values: |
| 2791 | } |
2791 | * @arg @ref LL_TIM_BREAK_POLARITY_LOW |
| 2792 | 2792 | * @arg @ref LL_TIM_BREAK_POLARITY_HIGH |
|
| 2793 | /** |
2793 | * @retval None |
| 2794 | * @brief Configure the break input. |
2794 | */ |
| 2795 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
2795 | __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) |
| 2796 | * a timer instance provides a break input. |
2796 | { |
| 2797 | * @rmtoll BDTR BKP LL_TIM_ConfigBRK |
2797 | __IO uint32_t tmpreg; |
| 2798 | * @param TIMx Timer instance |
2798 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); |
| 2799 | * @param BreakPolarity This parameter can be one of the following values: |
2799 | /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */ |
| 2800 | * @arg @ref LL_TIM_BREAK_POLARITY_LOW |
2800 | tmpreg = READ_REG(TIMx->BDTR); |
| 2801 | * @arg @ref LL_TIM_BREAK_POLARITY_HIGH |
2801 | (void)(tmpreg); |
| 2802 | * @retval None |
2802 | } |
| 2803 | */ |
2803 | |
| 2804 | __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) |
2804 | /** |
| 2805 | { |
2805 | * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. |
| 2806 | __IO uint32_t tmpreg; |
2806 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 2807 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); |
2807 | * a timer instance provides a break input. |
| 2808 | /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */ |
2808 | * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n |
| 2809 | tmpreg = READ_REG(TIMx->BDTR); |
2809 | * BDTR OSSR LL_TIM_SetOffStates |
| 2810 | (void)(tmpreg); |
2810 | * @param TIMx Timer instance |
| 2811 | } |
2811 | * @param OffStateIdle This parameter can be one of the following values: |
| 2812 | 2812 | * @arg @ref LL_TIM_OSSI_DISABLE |
|
| 2813 | /** |
2813 | * @arg @ref LL_TIM_OSSI_ENABLE |
| 2814 | * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. |
2814 | * @param OffStateRun This parameter can be one of the following values: |
| 2815 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
2815 | * @arg @ref LL_TIM_OSSR_DISABLE |
| 2816 | * a timer instance provides a break input. |
2816 | * @arg @ref LL_TIM_OSSR_ENABLE |
| 2817 | * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n |
2817 | * @retval None |
| 2818 | * BDTR OSSR LL_TIM_SetOffStates |
2818 | */ |
| 2819 | * @param TIMx Timer instance |
2819 | __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) |
| 2820 | * @param OffStateIdle This parameter can be one of the following values: |
2820 | { |
| 2821 | * @arg @ref LL_TIM_OSSI_DISABLE |
2821 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); |
| 2822 | * @arg @ref LL_TIM_OSSI_ENABLE |
2822 | } |
| 2823 | * @param OffStateRun This parameter can be one of the following values: |
2823 | |
| 2824 | * @arg @ref LL_TIM_OSSR_DISABLE |
2824 | /** |
| 2825 | * @arg @ref LL_TIM_OSSR_ENABLE |
2825 | * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). |
| 2826 | * @retval None |
2826 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 2827 | */ |
2827 | * a timer instance provides a break input. |
| 2828 | __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) |
2828 | * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput |
| 2829 | { |
2829 | * @param TIMx Timer instance |
| 2830 | MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); |
2830 | * @retval None |
| 2831 | } |
2831 | */ |
| 2832 | 2832 | __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) |
|
| 2833 | /** |
2833 | { |
| 2834 | * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). |
2834 | SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); |
| 2835 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
2835 | } |
| 2836 | * a timer instance provides a break input. |
2836 | |
| 2837 | * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput |
2837 | /** |
| 2838 | * @param TIMx Timer instance |
2838 | * @brief Disable automatic output (MOE can be set only by software). |
| 2839 | * @retval None |
2839 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 2840 | */ |
2840 | * a timer instance provides a break input. |
| 2841 | __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) |
2841 | * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput |
| 2842 | { |
2842 | * @param TIMx Timer instance |
| 2843 | SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); |
2843 | * @retval None |
| 2844 | } |
2844 | */ |
| 2845 | 2845 | __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) |
|
| 2846 | /** |
2846 | { |
| 2847 | * @brief Disable automatic output (MOE can be set only by software). |
2847 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); |
| 2848 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
2848 | } |
| 2849 | * a timer instance provides a break input. |
2849 | |
| 2850 | * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput |
2850 | /** |
| 2851 | * @param TIMx Timer instance |
2851 | * @brief Indicate whether automatic output is enabled. |
| 2852 | * @retval None |
2852 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 2853 | */ |
2853 | * a timer instance provides a break input. |
| 2854 | __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) |
2854 | * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput |
| 2855 | { |
2855 | * @param TIMx Timer instance |
| 2856 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); |
2856 | * @retval State of bit (1 or 0). |
| 2857 | } |
2857 | */ |
| 2858 | 2858 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx) |
|
| 2859 | /** |
2859 | { |
| 2860 | * @brief Indicate whether automatic output is enabled. |
2860 | return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); |
| 2861 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
2861 | } |
| 2862 | * a timer instance provides a break input. |
2862 | |
| 2863 | * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput |
2863 | /** |
| 2864 | * @param TIMx Timer instance |
2864 | * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). |
| 2865 | * @retval State of bit (1 or 0). |
2865 | * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by |
| 2866 | */ |
2866 | * software and is reset in case of break or break2 event |
| 2867 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) |
2867 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 2868 | { |
2868 | * a timer instance provides a break input. |
| 2869 | return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); |
2869 | * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs |
| 2870 | } |
2870 | * @param TIMx Timer instance |
| 2871 | 2871 | * @retval None |
|
| 2872 | /** |
2872 | */ |
| 2873 | * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). |
2873 | __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) |
| 2874 | * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by |
2874 | { |
| 2875 | * software and is reset in case of break or break2 event |
2875 | SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); |
| 2876 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
2876 | } |
| 2877 | * a timer instance provides a break input. |
2877 | |
| 2878 | * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs |
2878 | /** |
| 2879 | * @param TIMx Timer instance |
2879 | * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). |
| 2880 | * @retval None |
2880 | * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by |
| 2881 | */ |
2881 | * software and is reset in case of break or break2 event. |
| 2882 | __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) |
2882 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 2883 | { |
2883 | * a timer instance provides a break input. |
| 2884 | SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); |
2884 | * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs |
| 2885 | } |
2885 | * @param TIMx Timer instance |
| 2886 | 2886 | * @retval None |
|
| 2887 | /** |
2887 | */ |
| 2888 | * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). |
2888 | __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) |
| 2889 | * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by |
2889 | { |
| 2890 | * software and is reset in case of break or break2 event. |
2890 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); |
| 2891 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
2891 | } |
| 2892 | * a timer instance provides a break input. |
2892 | |
| 2893 | * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs |
2893 | /** |
| 2894 | * @param TIMx Timer instance |
2894 | * @brief Indicates whether outputs are enabled. |
| 2895 | * @retval None |
2895 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
| 2896 | */ |
2896 | * a timer instance provides a break input. |
| 2897 | __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) |
2897 | * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs |
| 2898 | { |
2898 | * @param TIMx Timer instance |
| 2899 | CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); |
2899 | * @retval State of bit (1 or 0). |
| 2900 | } |
2900 | */ |
| 2901 | 2901 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx) |
|
| 2902 | /** |
2902 | { |
| 2903 | * @brief Indicates whether outputs are enabled. |
2903 | return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); |
| 2904 | * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not |
2904 | } |
| 2905 | * a timer instance provides a break input. |
2905 | |
| 2906 | * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs |
2906 | /** |
| 2907 | * @param TIMx Timer instance |
2907 | * @} |
| 2908 | * @retval State of bit (1 or 0). |
2908 | */ |
| 2909 | */ |
2909 | |
| 2910 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) |
2910 | /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration |
| 2911 | { |
2911 | * @{ |
| 2912 | return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); |
2912 | */ |
| 2913 | } |
2913 | /** |
| 2914 | 2914 | * @brief Configures the timer DMA burst feature. |
|
| 2915 | /** |
2915 | * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or |
| 2916 | * @} |
2916 | * not a timer instance supports the DMA burst mode. |
| 2917 | */ |
2917 | * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n |
| 2918 | 2918 | * DCR DBA LL_TIM_ConfigDMABurst |
|
| 2919 | /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration |
2919 | * @param TIMx Timer instance |
| 2920 | * @{ |
2920 | * @param DMABurstBaseAddress This parameter can be one of the following values: |
| 2921 | */ |
2921 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 |
| 2922 | /** |
2922 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 |
| 2923 | * @brief Configures the timer DMA burst feature. |
2923 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR |
| 2924 | * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or |
2924 | * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER |
| 2925 | * not a timer instance supports the DMA burst mode. |
2925 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SR |
| 2926 | * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n |
2926 | * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR |
| 2927 | * DCR DBA LL_TIM_ConfigDMABurst |
2927 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 |
| 2928 | * @param TIMx Timer instance |
2928 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 |
| 2929 | * @param DMABurstBaseAddress This parameter can be one of the following values: |
2929 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER |
| 2930 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 |
2930 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT |
| 2931 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 |
2931 | * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC |
| 2932 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR |
2932 | * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR |
| 2933 | * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER |
2933 | * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR |
| 2934 | * @arg @ref LL_TIM_DMABURST_BASEADDR_SR |
2934 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 |
| 2935 | * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR |
2935 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 |
| 2936 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 |
2936 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 |
| 2937 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 |
2937 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 |
| 2938 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER |
2938 | * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR |
| 2939 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT |
2939 | * @param DMABurstLength This parameter can be one of the following values: |
| 2940 | * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC |
2940 | * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER |
| 2941 | * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR |
2941 | * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS |
| 2942 | * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR |
2942 | * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS |
| 2943 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 |
2943 | * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS |
| 2944 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 |
2944 | * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS |
| 2945 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 |
2945 | * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS |
| 2946 | * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 |
2946 | * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS |
| 2947 | * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR |
2947 | * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS |
| 2948 | * @param DMABurstLength This parameter can be one of the following values: |
2948 | * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS |
| 2949 | * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER |
2949 | * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS |
| 2950 | * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS |
2950 | * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS |
| 2951 | * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS |
2951 | * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS |
| 2952 | * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS |
2952 | * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS |
| 2953 | * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS |
2953 | * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS |
| 2954 | * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS |
2954 | * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS |
| 2955 | * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS |
2955 | * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS |
| 2956 | * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS |
2956 | * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS |
| 2957 | * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS |
2957 | * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS |
| 2958 | * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS |
2958 | * @retval None |
| 2959 | * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS |
2959 | */ |
| 2960 | * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS |
2960 | __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) |
| 2961 | * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS |
2961 | { |
| 2962 | * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS |
2962 | MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); |
| 2963 | * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS |
2963 | } |
| 2964 | * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS |
2964 | |
| 2965 | * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS |
2965 | /** |
| 2966 | * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS |
2966 | * @} |
| 2967 | * @retval None |
2967 | */ |
| 2968 | */ |
2968 | |
| 2969 | __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) |
2969 | |
| 2970 | { |
2970 | /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management |
| 2971 | MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); |
2971 | * @{ |
| 2972 | } |
2972 | */ |
| 2973 | 2973 | /** |
|
| 2974 | /** |
2974 | * @brief Clear the update interrupt flag (UIF). |
| 2975 | * @} |
2975 | * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE |
| 2976 | */ |
2976 | * @param TIMx Timer instance |
| 2977 | 2977 | * @retval None |
|
| 2978 | 2978 | */ |
|
| 2979 | /** |
2979 | __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) |
| 2980 | * @} |
2980 | { |
| 2981 | */ |
2981 | WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); |
| 2982 | 2982 | } |
|
| 2983 | /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management |
2983 | |
| 2984 | * @{ |
2984 | /** |
| 2985 | */ |
2985 | * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). |
| 2986 | /** |
2986 | * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE |
| 2987 | * @brief Clear the update interrupt flag (UIF). |
2987 | * @param TIMx Timer instance |
| 2988 | * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE |
2988 | * @retval State of bit (1 or 0). |
| 2989 | * @param TIMx Timer instance |
2989 | */ |
| 2990 | * @retval None |
2990 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx) |
| 2991 | */ |
2991 | { |
| 2992 | __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) |
2992 | return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); |
| 2993 | { |
2993 | } |
| 2994 | WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); |
2994 | |
| 2995 | } |
2995 | /** |
| 2996 | 2996 | * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). |
|
| 2997 | /** |
2997 | * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 |
| 2998 | * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). |
2998 | * @param TIMx Timer instance |
| 2999 | * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE |
2999 | * @retval None |
| 3000 | * @param TIMx Timer instance |
3000 | */ |
| 3001 | * @retval State of bit (1 or 0). |
3001 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) |
| 3002 | */ |
3002 | { |
| 3003 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) |
3003 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); |
| 3004 | { |
3004 | } |
| 3005 | return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); |
3005 | |
| 3006 | } |
3006 | /** |
| 3007 | 3007 | * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). |
|
| 3008 | /** |
3008 | * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 |
| 3009 | * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). |
3009 | * @param TIMx Timer instance |
| 3010 | * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 |
3010 | * @retval State of bit (1 or 0). |
| 3011 | * @param TIMx Timer instance |
3011 | */ |
| 3012 | * @retval None |
3012 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx) |
| 3013 | */ |
3013 | { |
| 3014 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) |
3014 | return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); |
| 3015 | { |
3015 | } |
| 3016 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); |
3016 | |
| 3017 | } |
3017 | /** |
| 3018 | 3018 | * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). |
|
| 3019 | /** |
3019 | * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 |
| 3020 | * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). |
3020 | * @param TIMx Timer instance |
| 3021 | * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 |
3021 | * @retval None |
| 3022 | * @param TIMx Timer instance |
3022 | */ |
| 3023 | * @retval State of bit (1 or 0). |
3023 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) |
| 3024 | */ |
3024 | { |
| 3025 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) |
3025 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); |
| 3026 | { |
3026 | } |
| 3027 | return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); |
3027 | |
| 3028 | } |
3028 | /** |
| 3029 | 3029 | * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). |
|
| 3030 | /** |
3030 | * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 |
| 3031 | * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). |
3031 | * @param TIMx Timer instance |
| 3032 | * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 |
3032 | * @retval State of bit (1 or 0). |
| 3033 | * @param TIMx Timer instance |
3033 | */ |
| 3034 | * @retval None |
3034 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx) |
| 3035 | */ |
3035 | { |
| 3036 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) |
3036 | return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); |
| 3037 | { |
3037 | } |
| 3038 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); |
3038 | |
| 3039 | } |
3039 | /** |
| 3040 | 3040 | * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). |
|
| 3041 | /** |
3041 | * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 |
| 3042 | * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). |
3042 | * @param TIMx Timer instance |
| 3043 | * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 |
3043 | * @retval None |
| 3044 | * @param TIMx Timer instance |
3044 | */ |
| 3045 | * @retval State of bit (1 or 0). |
3045 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) |
| 3046 | */ |
3046 | { |
| 3047 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) |
3047 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); |
| 3048 | { |
3048 | } |
| 3049 | return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); |
3049 | |
| 3050 | } |
3050 | /** |
| 3051 | 3051 | * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). |
|
| 3052 | /** |
3052 | * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 |
| 3053 | * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). |
3053 | * @param TIMx Timer instance |
| 3054 | * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 |
3054 | * @retval State of bit (1 or 0). |
| 3055 | * @param TIMx Timer instance |
3055 | */ |
| 3056 | * @retval None |
3056 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx) |
| 3057 | */ |
3057 | { |
| 3058 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) |
3058 | return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); |
| 3059 | { |
3059 | } |
| 3060 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); |
3060 | |
| 3061 | } |
3061 | /** |
| 3062 | 3062 | * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). |
|
| 3063 | /** |
3063 | * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 |
| 3064 | * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). |
3064 | * @param TIMx Timer instance |
| 3065 | * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 |
3065 | * @retval None |
| 3066 | * @param TIMx Timer instance |
3066 | */ |
| 3067 | * @retval State of bit (1 or 0). |
3067 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) |
| 3068 | */ |
3068 | { |
| 3069 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) |
3069 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); |
| 3070 | { |
3070 | } |
| 3071 | return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); |
3071 | |
| 3072 | } |
3072 | /** |
| 3073 | 3073 | * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). |
|
| 3074 | /** |
3074 | * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 |
| 3075 | * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). |
3075 | * @param TIMx Timer instance |
| 3076 | * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 |
3076 | * @retval State of bit (1 or 0). |
| 3077 | * @param TIMx Timer instance |
3077 | */ |
| 3078 | * @retval None |
3078 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx) |
| 3079 | */ |
3079 | { |
| 3080 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) |
3080 | return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); |
| 3081 | { |
3081 | } |
| 3082 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); |
3082 | |
| 3083 | } |
3083 | /** |
| 3084 | 3084 | * @brief Clear the commutation interrupt flag (COMIF). |
|
| 3085 | /** |
3085 | * @rmtoll SR COMIF LL_TIM_ClearFlag_COM |
| 3086 | * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). |
3086 | * @param TIMx Timer instance |
| 3087 | * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 |
3087 | * @retval None |
| 3088 | * @param TIMx Timer instance |
3088 | */ |
| 3089 | * @retval State of bit (1 or 0). |
3089 | __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) |
| 3090 | */ |
3090 | { |
| 3091 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) |
3091 | WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); |
| 3092 | { |
3092 | } |
| 3093 | return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); |
3093 | |
| 3094 | } |
3094 | /** |
| 3095 | 3095 | * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). |
|
| 3096 | /** |
3096 | * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM |
| 3097 | * @brief Clear the commutation interrupt flag (COMIF). |
3097 | * @param TIMx Timer instance |
| 3098 | * @rmtoll SR COMIF LL_TIM_ClearFlag_COM |
3098 | * @retval State of bit (1 or 0). |
| 3099 | * @param TIMx Timer instance |
3099 | */ |
| 3100 | * @retval None |
3100 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx) |
| 3101 | */ |
3101 | { |
| 3102 | __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) |
3102 | return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); |
| 3103 | { |
3103 | } |
| 3104 | WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); |
3104 | |
| 3105 | } |
3105 | /** |
| 3106 | 3106 | * @brief Clear the trigger interrupt flag (TIF). |
|
| 3107 | /** |
3107 | * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG |
| 3108 | * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). |
3108 | * @param TIMx Timer instance |
| 3109 | * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM |
3109 | * @retval None |
| 3110 | * @param TIMx Timer instance |
3110 | */ |
| 3111 | * @retval State of bit (1 or 0). |
3111 | __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) |
| 3112 | */ |
3112 | { |
| 3113 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) |
3113 | WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); |
| 3114 | { |
3114 | } |
| 3115 | return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); |
3115 | |
| 3116 | } |
3116 | /** |
| 3117 | 3117 | * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). |
|
| 3118 | /** |
3118 | * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG |
| 3119 | * @brief Clear the trigger interrupt flag (TIF). |
3119 | * @param TIMx Timer instance |
| 3120 | * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG |
3120 | * @retval State of bit (1 or 0). |
| 3121 | * @param TIMx Timer instance |
3121 | */ |
| 3122 | * @retval None |
3122 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx) |
| 3123 | */ |
3123 | { |
| 3124 | __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) |
3124 | return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); |
| 3125 | { |
3125 | } |
| 3126 | WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); |
3126 | |
| 3127 | } |
3127 | /** |
| 3128 | 3128 | * @brief Clear the break interrupt flag (BIF). |
|
| 3129 | /** |
3129 | * @rmtoll SR BIF LL_TIM_ClearFlag_BRK |
| 3130 | * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). |
3130 | * @param TIMx Timer instance |
| 3131 | * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG |
3131 | * @retval None |
| 3132 | * @param TIMx Timer instance |
3132 | */ |
| 3133 | * @retval State of bit (1 or 0). |
3133 | __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) |
| 3134 | */ |
3134 | { |
| 3135 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) |
3135 | WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); |
| 3136 | { |
3136 | } |
| 3137 | return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); |
3137 | |
| 3138 | } |
3138 | /** |
| 3139 | 3139 | * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). |
|
| 3140 | /** |
3140 | * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK |
| 3141 | * @brief Clear the break interrupt flag (BIF). |
3141 | * @param TIMx Timer instance |
| 3142 | * @rmtoll SR BIF LL_TIM_ClearFlag_BRK |
3142 | * @retval State of bit (1 or 0). |
| 3143 | * @param TIMx Timer instance |
3143 | */ |
| 3144 | * @retval None |
3144 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx) |
| 3145 | */ |
3145 | { |
| 3146 | __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) |
3146 | return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); |
| 3147 | { |
3147 | } |
| 3148 | WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); |
3148 | |
| 3149 | } |
3149 | /** |
| 3150 | 3150 | * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). |
|
| 3151 | /** |
3151 | * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR |
| 3152 | * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). |
3152 | * @param TIMx Timer instance |
| 3153 | * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK |
3153 | * @retval None |
| 3154 | * @param TIMx Timer instance |
3154 | */ |
| 3155 | * @retval State of bit (1 or 0). |
3155 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) |
| 3156 | */ |
3156 | { |
| 3157 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) |
3157 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); |
| 3158 | { |
3158 | } |
| 3159 | return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); |
3159 | |
| 3160 | } |
3160 | /** |
| 3161 | 3161 | * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set |
|
| 3162 | /** |
3162 | * (Capture/Compare 1 interrupt is pending). |
| 3163 | * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). |
3163 | * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR |
| 3164 | * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR |
3164 | * @param TIMx Timer instance |
| 3165 | * @param TIMx Timer instance |
3165 | * @retval State of bit (1 or 0). |
| 3166 | * @retval None |
3166 | */ |
| 3167 | */ |
3167 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx) |
| 3168 | __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) |
3168 | { |
| 3169 | { |
3169 | return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); |
| 3170 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); |
3170 | } |
| 3171 | } |
3171 | |
| 3172 | 3172 | /** |
|
| 3173 | /** |
3173 | * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). |
| 3174 | * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set |
3174 | * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR |
| 3175 | * (Capture/Compare 1 interrupt is pending). |
3175 | * @param TIMx Timer instance |
| 3176 | * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR |
3176 | * @retval None |
| 3177 | * @param TIMx Timer instance |
3177 | */ |
| 3178 | * @retval State of bit (1 or 0). |
3178 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) |
| 3179 | */ |
3179 | { |
| 3180 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) |
3180 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); |
| 3181 | { |
3181 | } |
| 3182 | return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); |
3182 | |
| 3183 | } |
3183 | /** |
| 3184 | 3184 | * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set |
|
| 3185 | /** |
3185 | * (Capture/Compare 2 over-capture interrupt is pending). |
| 3186 | * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). |
3186 | * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR |
| 3187 | * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR |
3187 | * @param TIMx Timer instance |
| 3188 | * @param TIMx Timer instance |
3188 | * @retval State of bit (1 or 0). |
| 3189 | * @retval None |
3189 | */ |
| 3190 | */ |
3190 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx) |
| 3191 | __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) |
3191 | { |
| 3192 | { |
3192 | return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); |
| 3193 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); |
3193 | } |
| 3194 | } |
3194 | |
| 3195 | 3195 | /** |
|
| 3196 | /** |
3196 | * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). |
| 3197 | * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set |
3197 | * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR |
| 3198 | * (Capture/Compare 2 over-capture interrupt is pending). |
3198 | * @param TIMx Timer instance |
| 3199 | * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR |
3199 | * @retval None |
| 3200 | * @param TIMx Timer instance |
3200 | */ |
| 3201 | * @retval State of bit (1 or 0). |
3201 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) |
| 3202 | */ |
3202 | { |
| 3203 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) |
3203 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); |
| 3204 | { |
3204 | } |
| 3205 | return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); |
3205 | |
| 3206 | } |
3206 | /** |
| 3207 | 3207 | * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set |
|
| 3208 | /** |
3208 | * (Capture/Compare 3 over-capture interrupt is pending). |
| 3209 | * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). |
3209 | * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR |
| 3210 | * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR |
3210 | * @param TIMx Timer instance |
| 3211 | * @param TIMx Timer instance |
3211 | * @retval State of bit (1 or 0). |
| 3212 | * @retval None |
3212 | */ |
| 3213 | */ |
3213 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx) |
| 3214 | __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) |
3214 | { |
| 3215 | { |
3215 | return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); |
| 3216 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); |
3216 | } |
| 3217 | } |
3217 | |
| 3218 | 3218 | /** |
|
| 3219 | /** |
3219 | * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). |
| 3220 | * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set |
3220 | * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR |
| 3221 | * (Capture/Compare 3 over-capture interrupt is pending). |
3221 | * @param TIMx Timer instance |
| 3222 | * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR |
3222 | * @retval None |
| 3223 | * @param TIMx Timer instance |
3223 | */ |
| 3224 | * @retval State of bit (1 or 0). |
3224 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) |
| 3225 | */ |
3225 | { |
| 3226 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) |
3226 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); |
| 3227 | { |
3227 | } |
| 3228 | return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); |
3228 | |
| 3229 | } |
3229 | /** |
| 3230 | 3230 | * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set |
|
| 3231 | /** |
3231 | * (Capture/Compare 4 over-capture interrupt is pending). |
| 3232 | * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). |
3232 | * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR |
| 3233 | * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR |
3233 | * @param TIMx Timer instance |
| 3234 | * @param TIMx Timer instance |
3234 | * @retval State of bit (1 or 0). |
| 3235 | * @retval None |
3235 | */ |
| 3236 | */ |
3236 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx) |
| 3237 | __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) |
3237 | { |
| 3238 | { |
3238 | return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); |
| 3239 | WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); |
3239 | } |
| 3240 | } |
3240 | |
| 3241 | 3241 | /** |
|
| 3242 | /** |
3242 | * @} |
| 3243 | * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set |
3243 | */ |
| 3244 | * (Capture/Compare 4 over-capture interrupt is pending). |
3244 | |
| 3245 | * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR |
3245 | /** @defgroup TIM_LL_EF_IT_Management IT-Management |
| 3246 | * @param TIMx Timer instance |
3246 | * @{ |
| 3247 | * @retval State of bit (1 or 0). |
3247 | */ |
| 3248 | */ |
3248 | /** |
| 3249 | __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) |
3249 | * @brief Enable update interrupt (UIE). |
| 3250 | { |
3250 | * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE |
| 3251 | return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); |
3251 | * @param TIMx Timer instance |
| 3252 | } |
3252 | * @retval None |
| 3253 | 3253 | */ |
|
| 3254 | /** |
3254 | __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) |
| 3255 | * @} |
3255 | { |
| 3256 | */ |
3256 | SET_BIT(TIMx->DIER, TIM_DIER_UIE); |
| 3257 | 3257 | } |
|
| 3258 | /** @defgroup TIM_LL_EF_IT_Management IT-Management |
3258 | |
| 3259 | * @{ |
3259 | /** |
| 3260 | */ |
3260 | * @brief Disable update interrupt (UIE). |
| 3261 | /** |
3261 | * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE |
| 3262 | * @brief Enable update interrupt (UIE). |
3262 | * @param TIMx Timer instance |
| 3263 | * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE |
3263 | * @retval None |
| 3264 | * @param TIMx Timer instance |
3264 | */ |
| 3265 | * @retval None |
3265 | __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) |
| 3266 | */ |
3266 | { |
| 3267 | __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) |
3267 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); |
| 3268 | { |
3268 | } |
| 3269 | SET_BIT(TIMx->DIER, TIM_DIER_UIE); |
3269 | |
| 3270 | } |
3270 | /** |
| 3271 | 3271 | * @brief Indicates whether the update interrupt (UIE) is enabled. |
|
| 3272 | /** |
3272 | * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE |
| 3273 | * @brief Disable update interrupt (UIE). |
3273 | * @param TIMx Timer instance |
| 3274 | * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE |
3274 | * @retval State of bit (1 or 0). |
| 3275 | * @param TIMx Timer instance |
3275 | */ |
| 3276 | * @retval None |
3276 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx) |
| 3277 | */ |
3277 | { |
| 3278 | __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) |
3278 | return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); |
| 3279 | { |
3279 | } |
| 3280 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); |
3280 | |
| 3281 | } |
3281 | /** |
| 3282 | 3282 | * @brief Enable capture/compare 1 interrupt (CC1IE). |
|
| 3283 | /** |
3283 | * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 |
| 3284 | * @brief Indicates whether the update interrupt (UIE) is enabled. |
3284 | * @param TIMx Timer instance |
| 3285 | * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE |
3285 | * @retval None |
| 3286 | * @param TIMx Timer instance |
3286 | */ |
| 3287 | * @retval State of bit (1 or 0). |
3287 | __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) |
| 3288 | */ |
3288 | { |
| 3289 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) |
3289 | SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
| 3290 | { |
3290 | } |
| 3291 | return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); |
3291 | |
| 3292 | } |
3292 | /** |
| 3293 | 3293 | * @brief Disable capture/compare 1 interrupt (CC1IE). |
|
| 3294 | /** |
3294 | * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 |
| 3295 | * @brief Enable capture/compare 1 interrupt (CC1IE). |
3295 | * @param TIMx Timer instance |
| 3296 | * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 |
3296 | * @retval None |
| 3297 | * @param TIMx Timer instance |
3297 | */ |
| 3298 | * @retval None |
3298 | __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) |
| 3299 | */ |
3299 | { |
| 3300 | __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) |
3300 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
| 3301 | { |
3301 | } |
| 3302 | SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
3302 | |
| 3303 | } |
3303 | /** |
| 3304 | 3304 | * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. |
|
| 3305 | /** |
3305 | * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 |
| 3306 | * @brief Disable capture/compare 1 interrupt (CC1IE). |
3306 | * @param TIMx Timer instance |
| 3307 | * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 |
3307 | * @retval State of bit (1 or 0). |
| 3308 | * @param TIMx Timer instance |
3308 | */ |
| 3309 | * @retval None |
3309 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx) |
| 3310 | */ |
3310 | { |
| 3311 | __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) |
3311 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); |
| 3312 | { |
3312 | } |
| 3313 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); |
3313 | |
| 3314 | } |
3314 | /** |
| 3315 | 3315 | * @brief Enable capture/compare 2 interrupt (CC2IE). |
|
| 3316 | /** |
3316 | * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 |
| 3317 | * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. |
3317 | * @param TIMx Timer instance |
| 3318 | * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 |
3318 | * @retval None |
| 3319 | * @param TIMx Timer instance |
3319 | */ |
| 3320 | * @retval State of bit (1 or 0). |
3320 | __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) |
| 3321 | */ |
3321 | { |
| 3322 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) |
3322 | SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
| 3323 | { |
3323 | } |
| 3324 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); |
3324 | |
| 3325 | } |
3325 | /** |
| 3326 | 3326 | * @brief Disable capture/compare 2 interrupt (CC2IE). |
|
| 3327 | /** |
3327 | * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 |
| 3328 | * @brief Enable capture/compare 2 interrupt (CC2IE). |
3328 | * @param TIMx Timer instance |
| 3329 | * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 |
3329 | * @retval None |
| 3330 | * @param TIMx Timer instance |
3330 | */ |
| 3331 | * @retval None |
3331 | __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) |
| 3332 | */ |
3332 | { |
| 3333 | __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) |
3333 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
| 3334 | { |
3334 | } |
| 3335 | SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
3335 | |
| 3336 | } |
3336 | /** |
| 3337 | 3337 | * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. |
|
| 3338 | /** |
3338 | * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 |
| 3339 | * @brief Disable capture/compare 2 interrupt (CC2IE). |
3339 | * @param TIMx Timer instance |
| 3340 | * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 |
3340 | * @retval State of bit (1 or 0). |
| 3341 | * @param TIMx Timer instance |
3341 | */ |
| 3342 | * @retval None |
3342 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx) |
| 3343 | */ |
3343 | { |
| 3344 | __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) |
3344 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); |
| 3345 | { |
3345 | } |
| 3346 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); |
3346 | |
| 3347 | } |
3347 | /** |
| 3348 | 3348 | * @brief Enable capture/compare 3 interrupt (CC3IE). |
|
| 3349 | /** |
3349 | * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 |
| 3350 | * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. |
3350 | * @param TIMx Timer instance |
| 3351 | * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 |
3351 | * @retval None |
| 3352 | * @param TIMx Timer instance |
3352 | */ |
| 3353 | * @retval State of bit (1 or 0). |
3353 | __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) |
| 3354 | */ |
3354 | { |
| 3355 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) |
3355 | SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
| 3356 | { |
3356 | } |
| 3357 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); |
3357 | |
| 3358 | } |
3358 | /** |
| 3359 | 3359 | * @brief Disable capture/compare 3 interrupt (CC3IE). |
|
| 3360 | /** |
3360 | * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 |
| 3361 | * @brief Enable capture/compare 3 interrupt (CC3IE). |
3361 | * @param TIMx Timer instance |
| 3362 | * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 |
3362 | * @retval None |
| 3363 | * @param TIMx Timer instance |
3363 | */ |
| 3364 | * @retval None |
3364 | __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) |
| 3365 | */ |
3365 | { |
| 3366 | __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) |
3366 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
| 3367 | { |
3367 | } |
| 3368 | SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
3368 | |
| 3369 | } |
3369 | /** |
| 3370 | 3370 | * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. |
|
| 3371 | /** |
3371 | * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 |
| 3372 | * @brief Disable capture/compare 3 interrupt (CC3IE). |
3372 | * @param TIMx Timer instance |
| 3373 | * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 |
3373 | * @retval State of bit (1 or 0). |
| 3374 | * @param TIMx Timer instance |
3374 | */ |
| 3375 | * @retval None |
3375 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx) |
| 3376 | */ |
3376 | { |
| 3377 | __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) |
3377 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); |
| 3378 | { |
3378 | } |
| 3379 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); |
3379 | |
| 3380 | } |
3380 | /** |
| 3381 | 3381 | * @brief Enable capture/compare 4 interrupt (CC4IE). |
|
| 3382 | /** |
3382 | * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 |
| 3383 | * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. |
3383 | * @param TIMx Timer instance |
| 3384 | * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 |
3384 | * @retval None |
| 3385 | * @param TIMx Timer instance |
3385 | */ |
| 3386 | * @retval State of bit (1 or 0). |
3386 | __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) |
| 3387 | */ |
3387 | { |
| 3388 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) |
3388 | SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
| 3389 | { |
3389 | } |
| 3390 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); |
3390 | |
| 3391 | } |
3391 | /** |
| 3392 | 3392 | * @brief Disable capture/compare 4 interrupt (CC4IE). |
|
| 3393 | /** |
3393 | * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 |
| 3394 | * @brief Enable capture/compare 4 interrupt (CC4IE). |
3394 | * @param TIMx Timer instance |
| 3395 | * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 |
3395 | * @retval None |
| 3396 | * @param TIMx Timer instance |
3396 | */ |
| 3397 | * @retval None |
3397 | __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) |
| 3398 | */ |
3398 | { |
| 3399 | __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) |
3399 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
| 3400 | { |
3400 | } |
| 3401 | SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
3401 | |
| 3402 | } |
3402 | /** |
| 3403 | 3403 | * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. |
|
| 3404 | /** |
3404 | * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 |
| 3405 | * @brief Disable capture/compare 4 interrupt (CC4IE). |
3405 | * @param TIMx Timer instance |
| 3406 | * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 |
3406 | * @retval State of bit (1 or 0). |
| 3407 | * @param TIMx Timer instance |
3407 | */ |
| 3408 | * @retval None |
3408 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx) |
| 3409 | */ |
3409 | { |
| 3410 | __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) |
3410 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); |
| 3411 | { |
3411 | } |
| 3412 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); |
3412 | |
| 3413 | } |
3413 | /** |
| 3414 | 3414 | * @brief Enable commutation interrupt (COMIE). |
|
| 3415 | /** |
3415 | * @rmtoll DIER COMIE LL_TIM_EnableIT_COM |
| 3416 | * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. |
3416 | * @param TIMx Timer instance |
| 3417 | * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 |
3417 | * @retval None |
| 3418 | * @param TIMx Timer instance |
3418 | */ |
| 3419 | * @retval State of bit (1 or 0). |
3419 | __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) |
| 3420 | */ |
3420 | { |
| 3421 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) |
3421 | SET_BIT(TIMx->DIER, TIM_DIER_COMIE); |
| 3422 | { |
3422 | } |
| 3423 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); |
3423 | |
| 3424 | } |
3424 | /** |
| 3425 | 3425 | * @brief Disable commutation interrupt (COMIE). |
|
| 3426 | /** |
3426 | * @rmtoll DIER COMIE LL_TIM_DisableIT_COM |
| 3427 | * @brief Enable commutation interrupt (COMIE). |
3427 | * @param TIMx Timer instance |
| 3428 | * @rmtoll DIER COMIE LL_TIM_EnableIT_COM |
3428 | * @retval None |
| 3429 | * @param TIMx Timer instance |
3429 | */ |
| 3430 | * @retval None |
3430 | __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) |
| 3431 | */ |
3431 | { |
| 3432 | __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) |
3432 | CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); |
| 3433 | { |
3433 | } |
| 3434 | SET_BIT(TIMx->DIER, TIM_DIER_COMIE); |
3434 | |
| 3435 | } |
3435 | /** |
| 3436 | 3436 | * @brief Indicates whether the commutation interrupt (COMIE) is enabled. |
|
| 3437 | /** |
3437 | * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM |
| 3438 | * @brief Disable commutation interrupt (COMIE). |
3438 | * @param TIMx Timer instance |
| 3439 | * @rmtoll DIER COMIE LL_TIM_DisableIT_COM |
3439 | * @retval State of bit (1 or 0). |
| 3440 | * @param TIMx Timer instance |
3440 | */ |
| 3441 | * @retval None |
3441 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx) |
| 3442 | */ |
3442 | { |
| 3443 | __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) |
3443 | return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); |
| 3444 | { |
3444 | } |
| 3445 | CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); |
3445 | |
| 3446 | } |
3446 | /** |
| 3447 | 3447 | * @brief Enable trigger interrupt (TIE). |
|
| 3448 | /** |
3448 | * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG |
| 3449 | * @brief Indicates whether the commutation interrupt (COMIE) is enabled. |
3449 | * @param TIMx Timer instance |
| 3450 | * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM |
3450 | * @retval None |
| 3451 | * @param TIMx Timer instance |
3451 | */ |
| 3452 | * @retval State of bit (1 or 0). |
3452 | __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) |
| 3453 | */ |
3453 | { |
| 3454 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) |
3454 | SET_BIT(TIMx->DIER, TIM_DIER_TIE); |
| 3455 | { |
3455 | } |
| 3456 | return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); |
3456 | |
| 3457 | } |
3457 | /** |
| 3458 | 3458 | * @brief Disable trigger interrupt (TIE). |
|
| 3459 | /** |
3459 | * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG |
| 3460 | * @brief Enable trigger interrupt (TIE). |
3460 | * @param TIMx Timer instance |
| 3461 | * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG |
3461 | * @retval None |
| 3462 | * @param TIMx Timer instance |
3462 | */ |
| 3463 | * @retval None |
3463 | __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) |
| 3464 | */ |
3464 | { |
| 3465 | __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) |
3465 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); |
| 3466 | { |
3466 | } |
| 3467 | SET_BIT(TIMx->DIER, TIM_DIER_TIE); |
3467 | |
| 3468 | } |
3468 | /** |
| 3469 | 3469 | * @brief Indicates whether the trigger interrupt (TIE) is enabled. |
|
| 3470 | /** |
3470 | * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG |
| 3471 | * @brief Disable trigger interrupt (TIE). |
3471 | * @param TIMx Timer instance |
| 3472 | * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG |
3472 | * @retval State of bit (1 or 0). |
| 3473 | * @param TIMx Timer instance |
3473 | */ |
| 3474 | * @retval None |
3474 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx) |
| 3475 | */ |
3475 | { |
| 3476 | __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) |
3476 | return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); |
| 3477 | { |
3477 | } |
| 3478 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); |
3478 | |
| 3479 | } |
3479 | /** |
| 3480 | 3480 | * @brief Enable break interrupt (BIE). |
|
| 3481 | /** |
3481 | * @rmtoll DIER BIE LL_TIM_EnableIT_BRK |
| 3482 | * @brief Indicates whether the trigger interrupt (TIE) is enabled. |
3482 | * @param TIMx Timer instance |
| 3483 | * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG |
3483 | * @retval None |
| 3484 | * @param TIMx Timer instance |
3484 | */ |
| 3485 | * @retval State of bit (1 or 0). |
3485 | __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) |
| 3486 | */ |
3486 | { |
| 3487 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) |
3487 | SET_BIT(TIMx->DIER, TIM_DIER_BIE); |
| 3488 | { |
3488 | } |
| 3489 | return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); |
3489 | |
| 3490 | } |
3490 | /** |
| 3491 | 3491 | * @brief Disable break interrupt (BIE). |
|
| 3492 | /** |
3492 | * @rmtoll DIER BIE LL_TIM_DisableIT_BRK |
| 3493 | * @brief Enable break interrupt (BIE). |
3493 | * @param TIMx Timer instance |
| 3494 | * @rmtoll DIER BIE LL_TIM_EnableIT_BRK |
3494 | * @retval None |
| 3495 | * @param TIMx Timer instance |
3495 | */ |
| 3496 | * @retval None |
3496 | __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) |
| 3497 | */ |
3497 | { |
| 3498 | __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) |
3498 | CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); |
| 3499 | { |
3499 | } |
| 3500 | SET_BIT(TIMx->DIER, TIM_DIER_BIE); |
3500 | |
| 3501 | } |
3501 | /** |
| 3502 | 3502 | * @brief Indicates whether the break interrupt (BIE) is enabled. |
|
| 3503 | /** |
3503 | * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK |
| 3504 | * @brief Disable break interrupt (BIE). |
3504 | * @param TIMx Timer instance |
| 3505 | * @rmtoll DIER BIE LL_TIM_DisableIT_BRK |
3505 | * @retval State of bit (1 or 0). |
| 3506 | * @param TIMx Timer instance |
3506 | */ |
| 3507 | * @retval None |
3507 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx) |
| 3508 | */ |
3508 | { |
| 3509 | __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) |
3509 | return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); |
| 3510 | { |
3510 | } |
| 3511 | CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); |
3511 | |
| 3512 | } |
3512 | /** |
| 3513 | 3513 | * @} |
|
| 3514 | /** |
3514 | */ |
| 3515 | * @brief Indicates whether the break interrupt (BIE) is enabled. |
3515 | |
| 3516 | * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK |
3516 | /** @defgroup TIM_LL_EF_DMA_Management DMA Management |
| 3517 | * @param TIMx Timer instance |
3517 | * @{ |
| 3518 | * @retval State of bit (1 or 0). |
3518 | */ |
| 3519 | */ |
3519 | /** |
| 3520 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) |
3520 | * @brief Enable update DMA request (UDE). |
| 3521 | { |
3521 | * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE |
| 3522 | return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); |
3522 | * @param TIMx Timer instance |
| 3523 | } |
3523 | * @retval None |
| 3524 | 3524 | */ |
|
| 3525 | /** |
3525 | __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
| 3526 | * @} |
3526 | { |
| 3527 | */ |
3527 | SET_BIT(TIMx->DIER, TIM_DIER_UDE); |
| 3528 | 3528 | } |
|
| 3529 | /** @defgroup TIM_LL_EF_DMA_Management DMA-Management |
3529 | |
| 3530 | * @{ |
3530 | /** |
| 3531 | */ |
3531 | * @brief Disable update DMA request (UDE). |
| 3532 | /** |
3532 | * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE |
| 3533 | * @brief Enable update DMA request (UDE). |
3533 | * @param TIMx Timer instance |
| 3534 | * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE |
3534 | * @retval None |
| 3535 | * @param TIMx Timer instance |
3535 | */ |
| 3536 | * @retval None |
3536 | __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
| 3537 | */ |
3537 | { |
| 3538 | __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
3538 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); |
| 3539 | { |
3539 | } |
| 3540 | SET_BIT(TIMx->DIER, TIM_DIER_UDE); |
3540 | |
| 3541 | } |
3541 | /** |
| 3542 | 3542 | * @brief Indicates whether the update DMA request (UDE) is enabled. |
|
| 3543 | /** |
3543 | * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE |
| 3544 | * @brief Disable update DMA request (UDE). |
3544 | * @param TIMx Timer instance |
| 3545 | * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE |
3545 | * @retval State of bit (1 or 0). |
| 3546 | * @param TIMx Timer instance |
3546 | */ |
| 3547 | * @retval None |
3547 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx) |
| 3548 | */ |
3548 | { |
| 3549 | __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) |
3549 | return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); |
| 3550 | { |
3550 | } |
| 3551 | CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); |
3551 | |
| 3552 | } |
3552 | /** |
| 3553 | 3553 | * @brief Enable capture/compare 1 DMA request (CC1DE). |
|
| 3554 | /** |
3554 | * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 |
| 3555 | * @brief Indicates whether the update DMA request (UDE) is enabled. |
3555 | * @param TIMx Timer instance |
| 3556 | * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE |
3556 | * @retval None |
| 3557 | * @param TIMx Timer instance |
3557 | */ |
| 3558 | * @retval State of bit (1 or 0). |
3558 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) |
| 3559 | */ |
3559 | { |
| 3560 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) |
3560 | SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
| 3561 | { |
3561 | } |
| 3562 | return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); |
3562 | |
| 3563 | } |
3563 | /** |
| 3564 | 3564 | * @brief Disable capture/compare 1 DMA request (CC1DE). |
|
| 3565 | /** |
3565 | * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 |
| 3566 | * @brief Enable capture/compare 1 DMA request (CC1DE). |
3566 | * @param TIMx Timer instance |
| 3567 | * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 |
3567 | * @retval None |
| 3568 | * @param TIMx Timer instance |
3568 | */ |
| 3569 | * @retval None |
3569 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) |
| 3570 | */ |
3570 | { |
| 3571 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) |
3571 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
| 3572 | { |
3572 | } |
| 3573 | SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
3573 | |
| 3574 | } |
3574 | /** |
| 3575 | 3575 | * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. |
|
| 3576 | /** |
3576 | * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 |
| 3577 | * @brief Disable capture/compare 1 DMA request (CC1DE). |
3577 | * @param TIMx Timer instance |
| 3578 | * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 |
3578 | * @retval State of bit (1 or 0). |
| 3579 | * @param TIMx Timer instance |
3579 | */ |
| 3580 | * @retval None |
3580 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx) |
| 3581 | */ |
3581 | { |
| 3582 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) |
3582 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); |
| 3583 | { |
3583 | } |
| 3584 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); |
3584 | |
| 3585 | } |
3585 | /** |
| 3586 | 3586 | * @brief Enable capture/compare 2 DMA request (CC2DE). |
|
| 3587 | /** |
3587 | * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 |
| 3588 | * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. |
3588 | * @param TIMx Timer instance |
| 3589 | * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 |
3589 | * @retval None |
| 3590 | * @param TIMx Timer instance |
3590 | */ |
| 3591 | * @retval State of bit (1 or 0). |
3591 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) |
| 3592 | */ |
3592 | { |
| 3593 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) |
3593 | SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
| 3594 | { |
3594 | } |
| 3595 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); |
3595 | |
| 3596 | } |
3596 | /** |
| 3597 | 3597 | * @brief Disable capture/compare 2 DMA request (CC2DE). |
|
| 3598 | /** |
3598 | * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 |
| 3599 | * @brief Enable capture/compare 2 DMA request (CC2DE). |
3599 | * @param TIMx Timer instance |
| 3600 | * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 |
3600 | * @retval None |
| 3601 | * @param TIMx Timer instance |
3601 | */ |
| 3602 | * @retval None |
3602 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) |
| 3603 | */ |
3603 | { |
| 3604 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) |
3604 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
| 3605 | { |
3605 | } |
| 3606 | SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
3606 | |
| 3607 | } |
3607 | /** |
| 3608 | 3608 | * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. |
|
| 3609 | /** |
3609 | * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 |
| 3610 | * @brief Disable capture/compare 2 DMA request (CC2DE). |
3610 | * @param TIMx Timer instance |
| 3611 | * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 |
3611 | * @retval State of bit (1 or 0). |
| 3612 | * @param TIMx Timer instance |
3612 | */ |
| 3613 | * @retval None |
3613 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx) |
| 3614 | */ |
3614 | { |
| 3615 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) |
3615 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); |
| 3616 | { |
3616 | } |
| 3617 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); |
3617 | |
| 3618 | } |
3618 | /** |
| 3619 | 3619 | * @brief Enable capture/compare 3 DMA request (CC3DE). |
|
| 3620 | /** |
3620 | * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 |
| 3621 | * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. |
3621 | * @param TIMx Timer instance |
| 3622 | * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 |
3622 | * @retval None |
| 3623 | * @param TIMx Timer instance |
3623 | */ |
| 3624 | * @retval State of bit (1 or 0). |
3624 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) |
| 3625 | */ |
3625 | { |
| 3626 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) |
3626 | SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
| 3627 | { |
3627 | } |
| 3628 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); |
3628 | |
| 3629 | } |
3629 | /** |
| 3630 | 3630 | * @brief Disable capture/compare 3 DMA request (CC3DE). |
|
| 3631 | /** |
3631 | * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 |
| 3632 | * @brief Enable capture/compare 3 DMA request (CC3DE). |
3632 | * @param TIMx Timer instance |
| 3633 | * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 |
3633 | * @retval None |
| 3634 | * @param TIMx Timer instance |
3634 | */ |
| 3635 | * @retval None |
3635 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) |
| 3636 | */ |
3636 | { |
| 3637 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) |
3637 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
| 3638 | { |
3638 | } |
| 3639 | SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
3639 | |
| 3640 | } |
3640 | /** |
| 3641 | 3641 | * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. |
|
| 3642 | /** |
3642 | * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 |
| 3643 | * @brief Disable capture/compare 3 DMA request (CC3DE). |
3643 | * @param TIMx Timer instance |
| 3644 | * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 |
3644 | * @retval State of bit (1 or 0). |
| 3645 | * @param TIMx Timer instance |
3645 | */ |
| 3646 | * @retval None |
3646 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx) |
| 3647 | */ |
3647 | { |
| 3648 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) |
3648 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); |
| 3649 | { |
3649 | } |
| 3650 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); |
3650 | |
| 3651 | } |
3651 | /** |
| 3652 | 3652 | * @brief Enable capture/compare 4 DMA request (CC4DE). |
|
| 3653 | /** |
3653 | * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 |
| 3654 | * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. |
3654 | * @param TIMx Timer instance |
| 3655 | * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 |
3655 | * @retval None |
| 3656 | * @param TIMx Timer instance |
3656 | */ |
| 3657 | * @retval State of bit (1 or 0). |
3657 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) |
| 3658 | */ |
3658 | { |
| 3659 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) |
3659 | SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
| 3660 | { |
3660 | } |
| 3661 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); |
3661 | |
| 3662 | } |
3662 | /** |
| 3663 | 3663 | * @brief Disable capture/compare 4 DMA request (CC4DE). |
|
| 3664 | /** |
3664 | * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 |
| 3665 | * @brief Enable capture/compare 4 DMA request (CC4DE). |
3665 | * @param TIMx Timer instance |
| 3666 | * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 |
3666 | * @retval None |
| 3667 | * @param TIMx Timer instance |
3667 | */ |
| 3668 | * @retval None |
3668 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) |
| 3669 | */ |
3669 | { |
| 3670 | __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) |
3670 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
| 3671 | { |
3671 | } |
| 3672 | SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
3672 | |
| 3673 | } |
3673 | /** |
| 3674 | 3674 | * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. |
|
| 3675 | /** |
3675 | * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 |
| 3676 | * @brief Disable capture/compare 4 DMA request (CC4DE). |
3676 | * @param TIMx Timer instance |
| 3677 | * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 |
3677 | * @retval State of bit (1 or 0). |
| 3678 | * @param TIMx Timer instance |
3678 | */ |
| 3679 | * @retval None |
3679 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx) |
| 3680 | */ |
3680 | { |
| 3681 | __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) |
3681 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); |
| 3682 | { |
3682 | } |
| 3683 | CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); |
3683 | |
| 3684 | } |
3684 | /** |
| 3685 | 3685 | * @brief Enable commutation DMA request (COMDE). |
|
| 3686 | /** |
3686 | * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM |
| 3687 | * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. |
3687 | * @param TIMx Timer instance |
| 3688 | * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 |
3688 | * @retval None |
| 3689 | * @param TIMx Timer instance |
3689 | */ |
| 3690 | * @retval State of bit (1 or 0). |
3690 | __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) |
| 3691 | */ |
3691 | { |
| 3692 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) |
3692 | SET_BIT(TIMx->DIER, TIM_DIER_COMDE); |
| 3693 | { |
3693 | } |
| 3694 | return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); |
3694 | |
| 3695 | } |
3695 | /** |
| 3696 | 3696 | * @brief Disable commutation DMA request (COMDE). |
|
| 3697 | /** |
3697 | * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM |
| 3698 | * @brief Enable commutation DMA request (COMDE). |
3698 | * @param TIMx Timer instance |
| 3699 | * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM |
3699 | * @retval None |
| 3700 | * @param TIMx Timer instance |
3700 | */ |
| 3701 | * @retval None |
3701 | __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) |
| 3702 | */ |
3702 | { |
| 3703 | __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) |
3703 | CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); |
| 3704 | { |
3704 | } |
| 3705 | SET_BIT(TIMx->DIER, TIM_DIER_COMDE); |
3705 | |
| 3706 | } |
3706 | /** |
| 3707 | 3707 | * @brief Indicates whether the commutation DMA request (COMDE) is enabled. |
|
| 3708 | /** |
3708 | * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM |
| 3709 | * @brief Disable commutation DMA request (COMDE). |
3709 | * @param TIMx Timer instance |
| 3710 | * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM |
3710 | * @retval State of bit (1 or 0). |
| 3711 | * @param TIMx Timer instance |
3711 | */ |
| 3712 | * @retval None |
3712 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx) |
| 3713 | */ |
3713 | { |
| 3714 | __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) |
3714 | return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); |
| 3715 | { |
3715 | } |
| 3716 | CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); |
3716 | |
| 3717 | } |
3717 | /** |
| 3718 | 3718 | * @brief Enable trigger interrupt (TDE). |
|
| 3719 | /** |
3719 | * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG |
| 3720 | * @brief Indicates whether the commutation DMA request (COMDE) is enabled. |
3720 | * @param TIMx Timer instance |
| 3721 | * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM |
3721 | * @retval None |
| 3722 | * @param TIMx Timer instance |
3722 | */ |
| 3723 | * @retval State of bit (1 or 0). |
3723 | __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) |
| 3724 | */ |
3724 | { |
| 3725 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) |
3725 | SET_BIT(TIMx->DIER, TIM_DIER_TDE); |
| 3726 | { |
3726 | } |
| 3727 | return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); |
3727 | |
| 3728 | } |
3728 | /** |
| 3729 | 3729 | * @brief Disable trigger interrupt (TDE). |
|
| 3730 | /** |
3730 | * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG |
| 3731 | * @brief Enable trigger interrupt (TDE). |
3731 | * @param TIMx Timer instance |
| 3732 | * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG |
3732 | * @retval None |
| 3733 | * @param TIMx Timer instance |
3733 | */ |
| 3734 | * @retval None |
3734 | __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) |
| 3735 | */ |
3735 | { |
| 3736 | __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) |
3736 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); |
| 3737 | { |
3737 | } |
| 3738 | SET_BIT(TIMx->DIER, TIM_DIER_TDE); |
3738 | |
| 3739 | } |
3739 | /** |
| 3740 | 3740 | * @brief Indicates whether the trigger interrupt (TDE) is enabled. |
|
| 3741 | /** |
3741 | * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG |
| 3742 | * @brief Disable trigger interrupt (TDE). |
3742 | * @param TIMx Timer instance |
| 3743 | * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG |
3743 | * @retval State of bit (1 or 0). |
| 3744 | * @param TIMx Timer instance |
3744 | */ |
| 3745 | * @retval None |
3745 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx) |
| 3746 | */ |
3746 | { |
| 3747 | __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) |
3747 | return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); |
| 3748 | { |
3748 | } |
| 3749 | CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); |
3749 | |
| 3750 | } |
3750 | /** |
| 3751 | 3751 | * @} |
|
| 3752 | /** |
3752 | */ |
| 3753 | * @brief Indicates whether the trigger interrupt (TDE) is enabled. |
3753 | |
| 3754 | * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG |
3754 | /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management |
| 3755 | * @param TIMx Timer instance |
3755 | * @{ |
| 3756 | * @retval State of bit (1 or 0). |
3756 | */ |
| 3757 | */ |
3757 | /** |
| 3758 | __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) |
3758 | * @brief Generate an update event. |
| 3759 | { |
3759 | * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE |
| 3760 | return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); |
3760 | * @param TIMx Timer instance |
| 3761 | } |
3761 | * @retval None |
| 3762 | 3762 | */ |
|
| 3763 | /** |
3763 | __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) |
| 3764 | * @} |
3764 | { |
| 3765 | */ |
3765 | SET_BIT(TIMx->EGR, TIM_EGR_UG); |
| 3766 | 3766 | } |
|
| 3767 | /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management |
3767 | |
| 3768 | * @{ |
3768 | /** |
| 3769 | */ |
3769 | * @brief Generate Capture/Compare 1 event. |
| 3770 | /** |
3770 | * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 |
| 3771 | * @brief Generate an update event. |
3771 | * @param TIMx Timer instance |
| 3772 | * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE |
3772 | * @retval None |
| 3773 | * @param TIMx Timer instance |
3773 | */ |
| 3774 | * @retval None |
3774 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) |
| 3775 | */ |
3775 | { |
| 3776 | __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) |
3776 | SET_BIT(TIMx->EGR, TIM_EGR_CC1G); |
| 3777 | { |
3777 | } |
| 3778 | SET_BIT(TIMx->EGR, TIM_EGR_UG); |
3778 | |
| 3779 | } |
3779 | /** |
| 3780 | 3780 | * @brief Generate Capture/Compare 2 event. |
|
| 3781 | /** |
3781 | * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 |
| 3782 | * @brief Generate Capture/Compare 1 event. |
3782 | * @param TIMx Timer instance |
| 3783 | * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 |
3783 | * @retval None |
| 3784 | * @param TIMx Timer instance |
3784 | */ |
| 3785 | * @retval None |
3785 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) |
| 3786 | */ |
3786 | { |
| 3787 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) |
3787 | SET_BIT(TIMx->EGR, TIM_EGR_CC2G); |
| 3788 | { |
3788 | } |
| 3789 | SET_BIT(TIMx->EGR, TIM_EGR_CC1G); |
3789 | |
| 3790 | } |
3790 | /** |
| 3791 | 3791 | * @brief Generate Capture/Compare 3 event. |
|
| 3792 | /** |
3792 | * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 |
| 3793 | * @brief Generate Capture/Compare 2 event. |
3793 | * @param TIMx Timer instance |
| 3794 | * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 |
3794 | * @retval None |
| 3795 | * @param TIMx Timer instance |
3795 | */ |
| 3796 | * @retval None |
3796 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) |
| 3797 | */ |
3797 | { |
| 3798 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) |
3798 | SET_BIT(TIMx->EGR, TIM_EGR_CC3G); |
| 3799 | { |
3799 | } |
| 3800 | SET_BIT(TIMx->EGR, TIM_EGR_CC2G); |
3800 | |
| 3801 | } |
3801 | /** |
| 3802 | 3802 | * @brief Generate Capture/Compare 4 event. |
|
| 3803 | /** |
3803 | * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 |
| 3804 | * @brief Generate Capture/Compare 3 event. |
3804 | * @param TIMx Timer instance |
| 3805 | * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 |
3805 | * @retval None |
| 3806 | * @param TIMx Timer instance |
3806 | */ |
| 3807 | * @retval None |
3807 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) |
| 3808 | */ |
3808 | { |
| 3809 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) |
3809 | SET_BIT(TIMx->EGR, TIM_EGR_CC4G); |
| 3810 | { |
3810 | } |
| 3811 | SET_BIT(TIMx->EGR, TIM_EGR_CC3G); |
3811 | |
| 3812 | } |
3812 | /** |
| 3813 | 3813 | * @brief Generate commutation event. |
|
| 3814 | /** |
3814 | * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM |
| 3815 | * @brief Generate Capture/Compare 4 event. |
3815 | * @param TIMx Timer instance |
| 3816 | * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 |
3816 | * @retval None |
| 3817 | * @param TIMx Timer instance |
3817 | */ |
| 3818 | * @retval None |
3818 | __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) |
| 3819 | */ |
3819 | { |
| 3820 | __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) |
3820 | SET_BIT(TIMx->EGR, TIM_EGR_COMG); |
| 3821 | { |
3821 | } |
| 3822 | SET_BIT(TIMx->EGR, TIM_EGR_CC4G); |
3822 | |
| 3823 | } |
3823 | /** |
| 3824 | 3824 | * @brief Generate trigger event. |
|
| 3825 | /** |
3825 | * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG |
| 3826 | * @brief Generate commutation event. |
3826 | * @param TIMx Timer instance |
| 3827 | * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM |
3827 | * @retval None |
| 3828 | * @param TIMx Timer instance |
3828 | */ |
| 3829 | * @retval None |
3829 | __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) |
| 3830 | */ |
3830 | { |
| 3831 | __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) |
3831 | SET_BIT(TIMx->EGR, TIM_EGR_TG); |
| 3832 | { |
3832 | } |
| 3833 | SET_BIT(TIMx->EGR, TIM_EGR_COMG); |
3833 | |
| 3834 | } |
3834 | /** |
| 3835 | 3835 | * @brief Generate break event. |
|
| 3836 | /** |
3836 | * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK |
| 3837 | * @brief Generate trigger event. |
3837 | * @param TIMx Timer instance |
| 3838 | * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG |
3838 | * @retval None |
| 3839 | * @param TIMx Timer instance |
3839 | */ |
| 3840 | * @retval None |
3840 | __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) |
| 3841 | */ |
3841 | { |
| 3842 | __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) |
3842 | SET_BIT(TIMx->EGR, TIM_EGR_BG); |
| 3843 | { |
3843 | } |
| 3844 | SET_BIT(TIMx->EGR, TIM_EGR_TG); |
3844 | |
| 3845 | } |
3845 | /** |
| 3846 | 3846 | * @} |
|
| 3847 | /** |
3847 | */ |
| 3848 | * @brief Generate break event. |
3848 | |
| 3849 | * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK |
3849 | #if defined(USE_FULL_LL_DRIVER) |
| 3850 | * @param TIMx Timer instance |
3850 | /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions |
| 3851 | * @retval None |
3851 | * @{ |
| 3852 | */ |
3852 | */ |
| 3853 | __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) |
3853 | |
| 3854 | { |
3854 | ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); |
| 3855 | SET_BIT(TIMx->EGR, TIM_EGR_BG); |
3855 | void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); |
| 3856 | } |
3856 | ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); |
| 3857 | 3857 | void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
|
| 3858 | /** |
3858 | ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
| 3859 | * @} |
3859 | void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
| 3860 | */ |
3860 | ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); |
| 3861 | 3861 | void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
|
| 3862 | #if defined(USE_FULL_LL_DRIVER) |
3862 | ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
| 3863 | /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions |
3863 | void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); |
| 3864 | * @{ |
3864 | ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); |
| 3865 | */ |
3865 | void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); |
| 3866 | 3866 | ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); |
|
| 3867 | ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); |
3867 | /** |
| 3868 | void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); |
3868 | * @} |
| 3869 | ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); |
3869 | */ |
| 3870 | void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
3870 | #endif /* USE_FULL_LL_DRIVER */ |
| 3871 | ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); |
3871 | |
| 3872 | void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
3872 | /** |
| 3873 | ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); |
3873 | * @} |
| 3874 | void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
3874 | */ |
| 3875 | ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); |
3875 | |
| 3876 | void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); |
3876 | /** |
| 3877 | ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); |
3877 | * @} |
| 3878 | void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); |
3878 | */ |
| 3879 | ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); |
3879 | |
| 3880 | /** |
3880 | #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ |
| 3881 | * @} |
3881 | |
| 3882 | */ |
3882 | /** |
| 3883 | #endif /* USE_FULL_LL_DRIVER */ |
3883 | * @} |
| 3884 | 3884 | */ |
|
| 3885 | /** |
3885 | |
| 3886 | * @} |
3886 | #ifdef __cplusplus |
| 3887 | */ |
3887 | } |
| 3888 | 3888 | #endif |
|
| 3889 | /** |
3889 | |
| 3890 | * @} |
3890 | #endif /* __STM32F1xx_LL_TIM_H */ |
| 3891 | */ |
- | |
| 3892 | - | ||
| 3893 | #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ |
- | |
| 3894 | - | ||
| 3895 | /** |
- | |
| 3896 | * @} |
- | |
| 3897 | */ |
- | |
| 3898 | - | ||
| 3899 | #ifdef __cplusplus |
- | |
| 3900 | } |
- | |
| 3901 | #endif |
- | |
| 3902 | - | ||
| 3903 | #endif /* __STM32F1xx_LL_TIM_H */ |
- | |
| 3904 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |