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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_ll_system.h |
3 | * @file stm32f1xx_ll_system.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of SYSTEM LL module. |
5 | * @brief Header file of SYSTEM LL module. |
| 6 | @verbatim |
6 | * |
| 7 | ============================================================================== |
7 | ****************************************************************************** |
| 8 | ##### How to use this driver ##### |
8 | * @attention |
| 9 | ============================================================================== |
9 | * |
| 10 | [..] |
10 | * Copyright (c) 2016 STMicroelectronics. |
| 11 | The LL SYSTEM driver contains a set of generic APIs that can be |
11 | * All rights reserved. |
| 12 | used by user: |
12 | * |
| 13 | (+) Some of the FLASH features need to be handled in the SYSTEM file. |
13 | * This software is licensed under terms that can be found in the LICENSE file |
| 14 | (+) Access to DBGCMU registers |
14 | * in the root directory of this software component. |
| 15 | (+) Access to SYSCFG registers |
15 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 16 | 16 | * |
|
| 17 | @endverbatim |
17 | ****************************************************************************** |
| 18 | ****************************************************************************** |
18 | @verbatim |
| 19 | * @attention |
19 | ============================================================================== |
| 20 | * |
20 | ##### How to use this driver ##### |
| 21 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
21 | ============================================================================== |
| 22 | * All rights reserved.</center></h2> |
22 | [..] |
| 23 | * |
23 | The LL SYSTEM driver contains a set of generic APIs that can be |
| 24 | * This software component is licensed by ST under BSD 3-Clause license, |
24 | used by user: |
| 25 | * the "License"; You may not use this file except in compliance with the |
25 | (+) Some of the FLASH features need to be handled in the SYSTEM file. |
| 26 | * License. You may obtain a copy of the License at: |
26 | (+) Access to DBGCMU registers |
| 27 | * opensource.org/licenses/BSD-3-Clause |
27 | (+) Access to SYSCFG registers |
| 28 | * |
28 | |
| 29 | ****************************************************************************** |
29 | @endverbatim |
| 30 | */ |
30 | ****************************************************************************** |
| 31 | 31 | */ |
|
| 32 | /* Define to prevent recursive inclusion -------------------------------------*/ |
32 | |
| 33 | #ifndef __STM32F1xx_LL_SYSTEM_H |
33 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| 34 | #define __STM32F1xx_LL_SYSTEM_H |
34 | #ifndef __STM32F1xx_LL_SYSTEM_H |
| 35 | 35 | #define __STM32F1xx_LL_SYSTEM_H |
|
| 36 | #ifdef __cplusplus |
36 | |
| 37 | extern "C" { |
37 | #ifdef __cplusplus |
| 38 | #endif |
38 | extern "C" { |
| 39 | 39 | #endif |
|
| 40 | /* Includes ------------------------------------------------------------------*/ |
40 | |
| 41 | #include "stm32f1xx.h" |
41 | /* Includes ------------------------------------------------------------------*/ |
| 42 | 42 | #include "stm32f1xx.h" |
|
| 43 | /** @addtogroup STM32F1xx_LL_Driver |
43 | |
| 44 | * @{ |
44 | /** @addtogroup STM32F1xx_LL_Driver |
| 45 | */ |
45 | * @{ |
| 46 | 46 | */ |
|
| 47 | #if defined (FLASH) || defined (DBGMCU) |
47 | |
| 48 | 48 | #if defined (FLASH) || defined (DBGMCU) |
|
| 49 | /** @defgroup SYSTEM_LL SYSTEM |
49 | |
| 50 | * @{ |
50 | /** @defgroup SYSTEM_LL SYSTEM |
| 51 | */ |
51 | * @{ |
| 52 | 52 | */ |
|
| 53 | /* Private types -------------------------------------------------------------*/ |
53 | |
| 54 | /* Private variables ---------------------------------------------------------*/ |
54 | /* Private types -------------------------------------------------------------*/ |
| 55 | 55 | /* Private variables ---------------------------------------------------------*/ |
|
| 56 | /* Private constants ---------------------------------------------------------*/ |
56 | |
| 57 | /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants |
57 | /* Private constants ---------------------------------------------------------*/ |
| 58 | * @{ |
58 | /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants |
| 59 | */ |
59 | * @{ |
| 60 | 60 | */ |
|
| 61 | /** |
61 | |
| 62 | * @} |
62 | /** |
| 63 | */ |
63 | * @} |
| 64 | 64 | */ |
|
| 65 | /* Private macros ------------------------------------------------------------*/ |
65 | |
| 66 | 66 | /* Private macros ------------------------------------------------------------*/ |
|
| 67 | /* Exported types ------------------------------------------------------------*/ |
67 | |
| 68 | /* Exported constants --------------------------------------------------------*/ |
68 | /* Exported types ------------------------------------------------------------*/ |
| 69 | /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants |
69 | /* Exported constants --------------------------------------------------------*/ |
| 70 | * @{ |
70 | /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants |
| 71 | */ |
71 | * @{ |
| 72 | 72 | */ |
|
| 73 | 73 | ||
| 74 | 74 | ||
| 75 | /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment |
75 | |
| 76 | * @{ |
76 | /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment |
| 77 | */ |
77 | * @{ |
| 78 | #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ |
78 | */ |
| 79 | #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ |
79 | #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ |
| 80 | #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ |
80 | #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ |
| 81 | #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ |
81 | #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ |
| 82 | #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ |
82 | #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ |
| 83 | /** |
83 | #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ |
| 84 | * @} |
84 | /** |
| 85 | */ |
85 | * @} |
| 86 | 86 | */ |
|
| 87 | /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP |
87 | |
| 88 | * @{ |
88 | /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP |
| 89 | */ |
89 | * @{ |
| 90 | #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ |
90 | */ |
| 91 | #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ |
91 | #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */ |
| 92 | #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ |
92 | #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ |
| 93 | #if defined(DBGMCU_CR_DBG_TIM5_STOP) |
93 | #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */ |
| 94 | #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ |
94 | #if defined(DBGMCU_CR_DBG_TIM5_STOP) |
| 95 | #endif /* DBGMCU_CR_DBG_TIM5_STOP */ |
95 | #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */ |
| 96 | #if defined(DBGMCU_CR_DBG_TIM6_STOP) |
96 | #endif /* DBGMCU_CR_DBG_TIM5_STOP */ |
| 97 | #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ |
97 | #if defined(DBGMCU_CR_DBG_TIM6_STOP) |
| 98 | #endif /* DBGMCU_CR_DBG_TIM6_STOP */ |
98 | #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */ |
| 99 | #if defined(DBGMCU_CR_DBG_TIM7_STOP) |
99 | #endif /* DBGMCU_CR_DBG_TIM6_STOP */ |
| 100 | #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ |
100 | #if defined(DBGMCU_CR_DBG_TIM7_STOP) |
| 101 | #endif /* DBGMCU_CR_DBG_TIM7_STOP */ |
101 | #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */ |
| 102 | #if defined(DBGMCU_CR_DBG_TIM12_STOP) |
102 | #endif /* DBGMCU_CR_DBG_TIM7_STOP */ |
| 103 | #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ |
103 | #if defined(DBGMCU_CR_DBG_TIM12_STOP) |
| 104 | #endif /* DBGMCU_CR_DBG_TIM12_STOP */ |
104 | #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_CR_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */ |
| 105 | #if defined(DBGMCU_CR_DBG_TIM13_STOP) |
105 | #endif /* DBGMCU_CR_DBG_TIM12_STOP */ |
| 106 | #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ |
106 | #if defined(DBGMCU_CR_DBG_TIM13_STOP) |
| 107 | #endif /* DBGMCU_CR_DBG_TIM13_STOP */ |
107 | #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_CR_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */ |
| 108 | #if defined(DBGMCU_CR_DBG_TIM14_STOP) |
108 | #endif /* DBGMCU_CR_DBG_TIM13_STOP */ |
| 109 | #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ |
109 | #if defined(DBGMCU_CR_DBG_TIM14_STOP) |
| 110 | #endif /* DBGMCU_CR_DBG_TIM14_STOP */ |
110 | #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_CR_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ |
| 111 | #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ |
111 | #endif /* DBGMCU_CR_DBG_TIM14_STOP */ |
| 112 | #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ |
112 | #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ |
| 113 | #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ |
113 | #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ |
| 114 | #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
114 | #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */ |
| 115 | #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ |
115 | #if defined(DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT) |
| 116 | #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */ |
116 | #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */ |
| 117 | #if defined(DBGMCU_CR_DBG_CAN1_STOP) |
117 | #endif /* DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT */ |
| 118 | #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ |
118 | #if defined(DBGMCU_CR_DBG_CAN1_STOP) |
| 119 | #endif /* DBGMCU_CR_DBG_CAN1_STOP */ |
119 | #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */ |
| 120 | #if defined(DBGMCU_CR_DBG_CAN2_STOP) |
120 | #endif /* DBGMCU_CR_DBG_CAN1_STOP */ |
| 121 | #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ |
121 | #if defined(DBGMCU_CR_DBG_CAN2_STOP) |
| 122 | #endif /* DBGMCU_CR_DBG_CAN2_STOP */ |
122 | #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */ |
| 123 | /** |
123 | #endif /* DBGMCU_CR_DBG_CAN2_STOP */ |
| 124 | * @} |
124 | /** |
| 125 | */ |
125 | * @} |
| 126 | 126 | */ |
|
| 127 | /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP |
127 | |
| 128 | * @{ |
128 | /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP |
| 129 | */ |
129 | * @{ |
| 130 | #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ |
130 | */ |
| 131 | #if defined(DBGMCU_CR_DBG_TIM8_STOP) |
131 | #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ |
| 132 | #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ |
132 | #if defined(DBGMCU_CR_DBG_TIM8_STOP) |
| 133 | #endif /* DBGMCU_CR_DBG_CAN1_STOP */ |
133 | #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_CR_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */ |
| 134 | #if defined(DBGMCU_CR_DBG_TIM9_STOP) |
134 | #endif /* DBGMCU_CR_DBG_CAN1_STOP */ |
| 135 | #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ |
135 | #if defined(DBGMCU_CR_DBG_TIM9_STOP) |
| 136 | #endif /* DBGMCU_CR_DBG_TIM9_STOP */ |
136 | #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */ |
| 137 | #if defined(DBGMCU_CR_DBG_TIM10_STOP) |
137 | #endif /* DBGMCU_CR_DBG_TIM9_STOP */ |
| 138 | #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ |
138 | #if defined(DBGMCU_CR_DBG_TIM10_STOP) |
| 139 | #endif /* DBGMCU_CR_DBG_TIM10_STOP */ |
139 | #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */ |
| 140 | #if defined(DBGMCU_CR_DBG_TIM11_STOP) |
140 | #endif /* DBGMCU_CR_DBG_TIM10_STOP */ |
| 141 | #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ |
141 | #if defined(DBGMCU_CR_DBG_TIM11_STOP) |
| 142 | #endif /* DBGMCU_CR_DBG_TIM11_STOP */ |
142 | #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */ |
| 143 | #if defined(DBGMCU_CR_DBG_TIM15_STOP) |
143 | #endif /* DBGMCU_CR_DBG_TIM11_STOP */ |
| 144 | #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ |
144 | #if defined(DBGMCU_CR_DBG_TIM15_STOP) |
| 145 | #endif /* DBGMCU_CR_DBG_TIM15_STOP */ |
145 | #define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_CR_DBG_TIM15_STOP /*!< TIM15 counter stopped when core is halted */ |
| 146 | #if defined(DBGMCU_CR_DBG_TIM16_STOP) |
146 | #endif /* DBGMCU_CR_DBG_TIM15_STOP */ |
| 147 | #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ |
147 | #if defined(DBGMCU_CR_DBG_TIM16_STOP) |
| 148 | #endif /* DBGMCU_CR_DBG_TIM16_STOP */ |
148 | #define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_CR_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ |
| 149 | #if defined(DBGMCU_CR_DBG_TIM17_STOP) |
149 | #endif /* DBGMCU_CR_DBG_TIM16_STOP */ |
| 150 | #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ |
150 | #if defined(DBGMCU_CR_DBG_TIM17_STOP) |
| 151 | #endif /* DBGMCU_CR_DBG_TIM17_STOP */ |
151 | #define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_CR_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ |
| 152 | /** |
152 | #endif /* DBGMCU_CR_DBG_TIM17_STOP */ |
| 153 | * @} |
153 | /** |
| 154 | */ |
154 | * @} |
| 155 | 155 | */ |
|
| 156 | /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY |
156 | |
| 157 | * @{ |
157 | /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY |
| 158 | */ |
158 | * @{ |
| 159 | #if defined(FLASH_ACR_LATENCY) |
159 | */ |
| 160 | #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
160 | #if defined(FLASH_ACR_LATENCY) |
| 161 | #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ |
161 | #define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ |
| 162 | #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ |
162 | #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */ |
| 163 | #else |
163 | #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two wait states */ |
| 164 | #endif /* FLASH_ACR_LATENCY */ |
164 | #else |
| 165 | /** |
165 | #endif /* FLASH_ACR_LATENCY */ |
| 166 | * @} |
166 | /** |
| 167 | */ |
167 | * @} |
| 168 | 168 | */ |
|
| 169 | /** |
169 | |
| 170 | * @} |
170 | /** |
| 171 | */ |
171 | * @} |
| 172 | 172 | */ |
|
| 173 | /* Exported macro ------------------------------------------------------------*/ |
173 | |
| 174 | 174 | /* Exported macro ------------------------------------------------------------*/ |
|
| 175 | /* Exported functions --------------------------------------------------------*/ |
175 | |
| 176 | /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions |
176 | /* Exported functions --------------------------------------------------------*/ |
| 177 | * @{ |
177 | /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions |
| 178 | */ |
178 | * @{ |
| 179 | 179 | */ |
|
| 180 | 180 | ||
| 181 | 181 | ||
| 182 | /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU |
182 | |
| 183 | * @{ |
183 | /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU |
| 184 | */ |
184 | * @{ |
| 185 | 185 | */ |
|
| 186 | /** |
186 | |
| 187 | * @brief Return the device identifier |
187 | /** |
| 188 | * @note For Low Density devices, the device ID is 0x412 |
188 | * @brief Return the device identifier |
| 189 | * @note For Medium Density devices, the device ID is 0x410 |
189 | * @note For Low Density devices, the device ID is 0x412 |
| 190 | * @note For High Density devices, the device ID is 0x414 |
190 | * @note For Medium Density devices, the device ID is 0x410 |
| 191 | * @note For XL Density devices, the device ID is 0x430 |
191 | * @note For High Density devices, the device ID is 0x414 |
| 192 | * @note For Connectivity Line devices, the device ID is 0x418 |
192 | * @note For XL Density devices, the device ID is 0x430 |
| 193 | * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID |
193 | * @note For Connectivity Line devices, the device ID is 0x418 |
| 194 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFF |
194 | * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID |
| 195 | */ |
195 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFF |
| 196 | __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) |
196 | */ |
| 197 | { |
197 | __STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) |
| 198 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); |
198 | { |
| 199 | } |
199 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); |
| 200 | 200 | } |
|
| 201 | /** |
201 | |
| 202 | * @brief Return the device revision identifier |
202 | /** |
| 203 | * @note This field indicates the revision of the device. |
203 | * @brief Return the device revision identifier |
| 204 | For example, it is read as revA -> 0x1000,for Low Density devices |
204 | * @note This field indicates the revision of the device. |
| 205 | For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices |
205 | For example, it is read as revA -> 0x1000,for Low Density devices |
| 206 | For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices |
206 | For example, it is read as revA -> 0x0000, revB -> 0x2000, revZ -> 0x2001, rev1,2,3,X or Y -> 0x2003,for Medium Density devices |
| 207 | For example, it is read as revA or 1 -> 0x1003,for XL Density devices |
207 | For example, it is read as revA or 1 -> 0x1000, revZ -> 0x1001,rev1,2,3,X or Y -> 0x1003,for Medium Density devices |
| 208 | For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices |
208 | For example, it is read as revA or 1 -> 0x1003,for XL Density devices |
| 209 | * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID |
209 | For example, it is read as revA -> 0x1000, revZ -> 0x1001 for Connectivity line devices |
| 210 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF |
210 | * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID |
| 211 | */ |
211 | * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF |
| 212 | __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) |
212 | */ |
| 213 | { |
213 | __STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) |
| 214 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); |
214 | { |
| 215 | } |
215 | return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); |
| 216 | 216 | } |
|
| 217 | /** |
217 | |
| 218 | * @brief Enable the Debug Module during SLEEP mode |
218 | /** |
| 219 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode |
219 | * @brief Enable the Debug Module during SLEEP mode |
| 220 | * @retval None |
220 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode |
| 221 | */ |
221 | * @retval None |
| 222 | __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) |
222 | */ |
| 223 | { |
223 | __STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) |
| 224 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
224 | { |
| 225 | } |
225 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
| 226 | 226 | } |
|
| 227 | /** |
227 | |
| 228 | * @brief Disable the Debug Module during SLEEP mode |
228 | /** |
| 229 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode |
229 | * @brief Disable the Debug Module during SLEEP mode |
| 230 | * @retval None |
230 | * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode |
| 231 | */ |
231 | * @retval None |
| 232 | __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) |
232 | */ |
| 233 | { |
233 | __STATIC_INLINE void LL_DBGMCU_DisableDBGSleepMode(void) |
| 234 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
234 | { |
| 235 | } |
235 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); |
| 236 | 236 | } |
|
| 237 | /** |
237 | |
| 238 | * @brief Enable the Debug Module during STOP mode |
238 | /** |
| 239 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode |
239 | * @brief Enable the Debug Module during STOP mode |
| 240 | * @retval None |
240 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode |
| 241 | */ |
241 | * @retval None |
| 242 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) |
242 | */ |
| 243 | { |
243 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) |
| 244 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
244 | { |
| 245 | } |
245 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
| 246 | 246 | } |
|
| 247 | /** |
247 | |
| 248 | * @brief Disable the Debug Module during STOP mode |
248 | /** |
| 249 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode |
249 | * @brief Disable the Debug Module during STOP mode |
| 250 | * @retval None |
250 | * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode |
| 251 | */ |
251 | * @retval None |
| 252 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) |
252 | */ |
| 253 | { |
253 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) |
| 254 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
254 | { |
| 255 | } |
255 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); |
| 256 | 256 | } |
|
| 257 | /** |
257 | |
| 258 | * @brief Enable the Debug Module during STANDBY mode |
258 | /** |
| 259 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode |
259 | * @brief Enable the Debug Module during STANDBY mode |
| 260 | * @retval None |
260 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode |
| 261 | */ |
261 | * @retval None |
| 262 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) |
262 | */ |
| 263 | { |
263 | __STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) |
| 264 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
264 | { |
| 265 | } |
265 | SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
| 266 | 266 | } |
|
| 267 | /** |
267 | |
| 268 | * @brief Disable the Debug Module during STANDBY mode |
268 | /** |
| 269 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode |
269 | * @brief Disable the Debug Module during STANDBY mode |
| 270 | * @retval None |
270 | * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode |
| 271 | */ |
271 | * @retval None |
| 272 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) |
272 | */ |
| 273 | { |
273 | __STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) |
| 274 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
274 | { |
| 275 | } |
275 | CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); |
| 276 | 276 | } |
|
| 277 | /** |
277 | |
| 278 | * @brief Set Trace pin assignment control |
278 | /** |
| 279 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n |
279 | * @brief Set Trace pin assignment control |
| 280 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment |
280 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n |
| 281 | * @param PinAssignment This parameter can be one of the following values: |
281 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment |
| 282 | * @arg @ref LL_DBGMCU_TRACE_NONE |
282 | * @param PinAssignment This parameter can be one of the following values: |
| 283 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
283 | * @arg @ref LL_DBGMCU_TRACE_NONE |
| 284 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
284 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
| 285 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
285 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
| 286 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
286 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
| 287 | * @retval None |
287 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
| 288 | */ |
288 | * @retval None |
| 289 | __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) |
289 | */ |
| 290 | { |
290 | __STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) |
| 291 | MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); |
291 | { |
| 292 | } |
292 | MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); |
| 293 | 293 | } |
|
| 294 | /** |
294 | |
| 295 | * @brief Get Trace pin assignment control |
295 | /** |
| 296 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n |
296 | * @brief Get Trace pin assignment control |
| 297 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment |
297 | * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n |
| 298 | * @retval Returned value can be one of the following values: |
298 | * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment |
| 299 | * @arg @ref LL_DBGMCU_TRACE_NONE |
299 | * @retval Returned value can be one of the following values: |
| 300 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
300 | * @arg @ref LL_DBGMCU_TRACE_NONE |
| 301 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
301 | * @arg @ref LL_DBGMCU_TRACE_ASYNCH |
| 302 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
302 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 |
| 303 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
303 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 |
| 304 | */ |
304 | * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 |
| 305 | __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) |
305 | */ |
| 306 | { |
306 | __STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) |
| 307 | return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); |
307 | { |
| 308 | } |
308 | return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); |
| 309 | 309 | } |
|
| 310 | /** |
310 | |
| 311 | * @brief Freeze APB1 peripherals (group1 peripherals) |
311 | /** |
| 312 | * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
312 | * @brief Freeze APB1 peripherals (group1 peripherals) |
| 313 | * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
313 | * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 314 | * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
314 | * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 315 | * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
315 | * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 316 | * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
316 | * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 317 | * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
317 | * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 318 | * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
318 | * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 319 | * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
319 | * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 320 | * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
320 | * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 321 | * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
321 | * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 322 | * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
322 | * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 323 | * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
323 | * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 324 | * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
324 | * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 325 | * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
325 | * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 326 | * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
326 | * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 327 | * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph |
327 | * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n |
| 328 | * @param Periphs This parameter can be a combination of the following values: |
328 | * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph |
| 329 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
329 | * @param Periphs This parameter can be a combination of the following values: |
| 330 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
330 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
| 331 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
331 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
| 332 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
332 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
| 333 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
333 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
| 334 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
334 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
| 335 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
335 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
| 336 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
336 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
| 337 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
337 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
| 338 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
338 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
| 339 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
339 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
| 340 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
340 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
| 341 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
341 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
| 342 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) |
342 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
| 343 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
343 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) |
| 344 | * |
344 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
| 345 | * (*) value not defined in all devices. |
345 | * |
| 346 | * @retval None |
346 | * (*) value not defined in all devices. |
| 347 | */ |
347 | * @retval None |
| 348 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) |
348 | */ |
| 349 | { |
349 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) |
| 350 | SET_BIT(DBGMCU->CR, Periphs); |
350 | { |
| 351 | } |
351 | SET_BIT(DBGMCU->CR, Periphs); |
| 352 | 352 | } |
|
| 353 | /** |
353 | |
| 354 | * @brief Unfreeze APB1 peripherals (group1 peripherals) |
354 | /** |
| 355 | * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
355 | * @brief Unfreeze APB1 peripherals (group1 peripherals) |
| 356 | * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
356 | * @rmtoll DBGMCU_CR_APB1 DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 357 | * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
357 | * DBGMCU_CR_APB1 DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 358 | * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
358 | * DBGMCU_CR_APB1 DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 359 | * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
359 | * DBGMCU_CR_APB1 DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 360 | * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
360 | * DBGMCU_CR_APB1 DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 361 | * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
361 | * DBGMCU_CR_APB1 DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 362 | * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
362 | * DBGMCU_CR_APB1 DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 363 | * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
363 | * DBGMCU_CR_APB1 DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 364 | * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
364 | * DBGMCU_CR_APB1 DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 365 | * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
365 | * DBGMCU_CR_APB1 DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 366 | * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
366 | * DBGMCU_CR_APB1 DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 367 | * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
367 | * DBGMCU_CR_APB1 DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 368 | * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
368 | * DBGMCU_CR_APB1 DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 369 | * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
369 | * DBGMCU_CR_APB1 DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 370 | * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph |
370 | * DBGMCU_CR_APB1 DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n |
| 371 | * @param Periphs This parameter can be a combination of the following values: |
371 | * DBGMCU_CR_APB1 DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph |
| 372 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
372 | * @param Periphs This parameter can be a combination of the following values: |
| 373 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
373 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP |
| 374 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
374 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP |
| 375 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
375 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP |
| 376 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
376 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP |
| 377 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
377 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP |
| 378 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
378 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP |
| 379 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
379 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP |
| 380 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
380 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP |
| 381 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP |
381 | * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP |
| 382 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
382 | * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP |
| 383 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
383 | * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP |
| 384 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
384 | * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP |
| 385 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
385 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP |
| 386 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) |
386 | * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP (*) |
| 387 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
387 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP (*) |
| 388 | * |
388 | * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*) |
| 389 | * (*) value not defined in all devices. |
389 | * |
| 390 | * @retval None |
390 | * (*) value not defined in all devices. |
| 391 | */ |
391 | * @retval None |
| 392 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) |
392 | */ |
| 393 | { |
393 | __STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) |
| 394 | CLEAR_BIT(DBGMCU->CR, Periphs); |
394 | { |
| 395 | } |
395 | CLEAR_BIT(DBGMCU->CR, Periphs); |
| 396 | 396 | } |
|
| 397 | /** |
397 | |
| 398 | * @brief Freeze APB2 peripherals |
398 | /** |
| 399 | * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
399 | * @brief Freeze APB2 peripherals |
| 400 | * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
400 | * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 401 | * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
401 | * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 402 | * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
402 | * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 403 | * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
403 | * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 404 | * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
404 | * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 405 | * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
405 | * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 406 | * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
406 | * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 407 | * @param Periphs This parameter can be a combination of the following values: |
407 | * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
| 408 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
408 | * @param Periphs This parameter can be a combination of the following values: |
| 409 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
409 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
| 410 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) |
410 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
| 411 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) |
411 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) |
| 412 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) |
412 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) |
| 413 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) |
413 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) |
| 414 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) |
414 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) |
| 415 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
415 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) |
| 416 | * |
416 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
| 417 | * (*) value not defined in all devices. |
417 | * |
| 418 | * @retval None |
418 | * (*) value not defined in all devices. |
| 419 | */ |
419 | * @retval None |
| 420 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) |
420 | */ |
| 421 | { |
421 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) |
| 422 | SET_BIT(DBGMCU->CR, Periphs); |
422 | { |
| 423 | } |
423 | SET_BIT(DBGMCU->CR, Periphs); |
| 424 | 424 | } |
|
| 425 | /** |
425 | |
| 426 | * @brief Unfreeze APB2 peripherals |
426 | /** |
| 427 | * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
427 | * @brief Unfreeze APB2 peripherals |
| 428 | * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
428 | * @rmtoll DBGMCU_CR_APB2 DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 429 | * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
429 | * DBGMCU_CR_APB2 DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 430 | * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
430 | * DBGMCU_CR_APB2 DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 431 | * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
431 | * DBGMCU_CR_APB2 DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 432 | * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
432 | * DBGMCU_CR_APB2 DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 433 | * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
433 | * DBGMCU_CR_APB2 DBG_TIM15_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 434 | * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
434 | * DBGMCU_CR_APB2 DBG_TIM16_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n |
| 435 | * @param Periphs This parameter can be a combination of the following values: |
435 | * DBGMCU_CR_APB2 DBG_TIM17_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph |
| 436 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
436 | * @param Periphs This parameter can be a combination of the following values: |
| 437 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
437 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP |
| 438 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) |
438 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP (*) |
| 439 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) |
439 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP (*) |
| 440 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) |
440 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP (*) |
| 441 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) |
441 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP (*) |
| 442 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) |
442 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP (*) |
| 443 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
443 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP (*) |
| 444 | * |
444 | * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP (*) |
| 445 | * (*) value not defined in all devices. |
445 | * |
| 446 | * @retval None |
446 | * (*) value not defined in all devices. |
| 447 | */ |
447 | * @retval None |
| 448 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) |
448 | */ |
| 449 | { |
449 | __STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) |
| 450 | CLEAR_BIT(DBGMCU->CR, Periphs); |
450 | { |
| 451 | } |
451 | CLEAR_BIT(DBGMCU->CR, Periphs); |
| 452 | /** |
452 | } |
| 453 | * @} |
453 | /** |
| 454 | */ |
454 | * @} |
| 455 | 455 | */ |
|
| 456 | #if defined(FLASH_ACR_LATENCY) |
456 | |
| 457 | /** @defgroup SYSTEM_LL_EF_FLASH FLASH |
457 | #if defined(FLASH_ACR_LATENCY) |
| 458 | * @{ |
458 | /** @defgroup SYSTEM_LL_EF_FLASH FLASH |
| 459 | */ |
459 | * @{ |
| 460 | 460 | */ |
|
| 461 | /** |
461 | |
| 462 | * @brief Set FLASH Latency |
462 | /** |
| 463 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency |
463 | * @brief Set FLASH Latency |
| 464 | * @param Latency This parameter can be one of the following values: |
464 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency |
| 465 | * @arg @ref LL_FLASH_LATENCY_0 |
465 | * @param Latency This parameter can be one of the following values: |
| 466 | * @arg @ref LL_FLASH_LATENCY_1 |
466 | * @arg @ref LL_FLASH_LATENCY_0 |
| 467 | * @arg @ref LL_FLASH_LATENCY_2 |
467 | * @arg @ref LL_FLASH_LATENCY_1 |
| 468 | * @retval None |
468 | * @arg @ref LL_FLASH_LATENCY_2 |
| 469 | */ |
469 | * @retval None |
| 470 | __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) |
470 | */ |
| 471 | { |
471 | __STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) |
| 472 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); |
472 | { |
| 473 | } |
473 | MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); |
| 474 | 474 | } |
|
| 475 | /** |
475 | |
| 476 | * @brief Get FLASH Latency |
476 | /** |
| 477 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency |
477 | * @brief Get FLASH Latency |
| 478 | * @retval Returned value can be one of the following values: |
478 | * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency |
| 479 | * @arg @ref LL_FLASH_LATENCY_0 |
479 | * @retval Returned value can be one of the following values: |
| 480 | * @arg @ref LL_FLASH_LATENCY_1 |
480 | * @arg @ref LL_FLASH_LATENCY_0 |
| 481 | * @arg @ref LL_FLASH_LATENCY_2 |
481 | * @arg @ref LL_FLASH_LATENCY_1 |
| 482 | */ |
482 | * @arg @ref LL_FLASH_LATENCY_2 |
| 483 | __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) |
483 | */ |
| 484 | { |
484 | __STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) |
| 485 | return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); |
485 | { |
| 486 | } |
486 | return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); |
| 487 | 487 | } |
|
| 488 | /** |
488 | |
| 489 | * @brief Enable Prefetch |
489 | /** |
| 490 | * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch |
490 | * @brief Enable Prefetch |
| 491 | * @retval None |
491 | * @rmtoll FLASH_ACR PRFTBE LL_FLASH_EnablePrefetch |
| 492 | */ |
492 | * @retval None |
| 493 | __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) |
493 | */ |
| 494 | { |
494 | __STATIC_INLINE void LL_FLASH_EnablePrefetch(void) |
| 495 | SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); |
495 | { |
| 496 | } |
496 | SET_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); |
| 497 | 497 | } |
|
| 498 | /** |
498 | |
| 499 | * @brief Disable Prefetch |
499 | /** |
| 500 | * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch |
500 | * @brief Disable Prefetch |
| 501 | * @retval None |
501 | * @rmtoll FLASH_ACR PRFTBE LL_FLASH_DisablePrefetch |
| 502 | */ |
502 | * @retval None |
| 503 | __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) |
503 | */ |
| 504 | { |
504 | __STATIC_INLINE void LL_FLASH_DisablePrefetch(void) |
| 505 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); |
505 | { |
| 506 | } |
506 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTBE); |
| 507 | 507 | } |
|
| 508 | /** |
508 | |
| 509 | * @brief Check if Prefetch buffer is enabled |
509 | /** |
| 510 | * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled |
510 | * @brief Check if Prefetch buffer is enabled |
| 511 | * @retval State of bit (1 or 0). |
511 | * @rmtoll FLASH_ACR PRFTBS LL_FLASH_IsPrefetchEnabled |
| 512 | */ |
512 | * @retval State of bit (1 or 0). |
| 513 | __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) |
513 | */ |
| 514 | { |
514 | __STATIC_INLINE uint32_t LL_FLASH_IsPrefetchEnabled(void) |
| 515 | return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); |
515 | { |
| 516 | } |
516 | return (READ_BIT(FLASH->ACR, FLASH_ACR_PRFTBS) == (FLASH_ACR_PRFTBS)); |
| 517 | 517 | } |
|
| 518 | #endif /* FLASH_ACR_LATENCY */ |
518 | |
| 519 | /** |
519 | #endif /* FLASH_ACR_LATENCY */ |
| 520 | * @brief Enable Flash Half Cycle Access |
520 | /** |
| 521 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess |
521 | * @brief Enable Flash Half Cycle Access |
| 522 | * @retval None |
522 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_EnableHalfCycleAccess |
| 523 | */ |
523 | * @retval None |
| 524 | __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) |
524 | */ |
| 525 | { |
525 | __STATIC_INLINE void LL_FLASH_EnableHalfCycleAccess(void) |
| 526 | SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); |
526 | { |
| 527 | } |
527 | SET_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); |
| 528 | 528 | } |
|
| 529 | /** |
529 | |
| 530 | * @brief Disable Flash Half Cycle Access |
530 | /** |
| 531 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess |
531 | * @brief Disable Flash Half Cycle Access |
| 532 | * @retval None |
532 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_DisableHalfCycleAccess |
| 533 | */ |
533 | * @retval None |
| 534 | __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) |
534 | */ |
| 535 | { |
535 | __STATIC_INLINE void LL_FLASH_DisableHalfCycleAccess(void) |
| 536 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); |
536 | { |
| 537 | } |
537 | CLEAR_BIT(FLASH->ACR, FLASH_ACR_HLFCYA); |
| 538 | 538 | } |
|
| 539 | /** |
539 | |
| 540 | * @brief Check if Flash Half Cycle Access is enabled or not |
540 | /** |
| 541 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled |
541 | * @brief Check if Flash Half Cycle Access is enabled or not |
| 542 | * @retval State of bit (1 or 0). |
542 | * @rmtoll FLASH_ACR HLFCYA LL_FLASH_IsHalfCycleAccessEnabled |
| 543 | */ |
543 | * @retval State of bit (1 or 0). |
| 544 | __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) |
544 | */ |
| 545 | { |
545 | __STATIC_INLINE uint32_t LL_FLASH_IsHalfCycleAccessEnabled(void) |
| 546 | return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); |
546 | { |
| 547 | } |
547 | return (READ_BIT(FLASH->ACR, FLASH_ACR_HLFCYA) == (FLASH_ACR_HLFCYA)); |
| 548 | 548 | } |
|
| 549 | 549 | ||
| 550 | /** |
550 | |
| 551 | * @} |
551 | /** |
| 552 | */ |
552 | * @} |
| 553 | 553 | */ |
|
| 554 | /** |
554 | |
| 555 | * @} |
555 | /** |
| 556 | */ |
556 | * @} |
| 557 | 557 | */ |
|
| 558 | /** |
558 | |
| 559 | * @} |
559 | /** |
| 560 | */ |
560 | * @} |
| 561 | 561 | */ |
|
| 562 | #endif /* defined (FLASH) || defined (DBGMCU) */ |
562 | |
| 563 | 563 | #endif /* defined (FLASH) || defined (DBGMCU) */ |
|
| 564 | /** |
564 | |
| 565 | * @} |
565 | /** |
| 566 | */ |
566 | * @} |
| 567 | 567 | */ |
|
| 568 | #ifdef __cplusplus |
568 | |
| 569 | } |
569 | #ifdef __cplusplus |
| 570 | #endif |
570 | } |
| 571 | 571 | #endif |
|
| 572 | #endif /* __STM32F1xx_LL_SYSTEM_H */ |
572 | |
| 573 | 573 | #endif /* __STM32F1xx_LL_SYSTEM_H */ |
|
| 574 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
574 | |
| - | 575 | ||