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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_ll_sdmmc.h |
3 | * @file stm32f1xx_ll_sdmmc.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of low layer SDMMC HAL module. |
5 | * @brief Header file of SDMMC HAL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
9 | * <h2><center>© Copyright (c) 2018 STMicroelectronics. |
| - | 10 | * All rights reserved.</center></h2> |
|
| 10 | * |
11 | * |
| 11 | * Redistribution and use in source and binary forms, with or without modification, |
12 | * This software component is licensed by ST under BSD 3-Clause license, |
| 12 | * are permitted provided that the following conditions are met: |
13 | * the "License"; You may not use this file except in compliance with the |
| 13 | * 1. Redistributions of source code must retain the above copyright notice, |
- | |
| 14 | * this list of conditions and the following disclaimer. |
14 | * License. You may obtain a copy of the License at: |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
- | |
| 16 | * this list of conditions and the following disclaimer in the documentation |
- | |
| 17 | * and/or other materials provided with the distribution. |
15 | * opensource.org/licenses/BSD-3-Clause |
| 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
- | |
| 19 | * may be used to endorse or promote products derived from this software |
- | |
| 20 | * without specific prior written permission. |
- | |
| 21 | * |
- | |
| 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
- | |
| 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
- | |
| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
- | |
| 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
- | |
| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
- | |
| 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
- | |
| 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
- | |
| 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
- | |
| 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
- | |
| 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
- | |
| 32 | * |
16 | * |
| 33 | ****************************************************************************** |
17 | ****************************************************************************** |
| 34 | */ |
18 | */ |
| 35 | 19 | ||
| 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| 37 | #ifndef __stm32f1xx_LL_SD_H |
21 | #ifndef STM32F1xx_LL_SDMMC_H |
| 38 | #define __stm32f1xx_LL_SD_H |
22 | #define STM32F1xx_LL_SDMMC_H |
| 39 | - | ||
| 40 | #if defined(STM32F103xE) || defined(STM32F103xG) |
- | |
| 41 | 23 | ||
| 42 | #ifdef __cplusplus |
24 | #ifdef __cplusplus |
| 43 | extern "C" { |
25 | extern "C" { |
| 44 | #endif |
26 | #endif |
| 45 | 27 | ||
| - | 28 | #if defined(SDIO) |
|
| - | 29 | ||
| 46 | /* Includes ------------------------------------------------------------------*/ |
30 | /* Includes ------------------------------------------------------------------*/ |
| 47 | #include "stm32f1xx_hal_def.h" |
31 | #include "stm32f1xx_hal_def.h" |
| 48 | 32 | ||
| 49 | /** @addtogroup STM32F1xx_HAL_Driver |
33 | /** @addtogroup STM32F1xx_Driver |
| 50 | * @{ |
34 | * @{ |
| 51 | */ |
35 | */ |
| 52 | 36 | ||
| 53 | /** @addtogroup SDMMC_LL |
37 | /** @addtogroup SDMMC_LL |
| 54 | * @{ |
38 | * @{ |
| Line 65... | Line 49... | ||
| 65 | typedef struct |
49 | typedef struct |
| 66 | { |
50 | { |
| 67 | uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. |
51 | uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made. |
| 68 | This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ |
52 | This parameter can be a value of @ref SDMMC_LL_Clock_Edge */ |
| 69 | 53 | ||
| 70 | uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is |
54 | uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is |
| 71 | enabled or disabled. |
55 | enabled or disabled. |
| 72 | This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ |
56 | This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */ |
| 73 | 57 | ||
| 74 | uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or |
58 | uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or |
| 75 | disabled when the bus is idle. |
59 | disabled when the bus is idle. |
| 76 | This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ |
60 | This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */ |
| 77 | 61 | ||
| 78 | uint32_t BusWide; /*!< Specifies the SDIO bus width. |
62 | uint32_t BusWide; /*!< Specifies the SDMMC bus width. |
| 79 | This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ |
63 | This parameter can be a value of @ref SDMMC_LL_Bus_Wide */ |
| 80 | 64 | ||
| 81 | uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled. |
65 | uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled. |
| 82 | This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ |
66 | This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */ |
| 83 | 67 | ||
| 84 | uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller. |
68 | uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. |
| 85 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
69 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| 86 | 70 | ||
| 87 | }SDIO_InitTypeDef; |
71 | }SDIO_InitTypeDef; |
| 88 | 72 | ||
| 89 | 73 | ||
| 90 | /** |
74 | /** |
| 91 | * @brief SDIO Command Control structure |
75 | * @brief SDMMC Command Control structure |
| 92 | */ |
76 | */ |
| 93 | typedef struct |
77 | typedef struct |
| 94 | { |
78 | { |
| 95 | uint32_t Argument; /*!< Specifies the SDIO command argument which is sent |
79 | uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent |
| 96 | to a card as part of a command message. If a command |
80 | to a card as part of a command message. If a command |
| 97 | contains an argument, it must be loaded into this register |
81 | contains an argument, it must be loaded into this register |
| 98 | before writing the command to the command register. */ |
82 | before writing the command to the command register. */ |
| 99 | 83 | ||
| 100 | uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and |
84 | uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and |
| 101 | Max_Data = 64 */ |
85 | Max_Data = 64 */ |
| 102 | 86 | ||
| 103 | uint32_t Response; /*!< Specifies the SDIO response type. |
87 | uint32_t Response; /*!< Specifies the SDMMC response type. |
| 104 | This parameter can be a value of @ref SDMMC_LL_Response_Type */ |
88 | This parameter can be a value of @ref SDMMC_LL_Response_Type */ |
| 105 | 89 | ||
| 106 | uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is |
90 | uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is |
| 107 | enabled or disabled. |
91 | enabled or disabled. |
| 108 | This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ |
92 | This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */ |
| 109 | 93 | ||
| 110 | uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM) |
94 | uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM) |
| 111 | is enabled or disabled. |
95 | is enabled or disabled. |
| 112 | This parameter can be a value of @ref SDMMC_LL_CPSM_State */ |
96 | This parameter can be a value of @ref SDMMC_LL_CPSM_State */ |
| 113 | }SDIO_CmdInitTypeDef; |
97 | }SDIO_CmdInitTypeDef; |
| 114 | 98 | ||
| 115 | 99 | ||
| 116 | /** |
100 | /** |
| 117 | * @brief SDIO Data Control structure |
101 | * @brief SDMMC Data Control structure |
| 118 | */ |
102 | */ |
| 119 | typedef struct |
103 | typedef struct |
| 120 | { |
104 | { |
| 121 | uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ |
105 | uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */ |
| 122 | 106 | ||
| Line 130... | Line 114... | ||
| 130 | This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ |
114 | This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */ |
| 131 | 115 | ||
| 132 | uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. |
116 | uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode. |
| 133 | This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ |
117 | This parameter can be a value of @ref SDMMC_LL_Transfer_Type */ |
| 134 | 118 | ||
| 135 | uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM) |
119 | uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM) |
| 136 | is enabled or disabled. |
120 | is enabled or disabled. |
| 137 | This parameter can be a value of @ref SDMMC_LL_DPSM_State */ |
121 | This parameter can be a value of @ref SDMMC_LL_DPSM_State */ |
| 138 | }SDIO_DataInitTypeDef; |
122 | }SDIO_DataInitTypeDef; |
| 139 | 123 | ||
| 140 | /** |
124 | /** |
| Line 143... | Line 127... | ||
| 143 | 127 | ||
| 144 | /* Exported constants --------------------------------------------------------*/ |
128 | /* Exported constants --------------------------------------------------------*/ |
| 145 | /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants |
129 | /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants |
| 146 | * @{ |
130 | * @{ |
| 147 | */ |
131 | */ |
| 148 | #define SDMMC_ERROR_NONE 0x00000000U /*!< No error */ |
132 | #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
| 149 | #define SDMMC_ERROR_CMD_CRC_FAIL 0x00000001U /*!< Command response received (but CRC check failed) */ |
133 | #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */ |
| 150 | #define SDMMC_ERROR_DATA_CRC_FAIL 0x00000002U /*!< Data block sent/received (CRC check failed) */ |
134 | #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */ |
| 151 | #define SDMMC_ERROR_CMD_RSP_TIMEOUT 0x00000004U /*!< Command response timeout */ |
135 | #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */ |
| 152 | #define SDMMC_ERROR_DATA_TIMEOUT 0x00000008U /*!< Data timeout */ |
136 | #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */ |
| 153 | #define SDMMC_ERROR_TX_UNDERRUN 0x00000010U /*!< Transmit FIFO underrun */ |
137 | #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */ |
| 154 | #define SDMMC_ERROR_RX_OVERRUN 0x00000020U /*!< Receive FIFO overrun */ |
138 | #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */ |
| 155 | #define SDMMC_ERROR_ADDR_MISALIGNED 0x00000040U /*!< Misaligned address */ |
139 | #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */ |
| 156 | #define SDMMC_ERROR_BLOCK_LEN_ERR 0x00000080U /*!< Transferred block length is not allowed for the card or the |
140 | #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the |
| 157 | number of transferred bytes does not match the block length */ |
141 | number of transferred bytes does not match the block length */ |
| 158 | #define SDMMC_ERROR_ERASE_SEQ_ERR 0x00000100U /*!< An error in the sequence of erase command occurs */ |
142 | #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */ |
| 159 | #define SDMMC_ERROR_BAD_ERASE_PARAM 0x00000200U /*!< An invalid selection for erase groups */ |
143 | #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */ |
| 160 | #define SDMMC_ERROR_WRITE_PROT_VIOLATION 0x00000400U /*!< Attempt to program a write protect block */ |
144 | #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */ |
| 161 | #define SDMMC_ERROR_LOCK_UNLOCK_FAILED 0x00000800U /*!< Sequence or password error has been detected in unlock |
145 | #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock |
| 162 | command or if there was an attempt to access a locked card */ |
146 | command or if there was an attempt to access a locked card */ |
| 163 | #define SDMMC_ERROR_COM_CRC_FAILED 0x00001000U /*!< CRC check of the previous command failed */ |
147 | #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */ |
| 164 | #define SDMMC_ERROR_ILLEGAL_CMD 0x00002000U /*!< Command is not legal for the card state */ |
148 | #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */ |
| 165 | #define SDMMC_ERROR_CARD_ECC_FAILED 0x00004000U /*!< Card internal ECC was applied but failed to correct the data */ |
149 | #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */ |
| 166 | #define SDMMC_ERROR_CC_ERR 0x00008000U /*!< Internal card controller error */ |
150 | #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */ |
| 167 | #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR 0x00010000U /*!< General or unknown error */ |
151 | #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */ |
| 168 | #define SDMMC_ERROR_STREAM_READ_UNDERRUN 0x00020000U /*!< The card could not sustain data reading in stream rmode */ |
152 | #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */ |
| 169 | #define SDMMC_ERROR_STREAM_WRITE_OVERRUN 0x00040000U /*!< The card could not sustain data programming in stream mode */ |
153 | #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */ |
| 170 | #define SDMMC_ERROR_CID_CSD_OVERWRITE 0x00080000U /*!< CID/CSD overwrite error */ |
154 | #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */ |
| 171 | #define SDMMC_ERROR_WP_ERASE_SKIP 0x00100000U /*!< Only partial address space was erased */ |
155 | #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */ |
| 172 | #define SDMMC_ERROR_CARD_ECC_DISABLED 0x00200000U /*!< Command has been executed without using internal ECC */ |
156 | #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */ |
| 173 | #define SDMMC_ERROR_ERASE_RESET 0x00400000U /*!< Erase sequence was cleared before executing because an out |
157 | #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out |
| 174 | of erase sequence command was received */ |
158 | of erase sequence command was received */ |
| 175 | #define SDMMC_ERROR_AKE_SEQ_ERR 0x00800000U /*!< Error in sequence of authentication */ |
159 | #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */ |
| 176 | #define SDMMC_ERROR_INVALID_VOLTRANGE 0x01000000U /*!< Error in case of invalid voltage range */ |
160 | #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */ |
| 177 | #define SDMMC_ERROR_ADDR_OUT_OF_RANGE 0x02000000U /*!< Error when addressed block is out of range */ |
161 | #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */ |
| 178 | #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE 0x04000000U /*!< Error when command request is not applicable */ |
162 | #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */ |
| 179 | #define SDMMC_ERROR_INVALID_PARAMETER 0x08000000U /*!< the used parameter is not valid */ |
163 | #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */ |
| 180 | #define SDMMC_ERROR_UNSUPPORTED_FEATURE 0x10000000U /*!< Error when feature is not insupported */ |
164 | #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */ |
| 181 | #define SDMMC_ERROR_BUSY 0x20000000U /*!< Error when transfer process is busy */ |
165 | #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */ |
| 182 | #define SDMMC_ERROR_DMA 0x40000000U /*!< Error while DMA transfer */ |
166 | #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ |
| 183 | #define SDMMC_ERROR_TIMEOUT 0x80000000U /*!< Timeout error */ |
167 | #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ |
| 184 | 168 | ||
| 185 | /** |
169 | /** |
| 186 | * @brief SDMMC Commands Index |
170 | * @brief SDMMC Commands Index |
| 187 | */ |
171 | */ |
| 188 | #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0) /*!< Resets the SD memory card. */ |
172 | #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ |
| 189 | #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1) /*!< Sends host capacity support information and activates the card's initialization process. */ |
173 | #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ |
| 190 | #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ |
174 | #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ |
| 191 | #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3) /*!< Asks the card to publish a new relative address (RCA). */ |
175 | #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ |
| 192 | #define SDMMC_CMD_SET_DSR ((uint8_t)4) /*!< Programs the DSR of all cards. */ |
176 | #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ |
| 193 | #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its |
177 | #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its |
| 194 | operating condition register (OCR) content in the response on the CMD line. */ |
178 | operating condition register (OCR) content in the response on the CMD line. */ |
| 195 | #define SDMMC_CMD_HS_SWITCH ((uint8_t)6) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ |
179 | #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ |
| 196 | #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7) /*!< Selects the card by its own relative address and gets deselected by any other address */ |
180 | #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ |
| 197 | #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information |
181 | #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information |
| 198 | and asks the card whether card supports voltage. */ |
182 | and asks the card whether card supports voltage. */ |
| 199 | #define SDMMC_CMD_SEND_CSD ((uint8_t)9) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ |
183 | #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ |
| 200 | #define SDMMC_CMD_SEND_CID ((uint8_t)10) /*!< Addressed card sends its card identification (CID) on the CMD line. */ |
184 | #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ |
| 201 | #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD card doesn't support it. */ |
185 | #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */ |
| 202 | #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12) /*!< Forces the card to stop transmission. */ |
186 | #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ |
| 203 | #define SDMMC_CMD_SEND_STATUS ((uint8_t)13) /*!< Addressed card sends its status register. */ |
187 | #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ |
| 204 | #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14) /*!< Reserved */ |
188 | #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ |
| 205 | #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15) /*!< Sends an addressed card into the inactive state. */ |
189 | #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ |
| 206 | #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16) /*!< Sets the block length (in bytes for SDSC) for all following block commands |
190 | #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands |
| 207 | (read, write, lock). Default block length is fixed to 512 Bytes. Not effective |
191 | (read, write, lock). Default block length is fixed to 512 Bytes. Not effective |
| 208 | for SDHS and SDXC. */ |
192 | for SDHS and SDXC. */ |
| 209 | #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
193 | #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
| 210 | fixed 512 bytes in case of SDHC and SDXC. */ |
194 | fixed 512 bytes in case of SDHC and SDXC. */ |
| 211 | #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18) /*!< Continuously transfers data blocks from card to host until interrupted by |
195 | #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by |
| 212 | STOP_TRANSMISSION command. */ |
196 | STOP_TRANSMISSION command. */ |
| 213 | #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ |
197 | #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ |
| 214 | #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< Speed class control command. */ |
198 | #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ |
| 215 | #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< Specify block count for CMD18 and CMD25. */ |
199 | #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ |
| 216 | #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
200 | #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of |
| 217 | fixed 512 bytes in case of SDHC and SDXC. */ |
201 | fixed 512 bytes in case of SDHC and SDXC. */ |
| 218 | #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ |
202 | #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ |
| 219 | #define SDMMC_CMD_PROG_CID ((uint8_t)26) /*!< Reserved for manufacturers. */ |
203 | #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ |
| 220 | #define SDMMC_CMD_PROG_CSD ((uint8_t)27) /*!< Programming of the programmable bits of the CSD. */ |
204 | #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ |
| 221 | #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28) /*!< Sets the write protection bit of the addressed group. */ |
205 | #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ |
| 222 | #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29) /*!< Clears the write protection bit of the addressed group. */ |
206 | #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ |
| 223 | #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30) /*!< Asks the card to send the status of the write protection bits. */ |
207 | #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ |
| 224 | #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< Sets the address of the first write block to be erased. (For SD card only). */ |
208 | #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ |
| 225 | #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< Sets the address of the last write block of the continuous range to be erased. */ |
209 | #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ |
| 226 | #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35) /*!< Sets the address of the first write block to be erased. Reserved for each command |
210 | #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command |
| 227 | system set by switch function command (CMD6). */ |
211 | system set by switch function command (CMD6). */ |
| 228 | #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36) /*!< Sets the address of the last write block of the continuous range to be erased. |
212 | #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. |
| 229 | Reserved for each command system set by switch function command (CMD6). */ |
213 | Reserved for each command system set by switch function command (CMD6). */ |
| 230 | #define SDMMC_CMD_ERASE ((uint8_t)38) /*!< Reserved for SD security applications. */ |
214 | #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ |
| 231 | #define SDMMC_CMD_FAST_IO ((uint8_t)39) /*!< SD card doesn't support it (Reserved). */ |
215 | #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ |
| 232 | #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD card doesn't support it (Reserved). */ |
216 | #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ |
| 233 | #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by |
217 | #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by |
| 234 | the SET_BLOCK_LEN command. */ |
218 | the SET_BLOCK_LEN command. */ |
| 235 | #define SDMMC_CMD_APP_CMD ((uint8_t)55) /*!< Indicates to the card that the next command is an application specific command rather |
219 | #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather |
| 236 | than a standard command. */ |
220 | than a standard command. */ |
| 237 | #define SDMMC_CMD_GEN_CMD ((uint8_t)56) /*!< Used either to transfer a data block to the card or to get a data block from the card |
221 | #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card |
| 238 | for general purpose/application specific commands. */ |
222 | for general purpose/application specific commands. */ |
| 239 | #define SDMMC_CMD_NO_CMD ((uint8_t)64) /*!< No command */ |
223 | #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ |
| 240 | 224 | ||
| 241 | /** |
225 | /** |
| 242 | * @brief Following commands are SD Card Specific commands. |
226 | * @brief Following commands are SD Card Specific commands. |
| 243 | * SDMMC_APP_CMD should be sent before sending these commands. |
227 | * SDMMC_APP_CMD should be sent before sending these commands. |
| 244 | */ |
228 | */ |
| 245 | #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus |
229 | #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus |
| 246 | widths are given in SCR register. */ |
230 | widths are given in SCR register. */ |
| 247 | #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13) /*!< (ACMD13) Sends the SD status. */ |
231 | #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ |
| 248 | #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with |
232 | #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with |
| 249 | 32bit+CRC data block. */ |
233 | 32bit+CRC data block. */ |
| 250 | #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to |
234 | #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to |
| 251 | send its operating condition register (OCR) content in the response on the CMD line. */ |
235 | send its operating condition register (OCR) content in the response on the CMD line. */ |
| 252 | #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ |
236 | #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ |
| 253 | #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< Reads the SD Configuration Register (SCR). */ |
237 | #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ |
| 254 | #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52) /*!< For SD I/O card only, reserved for security specification. */ |
238 | #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ |
| 255 | #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O card only, reserved for security specification. */ |
239 | #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ |
| 256 | 240 | ||
| 257 | /** |
241 | /** |
| 258 | * @brief Following commands are SD Card Specific security commands. |
242 | * @brief Following commands are SD Card Specific security commands. |
| 259 | * SDMMC_CMD_APP_CMD should be sent before sending these commands. |
243 | * SDMMC_CMD_APP_CMD should be sent before sending these commands. |
| 260 | */ |
244 | */ |
| 261 | #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43) |
245 | #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) |
| 262 | #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44) |
246 | #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) |
| 263 | #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) |
247 | #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) |
| 264 | #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) |
248 | #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) |
| 265 | #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) |
249 | #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) |
| 266 | #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) |
250 | #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) |
| 267 | #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) |
251 | #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) |
| 268 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) |
252 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) |
| 269 | #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) |
253 | #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) |
| 270 | #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) |
254 | #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) |
| 271 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) |
255 | #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) |
| 272 | 256 | ||
| 273 | /** |
257 | /** |
| 274 | * @brief Masks for errors Card Status R1 (OCR Register) |
258 | * @brief Masks for errors Card Status R1 (OCR Register) |
| 275 | */ |
259 | */ |
| 276 | #define SDMMC_OCR_ADDR_OUT_OF_RANGE 0x80000000U |
260 | #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U) |
| 277 | #define SDMMC_OCR_ADDR_MISALIGNED 0x40000000U |
261 | #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U) |
| 278 | #define SDMMC_OCR_BLOCK_LEN_ERR 0x20000000U |
262 | #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U) |
| 279 | #define SDMMC_OCR_ERASE_SEQ_ERR 0x10000000U |
263 | #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U) |
| 280 | #define SDMMC_OCR_BAD_ERASE_PARAM 0x08000000U |
264 | #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U) |
| 281 | #define SDMMC_OCR_WRITE_PROT_VIOLATION 0x04000000U |
265 | #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U) |
| 282 | #define SDMMC_OCR_LOCK_UNLOCK_FAILED 0x01000000U |
266 | #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U) |
| 283 | #define SDMMC_OCR_COM_CRC_FAILED 0x00800000U |
267 | #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U) |
| 284 | #define SDMMC_OCR_ILLEGAL_CMD 0x00400000U |
268 | #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U) |
| 285 | #define SDMMC_OCR_CARD_ECC_FAILED 0x00200000U |
269 | #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U) |
| 286 | #define SDMMC_OCR_CC_ERROR 0x00100000U |
270 | #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U) |
| 287 | #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR 0x00080000U |
271 | #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U) |
| 288 | #define SDMMC_OCR_STREAM_READ_UNDERRUN 0x00040000U |
272 | #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U) |
| 289 | #define SDMMC_OCR_STREAM_WRITE_OVERRUN 0x00020000U |
273 | #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U) |
| 290 | #define SDMMC_OCR_CID_CSD_OVERWRITE 0x00010000U |
274 | #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U) |
| 291 | #define SDMMC_OCR_WP_ERASE_SKIP 0x00008000U |
275 | #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U) |
| 292 | #define SDMMC_OCR_CARD_ECC_DISABLED 0x00004000U |
276 | #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U) |
| 293 | #define SDMMC_OCR_ERASE_RESET 0x00002000U |
277 | #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U) |
| 294 | #define SDMMC_OCR_AKE_SEQ_ERROR 0x00000008U |
278 | #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U) |
| 295 | #define SDMMC_OCR_ERRORBITS 0xFDFFE008U |
279 | #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U) |
| 296 | 280 | ||
| 297 | /** |
281 | /** |
| 298 | * @brief Masks for R6 Response |
282 | * @brief Masks for R6 Response |
| 299 | */ |
283 | */ |
| 300 | #define SDMMC_R6_GENERAL_UNKNOWN_ERROR 0x00002000U |
284 | #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U) |
| 301 | #define SDMMC_R6_ILLEGAL_CMD 0x00004000U |
285 | #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U) |
| 302 | #define SDMMC_R6_COM_CRC_FAILED 0x00008000U |
286 | #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U) |
| 303 | - | ||
| 304 | #define SDMMC_VOLTAGE_WINDOW_SD 0x80100000U |
- | |
| 305 | #define SDMMC_HIGH_CAPACITY 0x40000000U |
- | |
| 306 | #define SDMMC_STD_CAPACITY 0x00000000U |
- | |
| 307 | #define SDMMC_CHECK_PATTERN 0x000001AAU |
- | |
| 308 | 287 | ||
| - | 288 | #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U) |
|
| - | 289 | #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U) |
|
| - | 290 | #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U) |
|
| 309 | #define SDMMC_MAX_VOLT_TRIAL 0x0000FFFFU |
291 | #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU) |
| - | 292 | #define SD_SWITCH_1_8V_CAPACITY ((uint32_t)0x01000000U) |
|
| 310 | 293 | ||
| 311 | #define SDMMC_MAX_TRIAL 0x0000FFFFU |
294 | #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU) |
| 312 | 295 | ||
| 313 | #define SDMMC_ALLZERO 0x00000000U |
296 | #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU) |
| 314 | 297 | ||
| 315 | #define SDMMC_WIDE_BUS_SUPPORT 0x00040000U |
- | |
| 316 | #define SDMMC_SINGLE_BUS_SUPPORT 0x00010000U |
- | |
| 317 | #define SDMMC_CARD_LOCKED 0x02000000U |
- | |
| 318 | - | ||
| 319 | #define SDMMC_DATATIMEOUT 0xFFFFFFFFU |
- | |
| 320 | - | ||
| 321 | #define SDMMC_0TO7BITS 0x000000FFU |
298 | #define SDMMC_ALLZERO ((uint32_t)0x00000000U) |
| 322 | #define SDMMC_8TO15BITS 0x0000FF00U |
- | |
| 323 | #define SDMMC_16TO23BITS 0x00FF0000U |
- | |
| 324 | #define SDMMC_24TO31BITS 0xFF000000U |
- | |
| 325 | #define SDMMC_MAX_DATA_LENGTH 0x01FFFFFFU |
- | |
| 326 | 299 | ||
| - | 300 | #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U) |
|
| - | 301 | #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) |
|
| - | 302 | #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) |
|
| - | 303 | ||
| - | 304 | #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) |
|
| - | 305 | ||
| - | 306 | #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) |
|
| - | 307 | #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U) |
|
| - | 308 | #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U) |
|
| - | 309 | #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U) |
|
| - | 310 | #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU) |
|
| - | 311 | ||
| 327 | #define SDMMC_HALFFIFO 0x00000008U |
312 | #define SDMMC_HALFFIFO ((uint32_t)0x00000008U) |
| 328 | #define SDMMC_HALFFIFOBYTES 0x00000020U |
313 | #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U) |
| 329 | 314 | ||
| 330 | /** |
315 | /** |
| 331 | * @brief Command Class supported |
316 | * @brief Command Class supported |
| 332 | */ |
317 | */ |
| 333 | #define SDIO_CCCC_ERASE 0x00000020U |
318 | #define SDIO_CCCC_ERASE ((uint32_t)0x00000020U) |
| 334 | - | ||
| 335 | #define SDIO_CMDTIMEOUT 5000U /* Command send and response timeout */ |
- | |
| 336 | #define SDIO_MAXERASETIMEOUT 63000U /* Max erase Timeout 63 s */ |
- | |
| 337 | 319 | ||
| - | 320 | #define SDIO_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */ |
|
| - | 321 | #define SDIO_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */ |
|
| - | 322 | #define SDIO_STOPTRANSFERTIMEOUT ((uint32_t)100000000U) /* Timeout for STOP TRANSMISSION command */ |
|
| 338 | 323 | ||
| 339 | /** @defgroup SDIO_LL_Clock_Edge Clock Edge |
324 | /** @defgroup SDIO_LL_Clock_Edge Clock Edge |
| 340 | * @{ |
325 | * @{ |
| 341 | */ |
326 | */ |
| 342 | #define SDIO_CLOCK_EDGE_RISING 0x00000000U |
327 | #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000U) |
| 343 | #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE |
328 | #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE |
| 344 | 329 | ||
| 345 | #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ |
330 | #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \ |
| 346 | ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) |
331 | ((EDGE) == SDIO_CLOCK_EDGE_FALLING)) |
| 347 | /** |
332 | /** |
| 348 | * @} |
333 | * @} |
| 349 | */ |
334 | */ |
| 350 | 335 | ||
| 351 | /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass |
336 | /** @defgroup SDIO_LL_Clock_Bypass Clock Bypass |
| 352 | * @{ |
337 | * @{ |
| 353 | */ |
338 | */ |
| 354 | #define SDIO_CLOCK_BYPASS_DISABLE 0x00000000U |
339 | #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U) |
| 355 | #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS |
340 | #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS |
| 356 | 341 | ||
| 357 | #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ |
342 | #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \ |
| 358 | ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) |
343 | ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE)) |
| 359 | /** |
344 | /** |
| 360 | * @} |
345 | * @} |
| 361 | */ |
346 | */ |
| 362 | 347 | ||
| 363 | /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving |
348 | /** @defgroup SDIO_LL_Clock_Power_Save Clock Power Saving |
| 364 | * @{ |
349 | * @{ |
| 365 | */ |
350 | */ |
| 366 | #define SDIO_CLOCK_POWER_SAVE_DISABLE 0x00000000U |
351 | #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U) |
| 367 | #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV |
352 | #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV |
| 368 | 353 | ||
| 369 | #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ |
354 | #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \ |
| 370 | ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) |
355 | ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE)) |
| 371 | /** |
356 | /** |
| 372 | * @} |
357 | * @} |
| 373 | */ |
358 | */ |
| 374 | 359 | ||
| 375 | /** @defgroup SDIO_LL_Bus_Wide Bus Width |
360 | /** @defgroup SDIO_LL_Bus_Wide Bus Width |
| 376 | * @{ |
361 | * @{ |
| 377 | */ |
362 | */ |
| 378 | #define SDIO_BUS_WIDE_1B 0x00000000U |
363 | #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000U) |
| 379 | #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 |
364 | #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0 |
| 380 | #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 |
365 | #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1 |
| 381 | 366 | ||
| 382 | #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ |
367 | #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \ |
| 383 | ((WIDE) == SDIO_BUS_WIDE_4B) || \ |
368 | ((WIDE) == SDIO_BUS_WIDE_4B) || \ |
| 384 | ((WIDE) == SDIO_BUS_WIDE_8B)) |
369 | ((WIDE) == SDIO_BUS_WIDE_8B)) |
| 385 | /** |
370 | /** |
| 386 | * @} |
371 | * @} |
| 387 | */ |
372 | */ |
| 388 | 373 | ||
| 389 | /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control |
374 | /** @defgroup SDIO_LL_Hardware_Flow_Control Hardware Flow Control |
| 390 | * @{ |
375 | * @{ |
| 391 | */ |
376 | */ |
| 392 | #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE 0x00000000U |
377 | #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U) |
| 393 | #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN |
378 | #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN |
| 394 | 379 | ||
| 395 | #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ |
380 | #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \ |
| 396 | ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) |
381 | ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE)) |
| 397 | /** |
382 | /** |
| 398 | * @} |
383 | * @} |
| 399 | */ |
384 | */ |
| 400 | 385 | ||
| 401 | /** @defgroup SDIO_LL_Clock_Division Clock Division |
386 | /** @defgroup SDIO_LL_Clock_Division Clock Division |
| Line 415... | Line 400... | ||
| 415 | */ |
400 | */ |
| 416 | 401 | ||
| 417 | /** @defgroup SDIO_LL_Response_Type Response Type |
402 | /** @defgroup SDIO_LL_Response_Type Response Type |
| 418 | * @{ |
403 | * @{ |
| 419 | */ |
404 | */ |
| 420 | #define SDIO_RESPONSE_NO 0x00000000U |
405 | #define SDIO_RESPONSE_NO ((uint32_t)0x00000000U) |
| 421 | #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 |
406 | #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0 |
| 422 | #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP |
407 | #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP |
| 423 | 408 | ||
| 424 | #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ |
409 | #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \ |
| 425 | ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ |
410 | ((RESPONSE) == SDIO_RESPONSE_SHORT) || \ |
| 426 | ((RESPONSE) == SDIO_RESPONSE_LONG)) |
411 | ((RESPONSE) == SDIO_RESPONSE_LONG)) |
| 427 | /** |
412 | /** |
| 428 | * @} |
413 | * @} |
| 429 | */ |
414 | */ |
| 430 | 415 | ||
| 431 | /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt |
416 | /** @defgroup SDIO_LL_Wait_Interrupt_State Wait Interrupt |
| 432 | * @{ |
417 | * @{ |
| 433 | */ |
418 | */ |
| 434 | #define SDIO_WAIT_NO 0x00000000U |
419 | #define SDIO_WAIT_NO ((uint32_t)0x00000000U) |
| 435 | #define SDIO_WAIT_IT SDIO_CMD_WAITINT |
420 | #define SDIO_WAIT_IT SDIO_CMD_WAITINT |
| 436 | #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND |
421 | #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND |
| 437 | 422 | ||
| 438 | #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ |
423 | #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \ |
| 439 | ((WAIT) == SDIO_WAIT_IT) || \ |
424 | ((WAIT) == SDIO_WAIT_IT) || \ |
| 440 | ((WAIT) == SDIO_WAIT_PEND)) |
425 | ((WAIT) == SDIO_WAIT_PEND)) |
| 441 | /** |
426 | /** |
| 442 | * @} |
427 | * @} |
| 443 | */ |
428 | */ |
| 444 | 429 | ||
| 445 | /** @defgroup SDIO_LL_CPSM_State CPSM State |
430 | /** @defgroup SDIO_LL_CPSM_State CPSM State |
| 446 | * @{ |
431 | * @{ |
| 447 | */ |
432 | */ |
| 448 | #define SDIO_CPSM_DISABLE 0x00000000U |
433 | #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000U) |
| 449 | #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN |
434 | #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN |
| 450 | 435 | ||
| 451 | #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ |
436 | #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \ |
| 452 | ((CPSM) == SDIO_CPSM_ENABLE)) |
437 | ((CPSM) == SDIO_CPSM_ENABLE)) |
| 453 | /** |
438 | /** |
| 454 | * @} |
439 | * @} |
| 455 | */ |
440 | */ |
| 456 | 441 | ||
| 457 | /** @defgroup SDIO_LL_Response_Registers Response Register |
442 | /** @defgroup SDIO_LL_Response_Registers Response Register |
| 458 | * @{ |
443 | * @{ |
| 459 | */ |
444 | */ |
| 460 | #define SDIO_RESP1 0x00000000U |
445 | #define SDIO_RESP1 ((uint32_t)0x00000000U) |
| 461 | #define SDIO_RESP2 0x00000004U |
446 | #define SDIO_RESP2 ((uint32_t)0x00000004U) |
| 462 | #define SDIO_RESP3 0x00000008U |
447 | #define SDIO_RESP3 ((uint32_t)0x00000008U) |
| 463 | #define SDIO_RESP4 0x0000000CU |
448 | #define SDIO_RESP4 ((uint32_t)0x0000000CU) |
| 464 | 449 | ||
| 465 | #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ |
450 | #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \ |
| 466 | ((RESP) == SDIO_RESP2) || \ |
451 | ((RESP) == SDIO_RESP2) || \ |
| 467 | ((RESP) == SDIO_RESP3) || \ |
452 | ((RESP) == SDIO_RESP3) || \ |
| 468 | ((RESP) == SDIO_RESP4)) |
453 | ((RESP) == SDIO_RESP4)) |
| 469 | /** |
454 | /** |
| 470 | * @} |
455 | * @} |
| 471 | */ |
456 | */ |
| 472 | 457 | ||
| 473 | /** @defgroup SDIO_LL_Data_Length Data Lenght |
458 | /** @defgroup SDIO_LL_Data_Length Data Lenght |
| Line 479... | Line 464... | ||
| 479 | */ |
464 | */ |
| 480 | 465 | ||
| 481 | /** @defgroup SDIO_LL_Data_Block_Size Data Block Size |
466 | /** @defgroup SDIO_LL_Data_Block_Size Data Block Size |
| 482 | * @{ |
467 | * @{ |
| 483 | */ |
468 | */ |
| 484 | #define SDIO_DATABLOCK_SIZE_1B 0x00000000U |
469 | #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U) |
| 485 | #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 |
470 | #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0 |
| 486 | #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 |
471 | #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1 |
| 487 | #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) |
472 | #define SDIO_DATABLOCK_SIZE_8B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_1) |
| 488 | #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 |
473 | #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2 |
| 489 | #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) |
474 | #define SDIO_DATABLOCK_SIZE_32B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2) |
| Line 496... | Line 481... | ||
| 496 | #define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
481 | #define SDIO_DATABLOCK_SIZE_4096B (SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
| 497 | #define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
482 | #define SDIO_DATABLOCK_SIZE_8192B (SDIO_DCTRL_DBLOCKSIZE_0|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
| 498 | #define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
483 | #define SDIO_DATABLOCK_SIZE_16384B (SDIO_DCTRL_DBLOCKSIZE_1|SDIO_DCTRL_DBLOCKSIZE_2|SDIO_DCTRL_DBLOCKSIZE_3) |
| 499 | 484 | ||
| 500 | #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ |
485 | #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \ |
| 501 | ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ |
486 | ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \ |
| 502 | ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ |
487 | ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \ |
| 503 | ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ |
488 | ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \ |
| 504 | ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ |
489 | ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \ |
| 505 | ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ |
490 | ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \ |
| 506 | ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ |
491 | ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \ |
| 507 | ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ |
492 | ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \ |
| 508 | ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ |
493 | ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \ |
| 509 | ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ |
494 | ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \ |
| 510 | ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ |
495 | ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \ |
| 511 | ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ |
496 | ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \ |
| 512 | ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ |
497 | ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \ |
| 513 | ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ |
498 | ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \ |
| 514 | ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) |
499 | ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) |
| 515 | /** |
500 | /** |
| 516 | * @} |
501 | * @} |
| 517 | */ |
502 | */ |
| 518 | 503 | ||
| 519 | /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction |
504 | /** @defgroup SDIO_LL_Transfer_Direction Transfer Direction |
| 520 | * @{ |
505 | * @{ |
| 521 | */ |
506 | */ |
| 522 | #define SDIO_TRANSFER_DIR_TO_CARD 0x00000000U |
507 | #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U) |
| 523 | #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR |
508 | #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR |
| 524 | 509 | ||
| 525 | #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ |
510 | #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \ |
| 526 | ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) |
511 | ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO)) |
| 527 | /** |
512 | /** |
| 528 | * @} |
513 | * @} |
| 529 | */ |
514 | */ |
| 530 | 515 | ||
| 531 | /** @defgroup SDIO_LL_Transfer_Type Transfer Type |
516 | /** @defgroup SDIO_LL_Transfer_Type Transfer Type |
| 532 | * @{ |
517 | * @{ |
| 533 | */ |
518 | */ |
| 534 | #define SDIO_TRANSFER_MODE_BLOCK 0x00000000U |
519 | #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U) |
| 535 | #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE |
520 | #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE |
| 536 | 521 | ||
| 537 | #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ |
522 | #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \ |
| 538 | ((MODE) == SDIO_TRANSFER_MODE_STREAM)) |
523 | ((MODE) == SDIO_TRANSFER_MODE_STREAM)) |
| 539 | /** |
524 | /** |
| 540 | * @} |
525 | * @} |
| 541 | */ |
526 | */ |
| 542 | 527 | ||
| 543 | /** @defgroup SDIO_LL_DPSM_State DPSM State |
528 | /** @defgroup SDIO_LL_DPSM_State DPSM State |
| 544 | * @{ |
529 | * @{ |
| 545 | */ |
530 | */ |
| 546 | #define SDIO_DPSM_DISABLE 0x00000000U |
531 | #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000U) |
| 547 | #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN |
532 | #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN |
| 548 | 533 | ||
| 549 | #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ |
534 | #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\ |
| 550 | ((DPSM) == SDIO_DPSM_ENABLE)) |
535 | ((DPSM) == SDIO_DPSM_ENABLE)) |
| 551 | /** |
536 | /** |
| 552 | * @} |
537 | * @} |
| 553 | */ |
538 | */ |
| 554 | 539 | ||
| 555 | /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode |
540 | /** @defgroup SDIO_LL_Read_Wait_Mode Read Wait Mode |
| 556 | * @{ |
541 | * @{ |
| 557 | */ |
542 | */ |
| 558 | #define SDIO_READ_WAIT_MODE_DATA2 0x00000000U |
543 | #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U) |
| 559 | #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) |
544 | #define SDIO_READ_WAIT_MODE_CLK (SDIO_DCTRL_RWMOD) |
| 560 | 545 | ||
| 561 | #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ |
546 | #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \ |
| 562 | ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) |
547 | ((MODE) == SDIO_READ_WAIT_MODE_DATA2)) |
| 563 | /** |
548 | /** |
| 564 | * @} |
549 | * @} |
| 565 | */ |
550 | */ |
| 566 | 551 | ||
| 567 | /** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources |
552 | /** @defgroup SDIO_LL_Interrupt_sources Interrupt Sources |
| 568 | * @{ |
553 | * @{ |
| 569 | */ |
554 | */ |
| 570 | #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL |
555 | #define SDIO_IT_CCRCFAIL SDIO_MASK_CCRCFAILIE |
| 571 | #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL |
556 | #define SDIO_IT_DCRCFAIL SDIO_MASK_DCRCFAILIE |
| 572 | #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT |
557 | #define SDIO_IT_CTIMEOUT SDIO_MASK_CTIMEOUTIE |
| 573 | #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT |
558 | #define SDIO_IT_DTIMEOUT SDIO_MASK_DTIMEOUTIE |
| 574 | #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR |
559 | #define SDIO_IT_TXUNDERR SDIO_MASK_TXUNDERRIE |
| 575 | #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR |
560 | #define SDIO_IT_RXOVERR SDIO_MASK_RXOVERRIE |
| 576 | #define SDIO_IT_CMDREND SDIO_STA_CMDREND |
561 | #define SDIO_IT_CMDREND SDIO_MASK_CMDRENDIE |
| 577 | #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT |
562 | #define SDIO_IT_CMDSENT SDIO_MASK_CMDSENTIE |
| 578 | #define SDIO_IT_DATAEND SDIO_STA_DATAEND |
563 | #define SDIO_IT_DATAEND SDIO_MASK_DATAENDIE |
| 579 | #define SDIO_IT_STBITERR SDIO_STA_STBITERR |
564 | #define SDIO_IT_STBITERR SDIO_MASK_STBITERRIE |
| 580 | #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND |
565 | #define SDIO_IT_DBCKEND SDIO_MASK_DBCKENDIE |
| 581 | #define SDIO_IT_CMDACT SDIO_STA_CMDACT |
566 | #define SDIO_IT_CMDACT SDIO_MASK_CMDACTIE |
| 582 | #define SDIO_IT_TXACT SDIO_STA_TXACT |
567 | #define SDIO_IT_TXACT SDIO_MASK_TXACTIE |
| 583 | #define SDIO_IT_RXACT SDIO_STA_RXACT |
568 | #define SDIO_IT_RXACT SDIO_MASK_RXACTIE |
| 584 | #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE |
569 | #define SDIO_IT_TXFIFOHE SDIO_MASK_TXFIFOHEIE |
| 585 | #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF |
570 | #define SDIO_IT_RXFIFOHF SDIO_MASK_RXFIFOHFIE |
| 586 | #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF |
571 | #define SDIO_IT_TXFIFOF SDIO_MASK_TXFIFOFIE |
| 587 | #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF |
572 | #define SDIO_IT_RXFIFOF SDIO_MASK_RXFIFOFIE |
| 588 | #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE |
573 | #define SDIO_IT_TXFIFOE SDIO_MASK_TXFIFOEIE |
| 589 | #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE |
574 | #define SDIO_IT_RXFIFOE SDIO_MASK_RXFIFOEIE |
| 590 | #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL |
575 | #define SDIO_IT_TXDAVL SDIO_MASK_TXDAVLIE |
| 591 | #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL |
576 | #define SDIO_IT_RXDAVL SDIO_MASK_RXDAVLIE |
| 592 | #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT |
577 | #define SDIO_IT_SDIOIT SDIO_MASK_SDIOITIE |
| 593 | #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND |
578 | #define SDIO_IT_CEATAEND SDIO_MASK_CEATAENDIE |
| 594 | /** |
579 | /** |
| 595 | * @} |
580 | * @} |
| 596 | */ |
581 | */ |
| 597 | 582 | ||
| 598 | /** @defgroup SDMMC_LL_Flags Flags |
583 | /** @defgroup SDIO_LL_Flags Flags |
| 599 | * @{ |
584 | * @{ |
| 600 | */ |
585 | */ |
| 601 | #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL |
586 | #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL |
| 602 | #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL |
587 | #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL |
| 603 | #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT |
588 | #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT |
| Line 623... | Line 608... | ||
| 623 | #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT |
608 | #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT |
| 624 | #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND |
609 | #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND |
| 625 | #define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ |
610 | #define SDIO_STATIC_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\ |
| 626 | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ |
611 | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR |\ |
| 627 | SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ |
612 | SDIO_FLAG_CMDREND | SDIO_FLAG_CMDSENT | SDIO_FLAG_DATAEND |\ |
| - | 613 | SDIO_FLAG_DBCKEND | SDIO_FLAG_SDIOIT)) |
|
| - | 614 | ||
| - | 615 | #define SDIO_STATIC_CMD_FLAGS ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CTIMEOUT | SDIO_FLAG_CMDREND |\ |
|
| 628 | SDIO_FLAG_DBCKEND)) |
616 | SDIO_FLAG_CMDSENT)) |
| - | 617 | ||
| - | 618 | #define SDIO_STATIC_DATA_FLAGS ((uint32_t)(SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR |\ |
|
| - | 619 | SDIO_FLAG_RXOVERR | SDIO_FLAG_DATAEND | SDIO_FLAG_DBCKEND)) |
|
| 629 | /** |
620 | /** |
| 630 | * @} |
621 | * @} |
| 631 | */ |
622 | */ |
| 632 | 623 | ||
| 633 | /** |
624 | /** |
| Line 714... | Line 705... | ||
| 714 | /* CMD Register clear mask */ |
705 | /* CMD Register clear mask */ |
| 715 | #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ |
706 | #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\ |
| 716 | SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ |
707 | SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\ |
| 717 | SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) |
708 | SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND)) |
| 718 | 709 | ||
| 719 | /* SDIO RESP Registers Address */ |
- | |
| 720 | #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) |
- | |
| 721 | - | ||
| 722 | /* SDIO Intialization Frequency (400KHz max) */ |
710 | /* SDIO Initialization Frequency (400KHz max) */ |
| 723 | #define SDIO_INIT_CLK_DIV ((uint8_t)0xC3) |
711 | #define SDIO_INIT_CLK_DIV ((uint8_t)0x76) /* 48MHz / (SDMMC_INIT_CLK_DIV + 2) < 400KHz */ |
| 724 | - | ||
| 725 | /* SDIO Data Transfer Frequency */ |
- | |
| 726 | #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x9) |
- | |
| 727 | 712 | ||
| - | 713 | /* SDIO Data Transfer Frequency (25MHz max) */ |
|
| - | 714 | #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4) |
|
| 728 | /** |
715 | /** |
| 729 | * @} |
716 | * @} |
| 730 | */ |
717 | */ |
| 731 | 718 | ||
| 732 | /** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration |
719 | /** @defgroup SDIO_LL_Interrupt_Clock Interrupt And Clock Configuration |
| Line 736... | Line 723... | ||
| 736 | 723 | ||
| 737 | /** |
724 | /** |
| 738 | * @brief Enable the SDIO device. |
725 | * @brief Enable the SDIO device. |
| 739 | * @param __INSTANCE__: SDIO Instance |
726 | * @param __INSTANCE__: SDIO Instance |
| 740 | * @retval None |
727 | * @retval None |
| 741 | */ |
728 | */ |
| 742 | #define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) |
729 | #define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) |
| 743 | 730 | ||
| 744 | /** |
731 | /** |
| 745 | * @brief Disable the SDIO device. |
732 | * @brief Disable the SDIO device. |
| 746 | * @param __INSTANCE__: SDIO Instance |
733 | * @param __INSTANCE__: SDIO Instance |
| Line 750... | Line 737... | ||
| 750 | 737 | ||
| 751 | /** |
738 | /** |
| 752 | * @brief Enable the SDIO DMA transfer. |
739 | * @brief Enable the SDIO DMA transfer. |
| 753 | * @param __INSTANCE__: SDIO Instance |
740 | * @param __INSTANCE__: SDIO Instance |
| 754 | * @retval None |
741 | * @retval None |
| 755 | */ |
742 | */ |
| 756 | #define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) |
743 | #define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) |
| - | 744 | ||
| 757 | /** |
745 | /** |
| 758 | * @brief Disable the SDIO DMA transfer. |
746 | * @brief Disable the SDIO DMA transfer. |
| 759 | * @param __INSTANCE__: SDIO Instance |
747 | * @param __INSTANCE__: SDIO Instance |
| 760 | * @retval None |
748 | * @retval None |
| 761 | */ |
749 | */ |
| Line 772... | Line 760... | ||
| 772 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
760 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| 773 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
761 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| 774 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
762 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| 775 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
763 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| 776 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
764 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| 777 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
765 | * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
| 778 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
766 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| 779 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
767 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| 780 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
768 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| 781 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
769 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| 782 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
770 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| Line 785... | Line 773... | ||
| 785 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
773 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| 786 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
774 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| 787 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
775 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| 788 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
776 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| 789 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
777 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| 790 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
778 | * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt |
| 791 | * @retval None |
779 | * @retval None |
| 792 | */ |
780 | */ |
| 793 | #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) |
781 | #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__)) |
| 794 | 782 | ||
| 795 | /** |
783 | /** |
| Line 803... | Line 791... | ||
| 803 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
791 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| 804 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
792 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| 805 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
793 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| 806 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
794 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| 807 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
795 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| 808 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
796 | * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
| 809 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
797 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| 810 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
798 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| 811 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
799 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| 812 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
800 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| 813 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
801 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| Line 816... | Line 804... | ||
| 816 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
804 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| 817 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
805 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| 818 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
806 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| 819 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
807 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| 820 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
808 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| 821 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
809 | * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt |
| 822 | * @retval None |
810 | * @retval None |
| 823 | */ |
811 | */ |
| 824 | #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) |
812 | #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__)) |
| 825 | 813 | ||
| 826 | /** |
814 | /** |
| Line 834... | Line 822... | ||
| 834 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
822 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
| 835 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
823 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
| 836 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
824 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
| 837 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
825 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
| 838 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
826 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
| 839 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
827 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) |
| 840 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
828 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
| 841 | * @arg SDIO_FLAG_CMDACT: Command transfer in progress |
829 | * @arg SDIO_FLAG_CMDACT: Command transfer in progress |
| 842 | * @arg SDIO_FLAG_TXACT: Data transmit in progress |
830 | * @arg SDIO_FLAG_TXACT: Data transmit in progress |
| 843 | * @arg SDIO_FLAG_RXACT: Data receive in progress |
831 | * @arg SDIO_FLAG_RXACT: Data receive in progress |
| 844 | * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
832 | * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty |
| Line 847... | Line 835... | ||
| 847 | * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full |
835 | * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full |
| 848 | * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty |
836 | * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty |
| 849 | * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty |
837 | * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty |
| 850 | * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO |
838 | * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO |
| 851 | * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO |
839 | * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO |
| 852 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
840 | * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received |
| 853 | * @retval The new state of SDIO_FLAG (SET or RESET). |
841 | * @retval The new state of SDIO_FLAG (SET or RESET). |
| 854 | */ |
842 | */ |
| 855 | #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET) |
843 | #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != 0U) |
| 856 | 844 | ||
| 857 | 845 | ||
| 858 | /** |
846 | /** |
| 859 | * @brief Clears the SDIO pending flags. |
847 | * @brief Clears the SDIO pending flags. |
| 860 | * @param __INSTANCE__ : Pointer to SDIO register base |
848 | * @param __INSTANCE__ : Pointer to SDIO register base |
| Line 866... | Line 854... | ||
| 866 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
854 | * @arg SDIO_FLAG_DTIMEOUT: Data timeout |
| 867 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
855 | * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error |
| 868 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
856 | * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error |
| 869 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
857 | * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed) |
| 870 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
858 | * @arg SDIO_FLAG_CMDSENT: Command sent (no response required) |
| 871 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero) |
859 | * @arg SDIO_FLAG_DATAEND: Data end (data counter, DATACOUNT, is zero) |
| 872 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
860 | * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed) |
| 873 | * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received |
861 | * @arg SDIO_FLAG_SDIOIT: SDIO interrupt received |
| 874 | * @retval None |
862 | * @retval None |
| 875 | */ |
863 | */ |
| 876 | #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) |
864 | #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__)) |
| 877 | 865 | ||
| 878 | /** |
866 | /** |
| Line 886... | Line 874... | ||
| 886 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
874 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| 887 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
875 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| 888 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
876 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| 889 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
877 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| 890 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
878 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| 891 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt |
879 | * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
| 892 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
880 | * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt |
| 893 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
881 | * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt |
| 894 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
882 | * @arg SDIO_IT_TXACT: Data transmit in progress interrupt |
| 895 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
883 | * @arg SDIO_IT_RXACT: Data receive in progress interrupt |
| 896 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
884 | * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt |
| Line 899... | Line 887... | ||
| 899 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
887 | * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt |
| 900 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
888 | * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt |
| 901 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
889 | * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt |
| 902 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
890 | * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt |
| 903 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
891 | * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt |
| 904 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
892 | * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt |
| 905 | * @retval The new state of SDIO_IT (SET or RESET). |
893 | * @retval The new state of SDIO_IT (SET or RESET). |
| 906 | */ |
894 | */ |
| 907 | #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) |
895 | #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) |
| 908 | 896 | ||
| 909 | /** |
897 | /** |
| Line 917... | Line 905... | ||
| 917 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
905 | * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt |
| 918 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
906 | * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt |
| 919 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
907 | * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt |
| 920 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
908 | * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt |
| 921 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
909 | * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt |
| 922 | * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt |
910 | * @arg SDIO_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt |
| 923 | * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt |
911 | * @arg SDIO_IT_SDIOIT: SDIO interrupt received interrupt |
| 924 | * @retval None |
912 | * @retval None |
| 925 | */ |
913 | */ |
| 926 | #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) |
914 | #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__)) |
| 927 | 915 | ||
| 928 | /** |
916 | /** |
| 929 | * @brief Enable Start the SD I/O Read Wait operation. |
917 | * @brief Enable Start the SD I/O Read Wait operation. |
| 930 | * @param __INSTANCE__ : Pointer to SDIO register base |
918 | * @param __INSTANCE__ : Pointer to SDIO register base |
| 931 | * @retval None |
919 | * @retval None |
| 932 | */ |
920 | */ |
| 933 | #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) |
921 | #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) |
| 934 | 922 | ||
| 935 | /** |
923 | /** |
| 936 | * @brief Disable Start the SD I/O Read Wait operations. |
924 | * @brief Disable Start the SD I/O Read Wait operations. |
| 937 | * @param __INSTANCE__ : Pointer to SDIO register base |
925 | * @param __INSTANCE__ : Pointer to SDIO register base |
| 938 | * @retval None |
926 | * @retval None |
| 939 | */ |
927 | */ |
| 940 | #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) |
928 | #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) |
| 941 | 929 | ||
| 942 | /** |
930 | /** |
| 943 | * @brief Enable Start the SD I/O Read Wait operation. |
931 | * @brief Enable Start the SD I/O Read Wait operation. |
| 944 | * @param __INSTANCE__ : Pointer to SDIO register base |
932 | * @param __INSTANCE__ : Pointer to SDIO register base |
| 945 | * @retval None |
933 | * @retval None |
| 946 | */ |
934 | */ |
| 947 | #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) |
935 | #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) |
| 948 | 936 | ||
| 949 | /** |
937 | /** |
| 950 | * @brief Disable Stop the SD I/O Read Wait operations. |
938 | * @brief Disable Stop the SD I/O Read Wait operations. |
| 951 | * @param __INSTANCE__ : Pointer to SDIO register base |
939 | * @param __INSTANCE__ : Pointer to SDIO register base |
| 952 | * @retval None |
940 | * @retval None |
| 953 | */ |
941 | */ |
| 954 | #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) |
942 | #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) |
| 955 | 943 | ||
| 956 | /** |
944 | /** |
| 957 | * @brief Enable the SD I/O Mode Operation. |
945 | * @brief Enable the SD I/O Mode Operation. |
| 958 | * @param __INSTANCE__ : Pointer to SDIO register base |
946 | * @param __INSTANCE__ : Pointer to SDIO register base |
| 959 | * @retval None |
947 | * @retval None |
| 960 | */ |
948 | */ |
| 961 | #define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) |
949 | #define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) |
| 962 | 950 | ||
| 963 | /** |
951 | /** |
| 964 | * @brief Disable the SD I/O Mode Operation. |
952 | * @brief Disable the SD I/O Mode Operation. |
| 965 | * @param __INSTANCE__ : Pointer to SDIO register base |
953 | * @param __INSTANCE__ : Pointer to SDIO register base |
| 966 | * @retval None |
954 | * @retval None |
| 967 | */ |
955 | */ |
| 968 | #define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) |
956 | #define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) |
| 969 | 957 | ||
| 970 | /** |
958 | /** |
| 971 | * @brief Enable the SD I/O Suspend command sending. |
959 | * @brief Enable the SD I/O Suspend command sending. |
| 972 | * @param __INSTANCE__ : Pointer to SDIO register base |
960 | * @param __INSTANCE__ : Pointer to SDIO register base |
| 973 | * @retval None |
961 | * @retval None |
| 974 | */ |
962 | */ |
| 975 | #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) |
963 | #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) |
| 976 | 964 | ||
| 977 | /** |
965 | /** |
| 978 | * @brief Disable the SD I/O Suspend command sending. |
966 | * @brief Disable the SD I/O Suspend command sending. |
| 979 | * @param __INSTANCE__ : Pointer to SDIO register base |
967 | * @param __INSTANCE__ : Pointer to SDIO register base |
| 980 | * @retval None |
968 | * @retval None |
| 981 | */ |
969 | */ |
| 982 | #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) |
970 | #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE) |
| - | 971 | ||
| 983 | /** |
972 | /** |
| 984 | * @brief Enable the command completion signal. |
973 | * @brief Enable the command completion signal. |
| 985 | * @retval None |
974 | * @retval None |
| 986 | */ |
975 | */ |
| 987 | #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) |
976 | #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE) |
| Line 1013... | Line 1002... | ||
| 1013 | /** |
1002 | /** |
| 1014 | * @brief Disable send CE-ATA command (CMD61). |
1003 | * @brief Disable send CE-ATA command (CMD61). |
| 1015 | * @retval None |
1004 | * @retval None |
| 1016 | */ |
1005 | */ |
| 1017 | #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) |
1006 | #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE) |
| 1018 | 1007 | ||
| 1019 | /** |
1008 | /** |
| 1020 | * @} |
1009 | * @} |
| 1021 | */ |
1010 | */ |
| 1022 | 1011 | ||
| 1023 | /** |
1012 | /** |
| 1024 | * @} |
1013 | * @} |
| 1025 | */ |
1014 | */ |
| 1026 | 1015 | ||
| 1027 | /* Exported functions --------------------------------------------------------*/ |
1016 | /* Exported functions --------------------------------------------------------*/ |
| 1028 | /** @addtogroup SDMMC_LL_Exported_Functions |
1017 | /** @addtogroup SDMMC_LL_Exported_Functions |
| 1029 | * @{ |
1018 | * @{ |
| 1030 | */ |
1019 | */ |
| Line 1035... | Line 1024... | ||
| 1035 | */ |
1024 | */ |
| 1036 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); |
1025 | HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init); |
| 1037 | /** |
1026 | /** |
| 1038 | * @} |
1027 | * @} |
| 1039 | */ |
1028 | */ |
| 1040 | 1029 | ||
| 1041 | /* I/O operation functions *****************************************************/ |
1030 | /* I/O operation functions *****************************************************/ |
| 1042 | /** @addtogroup HAL_SDMMC_LL_Group2 |
1031 | /** @addtogroup HAL_SDMMC_LL_Group2 |
| 1043 | * @{ |
1032 | * @{ |
| 1044 | */ |
1033 | */ |
| 1045 | /* Blocking mode: Polling */ |
- | |
| 1046 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); |
1034 | uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx); |
| 1047 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); |
1035 | HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData); |
| 1048 | /** |
1036 | /** |
| 1049 | * @} |
1037 | * @} |
| 1050 | */ |
1038 | */ |
| Line 1074... | Line 1062... | ||
| 1074 | uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize); |
1062 | uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize); |
| 1075 | uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); |
1063 | uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); |
| 1076 | uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); |
1064 | uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd); |
| 1077 | uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); |
1065 | uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); |
| 1078 | uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); |
1066 | uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd); |
| - | 1067 | uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); |
|
| 1079 | uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); |
1068 | uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); |
| - | 1069 | uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); |
|
| 1080 | uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); |
1070 | uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); |
| 1081 | uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx); |
1071 | uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx); |
| 1082 | uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx); |
1072 | uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx); |
| 1083 | uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr); |
1073 | uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr); |
| 1084 | uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx); |
1074 | uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx); |
| 1085 | uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx); |
1075 | uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx); |
| 1086 | uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); |
1076 | uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); |
| 1087 | uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType); |
1077 | uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t Argument); |
| 1088 | uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); |
1078 | uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth); |
| 1089 | uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); |
1079 | uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx); |
| 1090 | uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); |
1080 | uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx); |
| 1091 | uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); |
1081 | uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument); |
| 1092 | uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); |
1082 | uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA); |
| 1093 | uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); |
1083 | uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument); |
| 1094 | uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); |
1084 | uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx); |
| 1095 | - | ||
| 1096 | uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); |
1085 | uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument); |
| 1097 | uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); |
1086 | uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument); |
| 1098 | uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd); |
- | |
| 1099 | uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd); |
- | |
| 1100 | 1087 | ||
| 1101 | /** |
1088 | /** |
| 1102 | * @} |
1089 | * @} |
| 1103 | */ |
1090 | */ |
| 1104 | 1091 | ||
| Line 1111... | Line 1098... | ||
| 1111 | */ |
1098 | */ |
| 1112 | 1099 | ||
| 1113 | /** |
1100 | /** |
| 1114 | * @} |
1101 | * @} |
| 1115 | */ |
1102 | */ |
| - | 1103 | ||
| - | 1104 | #endif /* SDIO */ |
|
| 1116 | 1105 | ||
| 1117 | #ifdef __cplusplus |
1106 | #ifdef __cplusplus |
| 1118 | } |
1107 | } |
| 1119 | #endif |
1108 | #endif |
| 1120 | 1109 | ||
| 1121 | #endif /* STM32F103xE || STM32F103xG */ |
- | |
| 1122 | - | ||
| 1123 | #endif /* __stm32f1xx_LL_SD_H */ |
1110 | #endif /* STM32F1xx_LL_SDMMC_H */ |
| 1124 | 1111 | ||
| 1125 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
1112 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |