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| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of RCC LL module. |
5 | * @brief Header file of RCC LL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
| - | 10 | * All rights reserved.</center></h2> |
|
| 10 | * |
11 | * |
| 11 | * Redistribution and use in source and binary forms, with or without modification, |
12 | * This software component is licensed by ST under BSD 3-Clause license, |
| 12 | * are permitted provided that the following conditions are met: |
13 | * the "License"; You may not use this file except in compliance with the |
| 13 | * 1. Redistributions of source code must retain the above copyright notice, |
- | |
| 14 | * this list of conditions and the following disclaimer. |
- | |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
- | |
| 16 | * this list of conditions and the following disclaimer in the documentation |
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| 17 | * and/or other materials provided with the distribution. |
14 | * License. You may obtain a copy of the License at: |
| 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
- | |
| 19 | * may be used to endorse or promote products derived from this software |
15 | * opensource.org/licenses/BSD-3-Clause |
| 20 | * without specific prior written permission. |
- | |
| 21 | * |
- | |
| 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
- | |
| 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
- | |
| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
- | |
| 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
- | |
| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
- | |
| 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
- | |
| 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
- | |
| 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
- | |
| 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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| 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
- | |
| 32 | * |
16 | * |
| 33 | ****************************************************************************** |
17 | ****************************************************************************** |
| 34 | */ |
18 | */ |
| 35 | 19 | ||
| 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Line 118... | Line 102... | ||
| 118 | #if !defined (LSE_VALUE) |
102 | #if !defined (LSE_VALUE) |
| 119 | #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ |
103 | #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ |
| 120 | #endif /* LSE_VALUE */ |
104 | #endif /* LSE_VALUE */ |
| 121 | 105 | ||
| 122 | #if !defined (LSI_VALUE) |
106 | #if !defined (LSI_VALUE) |
| 123 | #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ |
107 | #define LSI_VALUE 40000U /*!< Value of the LSI oscillator in Hz */ |
| 124 | #endif /* LSI_VALUE */ |
108 | #endif /* LSI_VALUE */ |
| 125 | /** |
109 | /** |
| 126 | * @} |
110 | * @} |
| 127 | */ |
111 | */ |
| 128 | 112 | ||
| Line 266... | Line 250... | ||
| 266 | */ |
250 | */ |
| 267 | 251 | ||
| 268 | /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection |
252 | /** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection |
| 269 | * @{ |
253 | * @{ |
| 270 | */ |
254 | */ |
| 271 | #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCOSEL_NOCLOCK /*!< MCO output disabled, no clock on MCO */ |
255 | #define LL_RCC_MCO1SOURCE_NOCLOCK RCC_CFGR_MCO_NOCLOCK /*!< MCO output disabled, no clock on MCO */ |
| 272 | #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_SYSCLK /*!< SYSCLK selection as MCO source */ |
256 | #define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK /*!< SYSCLK selection as MCO source */ |
| 273 | #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCOSEL_HSI /*!< HSI selection as MCO source */ |
257 | #define LL_RCC_MCO1SOURCE_HSI RCC_CFGR_MCO_HSI /*!< HSI selection as MCO source */ |
| 274 | #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_HSE /*!< HSE selection as MCO source */ |
258 | #define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCO_HSE /*!< HSE selection as MCO source */ |
| 275 | #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCOSEL_PLL_DIV2 /*!< PLL clock divided by 2*/ |
259 | #define LL_RCC_MCO1SOURCE_PLLCLK_DIV_2 RCC_CFGR_MCO_PLLCLK_DIV2 /*!< PLL clock divided by 2*/ |
| 276 | #if defined(RCC_CFGR_MCOSEL_PLL2CLK) |
260 | #if defined(RCC_CFGR_MCO_PLL2CLK) |
| 277 | #define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCOSEL_PLL2 /*!< PLL2 clock selected as MCO source*/ |
261 | #define LL_RCC_MCO1SOURCE_PLL2CLK RCC_CFGR_MCO_PLL2CLK /*!< PLL2 clock selected as MCO source*/ |
| 278 | #endif /* RCC_CFGR_MCOSEL_PLL2CLK */ |
262 | #endif /* RCC_CFGR_MCO_PLL2CLK */ |
| 279 | #if defined(RCC_CFGR_MCOSEL_PLL3CLK_DIV2) |
263 | #if defined(RCC_CFGR_MCO_PLL3CLK_DIV2) |
| 280 | #define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCOSEL_PLL3_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/ |
264 | #define LL_RCC_MCO1SOURCE_PLLI2SCLK_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 /*!< PLLI2S clock divided by 2 selected as MCO source*/ |
| 281 | #endif /* RCC_CFGR_MCOSEL_PLL3CLK_DIV2 */ |
265 | #endif /* RCC_CFGR_MCO_PLL3CLK_DIV2 */ |
| 282 | #if defined(RCC_CFGR_MCOSEL_EXT_HSE) |
266 | #if defined(RCC_CFGR_MCO_EXT_HSE) |
| 283 | #define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCOSEL_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ |
267 | #define LL_RCC_MCO1SOURCE_EXT_HSE RCC_CFGR_MCO_EXT_HSE /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ |
| 284 | #endif /* RCC_CFGR_MCOSEL_EXT_HSE */ |
268 | #endif /* RCC_CFGR_MCO_EXT_HSE */ |
| 285 | #if defined(RCC_CFGR_MCOSEL_PLL3CLK) |
269 | #if defined(RCC_CFGR_MCO_PLL3CLK) |
| 286 | #define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCOSEL_PLL3CLK /*!< PLLI2S clock selected as MCO source */ |
270 | #define LL_RCC_MCO1SOURCE_PLLI2SCLK RCC_CFGR_MCO_PLL3CLK /*!< PLLI2S clock selected as MCO source */ |
| 287 | #endif /* RCC_CFGR_MCOSEL_PLL3CLK */ |
271 | #endif /* RCC_CFGR_MCO_PLL3CLK */ |
| 288 | /** |
272 | /** |
| 289 | * @} |
273 | * @} |
| 290 | */ |
274 | */ |
| 291 | 275 | ||
| 292 | #if defined(USE_FULL_LL_DRIVER) |
276 | #if defined(USE_FULL_LL_DRIVER) |
| Line 318... | Line 302... | ||
| 318 | * @{ |
302 | * @{ |
| 319 | */ |
303 | */ |
| 320 | #if defined(RCC_CFGR_USBPRE) |
304 | #if defined(RCC_CFGR_USBPRE) |
| 321 | #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */ |
305 | #define LL_RCC_USB_CLKSOURCE_PLL RCC_CFGR_USBPRE /*!< PLL clock is not divided */ |
| 322 | #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */ |
306 | #define LL_RCC_USB_CLKSOURCE_PLL_DIV_1_5 0x00000000U /*!< PLL clock is divided by 1.5 */ |
| 323 | #endif /*RCC_CFGR_USBPRE*/ |
307 | #endif /*RCC_CFGR_USBPRE*/ |
| 324 | #if defined(RCC_CFGR_OTGFSPRE) |
308 | #if defined(RCC_CFGR_OTGFSPRE) |
| 325 | #define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */ |
309 | #define LL_RCC_USB_CLKSOURCE_PLL_DIV_2 RCC_CFGR_OTGFSPRE /*!< PLL clock is divided by 2 */ |
| 326 | #define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */ |
310 | #define LL_RCC_USB_CLKSOURCE_PLL_DIV_3 0x00000000U /*!< PLL clock is divided by 3 */ |
| 327 | #endif /*RCC_CFGR_OTGFSPRE*/ |
311 | #endif /*RCC_CFGR_OTGFSPRE*/ |
| 328 | /** |
312 | /** |
| 329 | * @} |
313 | * @} |
| Line 1534... | Line 1518... | ||
| 1534 | * (*) value not defined in all devices |
1518 | * (*) value not defined in all devices |
| 1535 | */ |
1519 | */ |
| 1536 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) |
1520 | __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) |
| 1537 | { |
1521 | { |
| 1538 | #if defined(RCC_CFGR2_PREDIV1SRC) |
1522 | #if defined(RCC_CFGR2_PREDIV1SRC) |
| 1539 | register uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC); |
1523 | uint32_t pllsrc = READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC); |
| 1540 | register uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); |
1524 | uint32_t predivsrc = (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PREDIV1SRC) << 4U); |
| 1541 | return (uint32_t)(pllsrc | predivsrc); |
1525 | return (uint32_t)(pllsrc | predivsrc); |
| 1542 | #else |
1526 | #else |
| 1543 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); |
1527 | return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)); |
| 1544 | #endif /*RCC_CFGR2_PREDIV1SRC*/ |
1528 | #endif /*RCC_CFGR2_PREDIV1SRC*/ |
| 1545 | } |
1529 | } |