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| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of IWDG LL module. |
5 | * @brief Header file of IWDG LL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
| - | 10 | * All rights reserved.</center></h2> |
|
| 10 | * |
11 | * |
| 11 | * Redistribution and use in source and binary forms, with or without modification, |
12 | * This software component is licensed by ST under BSD 3-Clause license, |
| 12 | * are permitted provided that the following conditions are met: |
13 | * the "License"; You may not use this file except in compliance with the |
| 13 | * 1. Redistributions of source code must retain the above copyright notice, |
- | |
| 14 | * this list of conditions and the following disclaimer. |
- | |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
- | |
| 16 | * this list of conditions and the following disclaimer in the documentation |
- | |
| 17 | * and/or other materials provided with the distribution. |
14 | * License. You may obtain a copy of the License at: |
| 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
- | |
| 19 | * may be used to endorse or promote products derived from this software |
15 | * opensource.org/licenses/BSD-3-Clause |
| 20 | * without specific prior written permission. |
- | |
| 21 | * |
- | |
| 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
- | |
| 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
- | |
| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
- | |
| 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
- | |
| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
- | |
| 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
- | |
| 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
- | |
| 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
- | |
| 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
- | |
| 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
- | |
| 32 | * |
16 | * |
| 33 | ****************************************************************************** |
17 | ****************************************************************************** |
| 34 | */ |
18 | */ |
| 35 | 19 | ||
| 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| 37 | #ifndef __STM32F1xx_LL_IWDG_H |
21 | #ifndef STM32F1xx_LL_IWDG_H |
| 38 | #define __STM32F1xx_LL_IWDG_H |
22 | #define STM32F1xx_LL_IWDG_H |
| 39 | 23 | ||
| 40 | #ifdef __cplusplus |
24 | #ifdef __cplusplus |
| 41 | extern "C" { |
25 | extern "C" { |
| 42 | #endif |
26 | #endif |
| 43 | 27 | ||
| Line 59... | Line 43... | ||
| 59 | 43 | ||
| 60 | /* Private constants ---------------------------------------------------------*/ |
44 | /* Private constants ---------------------------------------------------------*/ |
| 61 | /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants |
45 | /** @defgroup IWDG_LL_Private_Constants IWDG Private Constants |
| 62 | * @{ |
46 | * @{ |
| 63 | */ |
47 | */ |
| 64 | - | ||
| 65 | #define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ |
48 | #define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ |
| 66 | #define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ |
49 | #define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ |
| 67 | #define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ |
50 | #define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ |
| 68 | #define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ |
51 | #define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ |
| 69 | - | ||
| 70 | /** |
52 | /** |
| 71 | * @} |
53 | * @} |
| 72 | */ |
54 | */ |
| 73 | 55 | ||
| 74 | /* Private macros ------------------------------------------------------------*/ |
56 | /* Private macros ------------------------------------------------------------*/ |
| Line 83... | Line 65... | ||
| 83 | * @brief Flags defines which can be used with LL_IWDG_ReadReg function |
65 | * @brief Flags defines which can be used with LL_IWDG_ReadReg function |
| 84 | * @{ |
66 | * @{ |
| 85 | */ |
67 | */ |
| 86 | #define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ |
68 | #define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ |
| 87 | #define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ |
69 | #define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ |
| 88 | - | ||
| 89 | /** |
70 | /** |
| 90 | * @} |
71 | * @} |
| 91 | */ |
72 | */ |
| 92 | 73 | ||
| 93 | /** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider |
74 | /** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider |
| Line 157... | Line 138... | ||
| 157 | * @param IWDGx IWDG Instance |
138 | * @param IWDGx IWDG Instance |
| 158 | * @retval None |
139 | * @retval None |
| 159 | */ |
140 | */ |
| 160 | __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) |
141 | __STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) |
| 161 | { |
142 | { |
| 162 | WRITE_REG(IWDG->KR, LL_IWDG_KEY_ENABLE); |
143 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); |
| 163 | } |
144 | } |
| 164 | 145 | ||
| 165 | /** |
146 | /** |
| 166 | * @brief Reloads IWDG counter with value defined in the reload register |
147 | * @brief Reloads IWDG counter with value defined in the reload register |
| 167 | * @rmtoll KR KEY LL_IWDG_ReloadCounter |
148 | * @rmtoll KR KEY LL_IWDG_ReloadCounter |
| 168 | * @param IWDGx IWDG Instance |
149 | * @param IWDGx IWDG Instance |
| 169 | * @retval None |
150 | * @retval None |
| 170 | */ |
151 | */ |
| 171 | __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) |
152 | __STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) |
| 172 | { |
153 | { |
| 173 | WRITE_REG(IWDG->KR, LL_IWDG_KEY_RELOAD); |
154 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); |
| 174 | } |
155 | } |
| 175 | 156 | ||
| 176 | /** |
157 | /** |
| 177 | * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
158 | * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
| 178 | * @rmtoll KR KEY LL_IWDG_EnableWriteAccess |
159 | * @rmtoll KR KEY LL_IWDG_EnableWriteAccess |
| 179 | * @param IWDGx IWDG Instance |
160 | * @param IWDGx IWDG Instance |
| 180 | * @retval None |
161 | * @retval None |
| 181 | */ |
162 | */ |
| 182 | __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) |
163 | __STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) |
| 183 | { |
164 | { |
| 184 | WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); |
165 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); |
| 185 | } |
166 | } |
| 186 | 167 | ||
| 187 | /** |
168 | /** |
| 188 | * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
169 | * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers |
| 189 | * @rmtoll KR KEY LL_IWDG_DisableWriteAccess |
170 | * @rmtoll KR KEY LL_IWDG_DisableWriteAccess |
| 190 | * @param IWDGx IWDG Instance |
171 | * @param IWDGx IWDG Instance |
| 191 | * @retval None |
172 | * @retval None |
| 192 | */ |
173 | */ |
| 193 | __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) |
174 | __STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) |
| 194 | { |
175 | { |
| 195 | WRITE_REG(IWDG->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); |
176 | WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); |
| 196 | } |
177 | } |
| 197 | 178 | ||
| 198 | /** |
179 | /** |
| 199 | * @brief Select the prescaler of the IWDG |
180 | * @brief Select the prescaler of the IWDG |
| 200 | * @rmtoll PR PR LL_IWDG_SetPrescaler |
181 | * @rmtoll PR PR LL_IWDG_SetPrescaler |
| Line 227... | Line 208... | ||
| 227 | * @arg @ref LL_IWDG_PRESCALER_128 |
208 | * @arg @ref LL_IWDG_PRESCALER_128 |
| 228 | * @arg @ref LL_IWDG_PRESCALER_256 |
209 | * @arg @ref LL_IWDG_PRESCALER_256 |
| 229 | */ |
210 | */ |
| 230 | __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) |
211 | __STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) |
| 231 | { |
212 | { |
| 232 | return (uint32_t)(READ_REG(IWDGx->PR)); |
213 | return (READ_REG(IWDGx->PR)); |
| 233 | } |
214 | } |
| 234 | 215 | ||
| 235 | /** |
216 | /** |
| 236 | * @brief Specify the IWDG down-counter reload value |
217 | * @brief Specify the IWDG down-counter reload value |
| 237 | * @rmtoll RLR RL LL_IWDG_SetReloadCounter |
218 | * @rmtoll RLR RL LL_IWDG_SetReloadCounter |
| Line 250... | Line 231... | ||
| 250 | * @param IWDGx IWDG Instance |
231 | * @param IWDGx IWDG Instance |
| 251 | * @retval Value between Min_Data=0 and Max_Data=0x0FFF |
232 | * @retval Value between Min_Data=0 and Max_Data=0x0FFF |
| 252 | */ |
233 | */ |
| 253 | __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) |
234 | __STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) |
| 254 | { |
235 | { |
| 255 | return (uint32_t)(READ_REG(IWDGx->RLR)); |
236 | return (READ_REG(IWDGx->RLR)); |
| 256 | } |
237 | } |
| 257 | 238 | ||
| 258 | 239 | ||
| 259 | /** |
240 | /** |
| 260 | * @} |
241 | * @} |
| Line 270... | Line 251... | ||
| 270 | * @param IWDGx IWDG Instance |
251 | * @param IWDGx IWDG Instance |
| 271 | * @retval State of bit (1 or 0). |
252 | * @retval State of bit (1 or 0). |
| 272 | */ |
253 | */ |
| 273 | __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) |
254 | __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) |
| 274 | { |
255 | { |
| 275 | return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)); |
256 | return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); |
| 276 | } |
257 | } |
| 277 | 258 | ||
| 278 | /** |
259 | /** |
| 279 | * @brief Check if flag Reload Value Update is set or not |
260 | * @brief Check if flag Reload Value Update is set or not |
| 280 | * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU |
261 | * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU |
| 281 | * @param IWDGx IWDG Instance |
262 | * @param IWDGx IWDG Instance |
| 282 | * @retval State of bit (1 or 0). |
263 | * @retval State of bit (1 or 0). |
| 283 | */ |
264 | */ |
| 284 | __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) |
265 | __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) |
| 285 | { |
266 | { |
| 286 | return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)); |
267 | return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); |
| 287 | } |
268 | } |
| 288 | 269 | ||
| 289 | - | ||
| 290 | /** |
270 | /** |
| 291 | * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not |
271 | * @brief Check if flags Prescaler & Reload Value Update are reset or not |
| 292 | * @rmtoll SR PVU LL_IWDG_IsReady\n |
272 | * @rmtoll SR PVU LL_IWDG_IsReady\n |
| 293 | * SR RVU LL_IWDG_IsReady |
273 | * SR RVU LL_IWDG_IsReady |
| 294 | * @param IWDGx IWDG Instance |
274 | * @param IWDGx IWDG Instance |
| 295 | * @retval State of bits (1 or 0). |
275 | * @retval State of bits (1 or 0). |
| 296 | */ |
276 | */ |
| 297 | __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) |
277 | __STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) |
| 298 | { |
278 | { |
| 299 | return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U); |
279 | return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U) ? 1UL : 0UL); |
| 300 | } |
280 | } |
| 301 | 281 | ||
| 302 | /** |
282 | /** |
| 303 | * @} |
283 | * @} |
| 304 | */ |
284 | */ |
| Line 310... | Line 290... | ||
| 310 | 290 | ||
| 311 | /** |
291 | /** |
| 312 | * @} |
292 | * @} |
| 313 | */ |
293 | */ |
| 314 | 294 | ||
| 315 | #endif /* IWDG) */ |
295 | #endif /* IWDG */ |
| 316 | 296 | ||
| 317 | /** |
297 | /** |
| 318 | * @} |
298 | * @} |
| 319 | */ |
299 | */ |
| 320 | 300 | ||
| 321 | #ifdef __cplusplus |
301 | #ifdef __cplusplus |
| 322 | } |
302 | } |
| 323 | #endif |
303 | #endif |
| 324 | 304 | ||
| 325 | #endif /* __STM32F1xx_LL_IWDG_H */ |
305 | #endif /* STM32F1xx_LL_IWDG_H */ |
| 326 | 306 | ||
| 327 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
307 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |