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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_ll_gpio.h |
3 | * @file stm32f1xx_ll_gpio.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of GPIO LL module. |
5 | * @brief Header file of GPIO LL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef STM32F1xx_LL_GPIO_H |
| 21 | #ifndef STM32F1xx_LL_GPIO_H |
21 | #define STM32F1xx_LL_GPIO_H |
| 22 | #define STM32F1xx_LL_GPIO_H |
22 | |
| 23 | 23 | #ifdef __cplusplus |
|
| 24 | #ifdef __cplusplus |
24 | extern "C" { |
| 25 | extern "C" { |
25 | #endif |
| 26 | #endif |
26 | |
| 27 | 27 | /* Includes ------------------------------------------------------------------*/ |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | #include "stm32f1xx.h" |
| 29 | #include "stm32f1xx.h" |
29 | |
| 30 | 30 | /** @addtogroup STM32F1xx_LL_Driver |
|
| 31 | /** @addtogroup STM32F1xx_LL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) |
|
| 35 | #if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) |
35 | |
| 36 | 36 | /** @defgroup GPIO_LL GPIO |
|
| 37 | /** @defgroup GPIO_LL GPIO |
37 | * @{ |
| 38 | * @{ |
38 | */ |
| 39 | */ |
39 | |
| 40 | 40 | /* Private types -------------------------------------------------------------*/ |
|
| 41 | /* Private types -------------------------------------------------------------*/ |
41 | /* Private variables ---------------------------------------------------------*/ |
| 42 | /* Private variables ---------------------------------------------------------*/ |
42 | /* Private constants ---------------------------------------------------------*/ |
| 43 | /* Private constants ---------------------------------------------------------*/ |
43 | |
| 44 | 44 | /** @defgroup GPIO_LL_Private_Constants GPIO Private Constants |
|
| 45 | /** @defgroup GPIO_LL_Private_Constants GPIO Private Constants |
45 | * @{ |
| 46 | * @{ |
46 | */ |
| 47 | */ |
47 | /* Defines used for Pin Mask Initialization */ |
| 48 | /* Defines used for Pin Mask Initialization */ |
48 | #define GPIO_PIN_MASK_POS 8U |
| 49 | #define GPIO_PIN_MASK_POS 8U |
49 | #define GPIO_PIN_NB 16U |
| 50 | #define GPIO_PIN_NB 16U |
50 | /** |
| 51 | /** |
51 | * @} |
| 52 | * @} |
52 | */ |
| 53 | */ |
53 | |
| 54 | 54 | /* Private macros ------------------------------------------------------------*/ |
|
| 55 | /* Private macros ------------------------------------------------------------*/ |
55 | #if defined(USE_FULL_LL_DRIVER) |
| 56 | #if defined(USE_FULL_LL_DRIVER) |
56 | /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros |
| 57 | /** @defgroup GPIO_LL_Private_Macros GPIO Private Macros |
57 | * @{ |
| 58 | * @{ |
58 | */ |
| 59 | */ |
59 | |
| 60 | 60 | /** |
|
| 61 | /** |
61 | * @} |
| 62 | * @} |
62 | */ |
| 63 | */ |
63 | #endif /*USE_FULL_LL_DRIVER*/ |
| 64 | #endif /*USE_FULL_LL_DRIVER*/ |
64 | |
| 65 | 65 | /* Exported types ------------------------------------------------------------*/ |
|
| 66 | /* Exported types ------------------------------------------------------------*/ |
66 | #if defined(USE_FULL_LL_DRIVER) |
| 67 | #if defined(USE_FULL_LL_DRIVER) |
67 | /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures |
| 68 | /** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures |
68 | * @{ |
| 69 | * @{ |
69 | */ |
| 70 | */ |
70 | |
| 71 | 71 | /** |
|
| 72 | /** |
72 | * @brief LL GPIO Init Structure definition |
| 73 | * @brief LL GPIO Init Structure definition |
73 | */ |
| 74 | */ |
74 | typedef struct |
| 75 | typedef struct |
75 | { |
| 76 | { |
76 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured. |
| 77 | uint32_t Pin; /*!< Specifies the GPIO pins to be configured. |
77 | This parameter can be any value of @ref GPIO_LL_EC_PIN */ |
| 78 | This parameter can be any value of @ref GPIO_LL_EC_PIN */ |
78 | |
| 79 | 79 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins. |
|
| 80 | uint32_t Mode; /*!< Specifies the operating mode for the selected pins. |
80 | This parameter can be a value of @ref GPIO_LL_EC_MODE. |
| 81 | This parameter can be a value of @ref GPIO_LL_EC_MODE. |
81 | |
| 82 | 82 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ |
|
| 83 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ |
83 | |
| 84 | 84 | uint32_t Speed; /*!< Specifies the speed for the selected pins. |
|
| 85 | uint32_t Speed; /*!< Specifies the speed for the selected pins. |
85 | This parameter can be a value of @ref GPIO_LL_EC_SPEED. |
| 86 | This parameter can be a value of @ref GPIO_LL_EC_SPEED. |
86 | |
| 87 | 87 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ |
|
| 88 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ |
88 | |
| 89 | 89 | uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. |
|
| 90 | uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. |
90 | This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. |
| 91 | This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. |
91 | |
| 92 | 92 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ |
|
| 93 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ |
93 | |
| 94 | 94 | uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. |
|
| 95 | uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. |
95 | This parameter can be a value of @ref GPIO_LL_EC_PULL. |
| 96 | This parameter can be a value of @ref GPIO_LL_EC_PULL. |
96 | |
| 97 | 97 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ |
|
| 98 | GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ |
98 | } LL_GPIO_InitTypeDef; |
| 99 | } LL_GPIO_InitTypeDef; |
99 | |
| 100 | 100 | /** |
|
| 101 | /** |
101 | * @} |
| 102 | * @} |
102 | */ |
| 103 | */ |
103 | #endif /* USE_FULL_LL_DRIVER */ |
| 104 | #endif /* USE_FULL_LL_DRIVER */ |
104 | |
| 105 | 105 | /* Exported constants --------------------------------------------------------*/ |
|
| 106 | /* Exported constants --------------------------------------------------------*/ |
106 | /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants |
| 107 | /** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants |
107 | * @{ |
| 108 | * @{ |
108 | */ |
| 109 | */ |
109 | |
| 110 | 110 | /** @defgroup GPIO_LL_EC_PIN PIN |
|
| 111 | /** @defgroup GPIO_LL_EC_PIN PIN |
111 | * @{ |
| 112 | * @{ |
112 | */ |
| 113 | */ |
113 | #define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) | 0x00000001U) /*!< Select pin 0 */ |
| 114 | #define LL_GPIO_PIN_0 ((GPIO_BSRR_BS0 << GPIO_PIN_MASK_POS) | 0x00000001U) /*!< Select pin 0 */ |
114 | #define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) | 0x00000002U) /*!< Select pin 1 */ |
| 115 | #define LL_GPIO_PIN_1 ((GPIO_BSRR_BS1 << GPIO_PIN_MASK_POS) | 0x00000002U) /*!< Select pin 1 */ |
115 | #define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) | 0x00000004U) /*!< Select pin 2 */ |
| 116 | #define LL_GPIO_PIN_2 ((GPIO_BSRR_BS2 << GPIO_PIN_MASK_POS) | 0x00000004U) /*!< Select pin 2 */ |
116 | #define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) | 0x00000008U) /*!< Select pin 3 */ |
| 117 | #define LL_GPIO_PIN_3 ((GPIO_BSRR_BS3 << GPIO_PIN_MASK_POS) | 0x00000008U) /*!< Select pin 3 */ |
117 | #define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) | 0x00000010U) /*!< Select pin 4 */ |
| 118 | #define LL_GPIO_PIN_4 ((GPIO_BSRR_BS4 << GPIO_PIN_MASK_POS) | 0x00000010U) /*!< Select pin 4 */ |
118 | #define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) | 0x00000020U) /*!< Select pin 5 */ |
| 119 | #define LL_GPIO_PIN_5 ((GPIO_BSRR_BS5 << GPIO_PIN_MASK_POS) | 0x00000020U) /*!< Select pin 5 */ |
119 | #define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) | 0x00000040U) /*!< Select pin 6 */ |
| 120 | #define LL_GPIO_PIN_6 ((GPIO_BSRR_BS6 << GPIO_PIN_MASK_POS) | 0x00000040U) /*!< Select pin 6 */ |
120 | #define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) | 0x00000080U) /*!< Select pin 7 */ |
| 121 | #define LL_GPIO_PIN_7 ((GPIO_BSRR_BS7 << GPIO_PIN_MASK_POS) | 0x00000080U) /*!< Select pin 7 */ |
121 | #define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) | 0x04000001U) /*!< Select pin 8 */ |
| 122 | #define LL_GPIO_PIN_8 ((GPIO_BSRR_BS8 << GPIO_PIN_MASK_POS) | 0x04000001U) /*!< Select pin 8 */ |
122 | #define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) | 0x04000002U) /*!< Select pin 9 */ |
| 123 | #define LL_GPIO_PIN_9 ((GPIO_BSRR_BS9 << GPIO_PIN_MASK_POS) | 0x04000002U) /*!< Select pin 9 */ |
123 | #define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) | 0x04000004U) /*!< Select pin 10 */ |
| 124 | #define LL_GPIO_PIN_10 ((GPIO_BSRR_BS10 << GPIO_PIN_MASK_POS) | 0x04000004U) /*!< Select pin 10 */ |
124 | #define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) | 0x04000008U) /*!< Select pin 11 */ |
| 125 | #define LL_GPIO_PIN_11 ((GPIO_BSRR_BS11 << GPIO_PIN_MASK_POS) | 0x04000008U) /*!< Select pin 11 */ |
125 | #define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) | 0x04000010U) /*!< Select pin 12 */ |
| 126 | #define LL_GPIO_PIN_12 ((GPIO_BSRR_BS12 << GPIO_PIN_MASK_POS) | 0x04000010U) /*!< Select pin 12 */ |
126 | #define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) | 0x04000020U) /*!< Select pin 13 */ |
| 127 | #define LL_GPIO_PIN_13 ((GPIO_BSRR_BS13 << GPIO_PIN_MASK_POS) | 0x04000020U) /*!< Select pin 13 */ |
127 | #define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) | 0x04000040U) /*!< Select pin 14 */ |
| 128 | #define LL_GPIO_PIN_14 ((GPIO_BSRR_BS14 << GPIO_PIN_MASK_POS) | 0x04000040U) /*!< Select pin 14 */ |
128 | #define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) | 0x04000080U) /*!< Select pin 15 */ |
| 129 | #define LL_GPIO_PIN_15 ((GPIO_BSRR_BS15 << GPIO_PIN_MASK_POS) | 0x04000080U) /*!< Select pin 15 */ |
129 | #define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \ |
| 130 | #define LL_GPIO_PIN_ALL (LL_GPIO_PIN_0 | LL_GPIO_PIN_1 | LL_GPIO_PIN_2 | \ |
130 | LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \ |
| 131 | LL_GPIO_PIN_3 | LL_GPIO_PIN_4 | LL_GPIO_PIN_5 | \ |
131 | LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \ |
| 132 | LL_GPIO_PIN_6 | LL_GPIO_PIN_7 | LL_GPIO_PIN_8 | \ |
132 | LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \ |
| 133 | LL_GPIO_PIN_9 | LL_GPIO_PIN_10 | LL_GPIO_PIN_11 | \ |
133 | LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \ |
| 134 | LL_GPIO_PIN_12 | LL_GPIO_PIN_13 | LL_GPIO_PIN_14 | \ |
134 | LL_GPIO_PIN_15) /*!< Select all pins */ |
| 135 | LL_GPIO_PIN_15) /*!< Select all pins */ |
135 | /** |
| 136 | /** |
136 | * @} |
| 137 | * @} |
137 | */ |
| 138 | */ |
138 | |
| 139 | 139 | /** @defgroup GPIO_LL_EC_MODE Mode |
|
| 140 | /** @defgroup GPIO_LL_EC_MODE Mode |
140 | * @{ |
| 141 | * @{ |
141 | */ |
| 142 | */ |
142 | #define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */ |
| 143 | #define LL_GPIO_MODE_ANALOG 0x00000000U /*!< Select analog mode */ |
143 | #define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */ |
| 144 | #define LL_GPIO_MODE_FLOATING GPIO_CRL_CNF0_0 /*!< Select floating mode */ |
144 | #define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */ |
| 145 | #define LL_GPIO_MODE_INPUT GPIO_CRL_CNF0_1 /*!< Select input mode */ |
145 | #define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */ |
| 146 | #define LL_GPIO_MODE_OUTPUT GPIO_CRL_MODE0_0 /*!< Select general purpose output mode */ |
146 | #define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */ |
| 147 | #define LL_GPIO_MODE_ALTERNATE (GPIO_CRL_CNF0_1 | GPIO_CRL_MODE0_0) /*!< Select alternate function mode */ |
147 | /** |
| 148 | /** |
148 | * @} |
| 149 | * @} |
149 | */ |
| 150 | */ |
150 | |
| 151 | 151 | /** @defgroup GPIO_LL_EC_OUTPUT Output Type |
|
| 152 | /** @defgroup GPIO_LL_EC_OUTPUT Output Type |
152 | * @{ |
| 153 | * @{ |
153 | */ |
| 154 | */ |
154 | #define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */ |
| 155 | #define LL_GPIO_OUTPUT_PUSHPULL 0x00000000U /*!< Select push-pull as output type */ |
155 | #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */ |
| 156 | #define LL_GPIO_OUTPUT_OPENDRAIN GPIO_CRL_CNF0_0 /*!< Select open-drain as output type */ |
156 | /** |
| 157 | /** |
157 | * @} |
| 158 | * @} |
158 | */ |
| 159 | */ |
159 | |
| 160 | 160 | /** @defgroup GPIO_LL_EC_SPEED Output Speed |
|
| 161 | /** @defgroup GPIO_LL_EC_SPEED Output Speed |
161 | * @{ |
| 162 | * @{ |
162 | */ |
| 163 | */ |
163 | #define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */ |
| 164 | #define LL_GPIO_MODE_OUTPUT_10MHz GPIO_CRL_MODE0_0 /*!< Select Output mode, max speed 10 MHz */ |
164 | #define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */ |
| 165 | #define LL_GPIO_MODE_OUTPUT_2MHz GPIO_CRL_MODE0_1 /*!< Select Output mode, max speed 20 MHz */ |
165 | #define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */ |
| 166 | #define LL_GPIO_MODE_OUTPUT_50MHz GPIO_CRL_MODE0 /*!< Select Output mode, max speed 50 MHz */ |
166 | /** |
| 167 | /** |
167 | * @} |
| 168 | * @} |
168 | */ |
| 169 | */ |
169 | |
| 170 | 170 | #define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */ |
|
| 171 | #define LL_GPIO_SPEED_FREQ_LOW LL_GPIO_MODE_OUTPUT_2MHz /*!< Select I/O low output speed */ |
171 | #define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */ |
| 172 | #define LL_GPIO_SPEED_FREQ_MEDIUM LL_GPIO_MODE_OUTPUT_10MHz /*!< Select I/O medium output speed */ |
172 | #define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */ |
| 173 | #define LL_GPIO_SPEED_FREQ_HIGH LL_GPIO_MODE_OUTPUT_50MHz /*!< Select I/O high output speed */ |
173 | |
| 174 | 174 | /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down |
|
| 175 | /** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down |
175 | * @{ |
| 176 | * @{ |
176 | */ |
| 177 | */ |
177 | #define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */ |
| 178 | #define LL_GPIO_PULL_DOWN 0x00000000U /*!< Select I/O pull down */ |
178 | #define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */ |
| 179 | #define LL_GPIO_PULL_UP GPIO_ODR_ODR0 /*!< Select I/O pull up */ |
179 | |
| 180 | 180 | /** |
|
| 181 | /** |
181 | * @} |
| 182 | * @} |
182 | */ |
| 183 | */ |
183 | |
| 184 | 184 | /** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin |
|
| 185 | /** @defgroup GPIO_LL_EVENTOUT_PIN EVENTOUT Pin |
185 | * @{ |
| 186 | * @{ |
186 | */ |
| 187 | */ |
187 | |
| 188 | 188 | #define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ |
|
| 189 | #define LL_GPIO_AF_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ |
189 | #define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ |
| 190 | #define LL_GPIO_AF_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ |
190 | #define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ |
| 191 | #define LL_GPIO_AF_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ |
191 | #define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ |
| 192 | #define LL_GPIO_AF_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ |
192 | #define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ |
| 193 | #define LL_GPIO_AF_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ |
193 | #define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ |
| 194 | #define LL_GPIO_AF_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ |
194 | #define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ |
| 195 | #define LL_GPIO_AF_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ |
195 | #define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ |
| 196 | #define LL_GPIO_AF_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ |
196 | #define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ |
| 197 | #define LL_GPIO_AF_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ |
197 | #define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ |
| 198 | #define LL_GPIO_AF_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ |
198 | #define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ |
| 199 | #define LL_GPIO_AF_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ |
199 | #define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ |
| 200 | #define LL_GPIO_AF_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ |
200 | #define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ |
| 201 | #define LL_GPIO_AF_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ |
201 | #define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ |
| 202 | #define LL_GPIO_AF_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ |
202 | #define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ |
| 203 | #define LL_GPIO_AF_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ |
203 | #define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ |
| 204 | #define LL_GPIO_AF_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ |
204 | |
| 205 | 205 | /** |
|
| 206 | /** |
206 | * @} |
| 207 | * @} |
207 | */ |
| 208 | */ |
208 | |
| 209 | 209 | /** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port |
|
| 210 | /** @defgroup GPIO_LL_EVENTOUT_PORT EVENTOUT Port |
210 | * @{ |
| 211 | * @{ |
211 | */ |
| 212 | */ |
212 | |
| 213 | 213 | #define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ |
|
| 214 | #define LL_GPIO_AF_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ |
214 | #define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ |
| 215 | #define LL_GPIO_AF_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ |
215 | #define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ |
| 216 | #define LL_GPIO_AF_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ |
216 | #define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ |
| 217 | #define LL_GPIO_AF_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ |
217 | #define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ |
| 218 | #define LL_GPIO_AF_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ |
218 | |
| 219 | 219 | /** |
|
| 220 | /** |
220 | * @} |
| 221 | * @} |
221 | */ |
| 222 | */ |
222 | |
| 223 | 223 | /** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT |
|
| 224 | /** @defgroup GPIO_LL_EC_EXTI_PORT GPIO EXTI PORT |
224 | * @{ |
| 225 | * @{ |
225 | */ |
| 226 | */ |
226 | #define LL_GPIO_AF_EXTI_PORTA 0U /*!< EXTI PORT A */ |
| 227 | #define LL_GPIO_AF_EXTI_PORTA 0U /*!< EXTI PORT A */ |
227 | #define LL_GPIO_AF_EXTI_PORTB 1U /*!< EXTI PORT B */ |
| 228 | #define LL_GPIO_AF_EXTI_PORTB 1U /*!< EXTI PORT B */ |
228 | #define LL_GPIO_AF_EXTI_PORTC 2U /*!< EXTI PORT C */ |
| 229 | #define LL_GPIO_AF_EXTI_PORTC 2U /*!< EXTI PORT C */ |
229 | #define LL_GPIO_AF_EXTI_PORTD 3U /*!< EXTI PORT D */ |
| 230 | #define LL_GPIO_AF_EXTI_PORTD 3U /*!< EXTI PORT D */ |
230 | #define LL_GPIO_AF_EXTI_PORTE 4U /*!< EXTI PORT E */ |
| 231 | #define LL_GPIO_AF_EXTI_PORTE 4U /*!< EXTI PORT E */ |
231 | #define LL_GPIO_AF_EXTI_PORTF 5U /*!< EXTI PORT F */ |
| 232 | #define LL_GPIO_AF_EXTI_PORTF 5U /*!< EXTI PORT F */ |
232 | #define LL_GPIO_AF_EXTI_PORTG 6U /*!< EXTI PORT G */ |
| 233 | #define LL_GPIO_AF_EXTI_PORTG 6U /*!< EXTI PORT G */ |
233 | /** |
| 234 | /** |
234 | * @} |
| 235 | * @} |
235 | */ |
| 236 | */ |
236 | |
| 237 | 237 | /** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE |
|
| 238 | /** @defgroup GPIO_LL_EC_EXTI_LINE GPIO EXTI LINE |
238 | * @{ |
| 239 | * @{ |
239 | */ |
| 240 | */ |
240 | #define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ |
| 241 | #define LL_GPIO_AF_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ |
241 | #define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ |
| 242 | #define LL_GPIO_AF_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */ |
242 | #define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ |
| 243 | #define LL_GPIO_AF_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ |
243 | #define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ |
| 244 | #define LL_GPIO_AF_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */ |
244 | #define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ |
| 245 | #define LL_GPIO_AF_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ |
245 | #define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ |
| 246 | #define LL_GPIO_AF_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */ |
246 | #define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ |
| 247 | #define LL_GPIO_AF_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ |
247 | #define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ |
| 248 | #define LL_GPIO_AF_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */ |
248 | #define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ |
| 249 | #define LL_GPIO_AF_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ |
249 | #define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ |
| 250 | #define LL_GPIO_AF_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */ |
250 | #define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ |
| 251 | #define LL_GPIO_AF_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ |
251 | #define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ |
| 252 | #define LL_GPIO_AF_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */ |
252 | #define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ |
| 253 | #define LL_GPIO_AF_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ |
253 | #define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ |
| 254 | #define LL_GPIO_AF_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */ |
254 | #define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ |
| 255 | #define LL_GPIO_AF_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ |
255 | #define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ |
| 256 | #define LL_GPIO_AF_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */ |
256 | /** |
| 257 | /** |
257 | * @} |
| 258 | * @} |
258 | */ |
| 259 | */ |
259 | |
| 260 | 260 | /** |
|
| 261 | /** |
261 | * @} |
| 262 | * @} |
262 | */ |
| 263 | */ |
263 | |
| 264 | 264 | /* Exported macro ------------------------------------------------------------*/ |
|
| 265 | /* Exported macro ------------------------------------------------------------*/ |
265 | /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros |
| 266 | /** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros |
266 | * @{ |
| 267 | * @{ |
267 | */ |
| 268 | */ |
268 | |
| 269 | 269 | /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros |
|
| 270 | /** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros |
270 | * @{ |
| 271 | * @{ |
271 | */ |
| 272 | */ |
272 | |
| 273 | 273 | /** |
|
| 274 | /** |
274 | * @brief Write a value in GPIO register |
| 275 | * @brief Write a value in GPIO register |
275 | * @param __INSTANCE__ GPIO Instance |
| 276 | * @param __INSTANCE__ GPIO Instance |
276 | * @param __REG__ Register to be written |
| 277 | * @param __REG__ Register to be written |
277 | * @param __VALUE__ Value to be written in the register |
| 278 | * @param __VALUE__ Value to be written in the register |
278 | * @retval None |
| 279 | * @retval None |
279 | */ |
| 280 | */ |
280 | #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
| 281 | #define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) |
281 | |
| 282 | 282 | /** |
|
| 283 | /** |
283 | * @brief Read a value in GPIO register |
| 284 | * @brief Read a value in GPIO register |
284 | * @param __INSTANCE__ GPIO Instance |
| 285 | * @param __INSTANCE__ GPIO Instance |
285 | * @param __REG__ Register to be read |
| 286 | * @param __REG__ Register to be read |
286 | * @retval Register value |
| 287 | * @retval Register value |
287 | */ |
| 288 | */ |
288 | #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
| 289 | #define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) |
289 | /** |
| 290 | /** |
290 | * @} |
| 291 | * @} |
291 | */ |
| 292 | */ |
292 | |
| 293 | 293 | /** |
|
| 294 | /** |
294 | * @} |
| 295 | * @} |
295 | */ |
| 296 | */ |
296 | |
| 297 | 297 | /* Exported functions --------------------------------------------------------*/ |
|
| 298 | /* Exported functions --------------------------------------------------------*/ |
298 | /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions |
| 299 | /** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions |
299 | * @{ |
| 300 | * @{ |
300 | */ |
| 301 | */ |
301 | |
| 302 | 302 | /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration |
|
| 303 | /** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration |
303 | * @{ |
| 304 | * @{ |
304 | */ |
| 305 | */ |
305 | |
| 306 | 306 | /** |
|
| 307 | /** |
307 | * @brief Configure gpio mode for a dedicated pin on dedicated port. |
| 308 | * @brief Configure gpio mode for a dedicated pin on dedicated port. |
308 | * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, |
| 309 | * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, |
309 | * Alternate function Output. |
| 310 | * Alternate function Output. |
310 | * @note Warning: only one pin can be passed as parameter. |
| 311 | * @note Warning: only one pin can be passed as parameter. |
311 | * @rmtoll CRL CNFy LL_GPIO_SetPinMode |
| 312 | * @rmtoll CRL CNFy LL_GPIO_SetPinMode |
312 | * @rmtoll CRL MODEy LL_GPIO_SetPinMode |
| 313 | * @rmtoll CRL MODEy LL_GPIO_SetPinMode |
313 | * @rmtoll CRH CNFy LL_GPIO_SetPinMode |
| 314 | * @rmtoll CRH CNFy LL_GPIO_SetPinMode |
314 | * @rmtoll CRH MODEy LL_GPIO_SetPinMode |
| 315 | * @rmtoll CRH MODEy LL_GPIO_SetPinMode |
315 | * @param GPIOx GPIO Port |
| 316 | * @param GPIOx GPIO Port |
316 | * @param Pin This parameter can be one of the following values: |
| 317 | * @param Pin This parameter can be one of the following values: |
317 | * @arg @ref LL_GPIO_PIN_0 |
| 318 | * @arg @ref LL_GPIO_PIN_0 |
318 | * @arg @ref LL_GPIO_PIN_1 |
| 319 | * @arg @ref LL_GPIO_PIN_1 |
319 | * @arg @ref LL_GPIO_PIN_2 |
| 320 | * @arg @ref LL_GPIO_PIN_2 |
320 | * @arg @ref LL_GPIO_PIN_3 |
| 321 | * @arg @ref LL_GPIO_PIN_3 |
321 | * @arg @ref LL_GPIO_PIN_4 |
| 322 | * @arg @ref LL_GPIO_PIN_4 |
322 | * @arg @ref LL_GPIO_PIN_5 |
| 323 | * @arg @ref LL_GPIO_PIN_5 |
323 | * @arg @ref LL_GPIO_PIN_6 |
| 324 | * @arg @ref LL_GPIO_PIN_6 |
324 | * @arg @ref LL_GPIO_PIN_7 |
| 325 | * @arg @ref LL_GPIO_PIN_7 |
325 | * @arg @ref LL_GPIO_PIN_8 |
| 326 | * @arg @ref LL_GPIO_PIN_8 |
326 | * @arg @ref LL_GPIO_PIN_9 |
| 327 | * @arg @ref LL_GPIO_PIN_9 |
327 | * @arg @ref LL_GPIO_PIN_10 |
| 328 | * @arg @ref LL_GPIO_PIN_10 |
328 | * @arg @ref LL_GPIO_PIN_11 |
| 329 | * @arg @ref LL_GPIO_PIN_11 |
329 | * @arg @ref LL_GPIO_PIN_12 |
| 330 | * @arg @ref LL_GPIO_PIN_12 |
330 | * @arg @ref LL_GPIO_PIN_13 |
| 331 | * @arg @ref LL_GPIO_PIN_13 |
331 | * @arg @ref LL_GPIO_PIN_14 |
| 332 | * @arg @ref LL_GPIO_PIN_14 |
332 | * @arg @ref LL_GPIO_PIN_15 |
| 333 | * @arg @ref LL_GPIO_PIN_15 |
333 | * @param Mode This parameter can be one of the following values: |
| 334 | * @param Mode This parameter can be one of the following values: |
334 | * @arg @ref LL_GPIO_MODE_ANALOG |
| 335 | * @arg @ref LL_GPIO_MODE_ANALOG |
335 | * @arg @ref LL_GPIO_MODE_FLOATING |
| 336 | * @arg @ref LL_GPIO_MODE_FLOATING |
336 | * @arg @ref LL_GPIO_MODE_INPUT |
| 337 | * @arg @ref LL_GPIO_MODE_INPUT |
337 | * @arg @ref LL_GPIO_MODE_OUTPUT |
| 338 | * @arg @ref LL_GPIO_MODE_OUTPUT |
338 | * @arg @ref LL_GPIO_MODE_ALTERNATE |
| 339 | * @arg @ref LL_GPIO_MODE_ALTERNATE |
339 | * @retval None |
| 340 | * @retval None |
340 | */ |
| 341 | */ |
341 | __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) |
| 342 | __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) |
342 | { |
| 343 | { |
343 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
| 344 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
344 | MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U))); |
| 345 | MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U))); |
345 | } |
| 346 | } |
346 | |
| 347 | 347 | /** |
|
| 348 | /** |
348 | * @brief Return gpio mode for a dedicated pin on dedicated port. |
| 349 | * @brief Return gpio mode for a dedicated pin on dedicated port. |
349 | * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, |
| 350 | * @note I/O mode can be Analog, Floating input, Input with pull-up/pull-down, General purpose Output, |
350 | * Alternate function Output. |
| 351 | * Alternate function Output. |
351 | * @note Warning: only one pin can be passed as parameter. |
| 352 | * @note Warning: only one pin can be passed as parameter. |
352 | * @rmtoll CRL CNFy LL_GPIO_GetPinMode |
| 353 | * @rmtoll CRL CNFy LL_GPIO_GetPinMode |
353 | * @rmtoll CRL MODEy LL_GPIO_GetPinMode |
| 354 | * @rmtoll CRL MODEy LL_GPIO_GetPinMode |
354 | * @rmtoll CRH CNFy LL_GPIO_GetPinMode |
| 355 | * @rmtoll CRH CNFy LL_GPIO_GetPinMode |
355 | * @rmtoll CRH MODEy LL_GPIO_GetPinMode |
| 356 | * @rmtoll CRH MODEy LL_GPIO_GetPinMode |
356 | * @param GPIOx GPIO Port |
| 357 | * @param GPIOx GPIO Port |
357 | * @param Pin This parameter can be one of the following values: |
| 358 | * @param Pin This parameter can be one of the following values: |
358 | * @arg @ref LL_GPIO_PIN_0 |
| 359 | * @arg @ref LL_GPIO_PIN_0 |
359 | * @arg @ref LL_GPIO_PIN_1 |
| 360 | * @arg @ref LL_GPIO_PIN_1 |
360 | * @arg @ref LL_GPIO_PIN_2 |
| 361 | * @arg @ref LL_GPIO_PIN_2 |
361 | * @arg @ref LL_GPIO_PIN_3 |
| 362 | * @arg @ref LL_GPIO_PIN_3 |
362 | * @arg @ref LL_GPIO_PIN_4 |
| 363 | * @arg @ref LL_GPIO_PIN_4 |
363 | * @arg @ref LL_GPIO_PIN_5 |
| 364 | * @arg @ref LL_GPIO_PIN_5 |
364 | * @arg @ref LL_GPIO_PIN_6 |
| 365 | * @arg @ref LL_GPIO_PIN_6 |
365 | * @arg @ref LL_GPIO_PIN_7 |
| 366 | * @arg @ref LL_GPIO_PIN_7 |
366 | * @arg @ref LL_GPIO_PIN_8 |
| 367 | * @arg @ref LL_GPIO_PIN_8 |
367 | * @arg @ref LL_GPIO_PIN_9 |
| 368 | * @arg @ref LL_GPIO_PIN_9 |
368 | * @arg @ref LL_GPIO_PIN_10 |
| 369 | * @arg @ref LL_GPIO_PIN_10 |
369 | * @arg @ref LL_GPIO_PIN_11 |
| 370 | * @arg @ref LL_GPIO_PIN_11 |
370 | * @arg @ref LL_GPIO_PIN_12 |
| 371 | * @arg @ref LL_GPIO_PIN_12 |
371 | * @arg @ref LL_GPIO_PIN_13 |
| 372 | * @arg @ref LL_GPIO_PIN_13 |
372 | * @arg @ref LL_GPIO_PIN_14 |
| 373 | * @arg @ref LL_GPIO_PIN_14 |
373 | * @arg @ref LL_GPIO_PIN_15 |
| 374 | * @arg @ref LL_GPIO_PIN_15 |
374 | * @retval Returned value can be one of the following values: |
| 375 | * @retval Returned value can be one of the following values: |
375 | * @arg @ref LL_GPIO_MODE_ANALOG |
| 376 | * @arg @ref LL_GPIO_MODE_ANALOG |
376 | * @arg @ref LL_GPIO_MODE_FLOATING |
| 377 | * @arg @ref LL_GPIO_MODE_FLOATING |
377 | * @arg @ref LL_GPIO_MODE_INPUT |
| 378 | * @arg @ref LL_GPIO_MODE_INPUT |
378 | * @arg @ref LL_GPIO_MODE_OUTPUT |
| 379 | * @arg @ref LL_GPIO_MODE_OUTPUT |
379 | * @arg @ref LL_GPIO_MODE_ALTERNATE |
| 380 | * @arg @ref LL_GPIO_MODE_ALTERNATE |
380 | */ |
| 381 | */ |
381 | __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) |
| 382 | __STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) |
382 | { |
| 383 | { |
383 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
| 384 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
384 | return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); |
| 385 | return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); |
385 | } |
| 386 | } |
386 | |
| 387 | 387 | /** |
|
| 388 | /** |
388 | * @brief Configure gpio speed for a dedicated pin on dedicated port. |
| 389 | * @brief Configure gpio speed for a dedicated pin on dedicated port. |
389 | * @note I/O speed can be Low, Medium or Fast speed. |
| 390 | * @note I/O speed can be Low, Medium or Fast speed. |
390 | * @note Warning: only one pin can be passed as parameter. |
| 391 | * @note Warning: only one pin can be passed as parameter. |
391 | * @note Refer to datasheet for frequency specifications and the power |
| 392 | * @note Refer to datasheet for frequency specifications and the power |
392 | * supply and load conditions for each speed. |
| 393 | * supply and load conditions for each speed. |
393 | * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed |
| 394 | * @rmtoll CRL MODEy LL_GPIO_SetPinSpeed |
394 | * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed |
| 395 | * @rmtoll CRH MODEy LL_GPIO_SetPinSpeed |
395 | * @param GPIOx GPIO Port |
| 396 | * @param GPIOx GPIO Port |
396 | * @param Pin This parameter can be one of the following values: |
| 397 | * @param Pin This parameter can be one of the following values: |
397 | * @arg @ref LL_GPIO_PIN_0 |
| 398 | * @arg @ref LL_GPIO_PIN_0 |
398 | * @arg @ref LL_GPIO_PIN_1 |
| 399 | * @arg @ref LL_GPIO_PIN_1 |
399 | * @arg @ref LL_GPIO_PIN_2 |
| 400 | * @arg @ref LL_GPIO_PIN_2 |
400 | * @arg @ref LL_GPIO_PIN_3 |
| 401 | * @arg @ref LL_GPIO_PIN_3 |
401 | * @arg @ref LL_GPIO_PIN_4 |
| 402 | * @arg @ref LL_GPIO_PIN_4 |
402 | * @arg @ref LL_GPIO_PIN_5 |
| 403 | * @arg @ref LL_GPIO_PIN_5 |
403 | * @arg @ref LL_GPIO_PIN_6 |
| 404 | * @arg @ref LL_GPIO_PIN_6 |
404 | * @arg @ref LL_GPIO_PIN_7 |
| 405 | * @arg @ref LL_GPIO_PIN_7 |
405 | * @arg @ref LL_GPIO_PIN_8 |
| 406 | * @arg @ref LL_GPIO_PIN_8 |
406 | * @arg @ref LL_GPIO_PIN_9 |
| 407 | * @arg @ref LL_GPIO_PIN_9 |
407 | * @arg @ref LL_GPIO_PIN_10 |
| 408 | * @arg @ref LL_GPIO_PIN_10 |
408 | * @arg @ref LL_GPIO_PIN_11 |
| 409 | * @arg @ref LL_GPIO_PIN_11 |
409 | * @arg @ref LL_GPIO_PIN_12 |
| 410 | * @arg @ref LL_GPIO_PIN_12 |
410 | * @arg @ref LL_GPIO_PIN_13 |
| 411 | * @arg @ref LL_GPIO_PIN_13 |
411 | * @arg @ref LL_GPIO_PIN_14 |
| 412 | * @arg @ref LL_GPIO_PIN_14 |
412 | * @arg @ref LL_GPIO_PIN_15 |
| 413 | * @arg @ref LL_GPIO_PIN_15 |
413 | * @param Speed This parameter can be one of the following values: |
| 414 | * @param Speed This parameter can be one of the following values: |
414 | * @arg @ref LL_GPIO_SPEED_FREQ_LOW |
| 415 | * @arg @ref LL_GPIO_SPEED_FREQ_LOW |
415 | * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM |
| 416 | * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM |
416 | * @arg @ref LL_GPIO_SPEED_FREQ_HIGH |
| 417 | * @arg @ref LL_GPIO_SPEED_FREQ_HIGH |
417 | * @retval None |
| 418 | * @retval None |
418 | */ |
| 419 | */ |
419 | __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) |
| 420 | __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) |
420 | { |
| 421 | { |
421 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
| 422 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
422 | MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)), |
| 423 | MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)), |
423 | (Speed << (POSITION_VAL(Pin) * 4U))); |
| 424 | (Speed << (POSITION_VAL(Pin) * 4U))); |
424 | } |
| 425 | } |
425 | |
| 426 | 426 | /** |
|
| 427 | /** |
427 | * @brief Return gpio speed for a dedicated pin on dedicated port. |
| 428 | * @brief Return gpio speed for a dedicated pin on dedicated port. |
428 | * @note I/O speed can be Low, Medium, Fast or High speed. |
| 429 | * @note I/O speed can be Low, Medium, Fast or High speed. |
429 | * @note Warning: only one pin can be passed as parameter. |
| 430 | * @note Warning: only one pin can be passed as parameter. |
430 | * @note Refer to datasheet for frequency specifications and the power |
| 431 | * @note Refer to datasheet for frequency specifications and the power |
431 | * supply and load conditions for each speed. |
| 432 | * supply and load conditions for each speed. |
432 | * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed |
| 433 | * @rmtoll CRL MODEy LL_GPIO_GetPinSpeed |
433 | * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed |
| 434 | * @rmtoll CRH MODEy LL_GPIO_GetPinSpeed |
434 | * @param GPIOx GPIO Port |
| 435 | * @param GPIOx GPIO Port |
435 | * @param Pin This parameter can be one of the following values: |
| 436 | * @param Pin This parameter can be one of the following values: |
436 | * @arg @ref LL_GPIO_PIN_0 |
| 437 | * @arg @ref LL_GPIO_PIN_0 |
437 | * @arg @ref LL_GPIO_PIN_1 |
| 438 | * @arg @ref LL_GPIO_PIN_1 |
438 | * @arg @ref LL_GPIO_PIN_2 |
| 439 | * @arg @ref LL_GPIO_PIN_2 |
439 | * @arg @ref LL_GPIO_PIN_3 |
| 440 | * @arg @ref LL_GPIO_PIN_3 |
440 | * @arg @ref LL_GPIO_PIN_4 |
| 441 | * @arg @ref LL_GPIO_PIN_4 |
441 | * @arg @ref LL_GPIO_PIN_5 |
| 442 | * @arg @ref LL_GPIO_PIN_5 |
442 | * @arg @ref LL_GPIO_PIN_6 |
| 443 | * @arg @ref LL_GPIO_PIN_6 |
443 | * @arg @ref LL_GPIO_PIN_7 |
| 444 | * @arg @ref LL_GPIO_PIN_7 |
444 | * @arg @ref LL_GPIO_PIN_8 |
| 445 | * @arg @ref LL_GPIO_PIN_8 |
445 | * @arg @ref LL_GPIO_PIN_9 |
| 446 | * @arg @ref LL_GPIO_PIN_9 |
446 | * @arg @ref LL_GPIO_PIN_10 |
| 447 | * @arg @ref LL_GPIO_PIN_10 |
447 | * @arg @ref LL_GPIO_PIN_11 |
| 448 | * @arg @ref LL_GPIO_PIN_11 |
448 | * @arg @ref LL_GPIO_PIN_12 |
| 449 | * @arg @ref LL_GPIO_PIN_12 |
449 | * @arg @ref LL_GPIO_PIN_13 |
| 450 | * @arg @ref LL_GPIO_PIN_13 |
450 | * @arg @ref LL_GPIO_PIN_14 |
| 451 | * @arg @ref LL_GPIO_PIN_14 |
451 | * @arg @ref LL_GPIO_PIN_15 |
| 452 | * @arg @ref LL_GPIO_PIN_15 |
452 | * @retval Returned value can be one of the following values: |
| 453 | * @retval Returned value can be one of the following values: |
453 | * @arg @ref LL_GPIO_SPEED_FREQ_LOW |
| 454 | * @arg @ref LL_GPIO_SPEED_FREQ_LOW |
454 | * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM |
| 455 | * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM |
455 | * @arg @ref LL_GPIO_SPEED_FREQ_HIGH |
| 456 | * @arg @ref LL_GPIO_SPEED_FREQ_HIGH |
456 | */ |
| 457 | */ |
457 | __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) |
| 458 | __STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) |
458 | { |
| 459 | { |
459 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
| 460 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
460 | return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); |
| 461 | return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); |
461 | } |
| 462 | } |
462 | |
| 463 | 463 | /** |
|
| 464 | /** |
464 | * @brief Configure gpio output type for several pins on dedicated port. |
| 465 | * @brief Configure gpio output type for several pins on dedicated port. |
465 | * @note Output type as to be set when gpio pin is in output or |
| 466 | * @note Output type as to be set when gpio pin is in output or |
466 | * alternate modes. Possible type are Push-pull or Open-drain. |
| 467 | * alternate modes. Possible type are Push-pull or Open-drain. |
467 | * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType |
| 468 | * @rmtoll CRL MODEy LL_GPIO_SetPinOutputType |
468 | * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType |
| 469 | * @rmtoll CRH MODEy LL_GPIO_SetPinOutputType |
469 | * @param GPIOx GPIO Port |
| 470 | * @param GPIOx GPIO Port |
470 | * @param Pin This parameter can be a combination of the following values: |
| 471 | * @param Pin This parameter can be a combination of the following values: |
471 | * @arg @ref LL_GPIO_PIN_0 |
| 472 | * @arg @ref LL_GPIO_PIN_0 |
472 | * @arg @ref LL_GPIO_PIN_1 |
| 473 | * @arg @ref LL_GPIO_PIN_1 |
473 | * @arg @ref LL_GPIO_PIN_2 |
| 474 | * @arg @ref LL_GPIO_PIN_2 |
474 | * @arg @ref LL_GPIO_PIN_3 |
| 475 | * @arg @ref LL_GPIO_PIN_3 |
475 | * @arg @ref LL_GPIO_PIN_4 |
| 476 | * @arg @ref LL_GPIO_PIN_4 |
476 | * @arg @ref LL_GPIO_PIN_5 |
| 477 | * @arg @ref LL_GPIO_PIN_5 |
477 | * @arg @ref LL_GPIO_PIN_6 |
| 478 | * @arg @ref LL_GPIO_PIN_6 |
478 | * @arg @ref LL_GPIO_PIN_7 |
| 479 | * @arg @ref LL_GPIO_PIN_7 |
479 | * @arg @ref LL_GPIO_PIN_8 |
| 480 | * @arg @ref LL_GPIO_PIN_8 |
480 | * @arg @ref LL_GPIO_PIN_9 |
| 481 | * @arg @ref LL_GPIO_PIN_9 |
481 | * @arg @ref LL_GPIO_PIN_10 |
| 482 | * @arg @ref LL_GPIO_PIN_10 |
482 | * @arg @ref LL_GPIO_PIN_11 |
| 483 | * @arg @ref LL_GPIO_PIN_11 |
483 | * @arg @ref LL_GPIO_PIN_12 |
| 484 | * @arg @ref LL_GPIO_PIN_12 |
484 | * @arg @ref LL_GPIO_PIN_13 |
| 485 | * @arg @ref LL_GPIO_PIN_13 |
485 | * @arg @ref LL_GPIO_PIN_14 |
| 486 | * @arg @ref LL_GPIO_PIN_14 |
486 | * @arg @ref LL_GPIO_PIN_15 |
| 487 | * @arg @ref LL_GPIO_PIN_15 |
487 | * @arg @ref LL_GPIO_PIN_ALL |
| 488 | * @arg @ref LL_GPIO_PIN_ALL |
488 | * @param OutputType This parameter can be one of the following values: |
| 489 | * @param OutputType This parameter can be one of the following values: |
489 | * @arg @ref LL_GPIO_OUTPUT_PUSHPULL |
| 490 | * @arg @ref LL_GPIO_OUTPUT_PUSHPULL |
490 | * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN |
| 491 | * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN |
491 | * @retval None |
| 492 | * @retval None |
492 | */ |
| 493 | */ |
493 | __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType) |
| 494 | __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType) |
494 | { |
| 495 | { |
495 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
| 496 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
496 | MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)), |
| 497 | MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)), |
497 | (OutputType << (POSITION_VAL(Pin) * 4U))); |
| 498 | (OutputType << (POSITION_VAL(Pin) * 4U))); |
498 | } |
| 499 | } |
499 | |
| 500 | 500 | /** |
|
| 501 | /** |
501 | * @brief Return gpio output type for several pins on dedicated port. |
| 502 | * @brief Return gpio output type for several pins on dedicated port. |
502 | * @note Output type as to be set when gpio pin is in output or |
| 503 | * @note Output type as to be set when gpio pin is in output or |
503 | * alternate modes. Possible type are Push-pull or Open-drain. |
| 504 | * alternate modes. Possible type are Push-pull or Open-drain. |
504 | * @note Warning: only one pin can be passed as parameter. |
| 505 | * @note Warning: only one pin can be passed as parameter. |
505 | * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType |
| 506 | * @rmtoll CRL MODEy LL_GPIO_GetPinOutputType |
506 | * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType |
| 507 | * @rmtoll CRH MODEy LL_GPIO_GetPinOutputType |
507 | * @param GPIOx GPIO Port |
| 508 | * @param GPIOx GPIO Port |
508 | * @param Pin This parameter can be one of the following values: |
| 509 | * @param Pin This parameter can be one of the following values: |
509 | * @arg @ref LL_GPIO_PIN_0 |
| 510 | * @arg @ref LL_GPIO_PIN_0 |
510 | * @arg @ref LL_GPIO_PIN_1 |
| 511 | * @arg @ref LL_GPIO_PIN_1 |
511 | * @arg @ref LL_GPIO_PIN_2 |
| 512 | * @arg @ref LL_GPIO_PIN_2 |
512 | * @arg @ref LL_GPIO_PIN_3 |
| 513 | * @arg @ref LL_GPIO_PIN_3 |
513 | * @arg @ref LL_GPIO_PIN_4 |
| 514 | * @arg @ref LL_GPIO_PIN_4 |
514 | * @arg @ref LL_GPIO_PIN_5 |
| 515 | * @arg @ref LL_GPIO_PIN_5 |
515 | * @arg @ref LL_GPIO_PIN_6 |
| 516 | * @arg @ref LL_GPIO_PIN_6 |
516 | * @arg @ref LL_GPIO_PIN_7 |
| 517 | * @arg @ref LL_GPIO_PIN_7 |
517 | * @arg @ref LL_GPIO_PIN_8 |
| 518 | * @arg @ref LL_GPIO_PIN_8 |
518 | * @arg @ref LL_GPIO_PIN_9 |
| 519 | * @arg @ref LL_GPIO_PIN_9 |
519 | * @arg @ref LL_GPIO_PIN_10 |
| 520 | * @arg @ref LL_GPIO_PIN_10 |
520 | * @arg @ref LL_GPIO_PIN_11 |
| 521 | * @arg @ref LL_GPIO_PIN_11 |
521 | * @arg @ref LL_GPIO_PIN_12 |
| 522 | * @arg @ref LL_GPIO_PIN_12 |
522 | * @arg @ref LL_GPIO_PIN_13 |
| 523 | * @arg @ref LL_GPIO_PIN_13 |
523 | * @arg @ref LL_GPIO_PIN_14 |
| 524 | * @arg @ref LL_GPIO_PIN_14 |
524 | * @arg @ref LL_GPIO_PIN_15 |
| 525 | * @arg @ref LL_GPIO_PIN_15 |
525 | * @arg @ref LL_GPIO_PIN_ALL |
| 526 | * @arg @ref LL_GPIO_PIN_ALL |
526 | * @retval Returned value can be one of the following values: |
| 527 | * @retval Returned value can be one of the following values: |
527 | * @arg @ref LL_GPIO_OUTPUT_PUSHPULL |
| 528 | * @arg @ref LL_GPIO_OUTPUT_PUSHPULL |
528 | * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN |
| 529 | * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN |
529 | */ |
| 530 | */ |
530 | __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) |
| 531 | __STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) |
531 | { |
| 532 | { |
532 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
| 533 | register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24))); |
533 | return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); |
| 534 | return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); |
534 | |
| 535 | 535 | } |
|
| 536 | } |
536 | |
| 537 | 537 | /** |
|
| 538 | /** |
538 | * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. |
| 539 | * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. |
539 | * @note Warning: only one pin can be passed as parameter. |
| 540 | * @note Warning: only one pin can be passed as parameter. |
540 | * @rmtoll ODR ODR LL_GPIO_SetPinPull |
| 541 | * @rmtoll ODR ODR LL_GPIO_SetPinPull |
541 | * @param GPIOx GPIO Port |
| 542 | * @param GPIOx GPIO Port |
542 | * @param Pin This parameter can be one of the following values: |
| 543 | * @param Pin This parameter can be one of the following values: |
543 | * @arg @ref LL_GPIO_PIN_0 |
| 544 | * @arg @ref LL_GPIO_PIN_0 |
544 | * @arg @ref LL_GPIO_PIN_1 |
| 545 | * @arg @ref LL_GPIO_PIN_1 |
545 | * @arg @ref LL_GPIO_PIN_2 |
| 546 | * @arg @ref LL_GPIO_PIN_2 |
546 | * @arg @ref LL_GPIO_PIN_3 |
| 547 | * @arg @ref LL_GPIO_PIN_3 |
547 | * @arg @ref LL_GPIO_PIN_4 |
| 548 | * @arg @ref LL_GPIO_PIN_4 |
548 | * @arg @ref LL_GPIO_PIN_5 |
| 549 | * @arg @ref LL_GPIO_PIN_5 |
549 | * @arg @ref LL_GPIO_PIN_6 |
| 550 | * @arg @ref LL_GPIO_PIN_6 |
550 | * @arg @ref LL_GPIO_PIN_7 |
| 551 | * @arg @ref LL_GPIO_PIN_7 |
551 | * @arg @ref LL_GPIO_PIN_8 |
| 552 | * @arg @ref LL_GPIO_PIN_8 |
552 | * @arg @ref LL_GPIO_PIN_9 |
| 553 | * @arg @ref LL_GPIO_PIN_9 |
553 | * @arg @ref LL_GPIO_PIN_10 |
| 554 | * @arg @ref LL_GPIO_PIN_10 |
554 | * @arg @ref LL_GPIO_PIN_11 |
| 555 | * @arg @ref LL_GPIO_PIN_11 |
555 | * @arg @ref LL_GPIO_PIN_12 |
| 556 | * @arg @ref LL_GPIO_PIN_12 |
556 | * @arg @ref LL_GPIO_PIN_13 |
| 557 | * @arg @ref LL_GPIO_PIN_13 |
557 | * @arg @ref LL_GPIO_PIN_14 |
| 558 | * @arg @ref LL_GPIO_PIN_14 |
558 | * @arg @ref LL_GPIO_PIN_15 |
| 559 | * @arg @ref LL_GPIO_PIN_15 |
559 | * @param Pull This parameter can be one of the following values: |
| 560 | * @param Pull This parameter can be one of the following values: |
560 | * @arg @ref LL_GPIO_PULL_DOWN |
| 561 | * @arg @ref LL_GPIO_PULL_DOWN |
561 | * @arg @ref LL_GPIO_PULL_UP |
| 562 | * @arg @ref LL_GPIO_PULL_UP |
562 | * @retval None |
| 563 | * @retval None |
563 | */ |
| 564 | */ |
564 | __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) |
| 565 | __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) |
565 | { |
| 566 | { |
566 | MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS))); |
| 567 | MODIFY_REG(GPIOx->ODR, (Pin >> GPIO_PIN_MASK_POS), Pull << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS))); |
567 | } |
| 568 | } |
568 | |
| 569 | 569 | /** |
|
| 570 | /** |
570 | * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port |
| 571 | * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port |
571 | * @note Warning: only one pin can be passed as parameter. |
| 572 | * @note Warning: only one pin can be passed as parameter. |
572 | * @rmtoll ODR ODR LL_GPIO_GetPinPull |
| 573 | * @rmtoll ODR ODR LL_GPIO_GetPinPull |
573 | * @param GPIOx GPIO Port |
| 574 | * @param GPIOx GPIO Port |
574 | * @param Pin This parameter can be one of the following values: |
| 575 | * @param Pin This parameter can be one of the following values: |
575 | * @arg @ref LL_GPIO_PIN_0 |
| 576 | * @arg @ref LL_GPIO_PIN_0 |
576 | * @arg @ref LL_GPIO_PIN_1 |
| 577 | * @arg @ref LL_GPIO_PIN_1 |
577 | * @arg @ref LL_GPIO_PIN_2 |
| 578 | * @arg @ref LL_GPIO_PIN_2 |
578 | * @arg @ref LL_GPIO_PIN_3 |
| 579 | * @arg @ref LL_GPIO_PIN_3 |
579 | * @arg @ref LL_GPIO_PIN_4 |
| 580 | * @arg @ref LL_GPIO_PIN_4 |
580 | * @arg @ref LL_GPIO_PIN_5 |
| 581 | * @arg @ref LL_GPIO_PIN_5 |
581 | * @arg @ref LL_GPIO_PIN_6 |
| 582 | * @arg @ref LL_GPIO_PIN_6 |
582 | * @arg @ref LL_GPIO_PIN_7 |
| 583 | * @arg @ref LL_GPIO_PIN_7 |
583 | * @arg @ref LL_GPIO_PIN_8 |
| 584 | * @arg @ref LL_GPIO_PIN_8 |
584 | * @arg @ref LL_GPIO_PIN_9 |
| 585 | * @arg @ref LL_GPIO_PIN_9 |
585 | * @arg @ref LL_GPIO_PIN_10 |
| 586 | * @arg @ref LL_GPIO_PIN_10 |
586 | * @arg @ref LL_GPIO_PIN_11 |
| 587 | * @arg @ref LL_GPIO_PIN_11 |
587 | * @arg @ref LL_GPIO_PIN_12 |
| 588 | * @arg @ref LL_GPIO_PIN_12 |
588 | * @arg @ref LL_GPIO_PIN_13 |
| 589 | * @arg @ref LL_GPIO_PIN_13 |
589 | * @arg @ref LL_GPIO_PIN_14 |
| 590 | * @arg @ref LL_GPIO_PIN_14 |
590 | * @arg @ref LL_GPIO_PIN_15 |
| 591 | * @arg @ref LL_GPIO_PIN_15 |
591 | * @retval Returned value can be one of the following values: |
| 592 | * @retval Returned value can be one of the following values: |
592 | * @arg @ref LL_GPIO_PULL_DOWN |
| 593 | * @arg @ref LL_GPIO_PULL_DOWN |
593 | * @arg @ref LL_GPIO_PULL_UP |
| 594 | * @arg @ref LL_GPIO_PULL_UP |
594 | */ |
| 595 | */ |
595 | __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) |
| 596 | __STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) |
596 | { |
| 597 | { |
597 | return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS))); |
| 598 | return (READ_BIT(GPIOx->ODR, (GPIO_ODR_ODR0 << (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS)))) >> (POSITION_VAL(Pin >> GPIO_PIN_MASK_POS))); |
598 | } |
| 599 | } |
599 | |
| 600 | 600 | /** |
|
| 601 | /** |
601 | * @brief Lock configuration of several pins for a dedicated port. |
| 602 | * @brief Lock configuration of several pins for a dedicated port. |
602 | * @note When the lock sequence has been applied on a port bit, the |
| 603 | * @note When the lock sequence has been applied on a port bit, the |
603 | * value of this port bit can no longer be modified until the |
| 604 | * value of this port bit can no longer be modified until the |
604 | * next reset. |
| 605 | * next reset. |
605 | * @note Each lock bit freezes a specific configuration register |
| 606 | * @note Each lock bit freezes a specific configuration register |
606 | * (control and alternate function registers). |
| 607 | * (control and alternate function registers). |
607 | * @rmtoll LCKR LCKK LL_GPIO_LockPin |
| 608 | * @rmtoll LCKR LCKK LL_GPIO_LockPin |
608 | * @param GPIOx GPIO Port |
| 609 | * @param GPIOx GPIO Port |
609 | * @param PinMask This parameter can be a combination of the following values: |
| 610 | * @param PinMask This parameter can be a combination of the following values: |
610 | * @arg @ref LL_GPIO_PIN_0 |
| 611 | * @arg @ref LL_GPIO_PIN_0 |
611 | * @arg @ref LL_GPIO_PIN_1 |
| 612 | * @arg @ref LL_GPIO_PIN_1 |
612 | * @arg @ref LL_GPIO_PIN_2 |
| 613 | * @arg @ref LL_GPIO_PIN_2 |
613 | * @arg @ref LL_GPIO_PIN_3 |
| 614 | * @arg @ref LL_GPIO_PIN_3 |
614 | * @arg @ref LL_GPIO_PIN_4 |
| 615 | * @arg @ref LL_GPIO_PIN_4 |
615 | * @arg @ref LL_GPIO_PIN_5 |
| 616 | * @arg @ref LL_GPIO_PIN_5 |
616 | * @arg @ref LL_GPIO_PIN_6 |
| 617 | * @arg @ref LL_GPIO_PIN_6 |
617 | * @arg @ref LL_GPIO_PIN_7 |
| 618 | * @arg @ref LL_GPIO_PIN_7 |
618 | * @arg @ref LL_GPIO_PIN_8 |
| 619 | * @arg @ref LL_GPIO_PIN_8 |
619 | * @arg @ref LL_GPIO_PIN_9 |
| 620 | * @arg @ref LL_GPIO_PIN_9 |
620 | * @arg @ref LL_GPIO_PIN_10 |
| 621 | * @arg @ref LL_GPIO_PIN_10 |
621 | * @arg @ref LL_GPIO_PIN_11 |
| 622 | * @arg @ref LL_GPIO_PIN_11 |
622 | * @arg @ref LL_GPIO_PIN_12 |
| 623 | * @arg @ref LL_GPIO_PIN_12 |
623 | * @arg @ref LL_GPIO_PIN_13 |
| 624 | * @arg @ref LL_GPIO_PIN_13 |
624 | * @arg @ref LL_GPIO_PIN_14 |
| 625 | * @arg @ref LL_GPIO_PIN_14 |
625 | * @arg @ref LL_GPIO_PIN_15 |
| 626 | * @arg @ref LL_GPIO_PIN_15 |
626 | * @arg @ref LL_GPIO_PIN_ALL |
| 627 | * @arg @ref LL_GPIO_PIN_ALL |
627 | * @retval None |
| 628 | * @retval None |
628 | */ |
| 629 | */ |
629 | __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
| 630 | __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
630 | { |
| 631 | { |
631 | __IO uint32_t temp; |
| 632 | __IO uint32_t temp; |
632 | WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
| 633 | WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
633 | WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
| 634 | WRITE_REG(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
634 | WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
| 635 | WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
635 | temp = READ_REG(GPIOx->LCKR); |
| 636 | temp = READ_REG(GPIOx->LCKR); |
636 | (void) temp; |
| 637 | (void) temp; |
637 | } |
| 638 | } |
638 | |
| 639 | 639 | /** |
|
| 640 | /** |
640 | * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. |
| 641 | * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. |
641 | * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked |
| 642 | * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked |
642 | * @param GPIOx GPIO Port |
| 643 | * @param GPIOx GPIO Port |
643 | * @param PinMask This parameter can be a combination of the following values: |
| 644 | * @param PinMask This parameter can be a combination of the following values: |
644 | * @arg @ref LL_GPIO_PIN_0 |
| 645 | * @arg @ref LL_GPIO_PIN_0 |
645 | * @arg @ref LL_GPIO_PIN_1 |
| 646 | * @arg @ref LL_GPIO_PIN_1 |
646 | * @arg @ref LL_GPIO_PIN_2 |
| 647 | * @arg @ref LL_GPIO_PIN_2 |
647 | * @arg @ref LL_GPIO_PIN_3 |
| 648 | * @arg @ref LL_GPIO_PIN_3 |
648 | * @arg @ref LL_GPIO_PIN_4 |
| 649 | * @arg @ref LL_GPIO_PIN_4 |
649 | * @arg @ref LL_GPIO_PIN_5 |
| 650 | * @arg @ref LL_GPIO_PIN_5 |
650 | * @arg @ref LL_GPIO_PIN_6 |
| 651 | * @arg @ref LL_GPIO_PIN_6 |
651 | * @arg @ref LL_GPIO_PIN_7 |
| 652 | * @arg @ref LL_GPIO_PIN_7 |
652 | * @arg @ref LL_GPIO_PIN_8 |
| 653 | * @arg @ref LL_GPIO_PIN_8 |
653 | * @arg @ref LL_GPIO_PIN_9 |
| 654 | * @arg @ref LL_GPIO_PIN_9 |
654 | * @arg @ref LL_GPIO_PIN_10 |
| 655 | * @arg @ref LL_GPIO_PIN_10 |
655 | * @arg @ref LL_GPIO_PIN_11 |
| 656 | * @arg @ref LL_GPIO_PIN_11 |
656 | * @arg @ref LL_GPIO_PIN_12 |
| 657 | * @arg @ref LL_GPIO_PIN_12 |
657 | * @arg @ref LL_GPIO_PIN_13 |
| 658 | * @arg @ref LL_GPIO_PIN_13 |
658 | * @arg @ref LL_GPIO_PIN_14 |
| 659 | * @arg @ref LL_GPIO_PIN_14 |
659 | * @arg @ref LL_GPIO_PIN_15 |
| 660 | * @arg @ref LL_GPIO_PIN_15 |
660 | * @arg @ref LL_GPIO_PIN_ALL |
| 661 | * @arg @ref LL_GPIO_PIN_ALL |
661 | * @retval State of bit (1 or 0). |
| 662 | * @retval State of bit (1 or 0). |
662 | */ |
| 663 | */ |
663 | __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
| 664 | __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
664 | { |
| 665 | { |
665 | return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
| 666 | return (READ_BIT(GPIOx->LCKR, ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
666 | } |
| 667 | } |
667 | |
| 668 | 668 | /** |
|
| 669 | /** |
669 | * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. |
| 670 | * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. |
670 | * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked |
| 671 | * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked |
671 | * @param GPIOx GPIO Port |
| 672 | * @param GPIOx GPIO Port |
672 | * @retval State of bit (1 or 0). |
| 673 | * @retval State of bit (1 or 0). |
673 | */ |
| 674 | */ |
674 | __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) |
| 675 | __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) |
675 | { |
| 676 | { |
676 | return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); |
| 677 | return (READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)); |
677 | } |
| 678 | } |
678 | |
| 679 | 679 | /** |
|
| 680 | /** |
680 | * @} |
| 681 | * @} |
681 | */ |
| 682 | */ |
682 | |
| 683 | 683 | /** @defgroup GPIO_LL_EF_Data_Access Data Access |
|
| 684 | /** @defgroup GPIO_LL_EF_Data_Access Data Access |
684 | * @{ |
| 685 | * @{ |
685 | */ |
| 686 | */ |
686 | |
| 687 | 687 | /** |
|
| 688 | /** |
688 | * @brief Return full input data register value for a dedicated port. |
| 689 | * @brief Return full input data register value for a dedicated port. |
689 | * @rmtoll IDR IDy LL_GPIO_ReadInputPort |
| 690 | * @rmtoll IDR IDy LL_GPIO_ReadInputPort |
690 | * @param GPIOx GPIO Port |
| 691 | * @param GPIOx GPIO Port |
691 | * @retval Input data register value of port |
| 692 | * @retval Input data register value of port |
692 | */ |
| 693 | */ |
693 | __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) |
| 694 | __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) |
694 | { |
| 695 | { |
695 | return (READ_REG(GPIOx->IDR)); |
| 696 | return (READ_REG(GPIOx->IDR)); |
696 | } |
| 697 | } |
697 | |
| 698 | 698 | /** |
|
| 699 | /** |
699 | * @brief Return if input data level for several pins of dedicated port is high or low. |
| 700 | * @brief Return if input data level for several pins of dedicated port is high or low. |
700 | * @rmtoll IDR IDy LL_GPIO_IsInputPinSet |
| 701 | * @rmtoll IDR IDy LL_GPIO_IsInputPinSet |
701 | * @param GPIOx GPIO Port |
| 702 | * @param GPIOx GPIO Port |
702 | * @param PinMask This parameter can be a combination of the following values: |
| 703 | * @param PinMask This parameter can be a combination of the following values: |
703 | * @arg @ref LL_GPIO_PIN_0 |
| 704 | * @arg @ref LL_GPIO_PIN_0 |
704 | * @arg @ref LL_GPIO_PIN_1 |
| 705 | * @arg @ref LL_GPIO_PIN_1 |
705 | * @arg @ref LL_GPIO_PIN_2 |
| 706 | * @arg @ref LL_GPIO_PIN_2 |
706 | * @arg @ref LL_GPIO_PIN_3 |
| 707 | * @arg @ref LL_GPIO_PIN_3 |
707 | * @arg @ref LL_GPIO_PIN_4 |
| 708 | * @arg @ref LL_GPIO_PIN_4 |
708 | * @arg @ref LL_GPIO_PIN_5 |
| 709 | * @arg @ref LL_GPIO_PIN_5 |
709 | * @arg @ref LL_GPIO_PIN_6 |
| 710 | * @arg @ref LL_GPIO_PIN_6 |
710 | * @arg @ref LL_GPIO_PIN_7 |
| 711 | * @arg @ref LL_GPIO_PIN_7 |
711 | * @arg @ref LL_GPIO_PIN_8 |
| 712 | * @arg @ref LL_GPIO_PIN_8 |
712 | * @arg @ref LL_GPIO_PIN_9 |
| 713 | * @arg @ref LL_GPIO_PIN_9 |
713 | * @arg @ref LL_GPIO_PIN_10 |
| 714 | * @arg @ref LL_GPIO_PIN_10 |
714 | * @arg @ref LL_GPIO_PIN_11 |
| 715 | * @arg @ref LL_GPIO_PIN_11 |
715 | * @arg @ref LL_GPIO_PIN_12 |
| 716 | * @arg @ref LL_GPIO_PIN_12 |
716 | * @arg @ref LL_GPIO_PIN_13 |
| 717 | * @arg @ref LL_GPIO_PIN_13 |
717 | * @arg @ref LL_GPIO_PIN_14 |
| 718 | * @arg @ref LL_GPIO_PIN_14 |
718 | * @arg @ref LL_GPIO_PIN_15 |
| 719 | * @arg @ref LL_GPIO_PIN_15 |
719 | * @arg @ref LL_GPIO_PIN_ALL |
| 720 | * @arg @ref LL_GPIO_PIN_ALL |
720 | * @retval State of bit (1 or 0). |
| 721 | * @retval State of bit (1 or 0). |
721 | */ |
| 722 | */ |
722 | __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
| 723 | __STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
723 | { |
| 724 | { |
724 | return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
| 725 | return (READ_BIT(GPIOx->IDR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
725 | } |
| 726 | } |
726 | |
| 727 | 727 | /** |
|
| 728 | /** |
728 | * @brief Write output data register for the port. |
| 729 | * @brief Write output data register for the port. |
729 | * @rmtoll ODR ODy LL_GPIO_WriteOutputPort |
| 730 | * @rmtoll ODR ODy LL_GPIO_WriteOutputPort |
730 | * @param GPIOx GPIO Port |
| 731 | * @param GPIOx GPIO Port |
731 | * @param PortValue Level value for each pin of the port |
| 732 | * @param PortValue Level value for each pin of the port |
732 | * @retval None |
| 733 | * @retval None |
733 | */ |
| 734 | */ |
734 | __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) |
| 735 | __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) |
735 | { |
| 736 | { |
736 | WRITE_REG(GPIOx->ODR, PortValue); |
| 737 | WRITE_REG(GPIOx->ODR, PortValue); |
737 | } |
| 738 | } |
738 | |
| 739 | 739 | /** |
|
| 740 | /** |
740 | * @brief Return full output data register value for a dedicated port. |
| 741 | * @brief Return full output data register value for a dedicated port. |
741 | * @rmtoll ODR ODy LL_GPIO_ReadOutputPort |
| 742 | * @rmtoll ODR ODy LL_GPIO_ReadOutputPort |
742 | * @param GPIOx GPIO Port |
| 743 | * @param GPIOx GPIO Port |
743 | * @retval Output data register value of port |
| 744 | * @retval Output data register value of port |
744 | */ |
| 745 | */ |
745 | __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) |
| 746 | __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) |
746 | { |
| 747 | { |
747 | return (uint32_t)(READ_REG(GPIOx->ODR)); |
| 748 | return (uint32_t)(READ_REG(GPIOx->ODR)); |
748 | } |
| 749 | } |
749 | |
| 750 | 750 | /** |
|
| 751 | /** |
751 | * @brief Return if input data level for several pins of dedicated port is high or low. |
| 752 | * @brief Return if input data level for several pins of dedicated port is high or low. |
752 | * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet |
| 753 | * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet |
753 | * @param GPIOx GPIO Port |
| 754 | * @param GPIOx GPIO Port |
754 | * @param PinMask This parameter can be a combination of the following values: |
| 755 | * @param PinMask This parameter can be a combination of the following values: |
755 | * @arg @ref LL_GPIO_PIN_0 |
| 756 | * @arg @ref LL_GPIO_PIN_0 |
756 | * @arg @ref LL_GPIO_PIN_1 |
| 757 | * @arg @ref LL_GPIO_PIN_1 |
757 | * @arg @ref LL_GPIO_PIN_2 |
| 758 | * @arg @ref LL_GPIO_PIN_2 |
758 | * @arg @ref LL_GPIO_PIN_3 |
| 759 | * @arg @ref LL_GPIO_PIN_3 |
759 | * @arg @ref LL_GPIO_PIN_4 |
| 760 | * @arg @ref LL_GPIO_PIN_4 |
760 | * @arg @ref LL_GPIO_PIN_5 |
| 761 | * @arg @ref LL_GPIO_PIN_5 |
761 | * @arg @ref LL_GPIO_PIN_6 |
| 762 | * @arg @ref LL_GPIO_PIN_6 |
762 | * @arg @ref LL_GPIO_PIN_7 |
| 763 | * @arg @ref LL_GPIO_PIN_7 |
763 | * @arg @ref LL_GPIO_PIN_8 |
| 764 | * @arg @ref LL_GPIO_PIN_8 |
764 | * @arg @ref LL_GPIO_PIN_9 |
| 765 | * @arg @ref LL_GPIO_PIN_9 |
765 | * @arg @ref LL_GPIO_PIN_10 |
| 766 | * @arg @ref LL_GPIO_PIN_10 |
766 | * @arg @ref LL_GPIO_PIN_11 |
| 767 | * @arg @ref LL_GPIO_PIN_11 |
767 | * @arg @ref LL_GPIO_PIN_12 |
| 768 | * @arg @ref LL_GPIO_PIN_12 |
768 | * @arg @ref LL_GPIO_PIN_13 |
| 769 | * @arg @ref LL_GPIO_PIN_13 |
769 | * @arg @ref LL_GPIO_PIN_14 |
| 770 | * @arg @ref LL_GPIO_PIN_14 |
770 | * @arg @ref LL_GPIO_PIN_15 |
| 771 | * @arg @ref LL_GPIO_PIN_15 |
771 | * @arg @ref LL_GPIO_PIN_ALL |
| 772 | * @arg @ref LL_GPIO_PIN_ALL |
772 | * @retval State of bit (1 or 0). |
| 773 | * @retval State of bit (1 or 0). |
773 | */ |
| 774 | */ |
774 | __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
| 775 | __STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
775 | { |
| 776 | { |
776 | return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
| 777 | return (READ_BIT(GPIOx->ODR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU) == ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU)); |
777 | } |
| 778 | } |
778 | |
| 779 | 779 | /** |
|
| 780 | /** |
780 | * @brief Set several pins to high level on dedicated gpio port. |
| 781 | * @brief Set several pins to high level on dedicated gpio port. |
781 | * @rmtoll BSRR BSy LL_GPIO_SetOutputPin |
| 782 | * @rmtoll BSRR BSy LL_GPIO_SetOutputPin |
782 | * @param GPIOx GPIO Port |
| 783 | * @param GPIOx GPIO Port |
783 | * @param PinMask This parameter can be a combination of the following values: |
| 784 | * @param PinMask This parameter can be a combination of the following values: |
784 | * @arg @ref LL_GPIO_PIN_0 |
| 785 | * @arg @ref LL_GPIO_PIN_0 |
785 | * @arg @ref LL_GPIO_PIN_1 |
| 786 | * @arg @ref LL_GPIO_PIN_1 |
786 | * @arg @ref LL_GPIO_PIN_2 |
| 787 | * @arg @ref LL_GPIO_PIN_2 |
787 | * @arg @ref LL_GPIO_PIN_3 |
| 788 | * @arg @ref LL_GPIO_PIN_3 |
788 | * @arg @ref LL_GPIO_PIN_4 |
| 789 | * @arg @ref LL_GPIO_PIN_4 |
789 | * @arg @ref LL_GPIO_PIN_5 |
| 790 | * @arg @ref LL_GPIO_PIN_5 |
790 | * @arg @ref LL_GPIO_PIN_6 |
| 791 | * @arg @ref LL_GPIO_PIN_6 |
791 | * @arg @ref LL_GPIO_PIN_7 |
| 792 | * @arg @ref LL_GPIO_PIN_7 |
792 | * @arg @ref LL_GPIO_PIN_8 |
| 793 | * @arg @ref LL_GPIO_PIN_8 |
793 | * @arg @ref LL_GPIO_PIN_9 |
| 794 | * @arg @ref LL_GPIO_PIN_9 |
794 | * @arg @ref LL_GPIO_PIN_10 |
| 795 | * @arg @ref LL_GPIO_PIN_10 |
795 | * @arg @ref LL_GPIO_PIN_11 |
| 796 | * @arg @ref LL_GPIO_PIN_11 |
796 | * @arg @ref LL_GPIO_PIN_12 |
| 797 | * @arg @ref LL_GPIO_PIN_12 |
797 | * @arg @ref LL_GPIO_PIN_13 |
| 798 | * @arg @ref LL_GPIO_PIN_13 |
798 | * @arg @ref LL_GPIO_PIN_14 |
| 799 | * @arg @ref LL_GPIO_PIN_14 |
799 | * @arg @ref LL_GPIO_PIN_15 |
| 800 | * @arg @ref LL_GPIO_PIN_15 |
800 | * @arg @ref LL_GPIO_PIN_ALL |
| 801 | * @arg @ref LL_GPIO_PIN_ALL |
801 | * @retval None |
| 802 | * @retval None |
802 | */ |
| 803 | */ |
803 | __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
| 804 | __STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
804 | { |
| 805 | { |
805 | WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); |
| 806 | WRITE_REG(GPIOx->BSRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); |
806 | } |
| 807 | } |
807 | |
| 808 | 808 | /** |
|
| 809 | /** |
809 | * @brief Set several pins to low level on dedicated gpio port. |
| 810 | * @brief Set several pins to low level on dedicated gpio port. |
810 | * @rmtoll BRR BRy LL_GPIO_ResetOutputPin |
| 811 | * @rmtoll BRR BRy LL_GPIO_ResetOutputPin |
811 | * @param GPIOx GPIO Port |
| 812 | * @param GPIOx GPIO Port |
812 | * @param PinMask This parameter can be a combination of the following values: |
| 813 | * @param PinMask This parameter can be a combination of the following values: |
813 | * @arg @ref LL_GPIO_PIN_0 |
| 814 | * @arg @ref LL_GPIO_PIN_0 |
814 | * @arg @ref LL_GPIO_PIN_1 |
| 815 | * @arg @ref LL_GPIO_PIN_1 |
815 | * @arg @ref LL_GPIO_PIN_2 |
| 816 | * @arg @ref LL_GPIO_PIN_2 |
816 | * @arg @ref LL_GPIO_PIN_3 |
| 817 | * @arg @ref LL_GPIO_PIN_3 |
817 | * @arg @ref LL_GPIO_PIN_4 |
| 818 | * @arg @ref LL_GPIO_PIN_4 |
818 | * @arg @ref LL_GPIO_PIN_5 |
| 819 | * @arg @ref LL_GPIO_PIN_5 |
819 | * @arg @ref LL_GPIO_PIN_6 |
| 820 | * @arg @ref LL_GPIO_PIN_6 |
820 | * @arg @ref LL_GPIO_PIN_7 |
| 821 | * @arg @ref LL_GPIO_PIN_7 |
821 | * @arg @ref LL_GPIO_PIN_8 |
| 822 | * @arg @ref LL_GPIO_PIN_8 |
822 | * @arg @ref LL_GPIO_PIN_9 |
| 823 | * @arg @ref LL_GPIO_PIN_9 |
823 | * @arg @ref LL_GPIO_PIN_10 |
| 824 | * @arg @ref LL_GPIO_PIN_10 |
824 | * @arg @ref LL_GPIO_PIN_11 |
| 825 | * @arg @ref LL_GPIO_PIN_11 |
825 | * @arg @ref LL_GPIO_PIN_12 |
| 826 | * @arg @ref LL_GPIO_PIN_12 |
826 | * @arg @ref LL_GPIO_PIN_13 |
| 827 | * @arg @ref LL_GPIO_PIN_13 |
827 | * @arg @ref LL_GPIO_PIN_14 |
| 828 | * @arg @ref LL_GPIO_PIN_14 |
828 | * @arg @ref LL_GPIO_PIN_15 |
| 829 | * @arg @ref LL_GPIO_PIN_15 |
829 | * @arg @ref LL_GPIO_PIN_ALL |
| 830 | * @arg @ref LL_GPIO_PIN_ALL |
830 | * @retval None |
| 831 | * @retval None |
831 | */ |
| 832 | */ |
832 | __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
| 833 | __STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
833 | { |
| 834 | { |
834 | WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); |
| 835 | WRITE_REG(GPIOx->BRR, (PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); |
835 | } |
| 836 | } |
836 | |
| 837 | 837 | /** |
|
| 838 | /** |
838 | * @brief Toggle data value for several pin of dedicated port. |
| 839 | * @brief Toggle data value for several pin of dedicated port. |
839 | * @rmtoll ODR ODy LL_GPIO_TogglePin |
| 840 | * @rmtoll ODR ODy LL_GPIO_TogglePin |
840 | * @param GPIOx GPIO Port |
| 841 | * @param GPIOx GPIO Port |
841 | * @param PinMask This parameter can be a combination of the following values: |
| 842 | * @param PinMask This parameter can be a combination of the following values: |
842 | * @arg @ref LL_GPIO_PIN_0 |
| 843 | * @arg @ref LL_GPIO_PIN_0 |
843 | * @arg @ref LL_GPIO_PIN_1 |
| 844 | * @arg @ref LL_GPIO_PIN_1 |
844 | * @arg @ref LL_GPIO_PIN_2 |
| 845 | * @arg @ref LL_GPIO_PIN_2 |
845 | * @arg @ref LL_GPIO_PIN_3 |
| 846 | * @arg @ref LL_GPIO_PIN_3 |
846 | * @arg @ref LL_GPIO_PIN_4 |
| 847 | * @arg @ref LL_GPIO_PIN_4 |
847 | * @arg @ref LL_GPIO_PIN_5 |
| 848 | * @arg @ref LL_GPIO_PIN_5 |
848 | * @arg @ref LL_GPIO_PIN_6 |
| 849 | * @arg @ref LL_GPIO_PIN_6 |
849 | * @arg @ref LL_GPIO_PIN_7 |
| 850 | * @arg @ref LL_GPIO_PIN_7 |
850 | * @arg @ref LL_GPIO_PIN_8 |
| 851 | * @arg @ref LL_GPIO_PIN_8 |
851 | * @arg @ref LL_GPIO_PIN_9 |
| 852 | * @arg @ref LL_GPIO_PIN_9 |
852 | * @arg @ref LL_GPIO_PIN_10 |
| 853 | * @arg @ref LL_GPIO_PIN_10 |
853 | * @arg @ref LL_GPIO_PIN_11 |
| 854 | * @arg @ref LL_GPIO_PIN_11 |
854 | * @arg @ref LL_GPIO_PIN_12 |
| 855 | * @arg @ref LL_GPIO_PIN_12 |
855 | * @arg @ref LL_GPIO_PIN_13 |
| 856 | * @arg @ref LL_GPIO_PIN_13 |
856 | * @arg @ref LL_GPIO_PIN_14 |
| 857 | * @arg @ref LL_GPIO_PIN_14 |
857 | * @arg @ref LL_GPIO_PIN_15 |
| 858 | * @arg @ref LL_GPIO_PIN_15 |
858 | * @arg @ref LL_GPIO_PIN_ALL |
| 859 | * @arg @ref LL_GPIO_PIN_ALL |
859 | * @retval None |
| 860 | * @retval None |
860 | */ |
| 861 | */ |
861 | __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
| 862 | __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) |
862 | { |
| 863 | { |
863 | uint32_t odr = READ_REG(GPIOx->ODR); |
| 864 | uint32_t odr = READ_REG(GPIOx->ODR); |
864 | uint32_t pinmask = ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); |
| 865 | uint32_t pinmask = ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU); |
865 | WRITE_REG(GPIOx->BSRR, ((odr & pinmask) << 16u) | (~odr & pinmask)); |
| 866 | WRITE_REG(GPIOx->BSRR, ((odr & pinmask) << 16u) | (~odr & pinmask)); |
866 | } |
| 867 | } |
867 | |
| 868 | 868 | /** |
|
| 869 | /** |
869 | * @} |
| 870 | * @} |
870 | */ |
| 871 | */ |
871 | |
| 872 | 872 | /** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping |
|
| 873 | /** @defgroup GPIO_AF_REMAPPING Alternate Function Remapping |
873 | * @brief This section propose definition to remap the alternate function to some other port/pins. |
| 874 | * @brief This section propose definition to remap the alternate function to some other port/pins. |
874 | * @{ |
| 875 | * @{ |
875 | */ |
| 876 | */ |
876 | |
| 877 | 877 | /** |
|
| 878 | /** |
878 | * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
| 879 | * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
879 | * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1 |
| 880 | * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_EnableRemap_SPI1 |
880 | * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) |
| 881 | * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) |
881 | * @retval None |
| 882 | * @retval None |
882 | */ |
| 883 | */ |
883 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void) |
| 884 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void) |
884 | { |
| 885 | { |
885 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG); |
| 886 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG); |
886 | } |
| 887 | } |
887 | |
| 888 | 888 | /** |
|
| 889 | /** |
889 | * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
| 890 | * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
890 | * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1 |
| 891 | * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_DisableRemap_SPI1 |
891 | * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) |
| 892 | * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) |
892 | * @retval None |
| 893 | * @retval None |
893 | */ |
| 894 | */ |
894 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void) |
| 895 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void) |
895 | { |
| 896 | { |
896 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 897 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
897 | } |
| 898 | } |
898 | |
| 899 | 899 | /** |
|
| 900 | /** |
900 | * @brief Check if SPI1 has been remapped or not |
| 901 | * @brief Check if SPI1 has been remaped or not |
901 | * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1 |
| 902 | * @rmtoll MAPR SPI1_REMAP LL_GPIO_AF_IsEnabledRemap_SPI1 |
902 | * @retval State of bit (1 or 0). |
| 903 | * @retval State of bit (1 or 0). |
903 | */ |
| 904 | */ |
904 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void) |
| 905 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI1(void) |
905 | { |
| 906 | { |
906 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP)); |
| 907 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP) == (AFIO_MAPR_SPI1_REMAP)); |
907 | } |
| 908 | } |
908 | |
| 909 | 909 | /** |
|
| 910 | /** |
910 | * @brief Enable the remapping of I2C1 alternate function SCL and SDA. |
| 911 | * @brief Enable the remapping of I2C1 alternate function SCL and SDA. |
911 | * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1 |
| 912 | * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_EnableRemap_I2C1 |
912 | * @note ENABLE: Remap (SCL/PB8, SDA/PB9) |
| 913 | * @note ENABLE: Remap (SCL/PB8, SDA/PB9) |
913 | * @retval None |
| 914 | * @retval None |
914 | */ |
| 915 | */ |
915 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void) |
| 916 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void) |
916 | { |
| 917 | { |
917 | SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG); |
| 918 | SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG); |
918 | } |
| 919 | } |
919 | |
| 920 | 920 | /** |
|
| 921 | /** |
921 | * @brief Disable the remapping of I2C1 alternate function SCL and SDA. |
| 922 | * @brief Disable the remapping of I2C1 alternate function SCL and SDA. |
922 | * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1 |
| 923 | * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_DisableRemap_I2C1 |
923 | * @note DISABLE: No remap (SCL/PB6, SDA/PB7) |
| 924 | * @note DISABLE: No remap (SCL/PB6, SDA/PB7) |
924 | * @retval None |
| 925 | * @retval None |
925 | */ |
| 926 | */ |
926 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void) |
| 927 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void) |
927 | { |
| 928 | { |
928 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 929 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
929 | } |
| 930 | } |
930 | |
| 931 | 931 | /** |
|
| 932 | /** |
932 | * @brief Check if I2C1 has been remapped or not |
| 933 | * @brief Check if I2C1 has been remaped or not |
933 | * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1 |
| 934 | * @rmtoll MAPR I2C1_REMAP LL_GPIO_AF_IsEnabledRemap_I2C1 |
934 | * @retval State of bit (1 or 0). |
| 935 | * @retval State of bit (1 or 0). |
935 | */ |
| 936 | */ |
936 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void) |
| 937 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_I2C1(void) |
937 | { |
| 938 | { |
938 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP)); |
| 939 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP) == (AFIO_MAPR_I2C1_REMAP)); |
939 | } |
| 940 | } |
940 | |
| 941 | 941 | /** |
|
| 942 | /** |
942 | * @brief Enable the remapping of USART1 alternate function TX and RX. |
| 943 | * @brief Enable the remapping of USART1 alternate function TX and RX. |
943 | * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1 |
| 944 | * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_EnableRemap_USART1 |
944 | * @note ENABLE: Remap (TX/PB6, RX/PB7) |
| 945 | * @note ENABLE: Remap (TX/PB6, RX/PB7) |
945 | * @retval None |
| 946 | * @retval None |
946 | */ |
| 947 | */ |
947 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void) |
| 948 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void) |
948 | { |
| 949 | { |
949 | SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG); |
| 950 | SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG); |
950 | } |
| 951 | } |
951 | |
| 952 | 952 | /** |
|
| 953 | /** |
953 | * @brief Disable the remapping of USART1 alternate function TX and RX. |
| 954 | * @brief Disable the remapping of USART1 alternate function TX and RX. |
954 | * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1 |
| 955 | * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_DisableRemap_USART1 |
955 | * @note DISABLE: No remap (TX/PA9, RX/PA10) |
| 956 | * @note DISABLE: No remap (TX/PA9, RX/PA10) |
956 | * @retval None |
| 957 | * @retval None |
957 | */ |
| 958 | */ |
958 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void) |
| 959 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void) |
959 | { |
| 960 | { |
960 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 961 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
961 | } |
| 962 | } |
962 | |
| 963 | 963 | /** |
|
| 964 | /** |
964 | * @brief Check if USART1 has been remapped or not |
| 965 | * @brief Check if USART1 has been remaped or not |
965 | * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1 |
| 966 | * @rmtoll MAPR USART1_REMAP LL_GPIO_AF_IsEnabledRemap_USART1 |
966 | * @retval State of bit (1 or 0). |
| 967 | * @retval State of bit (1 or 0). |
967 | */ |
| 968 | */ |
968 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void) |
| 969 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART1(void) |
969 | { |
| 970 | { |
970 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP)); |
| 971 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP) == (AFIO_MAPR_USART1_REMAP)); |
971 | } |
| 972 | } |
972 | |
| 973 | 973 | /** |
|
| 974 | /** |
974 | * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
| 975 | * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
975 | * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2 |
| 976 | * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_EnableRemap_USART2 |
976 | * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) |
| 977 | * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) |
977 | * @retval None |
| 978 | * @retval None |
978 | */ |
| 979 | */ |
979 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void) |
| 980 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void) |
980 | { |
| 981 | { |
981 | SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG); |
| 982 | SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG); |
982 | } |
| 983 | } |
983 | |
| 984 | 984 | /** |
|
| 985 | /** |
985 | * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
| 986 | * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
986 | * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2 |
| 987 | * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_DisableRemap_USART2 |
987 | * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) |
| 988 | * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) |
988 | * @retval None |
| 989 | * @retval None |
989 | */ |
| 990 | */ |
990 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void) |
| 991 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void) |
991 | { |
| 992 | { |
992 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 993 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
993 | } |
| 994 | } |
994 | |
| 995 | 995 | /** |
|
| 996 | /** |
996 | * @brief Check if USART2 has been remapped or not |
| 997 | * @brief Check if USART2 has been remaped or not |
997 | * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2 |
| 998 | * @rmtoll MAPR USART2_REMAP LL_GPIO_AF_IsEnabledRemap_USART2 |
998 | * @retval State of bit (1 or 0). |
| 999 | * @retval State of bit (1 or 0). |
999 | */ |
| 1000 | */ |
1000 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void) |
| 1001 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_USART2(void) |
1001 | { |
| 1002 | { |
1002 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP)); |
| 1003 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP) == (AFIO_MAPR_USART2_REMAP)); |
1003 | } |
| 1004 | } |
1004 | |
| 1005 | 1005 | #if defined (AFIO_MAPR_USART3_REMAP) |
|
| 1006 | #if defined (AFIO_MAPR_USART3_REMAP) |
1006 | /** |
| 1007 | /** |
1007 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| 1008 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
1008 | * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3 |
| 1009 | * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_EnableRemap_USART3 |
1009 | * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) |
| 1010 | * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) |
1010 | * @retval None |
| 1011 | * @retval None |
1011 | */ |
| 1012 | */ |
1012 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void) |
| 1013 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void) |
1013 | { |
| 1014 | { |
1014 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
| 1015 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
1015 | } |
| 1016 | } |
1016 | |
| 1017 | 1017 | /** |
|
| 1018 | /** |
1018 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| 1019 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
1019 | * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3 |
| 1020 | * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_RemapPartial_USART3 |
1020 | * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) |
| 1021 | * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) |
1021 | * @retval None |
| 1022 | * @retval None |
1022 | */ |
| 1023 | */ |
1023 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void) |
| 1024 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void) |
1024 | { |
| 1025 | { |
1025 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); |
| 1026 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); |
1026 | } |
| 1027 | } |
1027 | |
| 1028 | 1028 | /** |
|
| 1029 | /** |
1029 | * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| 1030 | * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
1030 | * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3 |
| 1031 | * @rmtoll MAPR USART3_REMAP LL_GPIO_AF_DisableRemap_USART3 |
1031 | * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) |
| 1032 | * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) |
1032 | * @retval None |
| 1033 | * @retval None |
1033 | */ |
| 1034 | */ |
1034 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void) |
| 1035 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void) |
1035 | { |
| 1036 | { |
1036 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
| 1037 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
1037 | } |
| 1038 | } |
1038 | #endif |
| 1039 | #endif |
1039 | |
| 1040 | 1040 | /** |
|
| 1041 | /** |
1041 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| 1042 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
1042 | * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1 |
| 1043 | * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_EnableRemap_TIM1 |
1043 | * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) |
| 1044 | * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) |
1044 | * @retval None |
| 1045 | * @retval None |
1045 | */ |
| 1046 | */ |
1046 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void) |
| 1047 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void) |
1047 | { |
| 1048 | { |
1048 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
| 1049 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
1049 | } |
| 1050 | } |
1050 | |
| 1051 | 1051 | /** |
|
| 1052 | /** |
1052 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| 1053 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
1053 | * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1 |
| 1054 | * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_RemapPartial_TIM1 |
1054 | * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) |
| 1055 | * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) |
1055 | * @retval None |
| 1056 | * @retval None |
1056 | */ |
| 1057 | */ |
1057 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void) |
| 1058 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void) |
1058 | { |
| 1059 | { |
1059 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); |
| 1060 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); |
1060 | } |
| 1061 | } |
1061 | |
| 1062 | 1062 | /** |
|
| 1063 | /** |
1063 | * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| 1064 | * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
1064 | * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1 |
| 1065 | * @rmtoll MAPR TIM1_REMAP LL_GPIO_AF_DisableRemap_TIM1 |
1065 | * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) |
| 1066 | * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) |
1066 | * @retval None |
| 1067 | * @retval None |
1067 | */ |
| 1068 | */ |
1068 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void) |
| 1069 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void) |
1069 | { |
| 1070 | { |
1070 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
| 1071 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
1071 | } |
| 1072 | } |
1072 | |
| 1073 | 1073 | /** |
|
| 1074 | /** |
1074 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| 1075 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
1075 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2 |
| 1076 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_EnableRemap_TIM2 |
1076 | * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) |
| 1077 | * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) |
1077 | * @retval None |
| 1078 | * @retval None |
1078 | */ |
| 1079 | */ |
1079 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void) |
| 1080 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void) |
1080 | { |
| 1081 | { |
1081 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
| 1082 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
1082 | } |
| 1083 | } |
1083 | |
| 1084 | 1084 | /** |
|
| 1085 | /** |
1085 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| 1086 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
1086 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2 |
| 1087 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial2_TIM2 |
1087 | * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) |
| 1088 | * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) |
1088 | * @retval None |
| 1089 | * @retval None |
1089 | */ |
| 1090 | */ |
1090 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void) |
| 1091 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void) |
1091 | { |
| 1092 | { |
1092 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 | AFIO_MAPR_SWJ_CFG)); |
| 1093 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 | AFIO_MAPR_SWJ_CFG)); |
1093 | } |
| 1094 | } |
1094 | |
| 1095 | 1095 | /** |
|
| 1096 | /** |
1096 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| 1097 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
1097 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2 |
| 1098 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_RemapPartial1_TIM2 |
1098 | * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) |
| 1099 | * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) |
1099 | * @retval None |
| 1100 | * @retval None |
1100 | */ |
| 1101 | */ |
1101 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void) |
| 1102 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void) |
1102 | { |
| 1103 | { |
1103 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 | AFIO_MAPR_SWJ_CFG)); |
| 1104 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 | AFIO_MAPR_SWJ_CFG)); |
1104 | } |
| 1105 | } |
1105 | |
| 1106 | 1106 | /** |
|
| 1107 | /** |
1107 | * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| 1108 | * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
1108 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2 |
| 1109 | * @rmtoll MAPR TIM2_REMAP LL_GPIO_AF_DisableRemap_TIM2 |
1109 | * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) |
| 1110 | * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) |
1110 | * @retval None |
| 1111 | * @retval None |
1111 | */ |
| 1112 | */ |
1112 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void) |
| 1113 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void) |
1113 | { |
| 1114 | { |
1114 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
| 1115 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
1115 | } |
| 1116 | } |
1116 | |
| 1117 | 1117 | /** |
|
| 1118 | /** |
1118 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
| 1119 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
1119 | * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3 |
| 1120 | * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_EnableRemap_TIM3 |
1120 | * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) |
| 1121 | * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) |
1121 | * @note TIM3_ETR on PE0 is not re-mapped. |
| 1122 | * @note TIM3_ETR on PE0 is not re-mapped. |
1122 | * @retval None |
| 1123 | * @retval None |
1123 | */ |
| 1124 | */ |
1124 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void) |
| 1125 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void) |
1125 | { |
| 1126 | { |
1126 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
| 1127 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG)); |
1127 | } |
| 1128 | } |
1128 | |
| 1129 | 1129 | /** |
|
| 1130 | /** |
1130 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
| 1131 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
1131 | * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3 |
| 1132 | * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_RemapPartial_TIM3 |
1132 | * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) |
| 1133 | * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) |
1133 | * @note TIM3_ETR on PE0 is not re-mapped. |
| 1134 | * @note TIM3_ETR on PE0 is not re-mapped. |
1134 | * @retval None |
| 1135 | * @retval None |
1135 | */ |
| 1136 | */ |
1136 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void) |
| 1137 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void) |
1137 | { |
| 1138 | { |
1138 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); |
| 1139 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG)); |
1139 | } |
| 1140 | } |
1140 | |
| 1141 | 1141 | /** |
|
| 1142 | /** |
1142 | * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 |
| 1143 | * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 |
1143 | * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3 |
| 1144 | * @rmtoll MAPR TIM3_REMAP LL_GPIO_AF_DisableRemap_TIM3 |
1144 | * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) |
| 1145 | * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) |
1145 | * @note TIM3_ETR on PE0 is not re-mapped. |
| 1146 | * @note TIM3_ETR on PE0 is not re-mapped. |
1146 | * @retval None |
| 1147 | * @retval None |
1147 | */ |
| 1148 | */ |
1148 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void) |
| 1149 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void) |
1149 | { |
| 1150 | { |
1150 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
| 1151 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG)); |
1151 | } |
| 1152 | } |
1152 | |
| 1153 | 1153 | #if defined(AFIO_MAPR_TIM4_REMAP) |
|
| 1154 | #if defined(AFIO_MAPR_TIM4_REMAP) |
1154 | /** |
| 1155 | /** |
1155 | * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. |
| 1156 | * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. |
1156 | * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4 |
| 1157 | * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_EnableRemap_TIM4 |
1157 | * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) |
| 1158 | * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) |
1158 | * @note TIM4_ETR on PE0 is not re-mapped. |
| 1159 | * @note TIM4_ETR on PE0 is not re-mapped. |
1159 | * @retval None |
| 1160 | * @retval None |
1160 | */ |
| 1161 | */ |
1161 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void) |
| 1162 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void) |
1162 | { |
| 1163 | { |
1163 | SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG); |
| 1164 | SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG); |
1164 | } |
| 1165 | } |
1165 | /** |
| 1166 | /** |
1166 | * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. |
| 1167 | * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. |
1167 | * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4 |
| 1168 | * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_DisableRemap_TIM4 |
1168 | * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) |
| 1169 | * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) |
1169 | * @note TIM4_ETR on PE0 is not re-mapped. |
| 1170 | * @note TIM4_ETR on PE0 is not re-mapped. |
1170 | * @retval None |
| 1171 | * @retval None |
1171 | */ |
| 1172 | */ |
1172 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void) |
| 1173 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void) |
1173 | { |
| 1174 | { |
1174 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1175 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1175 | } |
| 1176 | } |
1176 | |
| 1177 | 1177 | /** |
|
| 1178 | /** |
1178 | * @brief Check if TIM4 has been remapped or not |
| 1179 | * @brief Check if TIM4 has been remaped or not |
1179 | * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4 |
| 1180 | * @rmtoll MAPR TIM4_REMAP LL_GPIO_AF_IsEnabledRemap_TIM4 |
1180 | * @retval State of bit (1 or 0). |
| 1181 | * @retval State of bit (1 or 0). |
1181 | */ |
| 1182 | */ |
1182 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void) |
| 1183 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM4(void) |
1183 | { |
| 1184 | { |
1184 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP)); |
| 1185 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP) == (AFIO_MAPR_TIM4_REMAP)); |
1185 | } |
| 1186 | } |
1186 | #endif |
| 1187 | #endif |
1187 | |
| 1188 | 1188 | #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) |
|
| 1189 | #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) |
1189 | |
| 1190 | 1190 | /** |
|
| 1191 | /** |
1191 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| 1192 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
1192 | * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1 |
| 1193 | * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial1_CAN1 |
1193 | * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 |
| 1194 | * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 |
1194 | * @retval None |
| 1195 | * @retval None |
1195 | */ |
| 1196 | */ |
1196 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void) |
| 1197 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void) |
1197 | { |
| 1198 | { |
1198 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP1 | AFIO_MAPR_SWJ_CFG)); |
| 1199 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP1 | AFIO_MAPR_SWJ_CFG)); |
1199 | } |
| 1200 | } |
1200 | |
| 1201 | 1201 | /** |
|
| 1202 | /** |
1202 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| 1203 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
1203 | * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1 |
| 1204 | * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial2_CAN1 |
1204 | * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) |
| 1205 | * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) |
1205 | * @retval None |
| 1206 | * @retval None |
1206 | */ |
| 1207 | */ |
1207 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void) |
| 1208 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void) |
1208 | { |
| 1209 | { |
1209 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP2 | AFIO_MAPR_SWJ_CFG)); |
| 1210 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP2 | AFIO_MAPR_SWJ_CFG)); |
1210 | } |
| 1211 | } |
1211 | |
| 1212 | 1212 | /** |
|
| 1213 | /** |
1213 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| 1214 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
1214 | * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1 |
| 1215 | * @rmtoll MAPR CAN_REMAP LL_GPIO_AF_RemapPartial3_CAN1 |
1215 | * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 |
| 1216 | * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 |
1216 | * @retval None |
| 1217 | * @retval None |
1217 | */ |
| 1218 | */ |
1218 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void) |
| 1219 | __STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void) |
1219 | { |
| 1220 | { |
1220 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP3 | AFIO_MAPR_SWJ_CFG)); |
| 1221 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP3 | AFIO_MAPR_SWJ_CFG)); |
1221 | } |
| 1222 | } |
1222 | #endif |
| 1223 | #endif |
1223 | |
| 1224 | 1224 | /** |
|
| 1225 | /** |
1225 | * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used |
| 1226 | * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used |
1226 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
| 1227 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
1227 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
| 1228 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
1228 | * on 100-pin and 144-pin packages, no need for remapping). |
| 1229 | * on 100-pin and 144-pin packages, no need for remapping). |
1229 | * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01 |
| 1230 | * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_EnableRemap_PD01 |
1230 | * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. |
| 1231 | * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. |
1231 | * @retval None |
| 1232 | * @retval None |
1232 | */ |
| 1233 | */ |
1233 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void) |
| 1234 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void) |
1234 | { |
| 1235 | { |
1235 | SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG); |
| 1236 | SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG); |
1236 | } |
| 1237 | } |
1237 | |
| 1238 | 1238 | /** |
|
| 1239 | /** |
1239 | * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used |
| 1240 | * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used |
1240 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
| 1241 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
1241 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
| 1242 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
1242 | * on 100-pin and 144-pin packages, no need for remapping). |
| 1243 | * on 100-pin and 144-pin packages, no need for remapping). |
1243 | * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01 |
| 1244 | * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_DisableRemap_PD01 |
1244 | * @note DISABLE: No remapping of PD0 and PD1 |
| 1245 | * @note DISABLE: No remapping of PD0 and PD1 |
1245 | * @retval None |
| 1246 | * @retval None |
1246 | */ |
| 1247 | */ |
1247 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void) |
| 1248 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void) |
1248 | { |
| 1249 | { |
1249 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1250 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1250 | } |
| 1251 | } |
1251 | |
| 1252 | 1252 | /** |
|
| 1253 | /** |
1253 | * @brief Check if PD01 has been remapped or not |
| 1254 | * @brief Check if PD01 has been remaped or not |
1254 | * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01 |
| 1255 | * @rmtoll MAPR PD01_REMAP LL_GPIO_AF_IsEnabledRemap_PD01 |
1255 | * @retval State of bit (1 or 0). |
| 1256 | * @retval State of bit (1 or 0). |
1256 | */ |
| 1257 | */ |
1257 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void) |
| 1258 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_PD01(void) |
1258 | { |
| 1259 | { |
1259 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP)); |
| 1260 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP) == (AFIO_MAPR_PD01_REMAP)); |
1260 | } |
| 1261 | } |
1261 | |
| 1262 | 1262 | #if defined(AFIO_MAPR_TIM5CH4_IREMAP) |
|
| 1263 | #if defined(AFIO_MAPR_TIM5CH4_IREMAP) |
1263 | /** |
| 1264 | /** |
1264 | * @brief Enable the remapping of TIM5CH4. |
| 1265 | * @brief Enable the remapping of TIM5CH4. |
1265 | * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4 |
| 1266 | * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_EnableRemap_TIM5CH4 |
1266 | * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. |
| 1267 | * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. |
1267 | * @note This function is available only in high density value line devices. |
| 1268 | * @note This function is available only in high density value line devices. |
1268 | * @retval None |
| 1269 | * @retval None |
1269 | */ |
| 1270 | */ |
1270 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void) |
| 1271 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void) |
1271 | { |
| 1272 | { |
1272 | SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG); |
| 1273 | SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG); |
1273 | } |
| 1274 | } |
1274 | |
| 1275 | 1275 | /** |
|
| 1276 | /** |
1276 | * @brief Disable the remapping of TIM5CH4. |
| 1277 | * @brief Disable the remapping of TIM5CH4. |
1277 | * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4 |
| 1278 | * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_DisableRemap_TIM5CH4 |
1278 | * @note DISABLE: TIM5_CH4 is connected to PA3 |
| 1279 | * @note DISABLE: TIM5_CH4 is connected to PA3 |
1279 | * @note This function is available only in high density value line devices. |
| 1280 | * @note This function is available only in high density value line devices. |
1280 | * @retval None |
| 1281 | * @retval None |
1281 | */ |
| 1282 | */ |
1282 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void) |
| 1283 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void) |
1283 | { |
| 1284 | { |
1284 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1285 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1285 | } |
| 1286 | } |
1286 | |
| 1287 | 1287 | /** |
|
| 1288 | /** |
1288 | * @brief Check if TIM5CH4 has been remapped or not |
| 1289 | * @brief Check if TIM5CH4 has been remaped or not |
1289 | * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4 |
| 1290 | * @rmtoll MAPR TIM5CH4_IREMAP LL_GPIO_AF_IsEnabledRemap_TIM5CH4 |
1290 | * @retval State of bit (1 or 0). |
| 1291 | * @retval State of bit (1 or 0). |
1291 | */ |
| 1292 | */ |
1292 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void) |
| 1293 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM5CH4(void) |
1293 | { |
| 1294 | { |
1294 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP)); |
| 1295 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP) == (AFIO_MAPR_TIM5CH4_IREMAP)); |
1295 | } |
| 1296 | } |
1296 | #endif |
| 1297 | #endif |
1297 | |
| 1298 | 1298 | #if defined(AFIO_MAPR_ETH_REMAP) |
|
| 1299 | #if defined(AFIO_MAPR_ETH_REMAP) |
1299 | /** |
| 1300 | /** |
1300 | * @brief Enable the remapping of Ethernet MAC connections with the PHY. |
| 1301 | * @brief Enable the remapping of Ethernet MAC connections with the PHY. |
1301 | * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH |
| 1302 | * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_EnableRemap_ETH |
1302 | * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) |
| 1303 | * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) |
1303 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 1304 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1304 | * @retval None |
| 1305 | * @retval None |
1305 | */ |
| 1306 | */ |
1306 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void) |
| 1307 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void) |
1307 | { |
| 1308 | { |
1308 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG); |
| 1309 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG); |
1309 | } |
| 1310 | } |
1310 | |
| 1311 | 1311 | /** |
|
| 1312 | /** |
1312 | * @brief Disable the remapping of Ethernet MAC connections with the PHY. |
| 1313 | * @brief Disable the remapping of Ethernet MAC connections with the PHY. |
1313 | * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH |
| 1314 | * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_DisableRemap_ETH |
1314 | * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) |
| 1315 | * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) |
1315 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 1316 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1316 | * @retval None |
| 1317 | * @retval None |
1317 | */ |
| 1318 | */ |
1318 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void) |
| 1319 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void) |
1319 | { |
| 1320 | { |
1320 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1321 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1321 | } |
| 1322 | } |
1322 | |
| 1323 | 1323 | /** |
|
| 1324 | /** |
1324 | * @brief Check if ETH has been remapped or not |
| 1325 | * @brief Check if ETH has been remaped or not |
1325 | * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH |
| 1326 | * @rmtoll MAPR ETH_REMAP LL_GPIO_AF_IsEnabledRemap_ETH |
1326 | * @retval State of bit (1 or 0). |
| 1327 | * @retval State of bit (1 or 0). |
1327 | */ |
| 1328 | */ |
1328 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void) |
| 1329 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ETH(void) |
1329 | { |
| 1330 | { |
1330 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP)); |
| 1331 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP) == (AFIO_MAPR_ETH_REMAP)); |
1331 | } |
| 1332 | } |
1332 | #endif |
| 1333 | #endif |
1333 | |
| 1334 | 1334 | #if defined(AFIO_MAPR_CAN2_REMAP) |
|
| 1335 | #if defined(AFIO_MAPR_CAN2_REMAP) |
1335 | |
| 1336 | 1336 | /** |
|
| 1337 | /** |
1337 | * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
| 1338 | * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
1338 | * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2 |
| 1339 | * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_EnableRemap_CAN2 |
1339 | * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) |
| 1340 | * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) |
1340 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 1341 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1341 | * @retval None |
| 1342 | * @retval None |
1342 | */ |
| 1343 | */ |
1343 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void) |
| 1344 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void) |
1344 | { |
| 1345 | { |
1345 | SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG); |
| 1346 | SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG); |
1346 | } |
| 1347 | } |
1347 | /** |
| 1348 | /** |
1348 | * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
| 1349 | * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
1349 | * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2 |
| 1350 | * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_DisableRemap_CAN2 |
1350 | * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) |
| 1351 | * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) |
1351 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 1352 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1352 | * @retval None |
| 1353 | * @retval None |
1353 | */ |
| 1354 | */ |
1354 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void) |
| 1355 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void) |
1355 | { |
| 1356 | { |
1356 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1357 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1357 | } |
| 1358 | } |
1358 | |
| 1359 | 1359 | /** |
|
| 1360 | /** |
1360 | * @brief Check if CAN2 has been remapped or not |
| 1361 | * @brief Check if CAN2 has been remaped or not |
1361 | * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2 |
| 1362 | * @rmtoll MAPR CAN2_REMAP LL_GPIO_AF_IsEnabledRemap_CAN2 |
1362 | * @retval State of bit (1 or 0). |
| 1363 | * @retval State of bit (1 or 0). |
1363 | */ |
| 1364 | */ |
1364 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void) |
| 1365 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CAN2(void) |
1365 | { |
| 1366 | { |
1366 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP)); |
| 1367 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP) == (AFIO_MAPR_CAN2_REMAP)); |
1367 | } |
| 1368 | } |
1368 | #endif |
| 1369 | #endif |
1369 | |
| 1370 | 1370 | #if defined(AFIO_MAPR_MII_RMII_SEL) |
|
| 1371 | #if defined(AFIO_MAPR_MII_RMII_SEL) |
1371 | /** |
| 1372 | /** |
1372 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
| 1373 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
1373 | * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII |
| 1374 | * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_RMII |
1374 | * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY |
| 1375 | * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY |
1375 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 1376 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1376 | * @retval None |
| 1377 | * @retval None |
1377 | */ |
| 1378 | */ |
1378 | __STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void) |
| 1379 | __STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void) |
1379 | { |
| 1380 | { |
1380 | SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG); |
| 1381 | SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG); |
1381 | } |
| 1382 | } |
1382 | |
| 1383 | 1383 | /** |
|
| 1384 | /** |
1384 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
| 1385 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
1385 | * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII |
| 1386 | * @rmtoll MAPR MII_RMII_SEL LL_GPIO_AF_Select_ETH_MII |
1386 | * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY |
| 1387 | * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY |
1387 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 1388 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1388 | * @retval None |
| 1389 | * @retval None |
1389 | */ |
| 1390 | */ |
1390 | __STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void) |
| 1391 | __STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void) |
1391 | { |
| 1392 | { |
1392 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1393 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1393 | } |
| 1394 | } |
1394 | #endif |
| 1395 | #endif |
1395 | |
| 1396 | 1396 | #if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
|
| 1397 | #if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
1397 | /** |
| 1398 | /** |
1398 | * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
| 1399 | * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
1399 | * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ |
| 1400 | * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ |
1400 | * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. |
| 1401 | * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. |
1401 | * @retval None |
| 1402 | * @retval None |
1402 | */ |
| 1403 | */ |
1403 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void) |
| 1404 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void) |
1404 | { |
| 1405 | { |
1405 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG); |
| 1406 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG); |
1406 | } |
| 1407 | } |
1407 | |
| 1408 | 1408 | /** |
|
| 1409 | /** |
1409 | * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
| 1410 | * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
1410 | * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ |
| 1411 | * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ |
1411 | * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 |
| 1412 | * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 |
1412 | * @retval None |
| 1413 | * @retval None |
1413 | */ |
| 1414 | */ |
1414 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void) |
| 1415 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void) |
1415 | { |
| 1416 | { |
1416 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1417 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1417 | } |
| 1418 | } |
1418 | |
| 1419 | 1419 | /** |
|
| 1420 | /** |
1420 | * @brief Check if ADC1_ETRGINJ has been remapped or not |
| 1421 | * @brief Check if ADC1_ETRGINJ has been remaped or not |
1421 | * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ |
| 1422 | * @rmtoll MAPR ADC1_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ |
1422 | * @retval State of bit (1 or 0). |
| 1423 | * @retval State of bit (1 or 0). |
1423 | */ |
| 1424 | */ |
1424 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void) |
| 1425 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ(void) |
1425 | { |
| 1426 | { |
1426 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP)); |
| 1427 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP) == (AFIO_MAPR_ADC1_ETRGINJ_REMAP)); |
1427 | } |
| 1428 | } |
1428 | #endif |
| 1429 | #endif |
1429 | |
| 1430 | 1430 | #if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
|
| 1431 | #if defined(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
1431 | /** |
| 1432 | /** |
1432 | * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
| 1433 | * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
1433 | * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG |
| 1434 | * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC1_ETRGREG |
1434 | * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. |
| 1435 | * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. |
1435 | * @retval None |
| 1436 | * @retval None |
1436 | */ |
| 1437 | */ |
1437 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void) |
| 1438 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void) |
1438 | { |
| 1439 | { |
1439 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG); |
| 1440 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG); |
1440 | } |
| 1441 | } |
1441 | |
| 1442 | 1442 | /** |
|
| 1443 | /** |
1443 | * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
| 1444 | * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
1444 | * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG |
| 1445 | * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC1_ETRGREG |
1445 | * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 |
| 1446 | * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 |
1446 | * @retval None |
| 1447 | * @retval None |
1447 | */ |
| 1448 | */ |
1448 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void) |
| 1449 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void) |
1449 | { |
| 1450 | { |
1450 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1451 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1451 | } |
| 1452 | } |
1452 | |
| 1453 | 1453 | /** |
|
| 1454 | /** |
1454 | * @brief Check if ADC1_ETRGREG has been remapped or not |
| 1455 | * @brief Check if ADC1_ETRGREG has been remaped or not |
1455 | * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG |
| 1456 | * @rmtoll MAPR ADC1_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG |
1456 | * @retval State of bit (1 or 0). |
| 1457 | * @retval State of bit (1 or 0). |
1457 | */ |
| 1458 | */ |
1458 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void) |
| 1459 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG(void) |
1459 | { |
| 1460 | { |
1460 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP)); |
| 1461 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP) == (AFIO_MAPR_ADC1_ETRGREG_REMAP)); |
1461 | } |
| 1462 | } |
1462 | #endif |
| 1463 | #endif |
1463 | |
| 1464 | 1464 | #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
|
| 1465 | #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
1465 | |
| 1466 | 1466 | /** |
|
| 1467 | /** |
1467 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
| 1468 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
1468 | * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ |
| 1469 | * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ |
1469 | * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. |
| 1470 | * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. |
1470 | * @retval None |
| 1471 | * @retval None |
1471 | */ |
| 1472 | */ |
1472 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void) |
| 1473 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void) |
1473 | { |
| 1474 | { |
1474 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG); |
| 1475 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG); |
1475 | } |
| 1476 | } |
1476 | |
| 1477 | 1477 | /** |
|
| 1478 | /** |
1478 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
| 1479 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
1479 | * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ |
| 1480 | * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ |
1480 | * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 |
| 1481 | * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 |
1481 | * @retval None |
| 1482 | * @retval None |
1482 | */ |
| 1483 | */ |
1483 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void) |
| 1484 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void) |
1484 | { |
| 1485 | { |
1485 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1486 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1486 | } |
| 1487 | } |
1487 | |
| 1488 | 1488 | /** |
|
| 1489 | /** |
1489 | * @brief Check if ADC2_ETRGINJ has been remapped or not |
| 1490 | * @brief Check if ADC2_ETRGINJ has been remaped or not |
1490 | * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ |
| 1491 | * @rmtoll MAPR ADC2_ETRGINJ_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ |
1491 | * @retval State of bit (1 or 0). |
| 1492 | * @retval State of bit (1 or 0). |
1492 | */ |
| 1493 | */ |
1493 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void) |
| 1494 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ(void) |
1494 | { |
| 1495 | { |
1495 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP)); |
| 1496 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP) == (AFIO_MAPR_ADC2_ETRGINJ_REMAP)); |
1496 | } |
| 1497 | } |
1497 | #endif |
| 1498 | #endif |
1498 | |
| 1499 | 1499 | #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) |
|
| 1500 | #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) |
1500 | |
| 1501 | 1501 | /** |
|
| 1502 | /** |
1502 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| 1503 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
1503 | * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG |
| 1504 | * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_EnableRemap_ADC2_ETRGREG |
1504 | * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. |
| 1505 | * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. |
1505 | * @retval None |
| 1506 | * @retval None |
1506 | */ |
| 1507 | */ |
1507 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void) |
| 1508 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void) |
1508 | { |
| 1509 | { |
1509 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG); |
| 1510 | SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG); |
1510 | } |
| 1511 | } |
1511 | |
| 1512 | 1512 | /** |
|
| 1513 | /** |
1513 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| 1514 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
1514 | * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG |
| 1515 | * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_DisableRemap_ADC2_ETRGREG |
1515 | * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 |
| 1516 | * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 |
1516 | * @retval None |
| 1517 | * @retval None |
1517 | */ |
| 1518 | */ |
1518 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void) |
| 1519 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void) |
1519 | { |
| 1520 | { |
1520 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1521 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1521 | } |
| 1522 | } |
1522 | |
| 1523 | 1523 | /** |
|
| 1524 | /** |
1524 | * @brief Check if ADC2_ETRGREG has been remapped or not |
| 1525 | * @brief Check if ADC2_ETRGREG has been remaped or not |
1525 | * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG |
| 1526 | * @rmtoll MAPR ADC2_ETRGREG_REMAP LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG |
1526 | * @retval State of bit (1 or 0). |
| 1527 | * @retval State of bit (1 or 0). |
1527 | */ |
| 1528 | */ |
1528 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void) |
| 1529 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG(void) |
1529 | { |
| 1530 | { |
1530 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP)); |
| 1531 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP) == (AFIO_MAPR_ADC2_ETRGREG_REMAP)); |
1531 | } |
| 1532 | } |
1532 | #endif |
| 1533 | #endif |
1533 | |
| 1534 | 1534 | /** |
|
| 1535 | /** |
1535 | * @brief Enable the Serial wire JTAG configuration |
| 1536 | * @brief Enable the Serial wire JTAG configuration |
1536 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ |
| 1537 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_EnableRemap_SWJ |
1537 | * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State |
| 1538 | * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State |
1538 | * @retval None |
| 1539 | * @retval None |
1539 | */ |
| 1540 | */ |
1540 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void) |
| 1541 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SWJ(void) |
1541 | { |
| 1542 | { |
1542 | MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_RESET); |
| 1543 | CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); |
1543 | } |
| 1544 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_RESET); |
1544 | |
| 1545 | } |
1545 | /** |
| 1546 | 1546 | * @brief Enable the Serial wire JTAG configuration |
|
| 1547 | /** |
1547 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST |
| 1548 | * @brief Enable the Serial wire JTAG configuration |
1548 | * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
| 1549 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NONJTRST |
1549 | * @retval None |
| 1550 | * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
1550 | */ |
| 1551 | * @retval None |
1551 | __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void) |
| 1552 | */ |
1552 | { |
| 1553 | __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NONJTRST(void) |
1553 | MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_NOJNTRST); |
| 1554 | { |
1554 | } |
| 1555 | CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); |
1555 | |
| 1556 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_NOJNTRST); |
1556 | /** |
| 1557 | } |
1557 | * @brief Enable the Serial wire JTAG configuration |
| 1558 | 1558 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG |
|
| 1559 | /** |
1559 | * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled |
| 1560 | * @brief Enable the Serial wire JTAG configuration |
1560 | * @retval None |
| 1561 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_Remap_SWJ_NOJTAG |
1561 | */ |
| 1562 | * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled |
1562 | __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void) |
| 1563 | * @retval None |
1563 | { |
| 1564 | */ |
1564 | MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); |
| 1565 | __STATIC_INLINE void LL_GPIO_AF_Remap_SWJ_NOJTAG(void) |
1565 | } |
| 1566 | { |
1566 | |
| 1567 | CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); |
1567 | /** |
| 1568 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_JTAGDISABLE); |
1568 | * @brief Disable the Serial wire JTAG configuration |
| 1569 | } |
1569 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ |
| 1570 | 1570 | * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled |
|
| 1571 | /** |
1571 | * @retval None |
| 1572 | * @brief Disable the Serial wire JTAG configuration |
1572 | */ |
| 1573 | * @rmtoll MAPR SWJ_CFG LL_GPIO_AF_DisableRemap_SWJ |
1573 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void) |
| 1574 | * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled |
1574 | { |
| 1575 | * @retval None |
1575 | MODIFY_REG(AFIO->MAPR, AFIO_MAPR_SWJ_CFG, AFIO_MAPR_SWJ_CFG_DISABLE); |
| 1576 | */ |
1576 | } |
| 1577 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SWJ(void) |
1577 | |
| 1578 | { |
1578 | #if defined(AFIO_MAPR_SPI3_REMAP) |
| 1579 | CLEAR_BIT(AFIO->MAPR,AFIO_MAPR_SWJ_CFG); |
1579 | |
| 1580 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SWJ_CFG_DISABLE); |
1580 | /** |
| 1581 | } |
1581 | * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
| 1582 | 1582 | * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3 |
|
| 1583 | #if defined(AFIO_MAPR_SPI3_REMAP) |
1583 | * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) |
| 1584 | 1584 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
| 1585 | /** |
1585 | * @retval None |
| 1586 | * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
1586 | */ |
| 1587 | * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_EnableRemap_SPI3 |
1587 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void) |
| 1588 | * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) |
1588 | { |
| 1589 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1589 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG); |
| 1590 | * @retval None |
1590 | } |
| 1591 | */ |
1591 | |
| 1592 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void) |
1592 | /** |
| 1593 | { |
1593 | * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
| 1594 | SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG); |
1594 | * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3 |
| 1595 | } |
1595 | * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). |
| 1596 | 1596 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
| 1597 | /** |
1597 | * @retval None |
| 1598 | * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
1598 | */ |
| 1599 | * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_DisableRemap_SPI3 |
1599 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void) |
| 1600 | * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). |
1600 | { |
| 1601 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1601 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1602 | * @retval None |
1602 | } |
| 1603 | */ |
1603 | |
| 1604 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void) |
1604 | /** |
| 1605 | { |
1605 | * @brief Check if SPI3 has been remapped or not |
| 1606 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1606 | * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP |
| 1607 | } |
1607 | * @retval State of bit (1 or 0). |
| 1608 | 1608 | */ |
|
| 1609 | /** |
1609 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void) |
| 1610 | * @brief Check if SPI3 has been remaped or not |
1610 | { |
| 1611 | * @rmtoll MAPR SPI3_REMAP LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP |
1611 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP)); |
| 1612 | * @retval State of bit (1 or 0). |
1612 | } |
| 1613 | */ |
1613 | #endif |
| 1614 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_SPI3(void) |
1614 | |
| 1615 | { |
1615 | #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) |
| 1616 | return (READ_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP) == (AFIO_MAPR_SPI3_REMAP)); |
1616 | |
| 1617 | } |
1617 | /** |
| 1618 | #endif |
1618 | * @brief Control of TIM2_ITR1 internal mapping. |
| 1619 | 1619 | * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB |
|
| 1620 | #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) |
1620 | * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. |
| 1621 | 1621 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
| 1622 | /** |
1622 | * @retval None |
| 1623 | * @brief Control of TIM2_ITR1 internal mapping. |
1623 | */ |
| 1624 | * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_USB |
1624 | __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void) |
| 1625 | * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. |
1625 | { |
| 1626 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1626 | SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG); |
| 1627 | * @retval None |
1627 | } |
| 1628 | */ |
1628 | |
| 1629 | __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void) |
1629 | /** |
| 1630 | { |
1630 | * @brief Control of TIM2_ITR1 internal mapping. |
| 1631 | SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG); |
1631 | * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH |
| 1632 | } |
1632 | * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. |
| 1633 | 1633 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
| 1634 | /** |
1634 | * @retval None |
| 1635 | * @brief Control of TIM2_ITR1 internal mapping. |
1635 | */ |
| 1636 | * @rmtoll MAPR TIM2ITR1_IREMAP LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH |
1636 | __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void) |
| 1637 | * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. |
1637 | { |
| 1638 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1638 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1639 | * @retval None |
1639 | } |
| 1640 | */ |
1640 | #endif |
| 1641 | __STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void) |
1641 | |
| 1642 | { |
1642 | #if defined(AFIO_MAPR_PTP_PPS_REMAP) |
| 1643 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1643 | |
| 1644 | } |
1644 | /** |
| 1645 | #endif |
1645 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| 1646 | 1646 | * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS |
|
| 1647 | #if defined(AFIO_MAPR_PTP_PPS_REMAP) |
1647 | * @note ENABLE: PTP_PPS is output on PB5 pin. |
| 1648 | 1648 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
| 1649 | /** |
1649 | * @retval None |
| 1650 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
1650 | */ |
| 1651 | * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_EnableRemap_ETH_PTP_PPS |
1651 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void) |
| 1652 | * @note ENABLE: PTP_PPS is output on PB5 pin. |
1652 | { |
| 1653 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1653 | SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG); |
| 1654 | * @retval None |
1654 | } |
| 1655 | */ |
1655 | |
| 1656 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void) |
1656 | /** |
| 1657 | { |
1657 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| 1658 | SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG); |
1658 | * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS |
| 1659 | } |
1659 | * @note DISABLE: PTP_PPS not output on PB5 pin. |
| 1660 | 1660 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
|
| 1661 | /** |
1661 | * @retval None |
| 1662 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
1662 | */ |
| 1663 | * @rmtoll MAPR PTP_PPS_REMAP LL_GPIO_AF_DisableRemap_ETH_PTP_PPS |
1663 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void) |
| 1664 | * @note DISABLE: PTP_PPS not output on PB5 pin. |
1664 | { |
| 1665 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
1665 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
| 1666 | * @retval None |
1666 | } |
| 1667 | */ |
1667 | #endif |
| 1668 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void) |
1668 | |
| 1669 | { |
1669 | #if defined(AFIO_MAPR2_TIM9_REMAP) |
| 1670 | MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG); |
1670 | |
| 1671 | } |
1671 | /** |
| 1672 | #endif |
1672 | * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. |
| 1673 | 1673 | * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9 |
|
| 1674 | #if defined(AFIO_MAPR2_TIM9_REMAP) |
1674 | * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). |
| 1675 | 1675 | * @retval None |
|
| 1676 | /** |
1676 | */ |
| 1677 | * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. |
1677 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void) |
| 1678 | * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_EnableRemap_TIM9 |
1678 | { |
| 1679 | * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). |
1679 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); |
| 1680 | * @retval None |
1680 | } |
| 1681 | */ |
1681 | |
| 1682 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM9(void) |
1682 | /** |
| 1683 | { |
1683 | * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. |
| 1684 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); |
1684 | * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9 |
| 1685 | } |
1685 | * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). |
| 1686 | 1686 | * @retval None |
|
| 1687 | /** |
1687 | */ |
| 1688 | * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. |
1688 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void) |
| 1689 | * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_DisableRemap_TIM9 |
1689 | { |
| 1690 | * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). |
1690 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); |
| 1691 | * @retval None |
1691 | } |
| 1692 | */ |
1692 | |
| 1693 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM9(void) |
1693 | /** |
| 1694 | { |
1694 | * @brief Check if TIM9_CH1 and TIM9_CH2 have been remapped or not |
| 1695 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP); |
1695 | * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9 |
| 1696 | } |
1696 | * @retval State of bit (1 or 0). |
| 1697 | 1697 | */ |
|
| 1698 | /** |
1698 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void) |
| 1699 | * @brief Check if TIM9_CH1 and TIM9_CH2 have been remaped or not |
1699 | { |
| 1700 | * @rmtoll MAPR2 TIM9_REMAP LL_GPIO_AF_IsEnabledRemap_TIM9 |
1700 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP)); |
| 1701 | * @retval State of bit (1 or 0). |
1701 | } |
| 1702 | */ |
1702 | #endif |
| 1703 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM9(void) |
1703 | |
| 1704 | { |
1704 | #if defined(AFIO_MAPR2_TIM10_REMAP) |
| 1705 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) == (AFIO_MAPR2_TIM9_REMAP)); |
1705 | |
| 1706 | } |
1706 | /** |
| 1707 | #endif |
1707 | * @brief Enable the remapping of TIM10_CH1. |
| 1708 | 1708 | * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10 |
|
| 1709 | #if defined(AFIO_MAPR2_TIM10_REMAP) |
1709 | * @note ENABLE: Remap (TIM10_CH1 on PF6). |
| 1710 | 1710 | * @retval None |
|
| 1711 | /** |
1711 | */ |
| 1712 | * @brief Enable the remapping of TIM10_CH1. |
1712 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void) |
| 1713 | * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_EnableRemap_TIM10 |
1713 | { |
| 1714 | * @note ENABLE: Remap (TIM10_CH1 on PF6). |
1714 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); |
| 1715 | * @retval None |
1715 | } |
| 1716 | */ |
1716 | |
| 1717 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM10(void) |
1717 | /** |
| 1718 | { |
1718 | * @brief Disable the remapping of TIM10_CH1. |
| 1719 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); |
1719 | * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10 |
| 1720 | } |
1720 | * @note DISABLE: No remap (TIM10_CH1 on PB8). |
| 1721 | 1721 | * @retval None |
|
| 1722 | /** |
1722 | */ |
| 1723 | * @brief Disable the remapping of TIM10_CH1. |
1723 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void) |
| 1724 | * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_DisableRemap_TIM10 |
1724 | { |
| 1725 | * @note DISABLE: No remap (TIM10_CH1 on PB8). |
1725 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); |
| 1726 | * @retval None |
1726 | } |
| 1727 | */ |
1727 | |
| 1728 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM10(void) |
1728 | /** |
| 1729 | { |
1729 | * @brief Check if TIM10_CH1 has been remapped or not |
| 1730 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP); |
1730 | * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10 |
| 1731 | } |
1731 | * @retval State of bit (1 or 0). |
| 1732 | 1732 | */ |
|
| 1733 | /** |
1733 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void) |
| 1734 | * @brief Check if TIM10_CH1 has been remaped or not |
1734 | { |
| 1735 | * @rmtoll MAPR2 TIM10_REMAP LL_GPIO_AF_IsEnabledRemap_TIM10 |
1735 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP)); |
| 1736 | * @retval State of bit (1 or 0). |
1736 | } |
| 1737 | */ |
1737 | #endif |
| 1738 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM10(void) |
1738 | |
| 1739 | { |
1739 | #if defined(AFIO_MAPR2_TIM11_REMAP) |
| 1740 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) == (AFIO_MAPR2_TIM10_REMAP)); |
1740 | /** |
| 1741 | } |
1741 | * @brief Enable the remapping of TIM11_CH1. |
| 1742 | #endif |
1742 | * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11 |
| 1743 | 1743 | * @note ENABLE: Remap (TIM11_CH1 on PF7). |
|
| 1744 | #if defined(AFIO_MAPR2_TIM11_REMAP) |
1744 | * @retval None |
| 1745 | /** |
1745 | */ |
| 1746 | * @brief Enable the remapping of TIM11_CH1. |
1746 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void) |
| 1747 | * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_EnableRemap_TIM11 |
1747 | { |
| 1748 | * @note ENABLE: Remap (TIM11_CH1 on PF7). |
1748 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); |
| 1749 | * @retval None |
1749 | } |
| 1750 | */ |
1750 | |
| 1751 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM11(void) |
1751 | /** |
| 1752 | { |
1752 | * @brief Disable the remapping of TIM11_CH1. |
| 1753 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); |
1753 | * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11 |
| 1754 | } |
1754 | * @note DISABLE: No remap (TIM11_CH1 on PB9). |
| 1755 | 1755 | * @retval None |
|
| 1756 | /** |
1756 | */ |
| 1757 | * @brief Disable the remapping of TIM11_CH1. |
1757 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void) |
| 1758 | * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_DisableRemap_TIM11 |
1758 | { |
| 1759 | * @note DISABLE: No remap (TIM11_CH1 on PB9). |
1759 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); |
| 1760 | * @retval None |
1760 | } |
| 1761 | */ |
1761 | |
| 1762 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM11(void) |
1762 | /** |
| 1763 | { |
1763 | * @brief Check if TIM11_CH1 has been remapped or not |
| 1764 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP); |
1764 | * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11 |
| 1765 | } |
1765 | * @retval State of bit (1 or 0). |
| 1766 | 1766 | */ |
|
| 1767 | /** |
1767 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void) |
| 1768 | * @brief Check if TIM11_CH1 has been remaped or not |
1768 | { |
| 1769 | * @rmtoll MAPR2 TIM11_REMAP LL_GPIO_AF_IsEnabledRemap_TIM11 |
1769 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP)); |
| 1770 | * @retval State of bit (1 or 0). |
1770 | } |
| 1771 | */ |
1771 | #endif |
| 1772 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM11(void) |
1772 | |
| 1773 | { |
1773 | #if defined(AFIO_MAPR2_TIM13_REMAP) |
| 1774 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) == (AFIO_MAPR2_TIM11_REMAP)); |
1774 | |
| 1775 | } |
1775 | /** |
| 1776 | #endif |
1776 | * @brief Enable the remapping of TIM13_CH1. |
| 1777 | 1777 | * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13 |
|
| 1778 | #if defined(AFIO_MAPR2_TIM13_REMAP) |
1778 | * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). |
| 1779 | 1779 | * @retval None |
|
| 1780 | /** |
1780 | */ |
| 1781 | * @brief Enable the remapping of TIM13_CH1. |
1781 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void) |
| 1782 | * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_EnableRemap_TIM13 |
1782 | { |
| 1783 | * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). |
1783 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); |
| 1784 | * @retval None |
1784 | } |
| 1785 | */ |
1785 | |
| 1786 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM13(void) |
1786 | /** |
| 1787 | { |
1787 | * @brief Disable the remapping of TIM13_CH1. |
| 1788 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); |
1788 | * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13 |
| 1789 | } |
1789 | * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). |
| 1790 | 1790 | * @retval None |
|
| 1791 | /** |
1791 | */ |
| 1792 | * @brief Disable the remapping of TIM13_CH1. |
1792 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void) |
| 1793 | * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_DisableRemap_TIM13 |
1793 | { |
| 1794 | * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). |
1794 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); |
| 1795 | * @retval None |
1795 | } |
| 1796 | */ |
1796 | |
| 1797 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM13(void) |
1797 | /** |
| 1798 | { |
1798 | * @brief Check if TIM13_CH1 has been remapped or not |
| 1799 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP); |
1799 | * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13 |
| 1800 | } |
1800 | * @retval State of bit (1 or 0). |
| 1801 | 1801 | */ |
|
| 1802 | /** |
1802 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void) |
| 1803 | * @brief Check if TIM13_CH1 has been remaped or not |
1803 | { |
| 1804 | * @rmtoll MAPR2 TIM13_REMAP LL_GPIO_AF_IsEnabledRemap_TIM13 |
1804 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP)); |
| 1805 | * @retval State of bit (1 or 0). |
1805 | } |
| 1806 | */ |
1806 | #endif |
| 1807 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM13(void) |
1807 | |
| 1808 | { |
1808 | #if defined(AFIO_MAPR2_TIM14_REMAP) |
| 1809 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) == (AFIO_MAPR2_TIM13_REMAP)); |
1809 | |
| 1810 | } |
1810 | /** |
| 1811 | #endif |
1811 | * @brief Enable the remapping of TIM14_CH1. |
| 1812 | 1812 | * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14 |
|
| 1813 | #if defined(AFIO_MAPR2_TIM14_REMAP) |
1813 | * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). |
| 1814 | 1814 | * @retval None |
|
| 1815 | /** |
1815 | */ |
| 1816 | * @brief Enable the remapping of TIM14_CH1. |
1816 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void) |
| 1817 | * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_EnableRemap_TIM14 |
1817 | { |
| 1818 | * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). |
1818 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); |
| 1819 | * @retval None |
1819 | } |
| 1820 | */ |
1820 | |
| 1821 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM14(void) |
1821 | /** |
| 1822 | { |
1822 | * @brief Disable the remapping of TIM14_CH1. |
| 1823 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); |
1823 | * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14 |
| 1824 | } |
1824 | * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). |
| 1825 | 1825 | * @retval None |
|
| 1826 | /** |
1826 | */ |
| 1827 | * @brief Disable the remapping of TIM14_CH1. |
1827 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void) |
| 1828 | * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_DisableRemap_TIM14 |
1828 | { |
| 1829 | * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). |
1829 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); |
| 1830 | * @retval None |
1830 | } |
| 1831 | */ |
1831 | |
| 1832 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM14(void) |
1832 | /** |
| 1833 | { |
1833 | * @brief Check if TIM14_CH1 has been remapped or not |
| 1834 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP); |
1834 | * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14 |
| 1835 | } |
1835 | * @retval State of bit (1 or 0). |
| 1836 | 1836 | */ |
|
| 1837 | /** |
1837 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void) |
| 1838 | * @brief Check if TIM14_CH1 has been remaped or not |
1838 | { |
| 1839 | * @rmtoll MAPR2 TIM14_REMAP LL_GPIO_AF_IsEnabledRemap_TIM14 |
1839 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP)); |
| 1840 | * @retval State of bit (1 or 0). |
1840 | } |
| 1841 | */ |
1841 | #endif |
| 1842 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM14(void) |
1842 | |
| 1843 | { |
1843 | #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) |
| 1844 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) == (AFIO_MAPR2_TIM14_REMAP)); |
1844 | |
| 1845 | } |
1845 | /** |
| 1846 | #endif |
1846 | * @brief Controls the use of the optional FSMC_NADV signal. |
| 1847 | 1847 | * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV |
|
| 1848 | #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) |
1848 | * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. |
| 1849 | 1849 | * @retval None |
|
| 1850 | /** |
1850 | */ |
| 1851 | * @brief Controls the use of the optional FSMC_NADV signal. |
1851 | __STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void) |
| 1852 | * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Disconnect_FSMCNADV |
1852 | { |
| 1853 | * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. |
1853 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); |
| 1854 | * @retval None |
1854 | } |
| 1855 | */ |
1855 | |
| 1856 | __STATIC_INLINE void LL_GPIO_AF_Disconnect_FSMCNADV(void) |
1856 | /** |
| 1857 | { |
1857 | * @brief Controls the use of the optional FSMC_NADV signal. |
| 1858 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); |
1858 | * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV |
| 1859 | } |
1859 | * @note CONNECTED: The NADV signal is connected to the output (default). |
| 1860 | 1860 | * @retval None |
|
| 1861 | /** |
1861 | */ |
| 1862 | * @brief Controls the use of the optional FSMC_NADV signal. |
1862 | __STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void) |
| 1863 | * @rmtoll MAPR2 FSMC_NADV LL_GPIO_AF_Connect_FSMCNADV |
1863 | { |
| 1864 | * @note CONNECTED: The NADV signal is connected to the output (default). |
1864 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); |
| 1865 | * @retval None |
1865 | } |
| 1866 | */ |
1866 | #endif |
| 1867 | __STATIC_INLINE void LL_GPIO_AF_Connect_FSMCNADV(void) |
1867 | |
| 1868 | { |
1868 | #if defined(AFIO_MAPR2_TIM15_REMAP) |
| 1869 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP); |
1869 | |
| 1870 | } |
1870 | /** |
| 1871 | #endif |
1871 | * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. |
| 1872 | 1872 | * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15 |
|
| 1873 | #if defined(AFIO_MAPR2_TIM15_REMAP) |
1873 | * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). |
| 1874 | 1874 | * @retval None |
|
| 1875 | /** |
1875 | */ |
| 1876 | * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. |
1876 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void) |
| 1877 | * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_EnableRemap_TIM15 |
1877 | { |
| 1878 | * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). |
1878 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); |
| 1879 | * @retval None |
1879 | } |
| 1880 | */ |
1880 | /** |
| 1881 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM15(void) |
1881 | * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. |
| 1882 | { |
1882 | * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15 |
| 1883 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); |
1883 | * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). |
| 1884 | } |
1884 | * @retval None |
| 1885 | /** |
1885 | */ |
| 1886 | * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. |
1886 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void) |
| 1887 | * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_DisableRemap_TIM15 |
1887 | { |
| 1888 | * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). |
1888 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); |
| 1889 | * @retval None |
1889 | } |
| 1890 | */ |
1890 | |
| 1891 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM15(void) |
1891 | /** |
| 1892 | { |
1892 | * @brief Check if TIM15_CH1 has been remapped or not |
| 1893 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP); |
1893 | * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15 |
| 1894 | } |
1894 | * @retval State of bit (1 or 0). |
| 1895 | 1895 | */ |
|
| 1896 | /** |
1896 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void) |
| 1897 | * @brief Check if TIM15_CH1 has been remaped or not |
1897 | { |
| 1898 | * @rmtoll MAPR2 TIM15_REMAP LL_GPIO_AF_IsEnabledRemap_TIM15 |
1898 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP)); |
| 1899 | * @retval State of bit (1 or 0). |
1899 | } |
| 1900 | */ |
1900 | #endif |
| 1901 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM15(void) |
1901 | |
| 1902 | { |
1902 | #if defined(AFIO_MAPR2_TIM16_REMAP) |
| 1903 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) == (AFIO_MAPR2_TIM15_REMAP)); |
1903 | |
| 1904 | } |
1904 | /** |
| 1905 | #endif |
1905 | * @brief Enable the remapping of TIM16_CH1. |
| 1906 | 1906 | * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16 |
|
| 1907 | #if defined(AFIO_MAPR2_TIM16_REMAP) |
1907 | * @note ENABLE: Remap (TIM16_CH1 on PA6). |
| 1908 | 1908 | * @retval None |
|
| 1909 | /** |
1909 | */ |
| 1910 | * @brief Enable the remapping of TIM16_CH1. |
1910 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void) |
| 1911 | * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_EnableRemap_TIM16 |
1911 | { |
| 1912 | * @note ENABLE: Remap (TIM16_CH1 on PA6). |
1912 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); |
| 1913 | * @retval None |
1913 | } |
| 1914 | */ |
1914 | |
| 1915 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM16(void) |
1915 | /** |
| 1916 | { |
1916 | * @brief Disable the remapping of TIM16_CH1. |
| 1917 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); |
1917 | * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16 |
| 1918 | } |
1918 | * @note DISABLE: No remap (TIM16_CH1 on PB8). |
| 1919 | 1919 | * @retval None |
|
| 1920 | /** |
1920 | */ |
| 1921 | * @brief Disable the remapping of TIM16_CH1. |
1921 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void) |
| 1922 | * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_DisableRemap_TIM16 |
1922 | { |
| 1923 | * @note DISABLE: No remap (TIM16_CH1 on PB8). |
1923 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); |
| 1924 | * @retval None |
1924 | } |
| 1925 | */ |
1925 | |
| 1926 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM16(void) |
1926 | /** |
| 1927 | { |
1927 | * @brief Check if TIM16_CH1 has been remapped or not |
| 1928 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP); |
1928 | * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16 |
| 1929 | } |
1929 | * @retval State of bit (1 or 0). |
| 1930 | 1930 | */ |
|
| 1931 | /** |
1931 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void) |
| 1932 | * @brief Check if TIM16_CH1 has been remaped or not |
1932 | { |
| 1933 | * @rmtoll MAPR2 TIM16_REMAP LL_GPIO_AF_IsEnabledRemap_TIM16 |
1933 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP)); |
| 1934 | * @retval State of bit (1 or 0). |
1934 | } |
| 1935 | */ |
1935 | #endif |
| 1936 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM16(void) |
1936 | |
| 1937 | { |
1937 | #if defined(AFIO_MAPR2_TIM17_REMAP) |
| 1938 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) == (AFIO_MAPR2_TIM16_REMAP)); |
1938 | |
| 1939 | } |
1939 | /** |
| 1940 | #endif |
1940 | * @brief Enable the remapping of TIM17_CH1. |
| 1941 | 1941 | * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17 |
|
| 1942 | #if defined(AFIO_MAPR2_TIM17_REMAP) |
1942 | * @note ENABLE: Remap (TIM17_CH1 on PA7). |
| 1943 | 1943 | * @retval None |
|
| 1944 | /** |
1944 | */ |
| 1945 | * @brief Enable the remapping of TIM17_CH1. |
1945 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void) |
| 1946 | * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_EnableRemap_TIM17 |
1946 | { |
| 1947 | * @note ENABLE: Remap (TIM17_CH1 on PA7). |
1947 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); |
| 1948 | * @retval None |
1948 | } |
| 1949 | */ |
1949 | |
| 1950 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM17(void) |
1950 | /** |
| 1951 | { |
1951 | * @brief Disable the remapping of TIM17_CH1. |
| 1952 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); |
1952 | * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17 |
| 1953 | } |
1953 | * @note DISABLE: No remap (TIM17_CH1 on PB9). |
| 1954 | 1954 | * @retval None |
|
| 1955 | /** |
1955 | */ |
| 1956 | * @brief Disable the remapping of TIM17_CH1. |
1956 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void) |
| 1957 | * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_DisableRemap_TIM17 |
1957 | { |
| 1958 | * @note DISABLE: No remap (TIM17_CH1 on PB9). |
1958 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); |
| 1959 | * @retval None |
1959 | } |
| 1960 | */ |
1960 | |
| 1961 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM17(void) |
1961 | /** |
| 1962 | { |
1962 | * @brief Check if TIM17_CH1 has been remapped or not |
| 1963 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP); |
1963 | * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17 |
| 1964 | } |
1964 | * @retval State of bit (1 or 0). |
| 1965 | 1965 | */ |
|
| 1966 | /** |
1966 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void) |
| 1967 | * @brief Check if TIM17_CH1 has been remaped or not |
1967 | { |
| 1968 | * @rmtoll MAPR2 TIM17_REMAP LL_GPIO_AF_IsEnabledRemap_TIM17 |
1968 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP)); |
| 1969 | * @retval State of bit (1 or 0). |
1969 | } |
| 1970 | */ |
1970 | #endif |
| 1971 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM17(void) |
1971 | |
| 1972 | { |
1972 | #if defined(AFIO_MAPR2_CEC_REMAP) |
| 1973 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) == (AFIO_MAPR2_TIM17_REMAP)); |
1973 | |
| 1974 | } |
1974 | /** |
| 1975 | #endif |
1975 | * @brief Enable the remapping of CEC. |
| 1976 | 1976 | * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC |
|
| 1977 | #if defined(AFIO_MAPR2_CEC_REMAP) |
1977 | * @note ENABLE: Remap (CEC on PB10). |
| 1978 | 1978 | * @retval None |
|
| 1979 | /** |
1979 | */ |
| 1980 | * @brief Enable the remapping of CEC. |
1980 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void) |
| 1981 | * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_EnableRemap_CEC |
1981 | { |
| 1982 | * @note ENABLE: Remap (CEC on PB10). |
1982 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); |
| 1983 | * @retval None |
1983 | } |
| 1984 | */ |
1984 | |
| 1985 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_CEC(void) |
1985 | /** |
| 1986 | { |
1986 | * @brief Disable the remapping of CEC. |
| 1987 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); |
1987 | * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC |
| 1988 | } |
1988 | * @note DISABLE: No remap (CEC on PB8). |
| 1989 | 1989 | * @retval None |
|
| 1990 | /** |
1990 | */ |
| 1991 | * @brief Disable the remapping of CEC. |
1991 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void) |
| 1992 | * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_DisableRemap_CEC |
1992 | { |
| 1993 | * @note DISABLE: No remap (CEC on PB8). |
1993 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); |
| 1994 | * @retval None |
1994 | } |
| 1995 | */ |
1995 | |
| 1996 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_CEC(void) |
1996 | /** |
| 1997 | { |
1997 | * @brief Check if CEC has been remapped or not |
| 1998 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP); |
1998 | * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC |
| 1999 | } |
1999 | * @retval State of bit (1 or 0). |
| 2000 | 2000 | */ |
|
| 2001 | /** |
2001 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void) |
| 2002 | * @brief Check if CEC has been remaped or not |
2002 | { |
| 2003 | * @rmtoll MAPR2 CEC_REMAP LL_GPIO_AF_IsEnabledRemap_CEC |
2003 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP)); |
| 2004 | * @retval State of bit (1 or 0). |
2004 | } |
| 2005 | */ |
2005 | #endif |
| 2006 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_CEC(void) |
2006 | |
| 2007 | { |
2007 | #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) |
| 2008 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) == (AFIO_MAPR2_CEC_REMAP)); |
2008 | |
| 2009 | } |
2009 | /** |
| 2010 | #endif |
2010 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
| 2011 | 2011 | * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA |
|
| 2012 | #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) |
2012 | * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) |
| 2013 | 2013 | * @retval None |
|
| 2014 | /** |
2014 | */ |
| 2015 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
2015 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void) |
| 2016 | * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM1DMA |
2016 | { |
| 2017 | * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) |
2017 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); |
| 2018 | * @retval None |
2018 | } |
| 2019 | */ |
2019 | |
| 2020 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1DMA(void) |
2020 | /** |
| 2021 | { |
2021 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
| 2022 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); |
2022 | * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA |
| 2023 | } |
2023 | * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). |
| 2024 | 2024 | * @retval None |
|
| 2025 | /** |
2025 | */ |
| 2026 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
2026 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void) |
| 2027 | * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM1DMA |
2027 | { |
| 2028 | * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). |
2028 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); |
| 2029 | * @retval None |
2029 | } |
| 2030 | */ |
2030 | |
| 2031 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1DMA(void) |
2031 | /** |
| 2032 | { |
2032 | * @brief Check if TIM1DMA has been remapped or not |
| 2033 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP); |
2033 | * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA |
| 2034 | } |
2034 | * @retval State of bit (1 or 0). |
| 2035 | 2035 | */ |
|
| 2036 | /** |
2036 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void) |
| 2037 | * @brief Check if TIM1DMA has been remaped or not |
2037 | { |
| 2038 | * @rmtoll MAPR2 TIM1_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM1DMA |
2038 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP)); |
| 2039 | * @retval State of bit (1 or 0). |
2039 | } |
| 2040 | */ |
2040 | #endif |
| 2041 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM1DMA(void) |
2041 | |
| 2042 | { |
2042 | #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
| 2043 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) == (AFIO_MAPR2_TIM1_DMA_REMAP)); |
2043 | |
| 2044 | } |
2044 | /** |
| 2045 | #endif |
2045 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
| 2046 | 2046 | * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA |
|
| 2047 | #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
2047 | * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) |
| 2048 | 2048 | * @retval None |
|
| 2049 | /** |
2049 | */ |
| 2050 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
2050 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void) |
| 2051 | * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_EnableRemap_TIM67DACDMA |
2051 | { |
| 2052 | * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) |
2052 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); |
| 2053 | * @retval None |
2053 | } |
| 2054 | */ |
2054 | |
| 2055 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM67DACDMA(void) |
2055 | /** |
| 2056 | { |
2056 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
| 2057 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); |
2057 | * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA |
| 2058 | } |
2058 | * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) |
| 2059 | 2059 | * @retval None |
|
| 2060 | /** |
2060 | */ |
| 2061 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
2061 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void) |
| 2062 | * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_DisableRemap_TIM67DACDMA |
2062 | { |
| 2063 | * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) |
2063 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); |
| 2064 | * @retval None |
2064 | } |
| 2065 | */ |
2065 | |
| 2066 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM67DACDMA(void) |
2066 | /** |
| 2067 | { |
2067 | * @brief Check if TIM67DACDMA has been remapped or not |
| 2068 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP); |
2068 | * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA |
| 2069 | } |
2069 | * @retval State of bit (1 or 0). |
| 2070 | 2070 | */ |
|
| 2071 | /** |
2071 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void) |
| 2072 | * @brief Check if TIM67DACDMA has been remaped or not |
2072 | { |
| 2073 | * @rmtoll MAPR2 TIM76_DAC_DMA_REMAP LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA |
2073 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP)); |
| 2074 | * @retval State of bit (1 or 0). |
2074 | } |
| 2075 | */ |
2075 | #endif |
| 2076 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM67DACDMA(void) |
2076 | |
| 2077 | { |
2077 | #if defined(AFIO_MAPR2_TIM12_REMAP) |
| 2078 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) == (AFIO_MAPR2_TIM67_DAC_DMA_REMAP)); |
2078 | |
| 2079 | } |
2079 | /** |
| 2080 | #endif |
2080 | * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. |
| 2081 | 2081 | * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12 |
|
| 2082 | #if defined(AFIO_MAPR2_TIM12_REMAP) |
2082 | * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). |
| 2083 | 2083 | * @note This bit is available only in high density value line devices. |
|
| 2084 | /** |
2084 | * @retval None |
| 2085 | * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. |
2085 | */ |
| 2086 | * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_EnableRemap_TIM12 |
2086 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void) |
| 2087 | * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). |
2087 | { |
| 2088 | * @note This bit is available only in high density value line devices. |
2088 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); |
| 2089 | * @retval None |
2089 | } |
| 2090 | */ |
2090 | |
| 2091 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM12(void) |
2091 | /** |
| 2092 | { |
2092 | * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. |
| 2093 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); |
2093 | * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12 |
| 2094 | } |
2094 | * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). |
| 2095 | 2095 | * @note This bit is available only in high density value line devices. |
|
| 2096 | /** |
2096 | * @retval None |
| 2097 | * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. |
2097 | */ |
| 2098 | * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_DisableRemap_TIM12 |
2098 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void) |
| 2099 | * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). |
2099 | { |
| 2100 | * @note This bit is available only in high density value line devices. |
2100 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); |
| 2101 | * @retval None |
2101 | } |
| 2102 | */ |
2102 | |
| 2103 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM12(void) |
2103 | /** |
| 2104 | { |
2104 | * @brief Check if TIM12_CH1 has been remapped or not |
| 2105 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP); |
2105 | * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12 |
| 2106 | } |
2106 | * @retval State of bit (1 or 0). |
| 2107 | 2107 | */ |
|
| 2108 | /** |
2108 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void) |
| 2109 | * @brief Check if TIM12_CH1 has been remaped or not |
2109 | { |
| 2110 | * @rmtoll MAPR2 TIM12_REMAP LL_GPIO_AF_IsEnabledRemap_TIM12 |
2110 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP)); |
| 2111 | * @retval State of bit (1 or 0). |
2111 | } |
| 2112 | */ |
2112 | #endif |
| 2113 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_TIM12(void) |
2113 | |
| 2114 | { |
2114 | #if defined(AFIO_MAPR2_MISC_REMAP) |
| 2115 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) == (AFIO_MAPR2_TIM12_REMAP)); |
2115 | |
| 2116 | } |
2116 | /** |
| 2117 | #endif |
2117 | * @brief Miscellaneous features remapping. |
| 2118 | 2118 | * This bit is set and cleared by software. It controls miscellaneous features. |
|
| 2119 | #if defined(AFIO_MAPR2_MISC_REMAP) |
2119 | * The DMA2 channel 5 interrupt position in the vector table. |
| 2120 | 2120 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
|
| 2121 | /** |
2121 | * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC |
| 2122 | * @brief Miscellaneous features remapping. |
2122 | * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is |
| 2123 | * This bit is set and cleared by software. It controls miscellaneous features. |
2123 | * selected as DAC Trigger 3, TIM15 triggers TIM1/3. |
| 2124 | * The DMA2 channel 5 interrupt position in the vector table. |
2124 | * @note This bit is available only in high density value line devices. |
| 2125 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
2125 | * @retval None |
| 2126 | * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_EnableRemap_MISC |
2126 | */ |
| 2127 | * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is |
2127 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void) |
| 2128 | * selected as DAC Trigger 3, TIM15 triggers TIM1/3. |
2128 | { |
| 2129 | * @note This bit is available only in high density value line devices. |
2129 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); |
| 2130 | * @retval None |
2130 | } |
| 2131 | */ |
2131 | |
| 2132 | __STATIC_INLINE void LL_GPIO_AF_EnableRemap_MISC(void) |
2132 | /** |
| 2133 | { |
2133 | * @brief Miscellaneous features remapping. |
| 2134 | SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); |
2134 | * This bit is set and cleared by software. It controls miscellaneous features. |
| 2135 | } |
2135 | * The DMA2 channel 5 interrupt position in the vector table. |
| 2136 | 2136 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
|
| 2137 | /** |
2137 | * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC |
| 2138 | * @brief Miscellaneous features remapping. |
2138 | * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO |
| 2139 | * This bit is set and cleared by software. It controls miscellaneous features. |
2139 | * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. |
| 2140 | * The DMA2 channel 5 interrupt position in the vector table. |
2140 | * @note This bit is available only in high density value line devices. |
| 2141 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
2141 | * @retval None |
| 2142 | * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_DisableRemap_MISC |
2142 | */ |
| 2143 | * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO |
2143 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void) |
| 2144 | * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. |
2144 | { |
| 2145 | * @note This bit is available only in high density value line devices. |
2145 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); |
| 2146 | * @retval None |
2146 | } |
| 2147 | */ |
2147 | |
| 2148 | __STATIC_INLINE void LL_GPIO_AF_DisableRemap_MISC(void) |
2148 | /** |
| 2149 | { |
2149 | * @brief Check if MISC has been remapped or not |
| 2150 | CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP); |
2150 | * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC |
| 2151 | } |
2151 | * @retval State of bit (1 or 0). |
| 2152 | 2152 | */ |
|
| 2153 | /** |
2153 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void) |
| 2154 | * @brief Check if MISC has been remaped or not |
2154 | { |
| 2155 | * @rmtoll MAPR2 MISC_REMAP LL_GPIO_AF_IsEnabledRemap_MISC |
2155 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP)); |
| 2156 | * @retval State of bit (1 or 0). |
2156 | } |
| 2157 | */ |
2157 | #endif |
| 2158 | __STATIC_INLINE uint32_t LL_GPIO_AF_IsEnabledRemap_MISC(void) |
2158 | |
| 2159 | { |
2159 | /** |
| 2160 | return (READ_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) == (AFIO_MAPR2_MISC_REMAP)); |
2160 | * @} |
| 2161 | } |
2161 | */ |
| 2162 | #endif |
2162 | |
| 2163 | 2163 | /** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration |
|
| 2164 | /** |
2164 | * @brief This section propose definition to Configure EVENTOUT Cortex feature . |
| 2165 | * @} |
2165 | * @{ |
| 2166 | */ |
2166 | */ |
| 2167 | 2167 | ||
| 2168 | /** @defgroup GPIO_AF_LL_EVENTOUT Output Event configuration |
2168 | /** |
| 2169 | * @brief This section propose definition to Configure EVENTOUT Cortex feature . |
2169 | * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. |
| 2170 | * @{ |
2170 | * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n |
| 2171 | */ |
2171 | * EVCR PIN LL_GPIO_AF_ConfigEventout |
| 2172 | 2172 | * @param LL_GPIO_PortSource This parameter can be one of the following values: |
|
| 2173 | /** |
2173 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A |
| 2174 | * @brief Configures the port and pin on which the EVENTOUT Cortex signal will be connected. |
2174 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B |
| 2175 | * @rmtoll EVCR PORT LL_GPIO_AF_ConfigEventout\n |
2175 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C |
| 2176 | * EVCR PIN LL_GPIO_AF_ConfigEventout |
2176 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D |
| 2177 | * @param LL_GPIO_PortSource This parameter can be one of the following values: |
2177 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E |
| 2178 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_A |
2178 | * @param LL_GPIO_PinSource This parameter can be one of the following values: |
| 2179 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_B |
2179 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0 |
| 2180 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_C |
2180 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1 |
| 2181 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_D |
2181 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2 |
| 2182 | * @arg @ref LL_GPIO_AF_EVENTOUT_PORT_E |
2182 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3 |
| 2183 | * @param LL_GPIO_PinSource This parameter can be one of the following values: |
2183 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4 |
| 2184 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_0 |
2184 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5 |
| 2185 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_1 |
2185 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6 |
| 2186 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_2 |
2186 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7 |
| 2187 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_3 |
2187 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8 |
| 2188 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_4 |
2188 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9 |
| 2189 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_5 |
2189 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10 |
| 2190 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_6 |
2190 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11 |
| 2191 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_7 |
2191 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12 |
| 2192 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_8 |
2192 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13 |
| 2193 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_9 |
2193 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14 |
| 2194 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_10 |
2194 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15 |
| 2195 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_11 |
2195 | * @retval None |
| 2196 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_12 |
2196 | */ |
| 2197 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_13 |
2197 | __STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource) |
| 2198 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_14 |
2198 | { |
| 2199 | * @arg @ref LL_GPIO_AF_EVENTOUT_PIN_15 |
2199 | MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource)); |
| 2200 | * @retval None |
2200 | } |
| 2201 | */ |
2201 | |
| 2202 | __STATIC_INLINE void LL_GPIO_AF_ConfigEventout(uint32_t LL_GPIO_PortSource, uint32_t LL_GPIO_PinSource) |
2202 | /** |
| 2203 | { |
2203 | * @brief Enables the Event Output. |
| 2204 | MODIFY_REG(AFIO->EVCR, (AFIO_EVCR_PORT) | (AFIO_EVCR_PIN), (LL_GPIO_PortSource) | (LL_GPIO_PinSource)); |
2204 | * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout |
| 2205 | } |
2205 | * @retval None |
| 2206 | 2206 | */ |
|
| 2207 | /** |
2207 | __STATIC_INLINE void LL_GPIO_AF_EnableEventout(void) |
| 2208 | * @brief Enables the Event Output. |
2208 | { |
| 2209 | * @rmtoll EVCR EVOE LL_GPIO_AF_EnableEventout |
2209 | SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); |
| 2210 | * @retval None |
2210 | } |
| 2211 | */ |
2211 | |
| 2212 | __STATIC_INLINE void LL_GPIO_AF_EnableEventout(void) |
2212 | /** |
| 2213 | { |
2213 | * @brief Disables the Event Output. |
| 2214 | SET_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); |
2214 | * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout |
| 2215 | } |
2215 | * @retval None |
| 2216 | 2216 | */ |
|
| 2217 | /** |
2217 | __STATIC_INLINE void LL_GPIO_AF_DisableEventout(void) |
| 2218 | * @brief Disables the Event Output. |
2218 | { |
| 2219 | * @rmtoll EVCR EVOE LL_GPIO_AF_DisableEventout |
2219 | CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); |
| 2220 | * @retval None |
2220 | } |
| 2221 | */ |
2221 | |
| 2222 | __STATIC_INLINE void LL_GPIO_AF_DisableEventout(void) |
2222 | /** |
| 2223 | { |
2223 | * @} |
| 2224 | CLEAR_BIT(AFIO->EVCR, AFIO_EVCR_EVOE); |
2224 | */ |
| 2225 | } |
2225 | /** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt |
| 2226 | 2226 | * @brief This section Configure source input for the EXTI external interrupt . |
|
| 2227 | /** |
2227 | * @{ |
| 2228 | * @} |
2228 | */ |
| 2229 | */ |
2229 | |
| 2230 | /** @defgroup GPIO_AF_LL_EXTI EXTI external interrupt |
2230 | /** |
| 2231 | * @brief This section Configure source input for the EXTI external interrupt . |
2231 | * @brief Configure source input for the EXTI external interrupt. |
| 2232 | * @{ |
2232 | * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n |
| 2233 | */ |
2233 | * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n |
| 2234 | 2234 | * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n |
|
| 2235 | /** |
2235 | * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource |
| 2236 | * @brief Configure source input for the EXTI external interrupt. |
2236 | * @param Port This parameter can be one of the following values: |
| 2237 | * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_SetEXTISource\n |
2237 | * @arg @ref LL_GPIO_AF_EXTI_PORTA |
| 2238 | * AFIO_EXTICR2 EXTIx LL_GPIO_AF_SetEXTISource\n |
2238 | * @arg @ref LL_GPIO_AF_EXTI_PORTB |
| 2239 | * AFIO_EXTICR3 EXTIx LL_GPIO_AF_SetEXTISource\n |
2239 | * @arg @ref LL_GPIO_AF_EXTI_PORTC |
| 2240 | * AFIO_EXTICR4 EXTIx LL_GPIO_AF_SetEXTISource |
2240 | * @arg @ref LL_GPIO_AF_EXTI_PORTD |
| 2241 | * @param Port This parameter can be one of the following values: |
2241 | * @arg @ref LL_GPIO_AF_EXTI_PORTE |
| 2242 | * @arg @ref LL_GPIO_AF_EXTI_PORTA |
2242 | * @arg @ref LL_GPIO_AF_EXTI_PORTF |
| 2243 | * @arg @ref LL_GPIO_AF_EXTI_PORTB |
2243 | * @arg @ref LL_GPIO_AF_EXTI_PORTG |
| 2244 | * @arg @ref LL_GPIO_AF_EXTI_PORTC |
2244 | * @param Line This parameter can be one of the following values: |
| 2245 | * @arg @ref LL_GPIO_AF_EXTI_PORTD |
2245 | * @arg @ref LL_GPIO_AF_EXTI_LINE0 |
| 2246 | * @arg @ref LL_GPIO_AF_EXTI_PORTE |
2246 | * @arg @ref LL_GPIO_AF_EXTI_LINE1 |
| 2247 | * @arg @ref LL_GPIO_AF_EXTI_PORTF |
2247 | * @arg @ref LL_GPIO_AF_EXTI_LINE2 |
| 2248 | * @arg @ref LL_GPIO_AF_EXTI_PORTG |
2248 | * @arg @ref LL_GPIO_AF_EXTI_LINE3 |
| 2249 | * @param Line This parameter can be one of the following values: |
2249 | * @arg @ref LL_GPIO_AF_EXTI_LINE4 |
| 2250 | * @arg @ref LL_GPIO_AF_EXTI_LINE0 |
2250 | * @arg @ref LL_GPIO_AF_EXTI_LINE5 |
| 2251 | * @arg @ref LL_GPIO_AF_EXTI_LINE1 |
2251 | * @arg @ref LL_GPIO_AF_EXTI_LINE6 |
| 2252 | * @arg @ref LL_GPIO_AF_EXTI_LINE2 |
2252 | * @arg @ref LL_GPIO_AF_EXTI_LINE7 |
| 2253 | * @arg @ref LL_GPIO_AF_EXTI_LINE3 |
2253 | * @arg @ref LL_GPIO_AF_EXTI_LINE8 |
| 2254 | * @arg @ref LL_GPIO_AF_EXTI_LINE4 |
2254 | * @arg @ref LL_GPIO_AF_EXTI_LINE9 |
| 2255 | * @arg @ref LL_GPIO_AF_EXTI_LINE5 |
2255 | * @arg @ref LL_GPIO_AF_EXTI_LINE10 |
| 2256 | * @arg @ref LL_GPIO_AF_EXTI_LINE6 |
2256 | * @arg @ref LL_GPIO_AF_EXTI_LINE11 |
| 2257 | * @arg @ref LL_GPIO_AF_EXTI_LINE7 |
2257 | * @arg @ref LL_GPIO_AF_EXTI_LINE12 |
| 2258 | * @arg @ref LL_GPIO_AF_EXTI_LINE8 |
2258 | * @arg @ref LL_GPIO_AF_EXTI_LINE13 |
| 2259 | * @arg @ref LL_GPIO_AF_EXTI_LINE9 |
2259 | * @arg @ref LL_GPIO_AF_EXTI_LINE14 |
| 2260 | * @arg @ref LL_GPIO_AF_EXTI_LINE10 |
2260 | * @arg @ref LL_GPIO_AF_EXTI_LINE15 |
| 2261 | * @arg @ref LL_GPIO_AF_EXTI_LINE11 |
2261 | * @retval None |
| 2262 | * @arg @ref LL_GPIO_AF_EXTI_LINE12 |
2262 | */ |
| 2263 | * @arg @ref LL_GPIO_AF_EXTI_LINE13 |
2263 | __STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line) |
| 2264 | * @arg @ref LL_GPIO_AF_EXTI_LINE14 |
2264 | { |
| 2265 | * @arg @ref LL_GPIO_AF_EXTI_LINE15 |
2265 | MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16))); |
| 2266 | * @retval None |
2266 | } |
| 2267 | */ |
2267 | |
| 2268 | __STATIC_INLINE void LL_GPIO_AF_SetEXTISource(uint32_t Port, uint32_t Line) |
2268 | /** |
| 2269 | { |
2269 | * @brief Get the configured defined for specific EXTI Line |
| 2270 | MODIFY_REG(AFIO->EXTICR[Line & 0xFF], (Line >> 16), Port << POSITION_VAL((Line >> 16))); |
2270 | * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n |
| 2271 | } |
2271 | * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n |
| 2272 | 2272 | * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n |
|
| 2273 | /** |
2273 | * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource |
| 2274 | * @brief Get the configured defined for specific EXTI Line |
2274 | * @param Line This parameter can be one of the following values: |
| 2275 | * @rmtoll AFIO_EXTICR1 EXTIx LL_GPIO_AF_GetEXTISource\n |
2275 | * @arg @ref LL_GPIO_AF_EXTI_LINE0 |
| 2276 | * AFIO_EXTICR2 EXTIx LL_GPIO_AF_GetEXTISource\n |
2276 | * @arg @ref LL_GPIO_AF_EXTI_LINE1 |
| 2277 | * AFIO_EXTICR3 EXTIx LL_GPIO_AF_GetEXTISource\n |
2277 | * @arg @ref LL_GPIO_AF_EXTI_LINE2 |
| 2278 | * AFIO_EXTICR4 EXTIx LL_GPIO_AF_GetEXTISource |
2278 | * @arg @ref LL_GPIO_AF_EXTI_LINE3 |
| 2279 | * @param Line This parameter can be one of the following values: |
2279 | * @arg @ref LL_GPIO_AF_EXTI_LINE4 |
| 2280 | * @arg @ref LL_GPIO_AF_EXTI_LINE0 |
2280 | * @arg @ref LL_GPIO_AF_EXTI_LINE5 |
| 2281 | * @arg @ref LL_GPIO_AF_EXTI_LINE1 |
2281 | * @arg @ref LL_GPIO_AF_EXTI_LINE6 |
| 2282 | * @arg @ref LL_GPIO_AF_EXTI_LINE2 |
2282 | * @arg @ref LL_GPIO_AF_EXTI_LINE7 |
| 2283 | * @arg @ref LL_GPIO_AF_EXTI_LINE3 |
2283 | * @arg @ref LL_GPIO_AF_EXTI_LINE8 |
| 2284 | * @arg @ref LL_GPIO_AF_EXTI_LINE4 |
2284 | * @arg @ref LL_GPIO_AF_EXTI_LINE9 |
| 2285 | * @arg @ref LL_GPIO_AF_EXTI_LINE5 |
2285 | * @arg @ref LL_GPIO_AF_EXTI_LINE10 |
| 2286 | * @arg @ref LL_GPIO_AF_EXTI_LINE6 |
2286 | * @arg @ref LL_GPIO_AF_EXTI_LINE11 |
| 2287 | * @arg @ref LL_GPIO_AF_EXTI_LINE7 |
2287 | * @arg @ref LL_GPIO_AF_EXTI_LINE12 |
| 2288 | * @arg @ref LL_GPIO_AF_EXTI_LINE8 |
2288 | * @arg @ref LL_GPIO_AF_EXTI_LINE13 |
| 2289 | * @arg @ref LL_GPIO_AF_EXTI_LINE9 |
2289 | * @arg @ref LL_GPIO_AF_EXTI_LINE14 |
| 2290 | * @arg @ref LL_GPIO_AF_EXTI_LINE10 |
2290 | * @arg @ref LL_GPIO_AF_EXTI_LINE15 |
| 2291 | * @arg @ref LL_GPIO_AF_EXTI_LINE11 |
2291 | * @retval Returned value can be one of the following values: |
| 2292 | * @arg @ref LL_GPIO_AF_EXTI_LINE12 |
2292 | * @arg @ref LL_GPIO_AF_EXTI_PORTA |
| 2293 | * @arg @ref LL_GPIO_AF_EXTI_LINE13 |
2293 | * @arg @ref LL_GPIO_AF_EXTI_PORTB |
| 2294 | * @arg @ref LL_GPIO_AF_EXTI_LINE14 |
2294 | * @arg @ref LL_GPIO_AF_EXTI_PORTC |
| 2295 | * @arg @ref LL_GPIO_AF_EXTI_LINE15 |
2295 | * @arg @ref LL_GPIO_AF_EXTI_PORTD |
| 2296 | * @retval Returned value can be one of the following values: |
2296 | * @arg @ref LL_GPIO_AF_EXTI_PORTE |
| 2297 | * @arg @ref LL_GPIO_AF_EXTI_PORTA |
2297 | * @arg @ref LL_GPIO_AF_EXTI_PORTF |
| 2298 | * @arg @ref LL_GPIO_AF_EXTI_PORTB |
2298 | * @arg @ref LL_GPIO_AF_EXTI_PORTG |
| 2299 | * @arg @ref LL_GPIO_AF_EXTI_PORTC |
2299 | */ |
| 2300 | * @arg @ref LL_GPIO_AF_EXTI_PORTD |
2300 | __STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line) |
| 2301 | * @arg @ref LL_GPIO_AF_EXTI_PORTE |
2301 | { |
| 2302 | * @arg @ref LL_GPIO_AF_EXTI_PORTF |
2302 | return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16)); |
| 2303 | * @arg @ref LL_GPIO_AF_EXTI_PORTG |
2303 | } |
| 2304 | */ |
2304 | |
| 2305 | __STATIC_INLINE uint32_t LL_GPIO_AF_GetEXTISource(uint32_t Line) |
2305 | /** |
| 2306 | { |
2306 | * @} |
| 2307 | return (uint32_t)(READ_BIT(AFIO->EXTICR[Line & 0xFF], (Line >> 16)) >> POSITION_VAL(Line >> 16)); |
2307 | */ |
| 2308 | } |
2308 | |
| 2309 | 2309 | #if defined(USE_FULL_LL_DRIVER) |
|
| 2310 | /** |
2310 | /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions |
| 2311 | * @} |
2311 | * @{ |
| 2312 | */ |
2312 | */ |
| 2313 | 2313 | ||
| 2314 | #if defined(USE_FULL_LL_DRIVER) |
2314 | ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); |
| 2315 | /** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions |
2315 | ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); |
| 2316 | * @{ |
2316 | void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); |
| 2317 | */ |
2317 | |
| 2318 | 2318 | /** |
|
| 2319 | ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); |
2319 | * @} |
| 2320 | ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); |
2320 | */ |
| 2321 | void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); |
2321 | #endif /* USE_FULL_LL_DRIVER */ |
| 2322 | 2322 | ||
| 2323 | /** |
2323 | /** |
| 2324 | * @} |
2324 | * @} |
| 2325 | */ |
2325 | */ |
| 2326 | #endif /* USE_FULL_LL_DRIVER */ |
2326 | |
| 2327 | 2327 | /** |
|
| 2328 | /** |
2328 | * @} |
| 2329 | * @} |
2329 | */ |
| 2330 | */ |
2330 | |
| 2331 | 2331 | #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */ |
|
| 2332 | /** |
2332 | /** |
| 2333 | * @} |
2333 | * @} |
| 2334 | */ |
2334 | */ |
| 2335 | 2335 | ||
| 2336 | #endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) */ |
2336 | #ifdef __cplusplus |
| 2337 | /** |
2337 | } |
| 2338 | * @} |
2338 | #endif |
| 2339 | */ |
2339 | |
| 2340 | 2340 | #endif /* STM32F1xx_LL_GPIO_H */ |
|
| 2341 | #ifdef __cplusplus |
2341 | |
| 2342 | } |
- | |
| 2343 | #endif |
- | |
| 2344 | - | ||
| 2345 | #endif /* STM32F1xx_LL_GPIO_H */ |
- | |
| 2346 | - | ||
| 2347 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |