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Line 4... Line 4...
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   Header file of GPIO LL module.
 5 
  * @brief   Header file of GPIO LL module.
6 
  ******************************************************************************
 6 
  ******************************************************************************
7 
  * @attention
 7 
  * @attention
8 
  *
 8 
  *
9 
  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
 9 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
- 
 
 10 
  * All rights reserved.</center></h2>
10 
  *
 11 
  *
11 
  * Redistribution and use in source and binary forms, with or without modification,
 12 
  * This software component is licensed by ST under BSD 3-Clause license,
12 
  * are permitted provided that the following conditions are met:
 13 
  * the "License"; You may not use this file except in compliance with the
13 
  *   1. Redistributions of source code must retain the above copyright notice,
 - 
 
14 
  *      this list of conditions and the following disclaimer.
 - 
 
15 
  *   2. Redistributions in binary form must reproduce the above copyright notice,
 - 
 
16 
  *      this list of conditions and the following disclaimer in the documentation
 - 
 
17 
  *      and/or other materials provided with the distribution.
 14 
  * License. You may obtain a copy of the License at:
18 
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
 - 
 
19 
  *      may be used to endorse or promote products derived from this software
 15 
  *                        opensource.org/licenses/BSD-3-Clause
20 
  *      without specific prior written permission.
 - 
 
21 
  *
 - 
 
22 
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 - 
 
23 
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 - 
 
24 
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 - 
 
25 
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 - 
 
26 
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 - 
 
27 
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 - 
 
28 
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 - 
 
29 
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 - 
 
30 
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 - 
 
31 
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 - 
 
32 
  *
 16 
  *
33 
  ******************************************************************************
 17 
  ******************************************************************************
34 
  */
 18 
  */
35 
 
 19 
 
36 
/* Define to prevent recursive inclusion -------------------------------------*/
 20 
/* Define to prevent recursive inclusion -------------------------------------*/
37 
#ifndef __STM32F1xx_LL_GPIO_H
 21 
#ifndef STM32F1xx_LL_GPIO_H
38 
#define __STM32F1xx_LL_GPIO_H
 22 
#define STM32F1xx_LL_GPIO_H
39 
 
 23 
 
40 
#ifdef __cplusplus
 24 
#ifdef __cplusplus
41 
extern "C" {
 25 
extern "C" {
42 
#endif
 26 
#endif
43 
 
 27 
 
Line 355... Line 339...
355 
  *         @arg @ref LL_GPIO_MODE_ALTERNATE
 339 
  *         @arg @ref LL_GPIO_MODE_ALTERNATE
356 
  * @retval None
 340 
  * @retval None
357 
  */
 341 
  */
358 
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
 342 
__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)
359 
{
 343 
{
360 
  register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
 344 
  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
361 
  MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
 345 
  MODIFY_REG(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U)), (Mode << (POSITION_VAL(Pin) * 4U)));
362 
}
 346 
}
363 
 
 347 
 
364 
/**
 348 
/**
365 
  * @brief  Return gpio mode for a dedicated pin on dedicated port.
 349 
  * @brief  Return gpio mode for a dedicated pin on dedicated port.
Line 395... Line 379...
395 
  *         @arg @ref LL_GPIO_MODE_OUTPUT
 379 
  *         @arg @ref LL_GPIO_MODE_OUTPUT
396 
  *         @arg @ref LL_GPIO_MODE_ALTERNATE
 380 
  *         @arg @ref LL_GPIO_MODE_ALTERNATE
397 
  */
 381 
  */
398 
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
 382 
__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)
399 
{
 383 
{
400 
  register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
 384 
  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
401 
  return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
 385 
  return (READ_BIT(*pReg, ((GPIO_CRL_CNF0 | GPIO_CRL_MODE0) << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
402 
}
 386 
}
403 
 
 387 
 
404 
/**
 388 
/**
405 
  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
 389 
  * @brief  Configure gpio speed for a dedicated pin on dedicated port.
Line 433... Line 417...
433 
  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
 417 
  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
434 
  * @retval None
 418 
  * @retval None
435 
  */
 419 
  */
436 
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
 420 
__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)
437 
{
 421 
{
438 
  register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
 422 
  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
439 
  MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
 423 
  MODIFY_REG(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U)),
440 
             (Speed << (POSITION_VAL(Pin) * 4U)));
 424 
             (Speed << (POSITION_VAL(Pin) * 4U)));
441 
}
 425 
}
442 
 
 426 
 
443 
/**
 427 
/**
Line 471... Line 455...
471 
  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
 455 
  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM
472 
  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
 456 
  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH
473 
  */
 457 
  */
474 
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
 458 
__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)
475 
{
 459 
{
476 
  register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
 460 
  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
477 
  return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
 461 
  return (READ_BIT(*pReg, (GPIO_CRL_MODE0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
478 
}
 462 
}
479 
 
 463 
 
480 
/**
 464 
/**
481 
  * @brief  Configure gpio output type for several pins on dedicated port.
 465 
  * @brief  Configure gpio output type for several pins on dedicated port.
Line 507... Line 491...
507 
  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
 491 
  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
508 
  * @retval None
 492 
  * @retval None
509 
  */
 493 
  */
510 
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
 494 
__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t OutputType)
511 
{
 495 
{
512 
  register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
 496 
  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
513 
  MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
 497 
  MODIFY_REG(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U)),
514 
             (OutputType << (POSITION_VAL(Pin) * 4U)));
 498 
             (OutputType << (POSITION_VAL(Pin) * 4U)));
515 
}
 499 
}
516 
 
 500 
 
517 
/**
 501 
/**
Line 544... Line 528...
544 
  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
 528 
  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL
545 
  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
 529 
  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN
546 
  */
 530 
  */
547 
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
 531 
__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)
548 
{
 532 
{
549 
  register uint32_t *pReg = (uint32_t *)((uint32_t)(&GPIOx->CRL) + (Pin >> 24));
 533 
  register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&GPIOx->CRL) + (Pin >> 24)));
550 
  return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
 534 
  return (READ_BIT(*pReg, (GPIO_CRL_CNF0_0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U));
551 
 
 535 
 
552 
}
 536 
}
553 
 
 537 
 
554 
/**
 538 
/**
Line 875... Line 859...
875 
  *         @arg @ref LL_GPIO_PIN_ALL
 859 
  *         @arg @ref LL_GPIO_PIN_ALL
876 
  * @retval None
 860 
  * @retval None
877 
  */
 861 
  */
878 
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
 862 
__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)
879 
{
 863 
{
- 
 
 864 
  uint32_t odr = READ_REG(GPIOx->ODR);
880 
  WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU));
 865 
  uint32_t pinmask = ((PinMask >> GPIO_PIN_MASK_POS) & 0x0000FFFFU);
- 
 
 866 
  WRITE_REG(GPIOx->BSRR, ((odr & pinmask) << 16u) | (~odr & pinmask));
881 
}
 867 
}
882 
 
 868 
 
883 
/**
 869 
/**
884 
  * @}
 870 
  * @}
885 
  */
 871 
  */
Line 895... Line 881...
895 
  * @note   ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
 881 
  * @note   ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5)
896 
  * @retval None
 882 
  * @retval None
897 
  */
 883 
  */
898 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
 884 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI1(void)
899 
{
 885 
{
900 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
 886 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG);
901 
}
 887 
}
902 
 
 888 
 
903 
/**
 889 
/**
904 
  * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
 890 
  * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI.
905 
  * @rmtoll MAPR          SPI1_REMAP           LL_GPIO_AF_DisableRemap_SPI1
 891 
  * @rmtoll MAPR          SPI1_REMAP           LL_GPIO_AF_DisableRemap_SPI1
906 
  * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
 892 
  * @note  DISABLE: No remap (NSS/PA4,  SCK/PA5, MISO/PA6, MOSI/PA7)
907 
  * @retval None
 893 
  * @retval None
908 
  */
 894 
  */
909 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
 895 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI1(void)
910 
{
 896 
{
911 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI1_REMAP);
 897 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
912 
}
 898 
}
913 
 
 899 
 
914 
/**
 900 
/**
915 
  * @brief  Check if SPI1 has been remaped or not
 901 
  * @brief  Check if SPI1 has been remaped or not
916 
  * @rmtoll MAPR         SPI1_REMAP         LL_GPIO_AF_IsEnabledRemap_SPI1
 902 
  * @rmtoll MAPR         SPI1_REMAP         LL_GPIO_AF_IsEnabledRemap_SPI1
Line 927... Line 913...
927 
  * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
 913 
  * @note  ENABLE: Remap     (SCL/PB8, SDA/PB9)
928 
  * @retval None
 914 
  * @retval None
929 
  */
 915 
  */
930 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
 916 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_I2C1(void)
931 
{
 917 
{
932 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
 918 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG);
933 
}
 919 
}
934 
 
 920 
 
935 
/**
 921 
/**
936 
  * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
 922 
  * @brief Disable the remapping of I2C1 alternate function SCL and SDA.
937 
  * @rmtoll MAPR          I2C1_REMAP           LL_GPIO_AF_DisableRemap_I2C1
 923 
  * @rmtoll MAPR          I2C1_REMAP           LL_GPIO_AF_DisableRemap_I2C1
938 
  * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
 924 
  * @note  DISABLE: No remap (SCL/PB6, SDA/PB7)
939 
  * @retval None
 925 
  * @retval None
940 
  */
 926 
  */
941 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
 927 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_I2C1(void)
942 
{
 928 
{
943 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_I2C1_REMAP);
 929 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_I2C1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
944 
}
 930 
}
945 
 
 931 
 
946 
/**
 932 
/**
947 
  * @brief  Check if I2C1 has been remaped or not
 933 
  * @brief  Check if I2C1 has been remaped or not
948 
  * @rmtoll MAPR         I2C1_REMAP         LL_GPIO_AF_IsEnabledRemap_I2C1
 934 
  * @rmtoll MAPR         I2C1_REMAP         LL_GPIO_AF_IsEnabledRemap_I2C1
Line 959... Line 945...
959 
  * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
 945 
  * @note  ENABLE: Remap     (TX/PB6, RX/PB7)
960 
  * @retval None
 946 
  * @retval None
961 
  */
 947 
  */
962 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
 948 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART1(void)
963 
{
 949 
{
964 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
 950 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG);
965 
}
 951 
}
966 
 
 952 
 
967 
/**
 953 
/**
968 
  * @brief Disable the remapping of USART1 alternate function TX and RX.
 954 
  * @brief Disable the remapping of USART1 alternate function TX and RX.
969 
  * @rmtoll MAPR          USART1_REMAP           LL_GPIO_AF_DisableRemap_USART1
 955 
  * @rmtoll MAPR          USART1_REMAP           LL_GPIO_AF_DisableRemap_USART1
970 
  * @note  DISABLE: No remap (TX/PA9, RX/PA10)
 956 
  * @note  DISABLE: No remap (TX/PA9, RX/PA10)
971 
  * @retval None
 957 
  * @retval None
972 
  */
 958 
  */
973 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
 959 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART1(void)
974 
{
 960 
{
975 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART1_REMAP);
 961 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART1_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
976 
}
 962 
}
977 
 
 963 
 
978 
/**
 964 
/**
979 
  * @brief  Check if USART1 has been remaped or not
 965 
  * @brief  Check if USART1 has been remaped or not
980 
  * @rmtoll MAPR         USART1_REMAP         LL_GPIO_AF_IsEnabledRemap_USART1
 966 
  * @rmtoll MAPR         USART1_REMAP         LL_GPIO_AF_IsEnabledRemap_USART1
Line 991... Line 977...
991 
  * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
 977 
  * @note  ENABLE: Remap     (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7)
992 
  * @retval None
 978 
  * @retval None
993 
  */
 979 
  */
994 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
 980 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART2(void)
995 
{
 981 
{
996 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
 982 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG);
997 
}
 983 
}
998 
 
 984 
 
999 
/**
 985 
/**
1000 
  * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
 986 
  * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX.
1001 
  * @rmtoll MAPR          USART2_REMAP           LL_GPIO_AF_DisableRemap_USART2
 987 
  * @rmtoll MAPR          USART2_REMAP           LL_GPIO_AF_DisableRemap_USART2
1002 
  * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
 988 
  * @note  DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4)
1003 
  * @retval None
 989 
  * @retval None
1004 
  */
 990 
  */
1005 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
 991 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART2(void)
1006 
{
 992 
{
1007 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART2_REMAP);
 993 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1008 
}
 994 
}
1009 
 
 995 
 
1010 
/**
 996 
/**
1011 
  * @brief  Check if USART2 has been remaped or not
 997 
  * @brief  Check if USART2 has been remaped or not
1012 
  * @rmtoll MAPR         USART2_REMAP         LL_GPIO_AF_IsEnabledRemap_USART2
 998 
  * @rmtoll MAPR         USART2_REMAP         LL_GPIO_AF_IsEnabledRemap_USART2
Line 1024... Line 1010...
1024 
  * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
 1010 
  * @note  ENABLE: Full remap     (TX/PD8,  RX/PD9,  CK/PD10, CTS/PD11, RTS/PD12)
1025 
  * @retval None
 1011 
  * @retval None
1026 
  */
 1012 
  */
1027 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
 1013 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_USART3(void)
1028 
{
 1014 
{
1029 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
 - 
 
1030 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_FULLREMAP);
 1015 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1031 
}
 1016 
}
1032 
 
 1017 
 
1033 
/**
 1018 
/**
1034 
  * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
 1019 
  * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
1035 
  * @rmtoll MAPR          USART3_REMAP           LL_GPIO_AF_RemapPartial_USART3
 1020 
  * @rmtoll MAPR          USART3_REMAP           LL_GPIO_AF_RemapPartial_USART3
1036 
  * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
 1021 
  * @note  PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14)
1037 
  * @retval None
 1022 
  * @retval None
1038 
  */
 1023 
  */
1039 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
 1024 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial_USART3(void)
1040 
{
 1025 
{
1041 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
 - 
 
1042 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_PARTIALREMAP);
 1026 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
1043 
}
 1027 
}
1044 
 
 1028 
 
1045 
/**
 1029 
/**
1046 
  * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
 1030 
  * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX.
1047 
  * @rmtoll MAPR          USART3_REMAP           LL_GPIO_AF_DisableRemap_USART3
 1031 
  * @rmtoll MAPR          USART3_REMAP           LL_GPIO_AF_DisableRemap_USART3
1048 
  * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
 1032 
  * @note  DISABLE: No remap      (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14)
1049 
  * @retval None
 1033 
  * @retval None
1050 
  */
 1034 
  */
1051 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
 1035 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_USART3(void)
1052 
{
 1036 
{
1053 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP);
 - 
 
1054 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_USART3_REMAP_NOREMAP);
 1037 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_USART3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_USART3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1055 
}
 1038 
}
1056 
#endif
 1039 
#endif
1057 
 
 1040 
 
1058 
/**
 1041 
/**
1059 
  * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
 1042 
  * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
Line 1061... Line 1044...
1061 
  * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
 1044 
  * @note  ENABLE: Full remap     (ETR/PE7,  CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8,  CH2N/PE10, CH3N/PE12)
1062 
  * @retval None
 1045 
  * @retval None
1063 
  */
 1046 
  */
1064 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
 1047 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM1(void)
1065 
{
 1048 
{
1066 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
 - 
 
1067 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_FULLREMAP);
 1049 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1068 
}
 1050 
}
1069 
 
 1051 
 
1070 
/**
 1052 
/**
1071 
  * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
 1053 
  * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
1072 
  * @rmtoll MAPR          TIM1_REMAP           LL_GPIO_AF_RemapPartial_TIM1
 1054 
  * @rmtoll MAPR          TIM1_REMAP           LL_GPIO_AF_RemapPartial_TIM1
1073 
  * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
 1055 
  * @note  PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PA6,  CH1N/PA7,  CH2N/PB0,  CH3N/PB1)
1074 
  * @retval None
 1056 
  * @retval None
1075 
  */
 1057 
  */
1076 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
 1058 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM1(void)
1077 
{
 1059 
{
1078 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
 - 
 
1079 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_PARTIALREMAP);
 1060 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
1080 
}
 1061 
}
1081 
 
 1062 
 
1082 
/**
 1063 
/**
1083 
  * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
 1064 
  * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN)
1084 
  * @rmtoll MAPR          TIM1_REMAP           LL_GPIO_AF_DisableRemap_TIM1
 1065 
  * @rmtoll MAPR          TIM1_REMAP           LL_GPIO_AF_DisableRemap_TIM1
1085 
  * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
 1066 
  * @note  DISABLE: No remap      (ETR/PA12, CH1/PA8, CH2/PA9,  CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15)
1086 
  * @retval None
 1067 
  * @retval None
1087 
  */
 1068 
  */
1088 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
 1069 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM1(void)
1089 
{
 1070 
{
1090 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP);
 - 
 
1091 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM1_REMAP_NOREMAP);
 1071 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM1_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM1_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1092 
}
 1072 
}
1093 
 
 1073 
 
1094 
/**
 1074 
/**
1095 
  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
 1075 
  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1096 
  * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_EnableRemap_TIM2
 1076 
  * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_EnableRemap_TIM2
1097 
  * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
 1077 
  * @note  ENABLE: Full remap       (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11)
1098 
  * @retval None
 1078 
  * @retval None
1099 
  */
 1079 
  */
1100 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
 1080 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM2(void)
1101 
{
 1081 
{
1102 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
 - 
 
1103 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_FULLREMAP);
 1082 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1104 
}
 1083 
}
1105 
 
 1084 
 
1106 
/**
 1085 
/**
1107 
  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
 1086 
  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1108 
  * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_RemapPartial2_TIM2
 1087 
  * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_RemapPartial2_TIM2
1109 
  * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
 1088 
  * @note  PARTIAL_2: Partial remap (CH1/ETR/PA0,  CH2/PA1, CH3/PB10, CH4/PB11)
1110 
  * @retval None
 1089 
  * @retval None
1111 
  */
 1090 
  */
1112 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
 1091 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_TIM2(void)
1113 
{
 1092 
{
1114 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
 - 
 
1115 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2);
 1093 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 | AFIO_MAPR_SWJ_CFG));
1116 
}
 1094 
}
1117 
 
 1095 
 
1118 
/**
 1096 
/**
1119 
  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
 1097 
  * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1120 
  * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_RemapPartial1_TIM2
 1098 
  * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_RemapPartial1_TIM2
1121 
  * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
 1099 
  * @note  PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2,  CH4/PA3)
1122 
  * @retval None
 1100 
  * @retval None
1123 
  */
 1101 
  */
1124 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
 1102 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_TIM2(void)
1125 
{
 1103 
{
1126 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
 - 
 
1127 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1);
 1104 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 | AFIO_MAPR_SWJ_CFG));
1128 
}
 1105 
}
1129 
 
 1106 
 
1130 
/**
 1107 
/**
1131 
  * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
 1108 
  * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR)
1132 
  * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_DisableRemap_TIM2
 1109 
  * @rmtoll MAPR          TIM2_REMAP           LL_GPIO_AF_DisableRemap_TIM2
1133 
  * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
 1110 
  * @note  DISABLE: No remap        (CH1/ETR/PA0,  CH2/PA1, CH3/PA2,  CH4/PA3)
1134 
  * @retval None
 1111 
  * @retval None
1135 
  */
 1112 
  */
1136 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
 1113 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM2(void)
1137 
{
 1114 
{
1138 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP);
 - 
 
1139 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2_REMAP_NOREMAP);
 1115 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM2_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1140 
}
 1116 
}
1141 
 
 1117 
 
1142 
/**
 1118 
/**
1143 
  * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
 1119 
  * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
1144 
  * @rmtoll MAPR          TIM3_REMAP           LL_GPIO_AF_EnableRemap_TIM3
 1120 
  * @rmtoll MAPR          TIM3_REMAP           LL_GPIO_AF_EnableRemap_TIM3
Line 1146... Line 1122...
1146 
  * @note  TIM3_ETR on PE0 is not re-mapped.
 1122 
  * @note  TIM3_ETR on PE0 is not re-mapped.
1147 
  * @retval None
 1123 
  * @retval None
1148 
  */
 1124 
  */
1149 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
 1125 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM3(void)
1150 
{
 1126 
{
1151 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
 - 
 
1152 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_FULLREMAP);
 1127 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_FULLREMAP | AFIO_MAPR_SWJ_CFG));
1153 
}
 1128 
}
1154 
 
 1129 
 
1155 
/**
 1130 
/**
1156 
  * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
 1131 
  * @brief Enable the remapping of TIM3 alternate function channels 1 to 4
1157 
  * @rmtoll MAPR          TIM3_REMAP           LL_GPIO_AF_RemapPartial_TIM3
 1132 
  * @rmtoll MAPR          TIM3_REMAP           LL_GPIO_AF_RemapPartial_TIM3
Line 1159... Line 1134...
1159 
  * @note  TIM3_ETR on PE0 is not re-mapped.
 1134 
  * @note  TIM3_ETR on PE0 is not re-mapped.
1160 
  * @retval None
 1135 
  * @retval None
1161 
  */
 1136 
  */
1162 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
 1137 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial_TIM3(void)
1163 
{
 1138 
{
1164 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
 - 
 
1165 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_PARTIALREMAP);
 1139 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG));
1166 
}
 1140 
}
1167 
 
 1141 
 
1168 
/**
 1142 
/**
1169 
  * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
 1143 
  * @brief Disable the remapping of TIM3 alternate function channels 1 to 4
1170 
  * @rmtoll MAPR          TIM3_REMAP           LL_GPIO_AF_DisableRemap_TIM3
 1144 
  * @rmtoll MAPR          TIM3_REMAP           LL_GPIO_AF_DisableRemap_TIM3
Line 1172... Line 1146...
1172 
  * @note  TIM3_ETR on PE0 is not re-mapped.
 1146 
  * @note  TIM3_ETR on PE0 is not re-mapped.
1173 
  * @retval None
 1147 
  * @retval None
1174 
  */
 1148 
  */
1175 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
 1149 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM3(void)
1176 
{
 1150 
{
1177 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP);
 - 
 
1178 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM3_REMAP_NOREMAP);
 1151 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM3_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_TIM3_REMAP_NOREMAP | AFIO_MAPR_SWJ_CFG));
1179 
}
 1152 
}
1180 
 
 1153 
 
1181 
#if defined(AFIO_MAPR_TIM4_REMAP)
 1154 
#if defined(AFIO_MAPR_TIM4_REMAP)
1182 
/**
 1155 
/**
1183 
  * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
 1156 
  * @brief Enable the remapping of TIM4 alternate function channels 1 to 4.
Line 1186... Line 1159...
1186 
  * @note  TIM4_ETR on PE0 is not re-mapped.
 1159 
  * @note  TIM4_ETR on PE0 is not re-mapped.
1187 
  * @retval None
 1160 
  * @retval None
1188 
  */
 1161 
  */
1189 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
 1162 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM4(void)
1190 
{
 1163 
{
1191 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
 1164 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG);
1192 
}
 1165 
}
1193 
/**
 1166 
/**
1194 
  * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
 1167 
  * @brief Disable the remapping of TIM4 alternate function channels 1 to 4.
1195 
  * @rmtoll MAPR          TIM4_REMAP           LL_GPIO_AF_DisableRemap_TIM4
 1168 
  * @rmtoll MAPR          TIM4_REMAP           LL_GPIO_AF_DisableRemap_TIM4
1196 
  * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
 1169 
  * @note  DISABLE: No remap  (TIM4_CH1/PB6,  TIM4_CH2/PB7,  TIM4_CH3/PB8,  TIM4_CH4/PB9)
1197 
  * @note  TIM4_ETR on PE0 is not re-mapped.
 1170 
  * @note  TIM4_ETR on PE0 is not re-mapped.
1198 
  * @retval None
 1171 
  * @retval None
1199 
  */
 1172 
  */
1200 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
 1173 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM4(void)
1201 
{
 1174 
{
1202 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM4_REMAP);
 1175 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM4_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1203 
}
 1176 
}
1204 
 
 1177 
 
1205 
/**
 1178 
/**
1206 
  * @brief  Check if TIM4 has been remaped or not
 1179 
  * @brief  Check if TIM4 has been remaped or not
1207 
  * @rmtoll MAPR         TIM4_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM4
 1180 
  * @rmtoll MAPR         TIM4_REMAP         LL_GPIO_AF_IsEnabledRemap_TIM4
Line 1221... Line 1194...
1221 
  * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
 1194 
  * @note  CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12
1222 
  * @retval None
 1195 
  * @retval None
1223 
  */
 1196 
  */
1224 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
 1197 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial1_CAN1(void)
1225 
{
 1198 
{
1226 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
 - 
 
1227 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP1);
 1199 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP1 | AFIO_MAPR_SWJ_CFG));
1228 
}
 1200 
}
1229 
 
 1201 
 
1230 
/**
 1202 
/**
1231 
  * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
 1203 
  * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
1232 
  * @rmtoll MAPR          CAN_REMAP           LL_GPIO_AF_RemapPartial2_CAN1
 1204 
  * @rmtoll MAPR          CAN_REMAP           LL_GPIO_AF_RemapPartial2_CAN1
1233 
  * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
 1205 
  * @note  CASE 2: CAN_RX mapped to PB8,  CAN_TX mapped to PB9 (not available on 36-pin package)
1234 
  * @retval None
 1206 
  * @retval None
1235 
  */
 1207 
  */
1236 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
 1208 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial2_CAN1(void)
1237 
{
 1209 
{
1238 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
 - 
 
1239 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP2);
 1210 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP2 | AFIO_MAPR_SWJ_CFG));
1240 
}
 1211 
}
1241 
 
 1212 
 
1242 
/**
 1213 
/**
1243 
  * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
 1214 
  * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface.
1244 
  * @rmtoll MAPR          CAN_REMAP           LL_GPIO_AF_RemapPartial3_CAN1
 1215 
  * @rmtoll MAPR          CAN_REMAP           LL_GPIO_AF_RemapPartial3_CAN1
1245 
  * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
 1216 
  * @note  CASE 3: CAN_RX mapped to PD0,  CAN_TX mapped to PD1
1246 
  * @retval None
 1217 
  * @retval None
1247 
  */
 1218 
  */
1248 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
 1219 
__STATIC_INLINE void LL_GPIO_AF_RemapPartial3_CAN1(void)
1249 
{
 1220 
{
1250 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP);
 - 
 
1251 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN_REMAP_REMAP3);
 1221 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN_REMAP | AFIO_MAPR_SWJ_CFG), (AFIO_MAPR_CAN_REMAP_REMAP3 | AFIO_MAPR_SWJ_CFG));
1252 
}
 1222 
}
1253 
#endif
 1223 
#endif
1254 
 
 1224 
 
1255 
/**
 1225 
/**
1256 
  * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
 1226 
  * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used
Line 1261... Line 1231...
1261 
  * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
 1231 
  * @note  ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT.
1262 
  * @retval None
 1232 
  * @retval None
1263 
  */
 1233 
  */
1264 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
 1234 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_PD01(void)
1265 
{
 1235 
{
1266 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
 1236 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG);
1267 
}
 1237 
}
1268 
 
 1238 
 
1269 
/**
 1239 
/**
1270 
  * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
 1240 
  * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used
1271 
  *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
 1241 
  *        (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and
Line 1275... Line 1245...
1275 
  * @note  DISABLE: No remapping of PD0 and PD1
 1245 
  * @note  DISABLE: No remapping of PD0 and PD1
1276 
  * @retval None
 1246 
  * @retval None
1277 
  */
 1247 
  */
1278 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
 1248 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_PD01(void)
1279 
{
 1249 
{
1280 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PD01_REMAP);
 1250 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PD01_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1281 
}
 1251 
}
1282 
 
 1252 
 
1283 
/**
 1253 
/**
1284 
  * @brief  Check if PD01 has been remaped or not
 1254 
  * @brief  Check if PD01 has been remaped or not
1285 
  * @rmtoll MAPR         PD01_REMAP         LL_GPIO_AF_IsEnabledRemap_PD01
 1255 
  * @rmtoll MAPR         PD01_REMAP         LL_GPIO_AF_IsEnabledRemap_PD01
Line 1298... Line 1268...
1298 
  * @note  This function is available only in high density value line devices.
 1268 
  * @note  This function is available only in high density value line devices.
1299 
  * @retval None
 1269 
  * @retval None
1300 
  */
 1270 
  */
1301 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
 1271 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_TIM5CH4(void)
1302 
{
 1272 
{
1303 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
 1273 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG);
1304 
}
 1274 
}
1305 
 
 1275 
 
1306 
/**
 1276 
/**
1307 
  * @brief Disable the remapping of TIM5CH4.
 1277 
  * @brief Disable the remapping of TIM5CH4.
1308 
  * @rmtoll MAPR          TIM5CH4_IREMAP           LL_GPIO_AF_DisableRemap_TIM5CH4
 1278 
  * @rmtoll MAPR          TIM5CH4_IREMAP           LL_GPIO_AF_DisableRemap_TIM5CH4
Line 1310... Line 1280...
1310 
  * @note  This function is available only in high density value line devices.
 1280 
  * @note  This function is available only in high density value line devices.
1311 
  * @retval None
 1281 
  * @retval None
1312 
  */
 1282 
  */
1313 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
 1283 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_TIM5CH4(void)
1314 
{
 1284 
{
1315 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM5CH4_IREMAP);
 1285 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM5CH4_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1316 
}
 1286 
}
1317 
 
 1287 
 
1318 
/**
 1288 
/**
1319 
  * @brief  Check if TIM5CH4 has been remaped or not
 1289 
  * @brief  Check if TIM5CH4 has been remaped or not
1320 
  * @rmtoll MAPR         TIM5CH4_IREMAP         LL_GPIO_AF_IsEnabledRemap_TIM5CH4
 1290 
  * @rmtoll MAPR         TIM5CH4_IREMAP         LL_GPIO_AF_IsEnabledRemap_TIM5CH4
Line 1334... Line 1304...
1334 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1304 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1335 
  * @retval None
 1305 
  * @retval None
1336 
  */
 1306 
  */
1337 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
 1307 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH(void)
1338 
{
 1308 
{
1339 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
 1309 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG);
1340 
}
 1310 
}
1341 
 
 1311 
 
1342 
/**
 1312 
/**
1343 
  * @brief Disable the remapping of Ethernet MAC connections with the PHY.
 1313 
  * @brief Disable the remapping of Ethernet MAC connections with the PHY.
1344 
  * @rmtoll MAPR          ETH_REMAP           LL_GPIO_AF_DisableRemap_ETH
 1314 
  * @rmtoll MAPR          ETH_REMAP           LL_GPIO_AF_DisableRemap_ETH
Line 1346... Line 1316...
1346 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1316 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1347 
  * @retval None
 1317 
  * @retval None
1348 
  */
 1318 
  */
1349 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
 1319 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH(void)
1350 
{
 1320 
{
1351 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ETH_REMAP);
 1321 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ETH_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1352 
}
 1322 
}
1353 
 
 1323 
 
1354 
/**
 1324 
/**
1355 
  * @brief  Check if ETH has been remaped or not
 1325 
  * @brief  Check if ETH has been remaped or not
1356 
  * @rmtoll MAPR         ETH_REMAP         LL_GPIO_AF_IsEnabledRemap_ETH
 1326 
  * @rmtoll MAPR         ETH_REMAP         LL_GPIO_AF_IsEnabledRemap_ETH
Line 1371... Line 1341...
1371 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1341 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1372 
  * @retval None
 1342 
  * @retval None
1373 
  */
 1343 
  */
1374 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
 1344 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_CAN2(void)
1375 
{
 1345 
{
1376 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
 1346 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG);
1377 
}
 1347 
}
1378 
/**
 1348 
/**
1379 
  * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
 1349 
  * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX.
1380 
  * @rmtoll MAPR          CAN2_REMAP           LL_GPIO_AF_DisableRemap_CAN2
 1350 
  * @rmtoll MAPR          CAN2_REMAP           LL_GPIO_AF_DisableRemap_CAN2
1381 
  * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
 1351 
  * @note  DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13)
1382 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1352 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1383 
  * @retval None
 1353 
  * @retval None
1384 
  */
 1354 
  */
1385 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
 1355 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_CAN2(void)
1386 
{
 1356 
{
1387 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_CAN2_REMAP);
 1357 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_CAN2_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1388 
}
 1358 
}
1389 
 
 1359 
 
1390 
/**
 1360 
/**
1391 
  * @brief  Check if CAN2 has been remaped or not
 1361 
  * @brief  Check if CAN2 has been remaped or not
1392 
  * @rmtoll MAPR         CAN2_REMAP         LL_GPIO_AF_IsEnabledRemap_CAN2
 1362 
  * @rmtoll MAPR         CAN2_REMAP         LL_GPIO_AF_IsEnabledRemap_CAN2
Line 1406... Line 1376...
1406 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1376 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1407 
  * @retval None
 1377 
  * @retval None
1408 
  */
 1378 
  */
1409 
__STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
 1379 
__STATIC_INLINE void LL_GPIO_AF_Select_ETH_RMII(void)
1410 
{
 1380 
{
1411 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
 1381 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG);
1412 
}
 1382 
}
1413 
 
 1383 
 
1414 
/**
 1384 
/**
1415 
  * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
 1385 
  * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY.
1416 
  * @rmtoll MAPR          MII_RMII_SEL           LL_GPIO_AF_Select_ETH_MII
 1386 
  * @rmtoll MAPR          MII_RMII_SEL           LL_GPIO_AF_Select_ETH_MII
Line 1418... Line 1388...
1418 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1388 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1419 
  * @retval None
 1389 
  * @retval None
1420 
  */
 1390 
  */
1421 
__STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
 1391 
__STATIC_INLINE void LL_GPIO_AF_Select_ETH_MII(void)
1422 
{
 1392 
{
1423 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_MII_RMII_SEL);
 1393 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_MII_RMII_SEL | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1424 
}
 1394 
}
1425 
#endif
 1395 
#endif
1426 
 
 1396 
 
1427 
#if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
 1397 
#if defined(AFIO_MAPR_ADC1_ETRGINJ_REMAP)
1428 
/**
 1398 
/**
Line 1431... Line 1401...
1431 
  * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
 1401 
  * @note  ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4.
1432 
  * @retval None
 1402 
  * @retval None
1433 
  */
 1403 
  */
1434 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
 1404 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGINJ(void)
1435 
{
 1405 
{
1436 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
 1406 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG);
1437 
}
 1407 
}
1438 
 
 1408 
 
1439 
/**
 1409 
/**
1440 
  * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
 1410 
  * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion).
1441 
  * @rmtoll MAPR          ADC1_ETRGINJ_REMAP           LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
 1411 
  * @rmtoll MAPR          ADC1_ETRGINJ_REMAP           LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ
1442 
  * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
 1412 
  * @note  DISABLE: ADC1 External trigger injected conversion is connected to EXTI15
1443 
  * @retval None
 1413 
  * @retval None
1444 
  */
 1414 
  */
1445 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
 1415 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGINJ(void)
1446 
{
 1416 
{
1447 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGINJ_REMAP);
 1417 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1448 
}
 1418 
}
1449 
 
 1419 
 
1450 
/**
 1420 
/**
1451 
  * @brief  Check if ADC1_ETRGINJ has been remaped or not
 1421 
  * @brief  Check if ADC1_ETRGINJ has been remaped or not
1452 
  * @rmtoll MAPR         ADC1_ETRGINJ_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
 1422 
  * @rmtoll MAPR         ADC1_ETRGINJ_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGINJ
Line 1465... Line 1435...
1465 
  * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
 1435 
  * @note  ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0.
1466 
  * @retval None
 1436 
  * @retval None
1467 
  */
 1437 
  */
1468 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
 1438 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC1_ETRGREG(void)
1469 
{
 1439 
{
1470 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
 1440 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG);
1471 
}
 1441 
}
1472 
 
 1442 
 
1473 
/**
 1443 
/**
1474 
  * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
 1444 
  * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion).
1475 
  * @rmtoll MAPR          ADC1_ETRGREG_REMAP           LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
 1445 
  * @rmtoll MAPR          ADC1_ETRGREG_REMAP           LL_GPIO_AF_DisableRemap_ADC1_ETRGREG
1476 
  * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
 1446 
  * @note  DISABLE: ADC1 External trigger regular conversion is connected to EXTI11
1477 
  * @retval None
 1447 
  * @retval None
1478 
  */
 1448 
  */
1479 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
 1449 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC1_ETRGREG(void)
1480 
{
 1450 
{
1481 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC1_ETRGREG_REMAP);
 1451 
   MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC1_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1482 
}
 1452 
}
1483 
 
 1453 
 
1484 
/**
 1454 
/**
1485 
  * @brief  Check if ADC1_ETRGREG has been remaped or not
 1455 
  * @brief  Check if ADC1_ETRGREG has been remaped or not
1486 
  * @rmtoll MAPR         ADC1_ETRGREG_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
 1456 
  * @rmtoll MAPR         ADC1_ETRGREG_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC1_ETRGREG
Line 1500... Line 1470...
1500 
  * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
 1470 
  * @note  ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4.
1501 
  * @retval None
 1471 
  * @retval None
1502 
  */
 1472 
  */
1503 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
 1473 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGINJ(void)
1504 
{
 1474 
{
1505 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
 1475 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG);
1506 
}
 1476 
}
1507 
 
 1477 
 
1508 
/**
 1478 
/**
1509 
  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
 1479 
  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion).
1510 
  * @rmtoll MAPR          ADC2_ETRGINJ_REMAP           LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
 1480 
  * @rmtoll MAPR          ADC2_ETRGINJ_REMAP           LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ
1511 
  * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
 1481 
  * @note  DISABLE: ADC2 External trigger injected conversion is connected to EXTI15
1512 
  * @retval None
 1482 
  * @retval None
1513 
  */
 1483 
  */
1514 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
 1484 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGINJ(void)
1515 
{
 1485 
{
1516 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGINJ_REMAP);
 1486 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGINJ_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1517 
}
 1487 
}
1518 
 
 1488 
 
1519 
/**
 1489 
/**
1520 
  * @brief  Check if ADC2_ETRGINJ has been remaped or not
 1490 
  * @brief  Check if ADC2_ETRGINJ has been remaped or not
1521 
  * @rmtoll MAPR         ADC2_ETRGINJ_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
 1491 
  * @rmtoll MAPR         ADC2_ETRGINJ_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGINJ
Line 1535... Line 1505...
1535 
  * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
 1505 
  * @note  ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0.
1536 
  * @retval None
 1506 
  * @retval None
1537 
  */
 1507 
  */
1538 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
 1508 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ADC2_ETRGREG(void)
1539 
{
 1509 
{
1540 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
 1510 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG);
1541 
}
 1511 
}
1542 
 
 1512 
 
1543 
/**
 1513 
/**
1544 
  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
 1514 
  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1545 
  * @rmtoll MAPR          ADC2_ETRGREG_REMAP           LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
 1515 
  * @rmtoll MAPR          ADC2_ETRGREG_REMAP           LL_GPIO_AF_DisableRemap_ADC2_ETRGREG
1546 
  * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
 1516 
  * @note  DISABLE: ADC2 External trigger regular conversion is connected to EXTI11
1547 
  * @retval None
 1517 
  * @retval None
1548 
  */
 1518 
  */
1549 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
 1519 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ADC2_ETRGREG(void)
1550 
{
 1520 
{
1551 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_ADC2_ETRGREG_REMAP);
 1521 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_ADC2_ETRGREG_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1552 
}
 1522 
}
1553 
 
 1523 
 
1554 
/**
 1524 
/**
1555 
  * @brief  Check if ADC2_ETRGREG has been remaped or not
 1525 
  * @brief  Check if ADC2_ETRGREG has been remaped or not
1556 
  * @rmtoll MAPR         ADC2_ETRGREG_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
 1526 
  * @rmtoll MAPR         ADC2_ETRGREG_REMAP         LL_GPIO_AF_IsEnabledRemap_ADC2_ETRGREG
Line 1619... Line 1589...
1619 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1589 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1620 
  * @retval None
 1590 
  * @retval None
1621 
  */
 1591 
  */
1622 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
 1592 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_SPI3(void)
1623 
{
 1593 
{
1624 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
 1594 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG);
1625 
}
 1595 
}
1626 
 
 1596 
 
1627 
/**
 1597 
/**
1628 
  * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
 1598 
  * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD.
1629 
  * @rmtoll MAPR          SPI3_REMAP           LL_GPIO_AF_DisableRemap_SPI3
 1599 
  * @rmtoll MAPR          SPI3_REMAP           LL_GPIO_AF_DisableRemap_SPI3
Line 1631... Line 1601...
1631 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1601 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1632 
  * @retval None
 1602 
  * @retval None
1633 
  */
 1603 
  */
1634 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
 1604 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_SPI3(void)
1635 
{
 1605 
{
1636 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_SPI3_REMAP);
 1606 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_SPI3_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1637 
}
 1607 
}
1638 
 
 1608 
 
1639 
/**
 1609 
/**
1640 
  * @brief  Check if SPI3 has been remaped or not
 1610 
  * @brief  Check if SPI3 has been remaped or not
1641 
  * @rmtoll MAPR         SPI3_REMAP         LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
 1611 
  * @rmtoll MAPR         SPI3_REMAP         LL_GPIO_AF_IsEnabledRemap_SPI3_REMAP
Line 1656... Line 1626...
1656 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1626 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1657 
  * @retval None
 1627 
  * @retval None
1658 
  */
 1628 
  */
1659 
__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
 1629 
__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_USB(void)
1660 
{
 1630 
{
1661 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
 1631 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG);
1662 
}
 1632 
}
1663 
 
 1633 
 
1664 
/**
 1634 
/**
1665 
  * @brief Control of TIM2_ITR1 internal mapping.
 1635 
  * @brief Control of TIM2_ITR1 internal mapping.
1666 
  * @rmtoll MAPR          TIM2ITR1_IREMAP           LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
 1636 
  * @rmtoll MAPR          TIM2ITR1_IREMAP           LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH
Line 1668... Line 1638...
1668 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1638 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1669 
  * @retval None
 1639 
  * @retval None
1670 
  */
 1640 
  */
1671 
__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
 1641 
__STATIC_INLINE void LL_GPIO_AF_Remap_TIM2ITR1_TO_ETH(void)
1672 
{
 1642 
{
1673 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_TIM2ITR1_IREMAP);
 1643 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_TIM2ITR1_IREMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1674 
}
 1644 
}
1675 
#endif
 1645 
#endif
1676 
 
 1646 
 
1677 
#if defined(AFIO_MAPR_PTP_PPS_REMAP)
 1647 
#if defined(AFIO_MAPR_PTP_PPS_REMAP)
1678 
 
 1648 
 
Line 1683... Line 1653...
1683 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1653 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1684 
  * @retval None
 1654 
  * @retval None
1685 
  */
 1655 
  */
1686 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
 1656 
__STATIC_INLINE void LL_GPIO_AF_EnableRemap_ETH_PTP_PPS(void)
1687 
{
 1657 
{
1688 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
 1658 
  SET_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG);
1689 
}
 1659 
}
1690 
 
 1660 
 
1691 
/**
 1661 
/**
1692 
  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
 1662 
  * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion).
1693 
  * @rmtoll MAPR          PTP_PPS_REMAP           LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
 1663 
  * @rmtoll MAPR          PTP_PPS_REMAP           LL_GPIO_AF_DisableRemap_ETH_PTP_PPS
Line 1695... Line 1665...
1695 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
 1665 
  * @note  This bit is available only in connectivity line devices and is reserved otherwise.
1696 
  * @retval None
 1666 
  * @retval None
1697 
  */
 1667 
  */
1698 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
 1668 
__STATIC_INLINE void LL_GPIO_AF_DisableRemap_ETH_PTP_PPS(void)
1699 
{
 1669 
{
1700 
  CLEAR_BIT(AFIO->MAPR, AFIO_MAPR_PTP_PPS_REMAP);
 1670 
  MODIFY_REG(AFIO->MAPR, (AFIO_MAPR_PTP_PPS_REMAP | AFIO_MAPR_SWJ_CFG), AFIO_MAPR_SWJ_CFG);
1701 
}
 1671 
}
1702 
#endif
 1672 
#endif
1703 
 
 1673 
 
1704 
#if defined(AFIO_MAPR2_TIM9_REMAP)
 1674 
#if defined(AFIO_MAPR2_TIM9_REMAP)
1705 
 
 1675 
 
Line 2370... Line 2340...
2370 
 
 2340 
 
2371 
#ifdef __cplusplus
 2341 
#ifdef __cplusplus
2372 
}
 2342 
}
2373 
#endif
 2343 
#endif
2374 
 
 2344 
 
2375 
#endif /* __STM32F1xx_LL_GPIO_H */
 2345 
#endif /* STM32F1xx_LL_GPIO_H */
2376 
 
 2346 
 
2377 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 2347 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/