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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_ll_fsmc.h |
3 | * @file stm32f1xx_ll_fsmc.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of FSMC HAL module. |
5 | * @brief Header file of FSMC HAL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef STM32F1xx_LL_FSMC_H |
| 21 | #ifndef STM32F1xx_LL_FSMC_H |
21 | #define STM32F1xx_LL_FSMC_H |
| 22 | #define STM32F1xx_LL_FSMC_H |
22 | |
| 23 | 23 | #ifdef __cplusplus |
|
| 24 | #ifdef __cplusplus |
24 | extern "C" { |
| 25 | extern "C" { |
25 | #endif |
| 26 | #endif |
26 | |
| 27 | 27 | /* Includes ------------------------------------------------------------------*/ |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | #include "stm32f1xx_hal_def.h" |
| 29 | #include "stm32f1xx_hal_def.h" |
29 | |
| 30 | 30 | /** @addtogroup STM32F1xx_HAL_Driver |
|
| 31 | /** @addtogroup STM32F1xx_HAL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | /** @addtogroup FSMC_LL |
|
| 35 | /** @addtogroup FSMC_LL |
35 | * @{ |
| 36 | * @{ |
36 | */ |
| 37 | */ |
37 | |
| 38 | 38 | /** @addtogroup FSMC_LL_Private_Macros |
|
| 39 | /** @addtogroup FSMC_LL_Private_Macros |
39 | * @{ |
| 40 | * @{ |
40 | */ |
| 41 | */ |
41 | #if defined(FSMC_BANK1) |
| 42 | #if defined(FSMC_BANK1) |
42 | |
| 43 | 43 | #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ |
|
| 44 | #define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_NORSRAM_BANK1) || \ |
44 | ((__BANK__) == FSMC_NORSRAM_BANK2) || \ |
| 45 | ((__BANK__) == FSMC_NORSRAM_BANK2) || \ |
45 | ((__BANK__) == FSMC_NORSRAM_BANK3) || \ |
| 46 | ((__BANK__) == FSMC_NORSRAM_BANK3) || \ |
46 | ((__BANK__) == FSMC_NORSRAM_BANK4)) |
| 47 | ((__BANK__) == FSMC_NORSRAM_BANK4)) |
47 | #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
| 48 | #define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \ |
48 | ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
| 49 | ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE)) |
49 | #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ |
| 50 | #define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \ |
50 | ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
| 51 | ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \ |
51 | ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) |
| 52 | ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR)) |
52 | #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
| 53 | #define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8) || \ |
53 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
| 54 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \ |
54 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
| 55 | ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32)) |
55 | #define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \ |
| 56 | #define IS_FSMC_PAGESIZE(__SIZE__) (((__SIZE__) == FSMC_PAGE_SIZE_NONE) || \ |
56 | ((__SIZE__) == FSMC_PAGE_SIZE_128) || \ |
| 57 | ((__SIZE__) == FSMC_PAGE_SIZE_128) || \ |
57 | ((__SIZE__) == FSMC_PAGE_SIZE_256) || \ |
| 58 | ((__SIZE__) == FSMC_PAGE_SIZE_256) || \ |
58 | ((__SIZE__) == FSMC_PAGE_SIZE_512) || \ |
| 59 | ((__SIZE__) == FSMC_PAGE_SIZE_512) || \ |
59 | ((__SIZE__) == FSMC_PAGE_SIZE_1024)) |
| 60 | ((__SIZE__) == FSMC_PAGE_SIZE_1024)) |
60 | #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ |
| 61 | #define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \ |
61 | ((__MODE__) == FSMC_ACCESS_MODE_B) || \ |
| 62 | ((__MODE__) == FSMC_ACCESS_MODE_B) || \ |
62 | ((__MODE__) == FSMC_ACCESS_MODE_C) || \ |
| 63 | ((__MODE__) == FSMC_ACCESS_MODE_C) || \ |
63 | ((__MODE__) == FSMC_ACCESS_MODE_D)) |
| 64 | ((__MODE__) == FSMC_ACCESS_MODE_D)) |
64 | #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
| 65 | #define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \ |
65 | ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
| 66 | ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE)) |
66 | #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
| 67 | #define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \ |
67 | ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
| 68 | ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH)) |
68 | #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ |
| 69 | #define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \ |
69 | ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) |
| 70 | ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) |
70 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
| 71 | #define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \ |
71 | ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) |
| 72 | ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) |
72 | #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ |
| 73 | #define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \ |
73 | ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) |
| 74 | ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE)) |
74 | #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
| 75 | #define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \ |
75 | ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) |
| 76 | ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) |
76 | #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ |
| 77 | #define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \ |
77 | ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) |
| 78 | ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE)) |
78 | #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
| 79 | #define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \ |
79 | ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
| 80 | ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE)) |
80 | #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) |
| 81 | #define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U)) |
81 | #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ |
| 82 | #define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \ |
82 | ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) |
| 83 | ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) |
83 | #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
| 84 | #define IS_FSMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \ |
84 | ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
| 85 | ((__CCLOCK__) == FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC)) |
85 | #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) |
| 86 | #define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U) |
86 | #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) |
| 87 | #define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U)) |
87 | #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) |
| 88 | #define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U)) |
88 | #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) |
| 89 | #define IS_FSMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U) |
89 | #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) |
| 90 | #define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U) |
90 | #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) |
| 91 | #define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U)) |
91 | #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) |
| 92 | #define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE) |
92 | #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) |
| 93 | #define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE) |
93 | |
| 94 | 94 | #endif /* FSMC_BANK1 */ |
|
| 95 | #endif /* FSMC_BANK1 */ |
95 | #if defined(FSMC_BANK3) |
| 96 | #if defined(FSMC_BANK3) |
96 | |
| 97 | 97 | #define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3) |
|
| 98 | #define IS_FSMC_NAND_BANK(__BANK__) ((__BANK__) == FSMC_NAND_BANK3) |
98 | #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ |
| 99 | #define IS_FSMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_DISABLE) || \ |
99 | ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) |
| 100 | ((__FEATURE__) == FSMC_NAND_PCC_WAIT_FEATURE_ENABLE)) |
100 | #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ |
| 101 | #define IS_FSMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_8) || \ |
101 | ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) |
| 102 | ((__WIDTH__) == FSMC_NAND_PCC_MEM_BUS_WIDTH_16)) |
102 | #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ |
| 103 | #define IS_FSMC_ECC_STATE(__STATE__) (((__STATE__) == FSMC_NAND_ECC_DISABLE) || \ |
103 | ((__STATE__) == FSMC_NAND_ECC_ENABLE)) |
| 104 | ((__STATE__) == FSMC_NAND_ECC_ENABLE)) |
104 | |
| 105 | 105 | #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
|
| 106 | #define IS_FSMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_256BYTE) || \ |
106 | ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
| 107 | ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_512BYTE) || \ |
107 | ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
| 108 | ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \ |
108 | ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
| 109 | ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \ |
109 | ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
| 110 | ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \ |
110 | ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
| 111 | ((__SIZE__) == FSMC_NAND_ECC_PAGE_SIZE_8192BYTE)) |
111 | #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) |
| 112 | #define IS_FSMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U) |
112 | #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) |
| 113 | #define IS_FSMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U) |
113 | #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) |
| 114 | #define IS_FSMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U) |
114 | #define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) |
| 115 | #define IS_FSMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U) |
115 | #define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) |
| 116 | #define IS_FSMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U) |
116 | #define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) |
| 117 | #define IS_FSMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U) |
117 | #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) |
| 118 | #define IS_FSMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NAND_DEVICE) |
118 | |
| 119 | 119 | #endif /* FSMC_BANK3 */ |
|
| 120 | #endif /* FSMC_BANK3 */ |
120 | #if defined(FSMC_BANK4) |
| 121 | #if defined(FSMC_BANK4) |
121 | #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) |
| 122 | #define IS_FSMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_PCCARD_DEVICE) |
122 | |
| 123 | 123 | #endif /* FSMC_BANK4 */ |
|
| 124 | #endif /* FSMC_BANK4 */ |
124 | |
| 125 | 125 | /** |
|
| 126 | /** |
126 | * @} |
| 127 | * @} |
127 | */ |
| 128 | */ |
128 | |
| 129 | 129 | /* Exported typedef ----------------------------------------------------------*/ |
|
| 130 | /* Exported typedef ----------------------------------------------------------*/ |
130 | |
| 131 | 131 | /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types |
|
| 132 | /** @defgroup FSMC_LL_Exported_typedef FSMC Low Layer Exported Types |
132 | * @{ |
| 133 | * @{ |
133 | */ |
| 134 | */ |
134 | |
| 135 | 135 | #if defined(FSMC_BANK1) |
|
| 136 | #if defined(FSMC_BANK1) |
136 | #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef |
| 137 | #define FSMC_NORSRAM_TypeDef FSMC_Bank1_TypeDef |
137 | #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef |
| 138 | #define FSMC_NORSRAM_EXTENDED_TypeDef FSMC_Bank1E_TypeDef |
138 | #endif /* FSMC_BANK1 */ |
| 139 | #endif /* FSMC_BANK1 */ |
139 | #if defined(FSMC_BANK3) |
| 140 | #if defined(FSMC_BANK3) |
140 | #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef |
| 141 | #define FSMC_NAND_TypeDef FSMC_Bank2_3_TypeDef |
141 | #endif /* FSMC_BANK3 */ |
| 142 | #endif /* FSMC_BANK3 */ |
142 | #if defined(FSMC_BANK4) |
| 143 | #if defined(FSMC_BANK4) |
143 | #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef |
| 144 | #define FSMC_PCCARD_TypeDef FSMC_Bank4_TypeDef |
144 | #endif /* FSMC_BANK4 */ |
| 145 | #endif /* FSMC_BANK4 */ |
145 | |
| 146 | 146 | #if defined(FSMC_BANK1) |
|
| 147 | #if defined(FSMC_BANK1) |
147 | #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
| 148 | #define FSMC_NORSRAM_DEVICE FSMC_Bank1 |
148 | #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
| 149 | #define FSMC_NORSRAM_EXTENDED_DEVICE FSMC_Bank1E |
149 | #endif /* FSMC_BANK1 */ |
| 150 | #endif /* FSMC_BANK1 */ |
150 | #if defined(FSMC_BANK3) |
| 151 | #if defined(FSMC_BANK3) |
151 | #define FSMC_NAND_DEVICE FSMC_Bank2_3 |
| 152 | #define FSMC_NAND_DEVICE FSMC_Bank2_3 |
152 | #endif /* FSMC_BANK3 */ |
| 153 | #endif /* FSMC_BANK3 */ |
153 | #if defined(FSMC_BANK4) |
| 154 | #if defined(FSMC_BANK4) |
154 | #define FSMC_PCCARD_DEVICE FSMC_Bank4 |
| 155 | #define FSMC_PCCARD_DEVICE FSMC_Bank4 |
155 | #endif /* FSMC_BANK4 */ |
| 156 | #endif /* FSMC_BANK4 */ |
156 | |
| 157 | 157 | #if defined(FSMC_BANK1) |
|
| 158 | #if defined(FSMC_BANK1) |
158 | /** |
| 159 | /** |
159 | * @brief FSMC NORSRAM Configuration Structure definition |
| 160 | * @brief FSMC NORSRAM Configuration Structure definition |
160 | */ |
| 161 | */ |
161 | typedef struct |
| 162 | typedef struct |
162 | { |
| 163 | { |
163 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
| 164 | uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. |
164 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
| 165 | This parameter can be a value of @ref FSMC_NORSRAM_Bank */ |
165 | |
| 166 | 166 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
|
| 167 | uint32_t DataAddressMux; /*!< Specifies whether the address and data values are |
167 | multiplexed on the data bus or not. |
| 168 | multiplexed on the data bus or not. |
168 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
| 169 | This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ |
169 | |
| 170 | 170 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
|
| 171 | uint32_t MemoryType; /*!< Specifies the type of external memory attached to |
171 | the corresponding memory device. |
| 172 | the corresponding memory device. |
172 | This parameter can be a value of @ref FSMC_Memory_Type */ |
| 173 | This parameter can be a value of @ref FSMC_Memory_Type */ |
173 | |
| 174 | 174 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
|
| 175 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
175 | This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
| 176 | This parameter can be a value of @ref FSMC_NORSRAM_Data_Width */ |
176 | |
| 177 | 177 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
|
| 178 | uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, |
178 | valid only with synchronous burst Flash memories. |
| 179 | valid only with synchronous burst Flash memories. |
179 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
| 180 | This parameter can be a value of @ref FSMC_Burst_Access_Mode */ |
180 | |
| 181 | 181 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
|
| 182 | uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing |
182 | the Flash memory in burst mode. |
| 183 | the Flash memory in burst mode. |
183 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
| 184 | This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ |
184 | |
| 185 | 185 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
|
| 186 | uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash |
186 | memory, valid only when accessing Flash memories in burst mode. |
| 187 | memory, valid only when accessing Flash memories in burst mode. |
187 | This parameter can be a value of @ref FSMC_Wrap_Mode */ |
| 188 | This parameter can be a value of @ref FSMC_Wrap_Mode */ |
188 | |
| 189 | 189 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
|
| 190 | uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one |
190 | clock cycle before the wait state or during the wait state, |
| 191 | clock cycle before the wait state or during the wait state, |
191 | valid only when accessing memories in burst mode. |
| 192 | valid only when accessing memories in burst mode. |
192 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
| 193 | This parameter can be a value of @ref FSMC_Wait_Timing */ |
193 | |
| 194 | 194 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
|
| 195 | uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FSMC. |
195 | This parameter can be a value of @ref FSMC_Write_Operation */ |
| 196 | This parameter can be a value of @ref FSMC_Write_Operation */ |
196 | |
| 197 | 197 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
|
| 198 | uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait |
198 | signal, valid for Flash memory access in burst mode. |
| 199 | signal, valid for Flash memory access in burst mode. |
199 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
| 200 | This parameter can be a value of @ref FSMC_Wait_Signal */ |
200 | |
| 201 | 201 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
|
| 202 | uint32_t ExtendedMode; /*!< Enables or disables the extended mode. |
202 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
| 203 | This parameter can be a value of @ref FSMC_Extended_Mode */ |
203 | |
| 204 | 204 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
|
| 205 | uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, |
205 | valid only with asynchronous Flash memories. |
| 206 | valid only with asynchronous Flash memories. |
206 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
| 207 | This parameter can be a value of @ref FSMC_AsynchronousWait */ |
207 | |
| 208 | 208 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
|
| 209 | uint32_t WriteBurst; /*!< Enables or disables the write burst operation. |
209 | This parameter can be a value of @ref FSMC_Write_Burst */ |
| 210 | This parameter can be a value of @ref FSMC_Write_Burst */ |
210 | |
| 211 | 211 | ||
| 212 | 212 | uint32_t PageSize; /*!< Specifies the memory page size. |
|
| 213 | uint32_t PageSize; /*!< Specifies the memory page size. |
213 | This parameter can be a value of @ref FSMC_Page_Size */ |
| 214 | This parameter can be a value of @ref FSMC_Page_Size */ |
214 | } FSMC_NORSRAM_InitTypeDef; |
| 215 | } FSMC_NORSRAM_InitTypeDef; |
215 | |
| 216 | 216 | /** |
|
| 217 | /** |
217 | * @brief FSMC NORSRAM Timing parameters structure definition |
| 218 | * @brief FSMC NORSRAM Timing parameters structure definition |
218 | */ |
| 219 | */ |
219 | typedef struct |
| 220 | typedef struct |
220 | { |
| 221 | { |
221 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
| 222 | uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure |
222 | the duration of the address setup time. |
| 223 | the duration of the address setup time. |
223 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| 224 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
224 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| 225 | @note This parameter is not used with synchronous NOR Flash memories. */ |
225 | |
| 226 | 226 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
|
| 227 | uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure |
227 | the duration of the address hold time. |
| 228 | the duration of the address hold time. |
228 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
| 229 | This parameter can be a value between Min_Data = 1 and Max_Data = 15. |
229 | @note This parameter is not used with synchronous NOR Flash memories. */ |
| 230 | @note This parameter is not used with synchronous NOR Flash memories. */ |
230 | |
| 231 | 231 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
|
| 232 | uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure |
232 | the duration of the data setup time. |
| 233 | the duration of the data setup time. |
233 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
| 234 | This parameter can be a value between Min_Data = 1 and Max_Data = 255. |
234 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
| 235 | @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed |
235 | NOR Flash memories. */ |
| 236 | NOR Flash memories. */ |
236 | |
| 237 | 237 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
|
| 238 | uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure |
238 | the duration of the bus turnaround. |
| 239 | the duration of the bus turnaround. |
239 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
| 240 | This parameter can be a value between Min_Data = 0 and Max_Data = 15. |
240 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
| 241 | @note This parameter is only used for multiplexed NOR Flash memories. */ |
241 | |
| 242 | 242 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
|
| 243 | uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of |
243 | HCLK cycles. This parameter can be a value between Min_Data = 2 and |
| 244 | HCLK cycles. This parameter can be a value between Min_Data = 2 and |
244 | Max_Data = 16. |
| 245 | Max_Data = 16. |
245 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
| 246 | @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM |
246 | accesses. */ |
| 247 | accesses. */ |
247 | |
| 248 | 248 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
|
| 249 | uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue |
249 | to the memory before getting the first data. |
| 250 | to the memory before getting the first data. |
250 | The parameter value depends on the memory type as shown below: |
| 251 | The parameter value depends on the memory type as shown below: |
251 | - It must be set to 0 in case of a CRAM |
| 252 | - It must be set to 0 in case of a CRAM |
252 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
| 253 | - It is don't care in asynchronous NOR, SRAM or ROM accesses |
253 | - It may assume a value between Min_Data = 2 and Max_Data = 17 |
| 254 | - It may assume a value between Min_Data = 2 and Max_Data = 17 |
254 | in NOR Flash memories with synchronous burst mode enable */ |
| 255 | in NOR Flash memories with synchronous burst mode enable */ |
255 | |
| 256 | 256 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
|
| 257 | uint32_t AccessMode; /*!< Specifies the asynchronous access mode. |
257 | This parameter can be a value of @ref FSMC_Access_Mode */ |
| 258 | This parameter can be a value of @ref FSMC_Access_Mode */ |
258 | } FSMC_NORSRAM_TimingTypeDef; |
| 259 | } FSMC_NORSRAM_TimingTypeDef; |
259 | #endif /* FSMC_BANK1 */ |
| 260 | #endif /* FSMC_BANK1 */ |
260 | |
| 261 | 261 | #if defined(FSMC_BANK3) |
|
| 262 | #if defined(FSMC_BANK3) |
262 | /** |
| 263 | /** |
263 | * @brief FSMC NAND Configuration Structure definition |
| 264 | * @brief FSMC NAND Configuration Structure definition |
264 | */ |
| 265 | */ |
265 | typedef struct |
| 266 | typedef struct |
266 | { |
| 267 | { |
267 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
| 268 | uint32_t NandBank; /*!< Specifies the NAND memory device that will be used. |
268 | This parameter can be a value of @ref FSMC_NAND_Bank */ |
| 269 | This parameter can be a value of @ref FSMC_NAND_Bank */ |
269 | |
| 270 | 270 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
|
| 271 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device. |
271 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| 272 | This parameter can be any value of @ref FSMC_Wait_feature */ |
272 | |
| 273 | 273 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
|
| 274 | uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. |
274 | This parameter can be any value of @ref FSMC_NAND_Data_Width */ |
| 275 | This parameter can be any value of @ref FSMC_NAND_Data_Width */ |
275 | |
| 276 | 276 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
|
| 277 | uint32_t EccComputation; /*!< Enables or disables the ECC computation. |
277 | This parameter can be any value of @ref FSMC_ECC */ |
| 278 | This parameter can be any value of @ref FSMC_ECC */ |
278 | |
| 279 | 279 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
|
| 280 | uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC. |
280 | This parameter can be any value of @ref FSMC_ECC_Page_Size */ |
| 281 | This parameter can be any value of @ref FSMC_ECC_Page_Size */ |
281 | |
| 282 | 282 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
|
| 283 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
283 | delay between CLE low and RE low. |
| 284 | delay between CLE low and RE low. |
284 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| 285 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
285 | |
| 286 | 286 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
|
| 287 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
287 | delay between ALE low and RE low. |
| 288 | delay between ALE low and RE low. |
288 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| 289 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
289 | } FSMC_NAND_InitTypeDef; |
| 290 | } FSMC_NAND_InitTypeDef; |
290 | #endif /* FSMC_BANK3 */ |
| 291 | #endif |
291 | |
| 292 | 292 | #if defined(FSMC_BANK3) || defined(FSMC_BANK4) |
|
| 293 | #if defined(FSMC_BANK3) || defined(FSMC_BANK4) |
293 | /** |
| 294 | /** |
294 | * @brief FSMC NAND Timing parameters structure definition |
| 295 | * @brief FSMC NAND Timing parameters structure definition |
295 | */ |
| 296 | */ |
296 | typedef struct |
| 297 | typedef struct |
297 | { |
| 298 | { |
298 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
| 299 | uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before |
299 | the command assertion for NAND-Flash read or write access |
| 300 | the command assertion for NAND-Flash read or write access |
300 | to common/Attribute or I/O memory space (depending on |
| 301 | to common/Attribute or I/O memory space (depending on |
301 | the memory space timing to be configured). |
| 302 | the memory space timing to be configured). |
302 | This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ |
| 303 | This parameter can be a value between Min_Data = 0 and Max_Data = 254 */ |
303 | |
| 304 | 304 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
|
| 305 | uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the |
305 | command for NAND-Flash read or write access to |
| 306 | command for NAND-Flash read or write access to |
306 | common/Attribute or I/O memory space (depending on the |
| 307 | common/Attribute or I/O memory space (depending on the |
307 | memory space timing to be configured). |
| 308 | memory space timing to be configured). |
308 | This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ |
| 309 | This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ |
309 | |
| 310 | 310 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
|
| 311 | uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address |
311 | (and data for write access) after the command de-assertion |
| 312 | (and data for write access) after the command de-assertion |
312 | for NAND-Flash read or write access to common/Attribute |
| 313 | for NAND-Flash read or write access to common/Attribute |
313 | or I/O memory space (depending on the memory space timing |
| 314 | or I/O memory space (depending on the memory space timing |
314 | to be configured). |
| 315 | to be configured). |
315 | This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ |
| 316 | This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ |
316 | |
| 317 | 317 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
|
| 318 | uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the |
318 | data bus is kept in HiZ after the start of a NAND-Flash |
| 319 | data bus is kept in HiZ after the start of a NAND-Flash |
319 | write access to common/Attribute or I/O memory space (depending |
| 320 | write access to common/Attribute or I/O memory space (depending |
320 | on the memory space timing to be configured). |
| 321 | on the memory space timing to be configured). |
321 | This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ |
| 322 | This parameter can be a number between Min_Data = 0 and Max_Data = 254 */ |
322 | } FSMC_NAND_PCC_TimingTypeDef; |
| 323 | } FSMC_NAND_PCC_TimingTypeDef; |
323 | #endif /* FSMC_BANK3 */ |
| 324 | #endif /* FSMC_BANK3 */ |
324 | |
| 325 | 325 | #if defined(FSMC_BANK4) |
|
| 326 | #if defined(FSMC_BANK4) |
326 | /** |
| 327 | /** |
327 | * @brief FSMC PCCARD Configuration Structure definition |
| 328 | * @brief FSMC PCCARD Configuration Structure definition |
328 | */ |
| 329 | */ |
329 | typedef struct |
| 330 | typedef struct |
330 | { |
| 331 | { |
331 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. |
| 332 | uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device. |
332 | This parameter can be any value of @ref FSMC_Wait_feature */ |
| 333 | This parameter can be any value of @ref FSMC_Wait_feature */ |
333 | |
| 334 | 334 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
|
| 335 | uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the |
335 | delay between CLE low and RE low. |
| 336 | delay between CLE low and RE low. |
336 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
| 337 | This parameter can be a value between Min_Data = 0 and Max_Data = 255 */ |
337 | |
| 338 | 338 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
|
| 339 | uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the |
339 | delay between ALE low and RE low. |
| 340 | delay between ALE low and RE low. |
340 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
| 341 | This parameter can be a number between Min_Data = 0 and Max_Data = 255 */ |
341 | }FSMC_PCCARD_InitTypeDef; |
| 342 | }FSMC_PCCARD_InitTypeDef; |
342 | #endif /* FSMC_BANK4 */ |
| 343 | #endif |
343 | |
| 344 | 344 | /** |
|
| 345 | /** |
345 | * @} |
| 346 | * @} |
346 | */ |
| 347 | */ |
347 | |
| 348 | 348 | /* Exported constants --------------------------------------------------------*/ |
|
| 349 | /* Exported constants --------------------------------------------------------*/ |
349 | /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants |
| 350 | /** @addtogroup FSMC_LL_Exported_Constants FSMC Low Layer Exported Constants |
350 | * @{ |
| 351 | * @{ |
351 | */ |
| 352 | */ |
352 | #if defined(FSMC_BANK1) |
| 353 | #if defined(FSMC_BANK1) |
353 | |
| 354 | 354 | /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller |
|
| 355 | /** @defgroup FSMC_LL_NOR_SRAM_Controller FSMC NOR/SRAM Controller |
355 | * @{ |
| 356 | * @{ |
356 | */ |
| 357 | */ |
357 | |
| 358 | 358 | /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank |
|
| 359 | /** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank |
359 | * @{ |
| 360 | * @{ |
360 | */ |
| 361 | */ |
361 | #define FSMC_NORSRAM_BANK1 (0x00000000U) |
| 362 | #define FSMC_NORSRAM_BANK1 (0x00000000U) |
362 | #define FSMC_NORSRAM_BANK2 (0x00000002U) |
| 363 | #define FSMC_NORSRAM_BANK2 (0x00000002U) |
363 | #define FSMC_NORSRAM_BANK3 (0x00000004U) |
| 364 | #define FSMC_NORSRAM_BANK3 (0x00000004U) |
364 | #define FSMC_NORSRAM_BANK4 (0x00000006U) |
| 365 | #define FSMC_NORSRAM_BANK4 (0x00000006U) |
365 | /** |
| 366 | /** |
366 | * @} |
| 367 | * @} |
367 | */ |
| 368 | */ |
368 | |
| 369 | 369 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing |
|
| 370 | /** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing |
370 | * @{ |
| 371 | * @{ |
371 | */ |
| 372 | */ |
372 | #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) |
| 373 | #define FSMC_DATA_ADDRESS_MUX_DISABLE (0x00000000U) |
373 | #define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) |
| 374 | #define FSMC_DATA_ADDRESS_MUX_ENABLE (0x00000002U) |
374 | /** |
| 375 | /** |
375 | * @} |
| 376 | * @} |
376 | */ |
| 377 | */ |
377 | |
| 378 | 378 | /** @defgroup FSMC_Memory_Type FSMC Memory Type |
|
| 379 | /** @defgroup FSMC_Memory_Type FSMC Memory Type |
379 | * @{ |
| 380 | * @{ |
380 | */ |
| 381 | */ |
381 | #define FSMC_MEMORY_TYPE_SRAM (0x00000000U) |
| 382 | #define FSMC_MEMORY_TYPE_SRAM (0x00000000U) |
382 | #define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) |
| 383 | #define FSMC_MEMORY_TYPE_PSRAM (0x00000004U) |
383 | #define FSMC_MEMORY_TYPE_NOR (0x00000008U) |
| 384 | #define FSMC_MEMORY_TYPE_NOR (0x00000008U) |
384 | /** |
| 385 | /** |
385 | * @} |
| 386 | * @} |
386 | */ |
| 387 | */ |
387 | |
| 388 | 388 | /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width |
|
| 389 | /** @defgroup FSMC_NORSRAM_Data_Width FSMC NORSRAM Data Width |
389 | * @{ |
| 390 | * @{ |
390 | */ |
| 391 | */ |
391 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) |
| 392 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_8 (0x00000000U) |
392 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) |
| 393 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_16 (0x00000010U) |
393 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) |
| 394 | #define FSMC_NORSRAM_MEM_BUS_WIDTH_32 (0x00000020U) |
394 | /** |
| 395 | /** |
395 | * @} |
| 396 | * @} |
396 | */ |
| 397 | */ |
397 | |
| 398 | 398 | /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access |
|
| 399 | /** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access |
399 | * @{ |
| 400 | * @{ |
400 | */ |
| 401 | */ |
401 | #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) |
| 402 | #define FSMC_NORSRAM_FLASH_ACCESS_ENABLE (0x00000040U) |
402 | #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) |
| 403 | #define FSMC_NORSRAM_FLASH_ACCESS_DISABLE (0x00000000U) |
403 | /** |
| 404 | /** |
404 | * @} |
| 405 | * @} |
405 | */ |
| 406 | */ |
406 | |
| 407 | 407 | /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode |
|
| 408 | /** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode |
408 | * @{ |
| 409 | * @{ |
409 | */ |
| 410 | */ |
410 | #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) |
| 411 | #define FSMC_BURST_ACCESS_MODE_DISABLE (0x00000000U) |
411 | #define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) |
| 412 | #define FSMC_BURST_ACCESS_MODE_ENABLE (0x00000100U) |
412 | /** |
| 413 | /** |
413 | * @} |
| 414 | * @} |
414 | */ |
| 415 | */ |
415 | |
| 416 | 416 | /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity |
|
| 417 | /** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity |
417 | * @{ |
| 418 | * @{ |
418 | */ |
| 419 | */ |
419 | #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) |
| 420 | #define FSMC_WAIT_SIGNAL_POLARITY_LOW (0x00000000U) |
420 | #define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) |
| 421 | #define FSMC_WAIT_SIGNAL_POLARITY_HIGH (0x00000200U) |
421 | /** |
| 422 | /** |
422 | * @} |
| 423 | * @} |
423 | */ |
| 424 | */ |
424 | |
| 425 | 425 | /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode |
|
| 426 | /** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode |
426 | * @{ |
| 427 | * @{ |
427 | */ |
| 428 | */ |
428 | #define FSMC_WRAP_MODE_DISABLE (0x00000000U) |
| 429 | #define FSMC_WRAP_MODE_DISABLE (0x00000000U) |
429 | #define FSMC_WRAP_MODE_ENABLE (0x00000400U) |
| 430 | #define FSMC_WRAP_MODE_ENABLE (0x00000400U) |
430 | /** |
| 431 | /** |
431 | * @} |
| 432 | * @} |
432 | */ |
| 433 | */ |
433 | |
| 434 | 434 | /** @defgroup FSMC_Wait_Timing FSMC Wait Timing |
|
| 435 | /** @defgroup FSMC_Wait_Timing FSMC Wait Timing |
435 | * @{ |
| 436 | * @{ |
436 | */ |
| 437 | */ |
437 | #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) |
| 438 | #define FSMC_WAIT_TIMING_BEFORE_WS (0x00000000U) |
438 | #define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) |
| 439 | #define FSMC_WAIT_TIMING_DURING_WS (0x00000800U) |
439 | /** |
| 440 | /** |
440 | * @} |
| 441 | * @} |
441 | */ |
| 442 | */ |
442 | |
| 443 | 443 | /** @defgroup FSMC_Write_Operation FSMC Write Operation |
|
| 444 | /** @defgroup FSMC_Write_Operation FSMC Write Operation |
444 | * @{ |
| 445 | * @{ |
445 | */ |
| 446 | */ |
446 | #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) |
| 447 | #define FSMC_WRITE_OPERATION_DISABLE (0x00000000U) |
447 | #define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) |
| 448 | #define FSMC_WRITE_OPERATION_ENABLE (0x00001000U) |
448 | /** |
| 449 | /** |
449 | * @} |
| 450 | * @} |
450 | */ |
| 451 | */ |
451 | |
| 452 | 452 | /** @defgroup FSMC_Wait_Signal FSMC Wait Signal |
|
| 453 | /** @defgroup FSMC_Wait_Signal FSMC Wait Signal |
453 | * @{ |
| 454 | * @{ |
454 | */ |
| 455 | */ |
455 | #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) |
| 456 | #define FSMC_WAIT_SIGNAL_DISABLE (0x00000000U) |
456 | #define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) |
| 457 | #define FSMC_WAIT_SIGNAL_ENABLE (0x00002000U) |
457 | /** |
| 458 | /** |
458 | * @} |
| 459 | * @} |
459 | */ |
| 460 | */ |
460 | |
| 461 | 461 | /** @defgroup FSMC_Extended_Mode FSMC Extended Mode |
|
| 462 | /** @defgroup FSMC_Extended_Mode FSMC Extended Mode |
462 | * @{ |
| 463 | * @{ |
463 | */ |
| 464 | */ |
464 | #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) |
| 465 | #define FSMC_EXTENDED_MODE_DISABLE (0x00000000U) |
465 | #define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) |
| 466 | #define FSMC_EXTENDED_MODE_ENABLE (0x00004000U) |
466 | /** |
| 467 | /** |
467 | * @} |
| 468 | * @} |
468 | */ |
| 469 | */ |
469 | |
| 470 | 470 | /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait |
|
| 471 | /** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait |
471 | * @{ |
| 472 | * @{ |
472 | */ |
| 473 | */ |
473 | #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) |
| 474 | #define FSMC_ASYNCHRONOUS_WAIT_DISABLE (0x00000000U) |
474 | #define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) |
| 475 | #define FSMC_ASYNCHRONOUS_WAIT_ENABLE (0x00008000U) |
475 | /** |
| 476 | /** |
476 | * @} |
| 477 | * @} |
477 | */ |
| 478 | */ |
478 | |
| 479 | 479 | /** @defgroup FSMC_Page_Size FSMC Page Size |
|
| 480 | /** @defgroup FSMC_Page_Size FSMC Page Size |
480 | * @{ |
| 481 | * @{ |
481 | */ |
| 482 | */ |
482 | #define FSMC_PAGE_SIZE_NONE (0x00000000U) |
| 483 | #define FSMC_PAGE_SIZE_NONE (0x00000000U) |
483 | #define FSMC_PAGE_SIZE_128 (0x00010000U) |
| 484 | #define FSMC_PAGE_SIZE_128 (0x00010000U) |
484 | #define FSMC_PAGE_SIZE_256 (0x00020000U) |
| 485 | #define FSMC_PAGE_SIZE_256 (0x00020000U) |
485 | #define FSMC_PAGE_SIZE_512 (0x00030000U) |
| 486 | #define FSMC_PAGE_SIZE_512 (0x00030000U) |
486 | #define FSMC_PAGE_SIZE_1024 (0x00040000U) |
| 487 | #define FSMC_PAGE_SIZE_1024 (0x00040000U) |
487 | /** |
| 488 | /** |
488 | * @} |
| 489 | * @} |
489 | */ |
| 490 | */ |
490 | |
| 491 | 491 | /** @defgroup FSMC_Write_Burst FSMC Write Burst |
|
| 492 | /** @defgroup FSMC_Write_Burst FSMC Write Burst |
492 | * @{ |
| 493 | * @{ |
493 | */ |
| 494 | */ |
494 | #define FSMC_WRITE_BURST_DISABLE (0x00000000U) |
| 495 | #define FSMC_WRITE_BURST_DISABLE (0x00000000U) |
495 | #define FSMC_WRITE_BURST_ENABLE (0x00080000U) |
| 496 | #define FSMC_WRITE_BURST_ENABLE (0x00080000U) |
496 | /** |
| 497 | /** |
497 | * @} |
| 498 | * @} |
498 | */ |
| 499 | */ |
499 | |
| 500 | 500 | /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock |
|
| 501 | /** @defgroup FSMC_Continous_Clock FSMC Continuous Clock |
501 | * @{ |
| 502 | * @{ |
502 | */ |
| 503 | */ |
503 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) |
| 504 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ONLY (0x00000000U) |
504 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) |
| 505 | #define FSMC_CONTINUOUS_CLOCK_SYNC_ASYNC (0x00100000U) |
505 | /** |
| 506 | /** |
506 | * @} |
| 507 | * @} |
507 | */ |
| 508 | */ |
508 | |
| 509 | 509 | /** @defgroup FSMC_Access_Mode FSMC Access Mode |
|
| 510 | /** @defgroup FSMC_Access_Mode FSMC Access Mode |
510 | * @{ |
| 511 | * @{ |
511 | */ |
| 512 | */ |
512 | #define FSMC_ACCESS_MODE_A (0x00000000U) |
| 513 | #define FSMC_ACCESS_MODE_A (0x00000000U) |
513 | #define FSMC_ACCESS_MODE_B (0x10000000U) |
| 514 | #define FSMC_ACCESS_MODE_B (0x10000000U) |
514 | #define FSMC_ACCESS_MODE_C (0x20000000U) |
| 515 | #define FSMC_ACCESS_MODE_C (0x20000000U) |
515 | #define FSMC_ACCESS_MODE_D (0x30000000U) |
| 516 | #define FSMC_ACCESS_MODE_D (0x30000000U) |
516 | /** |
| 517 | /** |
517 | * @} |
| 518 | * @} |
518 | */ |
| 519 | */ |
519 | |
| 520 | 520 | /** |
|
| 521 | /** |
521 | * @} |
| 522 | * @} |
522 | */ |
| 523 | */ |
523 | #endif /* FSMC_BANK1 */ |
| 524 | #endif /* FSMC_BANK1 */ |
524 | |
| 525 | 525 | #if defined(FSMC_BANK3) || defined(FSMC_BANK4) |
|
| 526 | #if defined(FSMC_BANK3) || defined(FSMC_BANK4) |
526 | |
| 527 | 527 | /** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller |
|
| 528 | /** @defgroup FSMC_LL_NAND_Controller FSMC NAND Controller |
528 | * @{ |
| 529 | * @{ |
529 | */ |
| 530 | */ |
530 | /** @defgroup FSMC_NAND_Bank FSMC NAND Bank |
| 531 | /** @defgroup FSMC_NAND_Bank FSMC NAND Bank |
531 | * @{ |
| 532 | * @{ |
532 | */ |
| 533 | */ |
533 | #define FSMC_NAND_BANK2 (0x00000010U) |
| 534 | #define FSMC_NAND_BANK2 (0x00000010U) |
534 | #define FSMC_NAND_BANK3 (0x00000100U) |
| 535 | #define FSMC_NAND_BANK3 (0x00000100U) |
535 | /** |
| 536 | /** |
536 | * @} |
| 537 | * @} |
537 | */ |
| 538 | */ |
538 | |
| 539 | 539 | /** @defgroup FSMC_Wait_feature FSMC Wait feature |
|
| 540 | /** @defgroup FSMC_Wait_feature FSMC Wait feature |
540 | * @{ |
| 541 | * @{ |
541 | */ |
| 542 | */ |
542 | #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) |
| 543 | #define FSMC_NAND_PCC_WAIT_FEATURE_DISABLE (0x00000000U) |
543 | #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) |
| 544 | #define FSMC_NAND_PCC_WAIT_FEATURE_ENABLE (0x00000002U) |
544 | /** |
| 545 | /** |
545 | * @} |
| 546 | * @} |
546 | */ |
| 547 | */ |
547 | |
| 548 | 548 | /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type |
|
| 549 | /** @defgroup FSMC_PCR_Memory_Type FSMC PCR Memory Type |
549 | * @{ |
| 550 | * @{ |
550 | */ |
| 551 | */ |
551 | #if defined(FSMC_BANK4) |
| 552 | #if defined(FSMC_BANK4) |
552 | #define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) |
| 553 | #define FSMC_PCR_MEMORY_TYPE_PCCARD (0x00000000U) |
553 | #endif /* FSMC_BANK4 */ |
| 554 | #endif |
554 | #define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U) |
| 555 | #define FSMC_PCR_MEMORY_TYPE_NAND (0x00000008U) |
555 | /** |
| 556 | /** |
556 | * @} |
| 557 | * @} |
557 | */ |
| 558 | */ |
558 | |
| 559 | 559 | /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width |
|
| 560 | /** @defgroup FSMC_NAND_Data_Width FSMC NAND Data Width |
560 | * @{ |
| 561 | * @{ |
561 | */ |
| 562 | */ |
562 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) |
| 563 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_8 (0x00000000U) |
563 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) |
| 564 | #define FSMC_NAND_PCC_MEM_BUS_WIDTH_16 (0x00000010U) |
564 | /** |
| 565 | /** |
565 | * @} |
| 566 | * @} |
566 | */ |
| 567 | */ |
567 | |
| 568 | 568 | /** @defgroup FSMC_ECC FSMC ECC |
|
| 569 | /** @defgroup FSMC_ECC FSMC ECC |
569 | * @{ |
| 570 | * @{ |
570 | */ |
| 571 | */ |
571 | #define FSMC_NAND_ECC_DISABLE (0x00000000U) |
| 572 | #define FSMC_NAND_ECC_DISABLE (0x00000000U) |
572 | #define FSMC_NAND_ECC_ENABLE (0x00000040U) |
| 573 | #define FSMC_NAND_ECC_ENABLE (0x00000040U) |
573 | /** |
| 574 | /** |
574 | * @} |
| 575 | * @} |
575 | */ |
| 576 | */ |
576 | |
| 577 | 577 | /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size |
|
| 578 | /** @defgroup FSMC_ECC_Page_Size FSMC ECC Page Size |
578 | * @{ |
| 579 | * @{ |
579 | */ |
| 580 | */ |
580 | #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) |
| 581 | #define FSMC_NAND_ECC_PAGE_SIZE_256BYTE (0x00000000U) |
581 | #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) |
| 582 | #define FSMC_NAND_ECC_PAGE_SIZE_512BYTE (0x00020000U) |
582 | #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) |
| 583 | #define FSMC_NAND_ECC_PAGE_SIZE_1024BYTE (0x00040000U) |
583 | #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) |
| 584 | #define FSMC_NAND_ECC_PAGE_SIZE_2048BYTE (0x00060000U) |
584 | #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) |
| 585 | #define FSMC_NAND_ECC_PAGE_SIZE_4096BYTE (0x00080000U) |
585 | #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) |
| 586 | #define FSMC_NAND_ECC_PAGE_SIZE_8192BYTE (0x000A0000U) |
586 | /** |
| 587 | /** |
587 | * @} |
| 588 | * @} |
588 | */ |
| 589 | */ |
589 | |
| 590 | 590 | /** |
|
| 591 | /** |
591 | * @} |
| 592 | * @} |
592 | */ |
| 593 | */ |
593 | #endif /* FSMC_BANK3 || FSMC_Bank4 */ |
| 594 | #endif /* FSMC_BANK3 */ |
594 | |
| 595 | 595 | ||
| 596 | 596 | /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition |
|
| 597 | /** @defgroup FSMC_LL_Interrupt_definition FSMC Low Layer Interrupt definition |
597 | * @{ |
| 598 | * @{ |
598 | */ |
| 599 | */ |
599 | #if defined(FSMC_BANK3) || defined(FSMC_BANK4) |
| 600 | #if defined(FSMC_BANK3) || defined(FSMC_BANK4) |
600 | #define FSMC_IT_RISING_EDGE (0x00000008U) |
| 601 | #define FSMC_IT_RISING_EDGE (0x00000008U) |
601 | #define FSMC_IT_LEVEL (0x00000010U) |
| 602 | #define FSMC_IT_LEVEL (0x00000010U) |
602 | #define FSMC_IT_FALLING_EDGE (0x00000020U) |
| 603 | #define FSMC_IT_FALLING_EDGE (0x00000020U) |
603 | #endif /* FSMC_BANK3 || FSMC_Bank4 */ |
| 604 | #endif /* FSMC_BANK3 */ |
604 | /** |
| 605 | /** |
605 | * @} |
| 606 | * @} |
606 | */ |
| 607 | */ |
607 | |
| 608 | 608 | /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition |
|
| 609 | /** @defgroup FSMC_LL_Flag_definition FSMC Low Layer Flag definition |
609 | * @{ |
| 610 | * @{ |
610 | */ |
| 611 | */ |
611 | #if defined(FSMC_BANK3) || defined(FSMC_BANK4) |
| 612 | #if defined(FSMC_BANK3) || defined(FSMC_BANK4) |
612 | #define FSMC_FLAG_RISING_EDGE (0x00000001U) |
| 613 | #define FSMC_FLAG_RISING_EDGE (0x00000001U) |
613 | #define FSMC_FLAG_LEVEL (0x00000002U) |
| 614 | #define FSMC_FLAG_LEVEL (0x00000002U) |
614 | #define FSMC_FLAG_FALLING_EDGE (0x00000004U) |
| 615 | #define FSMC_FLAG_FALLING_EDGE (0x00000004U) |
615 | #define FSMC_FLAG_FEMPT (0x00000040U) |
| 616 | #define FSMC_FLAG_FEMPT (0x00000040U) |
616 | #endif /* FSMC_BANK3 || FSMC_Bank4 */ |
| 617 | #endif /* FSMC_BANK3 */ |
617 | /** |
| 618 | /** |
618 | * @} |
| 619 | * @} |
619 | */ |
| 620 | */ |
620 | |
| 621 | 621 | /** |
|
| 622 | /** |
622 | * @} |
| 623 | * @} |
623 | */ |
| 624 | */ |
624 | |
| 625 | 625 | /** |
|
| 626 | /** |
626 | * @} |
| 627 | * @} |
627 | */ |
| 628 | */ |
628 | |
| 629 | 629 | /* Private macro -------------------------------------------------------------*/ |
|
| 630 | /* Private macro -------------------------------------------------------------*/ |
630 | /** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros |
| 631 | /** @defgroup FSMC_LL_Private_Macros FSMC_LL Private Macros |
631 | * @{ |
| 632 | * @{ |
632 | */ |
| 633 | */ |
633 | #if defined(FSMC_BANK1) |
| 634 | #if defined(FSMC_BANK1) |
634 | /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros |
| 635 | /** @defgroup FSMC_LL_NOR_Macros FSMC NOR/SRAM Macros |
635 | * @brief macros to handle NOR device enable/disable and read/write operations |
| 636 | * @brief macros to handle NOR device enable/disable and read/write operations |
636 | * @{ |
| 637 | * @{ |
637 | */ |
| 638 | */ |
638 | |
| 639 | 639 | /** |
|
| 640 | /** |
640 | * @brief Enable the NORSRAM device access. |
| 641 | * @brief Enable the NORSRAM device access. |
641 | * @param __INSTANCE__ FSMC_NORSRAM Instance |
| 642 | * @param __INSTANCE__ FSMC_NORSRAM Instance |
642 | * @param __BANK__ FSMC_NORSRAM Bank |
| 643 | * @param __BANK__ FSMC_NORSRAM Bank |
643 | * @retval None |
| 644 | * @retval None |
644 | */ |
| 645 | */ |
645 | #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ |
| 646 | #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ |
646 | |= FSMC_BCRx_MBKEN) |
| 647 | |= FSMC_BCRx_MBKEN) |
647 | |
| 648 | 648 | /** |
|
| 649 | /** |
649 | * @brief Disable the NORSRAM device access. |
| 650 | * @brief Disable the NORSRAM device access. |
650 | * @param __INSTANCE__ FSMC_NORSRAM Instance |
| 651 | * @param __INSTANCE__ FSMC_NORSRAM Instance |
651 | * @param __BANK__ FSMC_NORSRAM Bank |
| 652 | * @param __BANK__ FSMC_NORSRAM Bank |
652 | * @retval None |
| 653 | * @retval None |
653 | */ |
| 654 | */ |
654 | #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ |
| 655 | #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)]\ |
655 | &= ~FSMC_BCRx_MBKEN) |
| 656 | &= ~FSMC_BCRx_MBKEN) |
656 | |
| 657 | 657 | /** |
|
| 658 | /** |
658 | * @} |
| 659 | * @} |
659 | */ |
| 660 | */ |
660 | #endif /* FSMC_BANK1 */ |
| 661 | #endif /* FSMC_BANK1 */ |
661 | |
| 662 | 662 | #if defined(FSMC_BANK3) |
|
| 663 | #if defined(FSMC_BANK3) |
663 | /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros |
| 664 | /** @defgroup FSMC_LL_NAND_Macros FSMC NAND Macros |
664 | * @brief macros to handle NAND device enable/disable |
| 665 | * @brief macros to handle NAND device enable/disable |
665 | * @{ |
| 666 | * @{ |
666 | */ |
| 667 | */ |
667 | |
| 668 | 668 | /** |
|
| 669 | /** |
669 | * @brief Enable the NAND device access. |
| 670 | * @brief Enable the NAND device access. |
670 | * @param __INSTANCE__ FSMC_NAND Instance |
| 671 | * @param __INSTANCE__ FSMC_NAND Instance |
671 | * @param __BANK__ FSMC_NAND Bank |
| 672 | * @param __BANK__ FSMC_NAND Bank |
672 | * @retval None |
| 673 | * @retval None |
673 | */ |
| 674 | */ |
674 | #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN): \ |
| 675 | #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCRx_PBKEN): \ |
675 | ((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN)) |
| 676 | ((__INSTANCE__)->PCR3 |= FSMC_PCRx_PBKEN)) |
676 | |
| 677 | 677 | /** |
|
| 678 | /** |
678 | * @brief Disable the NAND device access. |
| 679 | * @brief Disable the NAND device access. |
679 | * @param __INSTANCE__ FSMC_NAND Instance |
| 680 | * @param __INSTANCE__ FSMC_NAND Instance |
680 | * @param __BANK__ FSMC_NAND Bank |
| 681 | * @param __BANK__ FSMC_NAND Bank |
681 | * @retval None |
| 682 | * @retval None |
682 | */ |
| 683 | */ |
683 | #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \ |
| 684 | #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? CLEAR_BIT((__INSTANCE__)->PCR2, FSMC_PCRx_PBKEN): \ |
684 | CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) |
| 685 | CLEAR_BIT((__INSTANCE__)->PCR3, FSMC_PCRx_PBKEN)) |
685 | |
| 686 | 686 | /** |
|
| 687 | /** |
687 | * @} |
| 688 | * @} |
688 | */ |
| 689 | */ |
689 | #endif /* FSMC_BANK3 */ |
| 690 | #endif |
690 | |
| 691 | 691 | #if defined(FSMC_BANK4) |
|
| 692 | #if defined(FSMC_BANK4) |
692 | /** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros |
| 693 | /** @defgroup FSMC_LL_PCCARD_Macros FMC PCCARD Macros |
693 | * @brief macros to handle PCCARD read/write operations |
| 694 | * @brief macros to handle PCCARD read/write operations |
694 | * @{ |
| 695 | * @{ |
695 | */ |
| 696 | */ |
696 | /** |
| 697 | /** |
697 | * @brief Enable the PCCARD device access. |
| 698 | * @brief Enable the PCCARD device access. |
698 | * @param __INSTANCE__ FSMC_PCCARD Instance |
| 699 | * @param __INSTANCE__ FSMC_PCCARD Instance |
699 | * @retval None |
| 700 | * @retval None |
700 | */ |
| 701 | */ |
701 | #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCRx_PBKEN) |
| 702 | #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCRx_PBKEN) |
702 | |
| 703 | 703 | /** |
|
| 704 | /** |
704 | * @brief Disable the PCCARD device access. |
| 705 | * @brief Disable the PCCARD device access. |
705 | * @param __INSTANCE__ FSMC_PCCARD Instance |
| 706 | * @param __INSTANCE__ FSMC_PCCARD Instance |
706 | * @retval None |
| 707 | * @retval None |
707 | */ |
| 708 | */ |
708 | #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCRx_PBKEN) |
| 709 | #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCRx_PBKEN) |
709 | /** |
| 710 | /** |
710 | * @} |
| 711 | * @} |
711 | */ |
| 712 | */ |
712 | |
| 713 | 713 | #endif |
|
| 714 | #endif |
714 | #if defined(FSMC_BANK3) |
| 715 | #if defined(FSMC_BANK3) |
715 | /** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt |
| 716 | /** @defgroup FSMC_LL_NAND_Interrupt FSMC NAND Interrupt |
716 | * @brief macros to handle NAND interrupts |
| 717 | * @brief macros to handle NAND interrupts |
717 | * @{ |
| 718 | * @{ |
718 | */ |
| 719 | */ |
719 | |
| 720 | 720 | /** |
|
| 721 | /** |
721 | * @brief Enable the NAND device interrupt. |
| 722 | * @brief Enable the NAND device interrupt. |
722 | * @param __INSTANCE__ FSMC_NAND instance |
| 723 | * @param __INSTANCE__ FSMC_NAND instance |
723 | * @param __BANK__ FSMC_NAND Bank |
| 724 | * @param __BANK__ FSMC_NAND Bank |
724 | * @param __INTERRUPT__ FSMC_NAND interrupt |
| 725 | * @param __INTERRUPT__ FSMC_NAND interrupt |
725 | * This parameter can be any combination of the following values: |
| 726 | * This parameter can be any combination of the following values: |
726 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| 727 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
727 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| 728 | * @arg FSMC_IT_LEVEL: Interrupt level. |
728 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| 729 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
729 | * @retval None |
| 730 | * @retval None |
730 | */ |
| 731 | */ |
731 | #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ |
| 732 | #define __FSMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 |= (__INTERRUPT__)): \ |
732 | ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) |
| 733 | ((__INSTANCE__)->SR3 |= (__INTERRUPT__))) |
733 | |
| 734 | 734 | /** |
|
| 735 | /** |
735 | * @brief Disable the NAND device interrupt. |
| 736 | * @brief Disable the NAND device interrupt. |
736 | * @param __INSTANCE__ FSMC_NAND Instance |
| 737 | * @param __INSTANCE__ FSMC_NAND Instance |
737 | * @param __BANK__ FSMC_NAND Bank |
| 738 | * @param __BANK__ FSMC_NAND Bank |
738 | * @param __INTERRUPT__ FSMC_NAND interrupt |
| 739 | * @param __INTERRUPT__ FSMC_NAND interrupt |
739 | * This parameter can be any combination of the following values: |
| 740 | * This parameter can be any combination of the following values: |
740 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| 741 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
741 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| 742 | * @arg FSMC_IT_LEVEL: Interrupt level. |
742 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| 743 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
743 | * @retval None |
| 744 | * @retval None |
744 | */ |
| 745 | */ |
745 | #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ |
| 746 | #define __FSMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \ |
746 | ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) |
| 747 | ((__INSTANCE__)->SR3 &= ~(__INTERRUPT__))) |
747 | |
| 748 | 748 | /** |
|
| 749 | /** |
749 | * @brief Get flag status of the NAND device. |
| 750 | * @brief Get flag status of the NAND device. |
750 | * @param __INSTANCE__ FSMC_NAND Instance |
| 751 | * @param __INSTANCE__ FSMC_NAND Instance |
751 | * @param __BANK__ FSMC_NAND Bank |
| 752 | * @param __BANK__ FSMC_NAND Bank |
752 | * @param __FLAG__ FSMC_NAND flag |
| 753 | * @param __FLAG__ FSMC_NAND flag |
753 | * This parameter can be any combination of the following values: |
| 754 | * This parameter can be any combination of the following values: |
754 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| 755 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
755 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| 756 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
756 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| 757 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
757 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| 758 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
758 | * @retval The state of FLAG (SET or RESET). |
| 759 | * @retval The state of FLAG (SET or RESET). |
759 | */ |
| 760 | */ |
760 | #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ |
| 761 | #define __FSMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \ |
761 | (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) |
| 762 | (((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__))) |
762 | |
| 763 | 763 | /** |
|
| 764 | /** |
764 | * @brief Clear flag status of the NAND device. |
| 765 | * @brief Clear flag status of the NAND device. |
765 | * @param __INSTANCE__ FSMC_NAND Instance |
| 766 | * @param __INSTANCE__ FSMC_NAND Instance |
766 | * @param __BANK__ FSMC_NAND Bank |
| 767 | * @param __BANK__ FSMC_NAND Bank |
767 | * @param __FLAG__ FSMC_NAND flag |
| 768 | * @param __FLAG__ FSMC_NAND flag |
768 | * This parameter can be any combination of the following values: |
| 769 | * This parameter can be any combination of the following values: |
769 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| 770 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
770 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| 771 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
771 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| 772 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
772 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| 773 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
773 | * @retval None |
| 774 | * @retval None |
774 | */ |
| 775 | */ |
775 | #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ |
| 776 | #define __FSMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \ |
776 | ((__INSTANCE__)->SR3 &= ~(__FLAG__))) |
| 777 | ((__INSTANCE__)->SR3 &= ~(__FLAG__))) |
777 | |
| 778 | 778 | /** |
|
| 779 | /** |
779 | * @} |
| 780 | * @} |
780 | */ |
| 781 | */ |
781 | #endif /* FSMC_BANK3 */ |
| 782 | #endif /* FSMC_BANK3 */ |
782 | |
| 783 | 783 | #if defined(FSMC_BANK4) |
|
| 784 | #if defined(FSMC_BANK4) |
784 | /** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt |
| 785 | /** @defgroup FSMC_LL_PCCARD_Interrupt FSMC PCCARD Interrupt |
785 | * @brief macros to handle PCCARD interrupts |
| 786 | * @brief macros to handle PCCARD interrupts |
786 | * @{ |
| 787 | * @{ |
787 | */ |
| 788 | */ |
788 | |
| 789 | 789 | /** |
|
| 790 | /** |
790 | * @brief Enable the PCCARD device interrupt. |
| 791 | * @brief Enable the PCCARD device interrupt. |
791 | * @param __INSTANCE__ FSMC_PCCARD instance |
| 792 | * @param __INSTANCE__ FSMC_PCCARD instance |
792 | * @param __INTERRUPT__ FSMC_PCCARD interrupt |
| 793 | * @param __INTERRUPT__ FSMC_PCCARD interrupt |
793 | * This parameter can be any combination of the following values: |
| 794 | * This parameter can be any combination of the following values: |
794 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| 795 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
795 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| 796 | * @arg FSMC_IT_LEVEL: Interrupt level. |
796 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| 797 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
797 | * @retval None |
| 798 | * @retval None |
798 | */ |
| 799 | */ |
799 | #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) |
| 800 | #define __FSMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 |= (__INTERRUPT__)) |
800 | |
| 801 | 801 | /** |
|
| 802 | /** |
802 | * @brief Disable the PCCARD device interrupt. |
| 803 | * @brief Disable the PCCARD device interrupt. |
803 | * @param __INSTANCE__ FSMC_PCCARD instance |
| 804 | * @param __INSTANCE__ FSMC_PCCARD instance |
804 | * @param __INTERRUPT__ FSMC_PCCARD interrupt |
| 805 | * @param __INTERRUPT__ FSMC_PCCARD interrupt |
805 | * This parameter can be any combination of the following values: |
| 806 | * This parameter can be any combination of the following values: |
806 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
| 807 | * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. |
807 | * @arg FSMC_IT_LEVEL: Interrupt level. |
| 808 | * @arg FSMC_IT_LEVEL: Interrupt level. |
808 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
| 809 | * @arg FSMC_IT_FALLING_EDGE: Interrupt falling edge. |
809 | * @retval None |
| 810 | * @retval None |
810 | */ |
| 811 | */ |
811 | #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) |
| 812 | #define __FSMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__)) |
812 | |
| 813 | 813 | /** |
|
| 814 | /** |
814 | * @brief Get flag status of the PCCARD device. |
| 815 | * @brief Get flag status of the PCCARD device. |
815 | * @param __INSTANCE__ FSMC_PCCARD instance |
| 816 | * @param __INSTANCE__ FSMC_PCCARD instance |
816 | * @param __FLAG__ FSMC_PCCARD flag |
| 817 | * @param __FLAG__ FSMC_PCCARD flag |
817 | * This parameter can be any combination of the following values: |
| 818 | * This parameter can be any combination of the following values: |
818 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| 819 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
819 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| 820 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
820 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| 821 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
821 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| 822 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
822 | * @retval The state of FLAG (SET or RESET). |
| 823 | * @retval The state of FLAG (SET or RESET). |
823 | */ |
| 824 | */ |
824 | #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) |
| 825 | #define __FSMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__)) |
825 | |
| 826 | 826 | /** |
|
| 827 | /** |
827 | * @brief Clear flag status of the PCCARD device. |
| 828 | * @brief Clear flag status of the PCCARD device. |
828 | * @param __INSTANCE__ FSMC_PCCARD instance |
| 829 | * @param __INSTANCE__ FSMC_PCCARD instance |
829 | * @param __FLAG__ FSMC_PCCARD flag |
| 830 | * @param __FLAG__ FSMC_PCCARD flag |
830 | * This parameter can be any combination of the following values: |
| 831 | * This parameter can be any combination of the following values: |
831 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
| 832 | * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. |
832 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
| 833 | * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. |
833 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
| 834 | * @arg FSMC_FLAG_FALLING_EDGE: Interrupt falling edge flag. |
834 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
| 835 | * @arg FSMC_FLAG_FEMPT: FIFO empty flag. |
835 | * @retval None |
| 836 | * @retval None |
836 | */ |
| 837 | */ |
837 | #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) |
| 838 | #define __FSMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__)) |
838 | |
| 839 | 839 | /** |
|
| 840 | /** |
840 | * @} |
| 841 | * @} |
841 | */ |
| 842 | */ |
842 | #endif |
| 843 | #endif |
843 | |
| 844 | 844 | /** |
|
| 845 | /** |
845 | * @} |
| 846 | * @} |
846 | */ |
| 847 | */ |
847 | |
| 848 | 848 | /** |
|
| 849 | /** |
849 | * @} |
| 850 | * @} |
850 | */ |
| 851 | */ |
851 | |
| 852 | 852 | /* Private functions ---------------------------------------------------------*/ |
|
| 853 | /* Private functions ---------------------------------------------------------*/ |
853 | /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions |
| 854 | /** @defgroup FSMC_LL_Private_Functions FSMC LL Private Functions |
854 | * @{ |
| 855 | * @{ |
855 | */ |
| 856 | */ |
856 | |
| 857 | 857 | #if defined(FSMC_BANK1) |
|
| 858 | #if defined(FSMC_BANK1) |
858 | /** @defgroup FSMC_LL_NORSRAM NOR SRAM |
| 859 | /** @defgroup FSMC_LL_NORSRAM NOR SRAM |
859 | * @{ |
| 860 | * @{ |
860 | */ |
| 861 | */ |
861 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions |
| 862 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions |
862 | * @{ |
| 863 | * @{ |
863 | */ |
| 864 | */ |
864 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, |
| 865 | HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, |
865 | FSMC_NORSRAM_InitTypeDef *Init); |
| 866 | FSMC_NORSRAM_InitTypeDef *Init); |
866 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, |
| 867 | HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, |
867 | FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
| 868 | FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); |
868 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, |
| 869 | HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, |
869 | FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, |
| 870 | FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, |
870 | uint32_t ExtendedMode); |
| 871 | uint32_t ExtendedMode); |
871 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, |
| 872 | HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, |
872 | FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
| 873 | FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); |
873 | /** |
| 874 | /** |
874 | * @} |
| 875 | * @} |
875 | */ |
| 876 | */ |
876 | |
| 877 | 877 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions |
|
| 878 | /** @defgroup FSMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions |
878 | * @{ |
| 879 | * @{ |
879 | */ |
| 880 | */ |
880 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| 881 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
881 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
| 882 | HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank); |
882 | /** |
| 883 | /** |
883 | * @} |
| 884 | * @} |
884 | */ |
| 885 | */ |
885 | /** |
| 886 | /** |
886 | * @} |
| 887 | * @} |
887 | */ |
| 888 | */ |
888 | #endif /* FSMC_BANK1 */ |
| 889 | #endif /* FSMC_BANK1 */ |
889 | |
| 890 | 890 | #if defined(FSMC_BANK3) |
|
| 891 | #if defined(FSMC_BANK3) |
891 | /** @defgroup FSMC_LL_NAND NAND |
| 892 | /** @defgroup FSMC_LL_NAND NAND |
892 | * @{ |
| 893 | * @{ |
893 | */ |
| 894 | */ |
894 | /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions |
| 895 | /** @defgroup FSMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions |
895 | * @{ |
| 896 | * @{ |
896 | */ |
| 897 | */ |
897 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); |
| 898 | HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init); |
898 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, |
| 899 | HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, |
899 | FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| 900 | FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
900 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, |
| 901 | HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, |
901 | FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
| 902 | FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); |
902 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| 903 | HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
903 | /** |
| 904 | /** |
904 | * @} |
| 905 | * @} |
905 | */ |
| 906 | */ |
906 | |
| 907 | 907 | /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions |
|
| 908 | /** @defgroup FSMC_LL_NAND_Private_Functions_Group2 NAND Control functions |
908 | * @{ |
| 909 | * @{ |
909 | */ |
| 910 | */ |
910 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| 911 | HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
911 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
| 912 | HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank); |
912 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, |
| 913 | HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, |
913 | uint32_t Timeout); |
| 914 | uint32_t Timeout); |
914 | /** |
| 915 | /** |
915 | * @} |
| 916 | * @} |
916 | */ |
| 917 | */ |
917 | /** |
| 918 | /** |
918 | * @} |
| 919 | * @} |
919 | */ |
| 920 | */ |
920 | #endif /* FSMC_BANK3 */ |
| 921 | #endif /* FSMC_BANK3 */ |
921 | |
| 922 | 922 | #if defined(FSMC_BANK4) |
|
| 923 | #if defined(FSMC_BANK4) |
923 | /** @defgroup FSMC_LL_PCCARD PCCARD |
| 924 | /** @defgroup FSMC_LL_PCCARD PCCARD |
924 | * @{ |
| 925 | * @{ |
925 | */ |
| 926 | */ |
926 | /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions |
| 927 | /** @defgroup FSMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions |
927 | * @{ |
| 928 | * @{ |
928 | */ |
| 929 | */ |
929 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); |
| 930 | HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init); |
930 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, |
| 931 | HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, |
931 | FSMC_NAND_PCC_TimingTypeDef *Timing); |
| 932 | FSMC_NAND_PCC_TimingTypeDef *Timing); |
932 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, |
| 933 | HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, |
933 | FSMC_NAND_PCC_TimingTypeDef *Timing); |
| 934 | FSMC_NAND_PCC_TimingTypeDef *Timing); |
934 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, |
| 935 | HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, |
935 | FSMC_NAND_PCC_TimingTypeDef *Timing); |
| 936 | FSMC_NAND_PCC_TimingTypeDef *Timing); |
936 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); |
| 937 | HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device); |
937 | /** |
| 938 | /** |
938 | * @} |
| 939 | * @} |
939 | */ |
| 940 | */ |
940 | /** |
| 941 | /** |
941 | * @} |
| 942 | * @} |
942 | */ |
| 943 | */ |
943 | #endif /* FSMC_BANK4 */ |
| 944 | #endif /* FSMC_BANK4 */ |
944 | |
| 945 | 945 | ||
| 946 | 946 | /** |
|
| 947 | /** |
947 | * @} |
| 948 | * @} |
948 | */ |
| 949 | */ |
949 | |
| 950 | 950 | /** |
|
| 951 | /** |
951 | * @} |
| 952 | * @} |
952 | */ |
| 953 | */ |
953 | |
| 954 | 954 | /** |
|
| 955 | /** |
955 | * @} |
| 956 | * @} |
956 | */ |
| 957 | */ |
957 | |
| 958 | 958 | #ifdef __cplusplus |
|
| 959 | #ifdef __cplusplus |
959 | } |
| 960 | } |
960 | #endif |
| 961 | #endif |
961 | |
| 962 | 962 | #endif /* STM32F1xx_LL_FSMC_H */ |
|
| 963 | #endif /* STM32F1xx_LL_FSMC_H */ |
- | |
| 964 | - | ||
| 965 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |