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/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32f1xx_ll_cortex.h
 3 
  * @file    stm32f1xx_ll_cortex.h
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   Header file of CORTEX LL module.
 5 
  * @brief   Header file of CORTEX LL module.
6 
  @verbatim
 6 
  @verbatim
7 
  ==============================================================================
 7 
  ==============================================================================
8 
                     ##### How to use this driver #####
 8 
                     ##### How to use this driver #####
9 
  ==============================================================================
 9 
  ==============================================================================
10 
    [..]
 10 
    [..]
11 
    The LL CORTEX driver contains a set of generic APIs that can be
 11 
    The LL CORTEX driver contains a set of generic APIs that can be
12 
    used by user:
 12 
    used by user:
13 
      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
 13 
      (+) SYSTICK configuration used by LL_mDelay and LL_Init1msTick
14 
          functions
 14 
          functions
15 
      (+) Low power mode configuration (SCB register of Cortex-MCU)
 15 
      (+) Low power mode configuration (SCB register of Cortex-MCU)
16 
      (+) MPU API to configure and enable regions
 16 
      (+) MPU API to configure and enable regions
17 
          (MPU services provided only on some devices)
 17 
          (MPU services provided only on some devices)
18 
      (+) API to access to MCU info (CPUID register)
 18 
      (+) API to access to MCU info (CPUID register)
19 
      (+) API to enable fault handler (SHCSR accesses)
 19 
      (+) API to enable fault handler (SHCSR accesses)
20 
 
 20 
 
21 
  @endverbatim
 21 
  @endverbatim
22 
  ******************************************************************************
 22 
  ******************************************************************************
23 
  * @attention
 23 
  * @attention
24 
  *
 24 
  *
25 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
 25 
  * Copyright (c) 2017 STMicroelectronics.
26 
  * All rights reserved.</center></h2>
 26 
  * All rights reserved.
27 
  *
 27 
  *
28 
  * This software component is licensed by ST under BSD 3-Clause license,
 28 
  * This software is licensed under terms that can be found in the LICENSE file in
29 
  * the "License"; You may not use this file except in compliance with the
 29 
  * the root directory of this software component.
30 
  * License. You may obtain a copy of the License at:
 30 
  * If no LICENSE file comes with this software, it is provided AS-IS.
31 
  *                        opensource.org/licenses/BSD-3-Clause
 31 
  *
32 
  *
 32 
  ******************************************************************************
33 
  ******************************************************************************
 33 
  */
34 
  */
 34 
 
35 
 
 35 
/* Define to prevent recursive inclusion -------------------------------------*/
36 
/* Define to prevent recursive inclusion -------------------------------------*/
 36 
#ifndef __STM32F1xx_LL_CORTEX_H
37 
#ifndef __STM32F1xx_LL_CORTEX_H
 37 
#define __STM32F1xx_LL_CORTEX_H
38 
#define __STM32F1xx_LL_CORTEX_H
 38 
 
39 
 
 39 
#ifdef __cplusplus
40 
#ifdef __cplusplus
 40 
extern "C" {
41 
extern "C" {
 41 
#endif
42 
#endif
 42 
 
43 
 
 43 
/* Includes ------------------------------------------------------------------*/
44 
/* Includes ------------------------------------------------------------------*/
 44 
#include "stm32f1xx.h"
45 
#include "stm32f1xx.h"
 45 
 
46 
 
 46 
/** @addtogroup STM32F1xx_LL_Driver
47 
/** @addtogroup STM32F1xx_LL_Driver
 47 
  * @{
48 
  * @{
 48 
  */
49 
  */
 49 
 
50 
 
 50 
/** @defgroup CORTEX_LL CORTEX
51 
/** @defgroup CORTEX_LL CORTEX
 51 
  * @{
52 
  * @{
 52 
  */
53 
  */
 53 
 
54 
 
 54 
/* Private types -------------------------------------------------------------*/
55 
/* Private types -------------------------------------------------------------*/
 55 
/* Private variables ---------------------------------------------------------*/
56 
/* Private variables ---------------------------------------------------------*/
 56 
 
57 
 
 57 
/* Private constants ---------------------------------------------------------*/
58 
/* Private constants ---------------------------------------------------------*/
 58 
 
59 
 
 59 
/* Private macros ------------------------------------------------------------*/
60 
/* Private macros ------------------------------------------------------------*/
 60 
 
61 
 
 61 
/* Exported types ------------------------------------------------------------*/
62 
/* Exported types ------------------------------------------------------------*/
 62 
/* Exported constants --------------------------------------------------------*/
63 
/* Exported constants --------------------------------------------------------*/
 63 
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
64 
/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
 64 
  * @{
65 
  * @{
 65 
  */
66 
  */
 66 
 
67 
 
 67 
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
68 
/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
 68 
  * @{
69 
  * @{
 69 
  */
70 
  */
 70 
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
71 
#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
 71 
#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
72 
#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
 72 
/**
73 
/**
 73 
  * @}
74 
  * @}
 74 
  */
75 
  */
 75 
 
76 
 
 76 
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
77 
/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
 77 
  * @{
78 
  * @{
 78 
  */
79 
  */
 79 
#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
80 
#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
 80 
#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
81 
#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
 81 
#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
82 
#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
 82 
/**
83 
/**
 83 
  * @}
84 
  * @}
 84 
  */
85 
  */
 85 
 
86 
 
 86 
#if __MPU_PRESENT
87 
#if __MPU_PRESENT
 87 
 
88 
 
 88 
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
89 
/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
 89 
  * @{
90 
  * @{
 90 
  */
91 
  */
 91 
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
92 
#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
 92 
#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
93 
#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
 93 
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
94 
#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
 94 
#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
95 
#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
 95 
/**
96 
/**
 96 
  * @}
97 
  * @}
 97 
  */
98 
  */
 98 
 
99 
 
 99 
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
100 
/** @defgroup CORTEX_LL_EC_REGION MPU Region Number
 100 
  * @{
101 
  * @{
 101 
  */
102 
  */
 102 
#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
103 
#define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
 103 
#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
104 
#define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
 104 
#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
105 
#define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
 105 
#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
106 
#define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
 106 
#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
107 
#define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
 107 
#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
108 
#define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
 108 
#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
109 
#define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
 109 
#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
110 
#define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
 110 
/**
111 
/**
 111 
  * @}
112 
  * @}
 112 
  */
113 
  */
 113 
 
114 
 
 114 
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
115 
/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
 115 
  * @{
116 
  * @{
 116 
  */
117 
  */
 117 
#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
118 
#define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
 118 
#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
119 
#define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
 119 
#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
120 
#define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
 120 
#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
121 
#define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
 121 
#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
122 
#define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
 122 
#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
123 
#define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
 123 
#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
124 
#define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
 124 
#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
125 
#define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
 125 
#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
126 
#define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
 126 
#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
127 
#define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
 127 
#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
128 
#define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
 128 
#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
129 
#define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
 129 
#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
130 
#define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
 130 
#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
131 
#define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
 131 
#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
132 
#define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
 132 
#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
133 
#define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
 133 
#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
134 
#define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
 134 
#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
135 
#define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
 135 
#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
136 
#define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
 136 
#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
137 
#define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
 137 
#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
138 
#define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
 138 
#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
139 
#define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
 139 
#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
140 
#define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
 140 
#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
141 
#define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
 141 
#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
142 
#define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
 142 
#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
143 
#define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
 143 
#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
144 
#define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
 144 
#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
145 
#define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
 145 
/**
146 
/**
 146 
  * @}
147 
  * @}
 147 
  */
148 
  */
 148 
 
149 
 
 149 
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
150 
/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
 150 
  * @{
151 
  * @{
 151 
  */
152 
  */
 152 
#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
153 
#define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
 153 
#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
154 
#define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
 154 
#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
155 
#define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
 155 
#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
156 
#define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
 156 
#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
157 
#define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
 157 
#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
158 
#define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
 158 
/**
159 
/**
 159 
  * @}
160 
  * @}
 160 
  */
161 
  */
 161 
 
162 
 
 162 
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
163 
/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
 163 
  * @{
164 
  * @{
 164 
  */
165 
  */
 165 
#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
166 
#define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
 166 
#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
167 
#define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
 167 
#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
168 
#define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
 168 
#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
169 
#define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
 169 
/**
170 
/**
 170 
  * @}
171 
  * @}
 171 
  */
172 
  */
 172 
 
173 
 
 173 
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
174 
/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
 174 
  * @{
175 
  * @{
 175 
  */
176 
  */
 176 
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
177 
#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
 177 
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
178 
#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
 178 
/**
179 
/**
 179 
  * @}
180 
  * @}
 180 
  */
181 
  */
 181 
 
182 
 
 182 
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
183 
/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
 183 
  * @{
184 
  * @{
 184 
  */
185 
  */
 185 
#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
186 
#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
 186 
#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
187 
#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
 187 
/**
188 
/**
 188 
  * @}
189 
  * @}
 189 
  */
190 
  */
 190 
 
191 
 
 191 
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
192 
/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
 192 
  * @{
193 
  * @{
 193 
  */
194 
  */
 194 
#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
195 
#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
 195 
#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
196 
#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
 196 
/**
197 
/**
 197 
  * @}
198 
  * @}
 198 
  */
199 
  */
 199 
 
200 
 
 200 
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
201 
/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
 201 
  * @{
202 
  * @{
 202 
  */
203 
  */
 203 
#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
204 
#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
 204 
#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
205 
#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
 205 
/**
206 
/**
 206 
  * @}
207 
  * @}
 207 
  */
208 
  */
 208 
#endif /* __MPU_PRESENT */
209 
#endif /* __MPU_PRESENT */
 209 
/**
210 
/**
 210 
  * @}
211 
  * @}
 211 
  */
212 
  */
 212 
 
213 
 
 213 
/* Exported macro ------------------------------------------------------------*/
214 
/* Exported macro ------------------------------------------------------------*/
 214 
 
215 
 
 215 
/* Exported functions --------------------------------------------------------*/
216 
/* Exported functions --------------------------------------------------------*/
 216 
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
217 
/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
 217 
  * @{
218 
  * @{
 218 
  */
219 
  */
 219 
 
220 
 
 220 
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
221 
/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
 221 
  * @{
222 
  * @{
 222 
  */
223 
  */
 223 
 
224 
 
 224 
/**
225 
/**
 225 
  * @brief  This function checks if the Systick counter flag is active or not.
226 
  * @brief  This function checks if the Systick counter flag is active or not.
 226 
  * @note   It can be used in timeout function on application side.
227 
  * @note   It can be used in timeout function on application side.
 227 
  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
228 
  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
 228 
  * @retval State of bit (1 or 0).
229 
  * @retval State of bit (1 or 0).
 229 
  */
230 
  */
 230 
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
231 
__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
 231 
{
232 
{
 232 
  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
233 
  return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
 233 
}
234 
}
 234 
 
235 
 
 235 
/**
236 
/**
 236 
  * @brief  Configures the SysTick clock source
237 
  * @brief  Configures the SysTick clock source
 237 
  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
238 
  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
 238 
  * @param  Source This parameter can be one of the following values:
239 
  * @param  Source This parameter can be one of the following values:
 239 
  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
240 
  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
 240 
  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
241 
  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
 241 
  * @retval None
242 
  * @retval None
 242 
  */
243 
  */
 243 
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
244 
__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
 244 
{
245 
{
 245 
  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
246 
  if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
 246 
  {
247 
  {
 247 
    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
248 
    SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
 248 
  }
249 
  }
 249 
  else
250 
  else
 250 
  {
251 
  {
 251 
    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
252 
    CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
 252 
  }
253 
  }
 253 
}
254 
}
 254 
 
255 
 
 255 
/**
256 
/**
 256 
  * @brief  Get the SysTick clock source
257 
  * @brief  Get the SysTick clock source
 257 
  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
258 
  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
 258 
  * @retval Returned value can be one of the following values:
259 
  * @retval Returned value can be one of the following values:
 259 
  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
260 
  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
 260 
  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
261 
  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
 261 
  */
262 
  */
 262 
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
263 
__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
 263 
{
264 
{
 264 
  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
265 
  return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
 265 
}
266 
}
 266 
 
267 
 
 267 
/**
268 
/**
 268 
  * @brief  Enable SysTick exception request
269 
  * @brief  Enable SysTick exception request
 269 
  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
270 
  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
 270 
  * @retval None
271 
  * @retval None
 271 
  */
272 
  */
 272 
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
273 
__STATIC_INLINE void LL_SYSTICK_EnableIT(void)
 273 
{
274 
{
 274 
  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
275 
  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
 275 
}
276 
}
 276 
 
277 
 
 277 
/**
278 
/**
 278 
  * @brief  Disable SysTick exception request
279 
  * @brief  Disable SysTick exception request
 279 
  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
280 
  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
 280 
  * @retval None
281 
  * @retval None
 281 
  */
282 
  */
 282 
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
283 
__STATIC_INLINE void LL_SYSTICK_DisableIT(void)
 283 
{
284 
{
 284 
  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
285 
  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
 285 
}
286 
}
 286 
 
287 
 
 287 
/**
288 
/**
 288 
  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
289 
  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
 289 
  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
290 
  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
 290 
  * @retval State of bit (1 or 0).
291 
  * @retval State of bit (1 or 0).
 291 
  */
292 
  */
 292 
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
293 
__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
 293 
{
294 
{
 294 
  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
295 
  return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
 295 
}
296 
}
 296 
 
297 
 
 297 
/**
298 
/**
 298 
  * @}
299 
  * @}
 299 
  */
300 
  */
 300 
 
301 
 
 301 
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
302 
/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
 302 
  * @{
303 
  * @{
 303 
  */
304 
  */
 304 
 
305 
 
 305 
/**
306 
/**
 306 
  * @brief  Processor uses sleep as its low power mode
307 
  * @brief  Processor uses sleep as its low power mode
 307 
  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
308 
  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
 308 
  * @retval None
309 
  * @retval None
 309 
  */
310 
  */
 310 
__STATIC_INLINE void LL_LPM_EnableSleep(void)
311 
__STATIC_INLINE void LL_LPM_EnableSleep(void)
 311 
{
312 
{
 312 
  /* Clear SLEEPDEEP bit of Cortex System Control Register */
313 
  /* Clear SLEEPDEEP bit of Cortex System Control Register */
 313 
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
314 
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 314 
}
315 
}
 315 
 
316 
 
 316 
/**
317 
/**
 317 
  * @brief  Processor uses deep sleep as its low power mode
318 
  * @brief  Processor uses deep sleep as its low power mode
 318 
  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
319 
  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
 319 
  * @retval None
320 
  * @retval None
 320 
  */
321 
  */
 321 
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
322 
__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
 322 
{
323 
{
 323 
  /* Set SLEEPDEEP bit of Cortex System Control Register */
324 
  /* Set SLEEPDEEP bit of Cortex System Control Register */
 324 
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
325 
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 325 
}
326 
}
 326 
 
327 
 
 327 
/**
328 
/**
 328 
  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
329 
  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
 329 
  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
330 
  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
 330 
  *         empty main application.
331 
  *         empty main application.
 331 
  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
332 
  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
 332 
  * @retval None
333 
  * @retval None
 333 
  */
334 
  */
 334 
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
335 
__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
 335 
{
336 
{
 336 
  /* Set SLEEPONEXIT bit of Cortex System Control Register */
337 
  /* Set SLEEPONEXIT bit of Cortex System Control Register */
 337 
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
338 
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 338 
}
339 
}
 339 
 
340 
 
 340 
/**
341 
/**
 341 
  * @brief  Do not sleep when returning to Thread mode.
342 
  * @brief  Do not sleep when returning to Thread mode.
 342 
  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
343 
  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
 343 
  * @retval None
344 
  * @retval None
 344 
  */
345 
  */
 345 
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
346 
__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
 346 
{
347 
{
 347 
  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
348 
  /* Clear SLEEPONEXIT bit of Cortex System Control Register */
 348 
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
349 
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 349 
}
350 
}
 350 
 
351 
 
 351 
/**
352 
/**
 352 
  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
353 
  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
 353 
  *         processor.
354 
  *         processor.
 354 
  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
355 
  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
 355 
  * @retval None
356 
  * @retval None
 356 
  */
357 
  */
 357 
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
358 
__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
 358 
{
359 
{
 359 
  /* Set SEVEONPEND bit of Cortex System Control Register */
360 
  /* Set SEVEONPEND bit of Cortex System Control Register */
 360 
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
361 
  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
 361 
}
362 
}
 362 
 
363 
 
 363 
/**
364 
/**
 364 
  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
365 
  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
 365 
  *         excluded
366 
  *         excluded
 366 
  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
367 
  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
 367 
  * @retval None
368 
  * @retval None
 368 
  */
369 
  */
 369 
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
370 
__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
 370 
{
371 
{
 371 
  /* Clear SEVEONPEND bit of Cortex System Control Register */
372 
  /* Clear SEVEONPEND bit of Cortex System Control Register */
 372 
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
373 
  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
 373 
}
374 
}
 374 
 
375 
 
 375 
/**
376 
/**
 376 
  * @}
377 
  * @}
 377 
  */
378 
  */
 378 
 
379 
 
 379 
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
380 
/** @defgroup CORTEX_LL_EF_HANDLER HANDLER
 380 
  * @{
381 
  * @{
 381 
  */
382 
  */
 382 
 
383 
 
 383 
/**
384 
/**
 384 
  * @brief  Enable a fault in System handler control register (SHCSR)
385 
  * @brief  Enable a fault in System handler control register (SHCSR)
 385 
  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
386 
  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
 386 
  * @param  Fault This parameter can be a combination of the following values:
387 
  * @param  Fault This parameter can be a combination of the following values:
 387 
  *         @arg @ref LL_HANDLER_FAULT_USG
388 
  *         @arg @ref LL_HANDLER_FAULT_USG
 388 
  *         @arg @ref LL_HANDLER_FAULT_BUS
389 
  *         @arg @ref LL_HANDLER_FAULT_BUS
 389 
  *         @arg @ref LL_HANDLER_FAULT_MEM
390 
  *         @arg @ref LL_HANDLER_FAULT_MEM
 390 
  * @retval None
391 
  * @retval None
 391 
  */
392 
  */
 392 
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
393 
__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
 393 
{
394 
{
 394 
  /* Enable the system handler fault */
395 
  /* Enable the system handler fault */
 395 
  SET_BIT(SCB->SHCSR, Fault);
396 
  SET_BIT(SCB->SHCSR, Fault);
 396 
}
397 
}
 397 
 
398 
 
 398 
/**
399 
/**
 399 
  * @brief  Disable a fault in System handler control register (SHCSR)
400 
  * @brief  Disable a fault in System handler control register (SHCSR)
 400 
  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
401 
  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
 401 
  * @param  Fault This parameter can be a combination of the following values:
402 
  * @param  Fault This parameter can be a combination of the following values:
 402 
  *         @arg @ref LL_HANDLER_FAULT_USG
403 
  *         @arg @ref LL_HANDLER_FAULT_USG
 403 
  *         @arg @ref LL_HANDLER_FAULT_BUS
404 
  *         @arg @ref LL_HANDLER_FAULT_BUS
 404 
  *         @arg @ref LL_HANDLER_FAULT_MEM
405 
  *         @arg @ref LL_HANDLER_FAULT_MEM
 405 
  * @retval None
406 
  * @retval None
 406 
  */
407 
  */
 407 
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
408 
__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
 408 
{
409 
{
 409 
  /* Disable the system handler fault */
410 
  /* Disable the system handler fault */
 410 
  CLEAR_BIT(SCB->SHCSR, Fault);
411 
  CLEAR_BIT(SCB->SHCSR, Fault);
 411 
}
412 
}
 412 
 
413 
 
 413 
/**
414 
/**
 414 
  * @}
415 
  * @}
 415 
  */
416 
  */
 416 
 
417 
 
 417 
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
418 
/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
 418 
  * @{
419 
  * @{
 419 
  */
420 
  */
 420 
 
421 
 
 421 
/**
422 
/**
 422 
  * @brief  Get Implementer code
423 
  * @brief  Get Implementer code
 423 
  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
424 
  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
 424 
  * @retval Value should be equal to 0x41 for ARM
425 
  * @retval Value should be equal to 0x41 for ARM
 425 
  */
426 
  */
 426 
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
427 
__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
 427 
{
428 
{
 428 
  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
429 
  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
 429 
}
430 
}
 430 
 
431 
 
 431 
/**
432 
/**
 432 
  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
433 
  * @brief  Get Variant number (The r value in the rnpn product revision identifier)
 433 
  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
434 
  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
 434 
  * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
435 
  * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
 435 
  */
436 
  */
 436 
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
437 
__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
 437 
{
438 
{
 438 
  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
439 
  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
 439 
}
440 
}
 440 
 
441 
 
 441 
/**
442 
/**
 442 
  * @brief  Get Constant number
443 
  * @brief  Get Constant number
 443 
  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
444 
  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
 444 
  * @retval Value should be equal to 0xF for Cortex-M3 devices
445 
  * @retval Value should be equal to 0xF for Cortex-M3 devices
 445 
  */
446 
  */
 446 
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
447 
__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
 447 
{
448 
{
 448 
  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
449 
  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
 449 
}
450 
}
 450 
 
451 
 
 451 
/**
452 
/**
 452 
  * @brief  Get Part number
453 
  * @brief  Get Part number
 453 
  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
454 
  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
 454 
  * @retval Value should be equal to 0xC23 for Cortex-M3
455 
  * @retval Value should be equal to 0xC23 for Cortex-M3
 455 
  */
456 
  */
 456 
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
457 
__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
 457 
{
458 
{
 458 
  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
459 
  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
 459 
}
460 
}
 460 
 
461 
 
 461 
/**
462 
/**
 462 
  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
463 
  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
 463 
  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
464 
  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
 464 
  * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
465 
  * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
 465 
  */
466 
  */
 466 
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
467 
__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
 467 
{
468 
{
 468 
  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
469 
  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
 469 
}
470 
}
 470 
 
471 
 
 471 
/**
472 
/**
 472 
  * @}
473 
  * @}
 473 
  */
474 
  */
 474 
 
475 
 
 475 
#if __MPU_PRESENT
476 
#if __MPU_PRESENT
 476 
/** @defgroup CORTEX_LL_EF_MPU MPU
477 
/** @defgroup CORTEX_LL_EF_MPU MPU
 477 
  * @{
478 
  * @{
 478 
  */
479 
  */
 479 
 
480 
 
 480 
/**
481 
/**
 481 
  * @brief  Enable MPU with input options
482 
  * @brief  Enable MPU with input options
 482 
  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
483 
  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
 483 
  * @param  Options This parameter can be one of the following values:
484 
  * @param  Options This parameter can be one of the following values:
 484 
  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
485 
  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
 485 
  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
486 
  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
 486 
  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
487 
  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
 487 
  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
488 
  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
 488 
  * @retval None
489 
  * @retval None
 489 
  */
490 
  */
 490 
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
491 
__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
 491 
{
492 
{
 492 
  /* Enable the MPU*/
493 
  /* Enable the MPU*/
 493 
  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
494 
  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
 494 
  /* Ensure MPU settings take effects */
495 
  /* Ensure MPU settings take effects */
 495 
  __DSB();
496 
  __DSB();
 496 
  /* Sequence instruction fetches using update settings */
497 
  /* Sequence instruction fetches using update settings */
 497 
  __ISB();
498 
  __ISB();
 498 
}
499 
}
 499 
 
500 
 
 500 
/**
501 
/**
 501 
  * @brief  Disable MPU
502 
  * @brief  Disable MPU
 502 
  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
503 
  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
 503 
  * @retval None
504 
  * @retval None
 504 
  */
505 
  */
 505 
__STATIC_INLINE void LL_MPU_Disable(void)
506 
__STATIC_INLINE void LL_MPU_Disable(void)
 506 
{
507 
{
 507 
  /* Make sure outstanding transfers are done */
508 
  /* Make sure outstanding transfers are done */
 508 
  __DMB();
509 
  __DMB();
 509 
  /* Disable MPU*/
510 
  /* Disable MPU*/
 510 
  WRITE_REG(MPU->CTRL, 0U);
511 
  WRITE_REG(MPU->CTRL, 0U);
 511 
}
512 
}
 512 
 
513 
 
 513 
/**
514 
/**
 514 
  * @brief  Check if MPU is enabled or not
515 
  * @brief  Check if MPU is enabled or not
 515 
  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
516 
  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
 516 
  * @retval State of bit (1 or 0).
517 
  * @retval State of bit (1 or 0).
 517 
  */
518 
  */
 518 
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
519 
__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
 519 
{
520 
{
 520 
  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
521 
  return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
 521 
}
522 
}
 522 
 
523 
 
 523 
/**
524 
/**
 524 
  * @brief  Enable a MPU region
525 
  * @brief  Enable a MPU region
 525 
  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
526 
  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
 526 
  * @param  Region This parameter can be one of the following values:
527 
  * @param  Region This parameter can be one of the following values:
 527 
  *         @arg @ref LL_MPU_REGION_NUMBER0
528 
  *         @arg @ref LL_MPU_REGION_NUMBER0
 528 
  *         @arg @ref LL_MPU_REGION_NUMBER1
529 
  *         @arg @ref LL_MPU_REGION_NUMBER1
 529 
  *         @arg @ref LL_MPU_REGION_NUMBER2
530 
  *         @arg @ref LL_MPU_REGION_NUMBER2
 530 
  *         @arg @ref LL_MPU_REGION_NUMBER3
531 
  *         @arg @ref LL_MPU_REGION_NUMBER3
 531 
  *         @arg @ref LL_MPU_REGION_NUMBER4
532 
  *         @arg @ref LL_MPU_REGION_NUMBER4
 532 
  *         @arg @ref LL_MPU_REGION_NUMBER5
533 
  *         @arg @ref LL_MPU_REGION_NUMBER5
 533 
  *         @arg @ref LL_MPU_REGION_NUMBER6
534 
  *         @arg @ref LL_MPU_REGION_NUMBER6
 534 
  *         @arg @ref LL_MPU_REGION_NUMBER7
535 
  *         @arg @ref LL_MPU_REGION_NUMBER7
 535 
  * @retval None
536 
  * @retval None
 536 
  */
537 
  */
 537 
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
538 
__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
 538 
{
539 
{
 539 
  /* Set Region number */
540 
  /* Set Region number */
 540 
  WRITE_REG(MPU->RNR, Region);
541 
  WRITE_REG(MPU->RNR, Region);
 541 
  /* Enable the MPU region */
542 
  /* Enable the MPU region */
 542 
  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
543 
  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
 543 
}
544 
}
 544 
 
545 
 
 545 
/**
546 
/**
 546 
  * @brief  Configure and enable a region
547 
  * @brief  Configure and enable a region
 547 
  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
548 
  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
 548 
  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
549 
  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
 549 
  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
550 
  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
 550 
  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
551 
  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
 551 
  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
552 
  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
 552 
  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
553 
  *         MPU_RASR     S             LL_MPU_ConfigRegion\n
 553 
  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
554 
  *         MPU_RASR     C             LL_MPU_ConfigRegion\n
 554 
  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
555 
  *         MPU_RASR     B             LL_MPU_ConfigRegion\n
 555 
  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
556 
  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
 556 
  * @param  Region This parameter can be one of the following values:
557 
  * @param  Region This parameter can be one of the following values:
 557 
  *         @arg @ref LL_MPU_REGION_NUMBER0
558 
  *         @arg @ref LL_MPU_REGION_NUMBER0
 558 
  *         @arg @ref LL_MPU_REGION_NUMBER1
559 
  *         @arg @ref LL_MPU_REGION_NUMBER1
 559 
  *         @arg @ref LL_MPU_REGION_NUMBER2
560 
  *         @arg @ref LL_MPU_REGION_NUMBER2
 560 
  *         @arg @ref LL_MPU_REGION_NUMBER3
561 
  *         @arg @ref LL_MPU_REGION_NUMBER3
 561 
  *         @arg @ref LL_MPU_REGION_NUMBER4
562 
  *         @arg @ref LL_MPU_REGION_NUMBER4
 562 
  *         @arg @ref LL_MPU_REGION_NUMBER5
563 
  *         @arg @ref LL_MPU_REGION_NUMBER5
 563 
  *         @arg @ref LL_MPU_REGION_NUMBER6
564 
  *         @arg @ref LL_MPU_REGION_NUMBER6
 564 
  *         @arg @ref LL_MPU_REGION_NUMBER7
565 
  *         @arg @ref LL_MPU_REGION_NUMBER7
 565 
  * @param  Address Value of region base address
566 
  * @param  Address Value of region base address
 566 
  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
567 
  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
 567 
  * @param  Attributes This parameter can be a combination of the following values:
568 
  * @param  Attributes This parameter can be a combination of the following values:
 568 
  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
569 
  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
 569 
  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
570 
  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
 570 
  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
571 
  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
 571 
  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
572 
  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
 572 
  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
573 
  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
 573 
  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
574 
  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
 574 
  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
575 
  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
 575 
  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
576 
  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
 576 
  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
577 
  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
 577 
  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
578 
  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
 578 
  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
579 
  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
 579 
  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
580 
  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
 580 
  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
581 
  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
 581 
  * @retval None
582 
  * @retval None
 582 
  */
583 
  */
 583 
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
584 
__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
 584 
{
585 
{
 585 
  /* Set Region number */
586 
  /* Set Region number */
 586 
  WRITE_REG(MPU->RNR, Region);
587 
  WRITE_REG(MPU->RNR, Region);
 587 
  /* Set base address */
588 
  /* Set base address */
 588 
  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
589 
  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
 589 
  /* Configure MPU */
590 
  /* Configure MPU */
 590 
  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
591 
  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
 591 
}
592 
}
 592 
 
593 
 
 593 
/**
594 
/**
 594 
  * @brief  Disable a region
595 
  * @brief  Disable a region
 595 
  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
596 
  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
 596 
  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
597 
  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
 597 
  * @param  Region This parameter can be one of the following values:
598 
  * @param  Region This parameter can be one of the following values:
 598 
  *         @arg @ref LL_MPU_REGION_NUMBER0
599 
  *         @arg @ref LL_MPU_REGION_NUMBER0
 599 
  *         @arg @ref LL_MPU_REGION_NUMBER1
600 
  *         @arg @ref LL_MPU_REGION_NUMBER1
 600 
  *         @arg @ref LL_MPU_REGION_NUMBER2
601 
  *         @arg @ref LL_MPU_REGION_NUMBER2
 601 
  *         @arg @ref LL_MPU_REGION_NUMBER3
602 
  *         @arg @ref LL_MPU_REGION_NUMBER3
 602 
  *         @arg @ref LL_MPU_REGION_NUMBER4
603 
  *         @arg @ref LL_MPU_REGION_NUMBER4
 603 
  *         @arg @ref LL_MPU_REGION_NUMBER5
604 
  *         @arg @ref LL_MPU_REGION_NUMBER5
 604 
  *         @arg @ref LL_MPU_REGION_NUMBER6
605 
  *         @arg @ref LL_MPU_REGION_NUMBER6
 605 
  *         @arg @ref LL_MPU_REGION_NUMBER7
606 
  *         @arg @ref LL_MPU_REGION_NUMBER7
 606 
  * @retval None
607 
  * @retval None
 607 
  */
608 
  */
 608 
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
609 
__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
 609 
{
610 
{
 610 
  /* Set Region number */
611 
  /* Set Region number */
 611 
  WRITE_REG(MPU->RNR, Region);
612 
  WRITE_REG(MPU->RNR, Region);
 612 
  /* Disable the MPU region */
613 
  /* Disable the MPU region */
 613 
  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
614 
  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
 614 
}
615 
}
 615 
 
616 
 
 616 
/**
617 
/**
 617 
  * @}
618 
  * @}
 618 
  */
619 
  */
 619 
 
620 
 
 620 
#endif /* __MPU_PRESENT */
621 
#endif /* __MPU_PRESENT */
 621 
/**
622 
/**
 622 
  * @}
623 
  * @}
 623 
  */
624 
  */
 624 
 
625 
 
 625 
/**
626 
/**
 626 
  * @}
627 
  * @}
 627 
  */
628 
  */
 628 
 
629 
 
 629 
/**
630 
/**
 630 
  * @}
631 
  * @}
 631 
  */
632 
  */
 632 
 
633 
 
 633 
#ifdef __cplusplus
634 
#ifdef __cplusplus
 634 
}
635 
}
 635 
#endif
636 
#endif
 636 
 
637 
 
 637 
#endif /* __STM32F1xx_LL_CORTEX_H */
638 
#endif /* __STM32F1xx_LL_CORTEX_H */
 638 
 
639 
 
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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