WebSVN – LedShow – Diff – /trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h



  * @author  MCD Application Team
  * @brief   Header file of ADC LL module.
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
  * All rights reserved.</center></h2>
  *
  * This software component is licensed by ST under BSD 3-Clause license,
  * the "License"; You may not use this file except in compliance with the
 
 
 
 
  * License. You may obtain a copy of the License at:
 
  *                        opensource.org/licenses/BSD-3-Clause
 
 
 
 
 
 
 
 
 
 
 
 
  *
  ******************************************************************************
  */
 
/* Define to prevent recursive inclusion -------------------------------------*/

  * @param  __REG__ Register basis from which the offset is applied.
  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
  * @retval Pointer to register address
  */
#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
 ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
 
/**
  * @}
  */
 

{
  /* Set bits with content of parameter "Channel" with bits position          */
  /* in register and register position depending on parameter "Rank".         */
  /* Parameters "Rank" and "Channel" are used with masks because containing   */
  /* other bits reserved for other purpose.                                   */
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
 
  MODIFY_REG(*preg,
             ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
             (Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}

  *             comparison with internal channel parameter to be done
  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
  */
__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
{
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
 
  return (uint32_t) (READ_BIT(*preg,
                              ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
                     >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
                    );

  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
  * @retval None
  */
__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
{
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
 
  MODIFY_REG(*preg,
             ADC_JOFR1_JOFFSET1,
             OffsetLevel);
}

  *         @arg @ref LL_ADC_INJ_RANK_4
  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  */
__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
{
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
 
  return (uint32_t)(READ_BIT(*preg,
                             ADC_JOFR1_JOFFSET1)
                   );
}

{
  /* Set bits with content of parameter "SamplingTime" with bits position     */
  /* in register and register position depending on parameter "Channel".      */
  /* Parameter "Channel" is used with masks because containing                */
  /* other bits reserved for other purpose.                                   */
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
 
  MODIFY_REG(*preg,
             ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
             SamplingTime   << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
}

  *         @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
  *         @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
  */
__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
{
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
 
  return (uint32_t)(READ_BIT(*preg,
                             ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
                    >> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
                   );

  * @param  AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
  * @retval None
  */
__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
{
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
 
  MODIFY_REG(*preg,
             ADC_HTR_HT,
             AWDThresholdValue);
}

  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
*/
__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
{
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
 
  return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
}
 
/**

  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTTRIG);
}
 
/**
  * @brief  Get ADC group regular conversion data, range fit for
  *         all ADC configurations: all ADC resolutions and

  * @param  ADCx ADC instance
  * @retval None
  */
__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
{
  CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTTRIG);
}
 
/**
  * @brief  Get ADC group regular conversion data, range fit for
  *         all ADC configurations: all ADC resolutions and

  *         @arg @ref LL_ADC_INJ_RANK_4
  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
  */
__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
{
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
 
  return (uint32_t)(READ_BIT(*preg,
                             ADC_JDR1_JDATA)
                   );
}

  *         @arg @ref LL_ADC_INJ_RANK_4
  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
  */
__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
{
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
 
  return (uint16_t)(READ_BIT(*preg,
                             ADC_JDR1_JDATA)
                   );
}

  /* Note: on this STM32 serie, there is no flag ADC group regular           */
  /*       end of unitary conversion.                                         */
  /*       Flag noted as "EOC" is corresponding to flag "EOS"                 */
  /*       in other STM32 families).                                          */
 
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
 
  return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
}
 
 

  /* Note: on this STM32 serie, there is no flag ADC group injected          */
  /*       end of unitary conversion.                                         */
  /*       Flag noted as "JEOC" is corresponding to flag "JEOS"               */
  /*       in other STM32 families).                                          */
 
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
 
  return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
}
 
/**

  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
  * @retval State of bit (1 or 0).
  */
__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
{
  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
 
  return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
}
 
#endif /* ADC_MULTIMODE_SUPPORT */

Rev 2	Rev 9
Line 4...	Line 4...
4	* @author MCD Application Team	4	* @author MCD Application Team
5	* @brief Header file of ADC LL module.	5	* @brief Header file of ADC LL module.
6	******************************************************************************	6	******************************************************************************
7	* @attention	7	* @attention
8	*	8	*
9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>	9	* <h2><center>© Copyright (c) 2017 STMicroelectronics.
-		10	* All rights reserved.</center></h2>
10	*	11	*
11	* Redistribution and use in source and binary forms, with or without modification,	12	* This software component is licensed by ST under BSD 3-Clause license,
12	* are permitted provided that the following conditions are met:	13	* the "License"; You may not use this file except in compliance with the
13	* 1. Redistributions of source code must retain the above copyright notice,	-
14	* this list of conditions and the following disclaimer.	-
15	* 2. Redistributions in binary form must reproduce the above copyright notice,	-
16	* this list of conditions and the following disclaimer in the documentation	-
17	* and/or other materials provided with the distribution.	14	* License. You may obtain a copy of the License at:
18	* 3. Neither the name of STMicroelectronics nor the names of its contributors	-
19	* may be used to endorse or promote products derived from this software	15	* opensource.org/licenses/BSD-3-Clause
20	* without specific prior written permission.	-
21	*	-
22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"	-
23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE	-
24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE	-
25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE	-
26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL	-
27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR	-
28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER	-
29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,	-
30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE	-
31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	-
32	*	16	*
33	******************************************************************************	17	******************************************************************************
34	*/	18	*/
35		19
36	/* Define to prevent recursive inclusion -------------------------------------*/	20	/* Define to prevent recursive inclusion -------------------------------------*/
Line 240...	Line 224...
240	* @param __REG__ Register basis from which the offset is applied.	224	* @param __REG__ Register basis from which the offset is applied.
241	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).	225	* @param __REG_OFFFSET__ Offset to be applied (unit: number of registers).
242	* @retval Pointer to register address	226	* @retval Pointer to register address
243	*/	227	*/
244	#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \	228	#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \
245	((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))	229	((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U))))
246		230
247	/**	231	/**
248	* @}	232	* @}
249	*/	233	*/
250		234
Line 2148...	Line 2132...
2148	{	2132	{
2149	/* Set bits with content of parameter "Channel" with bits position */	2133	/* Set bits with content of parameter "Channel" with bits position */
2150	/* in register and register position depending on parameter "Rank". */	2134	/* in register and register position depending on parameter "Rank". */
2151	/* Parameters "Rank" and "Channel" are used with masks because containing */	2135	/* Parameters "Rank" and "Channel" are used with masks because containing */
2152	/* other bits reserved for other purpose. */	2136	/* other bits reserved for other purpose. */
2153	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));	2137	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2154		2138
2155	MODIFY_REG(*preg,	2139	MODIFY_REG(*preg,
2156	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),	2140	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
2157	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));	2141	(Channel & ADC_CHANNEL_ID_NUMBER_MASK) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
2158	}	2142	}
Line 2238...	Line 2222...
2238	* comparison with internal channel parameter to be done	2222	* comparison with internal channel parameter to be done
2239	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().	2223	* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
2240	*/	2224	*/
2241	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)	2225	__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)
2242	{	2226	{
2243	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));	2227	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, __ADC_MASK_SHIFT(Rank, ADC_REG_SQRX_REGOFFSET_MASK));
2244		2228
2245	return (uint32_t) (READ_BIT(*preg,	2229	return (uint32_t) (READ_BIT(*preg,
2246	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))	2230	ADC_CHANNEL_ID_NUMBER_MASK << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
2247	>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)	2231	>> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
2248	);	2232	);
Line 2734...	Line 2718...
2734	* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF	2718	* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
2735	* @retval None	2719	* @retval None
2736	*/	2720	*/
2737	__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)	2721	__STATIC_INLINE void LL_ADC_INJ_SetOffset(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t OffsetLevel)
2738	{	2722	{
2739	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));	2723	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
2740		2724
2741	MODIFY_REG(*preg,	2725	MODIFY_REG(*preg,
2742	ADC_JOFR1_JOFFSET1,	2726	ADC_JOFR1_JOFFSET1,
2743	OffsetLevel);	2727	OffsetLevel);
2744	}	2728	}
Line 2761...	Line 2745...
2761	* @arg @ref LL_ADC_INJ_RANK_4	2745	* @arg @ref LL_ADC_INJ_RANK_4
2762	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF	2746	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
2763	*/	2747	*/
2764	__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)	2748	__STATIC_INLINE uint32_t LL_ADC_INJ_GetOffset(ADC_TypeDef *ADCx, uint32_t Rank)
2765	{	2749	{
2766	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));	2750	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JOFR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JOFRX_REGOFFSET_MASK));
2767		2751
2768	return (uint32_t)(READ_BIT(*preg,	2752	return (uint32_t)(READ_BIT(*preg,
2769	ADC_JOFR1_JOFFSET1)	2753	ADC_JOFR1_JOFFSET1)
2770	);	2754	);
2771	}	2755	}
Line 2854...	Line 2838...
2854	{	2838	{
2855	/* Set bits with content of parameter "SamplingTime" with bits position */	2839	/* Set bits with content of parameter "SamplingTime" with bits position */
2856	/* in register and register position depending on parameter "Channel". */	2840	/* in register and register position depending on parameter "Channel". */
2857	/* Parameter "Channel" is used with masks because containing */	2841	/* Parameter "Channel" is used with masks because containing */
2858	/* other bits reserved for other purpose. */	2842	/* other bits reserved for other purpose. */
2859	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));	2843	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
2860		2844
2861	MODIFY_REG(*preg,	2845	MODIFY_REG(*preg,
2862	ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),	2846	ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK),
2863	SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));	2847	SamplingTime << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK));
2864	}	2848	}
Line 2923...	Line 2907...
2923	* @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5	2907	* @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5
2924	* @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5	2908	* @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5
2925	*/	2909	*/
2926	__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)	2910	__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)
2927	{	2911	{
2928	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));	2912	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPRX_REGOFFSET_MASK));
2929		2913
2930	return (uint32_t)(READ_BIT(*preg,	2914	return (uint32_t)(READ_BIT(*preg,
2931	ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))	2915	ADC_SMPR2_SMP0 << __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK))
2932	>> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)	2916	>> __ADC_MASK_SHIFT(Channel, ADC_CHANNEL_SMPx_BITOFFSET_MASK)
2933	);	2917	);
Line 3147...	Line 3131...
3147	* @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF	3131	* @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF
3148	* @retval None	3132	* @retval None
3149	*/	3133	*/
3150	__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)	3134	__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
3151	{	3135	{
3152	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);	3136	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3153		3137
3154	MODIFY_REG(*preg,	3138	MODIFY_REG(*preg,
3155	ADC_HTR_HT,	3139	ADC_HTR_HT,
3156	AWDThresholdValue);	3140	AWDThresholdValue);
3157	}	3141	}
Line 3170...	Line 3154...
3170	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW	3154	* @arg @ref LL_ADC_AWD_THRESHOLD_LOW
3171	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF	3155	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3172	*/	3156	*/
3173	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)	3157	__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow)
3174	{	3158	{
3175	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);	3159	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->HTR, AWDThresholdsHighLow);
3176		3160
3177	return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));	3161	return (uint32_t)(READ_BIT(*preg, ADC_HTR_HT));
3178	}	3162	}
3179		3163
3180	/**	3164	/**
Line 3377...	Line 3361...
3377	* @param ADCx ADC instance	3361	* @param ADCx ADC instance
3378	* @retval None	3362	* @retval None
3379	*/	3363	*/
3380	__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)	3364	__STATIC_INLINE void LL_ADC_REG_StopConversionExtTrig(ADC_TypeDef *ADCx)
3381	{	3365	{
3382	CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTSEL);	3366	CLEAR_BIT(ADCx->CR2, ADC_CR2_EXTTRIG);
3383	}	3367	}
3384		3368
3385	/**	3369	/**
3386	* @brief Get ADC group regular conversion data, range fit for	3370	* @brief Get ADC group regular conversion data, range fit for
3387	* all ADC configurations: all ADC resolutions and	3371	* all ADC configurations: all ADC resolutions and
Line 3503...	Line 3487...
3503	* @param ADCx ADC instance	3487	* @param ADCx ADC instance
3504	* @retval None	3488	* @retval None
3505	*/	3489	*/
3506	__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)	3490	__STATIC_INLINE void LL_ADC_INJ_StopConversionExtTrig(ADC_TypeDef *ADCx)
3507	{	3491	{
3508	CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTSEL);	3492	CLEAR_BIT(ADCx->CR2, ADC_CR2_JEXTTRIG);
3509	}	3493	}
3510		3494
3511	/**	3495	/**
3512	* @brief Get ADC group regular conversion data, range fit for	3496	* @brief Get ADC group regular conversion data, range fit for
3513	* all ADC configurations: all ADC resolutions and	3497	* all ADC configurations: all ADC resolutions and
Line 3525...	Line 3509...
3525	* @arg @ref LL_ADC_INJ_RANK_4	3509	* @arg @ref LL_ADC_INJ_RANK_4
3526	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF	3510	* @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
3527	*/	3511	*/
3528	__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)	3512	__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)
3529	{	3513	{
3530	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));	3514	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
3531		3515
3532	return (uint32_t)(READ_BIT(*preg,	3516	return (uint32_t)(READ_BIT(*preg,
3533	ADC_JDR1_JDATA)	3517	ADC_JDR1_JDATA)
3534	);	3518	);
3535	}	3519	}
Line 3552...	Line 3536...
3552	* @arg @ref LL_ADC_INJ_RANK_4	3536	* @arg @ref LL_ADC_INJ_RANK_4
3553	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF	3537	* @retval Value between Min_Data=0x000 and Max_Data=0xFFF
3554	*/	3538	*/
3555	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)	3539	__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)
3556	{	3540	{
3557	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));	3541	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, __ADC_MASK_SHIFT(Rank, ADC_INJ_JDRX_REGOFFSET_MASK));
3558		3542
3559	return (uint16_t)(READ_BIT(*preg,	3543	return (uint16_t)(READ_BIT(*preg,
3560	ADC_JDR1_JDATA)	3544	ADC_JDR1_JDATA)
3561	);	3545	);
3562	}	3546	}
Line 3682...	Line 3666...
3682	/* Note: on this STM32 serie, there is no flag ADC group regular */	3666	/* Note: on this STM32 serie, there is no flag ADC group regular */
3683	/* end of unitary conversion. */	3667	/* end of unitary conversion. */
3684	/* Flag noted as "EOC" is corresponding to flag "EOS" */	3668	/* Flag noted as "EOC" is corresponding to flag "EOS" */
3685	/* in other STM32 families). */	3669	/* in other STM32 families). */
3686		3670
3687	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);	3671	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
3688		3672
3689	return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));	3673	return (READ_BIT(*preg, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV));
3690	}	3674	}
3691		3675
3692		3676
Line 3718...	Line 3702...
3718	/* Note: on this STM32 serie, there is no flag ADC group injected */	3702	/* Note: on this STM32 serie, there is no flag ADC group injected */
3719	/* end of unitary conversion. */	3703	/* end of unitary conversion. */
3720	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */	3704	/* Flag noted as "JEOC" is corresponding to flag "JEOS" */
3721	/* in other STM32 families). */	3705	/* in other STM32 families). */
3722		3706
3723	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);	3707	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
3724		3708
3725	return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));	3709	return (READ_BIT(*preg, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV));
3726	}	3710	}
3727		3711
3728	/**	3712	/**
Line 3744...	Line 3728...
3744	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )	3728	* (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
3745	* @retval State of bit (1 or 0).	3729	* @retval State of bit (1 or 0).
3746	*/	3730	*/
3747	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)	3731	__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)
3748	{	3732	{
3749	register uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);	3733	register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCxy_COMMON->SR, 1U);
3750		3734
3751	return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));	3735	return (READ_BIT(*preg, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1));
3752	}	3736	}
3753		3737
3754	#endif /* ADC_MULTIMODE_SUPPORT */	3738	#endif /* ADC_MULTIMODE_SUPPORT */

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_adc.h – Rev 2 → 9