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/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32f1xx_hal_sram.h
 3 
  * @file    stm32f1xx_hal_sram.h
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   Header file of SRAM HAL module.
 5 
  * @brief   Header file of SRAM HAL module.
6 
  ******************************************************************************
 6 
  ******************************************************************************
7 
  * @attention
 7 
  * @attention
8 
  *
 8 
  *
9 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
 9 
  * Copyright (c) 2016 STMicroelectronics.
10 
  * All rights reserved.</center></h2>
 10 
  * All rights reserved.
11 
  *
 11 
  *
12 
  * This software component is licensed by ST under BSD 3-Clause license,
 12 
  * This software is licensed under terms that can be found in the LICENSE file
13 
  * the "License"; You may not use this file except in compliance with the
 13 
  * in the root directory of this software component.
14 
  * License. You may obtain a copy of the License at:
 14 
  * If no LICENSE file comes with this software, it is provided AS-IS.
15 
  *                       opensource.org/licenses/BSD-3-Clause
 15 
  *
16 
  *
 16 
  ******************************************************************************
17 
  ******************************************************************************
 17 
  */
18 
  */
 18 
 
19 
 
 19 
/* Define to prevent recursive inclusion -------------------------------------*/
20 
/* Define to prevent recursive inclusion -------------------------------------*/
 20 
#ifndef STM32F1xx_HAL_SRAM_H
21 
#ifndef STM32F1xx_HAL_SRAM_H
 21 
#define STM32F1xx_HAL_SRAM_H
22 
#define STM32F1xx_HAL_SRAM_H
 22 
 
23 
 
 23 
#ifdef __cplusplus
24 
#ifdef __cplusplus
 24 
extern "C" {
25 
extern "C" {
 25 
#endif
26 
#endif
 26 
 
27 
 
 27 
#if defined(FSMC_BANK1)
28 
#if defined(FSMC_BANK1)
 28 
 
29 
 
 29 
/* Includes ------------------------------------------------------------------*/
30 
/* Includes ------------------------------------------------------------------*/
 30 
#include "stm32f1xx_ll_fsmc.h"
31 
#include "stm32f1xx_ll_fsmc.h"
 31 
 
32 
 
 32 
/** @addtogroup STM32F1xx_HAL_Driver
33 
/** @addtogroup STM32F1xx_HAL_Driver
 33 
  * @{
34 
  * @{
 34 
  */
35 
  */
 35 
/** @addtogroup SRAM
36 
/** @addtogroup SRAM
 36 
  * @{
37 
  * @{
 37 
  */
38 
  */
 38 
 
39 
 
 39 
/* Exported typedef ----------------------------------------------------------*/
40 
/* Exported typedef ----------------------------------------------------------*/
 40 
 
41 
 
 41 
/** @defgroup SRAM_Exported_Types SRAM Exported Types
42 
/** @defgroup SRAM_Exported_Types SRAM Exported Types
 42 
  * @{
43 
  * @{
 43 
  */
44 
  */
 44 
/**
45 
/**
 45 
  * @brief  HAL SRAM State structures definition
46 
  * @brief  HAL SRAM State structures definition
 46 
  */
47 
  */
 47 
typedef enum
48 
typedef enum
 48 
{
49 
{
 49 
  HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
50 
  HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
 50 
  HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
51 
  HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
 51 
  HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
52 
  HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
 52 
  HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
53 
  HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
 53 
  HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
54 
  HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
 54 
 
55 
 
 55 
} HAL_SRAM_StateTypeDef;
56 
} HAL_SRAM_StateTypeDef;
 56 
 
57 
 
 57 
/**
58 
/**
 58 
  * @brief  SRAM handle Structure definition
59 
  * @brief  SRAM handle Structure definition
 59 
  */
60 
  */
 60 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
61 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 61 
typedef struct __SRAM_HandleTypeDef
62 
typedef struct __SRAM_HandleTypeDef
 62 
#else
63 
#else
 63 
typedef struct
64 
typedef struct
 64 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
65 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
 65 
{
66 
{
 66 
  FSMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
67 
  FSMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
 67 
 
68 
 
 68 
  FSMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
69 
  FSMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
 69 
 
70 
 
 70 
  FSMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
71 
  FSMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
 71 
 
72 
 
 72 
  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
73 
  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
 73 
 
74 
 
 74 
  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
75 
  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
 75 
 
76 
 
 76 
  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
77 
  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
 77 
 
78 
 
 78 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
79 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 79 
  void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram);               /*!< SRAM Msp Init callback              */
80 
  void (* MspInitCallback)(struct __SRAM_HandleTypeDef *hsram);               /*!< SRAM Msp Init callback              */
 80 
  void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram);             /*!< SRAM Msp DeInit callback            */
81 
  void (* MspDeInitCallback)(struct __SRAM_HandleTypeDef *hsram);             /*!< SRAM Msp DeInit callback            */
 81 
  void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma);                      /*!< SRAM DMA Xfer Complete callback     */
82 
  void (* DmaXferCpltCallback)(DMA_HandleTypeDef *hdma);                      /*!< SRAM DMA Xfer Complete callback     */
 82 
  void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma);                     /*!< SRAM DMA Xfer Error callback        */
83 
  void (* DmaXferErrorCallback)(DMA_HandleTypeDef *hdma);                     /*!< SRAM DMA Xfer Error callback        */
 83 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
84 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
 84 
} SRAM_HandleTypeDef;
85 
} SRAM_HandleTypeDef;
 85 
 
86 
 
 86 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
87 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 87 
/**
88 
/**
 88 
  * @brief  HAL SRAM Callback ID enumeration definition
89 
  * @brief  HAL SRAM Callback ID enumeration definition
 89 
  */
90 
  */
 90 
typedef enum
91 
typedef enum
 91 
{
92 
{
 92 
  HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */
93 
  HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */
 93 
  HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */
94 
  HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */
 94 
  HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */
95 
  HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */
 95 
  HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */
96 
  HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */
 96 
} HAL_SRAM_CallbackIDTypeDef;
97 
} HAL_SRAM_CallbackIDTypeDef;
 97 
 
98 
 
 98 
/**
99 
/**
 99 
  * @brief  HAL SRAM Callback pointer definition
100 
  * @brief  HAL SRAM Callback pointer definition
 100 
  */
101 
  */
 101 
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
102 
typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);
 102 
typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
103 
typedef void (*pSRAM_DmaCallbackTypeDef)(DMA_HandleTypeDef *hdma);
 103 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
104 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
 104 
/**
105 
/**
 105 
  * @}
106 
  * @}
 106 
  */
107 
  */
 107 
 
108 
 
 108 
/* Exported constants --------------------------------------------------------*/
109 
/* Exported constants --------------------------------------------------------*/
 109 
/* Exported macro ------------------------------------------------------------*/
110 
/* Exported macro ------------------------------------------------------------*/
 110 
 
111 
 
 111 
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
112 
/** @defgroup SRAM_Exported_Macros SRAM Exported Macros
 112 
  * @{
113 
  * @{
 113 
  */
114 
  */
 114 
 
115 
 
 115 
/** @brief Reset SRAM handle state
116 
/** @brief Reset SRAM handle state
 116 
  * @param  __HANDLE__ SRAM handle
117 
  * @param  __HANDLE__ SRAM handle
 117 
  * @retval None
118 
  * @retval None
 118 
  */
119 
  */
 119 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
120 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 120 
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
121 
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \
 121 
                                                               (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
122 
                                                               (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \
 122 
                                                               (__HANDLE__)->MspInitCallback = NULL;       \
123 
                                                               (__HANDLE__)->MspInitCallback = NULL;       \
 123 
                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
124 
                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \
 124 
                                                             } while(0)
125 
                                                             } while(0)
 125 
#else
126 
#else
 126 
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
127 
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
 127 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
128 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
 128 
 
129 
 
 129 
/**
130 
/**
 130 
  * @}
131 
  * @}
 131 
  */
132 
  */
 132 
 
133 
 
 133 
/* Exported functions --------------------------------------------------------*/
134 
/* Exported functions --------------------------------------------------------*/
 134 
/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
135 
/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
 135 
  * @{
136 
  * @{
 136 
  */
137 
  */
 137 
 
138 
 
 138 
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
139 
/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
 139 
  * @{
140 
  * @{
 140 
  */
141 
  */
 141 
 
142 
 
 142 
/* Initialization/de-initialization functions  ********************************/
143 
/* Initialization/de-initialization functions  ********************************/
 143 
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
144 
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing,
 144 
                                FSMC_NORSRAM_TimingTypeDef *ExtTiming);
145 
                                FSMC_NORSRAM_TimingTypeDef *ExtTiming);
 145 
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
146 
HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
 146 
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
147 
void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
 147 
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
148 
void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
 148 
 
149 
 
 149 
/**
150 
/**
 150 
  * @}
151 
  * @}
 151 
  */
152 
  */
 152 
 
153 
 
 153 
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
154 
/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
 154 
  * @{
155 
  * @{
 155 
  */
156 
  */
 156 
 
157 
 
 157 
/* I/O operation functions  ***************************************************/
158 
/* I/O operation functions  ***************************************************/
 158 
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
159 
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer,
 159 
                                   uint32_t BufferSize);
160 
                                   uint32_t BufferSize);
 160 
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
161 
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer,
 161 
                                    uint32_t BufferSize);
162 
                                    uint32_t BufferSize);
 162 
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
163 
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer,
 163 
                                    uint32_t BufferSize);
164 
                                    uint32_t BufferSize);
 164 
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
165 
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer,
 165 
                                     uint32_t BufferSize);
166 
                                     uint32_t BufferSize);
 166 
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
167 
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
 167 
                                    uint32_t BufferSize);
168 
                                    uint32_t BufferSize);
 168 
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
169 
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
 169 
                                     uint32_t BufferSize);
170 
                                     uint32_t BufferSize);
 170 
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
171 
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer,
 171 
                                    uint32_t BufferSize);
172 
                                    uint32_t BufferSize);
 172 
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
173 
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer,
 173 
                                     uint32_t BufferSize);
174 
                                     uint32_t BufferSize);
 174 
 
175 
 
 175 
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
176 
void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
 176 
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
177 
void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
 177 
 
178 
 
 178 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
179 
#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)
 179 
/* SRAM callback registering/unregistering */
180 
/* SRAM callback registering/unregistering */
 180 
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
181 
HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
 181 
                                            pSRAM_CallbackTypeDef pCallback);
182 
                                            pSRAM_CallbackTypeDef pCallback);
 182 
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
183 
HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);
 183 
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
184 
HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId,
 184 
                                               pSRAM_DmaCallbackTypeDef pCallback);
185 
                                               pSRAM_DmaCallbackTypeDef pCallback);
 185 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
186 
#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */
 186 
 
187 
 
 187 
/**
188 
/**
 188 
  * @}
189 
  * @}
 189 
  */
190 
  */
 190 
 
191 
 
 191 
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
192 
/** @addtogroup SRAM_Exported_Functions_Group3 Control functions
 192 
  * @{
193 
  * @{
 193 
  */
194 
  */
 194 
 
195 
 
 195 
/* SRAM Control functions  ****************************************************/
196 
/* SRAM Control functions  ****************************************************/
 196 
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
197 
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
 197 
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
198 
HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
 198 
 
199 
 
 199 
/**
200 
/**
 200 
  * @}
201 
  * @}
 201 
  */
202 
  */
 202 
 
203 
 
 203 
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
204 
/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
 204 
  * @{
205 
  * @{
 205 
  */
206 
  */
 206 
 
207 
 
 207 
/* SRAM  State functions ******************************************************/
208 
/* SRAM  State functions ******************************************************/
 208 
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram);
209 
HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
 209 
 
210 
 
 210 
/**
211 
/**
 211 
  * @}
212 
  * @}
 212 
  */
213 
  */
 213 
 
214 
 
 214 
/**
215 
/**
 215 
  * @}
216 
  * @}
 216 
  */
217 
  */
 217 
 
218 
 
 218 
/**
219 
/**
 219 
  * @}
220 
  * @}
 220 
  */
221 
  */
 221 
 
222 
 
 222 
/**
223 
/**
 223 
  * @}
224 
  * @}
 224 
  */
225 
  */
 225 
 
226 
 
 226 
#endif /* FSMC_BANK1 */
227 
#endif /* FSMC_BANK1 */
 227 
 
228 
 
 228 
#ifdef __cplusplus
229 
#ifdef __cplusplus
 229 
}
230 
}
 230 
#endif
231 
#endif
 231 
 
232 
 
 232 
#endif /* STM32F1xx_HAL_SRAM_H */
233 
#endif /* STM32F1xx_HAL_SRAM_H */
 - 
 
234 
 
 - 
 
235 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 -