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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_hal_smartcard.h |
3 | * @file stm32f1xx_hal_smartcard.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @version V1.0.1 |
5 | * @version V1.0.4 |
| 6 | * @date 31-July-2015 |
6 | * @date 29-April-2016 |
| 7 | * @brief Header file of SMARTCARD HAL module. |
7 | * @brief Header file of SMARTCARD HAL module. |
| 8 | ****************************************************************************** |
8 | ****************************************************************************** |
| 9 | * @attention |
9 | * @attention |
| 10 | * |
10 | * |
| 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
| 12 | * |
12 | * |
| 13 | * Redistribution and use in source and binary forms, with or without modification, |
13 | * Redistribution and use in source and binary forms, with or without modification, |
| 14 | * are permitted provided that the following conditions are met: |
14 | * are permitted provided that the following conditions are met: |
| 15 | * 1. Redistributions of source code must retain the above copyright notice, |
15 | * 1. Redistributions of source code must retain the above copyright notice, |
| 16 | * this list of conditions and the following disclaimer. |
16 | * this list of conditions and the following disclaimer. |
| Line 95... | Line 95... | ||
| 95 | uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted |
95 | uint32_t CLKLastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted |
| 96 | data bit (MSB) has to be output on the SCLK pin in synchronous mode. |
96 | data bit (MSB) has to be output on the SCLK pin in synchronous mode. |
| 97 | This parameter can be a value of @ref SMARTCARD_Last_Bit */ |
97 | This parameter can be a value of @ref SMARTCARD_Last_Bit */ |
| 98 | 98 | ||
| 99 | uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock |
99 | uint32_t Prescaler; /*!< Specifies the SmartCard Prescaler value used for dividing the system clock |
| 100 | to provide the smartcard clock |
100 | to provide the smartcard clock. The value given in the register (5 significant bits) |
| - | 101 | is multiplied by 2 to give the division factor of the source clock frequency. |
|
| 101 | This parameter can be a value of @ref SMARTCARD_Prescaler */ |
102 | This parameter can be a value of @ref SMARTCARD_Prescaler */ |
| 102 | 103 | ||
| 103 | uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks |
104 | uint32_t GuardTime; /*!< Specifies the SmartCard Guard Time value in terms of number of baud clocks */ |
| 104 | The value given in the register (5 significant bits) is multiplied by 2 |
- | |
| 105 | to give the division factor of the source clock frequency */ |
- | |
| 106 | 105 | ||
| 107 | uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state |
106 | uint32_t NACKState; /*!< Specifies the SmartCard NACK Transmission state |
| 108 | This parameter can be a value of @ref SMARTCARD_NACK_State */ |
107 | This parameter can be a value of @ref SMARTCARD_NACK_State */ |
| 109 | }SMARTCARD_InitTypeDef; |
108 | }SMARTCARD_InitTypeDef; |
| 110 | 109 | ||
| Line 547... | Line 546... | ||
| 547 | #define SMARTCARD_CR3_REG_INDEX 3 |
546 | #define SMARTCARD_CR3_REG_INDEX 3 |
| 548 | 547 | ||
| 549 | #define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) |
548 | #define SMARTCARD_DIV(__PCLK__, __BAUD__) (((__PCLK__)*25)/(4*(__BAUD__))) |
| 550 | #define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100) |
549 | #define SMARTCARD_DIVMANT(__PCLK__, __BAUD__) (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100) |
| 551 | #define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) |
550 | #define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__) (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100) |
| - | 551 | /* UART BRR = mantissa + overflow + fraction |
|
| - | 552 | = (UART DIVMANT << 4) + (UART DIVFRAQ & 0xF0) + (UART DIVFRAQ & 0x0F) */ |
|
| 552 | #define SMARTCARD_BRR(__PCLK__, __BAUD__) ((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F)) |
553 | #define SMARTCARD_BRR(_PCLK_, _BAUD_) (((SMARTCARD_DIVMANT((_PCLK_), (_BAUD_)) << 4) + \ |
| - | 554 | (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0xF0)) + \ |
|
| - | 555 | (SMARTCARD_DIVFRAQ((_PCLK_), (_BAUD_)) & 0x0F)) |
|
| 553 | 556 | ||
| 554 | /** Check the Baud rate range. |
557 | /** Check the Baud rate range. |
| 555 | * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz) |
558 | * The maximum Baud Rate is derived from the maximum clock on APB (i.e. 72 MHz) |
| 556 | * divided by the smallest oversampling used on the USART (i.e. 16) |
559 | * divided by the smallest oversampling used on the USART (i.e. 16) |
| 557 | * __BAUDRATE__: Baud rate set by the configuration function. |
560 | * __BAUDRATE__: Baud rate set by the configuration function. |