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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_hal_rcc.h |
3 | * @file stm32f1xx_hal_rcc.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of RCC HAL module. |
5 | * @brief Header file of RCC HAL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file in |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | ****************************************************************************** |
| 16 | * |
16 | */ |
| 17 | ****************************************************************************** |
17 | |
| 18 | */ |
18 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| 19 | 19 | #ifndef __STM32F1xx_HAL_RCC_H |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #define __STM32F1xx_HAL_RCC_H |
| 21 | #ifndef __STM32F1xx_HAL_RCC_H |
21 | |
| 22 | #define __STM32F1xx_HAL_RCC_H |
22 | #ifdef __cplusplus |
| 23 | 23 | extern "C" { |
|
| 24 | #ifdef __cplusplus |
24 | #endif |
| 25 | extern "C" { |
25 | |
| 26 | #endif |
26 | /* Includes ------------------------------------------------------------------*/ |
| 27 | 27 | #include "stm32f1xx_hal_def.h" |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | |
| 29 | #include "stm32f1xx_hal_def.h" |
29 | |
| 30 | 30 | /** @addtogroup STM32F1xx_HAL_Driver |
|
| 31 | 31 | * @{ |
|
| 32 | /** @addtogroup STM32F1xx_HAL_Driver |
32 | */ |
| 33 | * @{ |
33 | |
| 34 | */ |
34 | /** @addtogroup RCC |
| 35 | 35 | * @{ |
|
| 36 | /** @addtogroup RCC |
36 | */ |
| 37 | * @{ |
37 | |
| 38 | */ |
38 | /* Exported types ------------------------------------------------------------*/ |
| 39 | 39 | ||
| 40 | /* Exported types ------------------------------------------------------------*/ |
40 | /** @defgroup RCC_Exported_Types RCC Exported Types |
| 41 | 41 | * @{ |
|
| 42 | /** @defgroup RCC_Exported_Types RCC Exported Types |
42 | */ |
| 43 | * @{ |
43 | |
| 44 | */ |
44 | /** |
| 45 | 45 | * @brief RCC PLL configuration structure definition |
|
| 46 | /** |
46 | */ |
| 47 | * @brief RCC PLL configuration structure definition |
47 | typedef struct |
| 48 | */ |
48 | { |
| 49 | typedef struct |
49 | uint32_t PLLState; /*!< PLLState: The new state of the PLL. |
| 50 | { |
50 | This parameter can be a value of @ref RCC_PLL_Config */ |
| 51 | uint32_t PLLState; /*!< PLLState: The new state of the PLL. |
51 | |
| 52 | This parameter can be a value of @ref RCC_PLL_Config */ |
52 | uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. |
| 53 | 53 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
|
| 54 | uint32_t PLLSource; /*!< PLLSource: PLL entry clock source. |
54 | |
| 55 | This parameter must be a value of @ref RCC_PLL_Clock_Source */ |
55 | uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock |
| 56 | 56 | This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ |
|
| 57 | uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock |
57 | } RCC_PLLInitTypeDef; |
| 58 | This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */ |
58 | |
| 59 | } RCC_PLLInitTypeDef; |
59 | /** |
| 60 | 60 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
|
| 61 | /** |
61 | */ |
| 62 | * @brief RCC System, AHB and APB busses clock configuration structure definition |
62 | typedef struct |
| 63 | */ |
63 | { |
| 64 | typedef struct |
64 | uint32_t ClockType; /*!< The clock to be configured. |
| 65 | { |
65 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
| 66 | uint32_t ClockType; /*!< The clock to be configured. |
66 | |
| 67 | This parameter can be a value of @ref RCC_System_Clock_Type */ |
67 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
| 68 | 68 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
|
| 69 | uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock. |
69 | |
| 70 | This parameter can be a value of @ref RCC_System_Clock_Source */ |
70 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
| 71 | 71 | This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
|
| 72 | uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). |
72 | |
| 73 | This parameter can be a value of @ref RCC_AHB_Clock_Source */ |
73 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
| 74 | 74 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
|
| 75 | uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). |
75 | |
| 76 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
76 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). |
| 77 | 77 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
|
| 78 | uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). |
78 | } RCC_ClkInitTypeDef; |
| 79 | This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */ |
79 | |
| 80 | } RCC_ClkInitTypeDef; |
80 | /** |
| 81 | 81 | * @} |
|
| 82 | /** |
82 | */ |
| 83 | * @} |
83 | |
| 84 | */ |
84 | /* Exported constants --------------------------------------------------------*/ |
| 85 | 85 | /** @defgroup RCC_Exported_Constants RCC Exported Constants |
|
| 86 | /* Exported constants --------------------------------------------------------*/ |
86 | * @{ |
| 87 | /** @defgroup RCC_Exported_Constants RCC Exported Constants |
87 | */ |
| 88 | * @{ |
88 | |
| 89 | */ |
89 | /** @defgroup RCC_PLL_Clock_Source PLL Clock Source |
| 90 | 90 | * @{ |
|
| 91 | /** @defgroup RCC_PLL_Clock_Source PLL Clock Source |
91 | */ |
| 92 | * @{ |
92 | |
| 93 | */ |
93 | #define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
| 94 | 94 | #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ |
|
| 95 | #define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
95 | |
| 96 | #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */ |
96 | /** |
| 97 | 97 | * @} |
|
| 98 | /** |
98 | */ |
| 99 | * @} |
99 | |
| 100 | */ |
100 | /** @defgroup RCC_Oscillator_Type Oscillator Type |
| 101 | 101 | * @{ |
|
| 102 | /** @defgroup RCC_Oscillator_Type Oscillator Type |
102 | */ |
| 103 | * @{ |
103 | #define RCC_OSCILLATORTYPE_NONE 0x00000000U |
| 104 | */ |
104 | #define RCC_OSCILLATORTYPE_HSE 0x00000001U |
| 105 | #define RCC_OSCILLATORTYPE_NONE 0x00000000U |
105 | #define RCC_OSCILLATORTYPE_HSI 0x00000002U |
| 106 | #define RCC_OSCILLATORTYPE_HSE 0x00000001U |
106 | #define RCC_OSCILLATORTYPE_LSE 0x00000004U |
| 107 | #define RCC_OSCILLATORTYPE_HSI 0x00000002U |
107 | #define RCC_OSCILLATORTYPE_LSI 0x00000008U |
| 108 | #define RCC_OSCILLATORTYPE_LSE 0x00000004U |
108 | /** |
| 109 | #define RCC_OSCILLATORTYPE_LSI 0x00000008U |
109 | * @} |
| 110 | /** |
110 | */ |
| 111 | * @} |
111 | |
| 112 | */ |
112 | /** @defgroup RCC_HSE_Config HSE Config |
| 113 | 113 | * @{ |
|
| 114 | /** @defgroup RCC_HSE_Config HSE Config |
114 | */ |
| 115 | * @{ |
115 | #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ |
| 116 | */ |
116 | #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ |
| 117 | #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ |
117 | #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ |
| 118 | #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ |
118 | /** |
| 119 | #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */ |
119 | * @} |
| 120 | /** |
120 | */ |
| 121 | * @} |
121 | |
| 122 | */ |
122 | /** @defgroup RCC_LSE_Config LSE Config |
| 123 | 123 | * @{ |
|
| 124 | /** @defgroup RCC_LSE_Config LSE Config |
124 | */ |
| 125 | * @{ |
125 | #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ |
| 126 | */ |
126 | #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ |
| 127 | #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */ |
127 | #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ |
| 128 | #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */ |
128 | |
| 129 | #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */ |
129 | /** |
| 130 | 130 | * @} |
|
| 131 | /** |
131 | */ |
| 132 | * @} |
132 | |
| 133 | */ |
133 | /** @defgroup RCC_HSI_Config HSI Config |
| 134 | 134 | * @{ |
|
| 135 | /** @defgroup RCC_HSI_Config HSI Config |
135 | */ |
| 136 | * @{ |
136 | #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ |
| 137 | */ |
137 | #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ |
| 138 | #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ |
138 | |
| 139 | #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ |
139 | #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ |
| 140 | 140 | ||
| 141 | #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ |
141 | /** |
| 142 | 142 | * @} |
|
| 143 | /** |
143 | */ |
| 144 | * @} |
144 | |
| 145 | */ |
145 | /** @defgroup RCC_LSI_Config LSI Config |
| 146 | 146 | * @{ |
|
| 147 | /** @defgroup RCC_LSI_Config LSI Config |
147 | */ |
| 148 | * @{ |
148 | #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ |
| 149 | */ |
149 | #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ |
| 150 | #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ |
150 | |
| 151 | #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */ |
151 | /** |
| 152 | 152 | * @} |
|
| 153 | /** |
153 | */ |
| 154 | * @} |
154 | |
| 155 | */ |
155 | /** @defgroup RCC_PLL_Config PLL Config |
| 156 | 156 | * @{ |
|
| 157 | /** @defgroup RCC_PLL_Config PLL Config |
157 | */ |
| 158 | * @{ |
158 | #define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ |
| 159 | */ |
159 | #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ |
| 160 | #define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */ |
160 | #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ |
| 161 | #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */ |
161 | |
| 162 | #define RCC_PLL_ON 0x00000002U /*!< PLL activation */ |
162 | /** |
| 163 | 163 | * @} |
|
| 164 | /** |
164 | */ |
| 165 | * @} |
165 | |
| 166 | */ |
166 | /** @defgroup RCC_System_Clock_Type System Clock Type |
| 167 | 167 | * @{ |
|
| 168 | /** @defgroup RCC_System_Clock_Type System Clock Type |
168 | */ |
| 169 | * @{ |
169 | #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ |
| 170 | */ |
170 | #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ |
| 171 | #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ |
171 | #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ |
| 172 | #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ |
172 | #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ |
| 173 | #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ |
173 | |
| 174 | #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ |
174 | /** |
| 175 | 175 | * @} |
|
| 176 | /** |
176 | */ |
| 177 | * @} |
177 | |
| 178 | */ |
178 | /** @defgroup RCC_System_Clock_Source System Clock Source |
| 179 | 179 | * @{ |
|
| 180 | /** @defgroup RCC_System_Clock_Source System Clock Source |
180 | */ |
| 181 | * @{ |
181 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ |
| 182 | */ |
182 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ |
| 183 | #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */ |
183 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ |
| 184 | #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */ |
184 | |
| 185 | #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */ |
185 | /** |
| 186 | 186 | * @} |
|
| 187 | /** |
187 | */ |
| 188 | * @} |
188 | |
| 189 | */ |
189 | /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status |
| 190 | 190 | * @{ |
|
| 191 | /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status |
191 | */ |
| 192 | * @{ |
192 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
| 193 | */ |
193 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
| 194 | #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */ |
194 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
| 195 | #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */ |
195 | |
| 196 | #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */ |
196 | /** |
| 197 | 197 | * @} |
|
| 198 | /** |
198 | */ |
| 199 | * @} |
199 | |
| 200 | */ |
200 | /** @defgroup RCC_AHB_Clock_Source AHB Clock Source |
| 201 | 201 | * @{ |
|
| 202 | /** @defgroup RCC_AHB_Clock_Source AHB Clock Source |
202 | */ |
| 203 | * @{ |
203 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ |
| 204 | */ |
204 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ |
| 205 | #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */ |
205 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ |
| 206 | #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */ |
206 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ |
| 207 | #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */ |
207 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ |
| 208 | #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */ |
208 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ |
| 209 | #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */ |
209 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ |
| 210 | #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */ |
210 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ |
| 211 | #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */ |
211 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ |
| 212 | #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */ |
212 | |
| 213 | #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */ |
213 | /** |
| 214 | 214 | * @} |
|
| 215 | /** |
215 | */ |
| 216 | * @} |
216 | |
| 217 | */ |
217 | /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source |
| 218 | 218 | * @{ |
|
| 219 | /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source |
219 | */ |
| 220 | * @{ |
220 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ |
| 221 | */ |
221 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ |
| 222 | #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */ |
222 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ |
| 223 | #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */ |
223 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ |
| 224 | #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */ |
224 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ |
| 225 | #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */ |
225 | |
| 226 | #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */ |
226 | /** |
| 227 | 227 | * @} |
|
| 228 | /** |
228 | */ |
| 229 | * @} |
229 | |
| 230 | */ |
230 | /** @defgroup RCC_RTC_Clock_Source RTC Clock Source |
| 231 | 231 | * @{ |
|
| 232 | /** @defgroup RCC_RTC_Clock_Source RTC Clock Source |
232 | */ |
| 233 | * @{ |
233 | #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ |
| 234 | */ |
234 | #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ |
| 235 | #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */ |
235 | #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ |
| 236 | #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */ |
236 | #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
| 237 | #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */ |
237 | /** |
| 238 | #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
238 | * @} |
| 239 | /** |
239 | */ |
| 240 | * @} |
240 | |
| 241 | */ |
241 | |
| 242 | 242 | /** @defgroup RCC_MCO_Index MCO Index |
|
| 243 | 243 | * @{ |
|
| 244 | /** @defgroup RCC_MCO_Index MCO Index |
244 | */ |
| 245 | * @{ |
245 | #define RCC_MCO1 0x00000000U |
| 246 | */ |
246 | #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ |
| 247 | #define RCC_MCO1 0x00000000U |
247 | |
| 248 | #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ |
248 | /** |
| 249 | 249 | * @} |
|
| 250 | /** |
250 | */ |
| 251 | * @} |
251 | |
| 252 | */ |
252 | /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler |
| 253 | 253 | * @{ |
|
| 254 | /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler |
254 | */ |
| 255 | * @{ |
255 | #define RCC_MCODIV_1 0x00000000U |
| 256 | */ |
256 | |
| 257 | #define RCC_MCODIV_1 0x00000000U |
257 | /** |
| 258 | 258 | * @} |
|
| 259 | /** |
259 | */ |
| 260 | * @} |
260 | |
| 261 | */ |
261 | /** @defgroup RCC_Interrupt Interrupts |
| 262 | 262 | * @{ |
|
| 263 | /** @defgroup RCC_Interrupt Interrupts |
263 | */ |
| 264 | * @{ |
264 | #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ |
| 265 | */ |
265 | #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ |
| 266 | #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */ |
266 | #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ |
| 267 | #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */ |
267 | #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ |
| 268 | #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */ |
268 | #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ |
| 269 | #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */ |
269 | #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ |
| 270 | #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */ |
270 | /** |
| 271 | #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */ |
271 | * @} |
| 272 | /** |
272 | */ |
| 273 | * @} |
273 | |
| 274 | */ |
274 | /** @defgroup RCC_Flag Flags |
| 275 | 275 | * Elements values convention: XXXYYYYYb |
|
| 276 | /** @defgroup RCC_Flag Flags |
276 | * - YYYYY : Flag position in the register |
| 277 | * Elements values convention: XXXYYYYYb |
277 | * - XXX : Register index |
| 278 | * - YYYYY : Flag position in the register |
278 | * - 001: CR register |
| 279 | * - XXX : Register index |
279 | * - 010: BDCR register |
| 280 | * - 001: CR register |
280 | * - 011: CSR register |
| 281 | * - 010: BDCR register |
281 | * @{ |
| 282 | * - 011: CSR register |
282 | */ |
| 283 | * @{ |
283 | /* Flags in the CR register */ |
| 284 | */ |
284 | #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ |
| 285 | /* Flags in the CR register */ |
285 | #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ |
| 286 | #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */ |
286 | #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ |
| 287 | #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */ |
287 | |
| 288 | #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */ |
288 | /* Flags in the CSR register */ |
| 289 | 289 | #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ |
|
| 290 | /* Flags in the CSR register */ |
290 | #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ |
| 291 | #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */ |
291 | #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ |
| 292 | #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ |
292 | #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ |
| 293 | #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */ |
293 | #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ |
| 294 | #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ |
294 | #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ |
| 295 | #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ |
295 | #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ |
| 296 | #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ |
296 | |
| 297 | #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ |
297 | /* Flags in the BDCR register */ |
| 298 | 298 | #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ |
|
| 299 | /* Flags in the BDCR register */ |
299 | |
| 300 | #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */ |
300 | /** |
| 301 | 301 | * @} |
|
| 302 | /** |
302 | */ |
| 303 | * @} |
303 | |
| 304 | */ |
304 | /** |
| 305 | 305 | * @} |
|
| 306 | /** |
306 | */ |
| 307 | * @} |
307 | |
| 308 | */ |
308 | /* Exported macro ------------------------------------------------------------*/ |
| 309 | 309 | ||
| 310 | /* Exported macro ------------------------------------------------------------*/ |
310 | /** @defgroup RCC_Exported_Macros RCC Exported Macros |
| 311 | 311 | * @{ |
|
| 312 | /** @defgroup RCC_Exported_Macros RCC Exported Macros |
312 | */ |
| 313 | * @{ |
313 | |
| 314 | */ |
314 | /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable |
| 315 | 315 | * @brief Enable or disable the AHB1 peripheral clock. |
|
| 316 | /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable |
316 | * @note After reset, the peripheral clock (used for registers read/write access) |
| 317 | * @brief Enable or disable the AHB1 peripheral clock. |
317 | * is disabled and the application software has to enable this clock before |
| 318 | * @note After reset, the peripheral clock (used for registers read/write access) |
318 | * using it. |
| 319 | * is disabled and the application software has to enable this clock before |
319 | * @{ |
| 320 | * using it. |
320 | */ |
| 321 | * @{ |
321 | #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ |
| 322 | */ |
322 | __IO uint32_t tmpreg; \ |
| 323 | #define __HAL_RCC_DMA1_CLK_ENABLE() do { \ |
323 | SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ |
| 324 | __IO uint32_t tmpreg; \ |
324 | /* Delay after an RCC peripheral clock enabling */\ |
| 325 | SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ |
325 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ |
| 326 | /* Delay after an RCC peripheral clock enabling */\ |
326 | UNUSED(tmpreg); \ |
| 327 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\ |
327 | } while(0U) |
| 328 | UNUSED(tmpreg); \ |
328 | |
| 329 | } while(0U) |
329 | #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ |
| 330 | 330 | __IO uint32_t tmpreg; \ |
|
| 331 | #define __HAL_RCC_SRAM_CLK_ENABLE() do { \ |
331 | SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ |
| 332 | __IO uint32_t tmpreg; \ |
332 | /* Delay after an RCC peripheral clock enabling */\ |
| 333 | SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ |
333 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ |
| 334 | /* Delay after an RCC peripheral clock enabling */\ |
334 | UNUSED(tmpreg); \ |
| 335 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\ |
335 | } while(0U) |
| 336 | UNUSED(tmpreg); \ |
336 | |
| 337 | } while(0U) |
337 | #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ |
| 338 | 338 | __IO uint32_t tmpreg; \ |
|
| 339 | #define __HAL_RCC_FLITF_CLK_ENABLE() do { \ |
339 | SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ |
| 340 | __IO uint32_t tmpreg; \ |
340 | /* Delay after an RCC peripheral clock enabling */\ |
| 341 | SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ |
341 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ |
| 342 | /* Delay after an RCC peripheral clock enabling */\ |
342 | UNUSED(tmpreg); \ |
| 343 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\ |
343 | } while(0U) |
| 344 | UNUSED(tmpreg); \ |
344 | |
| 345 | } while(0U) |
345 | #define __HAL_RCC_CRC_CLK_ENABLE() do { \ |
| 346 | 346 | __IO uint32_t tmpreg; \ |
|
| 347 | #define __HAL_RCC_CRC_CLK_ENABLE() do { \ |
347 | SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ |
| 348 | __IO uint32_t tmpreg; \ |
348 | /* Delay after an RCC peripheral clock enabling */\ |
| 349 | SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ |
349 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ |
| 350 | /* Delay after an RCC peripheral clock enabling */\ |
350 | UNUSED(tmpreg); \ |
| 351 | tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\ |
351 | } while(0U) |
| 352 | UNUSED(tmpreg); \ |
352 | |
| 353 | } while(0U) |
353 | #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) |
| 354 | 354 | #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) |
|
| 355 | #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN)) |
355 | #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) |
| 356 | #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN)) |
356 | #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) |
| 357 | #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN)) |
357 | |
| 358 | #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN)) |
358 | /** |
| 359 | 359 | * @} |
|
| 360 | /** |
360 | */ |
| 361 | * @} |
361 | |
| 362 | */ |
362 | /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status |
| 363 | 363 | * @brief Get the enable or disable status of the AHB peripheral clock. |
|
| 364 | /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status |
364 | * @note After reset, the peripheral clock (used for registers read/write access) |
| 365 | * @brief Get the enable or disable status of the AHB peripheral clock. |
365 | * is disabled and the application software has to enable this clock before |
| 366 | * @note After reset, the peripheral clock (used for registers read/write access) |
366 | * using it. |
| 367 | * is disabled and the application software has to enable this clock before |
367 | * @{ |
| 368 | * using it. |
368 | */ |
| 369 | * @{ |
369 | |
| 370 | */ |
370 | #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) |
| 371 | 371 | #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) |
|
| 372 | #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET) |
372 | #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) |
| 373 | #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET) |
373 | #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) |
| 374 | #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET) |
374 | #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) |
| 375 | #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET) |
375 | #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) |
| 376 | #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET) |
376 | #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) |
| 377 | #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET) |
377 | #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) |
| 378 | #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET) |
378 | |
| 379 | #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET) |
379 | /** |
| 380 | 380 | * @} |
|
| 381 | /** |
381 | */ |
| 382 | * @} |
382 | |
| 383 | */ |
383 | /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable |
| 384 | 384 | * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
|
| 385 | /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable |
385 | * @note After reset, the peripheral clock (used for registers read/write access) |
| 386 | * @brief Enable or disable the Low Speed APB (APB1) peripheral clock. |
386 | * is disabled and the application software has to enable this clock before |
| 387 | * @note After reset, the peripheral clock (used for registers read/write access) |
387 | * using it. |
| 388 | * is disabled and the application software has to enable this clock before |
388 | * @{ |
| 389 | * using it. |
389 | */ |
| 390 | * @{ |
390 | #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
| 391 | */ |
391 | __IO uint32_t tmpreg; \ |
| 392 | #define __HAL_RCC_TIM2_CLK_ENABLE() do { \ |
392 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
| 393 | __IO uint32_t tmpreg; \ |
393 | /* Delay after an RCC peripheral clock enabling */\ |
| 394 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
394 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
| 395 | /* Delay after an RCC peripheral clock enabling */\ |
395 | UNUSED(tmpreg); \ |
| 396 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\ |
396 | } while(0U) |
| 397 | UNUSED(tmpreg); \ |
397 | |
| 398 | } while(0U) |
398 | #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ |
| 399 | 399 | __IO uint32_t tmpreg; \ |
|
| 400 | #define __HAL_RCC_TIM3_CLK_ENABLE() do { \ |
400 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
| 401 | __IO uint32_t tmpreg; \ |
401 | /* Delay after an RCC peripheral clock enabling */\ |
| 402 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
402 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
| 403 | /* Delay after an RCC peripheral clock enabling */\ |
403 | UNUSED(tmpreg); \ |
| 404 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\ |
404 | } while(0U) |
| 405 | UNUSED(tmpreg); \ |
405 | |
| 406 | } while(0U) |
406 | #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ |
| 407 | 407 | __IO uint32_t tmpreg; \ |
|
| 408 | #define __HAL_RCC_WWDG_CLK_ENABLE() do { \ |
408 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
| 409 | __IO uint32_t tmpreg; \ |
409 | /* Delay after an RCC peripheral clock enabling */\ |
| 410 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
410 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
| 411 | /* Delay after an RCC peripheral clock enabling */\ |
411 | UNUSED(tmpreg); \ |
| 412 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\ |
412 | } while(0U) |
| 413 | UNUSED(tmpreg); \ |
413 | |
| 414 | } while(0U) |
414 | #define __HAL_RCC_USART2_CLK_ENABLE() do { \ |
| 415 | 415 | __IO uint32_t tmpreg; \ |
|
| 416 | #define __HAL_RCC_USART2_CLK_ENABLE() do { \ |
416 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
| 417 | __IO uint32_t tmpreg; \ |
417 | /* Delay after an RCC peripheral clock enabling */\ |
| 418 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
418 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
| 419 | /* Delay after an RCC peripheral clock enabling */\ |
419 | UNUSED(tmpreg); \ |
| 420 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\ |
420 | } while(0U) |
| 421 | UNUSED(tmpreg); \ |
421 | |
| 422 | } while(0U) |
422 | #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ |
| 423 | 423 | __IO uint32_t tmpreg; \ |
|
| 424 | #define __HAL_RCC_I2C1_CLK_ENABLE() do { \ |
424 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
| 425 | __IO uint32_t tmpreg; \ |
425 | /* Delay after an RCC peripheral clock enabling */\ |
| 426 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
426 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
| 427 | /* Delay after an RCC peripheral clock enabling */\ |
427 | UNUSED(tmpreg); \ |
| 428 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\ |
428 | } while(0U) |
| 429 | UNUSED(tmpreg); \ |
429 | |
| 430 | } while(0U) |
430 | #define __HAL_RCC_BKP_CLK_ENABLE() do { \ |
| 431 | 431 | __IO uint32_t tmpreg; \ |
|
| 432 | #define __HAL_RCC_BKP_CLK_ENABLE() do { \ |
432 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ |
| 433 | __IO uint32_t tmpreg; \ |
433 | /* Delay after an RCC peripheral clock enabling */\ |
| 434 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ |
434 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ |
| 435 | /* Delay after an RCC peripheral clock enabling */\ |
435 | UNUSED(tmpreg); \ |
| 436 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\ |
436 | } while(0U) |
| 437 | UNUSED(tmpreg); \ |
437 | |
| 438 | } while(0U) |
438 | #define __HAL_RCC_PWR_CLK_ENABLE() do { \ |
| 439 | 439 | __IO uint32_t tmpreg; \ |
|
| 440 | #define __HAL_RCC_PWR_CLK_ENABLE() do { \ |
440 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
| 441 | __IO uint32_t tmpreg; \ |
441 | /* Delay after an RCC peripheral clock enabling */\ |
| 442 | SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
442 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
| 443 | /* Delay after an RCC peripheral clock enabling */\ |
443 | UNUSED(tmpreg); \ |
| 444 | tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\ |
444 | } while(0U) |
| 445 | UNUSED(tmpreg); \ |
445 | |
| 446 | } while(0U) |
446 | #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
| 447 | 447 | #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
|
| 448 | #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN)) |
448 | #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
| 449 | #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN)) |
449 | #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
| 450 | #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN)) |
450 | #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
| 451 | #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN)) |
451 | |
| 452 | #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN)) |
452 | #define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) |
| 453 | 453 | #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
|
| 454 | #define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN)) |
454 | |
| 455 | #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN)) |
455 | /** |
| 456 | 456 | * @} |
|
| 457 | /** |
457 | */ |
| 458 | * @} |
458 | |
| 459 | */ |
459 | /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status |
| 460 | 460 | * @brief Get the enable or disable status of the APB1 peripheral clock. |
|
| 461 | /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status |
461 | * @note After reset, the peripheral clock (used for registers read/write access) |
| 462 | * @brief Get the enable or disable status of the APB1 peripheral clock. |
462 | * is disabled and the application software has to enable this clock before |
| 463 | * @note After reset, the peripheral clock (used for registers read/write access) |
463 | * using it. |
| 464 | * is disabled and the application software has to enable this clock before |
464 | * @{ |
| 465 | * using it. |
465 | */ |
| 466 | * @{ |
466 | |
| 467 | */ |
467 | #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) |
| 468 | 468 | #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) |
|
| 469 | #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET) |
469 | #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) |
| 470 | #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET) |
470 | #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) |
| 471 | #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET) |
471 | #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) |
| 472 | #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET) |
472 | #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) |
| 473 | #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET) |
473 | #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) |
| 474 | #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET) |
474 | #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) |
| 475 | #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET) |
475 | #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) |
| 476 | #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET) |
476 | #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) |
| 477 | #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET) |
477 | #define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) |
| 478 | #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET) |
478 | #define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) |
| 479 | #define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET) |
479 | #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) |
| 480 | #define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET) |
480 | #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) |
| 481 | #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET) |
481 | |
| 482 | #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET) |
482 | /** |
| 483 | 483 | * @} |
|
| 484 | /** |
484 | */ |
| 485 | * @} |
485 | |
| 486 | */ |
486 | /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable |
| 487 | 487 | * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
|
| 488 | /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable |
488 | * @note After reset, the peripheral clock (used for registers read/write access) |
| 489 | * @brief Enable or disable the High Speed APB (APB2) peripheral clock. |
489 | * is disabled and the application software has to enable this clock before |
| 490 | * @note After reset, the peripheral clock (used for registers read/write access) |
490 | * using it. |
| 491 | * is disabled and the application software has to enable this clock before |
491 | * @{ |
| 492 | * using it. |
492 | */ |
| 493 | * @{ |
493 | #define __HAL_RCC_AFIO_CLK_ENABLE() do { \ |
| 494 | */ |
494 | __IO uint32_t tmpreg; \ |
| 495 | #define __HAL_RCC_AFIO_CLK_ENABLE() do { \ |
495 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ |
| 496 | __IO uint32_t tmpreg; \ |
496 | /* Delay after an RCC peripheral clock enabling */\ |
| 497 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ |
497 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ |
| 498 | /* Delay after an RCC peripheral clock enabling */\ |
498 | UNUSED(tmpreg); \ |
| 499 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\ |
499 | } while(0U) |
| 500 | UNUSED(tmpreg); \ |
500 | |
| 501 | } while(0U) |
501 | #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ |
| 502 | 502 | __IO uint32_t tmpreg; \ |
|
| 503 | #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ |
503 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ |
| 504 | __IO uint32_t tmpreg; \ |
504 | /* Delay after an RCC peripheral clock enabling */\ |
| 505 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ |
505 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ |
| 506 | /* Delay after an RCC peripheral clock enabling */\ |
506 | UNUSED(tmpreg); \ |
| 507 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\ |
507 | } while(0U) |
| 508 | UNUSED(tmpreg); \ |
508 | |
| 509 | } while(0U) |
509 | #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ |
| 510 | 510 | __IO uint32_t tmpreg; \ |
|
| 511 | #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ |
511 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ |
| 512 | __IO uint32_t tmpreg; \ |
512 | /* Delay after an RCC peripheral clock enabling */\ |
| 513 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ |
513 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ |
| 514 | /* Delay after an RCC peripheral clock enabling */\ |
514 | UNUSED(tmpreg); \ |
| 515 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\ |
515 | } while(0U) |
| 516 | UNUSED(tmpreg); \ |
516 | |
| 517 | } while(0U) |
517 | #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ |
| 518 | 518 | __IO uint32_t tmpreg; \ |
|
| 519 | #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ |
519 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ |
| 520 | __IO uint32_t tmpreg; \ |
520 | /* Delay after an RCC peripheral clock enabling */\ |
| 521 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ |
521 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ |
| 522 | /* Delay after an RCC peripheral clock enabling */\ |
522 | UNUSED(tmpreg); \ |
| 523 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\ |
523 | } while(0U) |
| 524 | UNUSED(tmpreg); \ |
524 | |
| 525 | } while(0U) |
525 | #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
| 526 | 526 | __IO uint32_t tmpreg; \ |
|
| 527 | #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ |
527 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ |
| 528 | __IO uint32_t tmpreg; \ |
528 | /* Delay after an RCC peripheral clock enabling */\ |
| 529 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ |
529 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ |
| 530 | /* Delay after an RCC peripheral clock enabling */\ |
530 | UNUSED(tmpreg); \ |
| 531 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\ |
531 | } while(0U) |
| 532 | UNUSED(tmpreg); \ |
532 | |
| 533 | } while(0U) |
533 | #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ |
| 534 | 534 | __IO uint32_t tmpreg; \ |
|
| 535 | #define __HAL_RCC_ADC1_CLK_ENABLE() do { \ |
535 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
| 536 | __IO uint32_t tmpreg; \ |
536 | /* Delay after an RCC peripheral clock enabling */\ |
| 537 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
537 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
| 538 | /* Delay after an RCC peripheral clock enabling */\ |
538 | UNUSED(tmpreg); \ |
| 539 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\ |
539 | } while(0U) |
| 540 | UNUSED(tmpreg); \ |
540 | |
| 541 | } while(0U) |
541 | #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ |
| 542 | 542 | __IO uint32_t tmpreg; \ |
|
| 543 | #define __HAL_RCC_TIM1_CLK_ENABLE() do { \ |
543 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
| 544 | __IO uint32_t tmpreg; \ |
544 | /* Delay after an RCC peripheral clock enabling */\ |
| 545 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
545 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
| 546 | /* Delay after an RCC peripheral clock enabling */\ |
546 | UNUSED(tmpreg); \ |
| 547 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\ |
547 | } while(0U) |
| 548 | UNUSED(tmpreg); \ |
548 | |
| 549 | } while(0U) |
549 | #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ |
| 550 | 550 | __IO uint32_t tmpreg; \ |
|
| 551 | #define __HAL_RCC_SPI1_CLK_ENABLE() do { \ |
551 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
| 552 | __IO uint32_t tmpreg; \ |
552 | /* Delay after an RCC peripheral clock enabling */\ |
| 553 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
553 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
| 554 | /* Delay after an RCC peripheral clock enabling */\ |
554 | UNUSED(tmpreg); \ |
| 555 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\ |
555 | } while(0U) |
| 556 | UNUSED(tmpreg); \ |
556 | |
| 557 | } while(0U) |
557 | #define __HAL_RCC_USART1_CLK_ENABLE() do { \ |
| 558 | 558 | __IO uint32_t tmpreg; \ |
|
| 559 | #define __HAL_RCC_USART1_CLK_ENABLE() do { \ |
559 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
| 560 | __IO uint32_t tmpreg; \ |
560 | /* Delay after an RCC peripheral clock enabling */\ |
| 561 | SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
561 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
| 562 | /* Delay after an RCC peripheral clock enabling */\ |
562 | UNUSED(tmpreg); \ |
| 563 | tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\ |
563 | } while(0U) |
| 564 | UNUSED(tmpreg); \ |
564 | |
| 565 | } while(0U) |
565 | #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) |
| 566 | 566 | #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) |
|
| 567 | #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN)) |
567 | #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) |
| 568 | #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN)) |
568 | #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) |
| 569 | #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN)) |
569 | #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) |
| 570 | #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN)) |
570 | #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) |
| 571 | #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN)) |
571 | |
| 572 | #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN)) |
572 | #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) |
| 573 | 573 | #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
|
| 574 | #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN)) |
574 | #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
| 575 | #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN)) |
575 | |
| 576 | #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN)) |
576 | /** |
| 577 | 577 | * @} |
|
| 578 | /** |
578 | */ |
| 579 | * @} |
579 | |
| 580 | */ |
580 | /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status |
| 581 | 581 | * @brief Get the enable or disable status of the APB2 peripheral clock. |
|
| 582 | /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status |
582 | * @note After reset, the peripheral clock (used for registers read/write access) |
| 583 | * @brief Get the enable or disable status of the APB2 peripheral clock. |
583 | * is disabled and the application software has to enable this clock before |
| 584 | * @note After reset, the peripheral clock (used for registers read/write access) |
584 | * using it. |
| 585 | * is disabled and the application software has to enable this clock before |
585 | * @{ |
| 586 | * using it. |
586 | */ |
| 587 | * @{ |
587 | |
| 588 | */ |
588 | #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) |
| 589 | 589 | #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) |
|
| 590 | #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET) |
590 | #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) |
| 591 | #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET) |
591 | #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) |
| 592 | #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET) |
592 | #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) |
| 593 | #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET) |
593 | #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) |
| 594 | #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET) |
594 | #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) |
| 595 | #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET) |
595 | #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) |
| 596 | #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET) |
596 | #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) |
| 597 | #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET) |
597 | #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) |
| 598 | #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET) |
598 | #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) |
| 599 | #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET) |
599 | #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) |
| 600 | #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET) |
600 | #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) |
| 601 | #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET) |
601 | #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) |
| 602 | #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET) |
602 | #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) |
| 603 | #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET) |
603 | #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) |
| 604 | #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET) |
604 | #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) |
| 605 | #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET) |
605 | #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) |
| 606 | #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET) |
606 | |
| 607 | #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET) |
607 | /** |
| 608 | 608 | * @} |
|
| 609 | /** |
609 | */ |
| 610 | * @} |
610 | |
| 611 | */ |
611 | /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset |
| 612 | 612 | * @brief Force or release APB1 peripheral reset. |
|
| 613 | /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset |
613 | * @{ |
| 614 | * @brief Force or release APB1 peripheral reset. |
614 | */ |
| 615 | * @{ |
615 | #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU) |
| 616 | */ |
616 | #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
| 617 | #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) |
617 | #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
| 618 | #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST)) |
618 | #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
| 619 | #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST)) |
619 | #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
| 620 | #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST)) |
620 | #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
| 621 | #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST)) |
621 | |
| 622 | #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST)) |
622 | #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) |
| 623 | 623 | #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
|
| 624 | #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST)) |
624 | |
| 625 | #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST)) |
625 | #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) |
| 626 | 626 | #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
|
| 627 | #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00) |
627 | #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
| 628 | #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST)) |
628 | #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
| 629 | #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST)) |
629 | #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
| 630 | #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST)) |
630 | #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
| 631 | #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST)) |
631 | |
| 632 | #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST)) |
632 | #define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) |
| 633 | 633 | #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
|
| 634 | #define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST)) |
634 | |
| 635 | #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST)) |
635 | /** |
| 636 | 636 | * @} |
|
| 637 | /** |
637 | */ |
| 638 | * @} |
638 | |
| 639 | */ |
639 | /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset |
| 640 | 640 | * @brief Force or release APB2 peripheral reset. |
|
| 641 | /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset |
641 | * @{ |
| 642 | * @brief Force or release APB2 peripheral reset. |
642 | */ |
| 643 | * @{ |
643 | #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) |
| 644 | */ |
644 | #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) |
| 645 | #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU) |
645 | #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) |
| 646 | #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST)) |
646 | #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) |
| 647 | #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST)) |
647 | #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) |
| 648 | #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST)) |
648 | #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) |
| 649 | #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST)) |
649 | #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) |
| 650 | #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST)) |
650 | |
| 651 | #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST)) |
651 | #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) |
| 652 | 652 | #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
|
| 653 | #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST)) |
653 | #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
| 654 | #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST)) |
654 | |
| 655 | #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST)) |
655 | #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) |
| 656 | 656 | #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) |
|
| 657 | #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00) |
657 | #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) |
| 658 | #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST)) |
658 | #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) |
| 659 | #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST)) |
659 | #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) |
| 660 | #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST)) |
660 | #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) |
| 661 | #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST)) |
661 | #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) |
| 662 | #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST)) |
662 | |
| 663 | #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST)) |
663 | #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) |
| 664 | 664 | #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) |
|
| 665 | #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST)) |
665 | #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
| 666 | #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST)) |
666 | |
| 667 | #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST)) |
667 | /** |
| 668 | 668 | * @} |
|
| 669 | /** |
669 | */ |
| 670 | * @} |
670 | |
| 671 | */ |
671 | /** @defgroup RCC_HSI_Configuration HSI Configuration |
| 672 | 672 | * @{ |
|
| 673 | /** @defgroup RCC_HSI_Configuration HSI Configuration |
673 | */ |
| 674 | * @{ |
674 | |
| 675 | */ |
675 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
| 676 | 676 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
|
| 677 | /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI). |
677 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
| 678 | * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. |
678 | * you have to select another source of the system clock then stop the HSI. |
| 679 | * @note HSI can not be stopped if it is used as system clock source. In this case, |
679 | * @note After enabling the HSI, the application software should wait on HSIRDY |
| 680 | * you have to select another source of the system clock then stop the HSI. |
680 | * flag to be set indicating that HSI clock is stable and can be used as |
| 681 | * @note After enabling the HSI, the application software should wait on HSIRDY |
681 | * system clock source. |
| 682 | * flag to be set indicating that HSI clock is stable and can be used as |
682 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
| 683 | * system clock source. |
683 | * clock cycles. |
| 684 | * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator |
684 | */ |
| 685 | * clock cycles. |
685 | #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) |
| 686 | */ |
686 | #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) |
| 687 | #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE) |
687 | |
| 688 | #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE) |
688 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
| 689 | 689 | * @note The calibration is used to compensate for the variations in voltage |
|
| 690 | /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value. |
690 | * and temperature that influence the frequency of the internal HSI RC. |
| 691 | * @note The calibration is used to compensate for the variations in voltage |
691 | * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. |
| 692 | * and temperature that influence the frequency of the internal HSI RC. |
692 | * (default is RCC_HSICALIBRATION_DEFAULT). |
| 693 | * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value. |
693 | * This parameter must be a number between 0 and 0x1F. |
| 694 | * (default is RCC_HSICALIBRATION_DEFAULT). |
694 | */ |
| 695 | * This parameter must be a number between 0 and 0x1F. |
695 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ |
| 696 | */ |
696 | (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) |
| 697 | #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \ |
697 | |
| 698 | (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos)) |
698 | /** |
| 699 | 699 | * @} |
|
| 700 | /** |
700 | */ |
| 701 | * @} |
701 | |
| 702 | */ |
702 | /** @defgroup RCC_LSI_Configuration LSI Configuration |
| 703 | 703 | * @{ |
|
| 704 | /** @defgroup RCC_LSI_Configuration LSI Configuration |
704 | */ |
| 705 | * @{ |
705 | |
| 706 | */ |
706 | /** @brief Macro to enable the Internal Low Speed oscillator (LSI). |
| 707 | 707 | * @note After enabling the LSI, the application software should wait on |
|
| 708 | /** @brief Macro to enable the Internal Low Speed oscillator (LSI). |
708 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
| 709 | * @note After enabling the LSI, the application software should wait on |
709 | * be used to clock the IWDG and/or the RTC. |
| 710 | * LSIRDY flag to be set indicating that LSI clock is stable and can |
710 | */ |
| 711 | * be used to clock the IWDG and/or the RTC. |
711 | #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) |
| 712 | */ |
712 | |
| 713 | #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE) |
713 | /** @brief Macro to disable the Internal Low Speed oscillator (LSI). |
| 714 | 714 | * @note LSI can not be disabled if the IWDG is running. |
|
| 715 | /** @brief Macro to disable the Internal Low Speed oscillator (LSI). |
715 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
| 716 | * @note LSI can not be disabled if the IWDG is running. |
716 | * clock cycles. |
| 717 | * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator |
717 | */ |
| 718 | * clock cycles. |
718 | #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) |
| 719 | */ |
719 | |
| 720 | #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE) |
720 | /** |
| 721 | 721 | * @} |
|
| 722 | /** |
722 | */ |
| 723 | * @} |
723 | |
| 724 | */ |
724 | /** @defgroup RCC_HSE_Configuration HSE Configuration |
| 725 | 725 | * @{ |
|
| 726 | /** @defgroup RCC_HSE_Configuration HSE Configuration |
726 | */ |
| 727 | * @{ |
727 | |
| 728 | */ |
728 | /** |
| 729 | 729 | * @brief Macro to configure the External High Speed oscillator (HSE). |
|
| 730 | /** |
730 | * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not |
| 731 | * @brief Macro to configure the External High Speed oscillator (HSE). |
731 | * supported by this macro. User should request a transition to HSE Off |
| 732 | * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not |
732 | * first and then HSE On or HSE Bypass. |
| 733 | * supported by this macro. User should request a transition to HSE Off |
733 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
| 734 | * first and then HSE On or HSE Bypass. |
734 | * software should wait on HSERDY flag to be set indicating that HSE clock |
| 735 | * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application |
735 | * is stable and can be used to clock the PLL and/or system clock. |
| 736 | * software should wait on HSERDY flag to be set indicating that HSE clock |
736 | * @note HSE state can not be changed if it is used directly or through the |
| 737 | * is stable and can be used to clock the PLL and/or system clock. |
737 | * PLL as system clock. In this case, you have to select another source |
| 738 | * @note HSE state can not be changed if it is used directly or through the |
738 | * of the system clock then change the HSE state (ex. disable it). |
| 739 | * PLL as system clock. In this case, you have to select another source |
739 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
| 740 | * of the system clock then change the HSE state (ex. disable it). |
740 | * @note This function reset the CSSON bit, so if the clock security system(CSS) |
| 741 | * @note The HSE is stopped by hardware when entering STOP and STANDBY modes. |
741 | * was previously enabled you have to enable it again after calling this |
| 742 | * @note This function reset the CSSON bit, so if the clock security system(CSS) |
742 | * function. |
| 743 | * was previously enabled you have to enable it again after calling this |
743 | * @param __STATE__ specifies the new state of the HSE. |
| 744 | * function. |
744 | * This parameter can be one of the following values: |
| 745 | * @param __STATE__ specifies the new state of the HSE. |
745 | * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after |
| 746 | * This parameter can be one of the following values: |
746 | * 6 HSE oscillator clock cycles. |
| 747 | * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after |
747 | * @arg @ref RCC_HSE_ON turn ON the HSE oscillator |
| 748 | * 6 HSE oscillator clock cycles. |
748 | * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock |
| 749 | * @arg @ref RCC_HSE_ON turn ON the HSE oscillator |
749 | */ |
| 750 | * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock |
750 | #define __HAL_RCC_HSE_CONFIG(__STATE__) \ |
| 751 | */ |
751 | do{ \ |
| 752 | #define __HAL_RCC_HSE_CONFIG(__STATE__) \ |
752 | if ((__STATE__) == RCC_HSE_ON) \ |
| 753 | do{ \ |
753 | { \ |
| 754 | if ((__STATE__) == RCC_HSE_ON) \ |
754 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
| 755 | { \ |
755 | } \ |
| 756 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
756 | else if ((__STATE__) == RCC_HSE_OFF) \ |
| 757 | } \ |
757 | { \ |
| 758 | else if ((__STATE__) == RCC_HSE_OFF) \ |
758 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
| 759 | { \ |
759 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
| 760 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
760 | } \ |
| 761 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
761 | else if ((__STATE__) == RCC_HSE_BYPASS) \ |
| 762 | } \ |
762 | { \ |
| 763 | else if ((__STATE__) == RCC_HSE_BYPASS) \ |
763 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
| 764 | { \ |
764 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
| 765 | SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
765 | } \ |
| 766 | SET_BIT(RCC->CR, RCC_CR_HSEON); \ |
766 | else \ |
| 767 | } \ |
767 | { \ |
| 768 | else \ |
768 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
| 769 | { \ |
769 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
| 770 | CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ |
770 | } \ |
| 771 | CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ |
771 | }while(0U) |
| 772 | } \ |
772 | |
| 773 | }while(0U) |
773 | /** |
| 774 | 774 | * @} |
|
| 775 | /** |
775 | */ |
| 776 | * @} |
776 | |
| 777 | */ |
777 | /** @defgroup RCC_LSE_Configuration LSE Configuration |
| 778 | 778 | * @{ |
|
| 779 | /** @defgroup RCC_LSE_Configuration LSE Configuration |
779 | */ |
| 780 | * @{ |
780 | |
| 781 | */ |
781 | /** |
| 782 | 782 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
|
| 783 | /** |
783 | * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. |
| 784 | * @brief Macro to configure the External Low Speed oscillator (LSE). |
784 | * @note As the LSE is in the Backup domain and write access is denied to |
| 785 | * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro. |
785 | * this domain after reset, you have to enable write access using |
| 786 | * @note As the LSE is in the Backup domain and write access is denied to |
786 | * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
| 787 | * this domain after reset, you have to enable write access using |
787 | * (to be done once after reset). |
| 788 | * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE |
788 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
| 789 | * (to be done once after reset). |
789 | * software should wait on LSERDY flag to be set indicating that LSE clock |
| 790 | * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application |
790 | * is stable and can be used to clock the RTC. |
| 791 | * software should wait on LSERDY flag to be set indicating that LSE clock |
791 | * @param __STATE__ specifies the new state of the LSE. |
| 792 | * is stable and can be used to clock the RTC. |
792 | * This parameter can be one of the following values: |
| 793 | * @param __STATE__ specifies the new state of the LSE. |
793 | * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after |
| 794 | * This parameter can be one of the following values: |
794 | * 6 LSE oscillator clock cycles. |
| 795 | * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after |
795 | * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. |
| 796 | * 6 LSE oscillator clock cycles. |
796 | * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. |
| 797 | * @arg @ref RCC_LSE_ON turn ON the LSE oscillator. |
797 | */ |
| 798 | * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. |
798 | #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
| 799 | */ |
799 | do{ \ |
| 800 | #define __HAL_RCC_LSE_CONFIG(__STATE__) \ |
800 | if ((__STATE__) == RCC_LSE_ON) \ |
| 801 | do{ \ |
801 | { \ |
| 802 | if ((__STATE__) == RCC_LSE_ON) \ |
802 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| 803 | { \ |
803 | } \ |
| 804 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
804 | else if ((__STATE__) == RCC_LSE_OFF) \ |
| 805 | } \ |
805 | { \ |
| 806 | else if ((__STATE__) == RCC_LSE_OFF) \ |
806 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| 807 | { \ |
807 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
| 808 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
808 | } \ |
| 809 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
809 | else if ((__STATE__) == RCC_LSE_BYPASS) \ |
| 810 | } \ |
810 | { \ |
| 811 | else if ((__STATE__) == RCC_LSE_BYPASS) \ |
811 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
| 812 | { \ |
812 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| 813 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
813 | } \ |
| 814 | SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
814 | else \ |
| 815 | } \ |
815 | { \ |
| 816 | else \ |
816 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
| 817 | { \ |
817 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
| 818 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ |
818 | } \ |
| 819 | CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ |
819 | }while(0U) |
| 820 | } \ |
820 | |
| 821 | }while(0U) |
821 | /** |
| 822 | 822 | * @} |
|
| 823 | /** |
823 | */ |
| 824 | * @} |
824 | |
| 825 | */ |
825 | /** @defgroup RCC_PLL_Configuration PLL Configuration |
| 826 | 826 | * @{ |
|
| 827 | /** @defgroup RCC_PLL_Configuration PLL Configuration |
827 | */ |
| 828 | * @{ |
828 | |
| 829 | */ |
829 | /** @brief Macro to enable the main PLL. |
| 830 | 830 | * @note After enabling the main PLL, the application software should wait on |
|
| 831 | /** @brief Macro to enable the main PLL. |
831 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
| 832 | * @note After enabling the main PLL, the application software should wait on |
832 | * be used as system clock source. |
| 833 | * PLLRDY flag to be set indicating that PLL clock is stable and can |
833 | * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. |
| 834 | * be used as system clock source. |
834 | */ |
| 835 | * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. |
835 | #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) |
| 836 | */ |
836 | |
| 837 | #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE) |
837 | /** @brief Macro to disable the main PLL. |
| 838 | 838 | * @note The main PLL can not be disabled if it is used as system clock source |
|
| 839 | /** @brief Macro to disable the main PLL. |
839 | */ |
| 840 | * @note The main PLL can not be disabled if it is used as system clock source |
840 | #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) |
| 841 | */ |
841 | |
| 842 | #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE) |
842 | /** @brief Macro to configure the main PLL clock source and multiplication factors. |
| 843 | 843 | * @note This function must be used only when the main PLL is disabled. |
|
| 844 | /** @brief Macro to configure the main PLL clock source and multiplication factors. |
844 | * |
| 845 | * @note This function must be used only when the main PLL is disabled. |
845 | * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. |
| 846 | * |
846 | * This parameter can be one of the following values: |
| 847 | * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source. |
847 | * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry |
| 848 | * This parameter can be one of the following values: |
848 | * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry |
| 849 | * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry |
849 | * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock |
| 850 | * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry |
850 | * This parameter can be one of the following values: |
| 851 | * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock |
851 | * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 |
| 852 | * This parameter can be one of the following values: |
852 | * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 |
| 853 | * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4 |
853 | @if STM32F105xC |
| 854 | * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6 |
854 | * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 |
| 855 | @if STM32F105xC |
855 | @elseif STM32F107xC |
| 856 | * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 |
856 | * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 |
| 857 | @elseif STM32F107xC |
857 | @else |
| 858 | * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 |
858 | * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 |
| 859 | @else |
859 | * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 |
| 860 | * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 |
860 | * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 |
| 861 | * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 |
861 | * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 |
| 862 | * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 |
862 | * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 |
| 863 | * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 |
863 | * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 |
| 864 | * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 |
864 | * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 |
| 865 | * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 |
865 | * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 |
| 866 | * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 |
866 | * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 |
| 867 | * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 |
867 | @endif |
| 868 | * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 |
868 | * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 |
| 869 | @endif |
869 | * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 |
| 870 | * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8 |
870 | * |
| 871 | * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9 |
871 | */ |
| 872 | * |
872 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ |
| 873 | */ |
873 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) |
| 874 | #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\ |
874 | |
| 875 | MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) )) |
875 | /** @brief Get oscillator clock selected as PLL input clock |
| 876 | 876 | * @retval The clock source used for PLL entry. The returned value can be one |
|
| 877 | /** @brief Get oscillator clock selected as PLL input clock |
877 | * of the following: |
| 878 | * @retval The clock source used for PLL entry. The returned value can be one |
878 | * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock |
| 879 | * of the following: |
879 | * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock |
| 880 | * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock |
880 | */ |
| 881 | * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock |
881 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) |
| 882 | */ |
882 | |
| 883 | #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC))) |
883 | /** |
| 884 | 884 | * @} |
|
| 885 | /** |
885 | */ |
| 886 | * @} |
886 | |
| 887 | */ |
887 | /** @defgroup RCC_Get_Clock_source Get Clock source |
| 888 | 888 | * @{ |
|
| 889 | /** @defgroup RCC_Get_Clock_source Get Clock source |
889 | */ |
| 890 | * @{ |
890 | |
| 891 | */ |
891 | /** |
| 892 | 892 | * @brief Macro to configure the system clock source. |
|
| 893 | /** |
893 | * @param __SYSCLKSOURCE__ specifies the system clock source. |
| 894 | * @brief Macro to configure the system clock source. |
894 | * This parameter can be one of the following values: |
| 895 | * @param __SYSCLKSOURCE__ specifies the system clock source. |
895 | * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. |
| 896 | * This parameter can be one of the following values: |
896 | * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. |
| 897 | * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source. |
897 | * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. |
| 898 | * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source. |
898 | */ |
| 899 | * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source. |
899 | #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ |
| 900 | */ |
900 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) |
| 901 | #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ |
901 | |
| 902 | MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__)) |
902 | /** @brief Macro to get the clock source used as system clock. |
| 903 | 903 | * @retval The clock source used as system clock. The returned value can be one |
|
| 904 | /** @brief Macro to get the clock source used as system clock. |
904 | * of the following: |
| 905 | * @retval The clock source used as system clock. The returned value can be one |
905 | * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock |
| 906 | * of the following: |
906 | * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock |
| 907 | * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock |
907 | * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock |
| 908 | * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock |
908 | */ |
| 909 | * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock |
909 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) |
| 910 | */ |
910 | |
| 911 | #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS))) |
911 | /** |
| 912 | 912 | * @} |
|
| 913 | /** |
913 | */ |
| 914 | * @} |
914 | |
| 915 | */ |
915 | /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config |
| 916 | 916 | * @{ |
|
| 917 | /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config |
917 | */ |
| 918 | * @{ |
918 | |
| 919 | */ |
919 | #if defined(RCC_CFGR_MCO_3) |
| 920 | 920 | /** @brief Macro to configure the MCO clock. |
|
| 921 | #if defined(RCC_CFGR_MCO_3) |
921 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
| 922 | /** @brief Macro to configure the MCO clock. |
922 | * This parameter can be one of the following values: |
| 923 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
923 | * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock |
| 924 | * This parameter can be one of the following values: |
924 | * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock |
| 925 | * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock |
925 | * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock |
| 926 | * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock |
926 | * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock |
| 927 | * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock |
927 | * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock |
| 928 | * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock |
928 | * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock |
| 929 | * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock |
929 | * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock |
| 930 | * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock |
930 | * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock |
| 931 | * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock |
931 | * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock |
| 932 | * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock |
932 | * @param __MCODIV__ specifies the MCO clock prescaler. |
| 933 | * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock |
933 | * This parameter can be one of the following values: |
| 934 | * @param __MCODIV__ specifies the MCO clock prescaler. |
934 | * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source |
| 935 | * This parameter can be one of the following values: |
935 | */ |
| 936 | * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source |
936 | #else |
| 937 | */ |
937 | /** @brief Macro to configure the MCO clock. |
| 938 | #else |
938 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
| 939 | /** @brief Macro to configure the MCO clock. |
939 | * This parameter can be one of the following values: |
| 940 | * @param __MCOCLKSOURCE__ specifies the MCO clock source. |
940 | * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock |
| 941 | * This parameter can be one of the following values: |
941 | * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock |
| 942 | * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock |
942 | * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock |
| 943 | * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock |
943 | * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock |
| 944 | * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock |
944 | * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock |
| 945 | * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock |
945 | * @param __MCODIV__ specifies the MCO clock prescaler. |
| 946 | * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock |
946 | * This parameter can be one of the following values: |
| 947 | * @param __MCODIV__ specifies the MCO clock prescaler. |
947 | * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source |
| 948 | * This parameter can be one of the following values: |
948 | */ |
| 949 | * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source |
949 | #endif |
| 950 | */ |
950 | |
| 951 | #endif |
951 | #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
| 952 | 952 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) |
|
| 953 | #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ |
953 | |
| 954 | MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__)) |
954 | |
| 955 | 955 | /** |
|
| 956 | 956 | * @} |
|
| 957 | /** |
957 | */ |
| 958 | * @} |
958 | |
| 959 | */ |
959 | /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration |
| 960 | 960 | * @{ |
|
| 961 | /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration |
961 | */ |
| 962 | * @{ |
962 | |
| 963 | */ |
963 | /** @brief Macro to configure the RTC clock (RTCCLK). |
| 964 | 964 | * @note As the RTC clock configuration bits are in the Backup domain and write |
|
| 965 | /** @brief Macro to configure the RTC clock (RTCCLK). |
965 | * access is denied to this domain after reset, you have to enable write |
| 966 | * @note As the RTC clock configuration bits are in the Backup domain and write |
966 | * access using the Power Backup Access macro before to configure |
| 967 | * access is denied to this domain after reset, you have to enable write |
967 | * the RTC clock source (to be done once after reset). |
| 968 | * access using the Power Backup Access macro before to configure |
968 | * @note Once the RTC clock is configured it can't be changed unless the |
| 969 | * the RTC clock source (to be done once after reset). |
969 | * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by |
| 970 | * @note Once the RTC clock is configured it can't be changed unless the |
970 | * a Power On Reset (POR). |
| 971 | * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by |
971 | * |
| 972 | * a Power On Reset (POR). |
972 | * @param __RTC_CLKSOURCE__ specifies the RTC clock source. |
| 973 | * |
973 | * This parameter can be one of the following values: |
| 974 | * @param __RTC_CLKSOURCE__ specifies the RTC clock source. |
974 | * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock |
| 975 | * This parameter can be one of the following values: |
975 | * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock |
| 976 | * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock |
976 | * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock |
| 977 | * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock |
977 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock |
| 978 | * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock |
978 | * @note If the LSE or LSI is used as RTC clock source, the RTC continues to |
| 979 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock |
979 | * work in STOP and STANDBY modes, and can be used as wakeup source. |
| 980 | * @note If the LSE or LSI is used as RTC clock source, the RTC continues to |
980 | * However, when the HSE clock is used as RTC clock source, the RTC |
| 981 | * work in STOP and STANDBY modes, and can be used as wakeup source. |
981 | * cannot be used in STOP and STANDBY modes. |
| 982 | * However, when the HSE clock is used as RTC clock source, the RTC |
982 | * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as |
| 983 | * cannot be used in STOP and STANDBY modes. |
983 | * RTC clock source). |
| 984 | * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as |
984 | */ |
| 985 | * RTC clock source). |
985 | #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) |
| 986 | */ |
986 | |
| 987 | #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) |
987 | /** @brief Macro to get the RTC clock source. |
| 988 | 988 | * @retval The clock source can be one of the following values: |
|
| 989 | /** @brief Macro to get the RTC clock source. |
989 | * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock |
| 990 | * @retval The clock source can be one of the following values: |
990 | * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock |
| 991 | * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock |
991 | * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock |
| 992 | * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock |
992 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock |
| 993 | * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock |
993 | */ |
| 994 | * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock |
994 | #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) |
| 995 | */ |
995 | |
| 996 | #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)) |
996 | /** @brief Macro to enable the the RTC clock. |
| 997 | 997 | * @note These macros must be used only after the RTC clock source was selected. |
|
| 998 | /** @brief Macro to enable the the RTC clock. |
998 | */ |
| 999 | * @note These macros must be used only after the RTC clock source was selected. |
999 | #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) |
| 1000 | */ |
1000 | |
| 1001 | #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE) |
1001 | /** @brief Macro to disable the the RTC clock. |
| 1002 | 1002 | * @note These macros must be used only after the RTC clock source was selected. |
|
| 1003 | /** @brief Macro to disable the the RTC clock. |
1003 | */ |
| 1004 | * @note These macros must be used only after the RTC clock source was selected. |
1004 | #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) |
| 1005 | */ |
1005 | |
| 1006 | #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE) |
1006 | /** @brief Macro to force the Backup domain reset. |
| 1007 | 1007 | * @note This function resets the RTC peripheral (including the backup registers) |
|
| 1008 | /** @brief Macro to force the Backup domain reset. |
1008 | * and the RTC clock source selection in RCC_BDCR register. |
| 1009 | * @note This function resets the RTC peripheral (including the backup registers) |
1009 | */ |
| 1010 | * and the RTC clock source selection in RCC_BDCR register. |
1010 | #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) |
| 1011 | */ |
1011 | |
| 1012 | #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE) |
1012 | /** @brief Macros to release the Backup domain reset. |
| 1013 | 1013 | */ |
|
| 1014 | /** @brief Macros to release the Backup domain reset. |
1014 | #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) |
| 1015 | */ |
1015 | |
| 1016 | #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE) |
1016 | /** |
| 1017 | 1017 | * @} |
|
| 1018 | /** |
1018 | */ |
| 1019 | * @} |
1019 | |
| 1020 | */ |
1020 | /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management |
| 1021 | 1021 | * @brief macros to manage the specified RCC Flags and interrupts. |
|
| 1022 | /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management |
1022 | * @{ |
| 1023 | * @brief macros to manage the specified RCC Flags and interrupts. |
1023 | */ |
| 1024 | * @{ |
1024 | |
| 1025 | */ |
1025 | /** @brief Enable RCC interrupt. |
| 1026 | 1026 | * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. |
|
| 1027 | /** @brief Enable RCC interrupt. |
1027 | * This parameter can be any combination of the following values: |
| 1028 | * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled. |
1028 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt |
| 1029 | * This parameter can be any combination of the following values: |
1029 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt |
| 1030 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt |
1030 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt |
| 1031 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt |
1031 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt |
| 1032 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt |
1032 | * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt |
| 1033 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt |
1033 | @if STM32F105xx |
| 1034 | * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt |
1034 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
| 1035 | @if STM32F105xx |
1035 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
| 1036 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
1036 | @elsif STM32F107xx |
| 1037 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
1037 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
| 1038 | @elsif STM32F107xx |
1038 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
| 1039 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
1039 | @endif |
| 1040 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
1040 | */ |
| 1041 | @endif |
1041 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
| 1042 | */ |
1042 | |
| 1043 | #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__)) |
1043 | /** @brief Disable RCC interrupt. |
| 1044 | 1044 | * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. |
|
| 1045 | /** @brief Disable RCC interrupt. |
1045 | * This parameter can be any combination of the following values: |
| 1046 | * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled. |
1046 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt |
| 1047 | * This parameter can be any combination of the following values: |
1047 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt |
| 1048 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt |
1048 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt |
| 1049 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt |
1049 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt |
| 1050 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt |
1050 | * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt |
| 1051 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt |
1051 | @if STM32F105xx |
| 1052 | * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt |
1052 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
| 1053 | @if STM32F105xx |
1053 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
| 1054 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
1054 | @elsif STM32F107xx |
| 1055 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
1055 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
| 1056 | @elsif STM32F107xx |
1056 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
| 1057 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
1057 | @endif |
| 1058 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
1058 | */ |
| 1059 | @endif |
1059 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) |
| 1060 | */ |
1060 | |
| 1061 | #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__))) |
1061 | /** @brief Clear the RCC's interrupt pending bits. |
| 1062 | 1062 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
|
| 1063 | /** @brief Clear the RCC's interrupt pending bits. |
1063 | * This parameter can be any combination of the following values: |
| 1064 | * @param __INTERRUPT__ specifies the interrupt pending bit to clear. |
1064 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. |
| 1065 | * This parameter can be any combination of the following values: |
1065 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt. |
| 1066 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. |
1066 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. |
| 1067 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt. |
1067 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt. |
| 1068 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. |
1068 | * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. |
| 1069 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt. |
1069 | @if STM32F105xx |
| 1070 | * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. |
1070 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
| 1071 | @if STM32F105xx |
1071 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
| 1072 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
1072 | @elsif STM32F107xx |
| 1073 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
1073 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
| 1074 | @elsif STM32F107xx |
1074 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
| 1075 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
1075 | @endif |
| 1076 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
1076 | * @arg @ref RCC_IT_CSS Clock Security System interrupt |
| 1077 | @endif |
1077 | */ |
| 1078 | * @arg @ref RCC_IT_CSS Clock Security System interrupt |
1078 | #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) |
| 1079 | */ |
1079 | |
| 1080 | #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__)) |
1080 | /** @brief Check the RCC's interrupt has occurred or not. |
| 1081 | 1081 | * @param __INTERRUPT__ specifies the RCC interrupt source to check. |
|
| 1082 | /** @brief Check the RCC's interrupt has occurred or not. |
1082 | * This parameter can be one of the following values: |
| 1083 | * @param __INTERRUPT__ specifies the RCC interrupt source to check. |
1083 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. |
| 1084 | * This parameter can be one of the following values: |
1084 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt. |
| 1085 | * @arg @ref RCC_IT_LSIRDY LSI ready interrupt. |
1085 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. |
| 1086 | * @arg @ref RCC_IT_LSERDY LSE ready interrupt. |
1086 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt. |
| 1087 | * @arg @ref RCC_IT_HSIRDY HSI ready interrupt. |
1087 | * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. |
| 1088 | * @arg @ref RCC_IT_HSERDY HSE ready interrupt. |
1088 | @if STM32F105xx |
| 1089 | * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt. |
1089 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
| 1090 | @if STM32F105xx |
1090 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
| 1091 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
1091 | @elsif STM32F107xx |
| 1092 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
1092 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
| 1093 | @elsif STM32F107xx |
1093 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
| 1094 | * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt. |
1094 | @endif |
| 1095 | * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt. |
1095 | * @arg @ref RCC_IT_CSS Clock Security System interrupt |
| 1096 | @endif |
1096 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
| 1097 | * @arg @ref RCC_IT_CSS Clock Security System interrupt |
1097 | */ |
| 1098 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
1098 | #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) |
| 1099 | */ |
1099 | |
| 1100 | #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__)) |
1100 | /** @brief Set RMVF bit to clear the reset flags. |
| 1101 | 1101 | * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, |
|
| 1102 | /** @brief Set RMVF bit to clear the reset flags. |
1102 | * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST |
| 1103 | * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, |
1103 | */ |
| 1104 | * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST |
1104 | #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) |
| 1105 | */ |
1105 | |
| 1106 | #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE) |
1106 | /** @brief Check RCC flag is set or not. |
| 1107 | 1107 | * @param __FLAG__ specifies the flag to check. |
|
| 1108 | /** @brief Check RCC flag is set or not. |
1108 | * This parameter can be one of the following values: |
| 1109 | * @param __FLAG__ specifies the flag to check. |
1109 | * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. |
| 1110 | * This parameter can be one of the following values: |
1110 | * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. |
| 1111 | * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready. |
1111 | * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. |
| 1112 | * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready. |
1112 | @if STM32F105xx |
| 1113 | * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready. |
1113 | * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. |
| 1114 | @if STM32F105xx |
1114 | * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. |
| 1115 | * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. |
1115 | @elsif STM32F107xx |
| 1116 | * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. |
1116 | * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. |
| 1117 | @elsif STM32F107xx |
1117 | * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. |
| 1118 | * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready. |
1118 | @endif |
| 1119 | * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready. |
1119 | * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. |
| 1120 | @endif |
1120 | * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. |
| 1121 | * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready. |
1121 | * @arg @ref RCC_FLAG_PINRST Pin reset. |
| 1122 | * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready. |
1122 | * @arg @ref RCC_FLAG_PORRST POR/PDR reset. |
| 1123 | * @arg @ref RCC_FLAG_PINRST Pin reset. |
1123 | * @arg @ref RCC_FLAG_SFTRST Software reset. |
| 1124 | * @arg @ref RCC_FLAG_PORRST POR/PDR reset. |
1124 | * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. |
| 1125 | * @arg @ref RCC_FLAG_SFTRST Software reset. |
1125 | * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. |
| 1126 | * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset. |
1126 | * @arg @ref RCC_FLAG_LPWRRST Low Power reset. |
| 1127 | * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset. |
1127 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| 1128 | * @arg @ref RCC_FLAG_LPWRRST Low Power reset. |
1128 | */ |
| 1129 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
1129 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ |
| 1130 | */ |
1130 | ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ |
| 1131 | #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \ |
1131 | RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) |
| 1132 | ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \ |
1132 | |
| 1133 | RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK))) |
1133 | /** |
| 1134 | 1134 | * @} |
|
| 1135 | /** |
1135 | */ |
| 1136 | * @} |
1136 | |
| 1137 | */ |
1137 | /** |
| 1138 | 1138 | * @} |
|
| 1139 | /** |
1139 | */ |
| 1140 | * @} |
1140 | |
| 1141 | */ |
1141 | /* Include RCC HAL Extension module */ |
| 1142 | 1142 | #include "stm32f1xx_hal_rcc_ex.h" |
|
| 1143 | /* Include RCC HAL Extension module */ |
1143 | |
| 1144 | #include "stm32f1xx_hal_rcc_ex.h" |
1144 | /* Exported functions --------------------------------------------------------*/ |
| 1145 | 1145 | /** @addtogroup RCC_Exported_Functions |
|
| 1146 | /* Exported functions --------------------------------------------------------*/ |
1146 | * @{ |
| 1147 | /** @addtogroup RCC_Exported_Functions |
1147 | */ |
| 1148 | * @{ |
1148 | |
| 1149 | */ |
1149 | /** @addtogroup RCC_Exported_Functions_Group1 |
| 1150 | 1150 | * @{ |
|
| 1151 | /** @addtogroup RCC_Exported_Functions_Group1 |
1151 | */ |
| 1152 | * @{ |
1152 | |
| 1153 | */ |
1153 | /* Initialization and de-initialization functions ******************************/ |
| 1154 | 1154 | HAL_StatusTypeDef HAL_RCC_DeInit(void); |
|
| 1155 | /* Initialization and de-initialization functions ******************************/ |
1155 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
| 1156 | HAL_StatusTypeDef HAL_RCC_DeInit(void); |
1156 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
| 1157 | HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
1157 | |
| 1158 | HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); |
1158 | /** |
| 1159 | 1159 | * @} |
|
| 1160 | /** |
1160 | */ |
| 1161 | * @} |
1161 | |
| 1162 | */ |
1162 | /** @addtogroup RCC_Exported_Functions_Group2 |
| 1163 | 1163 | * @{ |
|
| 1164 | /** @addtogroup RCC_Exported_Functions_Group2 |
1164 | */ |
| 1165 | * @{ |
1165 | |
| 1166 | */ |
1166 | /* Peripheral Control functions ************************************************/ |
| 1167 | 1167 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
|
| 1168 | /* Peripheral Control functions ************************************************/ |
1168 | void HAL_RCC_EnableCSS(void); |
| 1169 | void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); |
1169 | void HAL_RCC_DisableCSS(void); |
| 1170 | void HAL_RCC_EnableCSS(void); |
1170 | uint32_t HAL_RCC_GetSysClockFreq(void); |
| 1171 | void HAL_RCC_DisableCSS(void); |
1171 | uint32_t HAL_RCC_GetHCLKFreq(void); |
| 1172 | uint32_t HAL_RCC_GetSysClockFreq(void); |
1172 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
| 1173 | uint32_t HAL_RCC_GetHCLKFreq(void); |
1173 | uint32_t HAL_RCC_GetPCLK2Freq(void); |
| 1174 | uint32_t HAL_RCC_GetPCLK1Freq(void); |
1174 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
| 1175 | uint32_t HAL_RCC_GetPCLK2Freq(void); |
1175 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
| 1176 | void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); |
1176 | |
| 1177 | void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency); |
1177 | /* CSS NMI IRQ handler */ |
| 1178 | 1178 | void HAL_RCC_NMI_IRQHandler(void); |
|
| 1179 | /* CSS NMI IRQ handler */ |
1179 | |
| 1180 | void HAL_RCC_NMI_IRQHandler(void); |
1180 | /* User Callbacks in non blocking mode (IT mode) */ |
| 1181 | 1181 | void HAL_RCC_CSSCallback(void); |
|
| 1182 | /* User Callbacks in non blocking mode (IT mode) */ |
1182 | |
| 1183 | void HAL_RCC_CSSCallback(void); |
1183 | /** |
| 1184 | 1184 | * @} |
|
| 1185 | /** |
1185 | */ |
| 1186 | * @} |
1186 | |
| 1187 | */ |
1187 | /** |
| 1188 | 1188 | * @} |
|
| 1189 | /** |
1189 | */ |
| 1190 | * @} |
1190 | |
| 1191 | */ |
1191 | /** @addtogroup RCC_Private_Constants |
| 1192 | 1192 | * @{ |
|
| 1193 | /** @addtogroup RCC_Private_Constants |
1193 | */ |
| 1194 | * @{ |
1194 | |
| 1195 | */ |
1195 | /** @defgroup RCC_Timeout RCC Timeout |
| 1196 | 1196 | * @{ |
|
| 1197 | /** @defgroup RCC_Timeout RCC Timeout |
1197 | */ |
| 1198 | * @{ |
1198 | |
| 1199 | */ |
1199 | /* Disable Backup domain write protection state change timeout */ |
| 1200 | 1200 | #define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ |
|
| 1201 | /* Disable Backup domain write protection state change timeout */ |
1201 | /* LSE state change timeout */ |
| 1202 | #define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */ |
1202 | #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT |
| 1203 | /* LSE state change timeout */ |
1203 | #define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ |
| 1204 | #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT |
1204 | #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
| 1205 | #define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */ |
1205 | #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ |
| 1206 | #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT |
1206 | #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ |
| 1207 | #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ |
1207 | #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ |
| 1208 | #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ |
1208 | |
| 1209 | #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */ |
1209 | /** |
| 1210 | 1210 | * @} |
|
| 1211 | /** |
1211 | */ |
| 1212 | * @} |
1212 | |
| 1213 | */ |
1213 | /** @defgroup RCC_Register_Offset Register offsets |
| 1214 | 1214 | * @{ |
|
| 1215 | /** @defgroup RCC_Register_Offset Register offsets |
1215 | */ |
| 1216 | * @{ |
1216 | #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
| 1217 | */ |
1217 | #define RCC_CR_OFFSET 0x00U |
| 1218 | #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
1218 | #define RCC_CFGR_OFFSET 0x04U |
| 1219 | #define RCC_CR_OFFSET 0x00U |
1219 | #define RCC_CIR_OFFSET 0x08U |
| 1220 | #define RCC_CFGR_OFFSET 0x04U |
1220 | #define RCC_BDCR_OFFSET 0x20U |
| 1221 | #define RCC_CIR_OFFSET 0x08U |
1221 | #define RCC_CSR_OFFSET 0x24U |
| 1222 | #define RCC_BDCR_OFFSET 0x20U |
1222 | |
| 1223 | #define RCC_CSR_OFFSET 0x24U |
1223 | /** |
| 1224 | 1224 | * @} |
|
| 1225 | /** |
1225 | */ |
| 1226 | * @} |
1226 | |
| 1227 | */ |
1227 | /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion |
| 1228 | 1228 | * @brief RCC registers bit address in the alias region |
|
| 1229 | /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion |
1229 | * @{ |
| 1230 | * @brief RCC registers bit address in the alias region |
1230 | */ |
| 1231 | * @{ |
1231 | #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) |
| 1232 | */ |
1232 | #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) |
| 1233 | #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET) |
1233 | #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) |
| 1234 | #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET) |
1234 | #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) |
| 1235 | #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET) |
1235 | #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) |
| 1236 | #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET) |
1236 | |
| 1237 | #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET) |
1237 | /* --- CR Register ---*/ |
| 1238 | 1238 | /* Alias word address of HSION bit */ |
|
| 1239 | /* --- CR Register ---*/ |
1239 | #define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos |
| 1240 | /* Alias word address of HSION bit */ |
1240 | #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) |
| 1241 | #define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos |
1241 | /* Alias word address of HSEON bit */ |
| 1242 | #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U))) |
1242 | #define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos |
| 1243 | /* Alias word address of HSEON bit */ |
1243 | #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) |
| 1244 | #define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos |
1244 | /* Alias word address of CSSON bit */ |
| 1245 | #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U))) |
1245 | #define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos |
| 1246 | /* Alias word address of CSSON bit */ |
1246 | #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) |
| 1247 | #define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos |
1247 | /* Alias word address of PLLON bit */ |
| 1248 | #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U))) |
1248 | #define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos |
| 1249 | /* Alias word address of PLLON bit */ |
1249 | #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) |
| 1250 | #define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos |
1250 | |
| 1251 | #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))) |
1251 | /* --- CSR Register ---*/ |
| 1252 | 1252 | /* Alias word address of LSION bit */ |
|
| 1253 | /* --- CSR Register ---*/ |
1253 | #define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos |
| 1254 | /* Alias word address of LSION bit */ |
1254 | #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) |
| 1255 | #define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos |
1255 | |
| 1256 | #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U))) |
1256 | /* Alias word address of RMVF bit */ |
| 1257 | 1257 | #define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos |
|
| 1258 | /* Alias word address of RMVF bit */ |
1258 | #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) |
| 1259 | #define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos |
1259 | |
| 1260 | #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U))) |
1260 | /* --- BDCR Registers ---*/ |
| 1261 | 1261 | /* Alias word address of LSEON bit */ |
|
| 1262 | /* --- BDCR Registers ---*/ |
1262 | #define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos |
| 1263 | /* Alias word address of LSEON bit */ |
1263 | #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) |
| 1264 | #define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos |
1264 | |
| 1265 | #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U))) |
1265 | /* Alias word address of LSEON bit */ |
| 1266 | 1266 | #define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos |
|
| 1267 | /* Alias word address of LSEON bit */ |
1267 | #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) |
| 1268 | #define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos |
1268 | |
| 1269 | #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U))) |
1269 | /* Alias word address of RTCEN bit */ |
| 1270 | 1270 | #define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos |
|
| 1271 | /* Alias word address of RTCEN bit */ |
1271 | #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) |
| 1272 | #define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos |
1272 | |
| 1273 | #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U))) |
1273 | /* Alias word address of BDRST bit */ |
| 1274 | 1274 | #define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos |
|
| 1275 | /* Alias word address of BDRST bit */ |
1275 | #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) |
| 1276 | #define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos |
1276 | |
| 1277 | #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))) |
1277 | /** |
| 1278 | 1278 | * @} |
|
| 1279 | /** |
1279 | */ |
| 1280 | * @} |
1280 | |
| 1281 | */ |
1281 | /* CR register byte 2 (Bits[23:16]) base address */ |
| 1282 | 1282 | #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) |
|
| 1283 | /* CR register byte 2 (Bits[23:16]) base address */ |
1283 | |
| 1284 | #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U)) |
1284 | /* CIR register byte 1 (Bits[15:8]) base address */ |
| 1285 | 1285 | #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) |
|
| 1286 | /* CIR register byte 1 (Bits[15:8]) base address */ |
1286 | |
| 1287 | #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U)) |
1287 | /* CIR register byte 2 (Bits[23:16]) base address */ |
| 1288 | 1288 | #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) |
|
| 1289 | /* CIR register byte 2 (Bits[23:16]) base address */ |
1289 | |
| 1290 | #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U)) |
1290 | /* Defines used for Flags */ |
| 1291 | 1291 | #define CR_REG_INDEX ((uint8_t)1) |
|
| 1292 | /* Defines used for Flags */ |
1292 | #define BDCR_REG_INDEX ((uint8_t)2) |
| 1293 | #define CR_REG_INDEX ((uint8_t)1) |
1293 | #define CSR_REG_INDEX ((uint8_t)3) |
| 1294 | #define BDCR_REG_INDEX ((uint8_t)2) |
1294 | |
| 1295 | #define CSR_REG_INDEX ((uint8_t)3) |
1295 | #define RCC_FLAG_MASK ((uint8_t)0x1F) |
| 1296 | 1296 | ||
| 1297 | #define RCC_FLAG_MASK ((uint8_t)0x1F) |
1297 | /** |
| 1298 | 1298 | * @} |
|
| 1299 | /** |
1299 | */ |
| 1300 | * @} |
1300 | |
| 1301 | */ |
1301 | /** @addtogroup RCC_Private_Macros |
| 1302 | 1302 | * @{ |
|
| 1303 | /** @addtogroup RCC_Private_Macros |
1303 | */ |
| 1304 | * @{ |
1304 | /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy |
| 1305 | */ |
1305 | * @{ |
| 1306 | /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy |
1306 | */ |
| 1307 | * @{ |
1307 | #define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE |
| 1308 | */ |
1308 | #define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE |
| 1309 | #define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE |
1309 | #define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET |
| 1310 | #define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE |
1310 | #define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET |
| 1311 | #define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET |
1311 | /** |
| 1312 | #define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET |
1312 | * @} |
| 1313 | /** |
1313 | */ |
| 1314 | * @} |
1314 | |
| 1315 | */ |
1315 | #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ |
| 1316 | 1316 | ((__SOURCE__) == RCC_PLLSOURCE_HSE)) |
|
| 1317 | #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \ |
1317 | #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ |
| 1318 | ((__SOURCE__) == RCC_PLLSOURCE_HSE)) |
1318 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
| 1319 | #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ |
1319 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
| 1320 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \ |
1320 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
| 1321 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \ |
1321 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) |
| 1322 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \ |
1322 | #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ |
| 1323 | (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)) |
1323 | ((__HSE__) == RCC_HSE_BYPASS)) |
| 1324 | #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ |
1324 | #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ |
| 1325 | ((__HSE__) == RCC_HSE_BYPASS)) |
1325 | ((__LSE__) == RCC_LSE_BYPASS)) |
| 1326 | #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ |
1326 | #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) |
| 1327 | ((__LSE__) == RCC_LSE_BYPASS)) |
1327 | #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) |
| 1328 | #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) |
1328 | #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) |
| 1329 | #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU) |
1329 | #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ |
| 1330 | #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) |
1330 | ((__PLL__) == RCC_PLL_ON)) |
| 1331 | #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \ |
1331 | |
| 1332 | ((__PLL__) == RCC_PLL_ON)) |
1332 | #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ |
| 1333 | 1333 | (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ |
|
| 1334 | #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \ |
1334 | (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ |
| 1335 | (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \ |
1335 | (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) |
| 1336 | (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \ |
1336 | #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ |
| 1337 | (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)) |
1337 | ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ |
| 1338 | #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ |
1338 | ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) |
| 1339 | ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ |
1339 | #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ |
| 1340 | ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) |
1340 | ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ |
| 1341 | #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \ |
1341 | ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) |
| 1342 | ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \ |
1342 | #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ |
| 1343 | ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK)) |
1343 | ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ |
| 1344 | #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ |
1344 | ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ |
| 1345 | ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ |
1345 | ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ |
| 1346 | ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ |
1346 | ((__HCLK__) == RCC_SYSCLK_DIV512)) |
| 1347 | ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ |
1347 | #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ |
| 1348 | ((__HCLK__) == RCC_SYSCLK_DIV512)) |
1348 | ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ |
| 1349 | #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ |
1349 | ((__PCLK__) == RCC_HCLK_DIV16)) |
| 1350 | ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ |
1350 | #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) |
| 1351 | ((__PCLK__) == RCC_HCLK_DIV16)) |
1351 | #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) |
| 1352 | #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO) |
1352 | #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ |
| 1353 | #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1)) |
1353 | ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ |
| 1354 | #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ |
1354 | ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ |
| 1355 | ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ |
1355 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) |
| 1356 | ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ |
1356 | |
| 1357 | ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128)) |
1357 | /** |
| 1358 | 1358 | * @} |
|
| 1359 | /** |
1359 | */ |
| 1360 | * @} |
1360 | |
| 1361 | */ |
1361 | /** |
| 1362 | 1362 | * @} |
|
| 1363 | /** |
1363 | */ |
| 1364 | * @} |
1364 | |
| 1365 | */ |
1365 | /** |
| 1366 | 1366 | * @} |
|
| 1367 | /** |
1367 | */ |
| 1368 | * @} |
1368 | |
| 1369 | */ |
1369 | #ifdef __cplusplus |
| 1370 | 1370 | } |
|
| 1371 | #ifdef __cplusplus |
1371 | #endif |
| 1372 | } |
1372 | |
| 1373 | #endif |
1373 | #endif /* __STM32F1xx_HAL_RCC_H */ |
| 1374 | 1374 | ||
| 1375 | #endif /* __STM32F1xx_HAL_RCC_H */ |
1375 | |
| 1376 | - | ||
| 1377 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |
| 1378 | - | ||