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 /**
   ******************************************************************************
   * @file    stm32f1xx_hal_rcc.h
   * @author  MCD Application Team
-  * @version V1.0.1
+  * @version V1.0.4
-  * @date    31-July-2015
+  * @date    29-April-2016
   * @brief   Header file of RCC HAL module.
   ******************************************************************************
   * @attention
+  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
   *   1. Redistributions of source code must retain the above copyright notice,
   *      this list of conditions and the following disclaimer.
 #define RCC_DBP_TIMEOUT_VALUE  ((uint32_t)100)       /* 100 ms */
 /* LSE state change timeout */
 #define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT
 #define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000)  /* 5 s    */
 #define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE         ((uint32_t)100)    /* 100 ms */
+#define HSI_TIMEOUT_VALUE         ((uint32_t)2)      /* 2 ms (minimum Tick + 1) */
-#define LSI_TIMEOUT_VALUE         ((uint32_t)100)    /* 100 ms */
+#define LSI_TIMEOUT_VALUE         ((uint32_t)2)      /* 2 ms (minimum Tick + 1) */
-#define PLL_TIMEOUT_VALUE         ((uint32_t)100)    /* 100 ms */
+#define PLL_TIMEOUT_VALUE         ((uint32_t)2)      /* 2 ms (minimum Tick + 1) */
 #define LSI_VALUE                 ((uint32_t)40000)  /* 40kHz */
 /**
   * @}
   */
 /** @defgroup RCC_Register_Offset Register offsets
   uint32_t PLLMUL;        /*!< PLLMUL: Multiplication factor for PLL VCO input clock
                               This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
 } RCC_PLLInitTypeDef;
 /**
   * @brief  RCC System, AHB and APB busses clock configuration structure definition
   */
 typedef struct
+{
   uint32_t ClockType;             /*!< The clock to be configured.
                                        This parameter can be a value of @ref RCC_System_Clock_Type */
   uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
                                        This parameter can be a value of @ref RCC_System_Clock_Source */
   uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
                                        This parameter can be a value of @ref RCC_AHB_Clock_Source */
   uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
   uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
                                        This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
 } RCC_ClkInitTypeDef;
 /**
   */
 /** @defgroup RCC_HSI_Config HSI Config
   * @{
   */
-#define RCC_HSI_OFF                      ((uint32_t)0x00000000)   /*!< HSI clock deactivation */
+#define RCC_HSI_OFF                      ((uint32_t)0x00000000)           /*!< HSI clock deactivation */
-#define RCC_HSI_ON                       RCC_CR_HSION             /*!< HSI clock activation */
+#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */
 #define RCC_HSICALIBRATION_DEFAULT       ((uint32_t)0x10)         /* Default HSI calibration trimming value */
 /**
   * @}
 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
   * @{
   */
 #define RCC_RTCCLKSOURCE_NO_CLK          ((uint32_t)0x00000000)                 /*!< No clock */
-#define RCC_RTCCLKSOURCE_LSE             RCC_BDCR_RTCSEL_LSE                    /*!< LSE oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSE             RCC_BDCR_RTCSEL_LSE                  /*!< LSE oscillator clock used as RTC clock */
-#define RCC_RTCCLKSOURCE_LSI             RCC_BDCR_RTCSEL_LSI                    /*!< LSI oscillator clock used as RTC clock */
+#define RCC_RTCCLKSOURCE_LSI             RCC_BDCR_RTCSEL_LSI                  /*!< LSI oscillator clock used as RTC clock */
 #define RCC_RTCCLKSOURCE_HSE_DIV128      RCC_BDCR_RTCSEL_HSE                    /*!< HSE oscillator clock divided by 128 used as RTC clock */
 /**
   * @}
   */
   */
 /** @defgroup RCC_Interrupt Interrupts
   * @{
   */
-#define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
+#define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF)   /*!< LSI Ready Interrupt flag */
-#define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
+#define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF)   /*!< LSE Ready Interrupt flag */
-#define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
+#define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF)   /*!< HSI Ready Interrupt flag */
-#define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
+#define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF)   /*!< HSE Ready Interrupt flag */
-#define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
+#define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF)   /*!< PLL Ready Interrupt flag */
-#define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)    /*!< Clock Security System Interrupt flag */
+#define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)      /*!< Clock Security System Interrupt flag */
 /**
   * @}
   */
 /** @defgroup RCC_Flag Flags
 #define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY))) /*!< External High Speed clock ready flag */
 #define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY))) /*!< PLL clock ready flag */
 /* Flags in the CSR register */
 #define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY)))   /*!< Internal Low Speed oscillator Ready */
-#define RCC_FLAG_RMV                     ((uint8_t)((CSR_REG_INDEX << 5) | RCC_RMVF_BIT_NUMBER))     /*!< Remove reset flag */
 #define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF)))  /*!< PIN reset flag */
 #define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF)))  /*!< POR/PDR reset flag */
 #define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF)))  /*!< Software Reset flag */
 #define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF))) /*!< Independent Watchdog reset flag */
 #define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF))) /*!< Window watchdog reset flag */
 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
   * @brief  Force or release APB1 peripheral reset.
   * @{
   */
-#define __HAL_RCC_APB1_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_APB1_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFFU)
 #define __HAL_RCC_TIM2_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
 #define __HAL_RCC_TIM3_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
 #define __HAL_RCC_WWDG_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
 #define __HAL_RCC_USART2_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
 #define __HAL_RCC_I2C1_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
   * @brief  Force or release APB2 peripheral reset.
   * @{
   */
-#define __HAL_RCC_APB2_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFF)
+#define __HAL_RCC_APB2_FORCE_RESET()       (RCC->APB2RSTR = 0xFFFFFFFFU)
 #define __HAL_RCC_AFIO_FORCE_RESET()       (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
 #define __HAL_RCC_GPIOA_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
 #define __HAL_RCC_GPIOB_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
 #define __HAL_RCC_GPIOC_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
 #define __HAL_RCC_GPIOD_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
   *         is stable and can be used to clock the PLL and/or system clock.
   * @note   HSE state can not be changed if it is used directly or through the
   *         PLL as system clock. In this case, you have to select another source
   *         of the system clock then change the HSE state (ex. disable it).
   * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   This function reset the CSSON bit, so if the Clock security system(CSS)
+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)
   *         was previously enabled you have to enable it again after calling this
   *         function.
   * @param  __STATE__ specifies the new state of the HSE.
   *          This parameter can be one of the following values:
-  *            @arg RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
+  *            @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
   *                              6 HSE oscillator clock cycles.
-  *            @arg RCC_HSE_ON turn ON the HSE oscillator
+  *            @arg @ref RCC_HSE_ON turn ON the HSE oscillator
-  *            @arg RCC_HSE_BYPASS HSE oscillator bypassed with external clock
+  *            @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
   */
 #define __HAL_RCC_HSE_CONFIG(__STATE__)                                     \
                     do{                                                     \
                       if ((__STATE__) == RCC_HSE_ON)                        \
                       {                                                     \
   * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
   *         software should wait on LSERDY flag to be set indicating that LSE clock
   *         is stable and can be used to clock the RTC.
   * @param  __STATE__ specifies the new state of the LSE.
   *         This parameter can be one of the following values:
-  *            @arg RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
+  *            @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
   *                              6 LSE oscillator clock cycles.
-  *            @arg RCC_LSE_ON turn ON the LSE oscillator.
+  *            @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
-  *            @arg RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
+  *            @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
   */
 #define __HAL_RCC_LSE_CONFIG(__STATE__)                                     \
                     do{                                                     \
                       if ((__STATE__) == RCC_LSE_ON)                        \
                       {                                                     \
 /** @brief Macro to configure the main PLL clock source and multiplication factors.
   * @note   This function must be used only when the main PLL is disabled.
+  *
   * @param  __RCC_PLLSOURCE__ specifies the PLL entry clock source.
   *          This parameter can be one of the following values:
-  *            @arg RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
-  *            @arg RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
+  *            @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
   * @param  __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
   *          This parameter can be one of the following values:
-  *             @arg RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2 (*)
+  *             @arg @ref RCC_PLL_MUL4   PLLVCO = PLL clock entry x 4
-  *             @arg RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3 (*)
+  *             @arg @ref RCC_PLL_MUL6   PLLVCO = PLL clock entry x 6
+  @if STM32F105xC
-  *             @arg RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
+  *             @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
+  @elseif STM32F107xC
-  *             @arg RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
+  *             @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
+  @else
-  *             @arg RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5 (**)
+  *             @arg @ref RCC_PLL_MUL2   PLLVCO = PLL clock entry x 2
-  *             @arg RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
+  *             @arg @ref RCC_PLL_MUL3   PLLVCO = PLL clock entry x 3
-  *             @arg RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
+  *             @arg @ref RCC_PLL_MUL10  PLLVCO = PLL clock entry x 10
-  *             @arg RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10 (*)
+  *             @arg @ref RCC_PLL_MUL11  PLLVCO = PLL clock entry x 11
-  *             @arg RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11 (*)
+  *             @arg @ref RCC_PLL_MUL12  PLLVCO = PLL clock entry x 12
-  *             @arg RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12 (*)
+  *             @arg @ref RCC_PLL_MUL13  PLLVCO = PLL clock entry x 13
-  *             @arg RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13 (*)
+  *             @arg @ref RCC_PLL_MUL14  PLLVCO = PLL clock entry x 14
-  *             @arg RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14 (*)
+  *             @arg @ref RCC_PLL_MUL15  PLLVCO = PLL clock entry x 15
-  *             @arg RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15 (*)
+  *             @arg @ref RCC_PLL_MUL16  PLLVCO = PLL clock entry x 16
+  @endif
-  *             @arg RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16 (*)
+  *             @arg @ref RCC_PLL_MUL8   PLLVCO = PLL clock entry x 8
-  * @note (*) These values are not available in STM32F105xx & STM32F107xx devices.
+  *             @arg @ref RCC_PLL_MUL9   PLLVCO = PLL clock entry x 9
-  * @note (**) This value is available in STM32F105xx & STM32F107xx devices only.
+  *
   */
 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
           MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
 /** @brief  Get oscillator clock selected as PLL input clock
   * @retval The clock source used for PLL entry. The returned value can be one
   *         of the following:
-  *             @arg RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
+  *             @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
-  *             @arg RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
+  *             @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
   */
 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
 /**
   * @}
   * @{
   */
 /**
   * @brief  Macro to configure the system clock source.
-  * @param  __RCC_SYSCLKSOURCE__ specifies the system clock source.
+  * @param  __SYSCLKSOURCE__ specifies the system clock source.
   *          This parameter can be one of the following values:
-  *              @arg RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
+  *              @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
-  *              @arg RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
+  *              @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
-  *              @arg RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
+  *              @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
   */
-#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) \
+#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
-                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
 /** @brief  Macro to get the clock source used as system clock.
   * @retval The clock source used as system clock. The returned value can be one
   *         of the following:
-  *             @arg RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
+  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
-  *             @arg RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
+  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
-  *             @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
+  *             @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
   */
 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
 /**
   * @}
 #if   defined(RCC_CFGR_MCO_3)
 /** @brief  Macro to configure the MCO clock.
   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
   *         This parameter can be one of the following values:
-  *            @arg RCC_MCO1SOURCE_NOCLOCK: No clock
+  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK      No clock selected as MCO clock
-  *            @arg RCC_MCO1SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_SYSCLK       System clock (SYSCLK) selected as MCO clock
-  *            @arg RCC_MCO1SOURCE_HSI: HSI selected as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_HSI          HSI selected as MCO clock
-  *            @arg RCC_MCO1SOURCE_HSE: HSE selected as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_HSE          HSE selected as MCO clock
-  *            @arg RCC_MCO1SOURCE_PLLCLK: PLL clock divided by 2 selected as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_PLLCLK       PLL clock divided by 2 selected as MCO clock
-  *            @arg RCC_MCO1SOURCE_PLL2CLK: PLL2 clock selected by 2 selected as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_PLL2CLK      PLL2 clock selected by 2 selected as MCO clock
-  *            @arg RCC_MCO1SOURCE_PLL3CLK_DIV2: PLL3 clock divided by 2 selected as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
-  *            @arg RCC_MCO1SOURCE_EXT_HSE: XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1  external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
-  *            @arg RCC_MCO1SOURCE_PLL3CLK: PLL3 clock selected (for Ethernet) as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_PLL3CLK      PLL3 clock selected (for Ethernet) as MCO clock
   * @param  __MCODIV__ specifies the MCO clock prescaler.
   *         This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: No division applied on MCO clock source
+  *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
   */
 #else
 /** @brief  Macro to configure the MCO clock.
   * @param  __MCOCLKSOURCE__ specifies the MCO clock source.
   *         This parameter can be one of the following values:
-  *            @arg RCC_MCO1SOURCE_NOCLOCK: No clock
+  *            @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
-  *            @arg RCC_MCO1SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_SYSCLK  System clock (SYSCLK) selected as MCO clock
-  *            @arg RCC_MCO1SOURCE_HSI: HSI selected as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
-  *            @arg RCC_MCO1SOURCE_HSE: HSE selected as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
-  *            @arg RCC_MCO1SOURCE_PLLCLK: PLL clock divided by 2 selected as MCO clock
+  *            @arg @ref RCC_MCO1SOURCE_PLLCLK  PLL clock divided by 2 selected as MCO clock
   * @param  __MCODIV__ specifies the MCO clock prescaler.
   *         This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: No division applied on MCO clock source
+  *            @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
   */
 #endif
 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
                  MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
   *         Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
   *         a Power On Reset (POR).
+  *
   * @param  __RTC_CLKSOURCE__ specifies the RTC clock source.
   *          This parameter can be one of the following values:
-  *             @arg RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+  *             @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+  *             @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+  *             @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
+  *             @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
   * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
   *         work in STOP and STANDBY modes, and can be used as wakeup source.
   *         However, when the HSE clock is used as RTC clock source, the RTC
   *         cannot be used in STOP and STANDBY modes.
   * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
   */
 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
 /** @brief Macro to get the RTC clock source.
   * @retval The clock source can be one of the following values:
-  *            @arg RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
-  *            @arg RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
-  *            @arg RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
-  *            @arg RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
+  *            @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
   */
 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
 /** @brief Macro to enable the the RTC clock.
   * @note   These macros must be used only after the RTC clock source was selected.
   */
 /** @brief Enable RCC interrupt.
   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
   *          This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY LSI ready interrupt
+  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
-  *            @arg RCC_IT_LSERDY LSE ready interrupt
+  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
-  *            @arg RCC_IT_HSIRDY HSI ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
-  *            @arg RCC_IT_HSERDY HSE ready interrupt
+  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
-  *            @arg RCC_IT_PLLRDY main PLL ready interrupt
+  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
+  @if STM32F105xx
-  *            @arg RCC_IT_PLL2RDY Main PLL2 ready interrupt.(*)
+  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.(*)
+  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+  @elsif STM32F107xx
+  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
+  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+  @endif
   */
 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
 /** @brief Disable RCC interrupt.
   * @param  __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
   *          This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY LSI ready interrupt
+  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt
-  *            @arg RCC_IT_LSERDY LSE ready interrupt
+  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt
-  *            @arg RCC_IT_HSIRDY HSI ready interrupt
+  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt
-  *            @arg RCC_IT_HSERDY HSE ready interrupt
+  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt
-  *            @arg RCC_IT_PLLRDY main PLL ready interrupt
+  *            @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
+  @if STM32F105xx
-  *            @arg RCC_IT_PLL2RDY Main PLL2 ready interrupt.(*)
+  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.(*)
+  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+  @elsif STM32F107xx
+  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
+  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+  @endif
   */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
 /** @brief Clear the RCC's interrupt pending bits.
   * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
   *          This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY LSI ready interrupt.
+  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY LSE ready interrupt.
+  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY HSI ready interrupt.
+  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY HSE ready interrupt.
+  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY Main PLL ready interrupt.
+  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
+  @if STM32F105xx
-  *            @arg RCC_IT_PLL2RDY Main PLL2 ready interrupt.(*)
+  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.(*)
+  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+  @elsif STM32F107xx
-  *            @arg RCC_IT_CSS Clock Security System interrupt
+  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
+  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+  @endif
+  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
   */
 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
 /** @brief Check the RCC's interrupt has occurred or not.
   * @param  __INTERRUPT__ specifies the RCC interrupt source to check.
   *          This parameter can be one of the following values:
-  *            @arg RCC_IT_LSIRDY LSI ready interrupt.
+  *            @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY LSE ready interrupt.
+  *            @arg @ref RCC_IT_LSERDY LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY HSI ready interrupt.
+  *            @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY HSE ready interrupt.
+  *            @arg @ref RCC_IT_HSERDY HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY Main PLL ready interrupt.
+  *            @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
+  @if STM32F105xx
-  *            @arg RCC_IT_PLL2RDY Main PLL2 ready interrupt.(*)
+  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  *            @arg RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.(*)
+  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+  @elsif STM32F107xx
-  *            @arg RCC_IT_CSS Clock Security System interrupt
+  *            @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
-  * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
+  *            @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
+  @endif
+  *            @arg @ref RCC_IT_CSS Clock Security System interrupt
   * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
   */
 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
 /** @brief Set RMVF bit to clear the reset flags.
 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
 /** @brief  Check RCC flag is set or not.
   * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be one of the following values:
-  *            @arg RCC_FLAG_HSIRDY HSI oscillator clock ready.
+  *            @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
-  *            @arg RCC_FLAG_HSERDY HSE oscillator clock ready.
+  *            @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
-  *            @arg RCC_FLAG_PLLRDY Main PLL clock ready.
+  *            @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
+  @if STM32F105xx
+  *            @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
+  *            @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
+  @elsif STM32F107xx
-  *            @arg RCC_FLAG_PLL2RDY Main PLL2 clock ready.(*)
+  *            @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
-  *            @arg RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.(*)
+  *            @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
+  @endif
-  *            @arg RCC_FLAG_LSERDY LSE oscillator clock ready.
+  *            @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
-  *            @arg RCC_FLAG_LSIRDY LSI oscillator clock ready.
+  *            @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
-  *            @arg RCC_FLAG_PINRST Pin reset.
+  *            @arg @ref RCC_FLAG_PINRST  Pin reset.
-  *            @arg RCC_FLAG_PORRST POR/PDR reset.
+  *            @arg @ref RCC_FLAG_PORRST  POR/PDR reset.
-  *            @arg RCC_FLAG_SFTRST Software reset.
+  *            @arg @ref RCC_FLAG_SFTRST  Software reset.
-  *            @arg RCC_FLAG_IWDGRST Independent Watchdog reset.
+  *            @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
-  *            @arg RCC_FLAG_WWDGRST Window Watchdog reset.
+  *            @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
-  *            @arg RCC_FLAG_LPWRRST Low Power reset.
+  *            @arg @ref RCC_FLAG_LPWRRST Low Power reset.
-  * @note (*) This bit is available in STM32F105xx & STM32F107xx devices only.
   * @retval The new state of __FLAG__ (TRUE or FALSE).
   */
 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)?   RCC->CR   : \
                                       ((((__FLAG__) >> 5) == BDCR_REG_INDEX)? RCC->BDCR : \
-                                                                             RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
+                                                                              RCC->CSR)) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
 /**
   * @}
   */

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(root)/trunk/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_rcc.h – Rev 2 → 5