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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_hal_gpio_ex.h |
3 | * @file stm32f1xx_hal_gpio_ex.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of GPIO HAL Extension module. |
5 | * @brief Header file of GPIO HAL Extension module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef STM32F1xx_HAL_GPIO_EX_H |
| 21 | #ifndef STM32F1xx_HAL_GPIO_EX_H |
21 | #define STM32F1xx_HAL_GPIO_EX_H |
| 22 | #define STM32F1xx_HAL_GPIO_EX_H |
22 | |
| 23 | 23 | #ifdef __cplusplus |
|
| 24 | #ifdef __cplusplus |
24 | extern "C" { |
| 25 | extern "C" { |
25 | #endif |
| 26 | #endif |
26 | |
| 27 | 27 | /* Includes ------------------------------------------------------------------*/ |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | #include "stm32f1xx_hal_def.h" |
| 29 | #include "stm32f1xx_hal_def.h" |
29 | |
| 30 | 30 | /** @addtogroup STM32F1xx_HAL_Driver |
|
| 31 | /** @addtogroup STM32F1xx_HAL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | /** @defgroup GPIOEx GPIOEx |
|
| 35 | /** @defgroup GPIOEx GPIOEx |
35 | * @{ |
| 36 | * @{ |
36 | */ |
| 37 | */ |
37 | /* Exported types ------------------------------------------------------------*/ |
| 38 | /* Exported types ------------------------------------------------------------*/ |
38 | /* Exported constants --------------------------------------------------------*/ |
| 39 | /* Exported constants --------------------------------------------------------*/ |
39 | |
| 40 | 40 | /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants |
|
| 41 | /** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants |
41 | * @{ |
| 42 | * @{ |
42 | */ |
| 43 | */ |
43 | |
| 44 | 44 | /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration |
|
| 45 | /** @defgroup GPIOEx_EVENTOUT EVENTOUT Cortex Configuration |
45 | * @brief This section propose definition to use the Cortex EVENTOUT signal. |
| 46 | * @brief This section propose definition to use the Cortex EVENTOUT signal. |
46 | * @{ |
| 47 | * @{ |
47 | */ |
| 48 | */ |
48 | |
| 49 | 49 | /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin |
|
| 50 | /** @defgroup GPIOEx_EVENTOUT_PIN EVENTOUT Pin |
50 | * @{ |
| 51 | * @{ |
51 | */ |
| 52 | */ |
52 | |
| 53 | 53 | #define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ |
|
| 54 | #define AFIO_EVENTOUT_PIN_0 AFIO_EVCR_PIN_PX0 /*!< EVENTOUT on pin 0 */ |
54 | #define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ |
| 55 | #define AFIO_EVENTOUT_PIN_1 AFIO_EVCR_PIN_PX1 /*!< EVENTOUT on pin 1 */ |
55 | #define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ |
| 56 | #define AFIO_EVENTOUT_PIN_2 AFIO_EVCR_PIN_PX2 /*!< EVENTOUT on pin 2 */ |
56 | #define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ |
| 57 | #define AFIO_EVENTOUT_PIN_3 AFIO_EVCR_PIN_PX3 /*!< EVENTOUT on pin 3 */ |
57 | #define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ |
| 58 | #define AFIO_EVENTOUT_PIN_4 AFIO_EVCR_PIN_PX4 /*!< EVENTOUT on pin 4 */ |
58 | #define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ |
| 59 | #define AFIO_EVENTOUT_PIN_5 AFIO_EVCR_PIN_PX5 /*!< EVENTOUT on pin 5 */ |
59 | #define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ |
| 60 | #define AFIO_EVENTOUT_PIN_6 AFIO_EVCR_PIN_PX6 /*!< EVENTOUT on pin 6 */ |
60 | #define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ |
| 61 | #define AFIO_EVENTOUT_PIN_7 AFIO_EVCR_PIN_PX7 /*!< EVENTOUT on pin 7 */ |
61 | #define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ |
| 62 | #define AFIO_EVENTOUT_PIN_8 AFIO_EVCR_PIN_PX8 /*!< EVENTOUT on pin 8 */ |
62 | #define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ |
| 63 | #define AFIO_EVENTOUT_PIN_9 AFIO_EVCR_PIN_PX9 /*!< EVENTOUT on pin 9 */ |
63 | #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ |
| 64 | #define AFIO_EVENTOUT_PIN_10 AFIO_EVCR_PIN_PX10 /*!< EVENTOUT on pin 10 */ |
64 | #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ |
| 65 | #define AFIO_EVENTOUT_PIN_11 AFIO_EVCR_PIN_PX11 /*!< EVENTOUT on pin 11 */ |
65 | #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ |
| 66 | #define AFIO_EVENTOUT_PIN_12 AFIO_EVCR_PIN_PX12 /*!< EVENTOUT on pin 12 */ |
66 | #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ |
| 67 | #define AFIO_EVENTOUT_PIN_13 AFIO_EVCR_PIN_PX13 /*!< EVENTOUT on pin 13 */ |
67 | #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ |
| 68 | #define AFIO_EVENTOUT_PIN_14 AFIO_EVCR_PIN_PX14 /*!< EVENTOUT on pin 14 */ |
68 | #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ |
| 69 | #define AFIO_EVENTOUT_PIN_15 AFIO_EVCR_PIN_PX15 /*!< EVENTOUT on pin 15 */ |
69 | |
| 70 | 70 | #define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \ |
|
| 71 | #define IS_AFIO_EVENTOUT_PIN(__PIN__) (((__PIN__) == AFIO_EVENTOUT_PIN_0) || \ |
71 | ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \ |
| 72 | ((__PIN__) == AFIO_EVENTOUT_PIN_1) || \ |
72 | ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \ |
| 73 | ((__PIN__) == AFIO_EVENTOUT_PIN_2) || \ |
73 | ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \ |
| 74 | ((__PIN__) == AFIO_EVENTOUT_PIN_3) || \ |
74 | ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \ |
| 75 | ((__PIN__) == AFIO_EVENTOUT_PIN_4) || \ |
75 | ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \ |
| 76 | ((__PIN__) == AFIO_EVENTOUT_PIN_5) || \ |
76 | ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \ |
| 77 | ((__PIN__) == AFIO_EVENTOUT_PIN_6) || \ |
77 | ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \ |
| 78 | ((__PIN__) == AFIO_EVENTOUT_PIN_7) || \ |
78 | ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \ |
| 79 | ((__PIN__) == AFIO_EVENTOUT_PIN_8) || \ |
79 | ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \ |
| 80 | ((__PIN__) == AFIO_EVENTOUT_PIN_9) || \ |
80 | ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \ |
| 81 | ((__PIN__) == AFIO_EVENTOUT_PIN_10) || \ |
81 | ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \ |
| 82 | ((__PIN__) == AFIO_EVENTOUT_PIN_11) || \ |
82 | ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \ |
| 83 | ((__PIN__) == AFIO_EVENTOUT_PIN_12) || \ |
83 | ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \ |
| 84 | ((__PIN__) == AFIO_EVENTOUT_PIN_13) || \ |
84 | ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \ |
| 85 | ((__PIN__) == AFIO_EVENTOUT_PIN_14) || \ |
85 | ((__PIN__) == AFIO_EVENTOUT_PIN_15)) |
| 86 | ((__PIN__) == AFIO_EVENTOUT_PIN_15)) |
86 | /** |
| 87 | /** |
87 | * @} |
| 88 | * @} |
88 | */ |
| 89 | */ |
89 | |
| 90 | 90 | /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port |
|
| 91 | /** @defgroup GPIOEx_EVENTOUT_PORT EVENTOUT Port |
91 | * @{ |
| 92 | * @{ |
92 | */ |
| 93 | */ |
93 | |
| 94 | 94 | #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ |
|
| 95 | #define AFIO_EVENTOUT_PORT_A AFIO_EVCR_PORT_PA /*!< EVENTOUT on port A */ |
95 | #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ |
| 96 | #define AFIO_EVENTOUT_PORT_B AFIO_EVCR_PORT_PB /*!< EVENTOUT on port B */ |
96 | #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ |
| 97 | #define AFIO_EVENTOUT_PORT_C AFIO_EVCR_PORT_PC /*!< EVENTOUT on port C */ |
97 | #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ |
| 98 | #define AFIO_EVENTOUT_PORT_D AFIO_EVCR_PORT_PD /*!< EVENTOUT on port D */ |
98 | #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ |
| 99 | #define AFIO_EVENTOUT_PORT_E AFIO_EVCR_PORT_PE /*!< EVENTOUT on port E */ |
99 | |
| 100 | 100 | #define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \ |
|
| 101 | #define IS_AFIO_EVENTOUT_PORT(__PORT__) (((__PORT__) == AFIO_EVENTOUT_PORT_A) || \ |
101 | ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \ |
| 102 | ((__PORT__) == AFIO_EVENTOUT_PORT_B) || \ |
102 | ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \ |
| 103 | ((__PORT__) == AFIO_EVENTOUT_PORT_C) || \ |
103 | ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \ |
| 104 | ((__PORT__) == AFIO_EVENTOUT_PORT_D) || \ |
104 | ((__PORT__) == AFIO_EVENTOUT_PORT_E)) |
| 105 | ((__PORT__) == AFIO_EVENTOUT_PORT_E)) |
105 | /** |
| 106 | /** |
106 | * @} |
| 107 | * @} |
107 | */ |
| 108 | */ |
108 | |
| 109 | 109 | /** |
|
| 110 | /** |
110 | * @} |
| 111 | * @} |
111 | */ |
| 112 | */ |
112 | |
| 113 | 113 | /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping |
|
| 114 | /** @defgroup GPIOEx_AFIO_AF_REMAPPING Alternate Function Remapping |
114 | * @brief This section propose definition to remap the alternate function to some other port/pins. |
| 115 | * @brief This section propose definition to remap the alternate function to some other port/pins. |
115 | * @{ |
| 116 | * @{ |
116 | */ |
| 117 | */ |
117 | |
| 118 | 118 | /** |
|
| 119 | /** |
119 | * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
| 120 | * @brief Enable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
120 | * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) |
| 121 | * @note ENABLE: Remap (NSS/PA15, SCK/PB3, MISO/PB4, MOSI/PB5) |
121 | * @retval None |
| 122 | * @retval None |
122 | */ |
| 123 | */ |
123 | #define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP) |
| 124 | #define __HAL_AFIO_REMAP_SPI1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI1_REMAP) |
124 | |
| 125 | 125 | /** |
|
| 126 | /** |
126 | * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
| 127 | * @brief Disable the remapping of SPI1 alternate function NSS, SCK, MISO and MOSI. |
127 | * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) |
| 128 | * @note DISABLE: No remap (NSS/PA4, SCK/PA5, MISO/PA6, MOSI/PA7) |
128 | * @retval None |
| 129 | * @retval None |
129 | */ |
| 130 | */ |
130 | #define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP) |
| 131 | #define __HAL_AFIO_REMAP_SPI1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI1_REMAP) |
131 | |
| 132 | 132 | /** |
|
| 133 | /** |
133 | * @brief Enable the remapping of I2C1 alternate function SCL and SDA. |
| 134 | * @brief Enable the remapping of I2C1 alternate function SCL and SDA. |
134 | * @note ENABLE: Remap (SCL/PB8, SDA/PB9) |
| 135 | * @note ENABLE: Remap (SCL/PB8, SDA/PB9) |
135 | * @retval None |
| 136 | * @retval None |
136 | */ |
| 137 | */ |
137 | #define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP) |
| 138 | #define __HAL_AFIO_REMAP_I2C1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_I2C1_REMAP) |
138 | |
| 139 | 139 | /** |
|
| 140 | /** |
140 | * @brief Disable the remapping of I2C1 alternate function SCL and SDA. |
| 141 | * @brief Disable the remapping of I2C1 alternate function SCL and SDA. |
141 | * @note DISABLE: No remap (SCL/PB6, SDA/PB7) |
| 142 | * @note DISABLE: No remap (SCL/PB6, SDA/PB7) |
142 | * @retval None |
| 143 | * @retval None |
143 | */ |
| 144 | */ |
144 | #define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP) |
| 145 | #define __HAL_AFIO_REMAP_I2C1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_I2C1_REMAP) |
145 | |
| 146 | 146 | /** |
|
| 147 | /** |
147 | * @brief Enable the remapping of USART1 alternate function TX and RX. |
| 148 | * @brief Enable the remapping of USART1 alternate function TX and RX. |
148 | * @note ENABLE: Remap (TX/PB6, RX/PB7) |
| 149 | * @note ENABLE: Remap (TX/PB6, RX/PB7) |
149 | * @retval None |
| 150 | * @retval None |
150 | */ |
| 151 | */ |
151 | #define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP) |
| 152 | #define __HAL_AFIO_REMAP_USART1_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART1_REMAP) |
152 | |
| 153 | 153 | /** |
|
| 154 | /** |
154 | * @brief Disable the remapping of USART1 alternate function TX and RX. |
| 155 | * @brief Disable the remapping of USART1 alternate function TX and RX. |
155 | * @note DISABLE: No remap (TX/PA9, RX/PA10) |
| 156 | * @note DISABLE: No remap (TX/PA9, RX/PA10) |
156 | * @retval None |
| 157 | * @retval None |
157 | */ |
| 158 | */ |
158 | #define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP) |
| 159 | #define __HAL_AFIO_REMAP_USART1_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART1_REMAP) |
159 | |
| 160 | 160 | /** |
|
| 161 | /** |
161 | * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
| 162 | * @brief Enable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
162 | * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) |
| 163 | * @note ENABLE: Remap (CTS/PD3, RTS/PD4, TX/PD5, RX/PD6, CK/PD7) |
163 | * @retval None |
| 164 | * @retval None |
164 | */ |
| 165 | */ |
165 | #define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP) |
| 166 | #define __HAL_AFIO_REMAP_USART2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_USART2_REMAP) |
166 | |
| 167 | 167 | /** |
|
| 168 | /** |
168 | * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
| 169 | * @brief Disable the remapping of USART2 alternate function CTS, RTS, CK, TX and RX. |
169 | * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) |
| 170 | * @note DISABLE: No remap (CTS/PA0, RTS/PA1, TX/PA2, RX/PA3, CK/PA4) |
170 | * @retval None |
| 171 | * @retval None |
171 | */ |
| 172 | */ |
172 | #define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP) |
| 173 | #define __HAL_AFIO_REMAP_USART2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_USART2_REMAP) |
173 | |
| 174 | 174 | /** |
|
| 175 | /** |
175 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| 176 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
176 | * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) |
| 177 | * @note ENABLE: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) |
177 | * @retval None |
| 178 | * @retval None |
178 | */ |
| 179 | */ |
179 | #define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
| 180 | #define __HAL_AFIO_REMAP_USART3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_FULLREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
180 | |
| 181 | 181 | /** |
|
| 182 | /** |
182 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| 183 | * @brief Enable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
183 | * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) |
| 184 | * @note PARTIAL: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) |
184 | * @retval None |
| 185 | * @retval None |
185 | */ |
| 186 | */ |
186 | #define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
| 187 | #define __HAL_AFIO_REMAP_USART3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_PARTIALREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
187 | |
| 188 | 188 | /** |
|
| 189 | /** |
189 | * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
| 190 | * @brief Disable the remapping of USART3 alternate function CTS, RTS, CK, TX and RX. |
190 | * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) |
| 191 | * @note DISABLE: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) |
191 | * @retval None |
| 192 | * @retval None |
192 | */ |
| 193 | */ |
193 | #define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
| 194 | #define __HAL_AFIO_REMAP_USART3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_USART3_REMAP_NOREMAP, AFIO_MAPR_USART3_REMAP_FULLREMAP) |
194 | |
| 195 | 195 | /** |
|
| 196 | /** |
196 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| 197 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
197 | * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) |
| 198 | * @note ENABLE: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) |
198 | * @retval None |
| 199 | * @retval None |
199 | */ |
| 200 | */ |
200 | #define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
| 201 | #define __HAL_AFIO_REMAP_TIM1_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_FULLREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
201 | |
| 202 | 202 | /** |
|
| 203 | /** |
203 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| 204 | * @brief Enable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
204 | * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) |
| 205 | * @note PARTIAL: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) |
205 | * @retval None |
| 206 | * @retval None |
206 | */ |
| 207 | */ |
207 | #define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
| 208 | #define __HAL_AFIO_REMAP_TIM1_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_PARTIALREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
208 | |
| 209 | 209 | /** |
|
| 210 | /** |
210 | * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
| 211 | * @brief Disable the remapping of TIM1 alternate function channels 1 to 4, 1N to 3N, external trigger (ETR) and Break input (BKIN) |
211 | * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) |
| 212 | * @note DISABLE: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) |
212 | * @retval None |
| 213 | * @retval None |
213 | */ |
| 214 | */ |
214 | #define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
| 215 | #define __HAL_AFIO_REMAP_TIM1_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM1_REMAP_NOREMAP, AFIO_MAPR_TIM1_REMAP_FULLREMAP) |
215 | |
| 216 | 216 | /** |
|
| 217 | /** |
217 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| 218 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
218 | * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) |
| 219 | * @note ENABLE: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) |
219 | * @retval None |
| 220 | * @retval None |
220 | */ |
| 221 | */ |
221 | #define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
| 222 | #define __HAL_AFIO_REMAP_TIM2_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_FULLREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
222 | |
| 223 | 223 | /** |
|
| 224 | /** |
224 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| 225 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
225 | * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) |
| 226 | * @note PARTIAL_2: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) |
226 | * @retval None |
| 227 | * @retval None |
227 | */ |
| 228 | */ |
228 | #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
| 229 | #define __HAL_AFIO_REMAP_TIM2_PARTIAL_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
229 | |
| 230 | 230 | /** |
|
| 231 | /** |
231 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| 232 | * @brief Enable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
232 | * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) |
| 233 | * @note PARTIAL_1: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) |
233 | * @retval None |
| 234 | * @retval None |
234 | */ |
| 235 | */ |
235 | #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
| 236 | #define __HAL_AFIO_REMAP_TIM2_PARTIAL_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
236 | |
| 237 | 237 | /** |
|
| 238 | /** |
238 | * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
| 239 | * @brief Disable the remapping of TIM2 alternate function channels 1 to 4 and external trigger (ETR) |
239 | * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) |
| 240 | * @note DISABLE: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) |
240 | * @retval None |
| 241 | * @retval None |
241 | */ |
| 242 | */ |
242 | #define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
| 243 | #define __HAL_AFIO_REMAP_TIM2_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM2_REMAP_NOREMAP, AFIO_MAPR_TIM2_REMAP_FULLREMAP) |
243 | |
| 244 | 244 | /** |
|
| 245 | /** |
245 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
| 246 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
246 | * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) |
| 247 | * @note ENABLE: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) |
247 | * @note TIM3_ETR on PE0 is not re-mapped. |
| 248 | * @note TIM3_ETR on PE0 is not re-mapped. |
248 | * @retval None |
| 249 | * @retval None |
249 | */ |
| 250 | */ |
250 | #define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
| 251 | #define __HAL_AFIO_REMAP_TIM3_ENABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_FULLREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
251 | |
| 252 | 252 | /** |
|
| 253 | /** |
253 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
| 254 | * @brief Enable the remapping of TIM3 alternate function channels 1 to 4 |
254 | * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) |
| 255 | * @note PARTIAL: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) |
255 | * @note TIM3_ETR on PE0 is not re-mapped. |
| 256 | * @note TIM3_ETR on PE0 is not re-mapped. |
256 | * @retval None |
| 257 | * @retval None |
257 | */ |
| 258 | */ |
258 | #define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
| 259 | #define __HAL_AFIO_REMAP_TIM3_PARTIAL() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_PARTIALREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
259 | |
| 260 | 260 | /** |
|
| 261 | /** |
261 | * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 |
| 262 | * @brief Disable the remapping of TIM3 alternate function channels 1 to 4 |
262 | * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) |
| 263 | * @note DISABLE: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) |
263 | * @note TIM3_ETR on PE0 is not re-mapped. |
| 264 | * @note TIM3_ETR on PE0 is not re-mapped. |
264 | * @retval None |
| 265 | * @retval None |
265 | */ |
| 266 | */ |
266 | #define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
| 267 | #define __HAL_AFIO_REMAP_TIM3_DISABLE() AFIO_REMAP_PARTIAL(AFIO_MAPR_TIM3_REMAP_NOREMAP, AFIO_MAPR_TIM3_REMAP_FULLREMAP) |
267 | |
| 268 | 268 | /** |
|
| 269 | /** |
269 | * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. |
| 270 | * @brief Enable the remapping of TIM4 alternate function channels 1 to 4. |
270 | * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) |
| 271 | * @note ENABLE: Full remap (TIM4_CH1/PD12, TIM4_CH2/PD13, TIM4_CH3/PD14, TIM4_CH4/PD15) |
271 | * @note TIM4_ETR on PE0 is not re-mapped. |
| 272 | * @note TIM4_ETR on PE0 is not re-mapped. |
272 | * @retval None |
| 273 | * @retval None |
273 | */ |
| 274 | */ |
274 | #define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP) |
| 275 | #define __HAL_AFIO_REMAP_TIM4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM4_REMAP) |
275 | |
| 276 | 276 | /** |
|
| 277 | /** |
277 | * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. |
| 278 | * @brief Disable the remapping of TIM4 alternate function channels 1 to 4. |
278 | * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) |
| 279 | * @note DISABLE: No remap (TIM4_CH1/PB6, TIM4_CH2/PB7, TIM4_CH3/PB8, TIM4_CH4/PB9) |
279 | * @note TIM4_ETR on PE0 is not re-mapped. |
| 280 | * @note TIM4_ETR on PE0 is not re-mapped. |
280 | * @retval None |
| 281 | * @retval None |
281 | */ |
| 282 | */ |
282 | #define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP) |
| 283 | #define __HAL_AFIO_REMAP_TIM4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM4_REMAP) |
283 | |
| 284 | 284 | #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) |
|
| 285 | #if defined(AFIO_MAPR_CAN_REMAP_REMAP1) |
285 | |
| 286 | 286 | /** |
|
| 287 | /** |
287 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| 288 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
288 | * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 |
| 289 | * @note CASE 1: CAN_RX mapped to PA11, CAN_TX mapped to PA12 |
289 | * @retval None |
| 290 | * @retval None |
290 | */ |
| 291 | */ |
291 | #define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP) |
| 292 | #define __HAL_AFIO_REMAP_CAN1_1() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP1, AFIO_MAPR_CAN_REMAP) |
292 | |
| 293 | 293 | /** |
|
| 294 | /** |
294 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| 295 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
295 | * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) |
| 296 | * @note CASE 2: CAN_RX mapped to PB8, CAN_TX mapped to PB9 (not available on 36-pin package) |
296 | * @retval None |
| 297 | * @retval None |
297 | */ |
| 298 | */ |
298 | #define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP) |
| 299 | #define __HAL_AFIO_REMAP_CAN1_2() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP2, AFIO_MAPR_CAN_REMAP) |
299 | |
| 300 | 300 | /** |
|
| 301 | /** |
301 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
| 302 | * @brief Enable or disable the remapping of CAN alternate function CAN_RX and CAN_TX in devices with a single CAN interface. |
302 | * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 |
| 303 | * @note CASE 3: CAN_RX mapped to PD0, CAN_TX mapped to PD1 |
303 | * @retval None |
| 304 | * @retval None |
304 | */ |
| 305 | */ |
305 | #define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP) |
| 306 | #define __HAL_AFIO_REMAP_CAN1_3() AFIO_REMAP_PARTIAL(AFIO_MAPR_CAN_REMAP_REMAP3, AFIO_MAPR_CAN_REMAP) |
306 | |
| 307 | 307 | #endif |
|
| 308 | #endif |
308 | |
| 309 | 309 | /** |
|
| 310 | /** |
310 | * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used |
| 311 | * @brief Enable the remapping of PD0 and PD1. When the HSE oscillator is not used |
311 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
| 312 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
312 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
| 313 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
313 | * on 100-pin and 144-pin packages, no need for remapping). |
| 314 | * on 100-pin and 144-pin packages, no need for remapping). |
314 | * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. |
| 315 | * @note ENABLE: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT. |
315 | * @retval None |
| 316 | * @retval None |
316 | */ |
| 317 | */ |
317 | #define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP) |
| 318 | #define __HAL_AFIO_REMAP_PD01_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PD01_REMAP) |
318 | |
| 319 | 319 | /** |
|
| 320 | /** |
320 | * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used |
| 321 | * @brief Disable the remapping of PD0 and PD1. When the HSE oscillator is not used |
321 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
| 322 | * (application running on internal 8 MHz RC) PD0 and PD1 can be mapped on OSC_IN and |
322 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
| 323 | * OSC_OUT. This is available only on 36, 48 and 64 pins packages (PD0 and PD1 are available |
323 | * on 100-pin and 144-pin packages, no need for remapping). |
| 324 | * on 100-pin and 144-pin packages, no need for remapping). |
324 | * @note DISABLE: No remapping of PD0 and PD1 |
| 325 | * @note DISABLE: No remapping of PD0 and PD1 |
325 | * @retval None |
| 326 | * @retval None |
326 | */ |
| 327 | */ |
327 | #define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP) |
| 328 | #define __HAL_AFIO_REMAP_PD01_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PD01_REMAP) |
328 | |
| 329 | 329 | #if defined(AFIO_MAPR_TIM5CH4_IREMAP) |
|
| 330 | #if defined(AFIO_MAPR_TIM5CH4_IREMAP) |
330 | /** |
| 331 | /** |
331 | * @brief Enable the remapping of TIM5CH4. |
| 332 | * @brief Enable the remapping of TIM5CH4. |
332 | * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. |
| 333 | * @note ENABLE: LSI internal clock is connected to TIM5_CH4 input for calibration purpose. |
333 | * @note This function is available only in high density value line devices. |
| 334 | * @note This function is available only in high density value line devices. |
334 | * @retval None |
| 335 | * @retval None |
335 | */ |
| 336 | */ |
336 | #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP) |
| 337 | #define __HAL_AFIO_REMAP_TIM5CH4_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM5CH4_IREMAP) |
337 | |
| 338 | 338 | /** |
|
| 339 | /** |
339 | * @brief Disable the remapping of TIM5CH4. |
| 340 | * @brief Disable the remapping of TIM5CH4. |
340 | * @note DISABLE: TIM5_CH4 is connected to PA3 |
| 341 | * @note DISABLE: TIM5_CH4 is connected to PA3 |
341 | * @note This function is available only in high density value line devices. |
| 342 | * @note This function is available only in high density value line devices. |
342 | * @retval None |
| 343 | * @retval None |
343 | */ |
| 344 | */ |
344 | #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP) |
| 345 | #define __HAL_AFIO_REMAP_TIM5CH4_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM5CH4_IREMAP) |
345 | #endif |
| 346 | #endif |
346 | |
| 347 | 347 | #if defined(AFIO_MAPR_ETH_REMAP) |
|
| 348 | #if defined(AFIO_MAPR_ETH_REMAP) |
348 | /** |
| 349 | /** |
349 | * @brief Enable the remapping of Ethernet MAC connections with the PHY. |
| 350 | * @brief Enable the remapping of Ethernet MAC connections with the PHY. |
350 | * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) |
| 351 | * @note ENABLE: Remap (RX_DV-CRS_DV/PD8, RXD0/PD9, RXD1/PD10, RXD2/PD11, RXD3/PD12) |
351 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 352 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
352 | * @retval None |
| 353 | * @retval None |
353 | */ |
| 354 | */ |
354 | #define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP) |
| 355 | #define __HAL_AFIO_REMAP_ETH_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ETH_REMAP) |
355 | |
| 356 | 356 | /** |
|
| 357 | /** |
357 | * @brief Disable the remapping of Ethernet MAC connections with the PHY. |
| 358 | * @brief Disable the remapping of Ethernet MAC connections with the PHY. |
358 | * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) |
| 359 | * @note DISABLE: No remap (RX_DV-CRS_DV/PA7, RXD0/PC4, RXD1/PC5, RXD2/PB0, RXD3/PB1) |
359 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 360 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
360 | * @retval None |
| 361 | * @retval None |
361 | */ |
| 362 | */ |
362 | #define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP) |
| 363 | #define __HAL_AFIO_REMAP_ETH_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ETH_REMAP) |
363 | #endif |
| 364 | #endif |
364 | |
| 365 | 365 | #if defined(AFIO_MAPR_CAN2_REMAP) |
|
| 366 | #if defined(AFIO_MAPR_CAN2_REMAP) |
366 | |
| 367 | 367 | /** |
|
| 368 | /** |
368 | * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
| 369 | * @brief Enable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
369 | * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) |
| 370 | * @note ENABLE: Remap (CAN2_RX/PB5, CAN2_TX/PB6) |
370 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 371 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
371 | * @retval None |
| 372 | * @retval None |
372 | */ |
| 373 | */ |
373 | #define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP) |
| 374 | #define __HAL_AFIO_REMAP_CAN2_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_CAN2_REMAP) |
374 | |
| 375 | 375 | /** |
|
| 376 | /** |
376 | * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
| 377 | * @brief Disable the remapping of CAN2 alternate function CAN2_RX and CAN2_TX. |
377 | * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) |
| 378 | * @note DISABLE: No remap (CAN2_RX/PB12, CAN2_TX/PB13) |
378 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 379 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
379 | * @retval None |
| 380 | * @retval None |
380 | */ |
| 381 | */ |
381 | #define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP) |
| 382 | #define __HAL_AFIO_REMAP_CAN2_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_CAN2_REMAP) |
382 | #endif |
| 383 | #endif |
383 | |
| 384 | 384 | #if defined(AFIO_MAPR_MII_RMII_SEL) |
|
| 385 | #if defined(AFIO_MAPR_MII_RMII_SEL) |
385 | /** |
| 386 | /** |
386 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
| 387 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
387 | * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY |
| 388 | * @note ETH_RMII: Configure Ethernet MAC for connection with an RMII PHY |
388 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 389 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
389 | * @retval None |
| 390 | * @retval None |
390 | */ |
| 391 | */ |
391 | #define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL) |
| 392 | #define __HAL_AFIO_ETH_RMII() AFIO_REMAP_ENABLE(AFIO_MAPR_MII_RMII_SEL) |
392 | |
| 393 | 393 | /** |
|
| 394 | /** |
394 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
| 395 | * @brief Configures the Ethernet MAC internally for use with an external MII or RMII PHY. |
395 | * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY |
| 396 | * @note ETH_MII: Configure Ethernet MAC for connection with an MII PHY |
396 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 397 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
397 | * @retval None |
| 398 | * @retval None |
398 | */ |
| 399 | */ |
399 | #define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL) |
| 400 | #define __HAL_AFIO_ETH_MII() AFIO_REMAP_DISABLE(AFIO_MAPR_MII_RMII_SEL) |
400 | #endif |
| 401 | #endif |
401 | |
| 402 | 402 | /** |
|
| 403 | /** |
403 | * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
| 404 | * @brief Enable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
404 | * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. |
| 405 | * @note ENABLE: ADC1 External Event injected conversion is connected to TIM8 Channel4. |
405 | * @retval None |
| 406 | * @retval None |
406 | */ |
| 407 | */ |
407 | #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
| 408 | #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
408 | |
| 409 | 409 | /** |
|
| 410 | /** |
410 | * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
| 411 | * @brief Disable the remapping of ADC1_ETRGINJ (ADC 1 External trigger injected conversion). |
411 | * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 |
| 412 | * @note DISABLE: ADC1 External trigger injected conversion is connected to EXTI15 |
412 | * @retval None |
| 413 | * @retval None |
413 | */ |
| 414 | */ |
414 | #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
| 415 | #define __HAL_AFIO_REMAP_ADC1_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGINJ_REMAP) |
415 | |
| 416 | 416 | /** |
|
| 417 | /** |
417 | * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
| 418 | * @brief Enable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
418 | * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. |
| 419 | * @note ENABLE: ADC1 External Event regular conversion is connected to TIM8 TRG0. |
419 | * @retval None |
| 420 | * @retval None |
420 | */ |
| 421 | */ |
421 | #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
| 422 | #define __HAL_AFIO_REMAP_ADC1_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
422 | |
| 423 | 423 | /** |
|
| 424 | /** |
424 | * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
| 425 | * @brief Disable the remapping of ADC1_ETRGREG (ADC 1 External trigger regular conversion). |
425 | * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 |
| 426 | * @note DISABLE: ADC1 External trigger regular conversion is connected to EXTI11 |
426 | * @retval None |
| 427 | * @retval None |
427 | */ |
| 428 | */ |
428 | #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
| 429 | #define __HAL_AFIO_REMAP_ADC1_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC1_ETRGREG_REMAP) |
429 | |
| 430 | 430 | #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
|
| 431 | #if defined(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
431 | |
| 432 | 432 | /** |
|
| 433 | /** |
433 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
| 434 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
434 | * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. |
| 435 | * @note ENABLE: ADC2 External Event injected conversion is connected to TIM8 Channel4. |
435 | * @retval None |
| 436 | * @retval None |
436 | */ |
| 437 | */ |
437 | #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
| 438 | #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
438 | |
| 439 | 439 | /** |
|
| 440 | /** |
440 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
| 441 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger injected conversion). |
441 | * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 |
| 442 | * @note DISABLE: ADC2 External trigger injected conversion is connected to EXTI15 |
442 | * @retval None |
| 443 | * @retval None |
443 | */ |
| 444 | */ |
444 | #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
| 445 | #define __HAL_AFIO_REMAP_ADC2_ETRGINJ_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGINJ_REMAP) |
445 | #endif |
| 446 | #endif |
446 | |
| 447 | 447 | #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) |
|
| 448 | #if defined (AFIO_MAPR_ADC2_ETRGREG_REMAP) |
448 | |
| 449 | 449 | /** |
|
| 450 | /** |
450 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| 451 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
451 | * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. |
| 452 | * @note ENABLE: ADC2 External Event regular conversion is connected to TIM8 TRG0. |
452 | * @retval None |
| 453 | * @retval None |
453 | */ |
| 454 | */ |
454 | #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) |
| 455 | #define __HAL_AFIO_REMAP_ADC2_ETRGREG_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) |
455 | |
| 456 | 456 | /** |
|
| 457 | /** |
457 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| 458 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
458 | * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 |
| 459 | * @note DISABLE: ADC2 External trigger regular conversion is connected to EXTI11 |
459 | * @retval None |
| 460 | * @retval None |
460 | */ |
| 461 | */ |
461 | #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) |
| 462 | #define __HAL_AFIO_REMAP_ADC2_ETRGREG_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_ADC2_ETRGREG_REMAP) |
462 | #endif |
| 463 | #endif |
463 | |
| 464 | 464 | /** |
|
| 465 | /** |
465 | * @brief Enable the Serial wire JTAG configuration |
| 466 | * @brief Enable the Serial wire JTAG configuration |
466 | * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State |
| 467 | * @note ENABLE: Full SWJ (JTAG-DP + SW-DP): Reset State |
467 | * @retval None |
| 468 | * @retval None |
468 | */ |
| 469 | */ |
469 | #define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET) |
| 470 | #define __HAL_AFIO_REMAP_SWJ_ENABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_RESET) |
470 | |
| 471 | 471 | /** |
|
| 472 | /** |
472 | * @brief Enable the Serial wire JTAG configuration |
| 473 | * @brief Enable the Serial wire JTAG configuration |
473 | * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
| 474 | * @note NONJTRST: Full SWJ (JTAG-DP + SW-DP) but without NJTRST |
474 | * @retval None |
| 475 | * @retval None |
475 | */ |
| 476 | */ |
476 | #define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST) |
| 477 | #define __HAL_AFIO_REMAP_SWJ_NONJTRST() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_NOJNTRST) |
477 | |
| 478 | 478 | /** |
|
| 479 | /** |
479 | * @brief Enable the Serial wire JTAG configuration |
| 480 | * @brief Enable the Serial wire JTAG configuration |
480 | * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled |
| 481 | * @note NOJTAG: JTAG-DP Disabled and SW-DP Enabled |
481 | * @retval None |
| 482 | * @retval None |
482 | */ |
| 483 | */ |
483 | |
| 484 | 484 | #define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE) |
|
| 485 | #define __HAL_AFIO_REMAP_SWJ_NOJTAG() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_JTAGDISABLE) |
485 | |
| 486 | 486 | /** |
|
| 487 | /** |
487 | * @brief Disable the Serial wire JTAG configuration |
| 488 | * @brief Disable the Serial wire JTAG configuration |
488 | * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled |
| 489 | * @note DISABLE: JTAG-DP Disabled and SW-DP Disabled |
489 | * @retval None |
| 490 | * @retval None |
490 | */ |
| 491 | */ |
491 | #define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE) |
| 492 | #define __HAL_AFIO_REMAP_SWJ_DISABLE() AFIO_DBGAFR_CONFIG(AFIO_MAPR_SWJ_CFG_DISABLE) |
492 | |
| 493 | 493 | #if defined(AFIO_MAPR_SPI3_REMAP) |
|
| 494 | #if defined(AFIO_MAPR_SPI3_REMAP) |
494 | |
| 495 | 495 | /** |
|
| 496 | /** |
496 | * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
| 497 | * @brief Enable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
497 | * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) |
| 498 | * @note ENABLE: Remap (SPI3_NSS-I2S3_WS/PA4, SPI3_SCK-I2S3_CK/PC10, SPI3_MISO/PC11, SPI3_MOSI-I2S3_SD/PC12) |
498 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 499 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
499 | * @retval None |
| 500 | * @retval None |
500 | */ |
| 501 | */ |
501 | #define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP) |
| 502 | #define __HAL_AFIO_REMAP_SPI3_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_SPI3_REMAP) |
502 | |
| 503 | 503 | /** |
|
| 504 | /** |
504 | * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
| 505 | * @brief Disable the remapping of SPI3 alternate functions SPI3_NSS/I2S3_WS, SPI3_SCK/I2S3_CK, SPI3_MISO, SPI3_MOSI/I2S3_SD. |
505 | * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). |
| 506 | * @note DISABLE: No remap (SPI3_NSS-I2S3_WS/PA15, SPI3_SCK-I2S3_CK/PB3, SPI3_MISO/PB4, SPI3_MOSI-I2S3_SD/PB5). |
506 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 507 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
507 | * @retval None |
| 508 | * @retval None |
508 | */ |
| 509 | */ |
509 | #define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP) |
| 510 | #define __HAL_AFIO_REMAP_SPI3_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_SPI3_REMAP) |
510 | #endif |
| 511 | #endif |
511 | |
| 512 | 512 | #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) |
|
| 513 | #if defined(AFIO_MAPR_TIM2ITR1_IREMAP) |
513 | |
| 514 | 514 | /** |
|
| 515 | /** |
515 | * @brief Control of TIM2_ITR1 internal mapping. |
| 516 | * @brief Control of TIM2_ITR1 internal mapping. |
516 | * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. |
| 517 | * @note TO_USB: Connect USB OTG SOF (Start of Frame) output to TIM2_ITR1 for calibration purposes. |
517 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 518 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
518 | * @retval None |
| 519 | * @retval None |
519 | */ |
| 520 | */ |
520 | #define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP) |
| 521 | #define __HAL_AFIO_TIM2ITR1_TO_USB() AFIO_REMAP_ENABLE(AFIO_MAPR_TIM2ITR1_IREMAP) |
521 | |
| 522 | 522 | /** |
|
| 523 | /** |
523 | * @brief Control of TIM2_ITR1 internal mapping. |
| 524 | * @brief Control of TIM2_ITR1 internal mapping. |
524 | * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. |
| 525 | * @note TO_ETH: Connect TIM2_ITR1 internally to the Ethernet PTP output for calibration purposes. |
525 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 526 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
526 | * @retval None |
| 527 | * @retval None |
527 | */ |
| 528 | */ |
528 | #define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP) |
| 529 | #define __HAL_AFIO_TIM2ITR1_TO_ETH() AFIO_REMAP_DISABLE(AFIO_MAPR_TIM2ITR1_IREMAP) |
529 | #endif |
| 530 | #endif |
530 | |
| 531 | 531 | #if defined(AFIO_MAPR_PTP_PPS_REMAP) |
|
| 532 | #if defined(AFIO_MAPR_PTP_PPS_REMAP) |
532 | |
| 533 | 533 | /** |
|
| 534 | /** |
534 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| 535 | * @brief Enable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
535 | * @note ENABLE: PTP_PPS is output on PB5 pin. |
| 536 | * @note ENABLE: PTP_PPS is output on PB5 pin. |
536 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 537 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
537 | * @retval None |
| 538 | * @retval None |
538 | */ |
| 539 | */ |
539 | #define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP) |
| 540 | #define __HAL_AFIO_ETH_PTP_PPS_ENABLE() AFIO_REMAP_ENABLE(AFIO_MAPR_PTP_PPS_REMAP) |
540 | |
| 541 | 541 | /** |
|
| 542 | /** |
542 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
| 543 | * @brief Disable the remapping of ADC2_ETRGREG (ADC 2 External trigger regular conversion). |
543 | * @note DISABLE: PTP_PPS not output on PB5 pin. |
| 544 | * @note DISABLE: PTP_PPS not output on PB5 pin. |
544 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
| 545 | * @note This bit is available only in connectivity line devices and is reserved otherwise. |
545 | * @retval None |
| 546 | * @retval None |
546 | */ |
| 547 | */ |
547 | #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP) |
| 548 | #define __HAL_AFIO_ETH_PTP_PPS_DISABLE() AFIO_REMAP_DISABLE(AFIO_MAPR_PTP_PPS_REMAP) |
548 | #endif |
| 549 | #endif |
549 | |
| 550 | 550 | #if defined(AFIO_MAPR2_TIM9_REMAP) |
|
| 551 | #if defined(AFIO_MAPR2_TIM9_REMAP) |
551 | |
| 552 | 552 | /** |
|
| 553 | /** |
553 | * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. |
| 554 | * @brief Enable the remapping of TIM9_CH1 and TIM9_CH2. |
554 | * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). |
| 555 | * @note ENABLE: Remap (TIM9_CH1 on PE5 and TIM9_CH2 on PE6). |
555 | * @retval None |
| 556 | * @retval None |
556 | */ |
| 557 | */ |
557 | #define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
| 558 | #define __HAL_AFIO_REMAP_TIM9_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
558 | |
| 559 | 559 | /** |
|
| 560 | /** |
560 | * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. |
| 561 | * @brief Disable the remapping of TIM9_CH1 and TIM9_CH2. |
561 | * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). |
| 562 | * @note DISABLE: No remap (TIM9_CH1 on PA2 and TIM9_CH2 on PA3). |
562 | * @retval None |
| 563 | * @retval None |
563 | */ |
| 564 | */ |
564 | #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
| 565 | #define __HAL_AFIO_REMAP_TIM9_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM9_REMAP) |
565 | #endif |
| 566 | #endif |
566 | |
| 567 | 567 | #if defined(AFIO_MAPR2_TIM10_REMAP) |
|
| 568 | #if defined(AFIO_MAPR2_TIM10_REMAP) |
568 | |
| 569 | 569 | /** |
|
| 570 | /** |
570 | * @brief Enable the remapping of TIM10_CH1. |
| 571 | * @brief Enable the remapping of TIM10_CH1. |
571 | * @note ENABLE: Remap (TIM10_CH1 on PF6). |
| 572 | * @note ENABLE: Remap (TIM10_CH1 on PF6). |
572 | * @retval None |
| 573 | * @retval None |
573 | */ |
| 574 | */ |
574 | #define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
| 575 | #define __HAL_AFIO_REMAP_TIM10_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
575 | |
| 576 | 576 | /** |
|
| 577 | /** |
577 | * @brief Disable the remapping of TIM10_CH1. |
| 578 | * @brief Disable the remapping of TIM10_CH1. |
578 | * @note DISABLE: No remap (TIM10_CH1 on PB8). |
| 579 | * @note DISABLE: No remap (TIM10_CH1 on PB8). |
579 | * @retval None |
| 580 | * @retval None |
580 | */ |
| 581 | */ |
581 | #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
| 582 | #define __HAL_AFIO_REMAP_TIM10_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM10_REMAP) |
582 | #endif |
| 583 | #endif |
583 | |
| 584 | 584 | #if defined(AFIO_MAPR2_TIM11_REMAP) |
|
| 585 | #if defined(AFIO_MAPR2_TIM11_REMAP) |
585 | /** |
| 586 | /** |
586 | * @brief Enable the remapping of TIM11_CH1. |
| 587 | * @brief Enable the remapping of TIM11_CH1. |
587 | * @note ENABLE: Remap (TIM11_CH1 on PF7). |
| 588 | * @note ENABLE: Remap (TIM11_CH1 on PF7). |
588 | * @retval None |
| 589 | * @retval None |
589 | */ |
| 590 | */ |
590 | #define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
| 591 | #define __HAL_AFIO_REMAP_TIM11_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
591 | |
| 592 | 592 | /** |
|
| 593 | /** |
593 | * @brief Disable the remapping of TIM11_CH1. |
| 594 | * @brief Disable the remapping of TIM11_CH1. |
594 | * @note DISABLE: No remap (TIM11_CH1 on PB9). |
| 595 | * @note DISABLE: No remap (TIM11_CH1 on PB9). |
595 | * @retval None |
| 596 | * @retval None |
596 | */ |
| 597 | */ |
597 | #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
| 598 | #define __HAL_AFIO_REMAP_TIM11_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM11_REMAP) |
598 | #endif |
| 599 | #endif |
599 | |
| 600 | 600 | #if defined(AFIO_MAPR2_TIM13_REMAP) |
|
| 601 | #if defined(AFIO_MAPR2_TIM13_REMAP) |
601 | |
| 602 | 602 | /** |
|
| 603 | /** |
603 | * @brief Enable the remapping of TIM13_CH1. |
| 604 | * @brief Enable the remapping of TIM13_CH1. |
604 | * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). |
| 605 | * @note ENABLE: Remap STM32F100:(TIM13_CH1 on PF8). Others:(TIM13_CH1 on PB0). |
605 | * @retval None |
| 606 | * @retval None |
606 | */ |
| 607 | */ |
607 | #define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
| 608 | #define __HAL_AFIO_REMAP_TIM13_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
608 | |
| 609 | 609 | /** |
|
| 610 | /** |
610 | * @brief Disable the remapping of TIM13_CH1. |
| 611 | * @brief Disable the remapping of TIM13_CH1. |
611 | * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). |
| 612 | * @note DISABLE: No remap STM32F100:(TIM13_CH1 on PA6). Others:(TIM13_CH1 on PC8). |
612 | * @retval None |
| 613 | * @retval None |
613 | */ |
| 614 | */ |
614 | #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
| 615 | #define __HAL_AFIO_REMAP_TIM13_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM13_REMAP) |
615 | #endif |
| 616 | #endif |
616 | |
| 617 | 617 | #if defined(AFIO_MAPR2_TIM14_REMAP) |
|
| 618 | #if defined(AFIO_MAPR2_TIM14_REMAP) |
618 | |
| 619 | 619 | /** |
|
| 620 | /** |
620 | * @brief Enable the remapping of TIM14_CH1. |
| 621 | * @brief Enable the remapping of TIM14_CH1. |
621 | * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). |
| 622 | * @note ENABLE: Remap STM32F100:(TIM14_CH1 on PB1). Others:(TIM14_CH1 on PF9). |
622 | * @retval None |
| 623 | * @retval None |
623 | */ |
| 624 | */ |
624 | #define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
| 625 | #define __HAL_AFIO_REMAP_TIM14_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
625 | |
| 626 | 626 | /** |
|
| 627 | /** |
627 | * @brief Disable the remapping of TIM14_CH1. |
| 628 | * @brief Disable the remapping of TIM14_CH1. |
628 | * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). |
| 629 | * @note DISABLE: No remap STM32F100:(TIM14_CH1 on PC9). Others:(TIM14_CH1 on PA7). |
629 | * @retval None |
| 630 | * @retval None |
630 | */ |
| 631 | */ |
631 | #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
| 632 | #define __HAL_AFIO_REMAP_TIM14_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM14_REMAP) |
632 | #endif |
| 633 | #endif |
633 | |
| 634 | 634 | #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) |
|
| 635 | #if defined(AFIO_MAPR2_FSMC_NADV_REMAP) |
635 | |
| 636 | 636 | /** |
|
| 637 | /** |
637 | * @brief Controls the use of the optional FSMC_NADV signal. |
| 638 | * @brief Controls the use of the optional FSMC_NADV signal. |
638 | * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. |
| 639 | * @note DISCONNECTED: The NADV signal is not connected. The I/O pin can be used by another peripheral. |
639 | * @retval None |
| 640 | * @retval None |
640 | */ |
| 641 | */ |
641 | #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
| 642 | #define __HAL_AFIO_FSMCNADV_DISCONNECTED() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
642 | |
| 643 | 643 | /** |
|
| 644 | /** |
644 | * @brief Controls the use of the optional FSMC_NADV signal. |
| 645 | * @brief Controls the use of the optional FSMC_NADV signal. |
645 | * @note CONNECTED: The NADV signal is connected to the output (default). |
| 646 | * @note CONNECTED: The NADV signal is connected to the output (default). |
646 | * @retval None |
| 647 | * @retval None |
647 | */ |
| 648 | */ |
648 | #define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
| 649 | #define __HAL_AFIO_FSMCNADV_CONNECTED() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_FSMC_NADV_REMAP) |
649 | #endif |
| 650 | #endif |
650 | |
| 651 | 651 | #if defined(AFIO_MAPR2_TIM15_REMAP) |
|
| 652 | #if defined(AFIO_MAPR2_TIM15_REMAP) |
652 | |
| 653 | 653 | /** |
|
| 654 | /** |
654 | * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. |
| 655 | * @brief Enable the remapping of TIM15_CH1 and TIM15_CH2. |
655 | * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). |
| 656 | * @note ENABLE: Remap (TIM15_CH1 on PB14 and TIM15_CH2 on PB15). |
656 | * @retval None |
| 657 | * @retval None |
657 | */ |
| 658 | */ |
658 | #define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
| 659 | #define __HAL_AFIO_REMAP_TIM15_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
659 | |
| 660 | 660 | /** |
|
| 661 | /** |
661 | * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. |
| 662 | * @brief Disable the remapping of TIM15_CH1 and TIM15_CH2. |
662 | * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). |
| 663 | * @note DISABLE: No remap (TIM15_CH1 on PA2 and TIM15_CH2 on PA3). |
663 | * @retval None |
| 664 | * @retval None |
664 | */ |
| 665 | */ |
665 | #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
| 666 | #define __HAL_AFIO_REMAP_TIM15_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM15_REMAP) |
666 | #endif |
| 667 | #endif |
667 | |
| 668 | 668 | #if defined(AFIO_MAPR2_TIM16_REMAP) |
|
| 669 | #if defined(AFIO_MAPR2_TIM16_REMAP) |
669 | |
| 670 | 670 | /** |
|
| 671 | /** |
671 | * @brief Enable the remapping of TIM16_CH1. |
| 672 | * @brief Enable the remapping of TIM16_CH1. |
672 | * @note ENABLE: Remap (TIM16_CH1 on PA6). |
| 673 | * @note ENABLE: Remap (TIM16_CH1 on PA6). |
673 | * @retval None |
| 674 | * @retval None |
674 | */ |
| 675 | */ |
675 | #define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
| 676 | #define __HAL_AFIO_REMAP_TIM16_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
676 | |
| 677 | 677 | /** |
|
| 678 | /** |
678 | * @brief Disable the remapping of TIM16_CH1. |
| 679 | * @brief Disable the remapping of TIM16_CH1. |
679 | * @note DISABLE: No remap (TIM16_CH1 on PB8). |
| 680 | * @note DISABLE: No remap (TIM16_CH1 on PB8). |
680 | * @retval None |
| 681 | * @retval None |
681 | */ |
| 682 | */ |
682 | #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
| 683 | #define __HAL_AFIO_REMAP_TIM16_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM16_REMAP) |
683 | #endif |
| 684 | #endif |
684 | |
| 685 | 685 | #if defined(AFIO_MAPR2_TIM17_REMAP) |
|
| 686 | #if defined(AFIO_MAPR2_TIM17_REMAP) |
686 | |
| 687 | 687 | /** |
|
| 688 | /** |
688 | * @brief Enable the remapping of TIM17_CH1. |
| 689 | * @brief Enable the remapping of TIM17_CH1. |
689 | * @note ENABLE: Remap (TIM17_CH1 on PA7). |
| 690 | * @note ENABLE: Remap (TIM17_CH1 on PA7). |
690 | * @retval None |
| 691 | * @retval None |
691 | */ |
| 692 | */ |
692 | #define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
| 693 | #define __HAL_AFIO_REMAP_TIM17_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
693 | |
| 694 | 694 | /** |
|
| 695 | /** |
695 | * @brief Disable the remapping of TIM17_CH1. |
| 696 | * @brief Disable the remapping of TIM17_CH1. |
696 | * @note DISABLE: No remap (TIM17_CH1 on PB9). |
| 697 | * @note DISABLE: No remap (TIM17_CH1 on PB9). |
697 | * @retval None |
| 698 | * @retval None |
698 | */ |
| 699 | */ |
699 | #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
| 700 | #define __HAL_AFIO_REMAP_TIM17_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM17_REMAP) |
700 | #endif |
| 701 | #endif |
701 | |
| 702 | 702 | #if defined(AFIO_MAPR2_CEC_REMAP) |
|
| 703 | #if defined(AFIO_MAPR2_CEC_REMAP) |
703 | |
| 704 | 704 | /** |
|
| 705 | /** |
705 | * @brief Enable the remapping of CEC. |
| 706 | * @brief Enable the remapping of CEC. |
706 | * @note ENABLE: Remap (CEC on PB10). |
| 707 | * @note ENABLE: Remap (CEC on PB10). |
707 | * @retval None |
| 708 | * @retval None |
708 | */ |
| 709 | */ |
709 | #define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
| 710 | #define __HAL_AFIO_REMAP_CEC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
710 | |
| 711 | 711 | /** |
|
| 712 | /** |
712 | * @brief Disable the remapping of CEC. |
| 713 | * @brief Disable the remapping of CEC. |
713 | * @note DISABLE: No remap (CEC on PB8). |
| 714 | * @note DISABLE: No remap (CEC on PB8). |
714 | * @retval None |
| 715 | * @retval None |
715 | */ |
| 716 | */ |
716 | #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
| 717 | #define __HAL_AFIO_REMAP_CEC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_CEC_REMAP) |
717 | #endif |
| 718 | #endif |
718 | |
| 719 | 719 | #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) |
|
| 720 | #if defined(AFIO_MAPR2_TIM1_DMA_REMAP) |
720 | |
| 721 | 721 | /** |
|
| 722 | /** |
722 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
| 723 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
723 | * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) |
| 724 | * @note ENABLE: Remap (TIM1_CH1 DMA request/DMA1 Channel6, TIM1_CH2 DMA request/DMA1 Channel6) |
724 | * @retval None |
| 725 | * @retval None |
725 | */ |
| 726 | */ |
726 | #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
| 727 | #define __HAL_AFIO_REMAP_TIM1DMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
727 | |
| 728 | 728 | /** |
|
| 729 | /** |
729 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
| 730 | * @brief Controls the mapping of the TIM1_CH1 TIM1_CH2 DMA requests onto the DMA1 channels. |
730 | * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). |
| 731 | * @note DISABLE: No remap (TIM1_CH1 DMA request/DMA1 Channel2, TIM1_CH2 DMA request/DMA1 Channel3). |
731 | * @retval None |
| 732 | * @retval None |
732 | */ |
| 733 | */ |
733 | #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
| 734 | #define __HAL_AFIO_REMAP_TIM1DMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM1_DMA_REMAP) |
734 | #endif |
| 735 | #endif |
735 | |
| 736 | 736 | #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
|
| 737 | #if defined(AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
737 | |
| 738 | 738 | /** |
|
| 739 | /** |
739 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
| 740 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
740 | * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) |
| 741 | * @note ENABLE: Remap (TIM6_DAC1 DMA request/DMA1 Channel3, TIM7_DAC2 DMA request/DMA1 Channel4) |
741 | * @retval None |
| 742 | * @retval None |
742 | */ |
| 743 | */ |
743 | #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
| 744 | #define __HAL_AFIO_REMAP_TIM67DACDMA_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
744 | |
| 745 | 745 | /** |
|
| 746 | /** |
746 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
| 747 | * @brief Controls the mapping of the TIM6_DAC1 and TIM7_DAC2 DMA requests onto the DMA1 channels. |
747 | * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) |
| 748 | * @note DISABLE: No remap (TIM6_DAC1 DMA request/DMA2 Channel3, TIM7_DAC2 DMA request/DMA2 Channel4) |
748 | * @retval None |
| 749 | * @retval None |
749 | */ |
| 750 | */ |
750 | #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
| 751 | #define __HAL_AFIO_REMAP_TIM67DACDMA_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM67_DAC_DMA_REMAP) |
751 | #endif |
| 752 | #endif |
752 | |
| 753 | 753 | #if defined(AFIO_MAPR2_TIM12_REMAP) |
|
| 754 | #if defined(AFIO_MAPR2_TIM12_REMAP) |
754 | |
| 755 | 755 | /** |
|
| 756 | /** |
756 | * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. |
| 757 | * @brief Enable the remapping of TIM12_CH1 and TIM12_CH2. |
757 | * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). |
| 758 | * @note ENABLE: Remap (TIM12_CH1 on PB12 and TIM12_CH2 on PB13). |
758 | * @note This bit is available only in high density value line devices. |
| 759 | * @note This bit is available only in high density value line devices. |
759 | * @retval None |
| 760 | * @retval None |
760 | */ |
| 761 | */ |
761 | #define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
| 762 | #define __HAL_AFIO_REMAP_TIM12_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
762 | |
| 763 | 763 | /** |
|
| 764 | /** |
764 | * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. |
| 765 | * @brief Disable the remapping of TIM12_CH1 and TIM12_CH2. |
765 | * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). |
| 766 | * @note DISABLE: No remap (TIM12_CH1 on PC4 and TIM12_CH2 on PC5). |
766 | * @note This bit is available only in high density value line devices. |
| 767 | * @note This bit is available only in high density value line devices. |
767 | * @retval None |
| 768 | * @retval None |
768 | */ |
| 769 | */ |
769 | #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
| 770 | #define __HAL_AFIO_REMAP_TIM12_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_TIM12_REMAP) |
770 | #endif |
| 771 | #endif |
771 | |
| 772 | 772 | #if defined(AFIO_MAPR2_MISC_REMAP) |
|
| 773 | #if defined(AFIO_MAPR2_MISC_REMAP) |
773 | |
| 774 | 774 | /** |
|
| 775 | /** |
775 | * @brief Miscellaneous features remapping. |
| 776 | * @brief Miscellaneous features remapping. |
776 | * This bit is set and cleared by software. It controls miscellaneous features. |
| 777 | * This bit is set and cleared by software. It controls miscellaneous features. |
777 | * The DMA2 channel 5 interrupt position in the vector table. |
| 778 | * The DMA2 channel 5 interrupt position in the vector table. |
778 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
| 779 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
779 | * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is |
| 780 | * @note ENABLE: DMA2 channel 5 interrupt is mapped separately at position 60 and TIM15 TRGO event is |
780 | * selected as DAC Trigger 3, TIM15 triggers TIM1/3. |
| 781 | * selected as DAC Trigger 3, TIM15 triggers TIM1/3. |
781 | * @note This bit is available only in high density value line devices. |
| 782 | * @note This bit is available only in high density value line devices. |
782 | * @retval None |
| 783 | * @retval None |
783 | */ |
| 784 | */ |
784 | #define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
| 785 | #define __HAL_AFIO_REMAP_MISC_ENABLE() SET_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
785 | |
| 786 | 786 | /** |
|
| 787 | /** |
787 | * @brief Miscellaneous features remapping. |
| 788 | * @brief Miscellaneous features remapping. |
788 | * This bit is set and cleared by software. It controls miscellaneous features. |
| 789 | * This bit is set and cleared by software. It controls miscellaneous features. |
789 | * The DMA2 channel 5 interrupt position in the vector table. |
| 790 | * The DMA2 channel 5 interrupt position in the vector table. |
790 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
| 791 | * The timer selection for DAC trigger 3 (TSEL[2:0] = 011, for more details refer to the DAC_CR register). |
791 | * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO |
| 792 | * @note DISABLE: DMA2 channel 5 interrupt is mapped with DMA2 channel 4 at position 59, TIM5 TRGO |
792 | * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. |
| 793 | * event is selected as DAC Trigger 3, TIM5 triggers TIM1/3. |
793 | * @note This bit is available only in high density value line devices. |
| 794 | * @note This bit is available only in high density value line devices. |
794 | * @retval None |
| 795 | * @retval None |
795 | */ |
| 796 | */ |
796 | #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
| 797 | #define __HAL_AFIO_REMAP_MISC_DISABLE() CLEAR_BIT(AFIO->MAPR2, AFIO_MAPR2_MISC_REMAP) |
797 | #endif |
| 798 | #endif |
798 | |
| 799 | 799 | /** |
|
| 800 | /** |
800 | * @} |
| 801 | * @} |
801 | */ |
| 802 | */ |
802 | |
| 803 | 803 | /** |
|
| 804 | /** |
804 | * @} |
| 805 | * @} |
805 | */ |
| 806 | */ |
806 | |
| 807 | 807 | /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros |
|
| 808 | /** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros |
808 | * @{ |
| 809 | * @{ |
809 | */ |
| 810 | */ |
810 | #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) |
| 811 | #if defined(STM32F101x6) || defined(STM32F102x6) || defined(STM32F102xB) || defined(STM32F103x6) |
811 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
| 812 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
812 | ((__GPIOx__) == (GPIOB))? 1uL :\ |
| 813 | ((__GPIOx__) == (GPIOB))? 1uL :\ |
813 | ((__GPIOx__) == (GPIOC))? 2uL :3uL) |
| 814 | ((__GPIOx__) == (GPIOC))? 2uL :3uL) |
814 | #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) |
| 815 | #elif defined(STM32F100xB) || defined(STM32F101xB) || defined(STM32F103xB) || defined(STM32F105xC) || defined(STM32F107xC) |
815 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
| 816 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
816 | ((__GPIOx__) == (GPIOB))? 1uL :\ |
| 817 | ((__GPIOx__) == (GPIOB))? 1uL :\ |
817 | ((__GPIOx__) == (GPIOC))? 2uL :\ |
| 818 | ((__GPIOx__) == (GPIOC))? 2uL :\ |
818 | ((__GPIOx__) == (GPIOD))? 3uL :4uL) |
| 819 | ((__GPIOx__) == (GPIOD))? 3uL :4uL) |
819 | #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
| 820 | #elif defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG) |
820 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
| 821 | #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ |
821 | ((__GPIOx__) == (GPIOB))? 1uL :\ |
| 822 | ((__GPIOx__) == (GPIOB))? 1uL :\ |
822 | ((__GPIOx__) == (GPIOC))? 2uL :\ |
| 823 | ((__GPIOx__) == (GPIOC))? 2uL :\ |
823 | ((__GPIOx__) == (GPIOD))? 3uL :\ |
| 824 | ((__GPIOx__) == (GPIOD))? 3uL :\ |
824 | ((__GPIOx__) == (GPIOE))? 4uL :\ |
| 825 | ((__GPIOx__) == (GPIOE))? 4uL :\ |
825 | ((__GPIOx__) == (GPIOF))? 5uL :6uL) |
| 826 | ((__GPIOx__) == (GPIOF))? 5uL :6uL) |
826 | #endif |
| 827 | #endif |
827 | |
| 828 | 828 | #define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ |
|
| 829 | #define AFIO_REMAP_ENABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ |
829 | tmpreg |= AFIO_MAPR_SWJ_CFG; \ |
| 830 | tmpreg |= AFIO_MAPR_SWJ_CFG; \ |
830 | tmpreg |= REMAP_PIN; \ |
| 831 | tmpreg |= REMAP_PIN; \ |
831 | AFIO->MAPR = tmpreg; \ |
| 832 | AFIO->MAPR = tmpreg; \ |
832 | }while(0u) |
| 833 | }while(0u) |
833 | |
| 834 | 834 | #define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ |
|
| 835 | #define AFIO_REMAP_DISABLE(REMAP_PIN) do{ uint32_t tmpreg = AFIO->MAPR; \ |
835 | tmpreg |= AFIO_MAPR_SWJ_CFG; \ |
| 836 | tmpreg |= AFIO_MAPR_SWJ_CFG; \ |
836 | tmpreg &= ~REMAP_PIN; \ |
| 837 | tmpreg &= ~REMAP_PIN; \ |
837 | AFIO->MAPR = tmpreg; \ |
| 838 | AFIO->MAPR = tmpreg; \ |
838 | }while(0u) |
| 839 | }while(0u) |
839 | |
| 840 | 840 | #define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \ |
|
| 841 | #define AFIO_REMAP_PARTIAL(REMAP_PIN, REMAP_PIN_MASK) do{ uint32_t tmpreg = AFIO->MAPR; \ |
841 | tmpreg &= ~REMAP_PIN_MASK; \ |
| 842 | tmpreg &= ~REMAP_PIN_MASK; \ |
842 | tmpreg |= AFIO_MAPR_SWJ_CFG; \ |
| 843 | tmpreg |= AFIO_MAPR_SWJ_CFG; \ |
843 | tmpreg |= REMAP_PIN; \ |
| 844 | tmpreg |= REMAP_PIN; \ |
844 | AFIO->MAPR = tmpreg; \ |
| 845 | AFIO->MAPR = tmpreg; \ |
845 | }while(0u) |
| 846 | }while(0u) |
846 | |
| 847 | 847 | #define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \ |
|
| 848 | #define AFIO_DBGAFR_CONFIG(DBGAFR_SWJCFG) do{ uint32_t tmpreg = AFIO->MAPR; \ |
848 | tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \ |
| 849 | tmpreg &= ~AFIO_MAPR_SWJ_CFG_Msk; \ |
849 | tmpreg |= DBGAFR_SWJCFG; \ |
| 850 | tmpreg |= DBGAFR_SWJCFG; \ |
850 | AFIO->MAPR = tmpreg; \ |
| 851 | AFIO->MAPR = tmpreg; \ |
851 | }while(0u) |
| 852 | }while(0u) |
852 | |
| 853 | 853 | /** |
|
| 854 | /** |
854 | * @} |
| 855 | * @} |
855 | */ |
| 856 | */ |
856 | |
| 857 | 857 | /* Exported macro ------------------------------------------------------------*/ |
|
| 858 | /* Exported macro ------------------------------------------------------------*/ |
858 | /* Exported functions --------------------------------------------------------*/ |
| 859 | /* Exported functions --------------------------------------------------------*/ |
859 | |
| 860 | 860 | /** @addtogroup GPIOEx_Exported_Functions |
|
| 861 | /** @addtogroup GPIOEx_Exported_Functions |
861 | * @{ |
| 862 | * @{ |
862 | */ |
| 863 | */ |
863 | |
| 864 | 864 | /** @addtogroup GPIOEx_Exported_Functions_Group1 |
|
| 865 | /** @addtogroup GPIOEx_Exported_Functions_Group1 |
865 | * @{ |
| 866 | * @{ |
866 | */ |
| 867 | */ |
867 | void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource); |
| 868 | void HAL_GPIOEx_ConfigEventout(uint32_t GPIO_PortSource, uint32_t GPIO_PinSource); |
868 | void HAL_GPIOEx_EnableEventout(void); |
| 869 | void HAL_GPIOEx_EnableEventout(void); |
869 | void HAL_GPIOEx_DisableEventout(void); |
| 870 | void HAL_GPIOEx_DisableEventout(void); |
870 | |
| 871 | 871 | /** |
|
| 872 | /** |
872 | * @} |
| 873 | * @} |
873 | */ |
| 874 | */ |
874 | |
| 875 | 875 | /** |
|
| 876 | /** |
876 | * @} |
| 877 | * @} |
877 | */ |
| 878 | */ |
878 | |
| 879 | 879 | /** |
|
| 880 | /** |
880 | * @} |
| 881 | * @} |
881 | */ |
| 882 | */ |
882 | |
| 883 | 883 | /** |
|
| 884 | /** |
884 | * @} |
| 885 | * @} |
885 | */ |
| 886 | */ |
886 | |
| 887 | 887 | #ifdef __cplusplus |
|
| 888 | #ifdef __cplusplus |
888 | } |
| 889 | } |
889 | #endif |
| 890 | #endif |
890 | |
| 891 | 891 | #endif /* STM32F1xx_HAL_GPIO_EX_H */ |
|
| 892 | #endif /* STM32F1xx_HAL_GPIO_EX_H */ |
892 | |
| 893 | - | ||
| 894 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |