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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_hal_eth.h |
3 | * @file stm32f1xx_hal_eth.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of ETH HAL module. |
5 | * @brief Header file of ETH HAL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | |
| 19 | 19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
|
| 20 | /* Define to prevent recursive inclusion -------------------------------------*/ |
20 | #ifndef __STM32F1xx_HAL_ETH_H |
| 21 | #ifndef __STM32F1xx_HAL_ETH_H |
21 | #define __STM32F1xx_HAL_ETH_H |
| 22 | #define __STM32F1xx_HAL_ETH_H |
22 | |
| 23 | 23 | #ifdef __cplusplus |
|
| 24 | #ifdef __cplusplus |
24 | extern "C" { |
| 25 | extern "C" { |
25 | #endif |
| 26 | #endif |
26 | |
| 27 | 27 | /* Includes ------------------------------------------------------------------*/ |
|
| 28 | /* Includes ------------------------------------------------------------------*/ |
28 | #include "stm32f1xx_hal_def.h" |
| 29 | #include "stm32f1xx_hal_def.h" |
29 | |
| 30 | 30 | #if defined (ETH) |
|
| 31 | #if defined (ETH) |
31 | |
| 32 | 32 | /** @addtogroup STM32F1xx_HAL_Driver |
|
| 33 | /** @addtogroup STM32F1xx_HAL_Driver |
33 | * @{ |
| 34 | * @{ |
34 | */ |
| 35 | */ |
35 | |
| 36 | 36 | /** @addtogroup ETH |
|
| 37 | /** @addtogroup ETH |
37 | * @{ |
| 38 | * @{ |
38 | */ |
| 39 | */ |
39 | |
| 40 | 40 | /** @addtogroup ETH_Private_Macros |
|
| 41 | /** @addtogroup ETH_Private_Macros |
41 | * @{ |
| 42 | * @{ |
42 | */ |
| 43 | */ |
43 | #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) |
| 44 | #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) |
44 | #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ |
| 45 | #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ |
45 | ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) |
| 46 | ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) |
46 | #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ |
| 47 | #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ |
47 | ((SPEED) == ETH_SPEED_100M)) |
| 48 | ((SPEED) == ETH_SPEED_100M)) |
48 | #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ |
| 49 | #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ |
49 | ((MODE) == ETH_MODE_HALFDUPLEX)) |
| 50 | ((MODE) == ETH_MODE_HALFDUPLEX)) |
50 | #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ |
| 51 | #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ |
51 | ((MODE) == ETH_RXINTERRUPT_MODE)) |
| 52 | ((MODE) == ETH_RXINTERRUPT_MODE)) |
52 | #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ |
| 53 | #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ |
53 | ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) |
| 54 | ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) |
54 | #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ |
| 55 | #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ |
55 | ((MODE) == ETH_MEDIA_INTERFACE_RMII)) |
| 56 | ((MODE) == ETH_MEDIA_INTERFACE_RMII)) |
56 | #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ |
| 57 | #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ |
57 | ((CMD) == ETH_WATCHDOG_DISABLE)) |
| 58 | ((CMD) == ETH_WATCHDOG_DISABLE)) |
58 | #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ |
| 59 | #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ |
59 | ((CMD) == ETH_JABBER_DISABLE)) |
| 60 | ((CMD) == ETH_JABBER_DISABLE)) |
60 | #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ |
| 61 | #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ |
61 | ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ |
| 62 | ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ |
62 | ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ |
| 63 | ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ |
63 | ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ |
| 64 | ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ |
64 | ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ |
| 65 | ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ |
65 | ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ |
| 66 | ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ |
66 | ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ |
| 67 | ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ |
67 | ((GAP) == ETH_INTERFRAMEGAP_40BIT)) |
| 68 | ((GAP) == ETH_INTERFRAMEGAP_40BIT)) |
68 | #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ |
| 69 | #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ |
69 | ((CMD) == ETH_CARRIERSENCE_DISABLE)) |
| 70 | ((CMD) == ETH_CARRIERSENCE_DISABLE)) |
70 | #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ |
| 71 | #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ |
71 | ((CMD) == ETH_RECEIVEOWN_DISABLE)) |
| 72 | ((CMD) == ETH_RECEIVEOWN_DISABLE)) |
72 | #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ |
| 73 | #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ |
73 | ((CMD) == ETH_LOOPBACKMODE_DISABLE)) |
| 74 | ((CMD) == ETH_LOOPBACKMODE_DISABLE)) |
74 | #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ |
| 75 | #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ |
75 | ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) |
| 76 | ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) |
76 | #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ |
| 77 | #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ |
77 | ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) |
| 78 | ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) |
78 | #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ |
| 79 | #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ |
79 | ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) |
| 80 | ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) |
80 | #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ |
| 81 | #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ |
81 | ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ |
| 82 | ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ |
82 | ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ |
| 83 | ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ |
83 | ((LIMIT) == ETH_BACKOFFLIMIT_1)) |
| 84 | ((LIMIT) == ETH_BACKOFFLIMIT_1)) |
84 | #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ |
| 85 | #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ |
85 | ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) |
| 86 | ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) |
86 | #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ |
| 87 | #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ |
87 | ((CMD) == ETH_RECEIVEAll_DISABLE)) |
| 88 | ((CMD) == ETH_RECEIVEAll_DISABLE)) |
88 | #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ |
| 89 | #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ |
89 | ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ |
| 90 | ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ |
90 | ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) |
| 91 | ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) |
91 | #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ |
| 92 | #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ |
92 | ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ |
| 93 | ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ |
93 | ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) |
| 94 | ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) |
94 | #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ |
| 95 | #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ |
95 | ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) |
| 96 | ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) |
96 | #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ |
| 97 | #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ |
97 | ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) |
| 98 | ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) |
98 | #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ |
| 99 | #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ |
99 | ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) |
| 100 | ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) |
100 | #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ |
| 101 | #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ |
101 | ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ |
| 102 | ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ |
102 | ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ |
| 103 | ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ |
103 | ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) |
| 104 | ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) |
104 | #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ |
| 105 | #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ |
105 | ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ |
| 106 | ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ |
106 | ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) |
| 107 | ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) |
107 | #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) |
| 108 | #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) |
108 | #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ |
| 109 | #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ |
109 | ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) |
| 110 | ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) |
110 | #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ |
| 111 | #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ |
111 | ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ |
| 112 | ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ |
112 | ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ |
| 113 | ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ |
113 | ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) |
| 114 | ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) |
114 | #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ |
| 115 | #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ |
115 | ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) |
| 116 | ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) |
116 | #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ |
| 117 | #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ |
117 | ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) |
| 118 | ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) |
118 | #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ |
| 119 | #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ |
119 | ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) |
| 120 | ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) |
120 | #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ |
| 121 | #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ |
121 | ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) |
| 122 | ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) |
122 | #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) |
| 123 | #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) |
123 | #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ |
| 124 | #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ |
124 | ((ADDRESS) == ETH_MAC_ADDRESS1) || \ |
| 125 | ((ADDRESS) == ETH_MAC_ADDRESS1) || \ |
125 | ((ADDRESS) == ETH_MAC_ADDRESS2) || \ |
| 126 | ((ADDRESS) == ETH_MAC_ADDRESS2) || \ |
126 | ((ADDRESS) == ETH_MAC_ADDRESS3)) |
| 127 | ((ADDRESS) == ETH_MAC_ADDRESS3)) |
127 | #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ |
| 128 | #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ |
128 | ((ADDRESS) == ETH_MAC_ADDRESS2) || \ |
| 129 | ((ADDRESS) == ETH_MAC_ADDRESS2) || \ |
129 | ((ADDRESS) == ETH_MAC_ADDRESS3)) |
| 130 | ((ADDRESS) == ETH_MAC_ADDRESS3)) |
130 | #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ |
| 131 | #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ |
131 | ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) |
| 132 | ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) |
132 | #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ |
| 133 | #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ |
133 | ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ |
| 134 | ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ |
134 | ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ |
| 135 | ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ |
135 | ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ |
| 136 | ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ |
136 | ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ |
| 137 | ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ |
137 | ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) |
| 138 | ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) |
138 | #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ |
| 139 | #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ |
139 | ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) |
| 140 | ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) |
140 | #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ |
| 141 | #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ |
141 | ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) |
| 142 | ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) |
142 | #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ |
| 143 | #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ |
143 | ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) |
| 144 | ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) |
144 | #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ |
| 145 | #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ |
145 | ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) |
| 146 | ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) |
146 | #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ |
| 147 | #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ |
147 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ |
| 148 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ |
148 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ |
| 149 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ |
149 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ |
| 150 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ |
150 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ |
| 151 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ |
151 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ |
| 152 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ |
152 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ |
| 153 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ |
153 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) |
| 154 | ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) |
154 | #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ |
| 155 | #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ |
155 | ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) |
| 156 | ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) |
156 | #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ |
| 157 | #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ |
157 | ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) |
| 158 | ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) |
158 | #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ |
| 159 | #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ |
159 | ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ |
| 160 | ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ |
160 | ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ |
| 161 | ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ |
161 | ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) |
| 162 | ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) |
162 | #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ |
| 163 | #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ |
163 | ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) |
| 164 | ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) |
164 | #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ |
| 165 | #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ |
165 | ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) |
| 166 | ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) |
166 | #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ |
| 167 | #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ |
167 | ((CMD) == ETH_FIXEDBURST_DISABLE)) |
| 168 | ((CMD) == ETH_FIXEDBURST_DISABLE)) |
168 | #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ |
| 169 | #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ |
169 | ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ |
| 170 | ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ |
170 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ |
| 171 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ |
171 | ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ |
| 172 | ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ |
172 | ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ |
| 173 | ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ |
173 | ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ |
| 174 | ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ |
174 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ |
| 175 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ |
175 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ |
| 176 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ |
176 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ |
| 177 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ |
177 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ |
| 178 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ |
178 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ |
| 179 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ |
179 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) |
| 180 | ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) |
180 | #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ |
| 181 | #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ |
181 | ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ |
| 182 | ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ |
182 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ |
| 183 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ |
183 | ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ |
| 184 | ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ |
184 | ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ |
| 185 | ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ |
185 | ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ |
| 186 | ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ |
186 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ |
| 187 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ |
187 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ |
| 188 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ |
188 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ |
| 189 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ |
189 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ |
| 190 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ |
190 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ |
| 191 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ |
191 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) |
| 192 | ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) |
192 | #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) |
| 193 | #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) |
193 | #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ |
| 194 | #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ |
194 | ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ |
| 195 | ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ |
195 | ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ |
| 196 | ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ |
196 | ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ |
| 197 | ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ |
197 | ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) |
| 198 | ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) |
198 | #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ |
| 199 | #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ |
199 | ((FLAG) == ETH_DMATXDESC_IC) || \ |
| 200 | ((FLAG) == ETH_DMATXDESC_IC) || \ |
200 | ((FLAG) == ETH_DMATXDESC_LS) || \ |
| 201 | ((FLAG) == ETH_DMATXDESC_LS) || \ |
201 | ((FLAG) == ETH_DMATXDESC_FS) || \ |
| 202 | ((FLAG) == ETH_DMATXDESC_FS) || \ |
202 | ((FLAG) == ETH_DMATXDESC_DC) || \ |
| 203 | ((FLAG) == ETH_DMATXDESC_DC) || \ |
203 | ((FLAG) == ETH_DMATXDESC_DP) || \ |
| 204 | ((FLAG) == ETH_DMATXDESC_DP) || \ |
204 | ((FLAG) == ETH_DMATXDESC_TTSE) || \ |
| 205 | ((FLAG) == ETH_DMATXDESC_TTSE) || \ |
205 | ((FLAG) == ETH_DMATXDESC_TER) || \ |
| 206 | ((FLAG) == ETH_DMATXDESC_TER) || \ |
206 | ((FLAG) == ETH_DMATXDESC_TCH) || \ |
| 207 | ((FLAG) == ETH_DMATXDESC_TCH) || \ |
207 | ((FLAG) == ETH_DMATXDESC_TTSS) || \ |
| 208 | ((FLAG) == ETH_DMATXDESC_TTSS) || \ |
208 | ((FLAG) == ETH_DMATXDESC_IHE) || \ |
| 209 | ((FLAG) == ETH_DMATXDESC_IHE) || \ |
209 | ((FLAG) == ETH_DMATXDESC_ES) || \ |
| 210 | ((FLAG) == ETH_DMATXDESC_ES) || \ |
210 | ((FLAG) == ETH_DMATXDESC_JT) || \ |
| 211 | ((FLAG) == ETH_DMATXDESC_JT) || \ |
211 | ((FLAG) == ETH_DMATXDESC_FF) || \ |
| 212 | ((FLAG) == ETH_DMATXDESC_FF) || \ |
212 | ((FLAG) == ETH_DMATXDESC_PCE) || \ |
| 213 | ((FLAG) == ETH_DMATXDESC_PCE) || \ |
213 | ((FLAG) == ETH_DMATXDESC_LCA) || \ |
| 214 | ((FLAG) == ETH_DMATXDESC_LCA) || \ |
214 | ((FLAG) == ETH_DMATXDESC_NC) || \ |
| 215 | ((FLAG) == ETH_DMATXDESC_NC) || \ |
215 | ((FLAG) == ETH_DMATXDESC_LCO) || \ |
| 216 | ((FLAG) == ETH_DMATXDESC_LCO) || \ |
216 | ((FLAG) == ETH_DMATXDESC_EC) || \ |
| 217 | ((FLAG) == ETH_DMATXDESC_EC) || \ |
217 | ((FLAG) == ETH_DMATXDESC_VF) || \ |
| 218 | ((FLAG) == ETH_DMATXDESC_VF) || \ |
218 | ((FLAG) == ETH_DMATXDESC_CC) || \ |
| 219 | ((FLAG) == ETH_DMATXDESC_CC) || \ |
219 | ((FLAG) == ETH_DMATXDESC_ED) || \ |
| 220 | ((FLAG) == ETH_DMATXDESC_ED) || \ |
220 | ((FLAG) == ETH_DMATXDESC_UF) || \ |
| 221 | ((FLAG) == ETH_DMATXDESC_UF) || \ |
221 | ((FLAG) == ETH_DMATXDESC_DB)) |
| 222 | ((FLAG) == ETH_DMATXDESC_DB)) |
222 | #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ |
| 223 | #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ |
223 | ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) |
| 224 | ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) |
224 | #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ |
| 225 | #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ |
225 | ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ |
| 226 | ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ |
226 | ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ |
| 227 | ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ |
227 | ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) |
| 228 | ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) |
228 | #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) |
| 229 | #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) |
229 | #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ |
| 230 | #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ |
230 | ((FLAG) == ETH_DMARXDESC_AFM) || \ |
| 231 | ((FLAG) == ETH_DMARXDESC_AFM) || \ |
231 | ((FLAG) == ETH_DMARXDESC_ES) || \ |
| 232 | ((FLAG) == ETH_DMARXDESC_ES) || \ |
232 | ((FLAG) == ETH_DMARXDESC_DE) || \ |
| 233 | ((FLAG) == ETH_DMARXDESC_DE) || \ |
233 | ((FLAG) == ETH_DMARXDESC_SAF) || \ |
| 234 | ((FLAG) == ETH_DMARXDESC_SAF) || \ |
234 | ((FLAG) == ETH_DMARXDESC_LE) || \ |
| 235 | ((FLAG) == ETH_DMARXDESC_LE) || \ |
235 | ((FLAG) == ETH_DMARXDESC_OE) || \ |
| 236 | ((FLAG) == ETH_DMARXDESC_OE) || \ |
236 | ((FLAG) == ETH_DMARXDESC_VLAN) || \ |
| 237 | ((FLAG) == ETH_DMARXDESC_VLAN) || \ |
237 | ((FLAG) == ETH_DMARXDESC_FS) || \ |
| 238 | ((FLAG) == ETH_DMARXDESC_FS) || \ |
238 | ((FLAG) == ETH_DMARXDESC_LS) || \ |
| 239 | ((FLAG) == ETH_DMARXDESC_LS) || \ |
239 | ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ |
| 240 | ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ |
240 | ((FLAG) == ETH_DMARXDESC_LC) || \ |
| 241 | ((FLAG) == ETH_DMARXDESC_LC) || \ |
241 | ((FLAG) == ETH_DMARXDESC_FT) || \ |
| 242 | ((FLAG) == ETH_DMARXDESC_FT) || \ |
242 | ((FLAG) == ETH_DMARXDESC_RWT) || \ |
| 243 | ((FLAG) == ETH_DMARXDESC_RWT) || \ |
243 | ((FLAG) == ETH_DMARXDESC_RE) || \ |
| 244 | ((FLAG) == ETH_DMARXDESC_RE) || \ |
244 | ((FLAG) == ETH_DMARXDESC_DBE) || \ |
| 245 | ((FLAG) == ETH_DMARXDESC_DBE) || \ |
245 | ((FLAG) == ETH_DMARXDESC_CE) || \ |
| 246 | ((FLAG) == ETH_DMARXDESC_CE) || \ |
246 | ((FLAG) == ETH_DMARXDESC_MAMPCE)) |
| 247 | ((FLAG) == ETH_DMARXDESC_MAMPCE)) |
247 | #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ |
| 248 | #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ |
248 | ((BUFFER) == ETH_DMARXDESC_BUFFER2)) |
| 249 | ((BUFFER) == ETH_DMARXDESC_BUFFER2)) |
249 | #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ |
| 250 | #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ |
250 | ((FLAG) == ETH_PMT_FLAG_MPR)) |
| 251 | ((FLAG) == ETH_PMT_FLAG_MPR)) |
251 | #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) |
| 252 | #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) |
252 | #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ |
| 253 | #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ |
253 | ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ |
| 254 | ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ |
254 | ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ |
| 255 | ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ |
255 | ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ |
| 256 | ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ |
256 | ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ |
| 257 | ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ |
257 | ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ |
| 258 | ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ |
258 | ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ |
| 259 | ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ |
259 | ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ |
| 260 | ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ |
260 | ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ |
| 261 | ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ |
261 | ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ |
| 262 | ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ |
262 | ((FLAG) == ETH_DMA_FLAG_T)) |
| 263 | ((FLAG) == ETH_DMA_FLAG_T)) |
263 | #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) |
| 264 | #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) |
264 | #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ |
| 265 | #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ |
265 | ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ |
| 266 | ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ |
266 | ((IT) == ETH_MAC_IT_PMT)) |
| 267 | ((IT) == ETH_MAC_IT_PMT)) |
267 | #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ |
| 268 | #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ |
268 | ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ |
| 269 | ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ |
269 | ((FLAG) == ETH_MAC_FLAG_PMT)) |
| 270 | ((FLAG) == ETH_MAC_FLAG_PMT)) |
270 | #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) |
| 271 | #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) |
271 | #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ |
| 272 | #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ |
272 | ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ |
| 273 | ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ |
273 | ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ |
| 274 | ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ |
274 | ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ |
| 275 | ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ |
275 | ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ |
| 276 | ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ |
276 | ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ |
| 277 | ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ |
277 | ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ |
| 278 | ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ |
278 | ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ |
| 279 | ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ |
279 | ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) |
| 280 | ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) |
280 | #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ |
| 281 | #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ |
281 | ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) |
| 282 | ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) |
282 | #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ |
| 283 | #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ |
283 | ((IT) != 0x00U)) |
| 284 | ((IT) != 0x00U)) |
284 | #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ |
| 285 | #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ |
285 | ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ |
| 286 | ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ |
286 | ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) |
| 287 | ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) |
287 | #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ |
| 288 | #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ |
288 | ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) |
| 289 | ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) |
289 | |
| 290 | 290 | /** |
|
| 291 | /** |
291 | * @} |
| 292 | * @} |
292 | */ |
| 293 | */ |
293 | |
| 294 | 294 | /** @addtogroup ETH_Private_Defines |
|
| 295 | /** @addtogroup ETH_Private_Defines |
295 | * @{ |
| 296 | * @{ |
296 | */ |
| 297 | */ |
297 | /* Delay to wait when writing to some Ethernet registers */ |
| 298 | /* Delay to wait when writing to some Ethernet registers */ |
298 | #define ETH_REG_WRITE_DELAY 0x00000001U |
| 299 | #define ETH_REG_WRITE_DELAY 0x00000001U |
299 | |
| 300 | 300 | /* ETHERNET Errors */ |
|
| 301 | /* ETHERNET Errors */ |
301 | #define ETH_SUCCESS 0U |
| 302 | #define ETH_SUCCESS 0U |
302 | #define ETH_ERROR 1U |
| 303 | #define ETH_ERROR 1U |
303 | |
| 304 | 304 | /* ETHERNET DMA Tx descriptors Collision Count Shift */ |
|
| 305 | /* ETHERNET DMA Tx descriptors Collision Count Shift */ |
305 | #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U |
| 306 | #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U |
306 | |
| 307 | 307 | /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ |
|
| 308 | /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ |
308 | #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U |
| 309 | #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U |
309 | |
| 310 | 310 | /* ETHERNET DMA Rx descriptors Frame Length Shift */ |
|
| 311 | /* ETHERNET DMA Rx descriptors Frame Length Shift */ |
311 | #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U |
| 312 | #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U |
312 | |
| 313 | 313 | /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ |
|
| 314 | /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ |
314 | #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U |
| 315 | #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U |
315 | |
| 316 | 316 | /* ETHERNET DMA Rx descriptors Frame length Shift */ |
|
| 317 | /* ETHERNET DMA Rx descriptors Frame length Shift */ |
317 | #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U |
| 318 | #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U |
318 | |
| 319 | 319 | /* ETHERNET MAC address offsets */ |
|
| 320 | /* ETHERNET MAC address offsets */ |
320 | #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ |
| 321 | #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ |
321 | #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ |
| 322 | #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ |
322 | |
| 323 | 323 | /* ETHERNET MACMIIAR register Mask */ |
|
| 324 | /* ETHERNET MACMIIAR register Mask */ |
324 | #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U |
| 325 | #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U |
325 | |
| 326 | 326 | /* ETHERNET MACCR register Mask */ |
|
| 327 | /* ETHERNET MACCR register Mask */ |
327 | #define ETH_MACCR_CLEAR_MASK 0xFF20810FU |
| 328 | #define ETH_MACCR_CLEAR_MASK 0xFF20810FU |
328 | |
| 329 | 329 | /* ETHERNET MACFCR register Mask */ |
|
| 330 | /* ETHERNET MACFCR register Mask */ |
330 | #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U |
| 331 | #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U |
331 | |
| 332 | 332 | /* ETHERNET DMAOMR register Mask */ |
|
| 333 | /* ETHERNET DMAOMR register Mask */ |
333 | #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U |
| 334 | #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U |
334 | |
| 335 | 335 | /* ETHERNET Remote Wake-up frame register length */ |
|
| 336 | /* ETHERNET Remote Wake-up frame register length */ |
336 | #define ETH_WAKEUP_REGISTER_LENGTH 8U |
| 337 | #define ETH_WAKEUP_REGISTER_LENGTH 8U |
337 | |
| 338 | 338 | /* ETHERNET Missed frames counter Shift */ |
|
| 339 | /* ETHERNET Missed frames counter Shift */ |
339 | #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U |
| 340 | #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U |
340 | /** |
| 341 | /** |
341 | * @} |
| 342 | * @} |
342 | */ |
| 343 | */ |
343 | |
| 344 | 344 | /* Exported types ------------------------------------------------------------*/ |
|
| 345 | /* Exported types ------------------------------------------------------------*/ |
345 | /** @defgroup ETH_Exported_Types ETH Exported Types |
| 346 | /** @defgroup ETH_Exported_Types ETH Exported Types |
346 | * @{ |
| 347 | * @{ |
347 | */ |
| 348 | */ |
348 | |
| 349 | 349 | /** |
|
| 350 | /** |
350 | * @brief HAL State structures definition |
| 351 | * @brief HAL State structures definition |
351 | */ |
| 352 | */ |
352 | typedef enum |
| 353 | typedef enum |
353 | { |
| 354 | { |
354 | HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ |
| 355 | HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ |
355 | HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
| 356 | HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
356 | HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ |
| 357 | HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ |
357 | HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ |
| 358 | HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ |
358 | HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ |
| 359 | HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ |
359 | HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ |
| 360 | HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ |
360 | HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ |
| 361 | HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ |
361 | HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ |
| 362 | HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ |
362 | HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
| 363 | HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
363 | HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ |
| 364 | HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ |
364 | } HAL_ETH_StateTypeDef; |
| 365 | } HAL_ETH_StateTypeDef; |
365 | |
| 366 | 366 | /** |
|
| 367 | /** |
367 | * @brief ETH Init Structure definition |
| 368 | * @brief ETH Init Structure definition |
368 | */ |
| 369 | */ |
369 | |
| 370 | 370 | typedef struct |
|
| 371 | typedef struct |
371 | { |
| 372 | { |
372 | uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY |
| 373 | uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY |
373 | The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) |
| 374 | The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) |
374 | and the mode (half/full-duplex). |
| 375 | and the mode (half/full-duplex). |
375 | This parameter can be a value of @ref ETH_AutoNegotiation */ |
| 376 | This parameter can be a value of @ref ETH_AutoNegotiation */ |
376 | |
| 377 | 377 | uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. |
|
| 378 | uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. |
378 | This parameter can be a value of @ref ETH_Speed */ |
| 379 | This parameter can be a value of @ref ETH_Speed */ |
379 | |
| 380 | 380 | uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode |
|
| 381 | uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode |
381 | This parameter can be a value of @ref ETH_Duplex_Mode */ |
| 382 | This parameter can be a value of @ref ETH_Duplex_Mode */ |
382 | |
| 383 | 383 | uint16_t PhyAddress; /*!< Ethernet PHY address. |
|
| 384 | uint16_t PhyAddress; /*!< Ethernet PHY address. |
384 | This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ |
| 385 | This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ |
385 | |
| 386 | 386 | uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ |
|
| 387 | uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ |
387 | |
| 388 | 388 | uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. |
|
| 389 | uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. |
389 | This parameter can be a value of @ref ETH_Rx_Mode */ |
| 390 | This parameter can be a value of @ref ETH_Rx_Mode */ |
390 | |
| 391 | 391 | uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. |
|
| 392 | uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. |
392 | This parameter can be a value of @ref ETH_Checksum_Mode */ |
| 393 | This parameter can be a value of @ref ETH_Checksum_Mode */ |
393 | |
| 394 | 394 | uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. |
|
| 395 | uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. |
395 | This parameter can be a value of @ref ETH_Media_Interface */ |
| 396 | This parameter can be a value of @ref ETH_Media_Interface */ |
396 | |
| 397 | 397 | } ETH_InitTypeDef; |
|
| 398 | } ETH_InitTypeDef; |
398 | |
| 399 | 399 | ||
| 400 | 400 | /** |
|
| 401 | /** |
401 | * @brief ETH MAC Configuration Structure definition |
| 402 | * @brief ETH MAC Configuration Structure definition |
402 | */ |
| 403 | */ |
403 | |
| 404 | 404 | typedef struct |
|
| 405 | typedef struct |
405 | { |
| 406 | { |
406 | uint32_t Watchdog; /*!< Selects or not the Watchdog timer |
| 407 | uint32_t Watchdog; /*!< Selects or not the Watchdog timer |
407 | When enabled, the MAC allows no more then 2048 bytes to be received. |
| 408 | When enabled, the MAC allows no more then 2048 bytes to be received. |
408 | When disabled, the MAC can receive up to 16384 bytes. |
| 409 | When disabled, the MAC can receive up to 16384 bytes. |
409 | This parameter can be a value of @ref ETH_Watchdog */ |
| 410 | This parameter can be a value of @ref ETH_Watchdog */ |
410 | |
| 411 | 411 | uint32_t Jabber; /*!< Selects or not Jabber timer |
|
| 412 | uint32_t Jabber; /*!< Selects or not Jabber timer |
412 | When enabled, the MAC allows no more then 2048 bytes to be sent. |
| 413 | When enabled, the MAC allows no more then 2048 bytes to be sent. |
413 | When disabled, the MAC can send up to 16384 bytes. |
| 414 | When disabled, the MAC can send up to 16384 bytes. |
414 | This parameter can be a value of @ref ETH_Jabber */ |
| 415 | This parameter can be a value of @ref ETH_Jabber */ |
415 | |
| 416 | 416 | uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. |
|
| 417 | uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. |
417 | This parameter can be a value of @ref ETH_Inter_Frame_Gap */ |
| 418 | This parameter can be a value of @ref ETH_Inter_Frame_Gap */ |
418 | |
| 419 | 419 | uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. |
|
| 420 | uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. |
420 | This parameter can be a value of @ref ETH_Carrier_Sense */ |
| 421 | This parameter can be a value of @ref ETH_Carrier_Sense */ |
421 | |
| 422 | 422 | uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, |
|
| 423 | uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, |
423 | ReceiveOwn allows the reception of frames when the TX_EN signal is asserted |
| 424 | ReceiveOwn allows the reception of frames when the TX_EN signal is asserted |
424 | in Half-Duplex mode. |
| 425 | in Half-Duplex mode. |
425 | This parameter can be a value of @ref ETH_Receive_Own */ |
| 426 | This parameter can be a value of @ref ETH_Receive_Own */ |
426 | |
| 427 | 427 | uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. |
|
| 428 | uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. |
428 | This parameter can be a value of @ref ETH_Loop_Back_Mode */ |
| 429 | This parameter can be a value of @ref ETH_Loop_Back_Mode */ |
429 | |
| 430 | 430 | uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. |
|
| 431 | uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. |
431 | This parameter can be a value of @ref ETH_Checksum_Offload */ |
| 432 | This parameter can be a value of @ref ETH_Checksum_Offload */ |
432 | |
| 433 | 433 | uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, |
|
| 434 | uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, |
434 | when a collision occurs (Half-Duplex mode). |
| 435 | when a collision occurs (Half-Duplex mode). |
435 | This parameter can be a value of @ref ETH_Retry_Transmission */ |
| 436 | This parameter can be a value of @ref ETH_Retry_Transmission */ |
436 | |
| 437 | 437 | uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. |
|
| 438 | uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. |
438 | This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ |
| 439 | This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ |
439 | |
| 440 | 440 | uint32_t BackOffLimit; /*!< Selects the BackOff limit value. |
|
| 441 | uint32_t BackOffLimit; /*!< Selects the BackOff limit value. |
441 | This parameter can be a value of @ref ETH_Back_Off_Limit */ |
| 442 | This parameter can be a value of @ref ETH_Back_Off_Limit */ |
442 | |
| 443 | 443 | uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). |
|
| 444 | uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). |
444 | This parameter can be a value of @ref ETH_Deferral_Check */ |
| 445 | This parameter can be a value of @ref ETH_Deferral_Check */ |
445 | |
| 446 | 446 | uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). |
|
| 447 | uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). |
447 | This parameter can be a value of @ref ETH_Receive_All */ |
| 448 | This parameter can be a value of @ref ETH_Receive_All */ |
448 | |
| 449 | 449 | uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. |
|
| 450 | uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. |
450 | This parameter can be a value of @ref ETH_Source_Addr_Filter */ |
| 451 | This parameter can be a value of @ref ETH_Source_Addr_Filter */ |
451 | |
| 452 | 452 | uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) |
|
| 453 | uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) |
453 | This parameter can be a value of @ref ETH_Pass_Control_Frames */ |
| 454 | This parameter can be a value of @ref ETH_Pass_Control_Frames */ |
454 | |
| 455 | 455 | uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. |
|
| 456 | uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. |
456 | This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ |
| 457 | This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ |
457 | |
| 458 | 458 | uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. |
|
| 459 | uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. |
459 | This parameter can be a value of @ref ETH_Destination_Addr_Filter */ |
| 460 | This parameter can be a value of @ref ETH_Destination_Addr_Filter */ |
460 | |
| 461 | 461 | uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode |
|
| 462 | uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode |
462 | This parameter can be a value of @ref ETH_Promiscuous_Mode */ |
| 463 | This parameter can be a value of @ref ETH_Promiscuous_Mode */ |
463 | |
| 464 | 464 | uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. |
|
| 465 | uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. |
465 | This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ |
| 466 | This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ |
466 | |
| 467 | 467 | uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. |
|
| 468 | uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. |
468 | This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ |
| 469 | This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ |
469 | |
| 470 | 470 | uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. |
|
| 471 | uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. |
471 | This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ |
| 472 | This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ |
472 | |
| 473 | 473 | uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. |
|
| 474 | uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. |
474 | This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ |
| 475 | This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ |
475 | |
| 476 | 476 | uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. |
|
| 477 | uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. |
477 | This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ |
| 478 | This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ |
478 | |
| 479 | 479 | uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. |
|
| 480 | uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. |
480 | This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ |
| 481 | This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ |
481 | |
| 482 | 482 | uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for |
|
| 483 | uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for |
483 | automatic retransmission of PAUSE Frame. |
| 484 | automatic retransmission of PAUSE Frame. |
484 | This parameter can be a value of @ref ETH_Pause_Low_Threshold */ |
| 485 | This parameter can be a value of @ref ETH_Pause_Low_Threshold */ |
485 | |
| 486 | 486 | uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 |
|
| 487 | uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 |
487 | unicast address and unique multicast address). |
| 488 | unicast address and unique multicast address). |
488 | This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ |
| 489 | This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ |
489 | |
| 490 | 490 | uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and |
|
| 491 | uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and |
491 | disable its transmitter for a specified time (Pause Time) |
| 492 | disable its transmitter for a specified time (Pause Time) |
492 | This parameter can be a value of @ref ETH_Receive_Flow_Control */ |
| 493 | This parameter can be a value of @ref ETH_Receive_Flow_Control */ |
493 | |
| 494 | 494 | uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) |
|
| 495 | uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) |
495 | or the MAC back-pressure operation (Half-Duplex mode) |
| 496 | or the MAC back-pressure operation (Half-Duplex mode) |
496 | This parameter can be a value of @ref ETH_Transmit_Flow_Control */ |
| 497 | This parameter can be a value of @ref ETH_Transmit_Flow_Control */ |
497 | |
| 498 | 498 | uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for |
|
| 499 | uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for |
499 | comparison and filtering. |
| 500 | comparison and filtering. |
500 | This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ |
| 501 | This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ |
501 | |
| 502 | 502 | uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ |
|
| 503 | uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ |
503 | |
| 504 | 504 | } ETH_MACInitTypeDef; |
|
| 505 | } ETH_MACInitTypeDef; |
505 | |
| 506 | 506 | /** |
|
| 507 | /** |
507 | * @brief ETH DMA Configuration Structure definition |
| 508 | * @brief ETH DMA Configuration Structure definition |
508 | */ |
| 509 | */ |
509 | |
| 510 | 510 | typedef struct |
|
| 511 | typedef struct |
511 | { |
| 512 | { |
512 | uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. |
| 513 | uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. |
513 | This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ |
| 514 | This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ |
514 | |
| 515 | 515 | uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. |
|
| 516 | uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. |
516 | This parameter can be a value of @ref ETH_Receive_Store_Forward */ |
| 517 | This parameter can be a value of @ref ETH_Receive_Store_Forward */ |
517 | |
| 518 | 518 | uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. |
|
| 519 | uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. |
519 | This parameter can be a value of @ref ETH_Flush_Received_Frame */ |
| 520 | This parameter can be a value of @ref ETH_Flush_Received_Frame */ |
520 | |
| 521 | 521 | uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. |
|
| 522 | uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. |
522 | This parameter can be a value of @ref ETH_Transmit_Store_Forward */ |
| 523 | This parameter can be a value of @ref ETH_Transmit_Store_Forward */ |
523 | |
| 524 | 524 | uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. |
|
| 525 | uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. |
525 | This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ |
| 526 | This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ |
526 | |
| 527 | 527 | uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. |
|
| 528 | uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. |
528 | This parameter can be a value of @ref ETH_Forward_Error_Frames */ |
| 529 | This parameter can be a value of @ref ETH_Forward_Error_Frames */ |
529 | |
| 530 | 530 | uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error |
|
| 531 | uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error |
531 | and length less than 64 bytes) including pad-bytes and CRC) |
| 532 | and length less than 64 bytes) including pad-bytes and CRC) |
532 | This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ |
| 533 | This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ |
533 | |
| 534 | 534 | uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. |
|
| 535 | uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. |
535 | This parameter can be a value of @ref ETH_Receive_Threshold_Control */ |
| 536 | This parameter can be a value of @ref ETH_Receive_Threshold_Control */ |
536 | |
| 537 | 537 | uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second |
|
| 538 | uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second |
538 | frame of Transmit data even before obtaining the status for the first frame. |
| 539 | frame of Transmit data even before obtaining the status for the first frame. |
539 | This parameter can be a value of @ref ETH_Second_Frame_Operate */ |
| 540 | This parameter can be a value of @ref ETH_Second_Frame_Operate */ |
540 | |
| 541 | 541 | uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. |
|
| 542 | uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. |
542 | This parameter can be a value of @ref ETH_Address_Aligned_Beats */ |
| 543 | This parameter can be a value of @ref ETH_Address_Aligned_Beats */ |
543 | |
| 544 | 544 | uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. |
|
| 545 | uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. |
545 | This parameter can be a value of @ref ETH_Fixed_Burst */ |
| 546 | This parameter can be a value of @ref ETH_Fixed_Burst */ |
546 | |
| 547 | 547 | uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. |
|
| 548 | uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. |
548 | This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ |
| 549 | This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ |
549 | |
| 550 | 550 | uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. |
|
| 551 | uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. |
551 | This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ |
| 552 | This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ |
552 | |
| 553 | 553 | uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) |
|
| 554 | uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) |
554 | This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ |
| 555 | This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ |
555 | |
| 556 | 556 | uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. |
|
| 557 | uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. |
557 | This parameter can be a value of @ref ETH_DMA_Arbitration */ |
| 558 | This parameter can be a value of @ref ETH_DMA_Arbitration */ |
558 | } ETH_DMAInitTypeDef; |
| 559 | } ETH_DMAInitTypeDef; |
559 | |
| 560 | 560 | ||
| 561 | 561 | /** |
|
| 562 | /** |
562 | * @brief ETH DMA Descriptors data structure definition |
| 563 | * @brief ETH DMA Descriptors data structure definition |
563 | */ |
| 564 | */ |
564 | |
| 565 | 565 | typedef struct |
|
| 566 | typedef struct |
566 | { |
| 567 | { |
567 | __IO uint32_t Status; /*!< Status */ |
| 568 | __IO uint32_t Status; /*!< Status */ |
568 | |
| 569 | 569 | uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ |
|
| 570 | uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ |
570 | |
| 571 | 571 | uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ |
|
| 572 | uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ |
572 | |
| 573 | 573 | uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ |
|
| 574 | uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ |
574 | |
| 575 | 575 | } ETH_DMADescTypeDef; |
|
| 576 | } ETH_DMADescTypeDef; |
576 | |
| 577 | 577 | /** |
|
| 578 | /** |
578 | * @brief Received Frame Information structure definition |
| 579 | * @brief Received Frame Informations structure definition |
579 | */ |
| 580 | */ |
580 | typedef struct |
| 581 | typedef struct |
581 | { |
| 582 | { |
582 | ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ |
| 583 | ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ |
583 | |
| 584 | 584 | ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ |
|
| 585 | ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ |
585 | |
| 586 | 586 | uint32_t SegCount; /*!< Segment count */ |
|
| 587 | uint32_t SegCount; /*!< Segment count */ |
587 | |
| 588 | 588 | uint32_t length; /*!< Frame length */ |
|
| 589 | uint32_t length; /*!< Frame length */ |
589 | |
| 590 | 590 | uint32_t buffer; /*!< Frame buffer */ |
|
| 591 | uint32_t buffer; /*!< Frame buffer */ |
591 | |
| 592 | 592 | } ETH_DMARxFrameInfos; |
|
| 593 | } ETH_DMARxFrameInfos; |
593 | |
| 594 | 594 | /** |
|
| 595 | /** |
595 | * @brief ETH Handle Structure definition |
| 596 | * @brief ETH Handle Structure definition |
596 | */ |
| 597 | */ |
597 | |
| 598 | 598 | #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) |
|
| 599 | #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) |
599 | typedef struct __ETH_HandleTypeDef |
| 600 | typedef struct __ETH_HandleTypeDef |
600 | #else |
| 601 | #else |
601 | typedef struct |
| 602 | typedef struct |
602 | #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ |
| 603 | #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ |
603 | { |
| 604 | { |
604 | ETH_TypeDef *Instance; /*!< Register base address */ |
| 605 | ETH_TypeDef *Instance; /*!< Register base address */ |
605 | |
| 606 | 606 | ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ |
|
| 607 | ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ |
607 | |
| 608 | 608 | uint32_t LinkStatus; /*!< Ethernet link status */ |
|
| 609 | uint32_t LinkStatus; /*!< Ethernet link status */ |
609 | |
| 610 | 610 | ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ |
|
| 611 | ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ |
611 | |
| 612 | 612 | ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ |
|
| 613 | ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ |
613 | |
| 614 | 614 | ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ |
|
| 615 | ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ |
615 | |
| 616 | 616 | __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ |
|
| 617 | __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ |
617 | |
| 618 | 618 | HAL_LockTypeDef Lock; /*!< ETH Lock */ |
|
| 619 | HAL_LockTypeDef Lock; /*!< ETH Lock */ |
619 | |
| 620 | 620 | #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) |
|
| 621 | #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) |
621 | |
| 622 | 622 | void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Tx Complete Callback */ |
|
| 623 | void (* TxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Tx Complete Callback */ |
623 | void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Rx Complete Callback */ |
| 624 | void (* RxCpltCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Rx Complete Callback */ |
624 | void (* DMAErrorCallback)(struct __ETH_HandleTypeDef *heth); /*!< DMA Error Callback */ |
| 625 | void (* DMAErrorCallback)(struct __ETH_HandleTypeDef *heth); /*!< DMA Error Callback */ |
625 | void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp Init callback */ |
| 626 | void (* MspInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp Init callback */ |
626 | void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp DeInit callback */ |
| 627 | void (* MspDeInitCallback)(struct __ETH_HandleTypeDef *heth); /*!< ETH Msp DeInit callback */ |
627 | |
| 628 | 628 | #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ |
|
| 629 | #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ |
629 | |
| 630 | 630 | } ETH_HandleTypeDef; |
|
| 631 | } ETH_HandleTypeDef; |
631 | |
| 632 | 632 | #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) |
|
| 633 | #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) |
633 | /** |
| 634 | /** |
634 | * @brief HAL ETH Callback ID enumeration definition |
| 635 | * @brief HAL ETH Callback ID enumeration definition |
635 | */ |
| 636 | */ |
636 | typedef enum |
| 637 | typedef enum |
637 | { |
| 638 | { |
638 | HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ |
| 639 | HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */ |
639 | HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ |
| 640 | HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */ |
640 | HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ |
| 641 | HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */ |
641 | HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ |
| 642 | HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */ |
642 | HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ |
| 643 | HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */ |
643 | |
| 644 | 644 | } HAL_ETH_CallbackIDTypeDef; |
|
| 645 | } HAL_ETH_CallbackIDTypeDef; |
645 | |
| 646 | 646 | /** |
|
| 647 | /** |
647 | * @brief HAL ETH Callback pointer definition |
| 648 | * @brief HAL ETH Callback pointer definition |
648 | */ |
| 649 | */ |
649 | typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth); /*!< pointer to an ETH callback function */ |
| 650 | typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef *heth); /*!< pointer to an ETH callback function */ |
650 | |
| 651 | 651 | #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ |
|
| 652 | #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ |
652 | |
| 653 | 653 | /** |
|
| 654 | /** |
654 | * @} |
| 655 | * @} |
655 | */ |
| 656 | */ |
656 | |
| 657 | 657 | /* Exported constants --------------------------------------------------------*/ |
|
| 658 | /* Exported constants --------------------------------------------------------*/ |
658 | /** @defgroup ETH_Exported_Constants ETH Exported Constants |
| 659 | /** @defgroup ETH_Exported_Constants ETH Exported Constants |
659 | * @{ |
| 660 | * @{ |
660 | */ |
| 661 | */ |
661 | |
| 662 | 662 | /** @defgroup ETH_Buffers_setting ETH Buffers setting |
|
| 663 | /** @defgroup ETH_Buffers_setting ETH Buffers setting |
663 | * @{ |
| 664 | * @{ |
664 | */ |
| 665 | */ |
665 | #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ |
| 666 | #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ |
666 | #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ |
| 667 | #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ |
667 | #define ETH_CRC 4U /*!< Ethernet CRC */ |
| 668 | #define ETH_CRC 4U /*!< Ethernet CRC */ |
668 | #define ETH_EXTRA 2U /*!< Extra bytes in some cases */ |
| 669 | #define ETH_EXTRA 2U /*!< Extra bytes in some cases */ |
669 | #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ |
| 670 | #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ |
670 | #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ |
| 671 | #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ |
671 | #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ |
| 672 | #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ |
672 | #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ |
| 673 | #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ |
673 | |
| 674 | 674 | /* Ethernet driver receive buffers are organized in a chained linked-list, when |
|
| 675 | /* Ethernet driver receive buffers are organized in a chained linked-list, when |
675 | an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO |
| 676 | an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO |
676 | to the driver receive buffers memory. |
| 677 | to the driver receive buffers memory. |
677 | |
| 678 | 678 | Depending on the size of the received ethernet packet and the size of |
|
| 679 | Depending on the size of the received ethernet packet and the size of |
679 | each ethernet driver receive buffer, the received packet can take one or more |
| 680 | each ethernet driver receive buffer, the received packet can take one or more |
680 | ethernet driver receive buffer. |
| 681 | ethernet driver receive buffer. |
681 | |
| 682 | 682 | In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE |
|
| 683 | In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE |
683 | and the total count of the driver receive buffers ETH_RXBUFNB. |
| 684 | and the total count of the driver receive buffers ETH_RXBUFNB. |
684 | |
| 685 | 685 | The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as |
|
| 686 | The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as |
686 | example, they can be reconfigured in the application layer to fit the application |
| 687 | example, they can be reconfigured in the application layer to fit the application |
687 | needs */ |
| 688 | needs */ |
688 | |
| 689 | 689 | /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet |
|
| 690 | /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet |
690 | packet */ |
| 691 | packet */ |
691 | #ifndef ETH_RX_BUF_SIZE |
| 692 | #ifndef ETH_RX_BUF_SIZE |
692 | #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE |
| 693 | #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE |
693 | #endif |
| 694 | #endif |
694 | |
| 695 | 695 | /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ |
|
| 696 | /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ |
696 | #ifndef ETH_RXBUFNB |
| 697 | #ifndef ETH_RXBUFNB |
697 | #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ |
| 698 | #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ |
698 | #endif |
| 699 | #endif |
699 | |
| 700 | 700 | ||
| 701 | 701 | /* Ethernet driver transmit buffers are organized in a chained linked-list, when |
|
| 702 | /* Ethernet driver transmit buffers are organized in a chained linked-list, when |
702 | an ethernet packet is transmitted, Tx-DMA will transfer the packet from the |
| 703 | an ethernet packet is transmitted, Tx-DMA will transfer the packet from the |
703 | driver transmit buffers memory to the TxFIFO. |
| 704 | driver transmit buffers memory to the TxFIFO. |
704 | |
| 705 | 705 | Depending on the size of the Ethernet packet to be transmitted and the size of |
|
| 706 | Depending on the size of the Ethernet packet to be transmitted and the size of |
706 | each ethernet driver transmit buffer, the packet to be transmitted can take |
| 707 | each ethernet driver transmit buffer, the packet to be transmitted can take |
707 | one or more ethernet driver transmit buffer. |
| 708 | one or more ethernet driver transmit buffer. |
708 | |
| 709 | 709 | In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE |
|
| 710 | In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE |
710 | and the total count of the driver transmit buffers ETH_TXBUFNB. |
| 711 | and the total count of the driver transmit buffers ETH_TXBUFNB. |
711 | |
| 712 | 712 | The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as |
|
| 713 | The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as |
713 | example, they can be reconfigured in the application layer to fit the application |
| 714 | example, they can be reconfigured in the application layer to fit the application |
714 | needs */ |
| 715 | needs */ |
715 | |
| 716 | 716 | /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet |
|
| 717 | /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet |
717 | packet */ |
| 718 | packet */ |
718 | #ifndef ETH_TX_BUF_SIZE |
| 719 | #ifndef ETH_TX_BUF_SIZE |
719 | #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE |
| 720 | #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE |
720 | #endif |
| 721 | #endif |
721 | |
| 722 | 722 | /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ |
|
| 723 | /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ |
723 | #ifndef ETH_TXBUFNB |
| 724 | #ifndef ETH_TXBUFNB |
724 | #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ |
| 725 | #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ |
725 | #endif |
| 726 | #endif |
726 | |
| 727 | 727 | /** |
|
| 728 | /** |
728 | * @} |
| 729 | * @} |
729 | */ |
| 730 | */ |
730 | |
| 731 | 731 | /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor |
|
| 732 | /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor |
732 | * @{ |
| 733 | * @{ |
733 | */ |
| 734 | */ |
734 | |
| 735 | 735 | /* |
|
| 736 | /* |
736 | DMA Tx Descriptor |
| 737 | DMA Tx Descriptor |
737 | ----------------------------------------------------------------------------------------------- |
| 738 | ----------------------------------------------------------------------------------------------- |
738 | TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | |
| 739 | TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | |
739 | ----------------------------------------------------------------------------------------------- |
| 740 | ----------------------------------------------------------------------------------------------- |
740 | TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | |
| 741 | TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | |
741 | ----------------------------------------------------------------------------------------------- |
| 742 | ----------------------------------------------------------------------------------------------- |
742 | TDES2 | Buffer1 Address [31:0] | |
| 743 | TDES2 | Buffer1 Address [31:0] | |
743 | ----------------------------------------------------------------------------------------------- |
| 744 | ----------------------------------------------------------------------------------------------- |
744 | TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | |
| 745 | TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | |
745 | ----------------------------------------------------------------------------------------------- |
| 746 | ----------------------------------------------------------------------------------------------- |
746 | */ |
| 747 | */ |
747 | |
| 748 | 748 | /** |
|
| 749 | /** |
749 | * @brief Bit definition of TDES0 register: DMA Tx descriptor status register |
| 750 | * @brief Bit definition of TDES0 register: DMA Tx descriptor status register |
750 | */ |
| 751 | */ |
751 | #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ |
| 752 | #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ |
752 | #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ |
| 753 | #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ |
753 | #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ |
| 754 | #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ |
754 | #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ |
| 755 | #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ |
755 | #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ |
| 756 | #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ |
756 | #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ |
| 757 | #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ |
757 | #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ |
| 758 | #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ |
758 | #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ |
| 759 | #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ |
759 | #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ |
| 760 | #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ |
760 | #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ |
| 761 | #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ |
761 | #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ |
| 762 | #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ |
762 | #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ |
| 763 | #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ |
763 | #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ |
| 764 | #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ |
764 | #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ |
| 765 | #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ |
765 | #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ |
| 766 | #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ |
766 | #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ |
| 767 | #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ |
767 | #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ |
| 768 | #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ |
768 | #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ |
| 769 | #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ |
769 | #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ |
| 770 | #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ |
770 | #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ |
| 771 | #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ |
771 | #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ |
| 772 | #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ |
772 | #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ |
| 773 | #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ |
773 | #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ |
| 774 | #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ |
774 | #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ |
| 775 | #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ |
775 | #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ |
| 776 | #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ |
776 | #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ |
| 777 | #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ |
777 | #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ |
| 778 | #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ |
778 | #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ |
| 779 | #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ |
779 | #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ |
| 780 | #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ |
780 | |
| 781 | 781 | /** |
|
| 782 | /** |
782 | * @brief Bit definition of TDES1 register |
| 783 | * @brief Bit definition of TDES1 register |
783 | */ |
| 784 | */ |
784 | #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ |
| 785 | #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ |
785 | #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ |
| 786 | #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ |
786 | |
| 787 | 787 | /** |
|
| 788 | /** |
788 | * @brief Bit definition of TDES2 register |
| 789 | * @brief Bit definition of TDES2 register |
789 | */ |
| 790 | */ |
790 | #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ |
| 791 | #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ |
791 | |
| 792 | 792 | /** |
|
| 793 | /** |
793 | * @brief Bit definition of TDES3 register |
| 794 | * @brief Bit definition of TDES3 register |
794 | */ |
| 795 | */ |
795 | #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ |
| 796 | #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ |
796 | |
| 797 | 797 | /** |
|
| 798 | /** |
798 | * @} |
| 799 | * @} |
799 | */ |
| 800 | */ |
800 | /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor |
| 801 | /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor |
801 | * @{ |
| 802 | * @{ |
802 | */ |
| 803 | */ |
803 | |
| 804 | 804 | /* |
|
| 805 | /* |
805 | DMA Rx Descriptor |
| 806 | DMA Rx Descriptor |
806 | -------------------------------------------------------------------------------------------------------------------- |
| 807 | -------------------------------------------------------------------------------------------------------------------- |
807 | RDES0 | OWN(31) | Status [30:0] | |
| 808 | RDES0 | OWN(31) | Status [30:0] | |
808 | --------------------------------------------------------------------------------------------------------------------- |
| 809 | --------------------------------------------------------------------------------------------------------------------- |
809 | RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | |
| 810 | RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | |
810 | --------------------------------------------------------------------------------------------------------------------- |
| 811 | --------------------------------------------------------------------------------------------------------------------- |
811 | RDES2 | Buffer1 Address [31:0] | |
| 812 | RDES2 | Buffer1 Address [31:0] | |
812 | --------------------------------------------------------------------------------------------------------------------- |
| 813 | --------------------------------------------------------------------------------------------------------------------- |
813 | RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | |
| 814 | RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | |
814 | --------------------------------------------------------------------------------------------------------------------- |
| 815 | --------------------------------------------------------------------------------------------------------------------- |
815 | */ |
| 816 | */ |
816 | |
| 817 | 817 | /** |
|
| 818 | /** |
818 | * @brief Bit definition of RDES0 register: DMA Rx descriptor status register |
| 819 | * @brief Bit definition of RDES0 register: DMA Rx descriptor status register |
819 | */ |
| 820 | */ |
820 | #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ |
| 821 | #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ |
821 | #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ |
| 822 | #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ |
822 | #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ |
| 823 | #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ |
823 | #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ |
| 824 | #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ |
824 | #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ |
| 825 | #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ |
825 | #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ |
| 826 | #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ |
826 | #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ |
| 827 | #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ |
827 | #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ |
| 828 | #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ |
828 | #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ |
| 829 | #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ |
829 | #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ |
| 830 | #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ |
830 | #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ |
| 831 | #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ |
831 | #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ |
| 832 | #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ |
832 | #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ |
| 833 | #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ |
833 | #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ |
| 834 | #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ |
834 | #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ |
| 835 | #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ |
835 | #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ |
| 836 | #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ |
836 | #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ |
| 837 | #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ |
837 | #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ |
| 838 | #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ |
838 | #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ |
| 839 | #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ |
839 | |
| 840 | 840 | /** |
|
| 841 | /** |
841 | * @brief Bit definition of RDES1 register |
| 842 | * @brief Bit definition of RDES1 register |
842 | */ |
| 843 | */ |
843 | #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ |
| 844 | #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ |
844 | #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ |
| 845 | #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ |
845 | #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ |
| 846 | #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ |
846 | #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ |
| 847 | #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ |
847 | #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ |
| 848 | #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ |
848 | |
| 849 | 849 | /** |
|
| 850 | /** |
850 | * @brief Bit definition of RDES2 register |
| 851 | * @brief Bit definition of RDES2 register |
851 | */ |
| 852 | */ |
852 | #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ |
| 853 | #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ |
853 | |
| 854 | 854 | /** |
|
| 855 | /** |
855 | * @brief Bit definition of RDES3 register |
| 856 | * @brief Bit definition of RDES3 register |
856 | */ |
| 857 | */ |
857 | #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ |
| 858 | #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ |
858 | |
| 859 | 859 | /** |
|
| 860 | /** |
860 | * @} |
| 861 | * @} |
861 | */ |
| 862 | */ |
862 | /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation |
| 863 | /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation |
863 | * @{ |
| 864 | * @{ |
864 | */ |
| 865 | */ |
865 | #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U |
| 866 | #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U |
866 | #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U |
| 867 | #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U |
867 | |
| 868 | 868 | /** |
|
| 869 | /** |
869 | * @} |
| 870 | * @} |
870 | */ |
| 871 | */ |
871 | /** @defgroup ETH_Speed ETH Speed |
| 872 | /** @defgroup ETH_Speed ETH Speed |
872 | * @{ |
| 873 | * @{ |
873 | */ |
| 874 | */ |
874 | #define ETH_SPEED_10M 0x00000000U |
| 875 | #define ETH_SPEED_10M 0x00000000U |
875 | #define ETH_SPEED_100M 0x00004000U |
| 876 | #define ETH_SPEED_100M 0x00004000U |
876 | |
| 877 | 877 | /** |
|
| 878 | /** |
878 | * @} |
| 879 | * @} |
879 | */ |
| 880 | */ |
880 | /** @defgroup ETH_Duplex_Mode ETH Duplex Mode |
| 881 | /** @defgroup ETH_Duplex_Mode ETH Duplex Mode |
881 | * @{ |
| 882 | * @{ |
882 | */ |
| 883 | */ |
883 | #define ETH_MODE_FULLDUPLEX 0x00000800U |
| 884 | #define ETH_MODE_FULLDUPLEX 0x00000800U |
884 | #define ETH_MODE_HALFDUPLEX 0x00000000U |
| 885 | #define ETH_MODE_HALFDUPLEX 0x00000000U |
885 | /** |
| 886 | /** |
886 | * @} |
| 887 | * @} |
887 | */ |
| 888 | */ |
888 | /** @defgroup ETH_Rx_Mode ETH Rx Mode |
| 889 | /** @defgroup ETH_Rx_Mode ETH Rx Mode |
889 | * @{ |
| 890 | * @{ |
890 | */ |
| 891 | */ |
891 | #define ETH_RXPOLLING_MODE 0x00000000U |
| 892 | #define ETH_RXPOLLING_MODE 0x00000000U |
892 | #define ETH_RXINTERRUPT_MODE 0x00000001U |
| 893 | #define ETH_RXINTERRUPT_MODE 0x00000001U |
893 | /** |
| 894 | /** |
894 | * @} |
| 895 | * @} |
895 | */ |
| 896 | */ |
896 | |
| 897 | 897 | /** @defgroup ETH_Checksum_Mode ETH Checksum Mode |
|
| 898 | /** @defgroup ETH_Checksum_Mode ETH Checksum Mode |
898 | * @{ |
| 899 | * @{ |
899 | */ |
| 900 | */ |
900 | #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U |
| 901 | #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U |
901 | #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U |
| 902 | #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U |
902 | /** |
| 903 | /** |
903 | * @} |
| 904 | * @} |
904 | */ |
| 905 | */ |
905 | |
| 906 | 906 | /** @defgroup ETH_Media_Interface ETH Media Interface |
|
| 907 | /** @defgroup ETH_Media_Interface ETH Media Interface |
907 | * @{ |
| 908 | * @{ |
908 | */ |
| 909 | */ |
909 | #define ETH_MEDIA_INTERFACE_MII 0x00000000U |
| 910 | #define ETH_MEDIA_INTERFACE_MII 0x00000000U |
910 | #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL) |
| 911 | #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL) |
911 | |
| 912 | 912 | /** |
|
| 913 | /** |
913 | * @} |
| 914 | * @} |
914 | */ |
| 915 | */ |
915 | |
| 916 | 916 | /** @defgroup ETH_Watchdog ETH Watchdog |
|
| 917 | /** @defgroup ETH_Watchdog ETH Watchdog |
917 | * @{ |
| 918 | * @{ |
918 | */ |
| 919 | */ |
919 | #define ETH_WATCHDOG_ENABLE 0x00000000U |
| 920 | #define ETH_WATCHDOG_ENABLE 0x00000000U |
920 | #define ETH_WATCHDOG_DISABLE 0x00800000U |
| 921 | #define ETH_WATCHDOG_DISABLE 0x00800000U |
921 | /** |
| 922 | /** |
922 | * @} |
| 923 | * @} |
923 | */ |
| 924 | */ |
924 | |
| 925 | 925 | /** @defgroup ETH_Jabber ETH Jabber |
|
| 926 | /** @defgroup ETH_Jabber ETH Jabber |
926 | * @{ |
| 927 | * @{ |
927 | */ |
| 928 | */ |
928 | #define ETH_JABBER_ENABLE 0x00000000U |
| 929 | #define ETH_JABBER_ENABLE 0x00000000U |
929 | #define ETH_JABBER_DISABLE 0x00400000U |
| 930 | #define ETH_JABBER_DISABLE 0x00400000U |
930 | /** |
| 931 | /** |
931 | * @} |
| 932 | * @} |
932 | */ |
| 933 | */ |
933 | |
| 934 | 934 | /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap |
|
| 935 | /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap |
935 | * @{ |
| 936 | * @{ |
936 | */ |
| 937 | */ |
937 | #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ |
| 938 | #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ |
938 | #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ |
| 939 | #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ |
939 | #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ |
| 940 | #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ |
940 | #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ |
| 941 | #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ |
941 | #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ |
| 942 | #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ |
942 | #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ |
| 943 | #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ |
943 | #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ |
| 944 | #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ |
944 | #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ |
| 945 | #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ |
945 | /** |
| 946 | /** |
946 | * @} |
| 947 | * @} |
947 | */ |
| 948 | */ |
948 | |
| 949 | 949 | /** @defgroup ETH_Carrier_Sense ETH Carrier Sense |
|
| 950 | /** @defgroup ETH_Carrier_Sense ETH Carrier Sense |
950 | * @{ |
| 951 | * @{ |
951 | */ |
| 952 | */ |
952 | #define ETH_CARRIERSENCE_ENABLE 0x00000000U |
| 953 | #define ETH_CARRIERSENCE_ENABLE 0x00000000U |
953 | #define ETH_CARRIERSENCE_DISABLE 0x00010000U |
| 954 | #define ETH_CARRIERSENCE_DISABLE 0x00010000U |
954 | /** |
| 955 | /** |
955 | * @} |
| 956 | * @} |
956 | */ |
| 957 | */ |
957 | |
| 958 | 958 | /** @defgroup ETH_Receive_Own ETH Receive Own |
|
| 959 | /** @defgroup ETH_Receive_Own ETH Receive Own |
959 | * @{ |
| 960 | * @{ |
960 | */ |
| 961 | */ |
961 | #define ETH_RECEIVEOWN_ENABLE 0x00000000U |
| 962 | #define ETH_RECEIVEOWN_ENABLE 0x00000000U |
962 | #define ETH_RECEIVEOWN_DISABLE 0x00002000U |
| 963 | #define ETH_RECEIVEOWN_DISABLE 0x00002000U |
963 | /** |
| 964 | /** |
964 | * @} |
| 965 | * @} |
965 | */ |
| 966 | */ |
966 | |
| 967 | 967 | /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode |
|
| 968 | /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode |
968 | * @{ |
| 969 | * @{ |
969 | */ |
| 970 | */ |
970 | #define ETH_LOOPBACKMODE_ENABLE 0x00001000U |
| 971 | #define ETH_LOOPBACKMODE_ENABLE 0x00001000U |
971 | #define ETH_LOOPBACKMODE_DISABLE 0x00000000U |
| 972 | #define ETH_LOOPBACKMODE_DISABLE 0x00000000U |
972 | /** |
| 973 | /** |
973 | * @} |
| 974 | * @} |
974 | */ |
| 975 | */ |
975 | |
| 976 | 976 | /** @defgroup ETH_Checksum_Offload ETH Checksum Offload |
|
| 977 | /** @defgroup ETH_Checksum_Offload ETH Checksum Offload |
977 | * @{ |
| 978 | * @{ |
978 | */ |
| 979 | */ |
979 | #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U |
| 980 | #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U |
980 | #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U |
| 981 | #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U |
981 | /** |
| 982 | /** |
982 | * @} |
| 983 | * @} |
983 | */ |
| 984 | */ |
984 | |
| 985 | 985 | /** @defgroup ETH_Retry_Transmission ETH Retry Transmission |
|
| 986 | /** @defgroup ETH_Retry_Transmission ETH Retry Transmission |
986 | * @{ |
| 987 | * @{ |
987 | */ |
| 988 | */ |
988 | #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U |
| 989 | #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U |
989 | #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U |
| 990 | #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U |
990 | /** |
| 991 | /** |
991 | * @} |
| 992 | * @} |
992 | */ |
| 993 | */ |
993 | |
| 994 | 994 | /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip |
|
| 995 | /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip |
995 | * @{ |
| 996 | * @{ |
996 | */ |
| 997 | */ |
997 | #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U |
| 998 | #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U |
998 | #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U |
| 999 | #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U |
999 | /** |
| 1000 | /** |
1000 | * @} |
| 1001 | * @} |
1001 | */ |
| 1002 | */ |
1002 | |
| 1003 | 1003 | /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit |
|
| 1004 | /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit |
1004 | * @{ |
| 1005 | * @{ |
1005 | */ |
| 1006 | */ |
1006 | #define ETH_BACKOFFLIMIT_10 0x00000000U |
| 1007 | #define ETH_BACKOFFLIMIT_10 0x00000000U |
1007 | #define ETH_BACKOFFLIMIT_8 0x00000020U |
| 1008 | #define ETH_BACKOFFLIMIT_8 0x00000020U |
1008 | #define ETH_BACKOFFLIMIT_4 0x00000040U |
| 1009 | #define ETH_BACKOFFLIMIT_4 0x00000040U |
1009 | #define ETH_BACKOFFLIMIT_1 0x00000060U |
| 1010 | #define ETH_BACKOFFLIMIT_1 0x00000060U |
1010 | /** |
| 1011 | /** |
1011 | * @} |
| 1012 | * @} |
1012 | */ |
| 1013 | */ |
1013 | |
| 1014 | 1014 | /** @defgroup ETH_Deferral_Check ETH Deferral Check |
|
| 1015 | /** @defgroup ETH_Deferral_Check ETH Deferral Check |
1015 | * @{ |
| 1016 | * @{ |
1016 | */ |
| 1017 | */ |
1017 | #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U |
| 1018 | #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U |
1018 | #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U |
| 1019 | #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U |
1019 | /** |
| 1020 | /** |
1020 | * @} |
| 1021 | * @} |
1021 | */ |
| 1022 | */ |
1022 | |
| 1023 | 1023 | /** @defgroup ETH_Receive_All ETH Receive All |
|
| 1024 | /** @defgroup ETH_Receive_All ETH Receive All |
1024 | * @{ |
| 1025 | * @{ |
1025 | */ |
| 1026 | */ |
1026 | #define ETH_RECEIVEALL_ENABLE 0x80000000U |
| 1027 | #define ETH_RECEIVEALL_ENABLE 0x80000000U |
1027 | #define ETH_RECEIVEAll_DISABLE 0x00000000U |
| 1028 | #define ETH_RECEIVEAll_DISABLE 0x00000000U |
1028 | /** |
| 1029 | /** |
1029 | * @} |
| 1030 | * @} |
1030 | */ |
| 1031 | */ |
1031 | |
| 1032 | 1032 | /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter |
|
| 1033 | /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter |
1033 | * @{ |
| 1034 | * @{ |
1034 | */ |
| 1035 | */ |
1035 | #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U |
| 1036 | #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U |
1036 | #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U |
| 1037 | #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U |
1037 | #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U |
| 1038 | #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U |
1038 | /** |
| 1039 | /** |
1039 | * @} |
| 1040 | * @} |
1040 | */ |
| 1041 | */ |
1041 | |
| 1042 | 1042 | /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames |
|
| 1043 | /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames |
1043 | * @{ |
| 1044 | * @{ |
1044 | */ |
| 1045 | */ |
1045 | #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ |
| 1046 | #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ |
1046 | #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ |
| 1047 | #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ |
1047 | #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ |
| 1048 | #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ |
1048 | /** |
| 1049 | /** |
1049 | * @} |
| 1050 | * @} |
1050 | */ |
| 1051 | */ |
1051 | |
| 1052 | 1052 | /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception |
|
| 1053 | /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception |
1053 | * @{ |
| 1054 | * @{ |
1054 | */ |
| 1055 | */ |
1055 | #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U |
| 1056 | #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U |
1056 | #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U |
| 1057 | #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U |
1057 | /** |
| 1058 | /** |
1058 | * @} |
| 1059 | * @} |
1059 | */ |
| 1060 | */ |
1060 | |
| 1061 | 1061 | /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter |
|
| 1062 | /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter |
1062 | * @{ |
| 1063 | * @{ |
1063 | */ |
| 1064 | */ |
1064 | #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U |
| 1065 | #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U |
1065 | #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U |
| 1066 | #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U |
1066 | /** |
| 1067 | /** |
1067 | * @} |
| 1068 | * @} |
1068 | */ |
| 1069 | */ |
1069 | |
| 1070 | 1070 | /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode |
|
| 1071 | /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode |
1071 | * @{ |
| 1072 | * @{ |
1072 | */ |
| 1073 | */ |
1073 | #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U |
| 1074 | #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U |
1074 | #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U |
| 1075 | #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U |
1075 | /** |
| 1076 | /** |
1076 | * @} |
| 1077 | * @} |
1077 | */ |
| 1078 | */ |
1078 | |
| 1079 | 1079 | /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter |
|
| 1080 | /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter |
1080 | * @{ |
| 1081 | * @{ |
1081 | */ |
| 1082 | */ |
1082 | #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U |
| 1083 | #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U |
1083 | #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U |
| 1084 | #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U |
1084 | #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U |
| 1085 | #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U |
1085 | #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U |
| 1086 | #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U |
1086 | /** |
| 1087 | /** |
1087 | * @} |
| 1088 | * @} |
1088 | */ |
| 1089 | */ |
1089 | |
| 1090 | 1090 | /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter |
|
| 1091 | /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter |
1091 | * @{ |
| 1092 | * @{ |
1092 | */ |
| 1093 | */ |
1093 | #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U |
| 1094 | #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U |
1094 | #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U |
| 1095 | #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U |
1095 | #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U |
| 1096 | #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U |
1096 | /** |
| 1097 | /** |
1097 | * @} |
| 1098 | * @} |
1098 | */ |
| 1099 | */ |
1099 | |
| 1100 | 1100 | /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause |
|
| 1101 | /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause |
1101 | * @{ |
| 1102 | * @{ |
1102 | */ |
| 1103 | */ |
1103 | #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U |
| 1104 | #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U |
1104 | #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U |
| 1105 | #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U |
1105 | /** |
| 1106 | /** |
1106 | * @} |
| 1107 | * @} |
1107 | */ |
| 1108 | */ |
1108 | |
| 1109 | 1109 | /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold |
|
| 1110 | /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold |
1110 | * @{ |
| 1111 | * @{ |
1111 | */ |
| 1112 | */ |
1112 | #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ |
| 1113 | #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ |
1113 | #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ |
| 1114 | #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ |
1114 | #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ |
| 1115 | #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ |
1115 | #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ |
| 1116 | #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ |
1116 | /** |
| 1117 | /** |
1117 | * @} |
| 1118 | * @} |
1118 | */ |
| 1119 | */ |
1119 | |
| 1120 | 1120 | /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect |
|
| 1121 | /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect |
1121 | * @{ |
| 1122 | * @{ |
1122 | */ |
| 1123 | */ |
1123 | #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U |
| 1124 | #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U |
1124 | #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U |
| 1125 | #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U |
1125 | /** |
| 1126 | /** |
1126 | * @} |
| 1127 | * @} |
1127 | */ |
| 1128 | */ |
1128 | |
| 1129 | 1129 | /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control |
|
| 1130 | /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control |
1130 | * @{ |
| 1131 | * @{ |
1131 | */ |
| 1132 | */ |
1132 | #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U |
| 1133 | #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U |
1133 | #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U |
| 1134 | #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U |
1134 | /** |
| 1135 | /** |
1135 | * @} |
| 1136 | * @} |
1136 | */ |
| 1137 | */ |
1137 | |
| 1138 | 1138 | /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control |
|
| 1139 | /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control |
1139 | * @{ |
| 1140 | * @{ |
1140 | */ |
| 1141 | */ |
1141 | #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U |
| 1142 | #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U |
1142 | #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U |
| 1143 | #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U |
1143 | /** |
| 1144 | /** |
1144 | * @} |
| 1145 | * @} |
1145 | */ |
| 1146 | */ |
1146 | |
| 1147 | 1147 | /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison |
|
| 1148 | /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison |
1148 | * @{ |
| 1149 | * @{ |
1149 | */ |
| 1150 | */ |
1150 | #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U |
| 1151 | #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U |
1151 | #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U |
| 1152 | #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U |
1152 | /** |
| 1153 | /** |
1153 | * @} |
| 1154 | * @} |
1154 | */ |
| 1155 | */ |
1155 | |
| 1156 | 1156 | /** @defgroup ETH_MAC_addresses ETH MAC addresses |
|
| 1157 | /** @defgroup ETH_MAC_addresses ETH MAC addresses |
1157 | * @{ |
| 1158 | * @{ |
1158 | */ |
| 1159 | */ |
1159 | #define ETH_MAC_ADDRESS0 0x00000000U |
| 1160 | #define ETH_MAC_ADDRESS0 0x00000000U |
1160 | #define ETH_MAC_ADDRESS1 0x00000008U |
| 1161 | #define ETH_MAC_ADDRESS1 0x00000008U |
1161 | #define ETH_MAC_ADDRESS2 0x00000010U |
| 1162 | #define ETH_MAC_ADDRESS2 0x00000010U |
1162 | #define ETH_MAC_ADDRESS3 0x00000018U |
| 1163 | #define ETH_MAC_ADDRESS3 0x00000018U |
1163 | /** |
| 1164 | /** |
1164 | * @} |
| 1165 | * @} |
1165 | */ |
| 1166 | */ |
1166 | |
| 1167 | 1167 | /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA |
|
| 1168 | /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA |
1168 | * @{ |
| 1169 | * @{ |
1169 | */ |
| 1170 | */ |
1170 | #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U |
| 1171 | #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U |
1171 | #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U |
| 1172 | #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U |
1172 | /** |
| 1173 | /** |
1173 | * @} |
| 1174 | * @} |
1174 | */ |
| 1175 | */ |
1175 | |
| 1176 | 1176 | /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes |
|
| 1177 | /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes |
1177 | * @{ |
| 1178 | * @{ |
1178 | */ |
| 1179 | */ |
1179 | #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ |
| 1180 | #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ |
1180 | #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ |
| 1181 | #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ |
1181 | #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ |
| 1182 | #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ |
1182 | #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ |
| 1183 | #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ |
1183 | #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ |
| 1184 | #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ |
1184 | #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ |
| 1185 | #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ |
1185 | /** |
| 1186 | /** |
1186 | * @} |
| 1187 | * @} |
1187 | */ |
| 1188 | */ |
1188 | |
| 1189 | 1189 | /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame |
|
| 1190 | /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame |
1190 | * @{ |
| 1191 | * @{ |
1191 | */ |
| 1192 | */ |
1192 | #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U |
| 1193 | #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U |
1193 | #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U |
| 1194 | #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U |
1194 | /** |
| 1195 | /** |
1195 | * @} |
| 1196 | * @} |
1196 | */ |
| 1197 | */ |
1197 | |
| 1198 | 1198 | /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward |
|
| 1199 | /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward |
1199 | * @{ |
| 1200 | * @{ |
1200 | */ |
| 1201 | */ |
1201 | #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U |
| 1202 | #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U |
1202 | #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U |
| 1203 | #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U |
1203 | /** |
| 1204 | /** |
1204 | * @} |
| 1205 | * @} |
1205 | */ |
| 1206 | */ |
1206 | |
| 1207 | 1207 | /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame |
|
| 1208 | /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame |
1208 | * @{ |
| 1209 | * @{ |
1209 | */ |
| 1210 | */ |
1210 | #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U |
| 1211 | #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U |
1211 | #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U |
| 1212 | #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U |
1212 | /** |
| 1213 | /** |
1213 | * @} |
| 1214 | * @} |
1214 | */ |
| 1215 | */ |
1215 | |
| 1216 | 1216 | /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward |
|
| 1217 | /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward |
1217 | * @{ |
| 1218 | * @{ |
1218 | */ |
| 1219 | */ |
1219 | #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U |
| 1220 | #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U |
1220 | #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U |
| 1221 | #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U |
1221 | /** |
| 1222 | /** |
1222 | * @} |
| 1223 | * @} |
1223 | */ |
| 1224 | */ |
1224 | |
| 1225 | 1225 | /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control |
|
| 1226 | /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control |
1226 | * @{ |
| 1227 | * @{ |
1227 | */ |
| 1228 | */ |
1228 | #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| 1229 | #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ |
1229 | #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| 1230 | #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ |
1230 | #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| 1231 | #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ |
1231 | #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| 1232 | #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ |
1232 | #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| 1233 | #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ |
1233 | #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| 1234 | #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ |
1234 | #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| 1235 | #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ |
1235 | #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| 1236 | #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ |
1236 | /** |
| 1237 | /** |
1237 | * @} |
| 1238 | * @} |
1238 | */ |
| 1239 | */ |
1239 | |
| 1240 | 1240 | /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames |
|
| 1241 | /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames |
1241 | * @{ |
| 1242 | * @{ |
1242 | */ |
| 1243 | */ |
1243 | #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U |
| 1244 | #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U |
1244 | #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U |
| 1245 | #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U |
1245 | /** |
| 1246 | /** |
1246 | * @} |
| 1247 | * @} |
1247 | */ |
| 1248 | */ |
1248 | |
| 1249 | 1249 | /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames |
|
| 1250 | /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames |
1250 | * @{ |
| 1251 | * @{ |
1251 | */ |
| 1252 | */ |
1252 | #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U |
| 1253 | #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U |
1253 | #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U |
| 1254 | #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U |
1254 | /** |
| 1255 | /** |
1255 | * @} |
| 1256 | * @} |
1256 | */ |
| 1257 | */ |
1257 | |
| 1258 | 1258 | /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control |
|
| 1259 | /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control |
1259 | * @{ |
| 1260 | * @{ |
1260 | */ |
| 1261 | */ |
1261 | #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ |
| 1262 | #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ |
1262 | #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ |
| 1263 | #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ |
1263 | #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ |
| 1264 | #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ |
1264 | #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ |
| 1265 | #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ |
1265 | /** |
| 1266 | /** |
1266 | * @} |
| 1267 | * @} |
1267 | */ |
| 1268 | */ |
1268 | |
| 1269 | 1269 | /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate |
|
| 1270 | /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate |
1270 | * @{ |
| 1271 | * @{ |
1271 | */ |
| 1272 | */ |
1272 | #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U |
| 1273 | #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U |
1273 | #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U |
| 1274 | #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U |
1274 | /** |
| 1275 | /** |
1275 | * @} |
| 1276 | * @} |
1276 | */ |
| 1277 | */ |
1277 | |
| 1278 | 1278 | /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats |
|
| 1279 | /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats |
1279 | * @{ |
| 1280 | * @{ |
1280 | */ |
| 1281 | */ |
1281 | #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U |
| 1282 | #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U |
1282 | #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U |
| 1283 | #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U |
1283 | /** |
| 1284 | /** |
1284 | * @} |
| 1285 | * @} |
1285 | */ |
| 1286 | */ |
1286 | |
| 1287 | 1287 | /** @defgroup ETH_Fixed_Burst ETH Fixed Burst |
|
| 1288 | /** @defgroup ETH_Fixed_Burst ETH Fixed Burst |
1288 | * @{ |
| 1289 | * @{ |
1289 | */ |
| 1290 | */ |
1290 | #define ETH_FIXEDBURST_ENABLE 0x00010000U |
| 1291 | #define ETH_FIXEDBURST_ENABLE 0x00010000U |
1291 | #define ETH_FIXEDBURST_DISABLE 0x00000000U |
| 1292 | #define ETH_FIXEDBURST_DISABLE 0x00000000U |
1292 | /** |
| 1293 | /** |
1293 | * @} |
| 1294 | * @} |
1294 | */ |
| 1295 | */ |
1295 | |
| 1296 | 1296 | /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length |
|
| 1297 | /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length |
1297 | * @{ |
| 1298 | * @{ |
1298 | */ |
| 1299 | */ |
1299 | #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| 1300 | #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
1300 | #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| 1301 | #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
1301 | #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| 1302 | #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
1302 | #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| 1303 | #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
1303 | #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| 1304 | #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
1304 | #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| 1305 | #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
1305 | #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| 1306 | #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
1306 | #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| 1307 | #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
1307 | #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| 1308 | #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
1308 | #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| 1309 | #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
1309 | #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| 1310 | #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
1310 | #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| 1311 | #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
1311 | /** |
| 1312 | /** |
1312 | * @} |
| 1313 | * @} |
1313 | */ |
| 1314 | */ |
1314 | |
| 1315 | 1315 | /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length |
|
| 1316 | /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length |
1316 | * @{ |
| 1317 | * @{ |
1317 | */ |
| 1318 | */ |
1318 | #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| 1319 | #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
1319 | #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| 1320 | #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
1320 | #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| 1321 | #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
1321 | #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| 1322 | #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
1322 | #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| 1323 | #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
1323 | #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| 1324 | #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
1324 | #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| 1325 | #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
1325 | #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| 1326 | #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
1326 | #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| 1327 | #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
1327 | #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| 1328 | #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
1328 | #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| 1329 | #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
1329 | #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| 1330 | #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
1330 | |
| 1331 | 1331 | /** |
|
| 1332 | /** |
1332 | * @} |
| 1333 | * @} |
1333 | */ |
| 1334 | */ |
1334 | |
| 1335 | 1335 | /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration |
|
| 1336 | /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration |
1336 | * @{ |
| 1337 | * @{ |
1337 | */ |
| 1338 | */ |
1338 | #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U |
| 1339 | #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U |
1339 | #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U |
| 1340 | #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U |
1340 | #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U |
| 1341 | #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U |
1341 | #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U |
| 1342 | #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U |
1342 | #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U |
| 1343 | #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U |
1343 | /** |
| 1344 | /** |
1344 | * @} |
| 1345 | * @} |
1345 | */ |
| 1346 | */ |
1346 | |
| 1347 | 1347 | /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment |
|
| 1348 | /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment |
1348 | * @{ |
| 1349 | * @{ |
1349 | */ |
| 1350 | */ |
1350 | #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ |
| 1351 | #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ |
1351 | #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ |
| 1352 | #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ |
1352 | /** |
| 1353 | /** |
1353 | * @} |
| 1354 | * @} |
1354 | */ |
| 1355 | */ |
1355 | |
| 1356 | 1356 | /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control |
|
| 1357 | /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control |
1357 | * @{ |
| 1358 | * @{ |
1358 | */ |
| 1359 | */ |
1359 | #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ |
| 1360 | #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ |
1360 | #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ |
| 1361 | #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ |
1361 | #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ |
| 1362 | #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ |
1362 | #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ |
| 1363 | #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ |
1363 | /** |
| 1364 | /** |
1364 | * @} |
| 1365 | * @} |
1365 | */ |
| 1366 | */ |
1366 | |
| 1367 | 1367 | /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers |
|
| 1368 | /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers |
1368 | * @{ |
| 1369 | * @{ |
1369 | */ |
| 1370 | */ |
1370 | #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ |
| 1371 | #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ |
1371 | #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ |
| 1372 | #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ |
1372 | /** |
| 1373 | /** |
1373 | * @} |
| 1374 | * @} |
1374 | */ |
| 1375 | */ |
1375 | |
| 1376 | 1376 | /** @defgroup ETH_PMT_Flags ETH PMT Flags |
|
| 1377 | /** @defgroup ETH_PMT_Flags ETH PMT Flags |
1377 | * @{ |
| 1378 | * @{ |
1378 | */ |
| 1379 | */ |
1379 | #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ |
| 1380 | #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ |
1380 | #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ |
| 1381 | #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ |
1381 | #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ |
| 1382 | #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ |
1382 | /** |
| 1383 | /** |
1383 | * @} |
| 1384 | * @} |
1384 | */ |
| 1385 | */ |
1385 | |
| 1386 | 1386 | /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts |
|
| 1387 | /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts |
1387 | * @{ |
| 1388 | * @{ |
1388 | */ |
| 1389 | */ |
1389 | #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ |
| 1390 | #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ |
1390 | #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ |
| 1391 | #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ |
1391 | #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ |
| 1392 | #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ |
1392 | /** |
| 1393 | /** |
1393 | * @} |
| 1394 | * @} |
1394 | */ |
| 1395 | */ |
1395 | |
| 1396 | 1396 | /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts |
|
| 1397 | /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts |
1397 | * @{ |
| 1398 | * @{ |
1398 | */ |
| 1399 | */ |
1399 | #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ |
| 1400 | #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ |
1400 | #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ |
| 1401 | #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ |
1401 | #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ |
| 1402 | #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ |
1402 | /** |
| 1403 | /** |
1403 | * @} |
| 1404 | * @} |
1404 | */ |
| 1405 | */ |
1405 | |
| 1406 | 1406 | /** @defgroup ETH_MAC_Flags ETH MAC Flags |
|
| 1407 | /** @defgroup ETH_MAC_Flags ETH MAC Flags |
1407 | * @{ |
| 1408 | * @{ |
1408 | */ |
| 1409 | */ |
1409 | #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ |
| 1410 | #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ |
1410 | #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ |
| 1411 | #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ |
1411 | #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ |
| 1412 | #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ |
1412 | #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ |
| 1413 | #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ |
1413 | #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ |
| 1414 | #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ |
1414 | /** |
| 1415 | /** |
1415 | * @} |
| 1416 | * @} |
1416 | */ |
| 1417 | */ |
1417 | |
| 1418 | 1418 | /** @defgroup ETH_DMA_Flags ETH DMA Flags |
|
| 1419 | /** @defgroup ETH_DMA_Flags ETH DMA Flags |
1419 | * @{ |
| 1420 | * @{ |
1420 | */ |
| 1421 | */ |
1421 | #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ |
| 1422 | #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ |
1422 | #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ |
| 1423 | #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ |
1423 | #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ |
| 1424 | #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ |
1424 | #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ |
| 1425 | #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ |
1425 | #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ |
| 1426 | #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ |
1426 | #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ |
| 1427 | #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ |
1427 | #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ |
| 1428 | #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ |
1428 | #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ |
| 1429 | #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ |
1429 | #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ |
| 1430 | #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ |
1430 | #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ |
| 1431 | #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ |
1431 | #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ |
| 1432 | #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ |
1432 | #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ |
| 1433 | #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ |
1433 | #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ |
| 1434 | #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ |
1434 | #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ |
| 1435 | #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ |
1435 | #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ |
| 1436 | #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ |
1436 | #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ |
| 1437 | #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ |
1437 | #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ |
| 1438 | #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ |
1438 | #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ |
| 1439 | #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ |
1439 | #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ |
| 1440 | #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ |
1440 | #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ |
| 1441 | #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ |
1441 | #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ |
| 1442 | #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ |
1442 | /** |
| 1443 | /** |
1443 | * @} |
| 1444 | * @} |
1444 | */ |
| 1445 | */ |
1445 | |
| 1446 | 1446 | /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts |
|
| 1447 | /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts |
1447 | * @{ |
| 1448 | * @{ |
1448 | */ |
| 1449 | */ |
1449 | #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ |
| 1450 | #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ |
1450 | #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ |
| 1451 | #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ |
1451 | #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ |
| 1452 | #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ |
1452 | #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ |
| 1453 | #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ |
1453 | #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ |
| 1454 | #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ |
1454 | /** |
| 1455 | /** |
1455 | * @} |
| 1456 | * @} |
1456 | */ |
| 1457 | */ |
1457 | |
| 1458 | 1458 | /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts |
|
| 1459 | /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts |
1459 | * @{ |
| 1460 | * @{ |
1460 | */ |
| 1461 | */ |
1461 | #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ |
| 1462 | #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ |
1462 | #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ |
| 1463 | #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ |
1463 | #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ |
| 1464 | #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ |
1464 | #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ |
| 1465 | #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ |
1465 | #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ |
| 1466 | #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ |
1466 | #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ |
| 1467 | #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ |
1467 | #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ |
| 1468 | #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ |
1468 | #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ |
| 1469 | #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ |
1469 | #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ |
| 1470 | #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ |
1470 | #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ |
| 1471 | #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ |
1471 | #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ |
| 1472 | #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ |
1472 | #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ |
| 1473 | #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ |
1473 | #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ |
| 1474 | #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ |
1474 | #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ |
| 1475 | #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ |
1475 | #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ |
| 1476 | #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ |
1476 | #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ |
| 1477 | #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ |
1477 | #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ |
| 1478 | #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ |
1478 | #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ |
| 1479 | #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ |
1479 | /** |
| 1480 | /** |
1480 | * @} |
| 1481 | * @} |
1481 | */ |
| 1482 | */ |
1482 | |
| 1483 | 1483 | /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state |
|
| 1484 | /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state |
1484 | * @{ |
| 1485 | * @{ |
1485 | */ |
| 1486 | */ |
1486 | #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ |
| 1487 | #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ |
1487 | #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ |
| 1488 | #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ |
1488 | #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ |
| 1489 | #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ |
1489 | #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ |
| 1490 | #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ |
1490 | #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ |
| 1491 | #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ |
1491 | #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ |
| 1492 | #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ |
1492 | |
| 1493 | 1493 | /** |
|
| 1494 | /** |
1494 | * @} |
| 1495 | * @} |
1495 | */ |
| 1496 | */ |
1496 | |
| 1497 | 1497 | ||
| 1498 | 1498 | /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state |
|
| 1499 | /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state |
1499 | * @{ |
| 1500 | * @{ |
1500 | */ |
| 1501 | */ |
1501 | #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ |
| 1502 | #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ |
1502 | #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ |
| 1503 | #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ |
1503 | #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ |
| 1504 | #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ |
1504 | #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ |
| 1505 | #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ |
1505 | #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ |
| 1506 | #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ |
1506 | #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ |
| 1507 | #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ |
1507 | |
| 1508 | 1508 | /** |
|
| 1509 | /** |
1509 | * @} |
| 1510 | * @} |
1510 | */ |
| 1511 | */ |
1511 | |
| 1512 | 1512 | /** @defgroup ETH_DMA_overflow ETH DMA overflow |
|
| 1513 | /** @defgroup ETH_DMA_overflow ETH DMA overflow |
1513 | * @{ |
| 1514 | * @{ |
1514 | */ |
| 1515 | */ |
1515 | #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ |
| 1516 | #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ |
1516 | #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ |
| 1517 | #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ |
1517 | /** |
| 1518 | /** |
1518 | * @} |
| 1519 | * @} |
1519 | */ |
| 1520 | */ |
1520 | |
| 1521 | 1521 | /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP |
|
| 1522 | /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP |
1522 | * @{ |
| 1523 | * @{ |
1523 | */ |
| 1524 | */ |
1524 | #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ |
| 1525 | #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ |
1525 | |
| 1526 | 1526 | /** |
|
| 1527 | /** |
1527 | * @} |
| 1528 | * @} |
1528 | */ |
| 1529 | */ |
1529 | |
| 1530 | 1530 | /** |
|
| 1531 | /** |
1531 | * @} |
| 1532 | * @} |
1532 | */ |
| 1533 | */ |
1533 | |
| 1534 | 1534 | /* Exported macro ------------------------------------------------------------*/ |
|
| 1535 | /* Exported macro ------------------------------------------------------------*/ |
1535 | /** @defgroup ETH_Exported_Macros ETH Exported Macros |
| 1536 | /** @defgroup ETH_Exported_Macros ETH Exported Macros |
1536 | * @brief macros to handle interrupts and specific clock configurations |
| 1537 | * @brief macros to handle interrupts and specific clock configurations |
1537 | * @{ |
| 1538 | * @{ |
1538 | */ |
| 1539 | */ |
1539 | |
| 1540 | 1540 | /** @brief Reset ETH handle state |
|
| 1541 | /** @brief Reset ETH handle state |
1541 | * @param __HANDLE__: specifies the ETH handle. |
| 1542 | * @param __HANDLE__: specifies the ETH handle. |
1542 | * @retval None |
| 1543 | * @retval None |
1543 | */ |
| 1544 | */ |
1544 | #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) |
| 1545 | #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) |
1545 | #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
| 1546 | #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
1546 | (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ |
| 1547 | (__HANDLE__)->State = HAL_ETH_STATE_RESET; \ |
1547 | (__HANDLE__)->MspInitCallback = NULL; \ |
| 1548 | (__HANDLE__)->MspInitCallback = NULL; \ |
1548 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
| 1549 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
1549 | } while(0) |
| 1550 | } while(0) |
1550 | #else |
| 1551 | #else |
1551 | #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) |
| 1552 | #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) |
1552 | #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ |
| 1553 | #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */ |
1553 | |
| 1554 | 1554 | /** |
|
| 1555 | /** |
1555 | * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. |
| 1556 | * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. |
1556 | * @param __HANDLE__: ETH Handle |
| 1557 | * @param __HANDLE__: ETH Handle |
1557 | * @param __FLAG__: specifies the flag of TDES0 to check. |
| 1558 | * @param __FLAG__: specifies the flag of TDES0 to check. |
1558 | * @retval the ETH_DMATxDescFlag (SET or RESET). |
| 1559 | * @retval the ETH_DMATxDescFlag (SET or RESET). |
1559 | */ |
| 1560 | */ |
1560 | #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) |
| 1561 | #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) |
1561 | |
| 1562 | 1562 | /** |
|
| 1563 | /** |
1563 | * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. |
| 1564 | * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. |
1564 | * @param __HANDLE__: ETH Handle |
| 1565 | * @param __HANDLE__: ETH Handle |
1565 | * @param __FLAG__: specifies the flag of RDES0 to check. |
| 1566 | * @param __FLAG__: specifies the flag of RDES0 to check. |
1566 | * @retval the ETH_DMATxDescFlag (SET or RESET). |
| 1567 | * @retval the ETH_DMATxDescFlag (SET or RESET). |
1567 | */ |
| 1568 | */ |
1568 | #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) |
| 1569 | #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) |
1569 | |
| 1570 | 1570 | /** |
|
| 1571 | /** |
1571 | * @brief Enables the specified DMA Rx Desc receive interrupt. |
| 1572 | * @brief Enables the specified DMA Rx Desc receive interrupt. |
1572 | * @param __HANDLE__: ETH Handle |
| 1573 | * @param __HANDLE__: ETH Handle |
1573 | * @retval None |
| 1574 | * @retval None |
1574 | */ |
| 1575 | */ |
1575 | #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) |
| 1576 | #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) |
1576 | |
| 1577 | 1577 | /** |
|
| 1578 | /** |
1578 | * @brief Disables the specified DMA Rx Desc receive interrupt. |
| 1579 | * @brief Disables the specified DMA Rx Desc receive interrupt. |
1579 | * @param __HANDLE__: ETH Handle |
| 1580 | * @param __HANDLE__: ETH Handle |
1580 | * @retval None |
| 1581 | * @retval None |
1581 | */ |
| 1582 | */ |
1582 | #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) |
| 1583 | #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) |
1583 | |
| 1584 | 1584 | /** |
|
| 1585 | /** |
1585 | * @brief Set the specified DMA Rx Desc Own bit. |
| 1586 | * @brief Set the specified DMA Rx Desc Own bit. |
1586 | * @param __HANDLE__: ETH Handle |
| 1587 | * @param __HANDLE__: ETH Handle |
1587 | * @retval None |
| 1588 | * @retval None |
1588 | */ |
| 1589 | */ |
1589 | #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) |
| 1590 | #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) |
1590 | |
| 1591 | 1591 | /** |
|
| 1592 | /** |
1592 | * @brief Returns the specified ETHERNET DMA Tx Desc collision count. |
| 1593 | * @brief Returns the specified ETHERNET DMA Tx Desc collision count. |
1593 | * @param __HANDLE__: ETH Handle |
| 1594 | * @param __HANDLE__: ETH Handle |
1594 | * @retval The Transmit descriptor collision counter value. |
| 1595 | * @retval The Transmit descriptor collision counter value. |
1595 | */ |
| 1596 | */ |
1596 | #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) |
| 1597 | #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) |
1597 | |
| 1598 | 1598 | /** |
|
| 1599 | /** |
1599 | * @brief Set the specified DMA Tx Desc Own bit. |
| 1600 | * @brief Set the specified DMA Tx Desc Own bit. |
1600 | * @param __HANDLE__: ETH Handle |
| 1601 | * @param __HANDLE__: ETH Handle |
1601 | * @retval None |
| 1602 | * @retval None |
1602 | */ |
| 1603 | */ |
1603 | #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) |
| 1604 | #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) |
1604 | |
| 1605 | 1605 | /** |
|
| 1606 | /** |
1606 | * @brief Enables the specified DMA Tx Desc Transmit interrupt. |
| 1607 | * @brief Enables the specified DMA Tx Desc Transmit interrupt. |
1607 | * @param __HANDLE__: ETH Handle |
| 1608 | * @param __HANDLE__: ETH Handle |
1608 | * @retval None |
| 1609 | * @retval None |
1609 | */ |
| 1610 | */ |
1610 | #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) |
| 1611 | #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) |
1611 | |
| 1612 | 1612 | /** |
|
| 1613 | /** |
1613 | * @brief Disables the specified DMA Tx Desc Transmit interrupt. |
| 1614 | * @brief Disables the specified DMA Tx Desc Transmit interrupt. |
1614 | * @param __HANDLE__: ETH Handle |
| 1615 | * @param __HANDLE__: ETH Handle |
1615 | * @retval None |
| 1616 | * @retval None |
1616 | */ |
| 1617 | */ |
1617 | #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) |
| 1618 | #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) |
1618 | |
| 1619 | 1619 | /** |
|
| 1620 | /** |
1620 | * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. |
| 1621 | * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. |
1621 | * @param __HANDLE__: ETH Handle |
| 1622 | * @param __HANDLE__: ETH Handle |
1622 | * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion. |
| 1623 | * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion. |
1623 | * This parameter can be one of the following values: |
| 1624 | * This parameter can be one of the following values: |
1624 | * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass |
| 1625 | * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass |
1625 | * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum |
| 1626 | * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum |
1626 | * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present |
| 1627 | * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present |
1627 | * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header |
| 1628 | * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header |
1628 | * @retval None |
| 1629 | * @retval None |
1629 | */ |
| 1630 | */ |
1630 | #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) |
| 1631 | #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) |
1631 | |
| 1632 | 1632 | /** |
|
| 1633 | /** |
1633 | * @brief Enables the DMA Tx Desc CRC. |
| 1634 | * @brief Enables the DMA Tx Desc CRC. |
1634 | * @param __HANDLE__: ETH Handle |
| 1635 | * @param __HANDLE__: ETH Handle |
1635 | * @retval None |
| 1636 | * @retval None |
1636 | */ |
| 1637 | */ |
1637 | #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) |
| 1638 | #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) |
1638 | |
| 1639 | 1639 | /** |
|
| 1640 | /** |
1640 | * @brief Disables the DMA Tx Desc CRC. |
| 1641 | * @brief Disables the DMA Tx Desc CRC. |
1641 | * @param __HANDLE__: ETH Handle |
| 1642 | * @param __HANDLE__: ETH Handle |
1642 | * @retval None |
| 1643 | * @retval None |
1643 | */ |
| 1644 | */ |
1644 | #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) |
| 1645 | #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) |
1645 | |
| 1646 | 1646 | /** |
|
| 1647 | /** |
1647 | * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. |
| 1648 | * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. |
1648 | * @param __HANDLE__: ETH Handle |
| 1649 | * @param __HANDLE__: ETH Handle |
1649 | * @retval None |
| 1650 | * @retval None |
1650 | */ |
| 1651 | */ |
1651 | #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) |
| 1652 | #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) |
1652 | |
| 1653 | 1653 | /** |
|
| 1654 | /** |
1654 | * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. |
| 1655 | * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. |
1655 | * @param __HANDLE__: ETH Handle |
| 1656 | * @param __HANDLE__: ETH Handle |
1656 | * @retval None |
| 1657 | * @retval None |
1657 | */ |
| 1658 | */ |
1658 | #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) |
| 1659 | #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) |
1659 | |
| 1660 | 1660 | /** |
|
| 1661 | /** |
1661 | * @brief Enables the specified ETHERNET MAC interrupts. |
| 1662 | * @brief Enables the specified ETHERNET MAC interrupts. |
1662 | * @param __HANDLE__ : ETH Handle |
| 1663 | * @param __HANDLE__ : ETH Handle |
1663 | * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be |
| 1664 | * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be |
1664 | * enabled or disabled. |
| 1665 | * enabled or disabled. |
1665 | * This parameter can be any combination of the following values: |
| 1666 | * This parameter can be any combination of the following values: |
1666 | * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt |
| 1667 | * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt |
1667 | * @arg ETH_MAC_IT_PMT : PMT interrupt |
| 1668 | * @arg ETH_MAC_IT_PMT : PMT interrupt |
1668 | * @retval None |
| 1669 | * @retval None |
1669 | */ |
| 1670 | */ |
1670 | #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) |
| 1671 | #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) |
1671 | |
| 1672 | 1672 | /** |
|
| 1673 | /** |
1673 | * @brief Disables the specified ETHERNET MAC interrupts. |
| 1674 | * @brief Disables the specified ETHERNET MAC interrupts. |
1674 | * @param __HANDLE__ : ETH Handle |
| 1675 | * @param __HANDLE__ : ETH Handle |
1675 | * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be |
| 1676 | * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be |
1676 | * enabled or disabled. |
| 1677 | * enabled or disabled. |
1677 | * This parameter can be any combination of the following values: |
| 1678 | * This parameter can be any combination of the following values: |
1678 | * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt |
| 1679 | * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt |
1679 | * @arg ETH_MAC_IT_PMT : PMT interrupt |
| 1680 | * @arg ETH_MAC_IT_PMT : PMT interrupt |
1680 | * @retval None |
| 1681 | * @retval None |
1681 | */ |
| 1682 | */ |
1682 | #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) |
| 1683 | #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) |
1683 | |
| 1684 | 1684 | /** |
|
| 1685 | /** |
1685 | * @brief Initiate a Pause Control Frame (Full-duplex only). |
| 1686 | * @brief Initiate a Pause Control Frame (Full-duplex only). |
1686 | * @param __HANDLE__: ETH Handle |
| 1687 | * @param __HANDLE__: ETH Handle |
1687 | * @retval None |
| 1688 | * @retval None |
1688 | */ |
| 1689 | */ |
1689 | #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) |
| 1690 | #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) |
1690 | |
| 1691 | 1691 | /** |
|
| 1692 | /** |
1692 | * @brief Checks whether the ETHERNET flow control busy bit is set or not. |
| 1693 | * @brief Checks whether the ETHERNET flow control busy bit is set or not. |
1693 | * @param __HANDLE__: ETH Handle |
| 1694 | * @param __HANDLE__: ETH Handle |
1694 | * @retval The new state of flow control busy status bit (SET or RESET). |
| 1695 | * @retval The new state of flow control busy status bit (SET or RESET). |
1695 | */ |
| 1696 | */ |
1696 | #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) |
| 1697 | #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) |
1697 | |
| 1698 | 1698 | /** |
|
| 1699 | /** |
1699 | * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). |
| 1700 | * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). |
1700 | * @param __HANDLE__: ETH Handle |
| 1701 | * @param __HANDLE__: ETH Handle |
1701 | * @retval None |
| 1702 | * @retval None |
1702 | */ |
| 1703 | */ |
1703 | #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) |
| 1704 | #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) |
1704 | |
| 1705 | 1705 | /** |
|
| 1706 | /** |
1706 | * @brief Disables the MAC BackPressure operation activation (Half-duplex only). |
| 1707 | * @brief Disables the MAC BackPressure operation activation (Half-duplex only). |
1707 | * @param __HANDLE__: ETH Handle |
| 1708 | * @param __HANDLE__: ETH Handle |
1708 | * @retval None |
| 1709 | * @retval None |
1709 | */ |
| 1710 | */ |
1710 | #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) |
| 1711 | #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) |
1711 | |
| 1712 | 1712 | /** |
|
| 1713 | /** |
1713 | * @brief Checks whether the specified ETHERNET MAC flag is set or not. |
| 1714 | * @brief Checks whether the specified ETHERNET MAC flag is set or not. |
1714 | * @param __HANDLE__: ETH Handle |
| 1715 | * @param __HANDLE__: ETH Handle |
1715 | * @param __FLAG__: specifies the flag to check. |
| 1716 | * @param __FLAG__: specifies the flag to check. |
1716 | * This parameter can be one of the following values: |
| 1717 | * This parameter can be one of the following values: |
1717 | * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag |
| 1718 | * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag |
1718 | * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag |
| 1719 | * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag |
1719 | * @arg ETH_MAC_FLAG_MMCR : MMC receive flag |
| 1720 | * @arg ETH_MAC_FLAG_MMCR : MMC receive flag |
1720 | * @arg ETH_MAC_FLAG_MMC : MMC flag |
| 1721 | * @arg ETH_MAC_FLAG_MMC : MMC flag |
1721 | * @arg ETH_MAC_FLAG_PMT : PMT flag |
| 1722 | * @arg ETH_MAC_FLAG_PMT : PMT flag |
1722 | * @retval The state of ETHERNET MAC flag. |
| 1723 | * @retval The state of ETHERNET MAC flag. |
1723 | */ |
| 1724 | */ |
1724 | #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) |
| 1725 | #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) |
1725 | |
| 1726 | 1726 | /** |
|
| 1727 | /** |
1727 | * @brief Enables the specified ETHERNET DMA interrupts. |
| 1728 | * @brief Enables the specified ETHERNET DMA interrupts. |
1728 | * @param __HANDLE__ : ETH Handle |
| 1729 | * @param __HANDLE__ : ETH Handle |
1729 | * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be |
| 1730 | * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be |
1730 | * enabled @ref ETH_DMA_Interrupts |
| 1731 | * enabled @ref ETH_DMA_Interrupts |
1731 | * @retval None |
| 1732 | * @retval None |
1732 | */ |
| 1733 | */ |
1733 | #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) |
| 1734 | #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) |
1734 | |
| 1735 | 1735 | /** |
|
| 1736 | /** |
1736 | * @brief Disables the specified ETHERNET DMA interrupts. |
| 1737 | * @brief Disables the specified ETHERNET DMA interrupts. |
1737 | * @param __HANDLE__ : ETH Handle |
| 1738 | * @param __HANDLE__ : ETH Handle |
1738 | * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be |
| 1739 | * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be |
1739 | * disabled. @ref ETH_DMA_Interrupts |
| 1740 | * disabled. @ref ETH_DMA_Interrupts |
1740 | * @retval None |
| 1741 | * @retval None |
1741 | */ |
| 1742 | */ |
1742 | #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) |
| 1743 | #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) |
1743 | |
| 1744 | 1744 | /** |
|
| 1745 | /** |
1745 | * @brief Clears the ETHERNET DMA IT pending bit. |
| 1746 | * @brief Clears the ETHERNET DMA IT pending bit. |
1746 | * @param __HANDLE__ : ETH Handle |
| 1747 | * @param __HANDLE__ : ETH Handle |
1747 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts |
| 1748 | * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts |
1748 | * @retval None |
| 1749 | * @retval None |
1749 | */ |
| 1750 | */ |
1750 | #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) |
| 1751 | #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) |
1751 | |
| 1752 | 1752 | /** |
|
| 1753 | /** |
1753 | * @brief Checks whether the specified ETHERNET DMA flag is set or not. |
| 1754 | * @brief Checks whether the specified ETHERNET DMA flag is set or not. |
1754 | * @param __HANDLE__: ETH Handle |
| 1755 | * @param __HANDLE__: ETH Handle |
1755 | * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags |
| 1756 | * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags |
1756 | * @retval The new state of ETH_DMA_FLAG (SET or RESET). |
| 1757 | * @retval The new state of ETH_DMA_FLAG (SET or RESET). |
1757 | */ |
| 1758 | */ |
1758 | #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) |
| 1759 | #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) |
1759 | |
| 1760 | 1760 | /** |
|
| 1761 | /** |
1761 | * @brief Checks whether the specified ETHERNET DMA flag is set or not. |
| 1762 | * @brief Checks whether the specified ETHERNET DMA flag is set or not. |
1762 | * @param __HANDLE__: ETH Handle |
| 1763 | * @param __HANDLE__: ETH Handle |
1763 | * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags |
| 1764 | * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags |
1764 | * @retval The new state of ETH_DMA_FLAG (SET or RESET). |
| 1765 | * @retval The new state of ETH_DMA_FLAG (SET or RESET). |
1765 | */ |
| 1766 | */ |
1766 | #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) |
| 1767 | #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) |
1767 | |
| 1768 | 1768 | /** |
|
| 1769 | /** |
1769 | * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. |
| 1770 | * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. |
1770 | * @param __HANDLE__: ETH Handle |
| 1771 | * @param __HANDLE__: ETH Handle |
1771 | * @param __OVERFLOW__: specifies the DMA overflow flag to check. |
| 1772 | * @param __OVERFLOW__: specifies the DMA overflow flag to check. |
1772 | * This parameter can be one of the following values: |
| 1773 | * This parameter can be one of the following values: |
1773 | * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter |
| 1774 | * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter |
1774 | * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter |
| 1775 | * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter |
1775 | * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). |
| 1776 | * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). |
1776 | */ |
| 1777 | */ |
1777 | #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) |
| 1778 | #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) |
1778 | |
| 1779 | 1779 | /** |
|
| 1780 | /** |
1780 | * @brief Set the DMA Receive status watchdog timer register value |
| 1781 | * @brief Set the DMA Receive status watchdog timer register value |
1781 | * @param __HANDLE__: ETH Handle |
| 1782 | * @param __HANDLE__: ETH Handle |
1782 | * @param __VALUE__: DMA Receive status watchdog timer register value |
| 1783 | * @param __VALUE__: DMA Receive status watchdog timer register value |
1783 | * @retval None |
| 1784 | * @retval None |
1784 | */ |
| 1785 | */ |
1785 | #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) |
| 1786 | #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) |
1786 | |
| 1787 | 1787 | /** |
|
| 1788 | /** |
1788 | * @brief Enables any unicast packet filtered by the MAC address |
| 1789 | * @brief Enables any unicast packet filtered by the MAC address |
1789 | * recognition to be a wake-up frame. |
| 1790 | * recognition to be a wake-up frame. |
1790 | * @param __HANDLE__: ETH Handle. |
| 1791 | * @param __HANDLE__: ETH Handle. |
1791 | * @retval None |
| 1792 | * @retval None |
1792 | */ |
| 1793 | */ |
1793 | #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) |
| 1794 | #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) |
1794 | |
| 1795 | 1795 | /** |
|
| 1796 | /** |
1796 | * @brief Disables any unicast packet filtered by the MAC address |
| 1797 | * @brief Disables any unicast packet filtered by the MAC address |
1797 | * recognition to be a wake-up frame. |
| 1798 | * recognition to be a wake-up frame. |
1798 | * @param __HANDLE__: ETH Handle. |
| 1799 | * @param __HANDLE__: ETH Handle. |
1799 | * @retval None |
| 1800 | * @retval None |
1800 | */ |
| 1801 | */ |
1801 | #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) |
| 1802 | #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) |
1802 | |
| 1803 | 1803 | /** |
|
| 1804 | /** |
1804 | * @brief Enables the MAC Wake-Up Frame Detection. |
| 1805 | * @brief Enables the MAC Wake-Up Frame Detection. |
1805 | * @param __HANDLE__: ETH Handle. |
| 1806 | * @param __HANDLE__: ETH Handle. |
1806 | * @retval None |
| 1807 | * @retval None |
1807 | */ |
| 1808 | */ |
1808 | #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) |
| 1809 | #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) |
1809 | |
| 1810 | 1810 | /** |
|
| 1811 | /** |
1811 | * @brief Disables the MAC Wake-Up Frame Detection. |
| 1812 | * @brief Disables the MAC Wake-Up Frame Detection. |
1812 | * @param __HANDLE__: ETH Handle. |
| 1813 | * @param __HANDLE__: ETH Handle. |
1813 | * @retval None |
| 1814 | * @retval None |
1814 | */ |
| 1815 | */ |
1815 | #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) |
| 1816 | #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) |
1816 | |
| 1817 | 1817 | /** |
|
| 1818 | /** |
1818 | * @brief Enables the MAC Magic Packet Detection. |
| 1819 | * @brief Enables the MAC Magic Packet Detection. |
1819 | * @param __HANDLE__: ETH Handle. |
| 1820 | * @param __HANDLE__: ETH Handle. |
1820 | * @retval None |
| 1821 | * @retval None |
1821 | */ |
| 1822 | */ |
1822 | #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) |
| 1823 | #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) |
1823 | |
| 1824 | 1824 | /** |
|
| 1825 | /** |
1825 | * @brief Disables the MAC Magic Packet Detection. |
| 1826 | * @brief Disables the MAC Magic Packet Detection. |
1826 | * @param __HANDLE__: ETH Handle. |
| 1827 | * @param __HANDLE__: ETH Handle. |
1827 | * @retval None |
| 1828 | * @retval None |
1828 | */ |
| 1829 | */ |
1829 | #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) |
| 1830 | #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) |
1830 | |
| 1831 | 1831 | /** |
|
| 1832 | /** |
1832 | * @brief Enables the MAC Power Down. |
| 1833 | * @brief Enables the MAC Power Down. |
1833 | * @param __HANDLE__: ETH Handle |
| 1834 | * @param __HANDLE__: ETH Handle |
1834 | * @retval None |
| 1835 | * @retval None |
1835 | */ |
| 1836 | */ |
1836 | #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) |
| 1837 | #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) |
1837 | |
| 1838 | 1838 | /** |
|
| 1839 | /** |
1839 | * @brief Disables the MAC Power Down. |
| 1840 | * @brief Disables the MAC Power Down. |
1840 | * @param __HANDLE__: ETH Handle |
| 1841 | * @param __HANDLE__: ETH Handle |
1841 | * @retval None |
| 1842 | * @retval None |
1842 | */ |
| 1843 | */ |
1843 | #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) |
| 1844 | #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) |
1844 | |
| 1845 | 1845 | /** |
|
| 1846 | /** |
1846 | * @brief Checks whether the specified ETHERNET PMT flag is set or not. |
| 1847 | * @brief Checks whether the specified ETHERNET PMT flag is set or not. |
1847 | * @param __HANDLE__: ETH Handle. |
| 1848 | * @param __HANDLE__: ETH Handle. |
1848 | * @param __FLAG__: specifies the flag to check. |
| 1849 | * @param __FLAG__: specifies the flag to check. |
1849 | * This parameter can be one of the following values: |
| 1850 | * This parameter can be one of the following values: |
1850 | * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset |
| 1851 | * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset |
1851 | * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received |
| 1852 | * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received |
1852 | * @arg ETH_PMT_FLAG_MPR : Magic Packet Received |
| 1853 | * @arg ETH_PMT_FLAG_MPR : Magic Packet Received |
1853 | * @retval The new state of ETHERNET PMT Flag (SET or RESET). |
| 1854 | * @retval The new state of ETHERNET PMT Flag (SET or RESET). |
1854 | */ |
| 1855 | */ |
1855 | #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) |
| 1856 | #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) |
1856 | |
| 1857 | 1857 | /** |
|
| 1858 | /** |
1858 | * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) |
| 1859 | * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) |
1859 | * @param __HANDLE__: ETH Handle. |
| 1860 | * @param __HANDLE__: ETH Handle. |
1860 | * @retval None |
| 1861 | * @retval None |
1861 | */ |
| 1862 | */ |
1862 | #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) |
| 1863 | #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) |
1863 | |
| 1864 | 1864 | /** |
|
| 1865 | /** |
1865 | * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) |
| 1866 | * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) |
1866 | * @param __HANDLE__: ETH Handle. |
| 1867 | * @param __HANDLE__: ETH Handle. |
1867 | * @retval None |
| 1868 | * @retval None |
1868 | */ |
| 1869 | */ |
1869 | #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ |
| 1870 | #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ |
1870 | (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while(0U) |
| 1871 | (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while(0U) |
1871 | |
| 1872 | 1872 | /** |
|
| 1873 | /** |
1873 | * @brief Enables the MMC Counter Freeze. |
| 1874 | * @brief Enables the MMC Counter Freeze. |
1874 | * @param __HANDLE__: ETH Handle. |
| 1875 | * @param __HANDLE__: ETH Handle. |
1875 | * @retval None |
| 1876 | * @retval None |
1876 | */ |
| 1877 | */ |
1877 | #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) |
| 1878 | #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) |
1878 | |
| 1879 | 1879 | /** |
|
| 1880 | /** |
1880 | * @brief Disables the MMC Counter Freeze. |
| 1881 | * @brief Disables the MMC Counter Freeze. |
1881 | * @param __HANDLE__: ETH Handle. |
| 1882 | * @param __HANDLE__: ETH Handle. |
1882 | * @retval None |
| 1883 | * @retval None |
1883 | */ |
| 1884 | */ |
1884 | #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) |
| 1885 | #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) |
1885 | |
| 1886 | 1886 | /** |
|
| 1887 | /** |
1887 | * @brief Enables the MMC Reset On Read. |
| 1888 | * @brief Enables the MMC Reset On Read. |
1888 | * @param __HANDLE__: ETH Handle. |
| 1889 | * @param __HANDLE__: ETH Handle. |
1889 | * @retval None |
| 1890 | * @retval None |
1890 | */ |
| 1891 | */ |
1891 | #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) |
| 1892 | #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) |
1892 | |
| 1893 | 1893 | /** |
|
| 1894 | /** |
1894 | * @brief Disables the MMC Reset On Read. |
| 1895 | * @brief Disables the MMC Reset On Read. |
1895 | * @param __HANDLE__: ETH Handle. |
| 1896 | * @param __HANDLE__: ETH Handle. |
1896 | * @retval None |
| 1897 | * @retval None |
1897 | */ |
| 1898 | */ |
1898 | #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) |
| 1899 | #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) |
1899 | |
| 1900 | 1900 | /** |
|
| 1901 | /** |
1901 | * @brief Enables the MMC Counter Stop Rollover. |
| 1902 | * @brief Enables the MMC Counter Stop Rollover. |
1902 | * @param __HANDLE__: ETH Handle. |
| 1903 | * @param __HANDLE__: ETH Handle. |
1903 | * @retval None |
| 1904 | * @retval None |
1904 | */ |
| 1905 | */ |
1905 | #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) |
| 1906 | #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) |
1906 | |
| 1907 | 1907 | /** |
|
| 1908 | /** |
1908 | * @brief Disables the MMC Counter Stop Rollover. |
| 1909 | * @brief Disables the MMC Counter Stop Rollover. |
1909 | * @param __HANDLE__: ETH Handle. |
| 1910 | * @param __HANDLE__: ETH Handle. |
1910 | * @retval None |
| 1911 | * @retval None |
1911 | */ |
| 1912 | */ |
1912 | #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) |
| 1913 | #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) |
1913 | |
| 1914 | 1914 | /** |
|
| 1915 | /** |
1915 | * @brief Resets the MMC Counters. |
| 1916 | * @brief Resets the MMC Counters. |
1916 | * @param __HANDLE__: ETH Handle. |
| 1917 | * @param __HANDLE__: ETH Handle. |
1917 | * @retval None |
| 1918 | * @retval None |
1918 | */ |
| 1919 | */ |
1919 | #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) |
| 1920 | #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) |
1920 | |
| 1921 | 1921 | /** |
|
| 1922 | /** |
1922 | * @brief Enables the specified ETHERNET MMC Rx interrupts. |
| 1923 | * @brief Enables the specified ETHERNET MMC Rx interrupts. |
1923 | * @param __HANDLE__: ETH Handle. |
| 1924 | * @param __HANDLE__: ETH Handle. |
1924 | * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. |
| 1925 | * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. |
1925 | * This parameter can be one of the following values: |
| 1926 | * This parameter can be one of the following values: |
1926 | * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value |
| 1927 | * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value |
1927 | * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value |
| 1928 | * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value |
1928 | * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value |
| 1929 | * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value |
1929 | * @retval None |
| 1930 | * @retval None |
1930 | */ |
| 1931 | */ |
1931 | #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) |
| 1932 | #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) |
1932 | /** |
| 1933 | /** |
1933 | * @brief Disables the specified ETHERNET MMC Rx interrupts. |
| 1934 | * @brief Disables the specified ETHERNET MMC Rx interrupts. |
1934 | * @param __HANDLE__: ETH Handle. |
| 1935 | * @param __HANDLE__: ETH Handle. |
1935 | * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. |
| 1936 | * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. |
1936 | * This parameter can be one of the following values: |
| 1937 | * This parameter can be one of the following values: |
1937 | * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value |
| 1938 | * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value |
1938 | * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value |
| 1939 | * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value |
1939 | * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value |
| 1940 | * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value |
1940 | * @retval None |
| 1941 | * @retval None |
1941 | */ |
| 1942 | */ |
1942 | #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) |
| 1943 | #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) |
1943 | /** |
| 1944 | /** |
1944 | * @brief Enables the specified ETHERNET MMC Tx interrupts. |
| 1945 | * @brief Enables the specified ETHERNET MMC Tx interrupts. |
1945 | * @param __HANDLE__: ETH Handle. |
| 1946 | * @param __HANDLE__: ETH Handle. |
1946 | * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. |
| 1947 | * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. |
1947 | * This parameter can be one of the following values: |
| 1948 | * This parameter can be one of the following values: |
1948 | * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value |
| 1949 | * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value |
1949 | * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value |
| 1950 | * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value |
1950 | * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value |
| 1951 | * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value |
1951 | * @retval None |
| 1952 | * @retval None |
1952 | */ |
| 1953 | */ |
1953 | #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) |
| 1954 | #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) |
1954 | |
| 1955 | 1955 | /** |
|
| 1956 | /** |
1956 | * @brief Disables the specified ETHERNET MMC Tx interrupts. |
| 1957 | * @brief Disables the specified ETHERNET MMC Tx interrupts. |
1957 | * @param __HANDLE__: ETH Handle. |
| 1958 | * @param __HANDLE__: ETH Handle. |
1958 | * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. |
| 1959 | * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled. |
1959 | * This parameter can be one of the following values: |
| 1960 | * This parameter can be one of the following values: |
1960 | * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value |
| 1961 | * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value |
1961 | * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value |
| 1962 | * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value |
1962 | * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value |
| 1963 | * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value |
1963 | * @retval None |
| 1964 | * @retval None |
1964 | */ |
| 1965 | */ |
1965 | #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) |
| 1966 | #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) |
1966 | |
| 1967 | 1967 | /** |
|
| 1968 | /** |
1968 | * @brief Enables the ETH External interrupt line. |
| 1969 | * @brief Enables the ETH External interrupt line. |
1969 | * @retval None |
| 1970 | * @retval None |
1970 | */ |
| 1971 | */ |
1971 | #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) |
| 1972 | #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) |
1972 | |
| 1973 | 1973 | /** |
|
| 1974 | /** |
1974 | * @brief Disables the ETH External interrupt line. |
| 1975 | * @brief Disables the ETH External interrupt line. |
1975 | * @retval None |
| 1976 | * @retval None |
1976 | */ |
| 1977 | */ |
1977 | #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) |
| 1978 | #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) |
1978 | |
| 1979 | 1979 | /** |
|
| 1980 | /** |
1980 | * @brief Enable event on ETH External event line. |
| 1981 | * @brief Enable event on ETH External event line. |
1981 | * @retval None. |
| 1982 | * @retval None. |
1982 | */ |
| 1983 | */ |
1983 | #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) |
| 1984 | #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) |
1984 | |
| 1985 | 1985 | /** |
|
| 1986 | /** |
1986 | * @brief Disable event on ETH External event line |
| 1987 | * @brief Disable event on ETH External event line |
1987 | * @retval None. |
| 1988 | * @retval None. |
1988 | */ |
| 1989 | */ |
1989 | #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) |
| 1990 | #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) |
1990 | |
| 1991 | 1991 | /** |
|
| 1992 | /** |
1992 | * @brief Get flag of the ETH External interrupt line. |
| 1993 | * @brief Get flag of the ETH External interrupt line. |
1993 | * @retval None |
| 1994 | * @retval None |
1994 | */ |
| 1995 | */ |
1995 | #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) |
| 1996 | #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) |
1996 | |
| 1997 | 1997 | /** |
|
| 1998 | /** |
1998 | * @brief Clear flag of the ETH External interrupt line. |
| 1999 | * @brief Clear flag of the ETH External interrupt line. |
1999 | * @retval None |
| 2000 | * @retval None |
2000 | */ |
| 2001 | */ |
2001 | #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) |
| 2002 | #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) |
2002 | |
| 2003 | 2003 | /** |
|
| 2004 | /** |
2004 | * @brief Enables rising edge trigger to the ETH External interrupt line. |
| 2005 | * @brief Enables rising edge trigger to the ETH External interrupt line. |
2005 | * @retval None |
| 2006 | * @retval None |
2006 | */ |
| 2007 | */ |
2007 | #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP |
| 2008 | #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP |
2008 | |
| 2009 | 2009 | /** |
|
| 2010 | /** |
2010 | * @brief Disables the rising edge trigger to the ETH External interrupt line. |
| 2011 | * @brief Disables the rising edge trigger to the ETH External interrupt line. |
2011 | * @retval None |
| 2012 | * @retval None |
2012 | */ |
| 2013 | */ |
2013 | #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) |
| 2014 | #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) |
2014 | |
| 2015 | 2015 | /** |
|
| 2016 | /** |
2016 | * @brief Enables falling edge trigger to the ETH External interrupt line. |
| 2017 | * @brief Enables falling edge trigger to the ETH External interrupt line. |
2017 | * @retval None |
| 2018 | * @retval None |
2018 | */ |
| 2019 | */ |
2019 | #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) |
| 2020 | #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) |
2020 | |
| 2021 | 2021 | /** |
|
| 2022 | /** |
2022 | * @brief Disables falling edge trigger to the ETH External interrupt line. |
| 2023 | * @brief Disables falling edge trigger to the ETH External interrupt line. |
2023 | * @retval None |
| 2024 | * @retval None |
2024 | */ |
| 2025 | */ |
2025 | #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) |
| 2026 | #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) |
2026 | |
| 2027 | 2027 | /** |
|
| 2028 | /** |
2028 | * @brief Enables rising/falling edge trigger to the ETH External interrupt line. |
| 2029 | * @brief Enables rising/falling edge trigger to the ETH External interrupt line. |
2029 | * @retval None |
| 2030 | * @retval None |
2030 | */ |
| 2031 | */ |
2031 | #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ |
| 2032 | #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ |
2032 | EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ |
| 2033 | EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ |
2033 | }while(0U) |
| 2034 | }while(0U) |
2034 | |
| 2035 | 2035 | /** |
|
| 2036 | /** |
2036 | * @brief Disables rising/falling edge trigger to the ETH External interrupt line. |
| 2037 | * @brief Disables rising/falling edge trigger to the ETH External interrupt line. |
2037 | * @retval None |
| 2038 | * @retval None |
2038 | */ |
| 2039 | */ |
2039 | #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ |
| 2040 | #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ |
2040 | EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ |
| 2041 | EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ |
2041 | }while(0U) |
| 2042 | }while(0U) |
2042 | |
| 2043 | 2043 | /** |
|
| 2044 | /** |
2044 | * @brief Generate a Software interrupt on selected EXTI line. |
| 2045 | * @brief Generate a Software interrupt on selected EXTI line. |
2045 | * @retval None. |
| 2046 | * @retval None. |
2046 | */ |
| 2047 | */ |
2047 | #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP |
| 2048 | #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP |
2048 | |
| 2049 | 2049 | /** |
|
| 2050 | /** |
2050 | * @} |
| 2051 | * @} |
2051 | */ |
| 2052 | */ |
2052 | /* Exported functions --------------------------------------------------------*/ |
| 2053 | /* Exported functions --------------------------------------------------------*/ |
2053 | |
| 2054 | 2054 | /** @addtogroup ETH_Exported_Functions |
|
| 2055 | /** @addtogroup ETH_Exported_Functions |
2055 | * @{ |
| 2056 | * @{ |
2056 | */ |
| 2057 | */ |
2057 | |
| 2058 | 2058 | /* Initialization and de-initialization functions ****************************/ |
|
| 2059 | /* Initialization and de-initialization functions ****************************/ |
2059 | |
| 2060 | 2060 | /** @addtogroup ETH_Exported_Functions_Group1 |
|
| 2061 | /** @addtogroup ETH_Exported_Functions_Group1 |
2061 | * @{ |
| 2062 | * @{ |
2062 | */ |
| 2063 | */ |
2063 | HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); |
| 2064 | HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); |
2064 | HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); |
| 2065 | HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); |
2065 | void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); |
| 2066 | void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); |
2066 | void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); |
| 2067 | void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); |
2067 | HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); |
| 2068 | HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); |
2068 | HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); |
| 2069 | HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); |
2069 | /* Callbacks Register/UnRegister functions ***********************************/ |
| 2070 | /* Callbacks Register/UnRegister functions ***********************************/ |
2070 | #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) |
| 2071 | #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1) |
2071 | HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); |
| 2072 | HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback); |
2072 | HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); |
| 2073 | HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID); |
2073 | #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ |
| 2074 | #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */ |
2074 | |
| 2075 | 2075 | /** |
|
| 2076 | /** |
2076 | * @} |
| 2077 | * @} |
2077 | */ |
| 2078 | */ |
2078 | /* IO operation functions ****************************************************/ |
| 2079 | /* IO operation functions ****************************************************/ |
2079 | |
| 2080 | 2080 | /** @addtogroup ETH_Exported_Functions_Group2 |
|
| 2081 | /** @addtogroup ETH_Exported_Functions_Group2 |
2081 | * @{ |
| 2082 | * @{ |
2082 | */ |
| 2083 | */ |
2083 | HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); |
| 2084 | HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); |
2084 | HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); |
| 2085 | HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); |
2085 | /* Communication with PHY functions*/ |
| 2086 | /* Communication with PHY functions*/ |
2086 | HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); |
| 2087 | HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); |
2087 | HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); |
| 2088 | HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); |
2088 | /* Non-Blocking mode: Interrupt */ |
| 2089 | /* Non-Blocking mode: Interrupt */ |
2089 | HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); |
| 2090 | HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); |
2090 | void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); |
| 2091 | void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); |
2091 | /* Callback in non blocking modes (Interrupt) */ |
| 2092 | /* Callback in non blocking modes (Interrupt) */ |
2092 | void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); |
| 2093 | void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); |
2093 | void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); |
| 2094 | void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); |
2094 | void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); |
| 2095 | void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); |
2095 | /** |
| 2096 | /** |
2096 | * @} |
| 2097 | * @} |
2097 | */ |
| 2098 | */ |
2098 | |
| 2099 | 2099 | /* Peripheral Control functions **********************************************/ |
|
| 2100 | /* Peripheral Control functions **********************************************/ |
2100 | |
| 2101 | 2101 | /** @addtogroup ETH_Exported_Functions_Group3 |
|
| 2102 | /** @addtogroup ETH_Exported_Functions_Group3 |
2102 | * @{ |
| 2103 | * @{ |
2103 | */ |
| 2104 | */ |
2104 | |
| 2105 | 2105 | HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); |
|
| 2106 | HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); |
2106 | HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); |
| 2107 | HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); |
2107 | HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); |
| 2108 | HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); |
2108 | HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); |
| 2109 | HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); |
2109 | /** |
| 2110 | /** |
2110 | * @} |
| 2111 | * @} |
2111 | */ |
| 2112 | */ |
2112 | |
| 2113 | 2113 | /* Peripheral State functions ************************************************/ |
|
| 2114 | /* Peripheral State functions ************************************************/ |
2114 | |
| 2115 | 2115 | /** @addtogroup ETH_Exported_Functions_Group4 |
|
| 2116 | /** @addtogroup ETH_Exported_Functions_Group4 |
2116 | * @{ |
| 2117 | * @{ |
2117 | */ |
| 2118 | */ |
2118 | HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); |
| 2119 | HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); |
2119 | /** |
| 2120 | /** |
2120 | * @} |
| 2121 | * @} |
2121 | */ |
| 2122 | */ |
2122 | |
| 2123 | 2123 | /** |
|
| 2124 | /** |
2124 | * @} |
| 2125 | * @} |
2125 | */ |
| 2126 | */ |
2126 | |
| 2127 | 2127 | /** |
|
| 2128 | /** |
2128 | * @} |
| 2129 | * @} |
2129 | */ |
| 2130 | */ |
2130 | |
| 2131 | 2131 | /** |
|
| 2132 | /** |
2132 | * @} |
| 2133 | * @} |
2133 | */ |
| 2134 | */ |
2134 | |
| 2135 | 2135 | #endif /* ETH */ |
|
| 2136 | #endif /* ETH */ |
2136 | |
| 2137 | 2137 | #ifdef __cplusplus |
|
| 2138 | #ifdef __cplusplus |
2138 | } |
| 2139 | } |
2139 | #endif |
| 2140 | #endif |
2140 | |
| 2141 | 2141 | #endif /* __STM32F1xx_HAL_ETH_H */ |
|
| 2142 | #endif /* __STM32F1xx_HAL_ETH_H */ |
- | |
| 2143 | - | ||
| 2144 | - | ||
| 2145 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |