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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f1xx_hal_can_legacy.h |
3 | * @file stm32f1xx_hal_can_legacy.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief Header file of CAN HAL module. |
5 | * @brief Header file of CAN HAL module. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * |
10 | * All rights reserved. |
| 11 | * Redistribution and use in source and binary forms, with or without modification, |
11 | * |
| 12 | * are permitted provided that the following conditions are met: |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * 1. Redistributions of source code must retain the above copyright notice, |
13 | * in the root directory of this software component. |
| 14 | * this list of conditions and the following disclaimer. |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
15 | * |
| 16 | * this list of conditions and the following disclaimer in the documentation |
16 | ****************************************************************************** |
| 17 | * and/or other materials provided with the distribution. |
17 | */ |
| 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
18 | |
| 19 | * may be used to endorse or promote products derived from this software |
19 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| 20 | * without specific prior written permission. |
20 | #ifndef __STM32F1xx_HAL_CAN_LEGACY_H |
| 21 | * |
21 | #define __STM32F1xx_HAL_CAN_LEGACY_H |
| 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
22 | |
| 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
23 | #ifdef __cplusplus |
| 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
24 | extern "C" { |
| 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
25 | #endif |
| 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
26 | |
| 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
27 | #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \ |
| 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
28 | defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) |
| 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
29 | |
| 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
30 | /* Includes ------------------------------------------------------------------*/ |
| 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
31 | #include "stm32f1xx_hal_def.h" |
| 32 | * |
32 | |
| 33 | ****************************************************************************** |
33 | /** @addtogroup STM32F1xx_HAL_Driver |
| 34 | */ |
34 | * @{ |
| 35 | 35 | */ |
|
| 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
36 | |
| 37 | #ifndef __STM32F1xx_HAL_CAN_LEGACY_H |
37 | /** @addtogroup CAN |
| 38 | #define __STM32F1xx_HAL_CAN_LEGACY_H |
38 | * @{ |
| 39 | 39 | */ |
|
| 40 | #ifdef __cplusplus |
40 | |
| 41 | extern "C" { |
41 | /* Exported types ------------------------------------------------------------*/ |
| 42 | #endif |
42 | /** @defgroup CAN_Exported_Types CAN Exported Types |
| 43 | 43 | * @{ |
|
| 44 | #if defined(STM32F103x6) || defined(STM32F103xB) || defined(STM32F103xE) || \ |
44 | */ |
| 45 | defined(STM32F103xG) || defined(STM32F105xC) || defined(STM32F107xC) |
45 | |
| 46 | 46 | /** |
|
| 47 | /* Includes ------------------------------------------------------------------*/ |
47 | * @brief HAL State structures definition |
| 48 | #include "stm32f1xx_hal_def.h" |
48 | */ |
| 49 | 49 | typedef enum |
|
| 50 | /** @addtogroup STM32F1xx_HAL_Driver |
50 | { |
| 51 | * @{ |
51 | HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ |
| 52 | */ |
52 | HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ |
| 53 | 53 | HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ |
|
| 54 | /** @addtogroup CAN |
54 | HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ |
| 55 | * @{ |
55 | HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ |
| 56 | */ |
56 | HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ |
| 57 | 57 | HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ |
|
| 58 | /* Exported types ------------------------------------------------------------*/ |
58 | HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ |
| 59 | /** @defgroup CAN_Exported_Types CAN Exported Types |
59 | HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ |
| 60 | * @{ |
60 | HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ |
| 61 | */ |
61 | HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ |
| 62 | 62 | HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ |
|
| 63 | /** |
63 | |
| 64 | * @brief HAL State structures definition |
64 | }HAL_CAN_StateTypeDef; |
| 65 | */ |
65 | |
| 66 | typedef enum |
66 | /** |
| 67 | { |
67 | * @brief CAN init structure definition |
| 68 | HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */ |
68 | */ |
| 69 | HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */ |
69 | typedef struct |
| 70 | HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */ |
70 | { |
| 71 | HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */ |
71 | uint32_t Prescaler; /*!< Specifies the length of a time quantum. |
| 72 | HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */ |
72 | This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ |
| 73 | HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */ |
73 | |
| 74 | HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */ |
74 | uint32_t Mode; /*!< Specifies the CAN operating mode. |
| 75 | HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */ |
75 | This parameter can be a value of @ref CAN_operating_mode */ |
| 76 | HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */ |
76 | |
| 77 | HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */ |
77 | uint32_t SJW; /*!< Specifies the maximum number of time quanta |
| 78 | HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */ |
78 | the CAN hardware is allowed to lengthen or |
| 79 | HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */ |
79 | shorten a bit to perform resynchronization. |
| 80 | 80 | This parameter can be a value of @ref CAN_synchronisation_jump_width */ |
|
| 81 | }HAL_CAN_StateTypeDef; |
81 | |
| 82 | 82 | uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. |
|
| 83 | /** |
83 | This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ |
| 84 | * @brief CAN init structure definition |
84 | |
| 85 | */ |
85 | uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. |
| 86 | typedef struct |
86 | This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ |
| 87 | { |
87 | |
| 88 | uint32_t Prescaler; /*!< Specifies the length of a time quantum. |
88 | uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. |
| 89 | This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ |
89 | This parameter can be set to ENABLE or DISABLE. */ |
| 90 | 90 | ||
| 91 | uint32_t Mode; /*!< Specifies the CAN operating mode. |
91 | uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. |
| 92 | This parameter can be a value of @ref CAN_operating_mode */ |
92 | This parameter can be set to ENABLE or DISABLE */ |
| 93 | 93 | ||
| 94 | uint32_t SJW; /*!< Specifies the maximum number of time quanta |
94 | uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. |
| 95 | the CAN hardware is allowed to lengthen or |
95 | This parameter can be set to ENABLE or DISABLE */ |
| 96 | shorten a bit to perform resynchronization. |
96 | |
| 97 | This parameter can be a value of @ref CAN_synchronisation_jump_width */ |
97 | uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. |
| 98 | 98 | This parameter can be set to ENABLE or DISABLE */ |
|
| 99 | uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1. |
99 | |
| 100 | This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */ |
100 | uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. |
| 101 | 101 | This parameter can be set to ENABLE or DISABLE */ |
|
| 102 | uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2. |
102 | |
| 103 | This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */ |
103 | uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. |
| 104 | 104 | This parameter can be set to ENABLE or DISABLE */ |
|
| 105 | uint32_t TTCM; /*!< Enable or disable the time triggered communication mode. |
105 | }CAN_InitTypeDef; |
| 106 | This parameter can be set to ENABLE or DISABLE. */ |
106 | |
| 107 | 107 | /** |
|
| 108 | uint32_t ABOM; /*!< Enable or disable the automatic bus-off management. |
108 | * @brief CAN Tx message structure definition |
| 109 | This parameter can be set to ENABLE or DISABLE */ |
109 | */ |
| 110 | 110 | typedef struct |
|
| 111 | uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode. |
111 | { |
| 112 | This parameter can be set to ENABLE or DISABLE */ |
112 | uint32_t StdId; /*!< Specifies the standard identifier. |
| 113 | 113 | This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ |
|
| 114 | uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode. |
114 | |
| 115 | This parameter can be set to ENABLE or DISABLE */ |
115 | uint32_t ExtId; /*!< Specifies the extended identifier. |
| 116 | 116 | This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ |
|
| 117 | uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode. |
117 | |
| 118 | This parameter can be set to ENABLE or DISABLE */ |
118 | uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. |
| 119 | 119 | This parameter can be a value of @ref CAN_Identifier_Type */ |
|
| 120 | uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority. |
120 | |
| 121 | This parameter can be set to ENABLE or DISABLE */ |
121 | uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. |
| 122 | }CAN_InitTypeDef; |
122 | This parameter can be a value of @ref CAN_remote_transmission_request */ |
| 123 | 123 | ||
| 124 | /** |
124 | uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. |
| 125 | * @brief CAN Tx message structure definition |
125 | This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ |
| 126 | */ |
126 | |
| 127 | typedef struct |
127 | uint8_t Data[8]; /*!< Contains the data to be transmitted. |
| 128 | { |
128 | This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ |
| 129 | uint32_t StdId; /*!< Specifies the standard identifier. |
129 | |
| 130 | This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ |
130 | }CanTxMsgTypeDef; |
| 131 | 131 | ||
| 132 | uint32_t ExtId; /*!< Specifies the extended identifier. |
132 | /** |
| 133 | This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ |
133 | * @brief CAN Rx message structure definition |
| 134 | 134 | */ |
|
| 135 | uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted. |
135 | typedef struct |
| 136 | This parameter can be a value of @ref CAN_Identifier_Type */ |
136 | { |
| 137 | 137 | uint32_t StdId; /*!< Specifies the standard identifier. |
|
| 138 | uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted. |
138 | This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ |
| 139 | This parameter can be a value of @ref CAN_remote_transmission_request */ |
139 | |
| 140 | 140 | uint32_t ExtId; /*!< Specifies the extended identifier. |
|
| 141 | uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted. |
141 | This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ |
| 142 | This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ |
142 | |
| 143 | 143 | uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. |
|
| 144 | uint8_t Data[8]; /*!< Contains the data to be transmitted. |
144 | This parameter can be a value of @ref CAN_Identifier_Type */ |
| 145 | This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ |
145 | |
| 146 | 146 | uint32_t RTR; /*!< Specifies the type of frame for the received message. |
|
| 147 | }CanTxMsgTypeDef; |
147 | This parameter can be a value of @ref CAN_remote_transmission_request */ |
| 148 | 148 | ||
| 149 | /** |
149 | uint32_t DLC; /*!< Specifies the length of the frame that will be received. |
| 150 | * @brief CAN Rx message structure definition |
150 | This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ |
| 151 | */ |
151 | |
| 152 | typedef struct |
152 | uint8_t Data[8]; /*!< Contains the data to be received. |
| 153 | { |
153 | This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ |
| 154 | uint32_t StdId; /*!< Specifies the standard identifier. |
154 | |
| 155 | This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */ |
155 | uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. |
| 156 | 156 | This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ |
|
| 157 | uint32_t ExtId; /*!< Specifies the extended identifier. |
157 | |
| 158 | This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */ |
158 | uint32_t FIFONumber; /*!< Specifies the receive FIFO number. |
| 159 | 159 | This parameter can be CAN_FIFO0 or CAN_FIFO1 */ |
|
| 160 | uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received. |
160 | |
| 161 | This parameter can be a value of @ref CAN_Identifier_Type */ |
161 | }CanRxMsgTypeDef; |
| 162 | 162 | ||
| 163 | uint32_t RTR; /*!< Specifies the type of frame for the received message. |
163 | /** |
| 164 | This parameter can be a value of @ref CAN_remote_transmission_request */ |
164 | * @brief CAN handle Structure definition |
| 165 | 165 | */ |
|
| 166 | uint32_t DLC; /*!< Specifies the length of the frame that will be received. |
166 | typedef struct |
| 167 | This parameter must be a number between Min_Data = 0 and Max_Data = 8 */ |
167 | { |
| 168 | 168 | CAN_TypeDef *Instance; /*!< Register base address */ |
|
| 169 | uint8_t Data[8]; /*!< Contains the data to be received. |
169 | |
| 170 | This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ |
170 | CAN_InitTypeDef Init; /*!< CAN required parameters */ |
| 171 | 171 | ||
| 172 | uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through. |
172 | CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ |
| 173 | This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */ |
173 | |
| 174 | 174 | CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ |
|
| 175 | uint32_t FIFONumber; /*!< Specifies the receive FIFO number. |
175 | |
| 176 | This parameter can be CAN_FIFO0 or CAN_FIFO1 */ |
176 | CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ |
| 177 | 177 | ||
| 178 | }CanRxMsgTypeDef; |
178 | __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ |
| 179 | 179 | ||
| 180 | /** |
180 | HAL_LockTypeDef Lock; /*!< CAN locking object */ |
| 181 | * @brief CAN handle Structure definition |
181 | |
| 182 | */ |
182 | __IO uint32_t ErrorCode; /*!< CAN Error code */ |
| 183 | typedef struct |
183 | |
| 184 | { |
184 | }CAN_HandleTypeDef; |
| 185 | CAN_TypeDef *Instance; /*!< Register base address */ |
185 | |
| 186 | 186 | /** |
|
| 187 | CAN_InitTypeDef Init; /*!< CAN required parameters */ |
187 | * @} |
| 188 | 188 | */ |
|
| 189 | CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */ |
189 | |
| 190 | 190 | /* Exported constants --------------------------------------------------------*/ |
|
| 191 | CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */ |
191 | /** @defgroup CAN_Exported_Constants CAN Exported Constants |
| 192 | 192 | * @{ |
|
| 193 | CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */ |
193 | */ |
| 194 | 194 | ||
| 195 | __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */ |
195 | /** @defgroup CAN_Error_Code CAN Error Code |
| 196 | 196 | * @{ |
|
| 197 | HAL_LockTypeDef Lock; /*!< CAN locking object */ |
197 | */ |
| 198 | 198 | #define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ |
|
| 199 | __IO uint32_t ErrorCode; /*!< CAN Error code */ |
199 | #define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ |
| 200 | 200 | #define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ |
|
| 201 | }CAN_HandleTypeDef; |
201 | #define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ |
| 202 | 202 | #define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ |
|
| 203 | /** |
203 | #define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ |
| 204 | * @} |
204 | #define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ |
| 205 | */ |
205 | #define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ |
| 206 | 206 | #define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ |
|
| 207 | /* Exported constants --------------------------------------------------------*/ |
207 | #define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ |
| 208 | /** @defgroup CAN_Exported_Constants CAN Exported Constants |
208 | #define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ |
| 209 | * @{ |
209 | #define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ |
| 210 | */ |
210 | #define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ |
| 211 | 211 | /** |
|
| 212 | /** @defgroup CAN_Error_Code CAN Error Code |
212 | * @} |
| 213 | * @{ |
213 | */ |
| 214 | */ |
214 | |
| 215 | #define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */ |
215 | /** @defgroup CAN_InitStatus CAN initialization Status |
| 216 | #define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */ |
216 | * @{ |
| 217 | #define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */ |
217 | */ |
| 218 | #define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */ |
218 | #define CAN_INITSTATUS_FAILED 0x00000000U /*!< CAN initialization failed */ |
| 219 | #define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */ |
219 | #define CAN_INITSTATUS_SUCCESS 0x00000001U /*!< CAN initialization OK */ |
| 220 | #define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */ |
220 | /** |
| 221 | #define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */ |
221 | * @} |
| 222 | #define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */ |
222 | */ |
| 223 | #define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */ |
223 | |
| 224 | #define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */ |
224 | /** @defgroup CAN_operating_mode CAN Operating Mode |
| 225 | #define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */ |
225 | * @{ |
| 226 | #define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */ |
226 | */ |
| 227 | #define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */ |
227 | #define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */ |
| 228 | /** |
228 | #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ |
| 229 | * @} |
229 | #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ |
| 230 | */ |
230 | #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ |
| 231 | 231 | /** |
|
| 232 | /** @defgroup CAN_InitStatus CAN initialization Status |
232 | * @} |
| 233 | * @{ |
233 | */ |
| 234 | */ |
234 | |
| 235 | #define CAN_INITSTATUS_FAILED 0x00000000U /*!< CAN initialization failed */ |
235 | /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width |
| 236 | #define CAN_INITSTATUS_SUCCESS 0x00000001U /*!< CAN initialization OK */ |
236 | * @{ |
| 237 | /** |
237 | */ |
| 238 | * @} |
238 | #define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */ |
| 239 | */ |
239 | #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ |
| 240 | 240 | #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ |
|
| 241 | /** @defgroup CAN_operating_mode CAN Operating Mode |
241 | #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ |
| 242 | * @{ |
242 | /** |
| 243 | */ |
243 | * @} |
| 244 | #define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */ |
244 | */ |
| 245 | #define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */ |
245 | |
| 246 | #define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */ |
246 | /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 |
| 247 | #define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */ |
247 | * @{ |
| 248 | /** |
248 | */ |
| 249 | * @} |
249 | #define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */ |
| 250 | */ |
250 | #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ |
| 251 | 251 | #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ |
|
| 252 | /** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width |
252 | #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ |
| 253 | * @{ |
253 | #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ |
| 254 | */ |
254 | #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ |
| 255 | #define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */ |
255 | #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ |
| 256 | #define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */ |
256 | #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ |
| 257 | #define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */ |
257 | #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ |
| 258 | #define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */ |
258 | #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ |
| 259 | /** |
259 | #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ |
| 260 | * @} |
260 | #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ |
| 261 | */ |
261 | #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ |
| 262 | 262 | #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ |
|
| 263 | /** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1 |
263 | #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ |
| 264 | * @{ |
264 | #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ |
| 265 | */ |
265 | /** |
| 266 | #define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */ |
266 | * @} |
| 267 | #define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */ |
267 | */ |
| 268 | #define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */ |
268 | |
| 269 | #define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */ |
269 | /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 |
| 270 | #define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */ |
270 | * @{ |
| 271 | #define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */ |
271 | */ |
| 272 | #define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */ |
272 | #define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */ |
| 273 | #define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */ |
273 | #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ |
| 274 | #define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */ |
274 | #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ |
| 275 | #define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */ |
275 | #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ |
| 276 | #define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */ |
276 | #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ |
| 277 | #define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */ |
277 | #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ |
| 278 | #define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */ |
278 | #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ |
| 279 | #define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */ |
279 | #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ |
| 280 | #define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */ |
280 | /** |
| 281 | #define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */ |
281 | * @} |
| 282 | /** |
282 | */ |
| 283 | * @} |
283 | |
| 284 | */ |
284 | /** @defgroup CAN_filter_mode CAN Filter Mode |
| 285 | 285 | * @{ |
|
| 286 | /** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2 |
286 | */ |
| 287 | * @{ |
287 | #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ |
| 288 | */ |
288 | #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ |
| 289 | #define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */ |
289 | /** |
| 290 | #define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */ |
290 | * @} |
| 291 | #define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */ |
291 | */ |
| 292 | #define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */ |
292 | |
| 293 | #define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */ |
293 | /** @defgroup CAN_filter_scale CAN Filter Scale |
| 294 | #define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */ |
294 | * @{ |
| 295 | #define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */ |
295 | */ |
| 296 | #define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */ |
296 | #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ |
| 297 | /** |
297 | #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ |
| 298 | * @} |
298 | /** |
| 299 | */ |
299 | * @} |
| 300 | 300 | */ |
|
| 301 | /** @defgroup CAN_filter_mode CAN Filter Mode |
301 | |
| 302 | * @{ |
302 | /** @defgroup CAN_filter_FIFO CAN Filter FIFO |
| 303 | */ |
303 | * @{ |
| 304 | #define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */ |
304 | */ |
| 305 | #define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */ |
305 | #define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ |
| 306 | /** |
306 | #define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ |
| 307 | * @} |
307 | /** |
| 308 | */ |
308 | * @} |
| 309 | 309 | */ |
|
| 310 | /** @defgroup CAN_filter_scale CAN Filter Scale |
310 | |
| 311 | * @{ |
311 | /** @defgroup CAN_Identifier_Type CAN Identifier Type |
| 312 | */ |
312 | * @{ |
| 313 | #define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */ |
313 | */ |
| 314 | #define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */ |
314 | #define CAN_ID_STD 0x00000000U /*!< Standard Id */ |
| 315 | /** |
315 | #define CAN_ID_EXT 0x00000004U /*!< Extended Id */ |
| 316 | * @} |
316 | /** |
| 317 | */ |
317 | * @} |
| 318 | 318 | */ |
|
| 319 | /** @defgroup CAN_filter_FIFO CAN Filter FIFO |
319 | |
| 320 | * @{ |
320 | /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request |
| 321 | */ |
321 | * @{ |
| 322 | #define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */ |
322 | */ |
| 323 | #define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */ |
323 | #define CAN_RTR_DATA 0x00000000U /*!< Data frame */ |
| 324 | /** |
324 | #define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */ |
| 325 | * @} |
325 | /** |
| 326 | */ |
326 | * @} |
| 327 | 327 | */ |
|
| 328 | /** @defgroup CAN_Identifier_Type CAN Identifier Type |
328 | |
| 329 | * @{ |
329 | /** @defgroup CAN_transmit_constants CAN Transmit Constants |
| 330 | */ |
330 | * @{ |
| 331 | #define CAN_ID_STD 0x00000000U /*!< Standard Id */ |
331 | */ |
| 332 | #define CAN_ID_EXT 0x00000004U /*!< Extended Id */ |
332 | #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ |
| 333 | /** |
333 | /** |
| 334 | * @} |
334 | * @} |
| 335 | */ |
335 | */ |
| 336 | 336 | ||
| 337 | /** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request |
337 | /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number |
| 338 | * @{ |
338 | * @{ |
| 339 | */ |
339 | */ |
| 340 | #define CAN_RTR_DATA 0x00000000U /*!< Data frame */ |
340 | #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ |
| 341 | #define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */ |
341 | #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ |
| 342 | /** |
342 | /** |
| 343 | * @} |
343 | * @} |
| 344 | */ |
344 | */ |
| 345 | 345 | ||
| 346 | /** @defgroup CAN_transmit_constants CAN Transmit Constants |
346 | /** @defgroup CAN_flags CAN Flags |
| 347 | * @{ |
347 | * @{ |
| 348 | */ |
348 | */ |
| 349 | #define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */ |
349 | /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() |
| 350 | /** |
350 | and CAN_ClearFlag() functions. */ |
| 351 | * @} |
351 | /* If the flag is 0x1XXXXXXX, it means that it can only be used with |
| 352 | */ |
352 | CAN_GetFlagStatus() function. */ |
| 353 | 353 | ||
| 354 | /** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number |
354 | /* Transmit Flags */ |
| 355 | * @{ |
355 | #define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Request MailBox0 flag */ |
| 356 | */ |
356 | #define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION)) /*!< Request MailBox1 flag */ |
| 357 | #define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */ |
357 | #define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION)) /*!< Request MailBox2 flag */ |
| 358 | #define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */ |
358 | #define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION)) /*!< Transmission OK MailBox0 flag */ |
| 359 | /** |
359 | #define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION)) /*!< Transmission OK MailBox1 flag */ |
| 360 | * @} |
360 | #define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK2_BIT_POSITION)) /*!< Transmission OK MailBox2 flag */ |
| 361 | */ |
361 | #define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */ |
| 362 | 362 | #define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */ |
|
| 363 | /** @defgroup CAN_flags CAN Flags |
363 | #define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */ |
| 364 | * @{ |
364 | |
| 365 | */ |
365 | /* Receive Flags */ |
| 366 | /* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() |
366 | #define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION)) /*!< FIFO 0 Full flag */ |
| 367 | and CAN_ClearFlag() functions. */ |
367 | #define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */ |
| 368 | /* If the flag is 0x1XXXXXXX, it means that it can only be used with |
368 | |
| 369 | CAN_GetFlagStatus() function. */ |
369 | #define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION)) /*!< FIFO 1 Full flag */ |
| 370 | 370 | #define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */ |
|
| 371 | /* Transmit Flags */ |
371 | |
| 372 | #define CAN_FLAG_RQCP0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP0_BIT_POSITION)) /*!< Request MailBox0 flag */ |
372 | /* Operating Mode Flags */ |
| 373 | #define CAN_FLAG_RQCP1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP1_BIT_POSITION)) /*!< Request MailBox1 flag */ |
373 | #define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */ |
| 374 | #define CAN_FLAG_RQCP2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_RQCP2_BIT_POSITION)) /*!< Request MailBox2 flag */ |
374 | #define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */ |
| 375 | #define CAN_FLAG_TXOK0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK0_BIT_POSITION)) /*!< Transmission OK MailBox0 flag */ |
375 | #define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */ |
| 376 | #define CAN_FLAG_TXOK1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK1_BIT_POSITION)) /*!< Transmission OK MailBox1 flag */ |
376 | |
| 377 | #define CAN_FLAG_TXOK2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TXOK2_BIT_POSITION)) /*!< Transmission OK MailBox2 flag */ |
377 | /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. |
| 378 | #define CAN_FLAG_TME0 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME0_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */ |
378 | In this case the SLAK bit can be polled.*/ |
| 379 | #define CAN_FLAG_TME1 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME1_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */ |
379 | |
| 380 | #define CAN_FLAG_TME2 ((uint32_t)((TSR_REGISTER_INDEX << 8U) | CAN_TSR_TME2_BIT_POSITION)) /*!< Transmit mailbox 0 empty flag */ |
380 | /* Error Flags */ |
| 381 | 381 | #define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION)) /*!< Error warning flag */ |
|
| 382 | /* Receive Flags */ |
382 | #define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION)) /*!< Error passive flag */ |
| 383 | #define CAN_FLAG_FF0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FF0_BIT_POSITION)) /*!< FIFO 0 Full flag */ |
383 | #define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION)) /*!< Bus-Off flag */ |
| 384 | #define CAN_FLAG_FOV0 ((uint32_t)((RF0R_REGISTER_INDEX << 8U) | CAN_RF0R_FOV0_BIT_POSITION)) /*!< FIFO 0 Overrun flag */ |
384 | |
| 385 | 385 | /** |
|
| 386 | #define CAN_FLAG_FF1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FF1_BIT_POSITION)) /*!< FIFO 1 Full flag */ |
386 | * @} |
| 387 | #define CAN_FLAG_FOV1 ((uint32_t)((RF1R_REGISTER_INDEX << 8U) | CAN_RF1R_FOV1_BIT_POSITION)) /*!< FIFO 1 Overrun flag */ |
387 | */ |
| 388 | 388 | ||
| 389 | /* Operating Mode Flags */ |
389 | /** @defgroup CAN_Interrupts CAN Interrupts |
| 390 | #define CAN_FLAG_WKU ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_WKU_BIT_POSITION)) /*!< Wake up flag */ |
390 | * @{ |
| 391 | #define CAN_FLAG_SLAK ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAK_BIT_POSITION)) /*!< Sleep acknowledge flag */ |
391 | */ |
| 392 | #define CAN_FLAG_SLAKI ((uint32_t)((MSR_REGISTER_INDEX << 8U) | CAN_MSR_SLAKI_BIT_POSITION)) /*!< Sleep acknowledge flag */ |
392 | #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ |
| 393 | 393 | ||
| 394 | /* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. |
394 | /* Receive Interrupts */ |
| 395 | In this case the SLAK bit can be polled.*/ |
395 | #define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ |
| 396 | 396 | #define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ |
|
| 397 | /* Error Flags */ |
397 | #define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ |
| 398 | #define CAN_FLAG_EWG ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EWG_BIT_POSITION)) /*!< Error warning flag */ |
398 | #define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ |
| 399 | #define CAN_FLAG_EPV ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_EPV_BIT_POSITION)) /*!< Error passive flag */ |
399 | #define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ |
| 400 | #define CAN_FLAG_BOF ((uint32_t)((ESR_REGISTER_INDEX << 8U) | CAN_ESR_BOF_BIT_POSITION)) /*!< Bus-Off flag */ |
400 | #define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ |
| 401 | 401 | ||
| 402 | /** |
402 | /* Operating Mode Interrupts */ |
| 403 | * @} |
403 | #define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ |
| 404 | */ |
404 | #define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ |
| 405 | 405 | ||
| 406 | /** @defgroup CAN_Interrupts CAN Interrupts |
406 | /* Error Interrupts */ |
| 407 | * @{ |
407 | #define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ |
| 408 | */ |
408 | #define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ |
| 409 | #define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */ |
409 | #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ |
| 410 | 410 | #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ |
|
| 411 | /* Receive Interrupts */ |
411 | #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ |
| 412 | #define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */ |
412 | /** |
| 413 | #define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */ |
413 | * @} |
| 414 | #define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */ |
414 | */ |
| 415 | #define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */ |
415 | |
| 416 | #define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */ |
416 | /** |
| 417 | #define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */ |
417 | * @} |
| 418 | 418 | */ |
|
| 419 | /* Operating Mode Interrupts */ |
419 | |
| 420 | #define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */ |
420 | /** @defgroup CAN_Private_Constants CAN Private Constants |
| 421 | #define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */ |
421 | * @{ |
| 422 | 422 | */ |
|
| 423 | /* Error Interrupts */ |
423 | |
| 424 | #define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */ |
424 | /* CAN intermediate shift values used for CAN flags */ |
| 425 | #define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */ |
425 | #define TSR_REGISTER_INDEX 0x5U |
| 426 | #define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */ |
426 | #define RF0R_REGISTER_INDEX 0x2U |
| 427 | #define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */ |
427 | #define RF1R_REGISTER_INDEX 0x4U |
| 428 | #define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */ |
428 | #define MSR_REGISTER_INDEX 0x1U |
| 429 | /** |
429 | #define ESR_REGISTER_INDEX 0x3U |
| 430 | * @} |
430 | |
| 431 | */ |
431 | /* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR registers) */ |
| 432 | 432 | /* Transmit Flags */ |
|
| 433 | /** |
433 | #define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U |
| 434 | * @} |
434 | #define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U |
| 435 | */ |
435 | #define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U |
| 436 | 436 | #define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U |
|
| 437 | /** @defgroup CAN_Private_Constants CAN Private Constants |
437 | #define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U |
| 438 | * @{ |
438 | #define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U |
| 439 | */ |
439 | #define CAN_TSR_TME0_BIT_POSITION 0x0000001AU |
| 440 | 440 | #define CAN_TSR_TME1_BIT_POSITION 0x0000001BU |
|
| 441 | /* CAN intermediate shift values used for CAN flags */ |
441 | #define CAN_TSR_TME2_BIT_POSITION 0x0000001CU |
| 442 | #define TSR_REGISTER_INDEX 0x5U |
442 | |
| 443 | #define RF0R_REGISTER_INDEX 0x2U |
443 | /* Receive Flags */ |
| 444 | #define RF1R_REGISTER_INDEX 0x4U |
444 | #define CAN_RF0R_FF0_BIT_POSITION 0x00000003U |
| 445 | #define MSR_REGISTER_INDEX 0x1U |
445 | #define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U |
| 446 | #define ESR_REGISTER_INDEX 0x3U |
446 | |
| 447 | 447 | #define CAN_RF1R_FF1_BIT_POSITION 0x00000003U |
|
| 448 | /* CAN flags bits position into their respective register (TSR, RF0R, RF1R or MSR regsiters) */ |
448 | #define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U |
| 449 | /* Transmit Flags */ |
449 | |
| 450 | #define CAN_TSR_RQCP0_BIT_POSITION 0x00000000U |
450 | /* Operating Mode Flags */ |
| 451 | #define CAN_TSR_RQCP1_BIT_POSITION 0x00000008U |
451 | #define CAN_MSR_WKU_BIT_POSITION 0x00000003U |
| 452 | #define CAN_TSR_RQCP2_BIT_POSITION 0x00000010U |
452 | #define CAN_MSR_SLAK_BIT_POSITION 0x00000001U |
| 453 | #define CAN_TSR_TXOK0_BIT_POSITION 0x00000001U |
453 | #define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U |
| 454 | #define CAN_TSR_TXOK1_BIT_POSITION 0x00000009U |
454 | |
| 455 | #define CAN_TSR_TXOK2_BIT_POSITION 0x00000011U |
455 | /* Error Flags */ |
| 456 | #define CAN_TSR_TME0_BIT_POSITION 0x0000001AU |
456 | #define CAN_ESR_EWG_BIT_POSITION 0x00000000U |
| 457 | #define CAN_TSR_TME1_BIT_POSITION 0x0000001BU |
457 | #define CAN_ESR_EPV_BIT_POSITION 0x00000001U |
| 458 | #define CAN_TSR_TME2_BIT_POSITION 0x0000001CU |
458 | #define CAN_ESR_BOF_BIT_POSITION 0x00000002U |
| 459 | 459 | ||
| 460 | /* Receive Flags */ |
460 | /* Mask used by macro to get/clear CAN flags*/ |
| 461 | #define CAN_RF0R_FF0_BIT_POSITION 0x00000003U |
461 | #define CAN_FLAG_MASK 0x000000FFU |
| 462 | #define CAN_RF0R_FOV0_BIT_POSITION 0x00000004U |
462 | |
| 463 | 463 | /* Mailboxes definition */ |
|
| 464 | #define CAN_RF1R_FF1_BIT_POSITION 0x00000003U |
464 | #define CAN_TXMAILBOX_0 ((uint8_t)0x00) |
| 465 | #define CAN_RF1R_FOV1_BIT_POSITION 0x00000004U |
465 | #define CAN_TXMAILBOX_1 ((uint8_t)0x01) |
| 466 | 466 | #define CAN_TXMAILBOX_2 ((uint8_t)0x02) |
|
| 467 | /* Operating Mode Flags */ |
467 | /** |
| 468 | #define CAN_MSR_WKU_BIT_POSITION 0x00000003U |
468 | * @} |
| 469 | #define CAN_MSR_SLAK_BIT_POSITION 0x00000001U |
469 | */ |
| 470 | #define CAN_MSR_SLAKI_BIT_POSITION 0x00000004U |
470 | |
| 471 | 471 | /* Exported macros -----------------------------------------------------------*/ |
|
| 472 | /* Error Flags */ |
472 | /** @defgroup CAN_Exported_Macros CAN Exported Macros |
| 473 | #define CAN_ESR_EWG_BIT_POSITION 0x00000000U |
473 | * @{ |
| 474 | #define CAN_ESR_EPV_BIT_POSITION 0x00000001U |
474 | */ |
| 475 | #define CAN_ESR_BOF_BIT_POSITION 0x00000002U |
475 | |
| 476 | 476 | /** @brief Reset CAN handle state |
|
| 477 | /* Mask used by macro to get/clear CAN flags*/ |
477 | * @param __HANDLE__: CAN handle. |
| 478 | #define CAN_FLAG_MASK 0x000000FFU |
478 | * @retval None |
| 479 | 479 | */ |
|
| 480 | /* Mailboxes definition */ |
480 | #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) |
| 481 | #define CAN_TXMAILBOX_0 ((uint8_t)0x00) |
481 | |
| 482 | #define CAN_TXMAILBOX_1 ((uint8_t)0x01) |
482 | /** |
| 483 | #define CAN_TXMAILBOX_2 ((uint8_t)0x02) |
483 | * @brief Enable the specified CAN interrupts |
| 484 | /** |
484 | * @param __HANDLE__: CAN handle. |
| 485 | * @} |
485 | * @param __INTERRUPT__: CAN Interrupt. |
| 486 | */ |
486 | * This parameter can be one of the following values: |
| 487 | 487 | * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable |
|
| 488 | /* Exported macros -----------------------------------------------------------*/ |
488 | * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt |
| 489 | /** @defgroup CAN_Exported_Macros CAN Exported Macros |
489 | * @arg CAN_IT_FF0 : FIFO 0 full interrupt |
| 490 | * @{ |
490 | * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt |
| 491 | */ |
491 | * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt |
| 492 | 492 | * @arg CAN_IT_FF1 : FIFO 1 full interrupt |
|
| 493 | /** @brief Reset CAN handle state |
493 | * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt |
| 494 | * @param __HANDLE__: CAN handle. |
494 | * @arg CAN_IT_WKU : Wake-up interrupt |
| 495 | * @retval None |
495 | * @arg CAN_IT_SLK : Sleep acknowledge interrupt |
| 496 | */ |
496 | * @arg CAN_IT_EWG : Error warning interrupt |
| 497 | #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET) |
497 | * @arg CAN_IT_EPV : Error passive interrupt |
| 498 | 498 | * @arg CAN_IT_BOF : Bus-off interrupt |
|
| 499 | /** |
499 | * @arg CAN_IT_LEC : Last error code interrupt |
| 500 | * @brief Enable the specified CAN interrupts |
500 | * @arg CAN_IT_ERR : Error Interrupt |
| 501 | * @param __HANDLE__: CAN handle. |
501 | * @retval None. |
| 502 | * @param __INTERRUPT__: CAN Interrupt. |
502 | */ |
| 503 | * This parameter can be one of the following values: |
503 | #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) |
| 504 | * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable |
504 | |
| 505 | * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt |
505 | /** |
| 506 | * @arg CAN_IT_FF0 : FIFO 0 full interrupt |
506 | * @brief Disable the specified CAN interrupts |
| 507 | * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt |
507 | * @param __HANDLE__: CAN handle. |
| 508 | * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt |
508 | * @param __INTERRUPT__: CAN Interrupt. |
| 509 | * @arg CAN_IT_FF1 : FIFO 1 full interrupt |
509 | * This parameter can be one of the following values: |
| 510 | * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt |
510 | * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable |
| 511 | * @arg CAN_IT_WKU : Wake-up interrupt |
511 | * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt |
| 512 | * @arg CAN_IT_SLK : Sleep acknowledge interrupt |
512 | * @arg CAN_IT_FF0 : FIFO 0 full interrupt |
| 513 | * @arg CAN_IT_EWG : Error warning interrupt |
513 | * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt |
| 514 | * @arg CAN_IT_EPV : Error passive interrupt |
514 | * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt |
| 515 | * @arg CAN_IT_BOF : Bus-off interrupt |
515 | * @arg CAN_IT_FF1 : FIFO 1 full interrupt |
| 516 | * @arg CAN_IT_LEC : Last error code interrupt |
516 | * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt |
| 517 | * @arg CAN_IT_ERR : Error Interrupt |
517 | * @arg CAN_IT_WKU : Wake-up interrupt |
| 518 | * @retval None. |
518 | * @arg CAN_IT_SLK : Sleep acknowledge interrupt |
| 519 | */ |
519 | * @arg CAN_IT_EWG : Error warning interrupt |
| 520 | #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) |
520 | * @arg CAN_IT_EPV : Error passive interrupt |
| 521 | 521 | * @arg CAN_IT_BOF : Bus-off interrupt |
|
| 522 | /** |
522 | * @arg CAN_IT_LEC : Last error code interrupt |
| 523 | * @brief Disable the specified CAN interrupts |
523 | * @arg CAN_IT_ERR : Error Interrupt |
| 524 | * @param __HANDLE__: CAN handle. |
524 | * @retval None. |
| 525 | * @param __INTERRUPT__: CAN Interrupt. |
525 | */ |
| 526 | * This parameter can be one of the following values: |
526 | #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) |
| 527 | * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable |
527 | |
| 528 | * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt |
528 | /** |
| 529 | * @arg CAN_IT_FF0 : FIFO 0 full interrupt |
529 | * @brief Return the number of pending received messages. |
| 530 | * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt |
530 | * @param __HANDLE__: CAN handle. |
| 531 | * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt |
531 | * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. |
| 532 | * @arg CAN_IT_FF1 : FIFO 1 full interrupt |
532 | * @retval The number of pending message. |
| 533 | * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt |
533 | */ |
| 534 | * @arg CAN_IT_WKU : Wake-up interrupt |
534 | #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ |
| 535 | * @arg CAN_IT_SLK : Sleep acknowledge interrupt |
535 | ((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U))) |
| 536 | * @arg CAN_IT_EWG : Error warning interrupt |
536 | |
| 537 | * @arg CAN_IT_EPV : Error passive interrupt |
537 | /** @brief Check whether the specified CAN flag is set or not. |
| 538 | * @arg CAN_IT_BOF : Bus-off interrupt |
538 | * @param __HANDLE__: specifies the CAN Handle. |
| 539 | * @arg CAN_IT_LEC : Last error code interrupt |
539 | * @param __FLAG__: specifies the flag to check. |
| 540 | * @arg CAN_IT_ERR : Error Interrupt |
540 | * This parameter can be one of the following values: |
| 541 | * @retval None. |
541 | * @arg CAN_TSR_RQCP0: Request MailBox0 Flag |
| 542 | */ |
542 | * @arg CAN_TSR_RQCP1: Request MailBox1 Flag |
| 543 | #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) |
543 | * @arg CAN_TSR_RQCP2: Request MailBox2 Flag |
| 544 | 544 | * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag |
|
| 545 | /** |
545 | * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag |
| 546 | * @brief Return the number of pending received messages. |
546 | * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag |
| 547 | * @param __HANDLE__: CAN handle. |
547 | * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag |
| 548 | * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. |
548 | * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag |
| 549 | * @retval The number of pending message. |
549 | * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag |
| 550 | */ |
550 | * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag |
| 551 | #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ |
551 | * @arg CAN_FLAG_FF0: FIFO 0 Full Flag |
| 552 | ((uint8_t)((__HANDLE__)->Instance->RF0R & 0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U))) |
552 | * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag |
| 553 | 553 | * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag |
|
| 554 | /** @brief Check whether the specified CAN flag is set or not. |
554 | * @arg CAN_FLAG_FF1: FIFO 1 Full Flag |
| 555 | * @param __HANDLE__: specifies the CAN Handle. |
555 | * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag |
| 556 | * @param __FLAG__: specifies the flag to check. |
556 | * @arg CAN_FLAG_WKU: Wake up Flag |
| 557 | * This parameter can be one of the following values: |
557 | * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag |
| 558 | * @arg CAN_TSR_RQCP0: Request MailBox0 Flag |
558 | * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag |
| 559 | * @arg CAN_TSR_RQCP1: Request MailBox1 Flag |
559 | * @arg CAN_FLAG_EWG: Error Warning Flag |
| 560 | * @arg CAN_TSR_RQCP2: Request MailBox2 Flag |
560 | * @arg CAN_FLAG_EPV: Error Passive Flag |
| 561 | * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag |
561 | * @arg CAN_FLAG_BOF: Bus-Off Flag |
| 562 | * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag |
562 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| 563 | * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag |
563 | */ |
| 564 | * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag |
564 | #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ |
| 565 | * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag |
565 | ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
| 566 | * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag |
566 | (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
| 567 | * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag |
567 | (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
| 568 | * @arg CAN_FLAG_FF0: FIFO 0 Full Flag |
568 | (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
| 569 | * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag |
569 | ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) |
| 570 | * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag |
570 | |
| 571 | * @arg CAN_FLAG_FF1: FIFO 1 Full Flag |
571 | /** @brief Clear the specified CAN pending flag. |
| 572 | * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag |
572 | * @param __HANDLE__: specifies the CAN Handle. |
| 573 | * @arg CAN_FLAG_WKU: Wake up Flag |
573 | * @param __FLAG__: specifies the flag to check. |
| 574 | * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag |
574 | * This parameter can be one of the following values: |
| 575 | * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag |
575 | * @arg CAN_TSR_RQCP0: Request MailBox0 Flag |
| 576 | * @arg CAN_FLAG_EWG: Error Warning Flag |
576 | * @arg CAN_TSR_RQCP1: Request MailBox1 Flag |
| 577 | * @arg CAN_FLAG_EPV: Error Passive Flag |
577 | * @arg CAN_TSR_RQCP2: Request MailBox2 Flag |
| 578 | * @arg CAN_FLAG_BOF: Bus-Off Flag |
578 | * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag |
| 579 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
579 | * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag |
| 580 | */ |
580 | * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag |
| 581 | #define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \ |
581 | * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag |
| 582 | ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
582 | * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag |
| 583 | (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
583 | * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag |
| 584 | (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
584 | * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag |
| 585 | (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
585 | * @arg CAN_FLAG_FF0: FIFO 0 Full Flag |
| 586 | ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK)))) |
586 | * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag |
| 587 | 587 | * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag |
|
| 588 | /** @brief Clear the specified CAN pending flag. |
588 | * @arg CAN_FLAG_FF1: FIFO 1 Full Flag |
| 589 | * @param __HANDLE__: specifies the CAN Handle. |
589 | * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag |
| 590 | * @param __FLAG__: specifies the flag to check. |
590 | * @arg CAN_FLAG_WKU: Wake up Flag |
| 591 | * This parameter can be one of the following values: |
591 | * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag |
| 592 | * @arg CAN_TSR_RQCP0: Request MailBox0 Flag |
592 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| 593 | * @arg CAN_TSR_RQCP1: Request MailBox1 Flag |
593 | */ |
| 594 | * @arg CAN_TSR_RQCP2: Request MailBox2 Flag |
594 | #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
| 595 | * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag |
595 | ((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
| 596 | * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag |
596 | (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
| 597 | * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag |
597 | (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
| 598 | * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag |
598 | (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) |
| 599 | * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag |
599 | |
| 600 | * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag |
600 | /** @brief Check if the specified CAN interrupt source is enabled or disabled. |
| 601 | * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag |
601 | * @param __HANDLE__: specifies the CAN Handle. |
| 602 | * @arg CAN_FLAG_FF0: FIFO 0 Full Flag |
602 | * @param __INTERRUPT__: specifies the CAN interrupt source to check. |
| 603 | * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag |
603 | * This parameter can be one of the following values: |
| 604 | * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag |
604 | * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable |
| 605 | * @arg CAN_FLAG_FF1: FIFO 1 Full Flag |
605 | * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt |
| 606 | * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag |
606 | * @arg CAN_IT_FF0 : FIFO 0 full interrupt |
| 607 | * @arg CAN_FLAG_WKU: Wake up Flag |
607 | * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt |
| 608 | * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag |
608 | * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt |
| 609 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
609 | * @arg CAN_IT_FF1 : FIFO 1 full interrupt |
| 610 | */ |
610 | * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt |
| 611 | #define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
611 | * @arg CAN_IT_WKU : Wake-up interrupt |
| 612 | ((((__FLAG__) >> 8U) == TSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
612 | * @arg CAN_IT_SLK : Sleep acknowledge interrupt |
| 613 | (((__FLAG__) >> 8U) == RF0R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
613 | * @arg CAN_IT_EWG : Error warning interrupt |
| 614 | (((__FLAG__) >> 8U) == RF1R_REGISTER_INDEX)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \ |
614 | * @arg CAN_IT_EPV : Error passive interrupt |
| 615 | (((__FLAG__) >> 8U) == MSR_REGISTER_INDEX) ? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U) |
615 | * @arg CAN_IT_BOF : Bus-off interrupt |
| 616 | 616 | * @arg CAN_IT_LEC : Last error code interrupt |
|
| 617 | /** @brief Check if the specified CAN interrupt source is enabled or disabled. |
617 | * @arg CAN_IT_ERR : Error Interrupt |
| 618 | * @param __HANDLE__: specifies the CAN Handle. |
618 | * @retval The new state of __IT__ (TRUE or FALSE). |
| 619 | * @param __INTERRUPT__: specifies the CAN interrupt source to check. |
619 | */ |
| 620 | * This parameter can be one of the following values: |
620 | #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| 621 | * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable |
621 | |
| 622 | * @arg CAN_IT_FMP0: FIFO 0 message pending interrupt |
622 | /** |
| 623 | * @arg CAN_IT_FF0 : FIFO 0 full interrupt |
623 | * @brief Check the transmission status of a CAN Frame. |
| 624 | * @arg CAN_IT_FOV0: FIFO 0 overrun interrupt |
624 | * @param __HANDLE__: specifies the CAN Handle. |
| 625 | * @arg CAN_IT_FMP1: FIFO 1 message pending interrupt |
625 | * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. |
| 626 | * @arg CAN_IT_FF1 : FIFO 1 full interrupt |
626 | * @retval The new status of transmission (TRUE or FALSE). |
| 627 | * @arg CAN_IT_FOV1: FIFO 1 overrun interrupt |
627 | */ |
| 628 | * @arg CAN_IT_WKU : Wake-up interrupt |
628 | #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ |
| 629 | * @arg CAN_IT_SLK : Sleep acknowledge interrupt |
629 | (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\ |
| 630 | * @arg CAN_IT_EWG : Error warning interrupt |
630 | ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\ |
| 631 | * @arg CAN_IT_EPV : Error passive interrupt |
631 | ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2))) |
| 632 | * @arg CAN_IT_BOF : Bus-off interrupt |
632 | |
| 633 | * @arg CAN_IT_LEC : Last error code interrupt |
633 | /** |
| 634 | * @arg CAN_IT_ERR : Error Interrupt |
634 | * @brief Release the specified receive FIFO. |
| 635 | * @retval The new state of __IT__ (TRUE or FALSE). |
635 | * @param __HANDLE__: CAN handle. |
| 636 | */ |
636 | * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. |
| 637 | #define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
637 | * @retval None. |
| 638 | 638 | */ |
|
| 639 | /** |
639 | #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ |
| 640 | * @brief Check the transmission status of a CAN Frame. |
640 | ((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) |
| 641 | * @param __HANDLE__: specifies the CAN Handle. |
641 | |
| 642 | * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. |
642 | /** |
| 643 | * @retval The new status of transmission (TRUE or FALSE). |
643 | * @brief Cancel a transmit request. |
| 644 | */ |
644 | * @param __HANDLE__: specifies the CAN Handle. |
| 645 | #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\ |
645 | * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. |
| 646 | (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\ |
646 | * @retval None. |
| 647 | ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\ |
647 | */ |
| 648 | ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2))) |
648 | #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ |
| 649 | 649 | (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ |
|
| 650 | /** |
650 | ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ |
| 651 | * @brief Release the specified receive FIFO. |
651 | ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) |
| 652 | * @param __HANDLE__: CAN handle. |
652 | |
| 653 | * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1. |
653 | /** |
| 654 | * @retval None. |
654 | * @brief Enable or disables the DBG Freeze for CAN. |
| 655 | */ |
655 | * @param __HANDLE__: specifies the CAN Handle. |
| 656 | #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \ |
656 | * @param __NEWSTATE__: new state of the CAN peripheral. |
| 657 | ((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1)) |
657 | * This parameter can be: ENABLE (CAN reception/transmission is frozen |
| 658 | 658 | * during debug. Reception FIFOs can still be accessed/controlled normally) |
|
| 659 | /** |
659 | * or DISABLE (CAN is working during debug). |
| 660 | * @brief Cancel a transmit request. |
660 | * @retval None |
| 661 | * @param __HANDLE__: specifies the CAN Handle. |
661 | */ |
| 662 | * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission. |
662 | #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ |
| 663 | * @retval None. |
663 | ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) |
| 664 | */ |
664 | |
| 665 | #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\ |
665 | /** |
| 666 | (((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\ |
666 | * @} |
| 667 | ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\ |
667 | */ |
| 668 | ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2)) |
668 | |
| 669 | 669 | /* Include CAN HAL Extension module */ |
|
| 670 | /** |
670 | #include "stm32f1xx_hal_can_ex_legacy.h" |
| 671 | * @brief Enable or disables the DBG Freeze for CAN. |
671 | |
| 672 | * @param __HANDLE__: specifies the CAN Handle. |
672 | /* Exported functions --------------------------------------------------------*/ |
| 673 | * @param __NEWSTATE__: new state of the CAN peripheral. |
673 | /** @addtogroup CAN_Exported_Functions |
| 674 | * This parameter can be: ENABLE (CAN reception/transmission is frozen |
674 | * @{ |
| 675 | * during debug. Reception FIFOs can still be accessed/controlled normally) |
675 | */ |
| 676 | * or DISABLE (CAN is working during debug). |
676 | |
| 677 | * @retval None |
677 | /** @addtogroup CAN_Exported_Functions_Group1 |
| 678 | */ |
678 | * @brief Initialization and Configuration functions |
| 679 | #define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \ |
679 | * @{ |
| 680 | ((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF)) |
680 | */ |
| 681 | 681 | /* Initialization and de-initialization functions *****************************/ |
|
| 682 | /** |
682 | HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); |
| 683 | * @} |
683 | HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); |
| 684 | */ |
684 | HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); |
| 685 | 685 | void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); |
|
| 686 | /* Include CAN HAL Extension module */ |
686 | void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); |
| 687 | #include "stm32f1xx_hal_can_ex_legacy.h" |
687 | /** |
| 688 | 688 | * @} |
|
| 689 | /* Exported functions --------------------------------------------------------*/ |
689 | */ |
| 690 | /** @addtogroup CAN_Exported_Functions |
690 | |
| 691 | * @{ |
691 | /** @addtogroup CAN_Exported_Functions_Group2 |
| 692 | */ |
692 | * @brief I/O operation functions |
| 693 | 693 | * @{ |
|
| 694 | /** @addtogroup CAN_Exported_Functions_Group1 |
694 | */ |
| 695 | * @brief Initialization and Configuration functions |
695 | /* I/O operation functions *****************************************************/ |
| 696 | * @{ |
696 | HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); |
| 697 | */ |
697 | HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); |
| 698 | /* Initialization and de-initialization functions *****************************/ |
698 | HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); |
| 699 | HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan); |
699 | HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); |
| 700 | HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig); |
700 | HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); |
| 701 | HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan); |
701 | HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); |
| 702 | void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan); |
702 | void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); |
| 703 | void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan); |
703 | void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); |
| 704 | /** |
704 | void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); |
| 705 | * @} |
705 | void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); |
| 706 | */ |
706 | /** |
| 707 | 707 | * @} |
|
| 708 | /** @addtogroup CAN_Exported_Functions_Group2 |
708 | */ |
| 709 | * @brief I/O operation functions |
709 | |
| 710 | * @{ |
710 | /** @addtogroup CAN_Exported_Functions_Group3 |
| 711 | */ |
711 | * @brief CAN Peripheral State functions |
| 712 | /* I/O operation functions *****************************************************/ |
712 | * @{ |
| 713 | HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout); |
713 | */ |
| 714 | HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan); |
714 | /* Peripheral State and Error functions ***************************************/ |
| 715 | HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout); |
715 | uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); |
| 716 | HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber); |
716 | HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); |
| 717 | HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan); |
717 | /** |
| 718 | HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan); |
718 | * @} |
| 719 | void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan); |
719 | */ |
| 720 | void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan); |
720 | |
| 721 | void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan); |
721 | /** |
| 722 | void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan); |
722 | * @} |
| 723 | /** |
723 | */ |
| 724 | * @} |
724 | |
| 725 | */ |
725 | /* Private macros --------------------------------------------------------*/ |
| 726 | 726 | /** @defgroup CAN_Private_Macros CAN Private Macros |
|
| 727 | /** @addtogroup CAN_Exported_Functions_Group3 |
727 | * @{ |
| 728 | * @brief CAN Peripheral State functions |
728 | */ |
| 729 | * @{ |
729 | |
| 730 | */ |
730 | #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ |
| 731 | /* Peripheral State and Error functions ***************************************/ |
731 | ((MODE) == CAN_MODE_LOOPBACK)|| \ |
| 732 | uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan); |
732 | ((MODE) == CAN_MODE_SILENT) || \ |
| 733 | HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan); |
733 | ((MODE) == CAN_MODE_SILENT_LOOPBACK)) |
| 734 | /** |
734 | #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ |
| 735 | * @} |
735 | ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) |
| 736 | */ |
736 | #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) |
| 737 | 737 | #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) |
|
| 738 | /** |
738 | #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) |
| 739 | * @} |
739 | |
| 740 | */ |
740 | #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ |
| 741 | 741 | ((MODE) == CAN_FILTERMODE_IDLIST)) |
|
| 742 | /* Private macros --------------------------------------------------------*/ |
742 | #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ |
| 743 | /** @defgroup CAN_Private_Macros CAN Private Macros |
743 | ((SCALE) == CAN_FILTERSCALE_32BIT)) |
| 744 | * @{ |
744 | #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ |
| 745 | */ |
745 | ((FIFO) == CAN_FILTER_FIFO1)) |
| 746 | 746 | #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) |
|
| 747 | #define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \ |
747 | |
| 748 | ((MODE) == CAN_MODE_LOOPBACK)|| \ |
748 | #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) |
| 749 | ((MODE) == CAN_MODE_SILENT) || \ |
749 | #define IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU) |
| 750 | ((MODE) == CAN_MODE_SILENT_LOOPBACK)) |
750 | #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) |
| 751 | #define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \ |
751 | #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) |
| 752 | ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ)) |
752 | |
| 753 | #define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ) |
753 | #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ |
| 754 | #define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ) |
754 | ((IDTYPE) == CAN_ID_EXT)) |
| 755 | #define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U)) |
755 | #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) |
| 756 | 756 | #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) |
|
| 757 | #define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \ |
757 | |
| 758 | ((MODE) == CAN_FILTERMODE_IDLIST)) |
758 | /** |
| 759 | #define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \ |
759 | * @} |
| 760 | ((SCALE) == CAN_FILTERSCALE_32BIT)) |
760 | */ |
| 761 | #define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \ |
761 | |
| 762 | ((FIFO) == CAN_FILTER_FIFO1)) |
762 | /** |
| 763 | #define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U) |
763 | * @} |
| 764 | 764 | */ |
|
| 765 | #define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02)) |
765 | |
| 766 | #define IS_CAN_STDID(STDID) ((STDID) <= 0x00007FFU) |
766 | /** |
| 767 | #define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU) |
767 | * @} |
| 768 | #define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08)) |
768 | */ |
| 769 | 769 | ||
| 770 | #define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \ |
770 | #endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */ |
| 771 | ((IDTYPE) == CAN_ID_EXT)) |
771 | |
| 772 | #define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE)) |
772 | #ifdef __cplusplus |
| 773 | #define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1)) |
773 | } |
| 774 | 774 | #endif |
|
| 775 | /** |
775 | |
| 776 | * @} |
776 | #endif /* __STM32F1xx_HAL_CAN_LEGACY_H */ |
| 777 | */ |
- | |
| 778 | - | ||
| 779 | /** |
- | |
| 780 | * @} |
- | |
| 781 | */ |
- | |
| 782 | - | ||
| 783 | /** |
- | |
| 784 | * @} |
- | |
| 785 | */ |
- | |
| 786 | - | ||
| 787 | #endif /* STM32F103x6) || STM32F103xB || STM32F103xE || STM32F103xG) || STM32F105xC || STM32F107xC */ |
- | |
| 788 | - | ||
| 789 | #ifdef __cplusplus |
- | |
| 790 | } |
- | |
| 791 | #endif |
- | |
| 792 | - | ||
| 793 | #endif /* __STM32F1xx_HAL_CAN_LEGACY_H */ |
- | |
| 794 | - | ||
| 795 | - | ||
| 796 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |