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/**
 1 
/**
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  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32_hal_legacy.h
 3 
  * @file    stm32_hal_legacy.h
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   This file contains aliases definition for the STM32Cube HAL constants
 5 
  * @brief   This file contains aliases definition for the STM32Cube HAL constants
6 
  *          macros and functions maintained for legacy purpose.
 6 
  *          macros and functions maintained for legacy purpose.
7 
  ******************************************************************************
 7 
  ******************************************************************************
8 
  * @attention
 8 
  * @attention
9 
  *
 9 
  *
10 
  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
 10 
  * Copyright (c) 2021 STMicroelectronics.
11 
  * All rights reserved.</center></h2>
 11 
  * All rights reserved.
12 
  *
 12 
  *
13 
  * This software component is licensed by ST under BSD 3-Clause license,
 13 
  * This software is licensed under terms that can be found in the LICENSE file
14 
  * the "License"; You may not use this file except in compliance with the
 14 
  * in the root directory of this software component.
15 
  * License. You may obtain a copy of the License at:
 15 
  * If no LICENSE file comes with this software, it is provided AS-IS.
16 
  *                        opensource.org/licenses/BSD-3-Clause
 16 
  *
17 
  *
 17 
  ******************************************************************************
18 
  ******************************************************************************
 18 
  */
19 
  */
 19 
 
20 
 
 20 
/* Define to prevent recursive inclusion -------------------------------------*/
21 
/* Define to prevent recursive inclusion -------------------------------------*/
 21 
#ifndef STM32_HAL_LEGACY
22 
#ifndef STM32_HAL_LEGACY
 22 
#define STM32_HAL_LEGACY
23 
#define STM32_HAL_LEGACY
 23 
 
24 
 
 24 
#ifdef __cplusplus
25 
#ifdef __cplusplus
 25 
extern "C" {
26 
 extern "C" {
 26 
#endif
27 
#endif
 27 
 
28 
 
 28 
/* Includes ------------------------------------------------------------------*/
29 
/* Includes ------------------------------------------------------------------*/
 29 
/* Exported types ------------------------------------------------------------*/
30 
/* Exported types ------------------------------------------------------------*/
 30 
/* Exported constants --------------------------------------------------------*/
31 
/* Exported constants --------------------------------------------------------*/
 31 
 
32 
 
 32 
/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
33 
/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose
 33 
  * @{
34 
  * @{
 34 
  */
35 
  */
 35 
#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
36 
#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR
 36 
#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
37 
#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR
 37 
#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
38 
#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF
 38 
#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
39 
#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR
 39 
#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
40 
#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR
 40 
#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
41 
/**
 41 
#define CRYP_DATATYPE_32B               CRYP_NO_SWAP
42 
  * @}
 42 
#define CRYP_DATATYPE_16B               CRYP_HALFWORD_SWAP
43 
  */
 43 
#define CRYP_DATATYPE_8B                CRYP_BYTE_SWAP
44 
 
 44 
#define CRYP_DATATYPE_1B                CRYP_BIT_SWAP
45 
/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
 45 
#if defined(STM32U5)
46 
  * @{
 46 
#define CRYP_CCF_CLEAR                  CRYP_CLEAR_CCF
47 
  */
 47 
#define CRYP_ERR_CLEAR                  CRYP_CLEAR_RWEIF
48 
#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
 48 
#endif /* STM32U5 */
49 
#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
 49 
#endif /* STM32U5 || STM32H7 || STM32MP1 */
50 
#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
 50 
/**
51 
#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
 51 
  * @}
52 
#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
 52 
  */
53 
#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
 53 
 
54 
#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
 54 
/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
55 
#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
 55 
  * @{
56 
#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
 56 
  */
57 
#define REGULAR_GROUP                   ADC_REGULAR_GROUP
 57 
#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B
58 
#define INJECTED_GROUP                  ADC_INJECTED_GROUP
 58 
#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B
59 
#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
 59 
#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B
60 
#define AWD_EVENT                       ADC_AWD_EVENT
 60 
#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B
61 
#define AWD1_EVENT                      ADC_AWD1_EVENT
 61 
#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN
62 
#define AWD2_EVENT                      ADC_AWD2_EVENT
 62 
#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED
63 
#define AWD3_EVENT                      ADC_AWD3_EVENT
 63 
#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV
64 
#define OVR_EVENT                       ADC_OVR_EVENT
 64 
#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV
65 
#define JQOVF_EVENT                     ADC_JQOVF_EVENT
 65 
#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV
66 
#define ALL_CHANNELS                    ADC_ALL_CHANNELS
 66 
#define REGULAR_GROUP                   ADC_REGULAR_GROUP
67 
#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
 67 
#define INJECTED_GROUP                  ADC_INJECTED_GROUP
68 
#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
 68 
#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP
69 
#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
 69 
#define AWD_EVENT                       ADC_AWD_EVENT
70 
#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
 70 
#define AWD1_EVENT                      ADC_AWD1_EVENT
71 
#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
 71 
#define AWD2_EVENT                      ADC_AWD2_EVENT
72 
#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
 72 
#define AWD3_EVENT                      ADC_AWD3_EVENT
73 
#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
 73 
#define OVR_EVENT                       ADC_OVR_EVENT
74 
#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
 74 
#define JQOVF_EVENT                     ADC_JQOVF_EVENT
75 
#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
 75 
#define ALL_CHANNELS                    ADC_ALL_CHANNELS
76 
#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
 76 
#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS
77 
#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
 77 
#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS
78 
#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
 78 
#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR
79 
#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
 79 
#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT
80 
#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
 80 
#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1
81 
#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
 81 
#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2
82 
#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
 82 
#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4
83 
#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
 83 
#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6
84 
#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
 84 
#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8
85 
#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
 85 
#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO
86 
#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
 86 
#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2
87 
#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
 87 
#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO
88 
 
 88 
#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4
89 
#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
 89 
#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO
90 
#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
 90 
#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11
91 
#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
 91 
#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1
92 
#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
 92 
#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE
93 
#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
 93 
#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING
94 
#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
 94 
#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING
95 
#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
 95 
#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
96 
 
 96 
#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5
97 
#if defined(STM32H7)
 97 
 
98 
#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
 98 
#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY
99 
#endif /* STM32H7 */
 99 
#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY
100 
/**
 100 
#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC
101 
  * @}
 101 
#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC
102 
  */
 102 
#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL
103 
 
 103 
#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL
104 
/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
 104 
#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1
105 
  * @{
 105 
 
106 
  */
 106 
#if defined(STM32H7)
107 
 
 107 
#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT
108 
#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
 108 
#endif /* STM32H7 */
109 
 
 109 
 
110 
/**
 110 
#if defined(STM32U5)
111 
  * @}
 111 
#define ADC_SAMPLETIME_5CYCLE           ADC_SAMPLETIME_5CYCLES
112 
  */
 112 
#define ADC_SAMPLETIME_391CYCLES_5      ADC_SAMPLETIME_391CYCLES
113 
 
 113 
#define ADC4_SAMPLETIME_160CYCLES_5     ADC4_SAMPLETIME_814CYCLES_5
114 
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
 114 
#endif /* STM32U5 */
115 
  * @{
 115 
 
116 
  */
 116 
#if defined(STM32H5)
117 
#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
 117 
#define ADC_CHANNEL_VCORE               ADC_CHANNEL_VDDCORE
118 
#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
 118 
#endif /* STM32H5 */
119 
#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
 119 
/**
120 
#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
 120 
  * @}
121 
#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
 121 
  */
122 
#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
 122 
 
123 
#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
 123 
/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
124 
#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
 124 
  * @{
125 
#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
 125 
  */
126 
#if defined(STM32L0)
 126 
 
127 
#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
 127 
#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
128 
#endif
 128 
 
129 
#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
 129 
/**
130 
#if defined(STM32F373xC) || defined(STM32F378xx)
 130 
  * @}
131 
#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
 131 
  */
132 
#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
 132 
 
133 
#endif /* STM32F373xC || STM32F378xx */
 133 
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
134 
 
 134 
  * @{
135 
#if defined(STM32L0) || defined(STM32L4)
 135 
  */
136 
#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
 136 
#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE
137 
 
 137 
#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE
138 
#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
 138 
#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1
139 
#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
 139 
#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2
140 
#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
 140 
#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3
141 
#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
 141 
#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4
142 
#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
 142 
#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5
143 
#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
 143 
#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6
144 
 
 144 
#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7
145 
#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
 145 
#if defined(STM32L0)
146 
#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
 146 
#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM
147 
#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
 147 
                                                                       input 1 for COMP1, LPTIM input 2 for COMP2 */
148 
#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
 148 
#endif
149 
#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
 149 
#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR
150 
#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
 150 
#if defined(STM32F373xC) || defined(STM32F378xx)
151 
#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
 151 
#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1
152 
#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
 152 
#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR
153 
#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
 153 
#endif /* STM32F373xC || STM32F378xx */
154 
#if defined(STM32L0)
 154 
 
155 
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
 155 
#if defined(STM32L0) || defined(STM32L4)
156 
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
 156 
#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
157 
/* to the second dedicated IO (only for COMP2).                               */
 157 
 
158 
#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
 158 
#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1
159 
#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
 159 
#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2
160 
#else
 160 
#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3
161 
#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
 161 
#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4
162 
#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
 162 
#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5
163 
#endif
 163 
#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6
164 
#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
 164 
 
165 
#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
 165 
#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT
166 
 
 166 
#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT
167 
#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
 167 
#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT
168 
#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
 168 
#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT
169 
 
 169 
#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1
170 
/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
 170 
#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2
171 
/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
 171 
#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1
172 
#if defined(COMP_CSR_LOCK)
 172 
#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2
173 
#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
 173 
#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1
174 
#elif defined(COMP_CSR_COMP1LOCK)
 174 
#if defined(STM32L0)
175 
#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
 175 
/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */
176 
#elif defined(COMP_CSR_COMPxLOCK)
 176 
/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */
177 
#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
 177 
/* to the second dedicated IO (only for COMP2).                               */
178 
#endif
 178 
#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2
179 
 
 179 
#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2
180 
#if defined(STM32L4)
 180 
#else
181 
#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
 181 
#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2
182 
#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
 182 
#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3
183 
#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
 183 
#endif
184 
#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
 184 
#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4
185 
#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
 185 
#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5
186 
#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
 186 
 
187 
#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
 187 
#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW
188 
#endif
 188 
#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH
189 
 
 189 
 
190 
#if defined(STM32L0)
 190 
/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */
191 
#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
 191 
/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */
192 
#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
 192 
#if defined(COMP_CSR_LOCK)
193 
#else
 193 
#define COMP_FLAG_LOCK                 COMP_CSR_LOCK
194 
#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
 194 
#elif defined(COMP_CSR_COMP1LOCK)
195 
#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
 195 
#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK
196 
#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
 196 
#elif defined(COMP_CSR_COMPxLOCK)
197 
#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
 197 
#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK
198 
#endif
 198 
#endif
199 
 
 199 
 
200 
#endif
 200 
#if defined(STM32L4)
201 
/**
 201 
#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1
202 
  * @}
 202 
#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1
203 
  */
 203 
#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1
204 
 
 204 
#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2
205 
/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
 205 
#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2
206 
  * @{
 206 
#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2
207 
  */
 207 
#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE
208 
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
 208 
#endif
209 
/**
 209 
 
210 
  * @}
 210 
#if defined(STM32L0)
211 
  */
 211 
#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED
212 
 
 212 
#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER
213 
/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
 213 
#else
214 
  * @{
 214 
#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED
215 
  */
 215 
#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED
216 
 
 216 
#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER
217 
#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
 217 
#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER
218 
#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
 218 
#endif
219 
 
 219 
 
220 
/**
 220 
#endif
221 
  * @}
 221 
 
222 
  */
 222 
#if defined(STM32U5)
223 
 
 223 
#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG
224 
/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
 224 
#endif
225 
  * @{
 225 
 
226 
  */
 226 
/**
227 
 
 227 
  * @}
228 
#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
 228 
  */
229 
#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
 229 
 
230 
#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
 230 
/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose
231 
#define DAC_WAVE_NONE                                   0x00000000U
 231 
  * @{
232 
#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
 232 
  */
233 
#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
 233 
#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig
234 
#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
 234 
#if defined(STM32U5)
235 
#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
 235 
#define  MPU_DEVICE_nGnRnE          MPU_DEVICE_NGNRNE
236 
#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
 236 
#define  MPU_DEVICE_nGnRE           MPU_DEVICE_NGNRE
237 
 
 237 
#define  MPU_DEVICE_nGRE            MPU_DEVICE_NGRE
238 
#if defined(STM32G4) || defined(STM32H7)
 238 
#endif /* STM32U5 */
239 
#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
 239 
/**
240 
#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
 240 
  * @}
241 
#endif
 241 
  */
242 
 
 242 
 
243 
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
 243 
/** @defgroup CRC_Aliases CRC API aliases
244 
#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
 244 
  * @{
245 
#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
 245 
  */
246 
#endif
 246 
#if defined(STM32H5) || defined(STM32C0)
247 
 
 247 
#else
248 
/**
 248 
#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
249 
  * @}
 249 
                                                                          inter STM32 series compatibility  */
250 
  */
 250 
#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
251 
 
 251 
                                                                          inter STM32 series compatibility */
252 
/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
 252 
#endif
253 
  * @{
 253 
/**
254 
  */
 254 
  * @}
255 
#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
 255 
  */
256 
#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
 256 
 
257 
#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
 257 
/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
258 
#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
 258 
  * @{
259 
#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
 259 
  */
260 
#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
 260 
 
261 
#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
 261 
#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE
262 
#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
 262 
#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE
263 
#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
 263 
 
264 
#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
 264 
/**
265 
#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
 265 
  * @}
266 
#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
 266 
  */
267 
#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
 267 
 
268 
#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
 268 
/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose
269 
 
 269 
  * @{
270 
#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
 270 
  */
271 
#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
 271 
 
272 
#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
 272 
#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1
273 
 
 273 
#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2
274 
#if defined(STM32L4)
 274 
#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1
275 
 
 275 
#define DAC_WAVE_NONE                                   0x00000000U
276 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
 276 
#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0
277 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
 277 
#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1
278 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
 278 
#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE
279 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
 279 
#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE
280 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
 280 
#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE
281 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
 281 
 
282 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
 282 
#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
283 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
 283 
#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL
284 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
 284 
#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL
285 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
 285 
#endif
286 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
 286 
 
287 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
 287 
#if defined(STM32U5)
288 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
 288 
#define DAC_TRIGGER_STOP_LPTIM1_OUT  DAC_TRIGGER_STOP_LPTIM1_CH1
289 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
 289 
#define DAC_TRIGGER_STOP_LPTIM3_OUT  DAC_TRIGGER_STOP_LPTIM3_CH1
290 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
 290 
#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
291 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
 291 
#define DAC_TRIGGER_LPTIM3_OUT       DAC_TRIGGER_LPTIM3_CH1
292 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
 292 
#endif
293 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
 293 
 
294 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
 294 
#if defined(STM32H5)
295 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
 295 
#define DAC_TRIGGER_LPTIM1_OUT       DAC_TRIGGER_LPTIM1_CH1
296 
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
 296 
#define DAC_TRIGGER_LPTIM2_OUT       DAC_TRIGGER_LPTIM2_CH1
297 
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
 297 
#endif
298 
#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
 298 
 
299 
#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
 299 
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
300 
#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
 300 
    defined(STM32F4) || defined(STM32G4)
301 
#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
 301 
#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID
302 
 
 302 
#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID
303 
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
 303 
#endif
304 
#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
 304 
 
305 
#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
 305 
/**
306 
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
 306 
  * @}
307 
 
 307 
  */
308 
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
 308 
 
309 
#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
 309 
/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
310 
#endif
 310 
  * @{
311 
 
 311 
  */
312 
#endif /* STM32L4 */
 312 
#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2
313 
 
 313 
#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4
314 
#if defined(STM32G0)
 314 
#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5
315 
#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
 315 
#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4
316 
#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
 316 
#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2
317 
#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
 317 
#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32
318 
#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
 318 
#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6
319 
 
 319 
#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7
320 
#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
 320 
#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67
321 
#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
 321 
#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67
322 
#endif
 322 
#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76
323 
 
 323 
#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6
324 
#if defined(STM32H7)
 324 
#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7
325 
 
 325 
#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6
326 
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
 326 
 
327 
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
 327 
#define IS_HAL_REMAPDMA                          IS_DMA_REMAP
328 
 
 328 
#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE
329 
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
 329 
#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE
330 
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
 330 
 
331 
 
 331 
#if defined(STM32L4)
332 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
 332 
 
333 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
 333 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0
334 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
 334 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1
335 
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
 335 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2
336 
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
 336 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3
337 
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
 337 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4
338 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
 338 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5
339 
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
 339 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6
340 
 
 340 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7
341 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
 341 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8
342 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
 342 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9
343 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
 343 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10
344 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
 344 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11
345 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
 345 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12
346 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
 346 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13
347 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
 347 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14
348 
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
 348 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15
349 
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
 349 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
350 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
 350 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
351 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
 351 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
352 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
 352 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT
353 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
 353 
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
354 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
 354 
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
355 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
 355 
#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE
356 
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
 356 
#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT
357 
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
 357 
#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT
358 
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
 358 
#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT
359 
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
 359 
 
360 
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
 360 
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT
361 
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
 361 
#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING
362 
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
 362 
#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING
363 
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
 363 
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING
364 
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
 364 
 
365 
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
 365 
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
366 
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
 366 
    defined(STM32L4S7xx) || defined(STM32L4S9xx)
367 
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
 367 
#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI
368 
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
 368 
#endif
369 
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
 369 
 
370 
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
 370 
#endif /* STM32L4 */
371 
 
 371 
 
372 
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
 372 
#if defined(STM32G0)
373 
#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
 373 
#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1
374 
#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
 374 
#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2
375 
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
 375 
#define DMA_REQUEST_TIM16_TRIG_COM               DMA_REQUEST_TIM16_COM
376 
 
 376 
#define DMA_REQUEST_TIM17_TRIG_COM               DMA_REQUEST_TIM17_COM
377 
#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
 377 
 
378 
#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
 378 
#define LL_DMAMUX_REQ_TIM16_TRIG_COM             LL_DMAMUX_REQ_TIM16_COM
379 
#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
 379 
#define LL_DMAMUX_REQ_TIM17_TRIG_COM             LL_DMAMUX_REQ_TIM17_COM
380 
 
 380 
#endif
381 
#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
 381 
 
382 
#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
 382 
#if defined(STM32H7)
383 
 
 383 
 
384 
#endif /* STM32H7 */
 384 
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
385 
 
 385 
#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
386 
/**
 386 
 
387 
  * @}
 387 
#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
388 
  */
 388 
#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
389 
 
 389 
 
390 
/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
 390 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
391 
  * @{
 391 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
392 
  */
 392 
#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
393 
 
 393 
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
394 
#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
 394 
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
395 
#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
 395 
#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
396 
#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
 396 
#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0
397 
#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
 397 
#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
398 
#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
 398 
 
399 
#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
 399 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
400 
#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
 400 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
401 
#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
 401 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
402 
#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
 402 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
403 
#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
 403 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
404 
#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
 404 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
405 
#define OBEX_PCROP                    OPTIONBYTE_PCROP
 405 
#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
406 
#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
 406 
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
407 
#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
 407 
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
408 
#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
 408 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
409 
#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
 409 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
410 
#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
 410 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
411 
#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
 411 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
412 
#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
 412 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
413 
#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
 413 
#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
414 
#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
 414 
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
415 
#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
 415 
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
416 
#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
 416 
#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT
417 
#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
 417 
#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT
418 
#define PAGESIZE                      FLASH_PAGE_SIZE
 418 
#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP
419 
#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
 419 
#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0
420 
#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
 420 
#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2
421 
#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
 421 
#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
422 
#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
 422 
#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT
423 
#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
 423 
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
424 
#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
 424 
#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
425 
#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
 425 
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT
426 
#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
 426 
#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
427 
#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
 427 
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
428 
#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
 428 
#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
429 
#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
 429 
 
430 
#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
 430 
#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT
431 
#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
 431 
#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING
432 
#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
 432 
#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING
433 
#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
 433 
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING
434 
#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
 434 
 
435 
#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
 435 
#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT
436 
#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
 436 
#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
437 
#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
 437 
#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
438 
#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
 438 
 
439 
#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
 439 
#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT
440 
#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
 440 
#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT
441 
#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
 441 
 
442 
#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
 442 
#endif /* STM32H7 */
443 
#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
 443 
 
444 
#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
 444 
#if defined(STM32U5)
445 
#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
 445 
#define GPDMA1_REQUEST_DCMI                        GPDMA1_REQUEST_DCMI_PSSI
446 
#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
 446 
#endif /* STM32U5 */
447 
#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
 447 
/**
448 
#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
 448 
  * @}
449 
#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
 449 
  */
450 
#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
 450 
 
451 
#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
 451 
/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
452 
#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
 452 
  * @{
453 
#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
 453 
  */
454 
#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
 454 
 
455 
#define OB_WDG_SW                     OB_IWDG_SW
 455 
#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE
456 
#define OB_WDG_HW                     OB_IWDG_HW
 456 
#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD
457 
#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
 457 
#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD
458 
#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
 458 
#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD
459 
#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
 459 
#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS
460 
#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
 460 
#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES
461 
#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
 461 
#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES
462 
#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
 462 
#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE
463 
#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
 463 
#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE
464 
#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
 464 
#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE
465 
#if defined(STM32G0)
 465 
#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE
466 
#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
 466 
#define OBEX_PCROP                    OPTIONBYTE_PCROP
467 
#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
 467 
#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG
468 
#else
 468 
#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE
469 
#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
 469 
#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE
470 
#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
 470 
#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE
471 
#endif
 471 
#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD
472 
#if defined(STM32H7)
 472 
#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD
473 
#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1
 473 
#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE
474 
#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1
 474 
#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD
475 
#define FLASH_FLAG_STRBER_BANK1R  FLASH_FLAG_STRBERR_BANK1
 475 
#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD
476 
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
 476 
#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE
477 
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
 477 
#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD
478 
#define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2
 478 
#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD
479 
#define FLASH_FLAG_WDW            FLASH_FLAG_WBNE
 479 
#define PAGESIZE                      FLASH_PAGE_SIZE
480 
#define OB_WRP_SECTOR_All         OB_WRP_SECTOR_ALL
 480 
#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE
481 
#endif /* STM32H7 */
 481 
#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD
482 
 
 482 
#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD
483 
/**
 483 
#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1
484 
  * @}
 484 
#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2
485 
  */
 485 
#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3
486 
 
 486 
#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4
487 
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
 487 
#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST
488 
  * @{
 488 
#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST
489 
  */
 489 
#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA
490 
 
 490 
#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB
491 
#if defined(STM32H7)
 491 
#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA
492 
#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
 492 
#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB
493 
#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
 493 
#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE
494 
#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
 494 
#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN
495 
#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
 495 
#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE
496 
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
 496 
#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN
497 
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
 497 
#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE
498 
#endif /* STM32H7 */
 498 
#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD
499 
 
 499 
#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG
500 
/**
 500 
#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS
501 
  * @}
 501 
#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP
502 
  */
 502 
#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV
503 
 
 503 
#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR
504 
/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
 504 
#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG
505 
  * @{
 505 
#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION
506 
  */
 506 
#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA
507 
 
 507 
#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE
508 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
 508 
#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE
509 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
 509 
#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS
510 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
 510 
#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS
511 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
 511 
#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST
512 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
 512 
#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR
513 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
 513 
#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO
514 
#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
 514 
#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION
515 
#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
 515 
#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS
516 
#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
 516 
#define OB_WDG_SW                     OB_IWDG_SW
517 
#if defined(STM32G4)
 517 
#define OB_WDG_HW                     OB_IWDG_HW
518 
 
 518 
#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET
519 
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
 519 
#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET
520 
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
 520 
#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET
521 
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
 521 
#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET
522 
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
 522 
#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR
523 
#endif /* STM32G4 */
 523 
#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0
524 
/**
 524 
#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1
525 
  * @}
 525 
#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2
526 
  */
 526 
#if defined(STM32G0) || defined(STM32C0)
527 
 
 527 
#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE
528 
 
 528 
#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH
529 
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
 529 
#else
530 
  * @{
 530 
#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE
531 
  */
 531 
#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE
532 
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
 532 
#endif
533 
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
 533 
#if defined(STM32H7)
534 
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
 534 
#define FLASH_FLAG_SNECCE_BANK1RR     FLASH_FLAG_SNECCERR_BANK1
535 
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
 535 
#define FLASH_FLAG_DBECCE_BANK1RR     FLASH_FLAG_DBECCERR_BANK1
536 
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
 536 
#define FLASH_FLAG_STRBER_BANK1R      FLASH_FLAG_STRBERR_BANK1
537 
#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
 537 
#define FLASH_FLAG_SNECCE_BANK2RR     FLASH_FLAG_SNECCERR_BANK2
538 
#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
 538 
#define FLASH_FLAG_DBECCE_BANK2RR     FLASH_FLAG_DBECCERR_BANK2
539 
#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
 539 
#define FLASH_FLAG_STRBER_BANK2R      FLASH_FLAG_STRBERR_BANK2
540 
#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
 540 
#define FLASH_FLAG_WDW                FLASH_FLAG_WBNE
541 
#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
 541 
#define OB_WRP_SECTOR_All             OB_WRP_SECTOR_ALL
542 
#endif
 542 
#endif /* STM32H7 */
543 
/**
 543 
#if defined(STM32U5)
544 
  * @}
 544 
#define OB_USER_nRST_STOP             OB_USER_NRST_STOP
545 
  */
 545 
#define OB_USER_nRST_STDBY            OB_USER_NRST_STDBY
546 
 
 546 
#define OB_USER_nRST_SHDW             OB_USER_NRST_SHDW
547 
/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
 547 
#define OB_USER_nSWBOOT0              OB_USER_NSWBOOT0
548 
  * @{
 548 
#define OB_USER_nBOOT0                OB_USER_NBOOT0
549 
  */
 549 
#define OB_nBOOT0_RESET               OB_NBOOT0_RESET
550 
 
 550 
#define OB_nBOOT0_SET                 OB_NBOOT0_SET
551 
#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
 551 
#define OB_USER_SRAM134_RST           OB_USER_SRAM_RST
552 
#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
 552 
#define OB_SRAM134_RST_ERASE          OB_SRAM_RST_ERASE
553 
/**
 553 
#define OB_SRAM134_RST_NOT_ERASE      OB_SRAM_RST_NOT_ERASE
554 
  * @}
 554 
#endif /* STM32U5 */
555 
  */
 555 
 
556 
 
 556 
/**
557 
/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
 557 
  * @}
558 
  * @{
 558 
  */
559 
  */
 559 
 
560 
#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
 560 
/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
561 
#define GET_GPIO_INDEX                            GPIO_GET_INDEX
 561 
  * @{
562 
 
 562 
  */
563 
#if defined(STM32F4)
 563 
 
564 
#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
 564 
#if defined(STM32H7)
565 
#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
 565 
#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE
566 
#endif
 566 
#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE
567 
 
 567 
#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET
568 
#if defined(STM32F7)
 568 
#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET
569 
#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
 569 
#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
570 
#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
 570 
#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
571 
#endif
 571 
#endif /* STM32H7 */
572 
 
 572 
 
573 
#if defined(STM32L4)
 573 
/**
574 
#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
 574 
  * @}
575 
#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
 575 
  */
576 
#endif
 576 
 
577 
 
 577 
/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
578 
#if defined(STM32H7)
 578 
  * @{
579 
#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
 579 
  */
580 
#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
 580 
 
581 
#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
 581 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9
582 
#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
 582 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10
583 
#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
 583 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6
584 
#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
 584 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7
585 
 
 585 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8
586 
#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
 586 
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9
587 
    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
 587 
#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1
588 
#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
 588 
#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2
589 
#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
 589 
#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3
590 
#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
 590 
#if defined(STM32G4)
591 
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
 591 
 
592 
#endif /* STM32H7 */
 592 
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster
593 
 
 593 
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster
594 
#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
 594 
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD
595 
#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
 595 
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD
596 
#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
 596 
#endif /* STM32G4 */
597 
 
 597 
 
598 
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
 598 
#if defined(STM32H5)
599 
#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
 599 
#define SYSCFG_IT_FPU_IOC         SBS_IT_FPU_IOC
600 
#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
 600 
#define SYSCFG_IT_FPU_DZC         SBS_IT_FPU_DZC
601 
#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
 601 
#define SYSCFG_IT_FPU_UFC         SBS_IT_FPU_UFC
602 
#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
 602 
#define SYSCFG_IT_FPU_OFC         SBS_IT_FPU_OFC
603 
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
 603 
#define SYSCFG_IT_FPU_IDC         SBS_IT_FPU_IDC
604 
 
 604 
#define SYSCFG_IT_FPU_IXC         SBS_IT_FPU_IXC
605 
#if defined(STM32L1)
 605 
 
606 
 #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
 606 
#define SYSCFG_BREAK_FLASH_ECC    SBS_BREAK_FLASH_ECC
607 
 #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
 607 
#define SYSCFG_BREAK_PVD          SBS_BREAK_PVD
608 
 #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
 608 
#define SYSCFG_BREAK_SRAM_ECC     SBS_BREAK_SRAM_ECC
609 
 #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
 609 
#define SYSCFG_BREAK_LOCKUP       SBS_BREAK_LOCKUP
610 
#endif /* STM32L1 */
 610 
 
611 
 
 611 
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_VOLTAGE_SCALE0
612 
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
 612 
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_VOLTAGE_SCALE1
613 
 #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
 613 
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_VOLTAGE_SCALE2
614 
 #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
 614 
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_VOLTAGE_SCALE3
615 
 #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
 615 
 
616 
#endif /* STM32F0 || STM32F3 || STM32F1 */
 616 
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE   VREFBUF_HIGH_IMPEDANCE_DISABLE
617 
 
 617 
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE    VREFBUF_HIGH_IMPEDANCE_ENABLE
618 
#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
 618 
 
619 
/**
 619 
#define SYSCFG_FASTMODEPLUS_PB6   SBS_FASTMODEPLUS_PB6
620 
  * @}
 620 
#define SYSCFG_FASTMODEPLUS_PB7   SBS_FASTMODEPLUS_PB7
621 
  */
 621 
#define SYSCFG_FASTMODEPLUS_PB8   SBS_FASTMODEPLUS_PB8
622 
 
 622 
#define SYSCFG_FASTMODEPLUS_PB9   SBS_FASTMODEPLUS_PB9
623 
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
 623 
 
624 
  * @{
 624 
#define SYSCFG_ETH_MII   SBS_ETH_MII
625 
  */
 625 
#define SYSCFG_ETH_RMII  SBS_ETH_RMII
626 
#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
 626 
#define IS_SYSCFG_ETHERNET_CONFIG  IS_SBS_ETHERNET_CONFIG
627 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
 627 
 
628 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
 628 
#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE   SBS_MEMORIES_ERASE_FLAG_IPMEE
629 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
 629 
#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR    SBS_MEMORIES_ERASE_FLAG_MCLR
630 
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
 630 
#define IS_SYSCFG_MEMORIES_ERASE_FLAG      IS_SBS_MEMORIES_ERASE_FLAG
631 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
 631 
 
632 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
 632 
#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
633 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
 633 
 
634 
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
 634 
#define SYSCFG_MPU_NSEC   SBS_MPU_NSEC
635 
 
 635 
#define SYSCFG_VTOR_NSEC  SBS_VTOR_NSEC
636 
#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
 636 
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
637 
#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
 637 
#define SYSCFG_SAU              SBS_SAU
638 
#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
 638 
#define SYSCFG_MPU_SEC          SBS_MPU_SEC
639 
#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
 639 
#define SYSCFG_VTOR_AIRCR_SEC   SBS_VTOR_AIRCR_SEC
640 
#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
 640 
#define SYSCFG_LOCK_ALL         SBS_LOCK_ALL
641 
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
 641 
#else
642 
#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
 642 
#define SYSCFG_LOCK_ALL         SBS_LOCK_ALL
643 
#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
 643 
#endif /* __ARM_FEATURE_CMSE */
644 
 
 644 
 
645 
#if defined(STM32G4)
 645 
#define SYSCFG_CLK      SBS_CLK
646 
#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
 646 
#define SYSCFG_CLASSB   SBS_CLASSB
647 
#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
 647 
#define SYSCFG_FPU      SBS_FPU
648 
#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
 648 
#define SYSCFG_ALL      SBS_ALL
649 
#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
 649 
 
650 
#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
 650 
#define SYSCFG_SEC      SBS_SEC
651 
#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
 651 
#define SYSCFG_NSEC     SBS_NSEC
652 
#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
 652 
 
653 
#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
 653 
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE   __HAL_SBS_FPU_INTERRUPT_ENABLE
654 
#endif /* STM32G4 */
 654 
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE  __HAL_SBS_FPU_INTERRUPT_DISABLE
655 
 
 655 
 
656 
#if defined(STM32H7)
 656 
#define __HAL_SYSCFG_BREAK_ECC_LOCK        __HAL_SBS_BREAK_ECC_LOCK
657 
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
 657 
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK     __HAL_SBS_BREAK_LOCKUP_LOCK
658 
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
 658 
#define __HAL_SYSCFG_BREAK_PVD_LOCK        __HAL_SBS_BREAK_PVD_LOCK
659 
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
 659 
#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK   __HAL_SBS_BREAK_SRAM_ECC_LOCK
660 
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
 660 
 
661 
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
 661 
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE   __HAL_SBS_FASTMODEPLUS_ENABLE
662 
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
 662 
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE  __HAL_SBS_FASTMODEPLUS_DISABLE
663 
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
 663 
 
664 
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
 664 
#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS    __HAL_SBS_GET_MEMORIES_ERASE_STATUS
665 
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
 665 
#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS  __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
666 
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
 666 
 
667 
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
 667 
#define IS_SYSCFG_FPU_INTERRUPT    IS_SBS_FPU_INTERRUPT
668 
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
 668 
#define IS_SYSCFG_BREAK_CONFIG     IS_SBS_BREAK_CONFIG
669 
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
 669 
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE     IS_VREFBUF_VOLTAGE_SCALE
670 
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
 670 
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE    IS_VREFBUF_HIGH_IMPEDANCE
671 
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
 671 
#define IS_SYSCFG_VREFBUF_TRIMMING  IS_VREFBUF_TRIMMING
672 
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
 672 
#define IS_SYSCFG_FASTMODEPLUS      IS_SBS_FASTMODEPLUS
673 
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
 673 
#define IS_SYSCFG_ITEMS_ATTRIBUTES  IS_SBS_ITEMS_ATTRIBUTES
674 
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
 674 
#define IS_SYSCFG_ATTRIBUTES        IS_SBS_ATTRIBUTES
675 
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
 675 
#define IS_SYSCFG_LOCK_ITEMS        IS_SBS_LOCK_ITEMS
676 
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
 676 
 
677 
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
 677 
#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig   HAL_VREFBUF_VoltageScalingConfig
678 
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
 678 
#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig    HAL_VREFBUF_HighImpedanceConfig
679 
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
 679 
#define HAL_SYSCFG_VREFBUF_TrimmingConfig         HAL_VREFBUF_TrimmingConfig
680 
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
 680 
#define HAL_SYSCFG_EnableVREFBUF                  HAL_EnableVREFBUF
681 
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
 681 
#define HAL_SYSCFG_DisableVREFBUF                 HAL_DisableVREFBUF
682 
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
 682 
 
683 
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
 683 
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SBS_EnableIOAnalogSwitchBooster
684 
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
 684 
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SBS_DisableIOAnalogSwitchBooster
685 
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
 685 
#define HAL_SYSCFG_ETHInterfaceSelect             HAL_SBS_ETHInterfaceSelect
686 
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
 686 
 
687 
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
 687 
#define HAL_SYSCFG_Lock     HAL_SBS_Lock
688 
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
 688 
#define HAL_SYSCFG_GetLock  HAL_SBS_GetLock
689 
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
 689 
 
690 
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
 690 
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
691 
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
 691 
#define HAL_SYSCFG_ConfigAttributes     HAL_SBS_ConfigAttributes
692 
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
 692 
#define HAL_SYSCFG_GetConfigAttributes  HAL_SBS_GetConfigAttributes
693 
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
 693 
#endif /* __ARM_FEATURE_CMSE */
694 
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
 694 
 
695 
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
 695 
#endif /* STM32H5 */
696 
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
 696 
 
697 
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
 697 
 
698 
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
 698 
/**
699 
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
 699 
  * @}
700 
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
 700 
  */
701 
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
 701 
 
702 
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
 702 
 
703 
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
 703 
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
704 
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
 704 
  * @{
705 
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
 705 
  */
706 
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
 706 
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
707 
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
 707 
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
708 
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
 708 
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
709 
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
 709 
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
710 
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
 710 
#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16
711 
 
 711 
#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)
712 
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
 712 
#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE
713 
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
 713 
#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE
714 
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
 714 
#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8
715 
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
 715 
#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16
716 
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
 716 
#endif
717 
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
 717 
/**
718 
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
 718 
  * @}
719 
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
 719 
  */
720 
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
 720 
 
721 
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
 721 
/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
722 
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
 722 
  * @{
723 
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
 723 
  */
724 
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
 724 
 
725 
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
 725 
#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef
726 
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
 726 
#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef
727 
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
 727 
/**
728 
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
 728 
  * @}
729 
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
 729 
  */
730 
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
 730 
 
731 
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
 731 
/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose
732 
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
 732 
  * @{
733 
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
 733 
  */
734 
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
 734 
#define GET_GPIO_SOURCE                           GPIO_GET_INDEX
735 
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
 735 
#define GET_GPIO_INDEX                            GPIO_GET_INDEX
736 
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
 736 
 
737 
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
 737 
#if defined(STM32F4)
738 
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
 738 
#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO
739 
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
 739 
#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO
740 
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
 740 
#endif
741 
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
 741 
 
742 
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
 742 
#if defined(STM32F7)
743 
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
 743 
#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
744 
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
 744 
#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
745 
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
 745 
#endif
746 
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
 746 
 
747 
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
 747 
#if defined(STM32L4)
748 
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
 748 
#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1
749 
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
 749 
#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1
750 
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
 750 
#endif
751 
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
 751 
 
752 
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
 752 
#if defined(STM32H7)
753 
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
 753 
#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1
754 
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
 754 
#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1
755 
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
 755 
#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1
756 
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
 756 
#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2
757 
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
 757 
#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2
758 
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
 758 
#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2
759 
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
 759 
 
760 
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
 760 
#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \
761 
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
 761 
    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)
762 
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
 762 
#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS
763 
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
 763 
#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS
764 
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
 764 
#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS
765 
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
 765 
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
766 
#endif /* STM32H7 */
 766 
         STM32H757xx */
767 
 
 767 
#endif /* STM32H7 */
768 
#if defined(STM32F3)
 768 
 
769 
/** @brief Constants defining available sources associated to external events.
 769 
#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1
770 
  */
 770 
#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1
771 
#define HRTIM_EVENTSRC_1              (0x00000000U)
 771 
#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1
772 
#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
 772 
 
773 
#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
 773 
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
774 
#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
 774 
    defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
775 
 
 775 
#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW
776 
/** @brief Constants defining the events that can be selected to configure the
 776 
#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM
777 
  *        set/reset crossbar of a timer output
 777 
#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH
778 
  */
 778 
#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH
779 
#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)
 779 
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/
780 
#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)
 780 
 
781 
#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)
 781 
#if defined(STM32L1)
782 
#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)
 782 
#define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW
783 
#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)
 783 
#define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM
784 
#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)
 784 
#define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH
785 
#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)
 785 
#define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH
786 
#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)
 786 
#endif /* STM32L1 */
787 
#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)
 787 
 
788 
 
 788 
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
789 
#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)
 789 
#define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW
790 
#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)
 790 
#define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
791 
#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)
 791 
#define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH
792 
#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)
 792 
#endif /* STM32F0 || STM32F3 || STM32F1 */
793 
#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)
 793 
 
794 
#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)
 794 
#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1
795 
#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)
 795 
 
796 
#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)
 796 
#if defined(STM32U5) || defined(STM32H5)
797 
#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)
 797 
#define GPIO_AF0_RTC_50Hz                         GPIO_AF0_RTC_50HZ
798 
 
 798 
#endif /* STM32U5 || STM32H5 */
799 
/** @brief Constants defining the event filtering applied to external events
 799 
#if defined(STM32U5)
800 
  *        by a timer
 800 
#define GPIO_AF0_S2DSTOP                          GPIO_AF0_SRDSTOP
801 
  */
 801 
#define GPIO_AF11_LPGPIO                          GPIO_AF11_LPGPIO1
802 
#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)
 802 
#endif /* STM32U5 */
803 
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)
 803 
/**
804 
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)
 804 
  * @}
805 
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
 805 
  */
806 
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)
 806 
 
807 
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
 807 
/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose
808 
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
 808 
  * @{
809 
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
 809 
  */
810 
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)
 810 
#if defined(STM32U5)
811 
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
 811 
#define GTZC_PERIPH_DCMI                      GTZC_PERIPH_DCMI_PSSI
812 
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
 812 
#define GTZC_PERIPH_LTDC                      GTZC_PERIPH_LTDCUSB
813 
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
 813 
#endif /* STM32U5 */
814 
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
 814 
#if defined(STM32H5)
815 
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
 815 
#define GTZC_PERIPH_DAC12                     GTZC_PERIPH_DAC1
816 
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
 816 
#define GTZC_PERIPH_ADC12                     GTZC_PERIPH_ADC
817 
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
 817 
#define GTZC_PERIPH_USBFS                     GTZC_PERIPH_USB
818 
 
 818 
#endif /* STM32H5 */
819 
/** @brief Constants defining the DLL calibration periods (in micro seconds)
 819 
#if defined(STM32H5) || defined(STM32U5)
820 
  */
 820 
#define GTZC_MCPBB_NB_VCTR_REG_MAX            GTZC_MPCBB_NB_VCTR_REG_MAX
821 
#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
 821 
#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX        GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
822 
#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
 822 
#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED        GTZC_MPCBB_SUPERBLOCK_UNLOCKED
823 
#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
 823 
#define GTZC_MCPBB_SUPERBLOCK_LOCKED          GTZC_MPCBB_SUPERBLOCK_LOCKED
824 
#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
 824 
#define GTZC_MCPBB_BLOCK_NSEC                 GTZC_MPCBB_BLOCK_NSEC
825 
 
 825 
#define GTZC_MCPBB_BLOCK_SEC                  GTZC_MPCBB_BLOCK_SEC
826 
#endif /* STM32F3 */
 826 
#define GTZC_MCPBB_BLOCK_NPRIV                GTZC_MPCBB_BLOCK_NPRIV
827 
/**
 827 
#define GTZC_MCPBB_BLOCK_PRIV                 GTZC_MPCBB_BLOCK_PRIV
828 
  * @}
 828 
#define GTZC_MCPBB_LOCK_OFF                   GTZC_MPCBB_LOCK_OFF
829 
  */
 829 
#define GTZC_MCPBB_LOCK_ON                    GTZC_MPCBB_LOCK_ON
830 
 
 830 
#endif /* STM32H5 || STM32U5 */
831 
/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
 831 
/**
832 
  * @{
 832 
  * @}
833 
  */
 833 
  */
834 
#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
 834 
 
835 
#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
 835 
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
836 
#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
 836 
  * @{
837 
#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
 837 
  */
838 
#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
 838 
#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED
839 
#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
 839 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6
840 
#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
 840 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6
841 
#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
 841 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6
842 
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
 842 
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6
843 
#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
 843 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7
844 
#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
 844 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
845 
#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
 845 
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
846 
#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
 846 
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
847 
#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
 847 
 
848 
#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
 848 
#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER
849 
#endif
 849 
#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER
850 
/**
 850 
#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD
851 
  * @}
 851 
#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD
852 
  */
 852 
#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER
853 
 
 853 
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
854 
/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
 854 
#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE
855 
  * @{
 855 
#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE
856 
  */
 856 
 
857 
#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
 857 
#if defined(STM32G4)
858 
#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
 858 
#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig
859 
 
 859 
#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable
860 
/**
 860 
#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable
861 
  * @}
 861 
#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset
862 
  */
 862 
#define HRTIM_TIMEEVENT_A                       HRTIM_EVENTCOUNTER_A
863 
 
 863 
#define HRTIM_TIMEEVENT_B                       HRTIM_EVENTCOUNTER_B
864 
/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
 864 
#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL  HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL
865 
  * @{
 865 
#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL    HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL
866 
  */
 866 
#endif /* STM32G4 */
867 
#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
 867 
 
868 
#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
 868 
#if defined(STM32H7)
869 
#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
 869 
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
870 
#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
 870 
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
871 
/**
 871 
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
872 
  * @}
 872 
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
873 
  */
 873 
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
874 
 
 874 
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
875 
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
 875 
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
876 
  * @{
 876 
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
877 
  */
 877 
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
878 
 
 878 
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
879 
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
 879 
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
880 
#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
 880 
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
881 
#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
 881 
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
882 
#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
 882 
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
883 
 
 883 
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
884 
#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
 884 
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
885 
#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
 885 
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
886 
#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
 886 
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
887 
 
 887 
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
888 
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
 888 
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
889 
#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
 889 
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
890 
#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
 890 
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
891 
#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
 891 
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
892 
 
 892 
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
893 
/* The following 3 definition have also been present in a temporary version of lptim.h */
 893 
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
894 
/* They need to be renamed also to the right name, just in case */
 894 
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
895 
#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
 895 
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
896 
#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
 896 
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
897 
#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
 897 
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
898 
 
 898 
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
899 
/**
 899 
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
900 
  * @}
 900 
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
901 
  */
 901 
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
902 
 
 902 
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
903 
/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
 903 
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
904 
  * @{
 904 
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
905 
  */
 905 
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
906 
#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
 906 
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
907 
#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
 907 
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
908 
#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
 908 
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
909 
#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
 909 
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
910 
 
 910 
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
911 
#define NAND_AddressTypedef             NAND_AddressTypeDef
 911 
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
912 
 
 912 
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
913 
#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
 913 
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
914 
#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
 914 
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
915 
#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
 915 
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
916 
#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
 916 
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
917 
#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
 917 
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
918 
/**
 918 
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
919 
  * @}
 919 
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
920 
  */
 920 
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
921 
 
 921 
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
922 
/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
 922 
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
923 
  * @{
 923 
 
924 
  */
 924 
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
925 
#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
 925 
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
926 
#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
 926 
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
927 
#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
 927 
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
928 
#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
 928 
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
929 
#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
 929 
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
930 
 
 930 
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
931 
#define __NOR_WRITE                    NOR_WRITE
 931 
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
932 
#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
 932 
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
933 
/**
 933 
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
934 
  * @}
 934 
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
935 
  */
 935 
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
936 
 
 936 
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
937 
/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
 937 
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
938 
  * @{
 938 
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
939 
  */
 939 
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
940 
 
 940 
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
941 
#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
 941 
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
942 
#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
 942 
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
943 
#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
 943 
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
944 
#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
 944 
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
945 
 
 945 
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
946 
#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
 946 
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
947 
#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
 947 
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
948 
#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
 948 
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
949 
#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
 949 
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
950 
 
 950 
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
951 
#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
 951 
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
952 
#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
 952 
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
953 
 
 953 
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
954 
#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
 954 
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
955 
#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
 955 
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
956 
 
 956 
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
957 
#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
 957 
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
958 
#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
 958 
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
959 
 
 959 
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
960 
#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
 960 
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
961 
 
 961 
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
962 
#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
 962 
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
963 
#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
 963 
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
964 
#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
 964 
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
965 
 
 965 
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
966 
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)
 966 
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
967 
#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
 967 
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
968 
#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
 968 
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
969 
#endif
 969 
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
970 
 
 970 
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
971 
 
 971 
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
972 
/**
 972 
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
973 
  * @}
 973 
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
974 
  */
 974 
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
975 
 
 975 
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
976 
/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
 976 
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
977 
  * @{
 977 
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
978 
  */
 978 
#endif /* STM32H7 */
979 
#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
 979 
 
980 
 
 980 
#if defined(STM32F3)
981 
#if defined(STM32H7)
 981 
/** @brief Constants defining available sources associated to external events.
982 
  #define I2S_IT_TXE               I2S_IT_TXP
 982 
  */
983 
  #define I2S_IT_RXNE              I2S_IT_RXP
 983 
#define HRTIM_EVENTSRC_1              (0x00000000U)
984 
 
 984 
#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)
985 
  #define I2S_FLAG_TXE             I2S_FLAG_TXP
 985 
#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)
986 
  #define I2S_FLAG_RXNE            I2S_FLAG_RXP
 986 
#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
987 
#endif
 987 
 
988 
 
 988 
/** @brief Constants defining the DLL calibration periods (in micro seconds)
989 
#if defined(STM32F7)
 989 
  */
990 
  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
 990 
#define HRTIM_CALIBRATIONRATE_7300             0x00000000U
991 
#endif
 991 
#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)
992 
/**
 992 
#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)
993 
  * @}
 993 
#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
994 
  */
 994 
 
995 
 
 995 
#endif /* STM32F3 */
996 
/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
 996 
/**
997 
  * @{
 997 
  * @}
998 
  */
 998 
  */
999 
 
 999 
 
1000 
/* Compact Flash-ATA registers description */
 1000 
/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose
1001 
#define CF_DATA                       ATA_DATA
 1001 
  * @{
1002 
#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
 1002 
  */
1003 
#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
 1003 
#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE
1004 
#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
 1004 
#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE
1005 
#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
 1005 
#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE
1006 
#define CF_CARD_HEAD                  ATA_CARD_HEAD
 1006 
#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE
1007 
#define CF_STATUS_CMD                 ATA_STATUS_CMD
 1007 
#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE
1008 
#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
 1008 
#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE
1009 
#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
 1009 
#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE
1010 
 
 1010 
#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE
1011 
/* Compact Flash-ATA commands */
 1011 
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
1012 
#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
 1012 
    defined(STM32L1) || defined(STM32F7)
1013 
#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
 1013 
#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX
1014 
#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
 1014 
#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX
1015 
#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
 1015 
#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX
1016 
 
 1016 
#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX
1017 
#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
 1017 
#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX
1018 
#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
 1018 
#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX
1019 
#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
 1019 
#endif
1020 
#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
 1020 
/**
1021 
#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
 1021 
  * @}
1022 
/**
 1022 
  */
1023 
  * @}
 1023 
 
1024 
  */
 1024 
/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose
1025 
 
 1025 
  * @{
1026 
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
 1026 
  */
1027 
  * @{
 1027 
#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE
1028 
  */
 1028 
#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE
1029 
 
 1029 
 
1030 
#define FORMAT_BIN                  RTC_FORMAT_BIN
 1030 
/**
1031 
#define FORMAT_BCD                  RTC_FORMAT_BCD
 1031 
  * @}
1032 
 
 1032 
  */
1033 
#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
 1033 
 
1034 
#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
 1034 
/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose
1035 
#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
 1035 
  * @{
1036 
#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
 1036 
  */
1037 
 
 1037 
#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD
1038 
#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
 1038 
#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE
1039 
#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
 1039 
#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE
1040 
#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
 1040 
#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE
1041 
#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
 1041 
/**
1042 
#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
 1042 
  * @}
1043 
 
 1043 
  */
1044 
#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
 1044 
 
1045 
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
 1045 
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
1046 
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
 1046 
  * @{
1047 
#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
 1047 
  */
1048 
 
 1048 
 
1049 
#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
 1049 
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION
1050 
#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
 1050 
#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS
1051 
#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
 1051 
#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS
1052 
 
 1052 
#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS
1053 
#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
 1053 
 
1054 
#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
 1054 
#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING
1055 
#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
 1055 
#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING
1056 
 
 1056 
#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING
1057 
#if defined(STM32H7)
 1057 
 
1058 
#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
 1058 
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
1059 
#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
 1059 
#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS
1060 
 
 1060 
#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS
1061 
#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
 1061 
#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS
1062 
#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
 1062 
 
1063 
#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
 1063 
/* The following 3 definition have also been present in a temporary version of lptim.h */
1064 
#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL
 1064 
/* They need to be renamed also to the right name, just in case */
1065 
#endif /* STM32H7 */
 1065 
#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS
1066 
 
 1066 
#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS
1067 
/**
 1067 
#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS
1068 
  * @}
 1068 
 
1069 
  */
 1069 
 
1070 
 
 1070 
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
1071 
 
 1071 
  * @{
1072 
/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
 1072 
  */
1073 
  * @{
 1073 
#define HAL_LPTIM_ReadCompare      HAL_LPTIM_ReadCapturedValue
1074 
  */
 1074 
/**
1075 
#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
 1075 
  * @}
1076 
#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
 1076 
  */
1077 
 
 1077 
 
1078 
#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
 1078 
#if defined(STM32U5)
1079 
#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
 1079 
#define LPTIM_ISR_CC1        LPTIM_ISR_CC1IF
1080 
#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
 1080 
#define LPTIM_ISR_CC2        LPTIM_ISR_CC2IF
1081 
#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
 1081 
#define LPTIM_CHANNEL_ALL    0x00000000U
1082 
 
 1082 
#endif /* STM32U5 */
1083 
#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
 1083 
/**
1084 
#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
 1084 
  * @}
1085 
 
 1085 
  */
1086 
#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
 1086 
 
1087 
#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
 1087 
/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
1088 
/**
 1088 
  * @{
1089 
  * @}
 1089 
  */
1090 
  */
 1090 
#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b
1091 
 
 1091 
#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b
1092 
 
 1092 
#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b
1093 
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
 1093 
#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b
1094 
  * @{
 1094 
 
1095 
  */
 1095 
#define NAND_AddressTypedef             NAND_AddressTypeDef
1096 
#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
 1096 
 
1097 
#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
 1097 
#define __ARRAY_ADDRESS                 ARRAY_ADDRESS
1098 
#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
 1098 
#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE
1099 
#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
 1099 
#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE
1100 
#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
 1100 
#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE
1101 
#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
 1101 
#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE
1102 
#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
 1102 
/**
1103 
#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
 1103 
  * @}
1104 
#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
 1104 
  */
1105 
#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
 1105 
 
1106 
#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
 1106 
/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
1107 
/**
 1107 
  * @{
1108 
  * @}
 1108 
  */
1109 
  */
 1109 
#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef
1110 
 
 1110 
#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS
1111 
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
 1111 
#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING
1112 
  * @{
 1112 
#define NOR_ERROR                      HAL_NOR_STATUS_ERROR
1113 
  */
 1113 
#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT
1114 
#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
 1114 
 
1115 
#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
 1115 
#define __NOR_WRITE                    NOR_WRITE
1116 
 
 1116 
#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT
1117 
#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
 1117 
/**
1118 
#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
 1118 
  * @}
1119 
 
 1119 
  */
1120 
#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
 1120 
 
1121 
#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
 1121 
/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose
1122 
 
 1122 
  * @{
1123 
#if defined(STM32H7)
 1123 
  */
1124 
 
 1124 
 
1125 
 #define SPI_FLAG_TXE                    SPI_FLAG_TXP
 1125 
#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0
1126 
 #define SPI_FLAG_RXNE                   SPI_FLAG_RXP
 1126 
#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1
1127 
 
 1127 
#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2
1128 
 #define SPI_IT_TXE                      SPI_IT_TXP
 1128 
#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3
1129 
 #define SPI_IT_RXNE                     SPI_IT_RXP
 1129 
 
1130 
 
 1130 
#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0
1131 
 #define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
 1131 
#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1
1132 
 #define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
 1132 
#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2
1133 
 #define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
 1133 
#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3
1134 
 #define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
 1134 
 
1135 
 
 1135 
#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0
1136 
#endif /* STM32H7 */
 1136 
#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1
1137 
 
 1137 
 
1138 
/**
 1138 
#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0
1139 
  * @}
 1139 
#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1
1140 
  */
 1140 
 
1141 
 
 1141 
#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0
1142 
/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
 1142 
#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1
1143 
  * @{
 1143 
 
1144 
  */
 1144 
#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1
1145 
#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
 1145 
 
1146 
#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
 1146 
#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
1147 
 
 1147 
#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
1148 
#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
 1148 
#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
1149 
#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
 1149 
 
1150 
#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
 1150 
#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5)
1151 
#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
 1151 
#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID
1152 
#define TIM_DMABase_SR                   TIM_DMABASE_SR
 1152 
#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID
1153 
#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
 1153 
#endif
1154 
#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
 1154 
 
1155 
#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
 1155 
#if defined(STM32L4) || defined(STM32L5)
1156 
#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
 1156 
#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALPOWER
1157 
#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
 1157 
#elif defined(STM32G4)
1158 
#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
 1158 
#define OPAMP_POWERMODE_NORMAL                OPAMP_POWERMODE_NORMALSPEED
1159 
#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
 1159 
#endif
1160 
#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
 1160 
 
1161 
#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
 1161 
/**
1162 
#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
 1162 
  * @}
1163 
#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
 1163 
  */
1164 
#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
 1164 
 
1165 
#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
 1165 
/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose
1166 
#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
 1166 
  * @{
1167 
#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
 1167 
  */
1168 
#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
 1168 
#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
1169 
#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
 1169 
 
1170 
#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
 1170 
#if defined(STM32H7)
1171 
#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
 1171 
#define I2S_IT_TXE               I2S_IT_TXP
1172 
#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
 1172 
#define I2S_IT_RXNE              I2S_IT_RXP
1173 
#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
 1173 
 
1174 
#define TIM_DMABase_OR                   TIM_DMABASE_OR
 1174 
#define I2S_FLAG_TXE             I2S_FLAG_TXP
1175 
 
 1175 
#define I2S_FLAG_RXNE            I2S_FLAG_RXP
1176 
#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
 1176 
#endif
1177 
#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
 1177 
 
1178 
#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
 1178 
#if defined(STM32F7)
1179 
#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
 1179 
#define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL
1180 
#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
 1180 
#endif
1181 
#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
 1181 
/**
1182 
#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
 1182 
  * @}
1183 
#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
 1183 
  */
1184 
#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
 1184 
 
1185 
 
 1185 
/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose
1186 
#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
 1186 
  * @{
1187 
#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
 1187 
  */
1188 
#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
 1188 
 
1189 
#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
 1189 
/* Compact Flash-ATA registers description */
1190 
#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
 1190 
#define CF_DATA                       ATA_DATA
1191 
#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
 1191 
#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT
1192 
#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
 1192 
#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER
1193 
#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
 1193 
#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW
1194 
#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
 1194 
#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH
1195 
#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
 1195 
#define CF_CARD_HEAD                  ATA_CARD_HEAD
1196 
#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
 1196 
#define CF_STATUS_CMD                 ATA_STATUS_CMD
1197 
#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
 1197 
#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE
1198 
#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
 1198 
#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA
1199 
#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
 1199 
 
1200 
#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
 1200 
/* Compact Flash-ATA commands */
1201 
#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
 1201 
#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD
1202 
#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
 1202 
#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD
1203 
#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
 1203 
#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD
1204 
 
 1204 
#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD
1205 
#if defined(STM32L0)
 1205 
 
1206 
#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
 1206 
#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef
1207 
#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
 1207 
#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS
1208 
#endif
 1208 
#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING
1209 
 
 1209 
#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR
1210 
#if defined(STM32F3)
 1210 
#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT
1211 
#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
 1211 
/**
1212 
#endif
 1212 
  * @}
1213 
 
 1213 
  */
1214 
#if defined(STM32H7)
 1214 
 
1215 
#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
 1215 
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
1216 
#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
 1216 
  * @{
1217 
#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
 1217 
  */
1218 
#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
 1218 
 
1219 
#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
 1219 
#define FORMAT_BIN                  RTC_FORMAT_BIN
1220 
#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
 1220 
#define FORMAT_BCD                  RTC_FORMAT_BCD
1221 
#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
 1221 
 
1222 
#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
 1222 
#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE
1223 
#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
 1223 
#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE
1224 
#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
 1224 
#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE
1225 
#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
 1225 
#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE
1226 
#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
 1226 
 
1227 
#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
 1227 
#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE
1228 
#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
 1228 
#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE
1229 
#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
 1229 
#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE
1230 
#endif
 1230 
#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT
1231 
 
 1231 
#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT
1232 
/**
 1232 
 
1233 
  * @}
 1233 
#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT
1234 
  */
 1234 
#define RTC_TIMESTAMPPIN_PA0   RTC_TIMESTAMPPIN_POS1
1235 
 
 1235 
#define RTC_TIMESTAMPPIN_PI8   RTC_TIMESTAMPPIN_POS1
1236 
/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
 1236 
#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2
1237 
  * @{
 1237 
 
1238 
  */
 1238 
#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE
1239 
#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
 1239 
#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1
1240 
#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
 1240 
#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1
1241 
/**
 1241 
 
1242 
  * @}
 1242 
#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
1243 
  */
 1243 
#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1
1244 
 
 1244 
#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1
1245 
/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
 1245 
 
1246 
  * @{
 1246 
#if defined(STM32H5)
1247 
  */
 1247 
#define TAMP_SECRETDEVICE_ERASE_NONE        TAMP_DEVICESECRETS_ERASE_NONE
1248 
#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
 1248 
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM    TAMP_DEVICESECRETS_ERASE_BKPSRAM
1249 
#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
 1249 
#endif /* STM32H5 */
1250 
#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
 1250 
 
1251 
#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
 1251 
#if defined(STM32WBA)
1252 
 
 1252 
#define TAMP_SECRETDEVICE_ERASE_NONE            TAMP_DEVICESECRETS_ERASE_NONE
1253 
#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
 1253 
#define TAMP_SECRETDEVICE_ERASE_SRAM2           TAMP_DEVICESECRETS_ERASE_SRAM2
1254 
#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
 1254 
#define TAMP_SECRETDEVICE_ERASE_RHUK            TAMP_DEVICESECRETS_ERASE_RHUK
1255 
 
 1255 
#define TAMP_SECRETDEVICE_ERASE_ICACHE          TAMP_DEVICESECRETS_ERASE_ICACHE
1256 
#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
 1256 
#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH   TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
1257 
#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
 1257 
#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM        TAMP_DEVICESECRETS_ERASE_PKA_SRAM
1258 
#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
 1258 
#define TAMP_SECRETDEVICE_ERASE_ALL             TAMP_DEVICESECRETS_ERASE_ALL
1259 
#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
 1259 
#endif /* STM32WBA */
1260 
 
 1260 
 
1261 
#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
 1261 
#if defined(STM32H5) || defined(STM32WBA)
1262 
#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
 1262 
#define TAMP_SECRETDEVICE_ERASE_DISABLE     TAMP_DEVICESECRETS_ERASE_NONE
1263 
#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
 1263 
#define TAMP_SECRETDEVICE_ERASE_ENABLE      TAMP_SECRETDEVICE_ERASE_ALL
1264 
#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
 1264 
#endif /* STM32H5 || STM32WBA */
1265 
 
 1265 
 
1266 
#define __DIV_LPUART                    UART_DIV_LPUART
 1266 
#if defined(STM32F7)
1267 
 
 1267 
#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_ENABLE_BITS_MASK
1268 
#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
 1268 
#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_IT_ENABLE_BITS_MASK
1269 
#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
 1269 
#endif /* STM32F7 */
1270 
 
 1270 
 
1271 
/**
 1271 
#if defined(STM32H7)
1272 
  * @}
 1272 
#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X
1273 
  */
 1273 
#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT
1274 
 
 1274 
#endif /* STM32H7 */
1275 
 
 1275 
 
1276 
/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
 1276 
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
1277 
  * @{
 1277 
#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1
1278 
  */
 1278 
#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2
1279 
 
 1279 
#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3
1280 
#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
 1280 
#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMP
1281 
#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
 1281 
#endif /* STM32F7 || STM32H7 || STM32L0 */
1282 
 
 1282 
 
1283 
#define USARTNACK_ENABLED               USART_NACK_ENABLE
 1283 
/**
1284 
#define USARTNACK_DISABLED              USART_NACK_DISABLE
 1284 
  * @}
1285 
/**
 1285 
  */
1286 
  * @}
 1286 
 
1287 
  */
 1287 
 
1288 
 
 1288 
/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
1289 
/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
 1289 
  * @{
1290 
  * @{
 1290 
  */
1291 
  */
 1291 
#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE
1292 
#define CFR_BASE                    WWDG_CFR_BASE
 1292 
#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE
1293 
 
 1293 
 
1294 
/**
 1294 
#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE
1295 
  * @}
 1295 
#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE
1296 
  */
 1296 
#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE
1297 
 
 1297 
#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE
1298 
/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
 1298 
 
1299 
  * @{
 1299 
#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE
1300 
  */
 1300 
#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE
1301 
#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
 1301 
 
1302 
#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
 1302 
#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE
1303 
#define CAN_IT_RQCP0                CAN_IT_TME
 1303 
#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE
1304 
#define CAN_IT_RQCP1                CAN_IT_TME
 1304 
/**
1305 
#define CAN_IT_RQCP2                CAN_IT_TME
 1305 
  * @}
1306 
#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
 1306 
  */
1307 
#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
 1307 
 
1308 
#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
 1308 
 
1309 
#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
 1309 
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
1310 
#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
 1310 
  * @{
1311 
 
 1311 
  */
1312 
/**
 1312 
#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE
1313 
  * @}
 1313 
#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE
1314 
  */
 1314 
#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE
1315 
 
 1315 
#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE
1316 
/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
 1316 
#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE
1317 
  * @{
 1317 
#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE
1318 
  */
 1318 
#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE
1319 
 
 1319 
#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE
1320 
#define VLAN_TAG                ETH_VLAN_TAG
 1320 
#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE
1321 
#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
 1321 
#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE
1322 
#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
 1322 
#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN
1323 
#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
 1323 
/**
1324 
#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
 1324 
  * @}
1325 
#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
 1325 
  */
1326 
#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
 1326 
 
1327 
#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
 1327 
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
1328 
 
 1328 
  * @{
1329 
#define ETH_MMCCR              0x00000100U
 1329 
  */
1330 
#define ETH_MMCRIR             0x00000104U
 1330 
#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE
1331 
#define ETH_MMCTIR             0x00000108U
 1331 
#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE
1332 
#define ETH_MMCRIMR            0x0000010CU
 1332 
 
1333 
#define ETH_MMCTIMR            0x00000110U
 1333 
#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE
1334 
#define ETH_MMCTGFSCCR         0x0000014CU
 1334 
#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE
1335 
#define ETH_MMCTGFMSCCR        0x00000150U
 1335 
 
1336 
#define ETH_MMCTGFCR           0x00000168U
 1336 
#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE
1337 
#define ETH_MMCRFCECR          0x00000194U
 1337 
#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE
1338 
#define ETH_MMCRFAECR          0x00000198U
 1338 
 
1339 
#define ETH_MMCRGUFCR          0x000001C4U
 1339 
#if defined(STM32H7)
1340 
 
 1340 
 
1341 
#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */
 1341 
#define SPI_FLAG_TXE                    SPI_FLAG_TXP
1342 
#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */
 1342 
#define SPI_FLAG_RXNE                   SPI_FLAG_RXP
1343 
#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */
 1343 
 
1344 
#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */
 1344 
#define SPI_IT_TXE                      SPI_IT_TXP
1345 
#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
 1345 
#define SPI_IT_RXNE                     SPI_IT_RXP
1346 
#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
 1346 
 
1347 
#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
 1347 
#define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET
1348 
#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */
 1348 
#define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET
1349 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */
 1349 
#define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET
1350 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
 1350 
#define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET
1351 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
 1351 
 
1352 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */
 1352 
#endif /* STM32H7 */
1353 
#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
 1353 
 
1354 
#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
 1354 
/**
1355 
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
 1355 
  * @}
1356 
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
 1356 
  */
1357 
#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
 1357 
 
1358 
#if defined(STM32F1)
 1358 
/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
1359 
#else
 1359 
  * @{
1360 
#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
 1360 
  */
1361 
#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
 1361 
#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK
1362 
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
 1362 
#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK
1363 
#endif
 1363 
 
1364 
#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
 1364 
#define TIM_DMABase_CR1                  TIM_DMABASE_CR1
1365 
#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
 1365 
#define TIM_DMABase_CR2                  TIM_DMABASE_CR2
1366 
#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
 1366 
#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR
1367 
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
 1367 
#define TIM_DMABase_DIER                 TIM_DMABASE_DIER
1368 
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
 1368 
#define TIM_DMABase_SR                   TIM_DMABASE_SR
1369 
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
 1369 
#define TIM_DMABase_EGR                  TIM_DMABASE_EGR
1370 
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
 1370 
#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1
1371 
 
 1371 
#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2
1372 
/**
 1372 
#define TIM_DMABase_CCER                 TIM_DMABASE_CCER
1373 
  * @}
 1373 
#define TIM_DMABase_CNT                  TIM_DMABASE_CNT
1374 
  */
 1374 
#define TIM_DMABase_PSC                  TIM_DMABASE_PSC
1375 
 
 1375 
#define TIM_DMABase_ARR                  TIM_DMABASE_ARR
1376 
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
 1376 
#define TIM_DMABase_RCR                  TIM_DMABASE_RCR
1377 
  * @{
 1377 
#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1
1378 
  */
 1378 
#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2
1379 
#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
 1379 
#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3
1380 
#define DCMI_IT_OVF             DCMI_IT_OVR
 1380 
#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4
1381 
#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
 1381 
#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR
1382 
#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
 1382 
#define TIM_DMABase_DCR                  TIM_DMABASE_DCR
1383 
 
 1383 
#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR
1384 
#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
 1384 
#define TIM_DMABase_OR1                  TIM_DMABASE_OR1
1385 
#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
 1385 
#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3
1386 
#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
 1386 
#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5
1387 
 
 1387 
#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6
1388 
/**
 1388 
#define TIM_DMABase_OR2                  TIM_DMABASE_OR2
1389 
  * @}
 1389 
#define TIM_DMABase_OR3                  TIM_DMABASE_OR3
1390 
  */
 1390 
#define TIM_DMABase_OR                   TIM_DMABASE_OR
1391 
 
 1391 
 
1392 
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
 1392 
#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE
1393 
  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
 1393 
#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1
1394 
  || defined(STM32H7)
 1394 
#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2
1395 
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
 1395 
#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3
1396 
  * @{
 1396 
#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4
1397 
  */
 1397 
#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM
1398 
#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
 1398 
#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER
1399 
#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
 1399 
#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK
1400 
#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
 1400 
#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2
1401 
#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
 1401 
 
1402 
#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
 1402 
#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER
1403 
 
 1403 
#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS
1404 
#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
 1404 
#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS
1405 
#define CM_RGB888               DMA2D_INPUT_RGB888
 1405 
#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS
1406 
#define CM_RGB565               DMA2D_INPUT_RGB565
 1406 
#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS
1407 
#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
 1407 
#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS
1408 
#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
 1408 
#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS
1409 
#define CM_L8                   DMA2D_INPUT_L8
 1409 
#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS
1410 
#define CM_AL44                 DMA2D_INPUT_AL44
 1410 
#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS
1411 
#define CM_AL88                 DMA2D_INPUT_AL88
 1411 
#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS
1412 
#define CM_L4                   DMA2D_INPUT_L4
 1412 
#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS
1413 
#define CM_A8                   DMA2D_INPUT_A8
 1413 
#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS
1414 
#define CM_A4                   DMA2D_INPUT_A4
 1414 
#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS
1415 
/**
 1415 
#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS
1416 
  * @}
 1416 
#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS
1417 
  */
 1417 
#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS
1418 
#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
 1418 
#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS
1419 
 
 1419 
#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS
1420 
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
 1420 
 
1421 
  * @{
 1421 
#if defined(STM32L0)
1422 
  */
 1422 
#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO
1423 
 
 1423 
#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO
1424 
/**
 1424 
#endif
1425 
  * @}
 1425 
 
1426 
  */
 1426 
#if defined(STM32F3)
1427 
 
 1427 
#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
1428 
/* Exported functions --------------------------------------------------------*/
 1428 
#endif
1429 
 
 1429 
 
1430 
/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
 1430 
#if defined(STM32H7)
1431 
  * @{
 1431 
#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1
1432 
  */
 1432 
#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2
1433 
#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
 1433 
#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1
1434 
/**
 1434 
#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2
1435 
  * @}
 1435 
#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1
1436 
  */
 1436 
#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2
1437 
 
 1437 
#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1
1438 
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
 1438 
#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1
1439 
  * @{
 1439 
#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2
1440 
  */
 1440 
#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1
1441 
#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
 1441 
#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2
1442 
#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
 1442 
#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2
1443 
#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
 1443 
#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1
1444 
#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
 1444 
#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2
1445 
#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
 1445 
#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2
1446 
#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
 1446 
#endif
1447 
 
 1447 
 
1448 
/*HASH Algorithm Selection*/
 1448 
#if defined(STM32U5)
1449 
 
 1449 
#define OCREF_CLEAR_SELECT_Pos       OCREF_CLEAR_SELECT_POS
1450 
#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
 1450 
#define OCREF_CLEAR_SELECT_Msk       OCREF_CLEAR_SELECT_MSK
1451 
#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
 1451 
#endif
1452 
#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
 1452 
/**
1453 
#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
 1453 
  * @}
1454 
 
 1454 
  */
1455 
#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
 1455 
 
1456 
#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
 1456 
/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose
1457 
 
 1457 
  * @{
1458 
#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
 1458 
  */
1459 
#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
 1459 
#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING
1460 
 
 1460 
#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING
1461 
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
 1461 
/**
1462 
 
 1462 
  * @}
1463 
#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
 1463 
  */
1464 
#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
 1464 
 
1465 
#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
 1465 
/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose
1466 
#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
 1466 
  * @{
1467 
 
 1467 
  */
1468 
#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
 1468 
#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE
1469 
#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
 1469 
#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE
1470 
#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
 1470 
#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE
1471 
#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
 1471 
#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE
1472 
 
 1472 
 
1473 
#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
 1473 
#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE
1474 
#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
 1474 
#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE
1475 
#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
 1475 
 
1476 
#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
 1476 
#define __DIV_SAMPLING16                UART_DIV_SAMPLING16
1477 
 
 1477 
#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16
1478 
#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
 1478 
#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16
1479 
#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
 1479 
#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16
1480 
#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
 1480 
 
1481 
#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
 1481 
#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8
1482 
 
 1482 
#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8
1483 
#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
 1483 
#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8
1484 
/**
 1484 
#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8
1485 
  * @}
 1485 
 
1486 
  */
 1486 
#define __DIV_LPUART                    UART_DIV_LPUART
1487 
 
 1487 
 
1488 
/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
 1488 
#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE
1489 
  * @{
 1489 
#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK
1490 
  */
 1490 
 
1491 
#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
 1491 
/**
1492 
#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
 1492 
  * @}
1493 
#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
 1493 
  */
1494 
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
 1494 
 
1495 
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
 1495 
 
1496 
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
 1496 
/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
1497 
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
 1497 
  * @{
1498 
#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
 1498 
  */
1499 
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
 1499 
 
1500 
#if defined(STM32L0)
 1500 
#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE
1501 
#else
 1501 
#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE
1502 
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
 1502 
 
1503 
#endif
 1503 
#define USARTNACK_ENABLED               USART_NACK_ENABLE
1504 
#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
 1504 
#define USARTNACK_DISABLED              USART_NACK_DISABLE
1505 
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
 1505 
/**
1506 
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
 1506 
  * @}
1507 
#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
 1507 
  */
1508 
#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
 1508 
 
1509 
#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
 1509 
/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose
1510 
#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
 1510 
  * @{
1511 
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
 1511 
  */
1512 
 
 1512 
#define CFR_BASE                    WWDG_CFR_BASE
1513 
/**
 1513 
 
1514 
  * @}
 1514 
/**
1515 
  */
 1515 
  * @}
1516 
 
 1516 
  */
1517 
/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
 1517 
 
1518 
  * @{
 1518 
/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose
1519 
  */
 1519 
  * @{
1520 
#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
 1520 
  */
1521 
#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
 1521 
#define CAN_FilterFIFO0             CAN_FILTER_FIFO0
1522 
#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
 1522 
#define CAN_FilterFIFO1             CAN_FILTER_FIFO1
1523 
#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
 1523 
#define CAN_IT_RQCP0                CAN_IT_TME
1524 
#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
 1524 
#define CAN_IT_RQCP1                CAN_IT_TME
1525 
#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
 1525 
#define CAN_IT_RQCP2                CAN_IT_TME
1526 
#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
 1526 
#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE
1527 
 
 1527 
#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE
1528 
 /**
 1528 
#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)
1529 
  * @}
 1529 
#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)
1530 
  */
 1530 
#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)
1531 
 
 1531 
 
1532 
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
 1532 
/**
1533 
  * @{
 1533 
  * @}
1534 
  */
 1534 
  */
1535 
#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
 1535 
 
1536 
#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
 1536 
/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
1537 
#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
 1537 
  * @{
1538 
#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
 1538 
  */
1539 
 
 1539 
 
1540 
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
 1540 
#define VLAN_TAG                ETH_VLAN_TAG
1541 
 
 1541 
#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD
1542 
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
 1542 
#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD
1543 
#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
 1543 
#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD
1544 
#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
 1544 
#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK
1545 
#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
 1545 
#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK
1546 
#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
 1546 
#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK
1547 
#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
 1547 
#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK
1548 
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
 1548 
 
1549 
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
 1549 
#define ETH_MMCCR              0x00000100U
1550 
#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
 1550 
#define ETH_MMCRIR             0x00000104U
1551 
#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
 1551 
#define ETH_MMCTIR             0x00000108U
1552 
#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
 1552 
#define ETH_MMCRIMR            0x0000010CU
1553 
#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
 1553 
#define ETH_MMCTIMR            0x00000110U
1554 
 
 1554 
#define ETH_MMCTGFSCCR         0x0000014CU
1555 
#if defined(STM32F4)
 1555 
#define ETH_MMCTGFMSCCR        0x00000150U
1556 
#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
 1556 
#define ETH_MMCTGFCR           0x00000168U
1557 
#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
 1557 
#define ETH_MMCRFCECR          0x00000194U
1558 
#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
 1558 
#define ETH_MMCRFAECR          0x00000198U
1559 
#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
 1559 
#define ETH_MMCRGUFCR          0x000001C4U
1560 
#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
 1560 
 
1561 
#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
 1561 
#define ETH_MAC_TXFIFO_FULL                           0x02000000U  /* Tx FIFO full */
1562 
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
 1562 
#define ETH_MAC_TXFIFONOT_EMPTY                       0x01000000U  /* Tx FIFO not empty */
1563 
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
 1563 
#define ETH_MAC_TXFIFO_WRITE_ACTIVE                   0x00400000U  /* Tx FIFO write active */
1564 
#endif /* STM32F4 */
 1564 
#define ETH_MAC_TXFIFO_IDLE                           0x00000000U  /* Tx FIFO read status: Idle */
1565 
 /**
 1565 
#define ETH_MAC_TXFIFO_READ                           0x00100000U  /* Tx FIFO read status: Read (transferring data to
1566 
  * @}
 1566 
                                                                      the MAC transmitter) */
1567 
  */
 1567 
#define ETH_MAC_TXFIFO_WAITING                        0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from
1568 
 
 1568 
                                                                      MAC transmitter */
1569 
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
 1569 
#define ETH_MAC_TXFIFO_WRITING                        0x00300000U  /* Tx FIFO read status: Writing the received TxStatus
1570 
  * @{
 1570 
                                                                      or flushing the TxFIFO */
1571 
  */
 1571 
#define ETH_MAC_TRANSMISSION_PAUSE                    0x00080000U  /* MAC transmitter in pause */
1572 
 
 1572 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE          0x00000000U  /* MAC transmit frame controller: Idle */
1573 
#if defined(STM32G0)
 1573 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING       0x00020000U  /* MAC transmit frame controller: Waiting for Status
1574 
#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
 1574 
                                                                   of previous frame or IFG/backoff period to be over */
1575 
#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
 1575 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U  /* MAC transmit frame controller: Generating and
1576 
#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
 1576 
                                                             transmitting a Pause control frame (in full duplex mode) */
1577 
#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
 1577 
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING  0x00060000U  /* MAC transmit frame controller: Transferring input
1578 
#endif
 1578 
                                                                      frame for transmission */
1579 
#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
 1579 
#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */
1580 
#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
 1580 
#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */
1581 
#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
 1581 
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control
1582 
#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
 1582 
                                                              de-activate threshold */
1583 
#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
 1583 
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control
1584 
#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
 1584 
                                                              activate threshold */
1585 
#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
 1585 
#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
1586 
#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
 1586 
#if defined(STM32F1)
1587 
#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
 1587 
#else
1588 
#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
 1588 
#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
1589 
#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
 1589 
#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
1590 
#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
 1590 
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status
1591 
#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
 1591 
                                                             (or time-stamp) */
1592 
#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
 1592 
#endif
1593 
#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
 1593 
#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and
1594 
#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
 1594 
                                                              status */
1595 
 
 1595 
#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
1596 
#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
 1596 
#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
1597 
#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
 1597 
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */
1598 
#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
 1598 
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */
1599 
#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
 1599 
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */
1600 
#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
 1600 
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */
1601 
#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
 1601 
 
1602 
#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
 1602 
/**
1603 
 
 1603 
  * @}
1604 
#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
 1604 
  */
1605 
#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
 1605 
 
1606 
#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
 1606 
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
1607 
#define CR_PMODE_BB                                   CR_VOS_BB
 1607 
  * @{
1608 
 
 1608 
  */
1609 
#define DBP_BitNumber                                 DBP_BIT_NUMBER
 1609 
#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR
1610 
#define PVDE_BitNumber                                PVDE_BIT_NUMBER
 1610 
#define DCMI_IT_OVF             DCMI_IT_OVR
1611 
#define PMODE_BitNumber                               PMODE_BIT_NUMBER
 1611 
#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI
1612 
#define EWUP_BitNumber                                EWUP_BIT_NUMBER
 1612 
#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI
1613 
#define FPDS_BitNumber                                FPDS_BIT_NUMBER
 1613 
 
1614 
#define ODEN_BitNumber                                ODEN_BIT_NUMBER
 1614 
#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop
1615 
#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
 1615 
#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop
1616 
#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
 1616 
#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop
1617 
#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
 1617 
 
1618 
#define BRE_BitNumber                                 BRE_BIT_NUMBER
 1618 
/**
1619 
 
 1619 
  * @}
1620 
#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
 1620 
  */
1621 
 
 1621 
 
1622 
 /**
 1622 
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
1623 
  * @}
 1623 
  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
1624 
  */
 1624 
  || defined(STM32H7)
1625 
 
 1625 
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
1626 
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
 1626 
  * @{
1627 
  * @{
 1627 
  */
1628 
  */
 1628 
#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888
1629 
#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
 1629 
#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888
1630 
#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
 1630 
#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565
1631 
#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
 1631 
#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555
1632 
/**
 1632 
#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444
1633 
  * @}
 1633 
 
1634 
  */
 1634 
#define CM_ARGB8888             DMA2D_INPUT_ARGB8888
1635 
 
 1635 
#define CM_RGB888               DMA2D_INPUT_RGB888
1636 
/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
 1636 
#define CM_RGB565               DMA2D_INPUT_RGB565
1637 
  * @{
 1637 
#define CM_ARGB1555             DMA2D_INPUT_ARGB1555
1638 
  */
 1638 
#define CM_ARGB4444             DMA2D_INPUT_ARGB4444
1639 
#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
 1639 
#define CM_L8                   DMA2D_INPUT_L8
1640 
/**
 1640 
#define CM_AL44                 DMA2D_INPUT_AL44
1641 
  * @}
 1641 
#define CM_AL88                 DMA2D_INPUT_AL88
1642 
  */
 1642 
#define CM_L4                   DMA2D_INPUT_L4
1643 
 
 1643 
#define CM_A8                   DMA2D_INPUT_A8
1644 
/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
 1644 
#define CM_A4                   DMA2D_INPUT_A4
1645 
  * @{
 1645 
/**
1646 
  */
 1646 
  * @}
1647 
#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
 1647 
  */
1648 
#define HAL_TIM_DMAError                                TIM_DMAError
 1648 
#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */
1649 
#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
 1649 
 
1650 
#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
 1650 
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \
1651 
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
 1651 
  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \
1652 
#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
 1652 
  || defined(STM32H7) || defined(STM32U5)
1653 
#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
 1653 
/** @defgroup DMA2D_Aliases DMA2D API Aliases
1654 
#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
 1654 
  * @{
1655 
#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
 1655 
  */
1656 
#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
 1656 
#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort
1657 
#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
 1657 
                                                                        for compatibility with legacy code */
1658 
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
 1658 
/**
1659 
/**
 1659 
  * @}
1660 
  * @}
 1660 
  */
1661 
  */
 1661 
 
1662 
 
 1662 
#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 || STM32U5 */
1663 
/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
 1663 
 
1664 
  * @{
 1664 
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
1665 
  */
 1665 
  * @{
1666 
#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
 1666 
  */
1667 
/**
 1667 
 
1668 
  * @}
 1668 
/**
1669 
  */
 1669 
  * @}
1670 
 
 1670 
  */
1671 
/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
 1671 
 
1672 
  * @{
 1672 
/* Exported functions --------------------------------------------------------*/
1673 
  */
 1673 
 
1674 
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
 1674 
/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose
1675 
#define HAL_LTDC_Relaod           HAL_LTDC_Reload
 1675 
  * @{
1676 
#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
 1676 
  */
1677 
#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
 1677 
#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback
1678 
/**
 1678 
/**
1679 
  * @}
 1679 
  * @}
1680 
  */
 1680 
  */
1681 
 
 1681 
 
1682 
 
 1682 
/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose
1683 
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
 1683 
  * @{
1684 
  * @{
 1684 
  */
1685 
  */
 1685 
 
1686 
 
 1686 
#if defined(STM32U5)
1687 
/**
 1687 
#define HAL_DCACHE_CleanInvalidateByAddr     HAL_DCACHE_CleanInvalidByAddr
1688 
  * @}
 1688 
#define HAL_DCACHE_CleanInvalidateByAddr_IT  HAL_DCACHE_CleanInvalidByAddr_IT
1689 
  */
 1689 
#endif /* STM32U5 */
1690 
 
 1690 
 
1691 
/* Exported macros ------------------------------------------------------------*/
 1691 
/**
1692 
 
 1692 
  * @}
1693 
/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
 1693 
  */
1694 
  * @{
 1694 
 
1695 
  */
 1695 
#if !defined(STM32F2)
1696 
#define AES_IT_CC                      CRYP_IT_CC
 1696 
/** @defgroup HASH_alias HASH API alias
1697 
#define AES_IT_ERR                     CRYP_IT_ERR
 1697 
  * @{
1698 
#define AES_FLAG_CCF                   CRYP_FLAG_CCF
 1698 
  */
1699 
/**
 1699 
#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< Redirection for compatibility with legacy code */
1700 
  * @}
 1700 
/**
1701 
  */
 1701 
  *
1702 
 
 1702 
  * @}
1703 
/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
 1703 
  */
1704 
  * @{
 1704 
#endif /* STM32F2 */
1705 
  */
 1705 
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
1706 
#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
 1706 
  * @{
1707 
#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
 1707 
  */
1708 
#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
 1708 
#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef
1709 
#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
 1709 
#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef
1710 
#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
 1710 
#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish
1711 
#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
 1711 
#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish
1712 
#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
 1712 
#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish
1713 
#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
 1713 
#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish
1714 
#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
 1714 
 
1715 
#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
 1715 
/*HASH Algorithm Selection*/
1716 
#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
 1716 
 
1717 
#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
 1717 
#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1
1718 
#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
 1718 
#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224
1719 
#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
 1719 
#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256
1720 
 
 1720 
#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5
1721 
#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
 1721 
 
1722 
#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
 1722 
#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH
1723 
#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
 1723 
#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC
1724 
#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
 1724 
 
1725 
#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
 1725 
#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY
1726 
 
 1726 
#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY
1727 
/**
 1727 
 
1728 
  * @}
 1728 
#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
1729 
  */
 1729 
 
1730 
 
 1730 
#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt
1731 
 
 1731 
#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End
1732 
/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
 1732 
#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT
1733 
  * @{
 1733 
#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT
1734 
  */
 1734 
 
1735 
#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
 1735 
#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt
1736 
#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
 1736 
#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End
1737 
#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
 1737 
#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT
1738 
#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
 1738 
#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT
1739 
#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
 1739 
 
1740 
#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
 1740 
#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt
1741 
#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
 1741 
#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End
1742 
#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
 1742 
#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT
1743 
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
 1743 
#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT
1744 
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
 1744 
 
1745 
#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
 1745 
#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt
1746 
#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
 1746 
#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End
1747 
#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
 1747 
#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT
1748 
 
 1748 
#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT
1749 
#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
 1749 
 
1750 
#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
 1750 
#endif  /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */
1751 
#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
 1751 
/**
1752 
#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
 1752 
  * @}
1753 
#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
 1753 
  */
1754 
#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
 1754 
 
1755 
#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
 1755 
/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
1756 
#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
 1756 
  * @{
1757 
#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
 1757 
  */
1758 
#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
 1758 
#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode
1759 
#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
 1759 
#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode
1760 
#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
 1760 
#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode
1761 
#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
 1761 
#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode
1762 
#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
 1762 
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
1763 
#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
 1763 
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
1764 
#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
 1764 
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
1765 
#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
 1765 
                                              )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
1766 
#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
 1766 
                                             HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
1767 
#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
 1767 
#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect
1768 
#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
 1768 
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
1769 
 
 1769 
#if defined(STM32L0)
1770 
#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
 1770 
#else
1771 
#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
 1771 
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
1772 
#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
 1772 
#endif
1773 
#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
 1773 
#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
1774 
#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
 1774 
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
1775 
#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
 1775 
                                              )==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : \
1776 
#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
 1776 
                                             HAL_ADCEx_DisableVREFINTTempSensor())
1777 
#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
 1777 
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
1778 
#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
 1778 
    defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
1779 
#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
 1779 
#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode
1780 
 
 1780 
#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode
1781 
#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
 1781 
#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode
1782 
#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
 1782 
#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode
1783 
#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
 1783 
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */
1784 
#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
 1784 
 
1785 
#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
 1785 
/**
1786 
#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
 1786 
  * @}
1787 
#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
 1787 
  */
1788 
#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
 1788 
 
1789 
 
 1789 
/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose
1790 
#define __HAL_ADC_SQR1                                   ADC_SQR1
 1790 
  * @{
1791 
#define __HAL_ADC_SMPR1                                  ADC_SMPR1
 1791 
  */
1792 
#define __HAL_ADC_SMPR2                                  ADC_SMPR2
 1792 
#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram
1793 
#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
 1793 
#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown
1794 
#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
 1794 
#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown
1795 
#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
 1795 
#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock
1796 
#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
 1796 
#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock
1797 
#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
 1797 
#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase
1798 
#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
 1798 
#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program
1799 
#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
 1799 
 
1800 
#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
 1800 
/**
1801 
#define __HAL_ADC_JSQR                                   ADC_JSQR
 1801 
  * @}
1802 
 
 1802 
 */
1803 
#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
 1803 
 
1804 
#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
 1804 
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
1805 
#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
 1805 
  * @{
1806 
#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
 1806 
  */
1807 
#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
 1807 
#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter
1808 
#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
 1808 
#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter
1809 
#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
 1809 
#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter
1810 
#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
 1810 
#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter
1811 
 
 1811 
 
1812 
/**
 1812 
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
1813 
  * @}
 1813 
                                                                HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
1814 
  */
 1814 
                                                                HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
1815 
 
 1815 
 
1816 
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
 1816 
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
1817 
  * @{
 1817 
    defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
1818 
  */
 1818 
    defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
1819 
#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
 1819 
#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT
1820 
#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
 1820 
#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT
1821 
#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
 1821 
#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT
1822 
#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
 1822 
#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT
1823 
 
 1823 
#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
1824 
/**
 1824 
          STM32L4 || STM32L5 || STM32G4 || STM32L1 */
1825 
  * @}
 1825 
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
1826 
  */
 1826 
    defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
1827 
 
 1827 
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
1828 
/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
 1828 
#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA
1829 
  * @{
 1829 
#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA
1830 
  */
 1830 
#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA
1831 
#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
 1831 
#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
1832 
#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
 1832 
 
1833 
#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
 1833 
#if defined(STM32F4)
1834 
#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
 1834 
#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT
1835 
#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
 1835 
#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT
1836 
#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
 1836 
#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT
1837 
#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
 1837 
#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT
1838 
#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
 1838 
#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA
1839 
#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
 1839 
#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA
1840 
#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
 1840 
#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA
1841 
#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
 1841 
#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA
1842 
#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
 1842 
#endif /* STM32F4 */
1843 
#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
 1843 
/**
1844 
#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
 1844 
  * @}
1845 
#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
 1845 
 */
1846 
#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
 1846 
 
1847 
 
 1847 
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
1848 
#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
 1848 
  * @{
1849 
#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
 1849 
  */
1850 
#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
 1850 
 
1851 
#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
 1851 
#if defined(STM32G0)
1852 
#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
 1852 
#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD
1853 
#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
 1853 
#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD
1854 
#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
 1854 
#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD
1855 
#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
 1855 
#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler
1856 
#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
 1856 
#endif
1857 
#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
 1857 
#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD
1858 
#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
 1858 
#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg
1859 
#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
 1859 
#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown
1860 
#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
 1860 
#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor
1861 
#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
 1861 
#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg
1862 
 
 1862 
#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown
1863 
 
 1863 
#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor
1864 
#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
 1864 
#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler
1865 
#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
 1865 
#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD
1866 
#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
 1866 
#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler
1867 
#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
 1867 
#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback
1868 
#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
 1868 
#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive
1869 
#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
 1869 
#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive
1870 
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
 1870 
#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC
1871 
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
 1871 
#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC
1872 
#if defined(STM32H7)
 1872 
#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM
1873 
  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
 1873 
 
1874 
  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
 1874 
#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL
1875 
  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
 1875 
#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING
1876 
  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
 1876 
#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING
1877 
#else
 1877 
#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING
1878 
  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
 1878 
#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING
1879 
  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
 1879 
#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING
1880 
  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
 1880 
#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING
1881 
  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
 1881 
 
1882 
#endif /* STM32H7 */
 1882 
#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB
1883 
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
 1883 
#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB
1884 
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
 1884 
#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER
1885 
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
 1885 
#define CR_PMODE_BB                                   CR_VOS_BB
1886 
#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
 1886 
 
1887 
#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
 1887 
#define DBP_BitNumber                                 DBP_BIT_NUMBER
1888 
#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
 1888 
#define PVDE_BitNumber                                PVDE_BIT_NUMBER
1889 
#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
 1889 
#define PMODE_BitNumber                               PMODE_BIT_NUMBER
1890 
#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
 1890 
#define EWUP_BitNumber                                EWUP_BIT_NUMBER
1891 
#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
 1891 
#define FPDS_BitNumber                                FPDS_BIT_NUMBER
1892 
#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
 1892 
#define ODEN_BitNumber                                ODEN_BIT_NUMBER
1893 
#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
 1893 
#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER
1894 
#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
 1894 
#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER
1895 
 
 1895 
#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER
1896 
/**
 1896 
#define BRE_BitNumber                                 BRE_BIT_NUMBER
1897 
  * @}
 1897 
 
1898 
  */
 1898 
#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL
1899 
 
 1899 
 
1900 
/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
 1900 
#if defined (STM32U5)
1901 
  * @{
 1901 
#define PWR_SRAM1_PAGE1_STOP_RETENTION                PWR_SRAM1_PAGE1_STOP
1902 
  */
 1902 
#define PWR_SRAM1_PAGE2_STOP_RETENTION                PWR_SRAM1_PAGE2_STOP
1903 
#if defined(STM32F3)
 1903 
#define PWR_SRAM1_PAGE3_STOP_RETENTION                PWR_SRAM1_PAGE3_STOP
1904 
#define COMP_START                                       __HAL_COMP_ENABLE
 1904 
#define PWR_SRAM1_PAGE4_STOP_RETENTION                PWR_SRAM1_PAGE4_STOP
1905 
#define COMP_STOP                                        __HAL_COMP_DISABLE
 1905 
#define PWR_SRAM1_PAGE5_STOP_RETENTION                PWR_SRAM1_PAGE5_STOP
1906 
#define COMP_LOCK                                        __HAL_COMP_LOCK
 1906 
#define PWR_SRAM1_PAGE6_STOP_RETENTION                PWR_SRAM1_PAGE6_STOP
1907 
 
 1907 
#define PWR_SRAM1_PAGE7_STOP_RETENTION                PWR_SRAM1_PAGE7_STOP
1908 
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
 1908 
#define PWR_SRAM1_PAGE8_STOP_RETENTION                PWR_SRAM1_PAGE8_STOP
1909 
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
 1909 
#define PWR_SRAM1_PAGE9_STOP_RETENTION                PWR_SRAM1_PAGE9_STOP
1910 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
 1910 
#define PWR_SRAM1_PAGE10_STOP_RETENTION               PWR_SRAM1_PAGE10_STOP
1911 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
 1911 
#define PWR_SRAM1_PAGE11_STOP_RETENTION               PWR_SRAM1_PAGE11_STOP
1912 
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
 1912 
#define PWR_SRAM1_PAGE12_STOP_RETENTION               PWR_SRAM1_PAGE12_STOP
1913 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
 1913 
#define PWR_SRAM1_FULL_STOP_RETENTION                 PWR_SRAM1_FULL_STOP
1914 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
 1914 
 
1915 
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
 1915 
#define PWR_SRAM2_PAGE1_STOP_RETENTION                PWR_SRAM2_PAGE1_STOP
1916 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
 1916 
#define PWR_SRAM2_PAGE2_STOP_RETENTION                PWR_SRAM2_PAGE2_STOP
1917 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
 1917 
#define PWR_SRAM2_FULL_STOP_RETENTION                 PWR_SRAM2_FULL_STOP
1918 
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
 1918 
 
1919 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
 1919 
#define PWR_SRAM3_PAGE1_STOP_RETENTION                PWR_SRAM3_PAGE1_STOP
1920 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
 1920 
#define PWR_SRAM3_PAGE2_STOP_RETENTION                PWR_SRAM3_PAGE2_STOP
1921 
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
 1921 
#define PWR_SRAM3_PAGE3_STOP_RETENTION                PWR_SRAM3_PAGE3_STOP
1922 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
 1922 
#define PWR_SRAM3_PAGE4_STOP_RETENTION                PWR_SRAM3_PAGE4_STOP
1923 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
 1923 
#define PWR_SRAM3_PAGE5_STOP_RETENTION                PWR_SRAM3_PAGE5_STOP
1924 
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
 1924 
#define PWR_SRAM3_PAGE6_STOP_RETENTION                PWR_SRAM3_PAGE6_STOP
1925 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
 1925 
#define PWR_SRAM3_PAGE7_STOP_RETENTION                PWR_SRAM3_PAGE7_STOP
1926 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
 1926 
#define PWR_SRAM3_PAGE8_STOP_RETENTION                PWR_SRAM3_PAGE8_STOP
1927 
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
 1927 
#define PWR_SRAM3_PAGE9_STOP_RETENTION                PWR_SRAM3_PAGE9_STOP
1928 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
 1928 
#define PWR_SRAM3_PAGE10_STOP_RETENTION               PWR_SRAM3_PAGE10_STOP
1929 
                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
 1929 
#define PWR_SRAM3_PAGE11_STOP_RETENTION               PWR_SRAM3_PAGE11_STOP
1930 
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
 1930 
#define PWR_SRAM3_PAGE12_STOP_RETENTION               PWR_SRAM3_PAGE12_STOP
1931 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
 1931 
#define PWR_SRAM3_PAGE13_STOP_RETENTION               PWR_SRAM3_PAGE13_STOP
1932 
                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
 1932 
#define PWR_SRAM3_FULL_STOP_RETENTION                 PWR_SRAM3_FULL_STOP
1933 
# endif
 1933 
 
1934 
# if defined(STM32F302xE) || defined(STM32F302xC)
 1934 
#define PWR_SRAM4_FULL_STOP_RETENTION                 PWR_SRAM4_FULL_STOP
1935 
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
 1935 
 
1936 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
 1936 
#define PWR_SRAM5_PAGE1_STOP_RETENTION                PWR_SRAM5_PAGE1_STOP
1937 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
 1937 
#define PWR_SRAM5_PAGE2_STOP_RETENTION                PWR_SRAM5_PAGE2_STOP
1938 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
 1938 
#define PWR_SRAM5_PAGE3_STOP_RETENTION                PWR_SRAM5_PAGE3_STOP
1939 
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
 1939 
#define PWR_SRAM5_PAGE4_STOP_RETENTION                PWR_SRAM5_PAGE4_STOP
1940 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
 1940 
#define PWR_SRAM5_PAGE5_STOP_RETENTION                PWR_SRAM5_PAGE5_STOP
1941 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
 1941 
#define PWR_SRAM5_PAGE6_STOP_RETENTION                PWR_SRAM5_PAGE6_STOP
1942 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
 1942 
#define PWR_SRAM5_PAGE7_STOP_RETENTION                PWR_SRAM5_PAGE7_STOP
1943 
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
 1943 
#define PWR_SRAM5_PAGE8_STOP_RETENTION                PWR_SRAM5_PAGE8_STOP
1944 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
 1944 
#define PWR_SRAM5_PAGE9_STOP_RETENTION                PWR_SRAM5_PAGE9_STOP
1945 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
 1945 
#define PWR_SRAM5_PAGE10_STOP_RETENTION               PWR_SRAM5_PAGE10_STOP
1946 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
 1946 
#define PWR_SRAM5_PAGE11_STOP_RETENTION               PWR_SRAM5_PAGE11_STOP
1947 
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
 1947 
#define PWR_SRAM5_PAGE12_STOP_RETENTION               PWR_SRAM5_PAGE12_STOP
1948 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
 1948 
#define PWR_SRAM5_PAGE13_STOP_RETENTION               PWR_SRAM5_PAGE13_STOP
1949 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
 1949 
#define PWR_SRAM5_FULL_STOP_RETENTION                 PWR_SRAM5_FULL_STOP
1950 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
 1950 
 
1951 
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
 1951 
#define PWR_SRAM6_PAGE1_STOP_RETENTION                PWR_SRAM6_PAGE1_STOP
1952 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
 1952 
#define PWR_SRAM6_PAGE2_STOP_RETENTION                PWR_SRAM6_PAGE2_STOP
1953 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
 1953 
#define PWR_SRAM6_PAGE3_STOP_RETENTION                PWR_SRAM6_PAGE3_STOP
1954 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
 1954 
#define PWR_SRAM6_PAGE4_STOP_RETENTION                PWR_SRAM6_PAGE4_STOP
1955 
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
 1955 
#define PWR_SRAM6_PAGE5_STOP_RETENTION                PWR_SRAM6_PAGE5_STOP
1956 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
 1956 
#define PWR_SRAM6_PAGE6_STOP_RETENTION                PWR_SRAM6_PAGE6_STOP
1957 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
 1957 
#define PWR_SRAM6_PAGE7_STOP_RETENTION                PWR_SRAM6_PAGE7_STOP
1958 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
 1958 
#define PWR_SRAM6_PAGE8_STOP_RETENTION                PWR_SRAM6_PAGE8_STOP
1959 
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
 1959 
#define PWR_SRAM6_FULL_STOP_RETENTION                 PWR_SRAM6_FULL_STOP
1960 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
 1960 
 
1961 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
 1961 
 
1962 
                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
 1962 
#define PWR_ICACHE_FULL_STOP_RETENTION                PWR_ICACHE_FULL_STOP
1963 
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
 1963 
#define PWR_DCACHE1_FULL_STOP_RETENTION               PWR_DCACHE1_FULL_STOP
1964 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
 1964 
#define PWR_DCACHE2_FULL_STOP_RETENTION               PWR_DCACHE2_FULL_STOP
1965 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
 1965 
#define PWR_DMA2DRAM_FULL_STOP_RETENTION              PWR_DMA2DRAM_FULL_STOP
1966 
                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
 1966 
#define PWR_PERIPHRAM_FULL_STOP_RETENTION             PWR_PERIPHRAM_FULL_STOP
1967 
# endif
 1967 
#define PWR_PKA32RAM_FULL_STOP_RETENTION              PWR_PKA32RAM_FULL_STOP
1968 
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
 1968 
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION           PWR_GRAPHICPRAM_FULL_STOP
1969 
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
 1969 
#define PWR_DSIRAM_FULL_STOP_RETENTION                PWR_DSIRAM_FULL_STOP
1970 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
 1970 
#define PWR_JPEGRAM_FULL_STOP_RETENTION               PWR_JPEGRAM_FULL_STOP
1971 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
 1971 
 
1972 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
 1972 
 
1973 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
 1973 
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION             PWR_SRAM2_PAGE1_STANDBY
1974 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
 1974 
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION             PWR_SRAM2_PAGE2_STANDBY
1975 
                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
 1975 
#define PWR_SRAM2_FULL_STANDBY_RETENTION              PWR_SRAM2_FULL_STANDBY
1976 
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
 1976 
 
1977 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
 1977 
#define PWR_SRAM1_FULL_RUN_RETENTION                  PWR_SRAM1_FULL_RUN
1978 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
 1978 
#define PWR_SRAM2_FULL_RUN_RETENTION                  PWR_SRAM2_FULL_RUN
1979 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
 1979 
#define PWR_SRAM3_FULL_RUN_RETENTION                  PWR_SRAM3_FULL_RUN
1980 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
 1980 
#define PWR_SRAM4_FULL_RUN_RETENTION                  PWR_SRAM4_FULL_RUN
1981 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
 1981 
#define PWR_SRAM5_FULL_RUN_RETENTION                  PWR_SRAM5_FULL_RUN
1982 
                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
 1982 
#define PWR_SRAM6_FULL_RUN_RETENTION                  PWR_SRAM6_FULL_RUN
1983 
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
 1983 
 
1984 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
 1984 
#define PWR_ALL_RAM_RUN_RETENTION_MASK                PWR_ALL_RAM_RUN_MASK
1985 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
 1985 
#endif
1986 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
 1986 
 
1987 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
 1987 
/**
1988 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
 1988 
  * @}
1989 
                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
 1989 
 */
1990 
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
 1990 
 
1991 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
 1991 
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
1992 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
 1992 
  * @{
1993 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
 1993 
  */
1994 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
 1994 
#if defined(STM32H5) || defined(STM32WBA)
1995 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
 1995 
#define HAL_RTCEx_SetBoothardwareKey            HAL_RTCEx_LockBootHardwareKey
1996 
                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
 1996 
#define HAL_RTCEx_BKUPBlock_Enable              HAL_RTCEx_BKUPBlock
1997 
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
 1997 
#define HAL_RTCEx_BKUPBlock_Disable             HAL_RTCEx_BKUPUnblock
1998 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
 1998 
#define HAL_RTCEx_Erase_SecretDev_Conf          HAL_RTCEx_ConfigEraseDeviceSecrets
1999 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
 1999 
#endif /* STM32H5 || STM32WBA */
2000 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
 2000 
 
2001 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
 2001 
/**
2002 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
 2002 
  * @}
2003 
                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
 2003 
  */
2004 
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
 2004 
 
2005 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
 2005 
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
2006 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
 2006 
  * @{
2007 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
 2007 
  */
2008 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
 2008 
#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT
2009 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
 2009 
#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback
2010 
                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
 2010 
#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback
2011 
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
 2011 
/**
2012 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
 2012 
  * @}
2013 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
 2013 
  */
2014 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
 2014 
 
2015 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
 2015 
/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose
2016 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
 2016 
  * @{
2017 
                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
 2017 
  */
2018 
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
 2018 
#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo
2019 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
 2019 
/**
2020 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
 2020 
  * @}
2021 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
 2021 
  */
2022 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
 2022 
 
2023 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
 2023 
/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
2024 
                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
 2024 
  * @{
2025 
# endif
 2025 
  */
2026 
# if defined(STM32F373xC) ||defined(STM32F378xx)
 2026 
#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt
2027 
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
 2027 
#define HAL_TIM_DMAError                                TIM_DMAError
2028 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
 2028 
#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt
2029 
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
 2029 
#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt
2030 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
 2030 
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
2031 
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
 2031 
    defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
2032 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
 2032 
#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro
2033 
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
 2033 
#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT
2034 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
 2034 
#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback
2035 
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
 2035 
#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent
2036 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
 2036 
#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT
2037 
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
 2037 
#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA
2038 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
 2038 
#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
2039 
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
 2039 
/**
2040 
                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
 2040 
  * @}
2041 
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
 2041 
  */
2042 
                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
 2042 
 
2043 
# endif
 2043 
/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
2044 
#else
 2044 
  * @{
2045 
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
 2045 
  */
2046 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
 2046 
#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
2047 
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
 2047 
/**
2048 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
 2048 
  * @}
2049 
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
 2049 
  */
2050 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
 2050 
 
2051 
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
 2051 
/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
2052 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
 2052 
  * @{
2053 
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
 2053 
  */
2054 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
 2054 
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
2055 
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
 2055 
#define HAL_LTDC_Relaod           HAL_LTDC_Reload
2056 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
 2056 
#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
2057 
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
 2057 
#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
2058 
                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
 2058 
/**
2059 
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
 2059 
  * @}
2060 
                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
 2060 
  */
2061 
#endif
 2061 
 
2062 
 
 2062 
 
2063 
#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
 2063 
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
2064 
 
 2064 
  * @{
2065 
#if defined(STM32L0) || defined(STM32L4)
 2065 
  */
2066 
/* Note: On these STM32 families, the only argument of this macro             */
 2066 
 
2067 
/*       is COMP_FLAG_LOCK.                                                   */
 2067 
/**
2068 
/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
 2068 
  * @}
2069 
/*       argument.                                                            */
 2069 
  */
2070 
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
 2070 
 
2071 
#endif
 2071 
/* Exported macros ------------------------------------------------------------*/
2072 
/**
 2072 
 
2073 
  * @}
 2073 
/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose
2074 
  */
 2074 
  * @{
2075 
 
 2075 
  */
2076 
#if defined(STM32L0) || defined(STM32L4)
 2076 
#define AES_IT_CC                      CRYP_IT_CC
2077 
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
 2077 
#define AES_IT_ERR                     CRYP_IT_ERR
2078 
  * @{
 2078 
#define AES_FLAG_CCF                   CRYP_FLAG_CCF
2079 
  */
 2079 
/**
2080 
#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
 2080 
  * @}
2081 
#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
 2081 
  */
2082 
/**
 2082 
 
2083 
  * @}
 2083 
/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
2084 
  */
 2084 
  * @{
2085 
#endif
 2085 
  */
2086 
 
 2086 
#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE
2087 
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
 2087 
#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH
2088 
  * @{
 2088 
#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
2089 
  */
 2089 
#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM
2090 
 
 2090 
#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC
2091 
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
 2091 
#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
2092 
                          ((WAVE) == DAC_WAVE_NOISE)|| \
 2092 
#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC
2093 
                          ((WAVE) == DAC_WAVE_TRIANGLE))
 2093 
#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI
2094 
 
 2094 
#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK
2095 
/**
 2095 
#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG
2096 
  * @}
 2096 
#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG
2097 
  */
 2097 
#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE
2098 
 
 2098 
#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE
2099 
/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
 2099 
#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
2100 
  * @{
 2100 
 
2101 
  */
 2101 
#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY
2102 
 
 2102 
#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48
2103 
#define IS_WRPAREA          IS_OB_WRPAREA
 2103 
#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS
2104 
#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
 2104 
#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER
2105 
#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
 2105 
#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER
2106 
#define IS_TYPEERASE        IS_FLASH_TYPEERASE
 2106 
 
2107 
#define IS_NBSECTORS        IS_FLASH_NBSECTORS
 2107 
/**
2108 
#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
 2108 
  * @}
2109 
 
 2109 
  */
2110 
/**
 2110 
 
2111 
  * @}
 2111 
 
2112 
  */
 2112 
/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
2113 
 
 2113 
  * @{
2114 
/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
 2114 
  */
2115 
  * @{
 2115 
#define __ADC_ENABLE                                     __HAL_ADC_ENABLE
2116 
  */
 2116 
#define __ADC_DISABLE                                    __HAL_ADC_DISABLE
2117 
 
 2117 
#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS
2118 
#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
 2118 
#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS
2119 
#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
 2119 
#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE
2120 
#if defined(STM32F1)
 2120 
#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE
2121 
#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
 2121 
#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR
2122 
#else
 2122 
#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED
2123 
#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
 2123 
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED
2124 
#endif /* STM32F1 */
 2124 
#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR
2125 
#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
 2125 
#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED
2126 
#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
 2126 
#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING
2127 
#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
 2127 
#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE
2128 
#define __HAL_I2C_SPEED                 I2C_SPEED
 2128 
 
2129 
#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
 2129 
#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION
2130 
#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
 2130 
#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK
2131 
#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
 2131 
#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT
2132 
#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
 2132 
#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR
2133 
#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
 2133 
#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION
2134 
#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
 2134 
#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE
2135 
#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
 2135 
#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS
2136 
#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
 2136 
#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS
2137 
/**
 2137 
#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM
2138 
  * @}
 2138 
#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT
2139 
  */
 2139 
#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS
2140 
 
 2140 
#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN
2141 
/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
 2141 
#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ
2142 
  * @{
 2142 
#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET
2143 
  */
 2143 
#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET
2144 
 
 2144 
#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL
2145 
#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
 2145 
#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL
2146 
#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
 2146 
#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET
2147 
 
 2147 
#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET
2148 
#if defined(STM32H7)
 2148 
#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD
2149 
  #define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
 2149 
 
2150 
#endif
 2150 
#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION
2151 
 
 2151 
#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION
2152 
/**
 2152 
#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION
2153 
  * @}
 2153 
#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER
2154 
  */
 2154 
#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI
2155 
 
 2155 
#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE
2156 
/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
 2156 
#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE
2157 
  * @{
 2157 
#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER
2158 
  */
 2158 
#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER
2159 
 
 2159 
#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE
2160 
#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
 2160 
 
2161 
#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
 2161 
#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT
2162 
 
 2162 
#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT
2163 
#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
 2163 
#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL
2164 
#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
 2164 
#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM
2165 
#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
 2165 
#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET
2166 
#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
 2166 
#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE
2167 
 
 2167 
#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE
2168 
#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
 2168 
#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER
2169 
 
 2169 
 
2170 
 
 2170 
#define __HAL_ADC_SQR1                                   ADC_SQR1
2171 
/**
 2171 
#define __HAL_ADC_SMPR1                                  ADC_SMPR1
2172 
  * @}
 2172 
#define __HAL_ADC_SMPR2                                  ADC_SMPR2
2173 
  */
 2173 
#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK
2174 
 
 2174 
#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK
2175 
 
 2175 
#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK
2176 
/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
 2176 
#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS
2177 
  * @{
 2177 
#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS
2178 
  */
 2178 
#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV
2179 
#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
 2179 
#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection
2180 
#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
 2180 
#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq
2181 
/**
 2181 
#define __HAL_ADC_JSQR                                   ADC_JSQR
2182 
  * @}
 2182 
 
2183 
  */
 2183 
#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL
2184 
 
 2184 
#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS
2185 
 
 2185 
#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF
2186 
/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
 2186 
#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT
2187 
  * @{
 2187 
#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS
2188 
  */
 2188 
#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN
2189 
 
 2189 
#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR
2190 
#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
 2190 
#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ
2191 
#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
 2191 
 
2192 
#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
 2192 
/**
2193 
 
 2193 
  * @}
2194 
/**
 2194 
  */
2195 
  * @}
 2195 
 
2196 
  */
 2196 
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
2197 
 
 2197 
  * @{
2198 
 
 2198 
  */
2199 
/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
 2199 
#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT
2200 
  * @{
 2200 
#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT
2201 
  */
 2201 
#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT
2202 
#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
 2202 
#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE
2203 
#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
 2203 
 
2204 
#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
 2204 
/**
2205 
#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
 2205 
  * @}
2206 
#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
 2206 
  */
2207 
#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
 2207 
 
2208 
#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
 2208 
/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
2209 
#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
 2209 
  * @{
2210 
#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
 2210 
  */
2211 
#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
 2211 
#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1
2212 
#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
 2212 
#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1
2213 
#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
 2213 
#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2
2214 
#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
 2214 
#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2
2215 
 
 2215 
#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3
2216 
/**
 2216 
#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3
2217 
  * @}
 2217 
#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4
2218 
  */
 2218 
#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4
2219 
 
 2219 
#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5
2220 
 
 2220 
#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5
2221 
/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
 2221 
#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6
2222 
  * @{
 2222 
#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6
2223 
  */
 2223 
#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7
2224 
#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
 2224 
#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7
2225 
#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
 2225 
#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8
2226 
#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
 2226 
#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8
2227 
#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
 2227 
 
2228 
#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
 2228 
#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9
2229 
#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
 2229 
#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9
2230 
#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
 2230 
#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10
2231 
#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
 2231 
#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10
2232 
#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
 2232 
#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11
2233 
#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
 2233 
#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11
2234 
#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
 2234 
#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12
2235 
#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
 2235 
#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12
2236 
#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
 2236 
#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13
2237 
#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
 2237 
#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13
2238 
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
 2238 
#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14
2239 
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
 2239 
#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14
2240 
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
 2240 
#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2
2241 
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
 2241 
#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2
2242 
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
 2242 
 
2243 
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
 2243 
 
2244 
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
 2244 
#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15
2245 
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
 2245 
#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15
2246 
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
 2246 
#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16
2247 
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
 2247 
#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16
2248 
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
 2248 
#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17
2249 
#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
 2249 
#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17
2250 
#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
 2250 
#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC
2251 
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
 2251 
#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC
2252 
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
 2252 
#if defined(STM32H7)
2253 
#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
 2253 
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1
2254 
#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
 2254 
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1
2255 
#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
 2255 
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1
2256 
#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
 2256 
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1
2257 
#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
 2257 
#else
2258 
#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
 2258 
#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG
2259 
 
 2259 
#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG
2260 
#if defined (STM32F4)
 2260 
#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG
2261 
#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
 2261 
#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG
2262 
#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
 2262 
#endif /* STM32H7 */
2263 
#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
 2263 
#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT
2264 
#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
 2264 
#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT
2265 
#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
 2265 
#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT
2266 
#else
 2266 
#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT
2267 
#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
 2267 
#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT
2268 
#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
 2268 
#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT
2269 
#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
 2269 
#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1
2270 
#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
 2270 
#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1
2271 
#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
 2271 
#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1
2272 
#endif /* STM32F4 */
 2272 
#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1
2273 
/**
 2273 
#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2
2274 
  * @}
 2274 
#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2
2275 
  */
 2275 
 
2276 
 
 2276 
/**
2277 
 
 2277 
  * @}
2278 
/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
 2278 
  */
2279 
  * @{
 2279 
 
2280 
  */
 2280 
/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose
2281 
 
 2281 
  * @{
2282 
#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
 2282 
  */
2283 
#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
 2283 
#if defined(STM32F3)
2284 
 
 2284 
#define COMP_START                                       __HAL_COMP_ENABLE
2285 
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
 2285 
#define COMP_STOP                                        __HAL_COMP_DISABLE
2286 
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
 2286 
#define COMP_LOCK                                        __HAL_COMP_LOCK
2287 
 
 2287 
 
2288 
#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
 2288 
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
2289 
#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
 2289 
    defined(STM32F334x8) || defined(STM32F328xx)
2290 
#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
 2290 
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
2291 
#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
 2291 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
2292 
#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
 2292 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
2293 
#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
 2293 
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
2294 
#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
 2294 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
2295 
#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
 2295 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
2296 
#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
 2296 
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
2297 
#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
 2297 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
2298 
#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
 2298 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
2299 
#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
 2299 
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
2300 
#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
 2300 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
2301 
#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
 2301 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
2302 
#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
 2302 
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
2303 
#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
 2303 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
2304 
#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
 2304 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
2305 
#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
 2305 
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
2306 
#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
 2306 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
2307 
#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
 2307 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
2308 
#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
 2308 
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
2309 
#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
 2309 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
2310 
#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
 2310 
                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
2311 
#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
 2311 
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
2312 
#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
 2312 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
2313 
#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
 2313 
                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
2314 
#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
 2314 
# endif
2315 
#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
 2315 
# if defined(STM32F302xE) || defined(STM32F302xC)
2316 
#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
 2316 
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
2317 
#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
 2317 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
2318 
#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
 2318 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
2319 
#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
 2319 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
2320 
#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
 2320 
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
2321 
#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
 2321 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
2322 
#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
 2322 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
2323 
#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
 2323 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())
2324 
#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
 2324 
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
2325 
#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
 2325 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
2326 
#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
 2326 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
2327 
#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
 2327 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())
2328 
#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
 2328 
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
2329 
#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
 2329 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
2330 
#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
 2330 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
2331 
#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
 2331 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())
2332 
#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
 2332 
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
2333 
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
 2333 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
2334 
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
 2334 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
2335 
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
 2335 
                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())
2336 
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
 2336 
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
2337 
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
 2337 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
2338 
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
 2338 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
2339 
#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
 2339 
                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())
2340 
#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
 2340 
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
2341 
#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
 2341 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
2342 
#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
 2342 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
2343 
#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
 2343 
                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())
2344 
#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
 2344 
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
2345 
#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
 2345 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
2346 
#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
 2346 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
2347 
#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
 2347 
                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
2348 
#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
 2348 
# endif
2349 
#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
 2349 
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
2350 
#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
 2350 
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
2351 
#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
 2351 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
2352 
#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
 2352 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
2353 
#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
 2353 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
2354 
#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
 2354 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \
2355 
#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
 2355 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \
2356 
#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
 2356 
                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())
2357 
#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
 2357 
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
2358 
#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
 2358 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \
2359 
#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
 2359 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \
2360 
#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
 2360 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \
2361 
#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
 2361 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \
2362 
#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
 2362 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \
2363 
#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
 2363 
                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())
2364 
#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
 2364 
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
2365 
#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
 2365 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \
2366 
#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
 2366 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \
2367 
#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
 2367 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \
2368 
#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
 2368 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \
2369 
#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
 2369 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \
2370 
#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
 2370 
                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())
2371 
#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
 2371 
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
2372 
#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
 2372 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \
2373 
#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
 2373 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \
2374 
#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
 2374 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \
2375 
#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
 2375 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \
2376 
#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
 2376 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \
2377 
#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
 2377 
                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())
2378 
#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
 2378 
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
2379 
#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
 2379 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \
2380 
#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
 2380 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \
2381 
#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
 2381 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \
2382 
#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
 2382 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \
2383 
#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
 2383 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \
2384 
#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
 2384 
                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())
2385 
#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
 2385 
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
2386 
#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
 2386 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \
2387 
#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
 2387 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \
2388 
#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
 2388 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \
2389 
#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
 2389 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \
2390 
#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
 2390 
                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \
2391 
#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
 2391 
                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())
2392 
#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
 2392 
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
2393 
#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
 2393 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \
2394 
#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
 2394 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \
2395 
#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
 2395 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \
2396 
#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
 2396 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \
2397 
#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
 2397 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \
2398 
#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
 2398 
                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())
2399 
#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
 2399 
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
2400 
#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
 2400 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
2401 
#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
 2401 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \
2402 
#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
 2402 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
2403 
#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
 2403 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
2404 
#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
 2404 
                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
2405 
#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
 2405 
                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
2406 
#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
 2406 
# endif
2407 
#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
 2407 
# if defined(STM32F373xC) ||defined(STM32F378xx)
2408 
#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
 2408 
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
2409 
#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
 2409 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
2410 
#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
 2410 
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
2411 
#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
 2411 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
2412 
#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
 2412 
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
2413 
#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
 2413 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
2414 
#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
 2414 
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
2415 
#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
 2415 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
2416 
#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
 2416 
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
2417 
#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
 2417 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
2418 
#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
 2418 
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
2419 
#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
 2419 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
2420 
#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
 2420 
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
2421 
#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
 2421 
                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
2422 
#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
 2422 
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
2423 
#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
 2423 
                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
2424 
#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
 2424 
# endif
2425 
#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
 2425 
#else
2426 
#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
 2426 
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
2427 
#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
 2427 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
2428 
#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
 2428 
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
2429 
#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
 2429 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())
2430 
#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
 2430 
#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \
2431 
#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
 2431 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())
2432 
#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
 2432 
#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \
2433 
#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
 2433 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())
2434 
#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
 2434 
#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \
2435 
#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
 2435 
                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())
2436 
#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
 2436 
#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \
2437 
#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
 2437 
                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())
2438 
#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
 2438 
#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \
2439 
#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
 2439 
                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())
2440 
#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
 2440 
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
2441 
#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
 2441 
                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
2442 
#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
 2442 
#endif
2443 
#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
 2443 
 
2444 
#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
 2444 
#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE
2445 
#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
 2445 
 
2446 
#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
 2446 
#if defined(STM32L0) || defined(STM32L4)
2447 
#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
 2447 
/* Note: On these STM32 families, the only argument of this macro             */
2448 
#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
 2448 
/*       is COMP_FLAG_LOCK.                                                   */
2449 
#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
 2449 
/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */
2450 
#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
 2450 
/*       argument.                                                            */
2451 
#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
 2451 
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))
2452 
#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
 2452 
#endif
2453 
#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
 2453 
/**
2454 
#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
 2454 
  * @}
2455 
#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
 2455 
  */
2456 
#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
 2456 
 
2457 
#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
 2457 
#if defined(STM32L0) || defined(STM32L4)
2458 
#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
 2458 
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
2459 
#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
 2459 
  * @{
2460 
#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
 2460 
  */
2461 
#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
 2461 
#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
2462 
#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
 2462 
                                                  done into HAL_COMP_Init() */
2463 
#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
 2463 
#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is
2464 
#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
 2464 
                                                  done into HAL_COMP_Init() */
2465 
#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
 2465 
/**
2466 
#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
 2466 
  * @}
2467 
#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
 2467 
  */
2468 
#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
 2468 
#endif
2469 
#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
 2469 
 
2470 
#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
 2470 
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
2471 
#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
 2471 
  * @{
2472 
#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
 2472 
  */
2473 
#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
 2473 
 
2474 
#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
 2474 
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
2475 
#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
 2475 
                           ((WAVE) == DAC_WAVE_NOISE)|| \
2476 
#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
 2476 
                           ((WAVE) == DAC_WAVE_TRIANGLE))
2477 
#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
 2477 
 
2478 
#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
 2478 
/**
2479 
#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
 2479 
  * @}
2480 
#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
 2480 
  */
2481 
#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
 2481 
 
2482 
#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
 2482 
/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose
2483 
#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
 2483 
  * @{
2484 
#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
 2484 
  */
2485 
#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
 2485 
 
2486 
#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
 2486 
#define IS_WRPAREA          IS_OB_WRPAREA
2487 
#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
 2487 
#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM
2488 
#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
 2488 
#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM
2489 
#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
 2489 
#define IS_TYPEERASE        IS_FLASH_TYPEERASE
2490 
#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
 2490 
#define IS_NBSECTORS        IS_FLASH_NBSECTORS
2491 
#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
 2491 
#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE
2492 
#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
 2492 
 
2493 
#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
 2493 
/**
2494 
#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
 2494 
  * @}
2495 
#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
 2495 
  */
2496 
#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
 2496 
 
2497 
#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
 2497 
/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
2498 
#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
 2498 
  * @{
2499 
#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
 2499 
  */
2500 
#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
 2500 
 
2501 
#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
 2501 
#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
2502 
#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
 2502 
#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
2503 
#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
 2503 
#if defined(STM32F1)
2504 
#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
 2504 
#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
2505 
#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
 2505 
#else
2506 
#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
 2506 
#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
2507 
#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
 2507 
#endif /* STM32F1 */
2508 
#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
 2508 
#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
2509 
#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
 2509 
#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
2510 
#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
 2510 
#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
2511 
#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
 2511 
#define __HAL_I2C_SPEED                 I2C_SPEED
2512 
#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
 2512 
#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE
2513 
#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
 2513 
#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ
2514 
#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
 2514 
#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS
2515 
#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
 2515 
#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE
2516 
#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
 2516 
#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ
2517 
#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
 2517 
#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB
2518 
#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
 2518 
#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB
2519 
#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
 2519 
#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE
2520 
#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
 2520 
/**
2521 
#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
 2521 
  * @}
2522 
#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
 2522 
  */
2523 
#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
 2523 
 
2524 
#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
 2524 
/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
2525 
#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
 2525 
  * @{
2526 
#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
 2526 
  */
2527 
#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
 2527 
 
2528 
#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
 2528 
#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE
2529 
#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
 2529 
#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT
2530 
#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
 2530 
 
2531 
#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
 2531 
#if defined(STM32H7)
2532 
#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
 2532 
#define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG
2533 
#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
 2533 
#endif
2534 
#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
 2534 
 
2535 
#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
 2535 
/**
2536 
#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
 2536 
  * @}
2537 
#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
 2537 
  */
2538 
#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
 2538 
 
2539 
#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
 2539 
/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
2540 
#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
 2540 
  * @{
2541 
#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
 2541 
  */
2542 
#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
 2542 
 
2543 
#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
 2543 
#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE
2544 
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
 2544 
#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE
2545 
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
 2545 
 
2546 
 
 2546 
#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE
2547 
#if defined(STM32WB)
 2547 
#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION
2548 
#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
 2548 
#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE
2549 
#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
 2549 
#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION
2550 
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
 2550 
 
2551 
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
 2551 
#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE
2552 
#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
 2552 
 
2553 
#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
 2553 
 
2554 
#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
 2554 
/**
2555 
#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
 2555 
  * @}
2556 
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
 2556 
  */
2557 
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
 2557 
 
2558 
#define QSPI_IRQHandler QUADSPI_IRQHandler
 2558 
 
2559 
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
 2559 
/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose
2560 
 
 2560 
  * @{
2561 
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
 2561 
  */
2562 
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
 2562 
#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS
2563 
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
 2563 
#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS
2564 
#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
 2564 
/**
2565 
#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
 2565 
  * @}
2566 
#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
 2566 
  */
2567 
#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
 2567 
 
2568 
#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
 2568 
 
2569 
#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
 2569 
/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose
2570 
#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
 2570 
  * @{
2571 
#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
 2571 
  */
2572 
#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
 2572 
 
2573 
#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
 2573 
#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT
2574 
#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
 2574 
#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT
2575 
#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
 2575 
#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE
2576 
#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
 2576 
 
2577 
#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
 2577 
/**
2578 
#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
 2578 
  * @}
2579 
#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
 2579 
  */
2580 
#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
 2580 
 
2581 
#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
 2581 
 
2582 
#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
 2582 
/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
2583 
#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
 2583 
  * @{
2584 
#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
 2584 
  */
2585 
#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
 2585 
#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD
2586 
#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
 2586 
#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX
2587 
#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
 2587 
#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX
2588 
#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
 2588 
#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX
2589 
#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
 2589 
#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX
2590 
#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
 2590 
#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L
2591 
#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
 2591 
#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H
2592 
#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
 2592 
#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM
2593 
#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
 2593 
#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES
2594 
#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
 2594 
#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX
2595 
#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
 2595 
#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT
2596 
#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
 2596 
#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION
2597 
#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
 2597 
#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET
2598 
#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
 2598 
 
2599 
#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
 2599 
/**
2600 
#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
 2600 
  * @}
2601 
#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
 2601 
  */
2602 
#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
 2602 
 
2603 
#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
 2603 
 
2604 
#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
 2604 
/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose
2605 
#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
 2605 
  * @{
2606 
#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
 2606 
  */
2607 
#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
 2607 
#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT
2608 
#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
 2608 
#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT
2609 
#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
 2609 
#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
2610 
#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
 2610 
#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
2611 
#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
 2611 
#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
2612 
#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
 2612 
#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
2613 
#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
 2613 
#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE
2614 
#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
 2614 
#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE
2615 
#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
 2615 
#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE
2616 
#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
 2616 
#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE
2617 
#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
 2617 
#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE
2618 
#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
 2618 
#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE
2619 
#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
 2619 
#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine
2620 
#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
 2620 
#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine
2621 
#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
 2621 
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig
2622 
#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
 2622 
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig
2623 
#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
 2623 
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
2624 
#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
 2624 
                                                                      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
2625 
#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
 2625 
                                                                    } while(0)
2626 
#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
 2626 
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT
2627 
#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
 2627 
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT
2628 
#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
 2628 
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
2629 
#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
 2629 
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
2630 
#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
 2630 
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE
2631 
#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
 2631 
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
2632 
#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
 2632 
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
2633 
#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
 2633 
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
2634 
#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
 2634 
#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
2635 
#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
 2635 
                                                                      HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
2636 
#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
 2636 
                                                                    } while(0)
2637 
#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
 2637 
#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
2638 
#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
 2638 
                                                                      HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
2639 
#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
 2639 
                                                                    } while(0)
2640 
#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
 2640 
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention
2641 
#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
 2641 
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention
2642 
#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
 2642 
#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2
2643 
#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
 2643 
#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2
2644 
#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
 2644 
#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE
2645 
#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
 2645 
#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE
2646 
#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
 2646 
#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB
2647 
#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
 2647 
#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB
2648 
#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
 2648 
 
2649 
#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
 2649 
#if defined (STM32F4)
2650 
#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
 2650 
#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()
2651 
#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
 2651 
#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()
2652 
#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
 2652 
#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()
2653 
#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
 2653 
#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
2654 
#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
 2654 
#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
2655 
#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
 2655 
#else
2656 
#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
 2656 
#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG
2657 
#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
 2657 
#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT
2658 
#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
 2658 
#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT
2659 
#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
 2659 
#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT
2660 
#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
 2660 
#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG
2661 
#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
 2661 
#endif /* STM32F4 */
2662 
#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
 2662 
/**
2663 
#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
 2663 
  * @}
2664 
#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
 2664 
  */
2665 
#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
 2665 
 
2666 
#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
 2666 
 
2667 
#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
 2667 
/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
2668 
#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
 2668 
  * @{
2669 
#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
 2669 
  */
2670 
#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
 2670 
 
2671 
#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
 2671 
#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI
2672 
#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
 2672 
#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI
2673 
#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
 2673 
 
2674 
#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
 2674 
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
2675 
#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
 2675 
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
2676 
#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
 2676 
                                        HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
2677 
#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
 2677 
 
2678 
#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
 2678 
#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE
2679 
#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
 2679 
#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE
2680 
#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
 2680 
#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE
2681 
#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
 2681 
#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE
2682 
#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
 2682 
#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET
2683 
#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
 2683 
#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET
2684 
#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
 2684 
#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE
2685 
#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
 2685 
#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE
2686 
#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
 2686 
#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET
2687 
#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
 2687 
#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET
2688 
#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
 2688 
#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
2689 
#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
 2689 
#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
2690 
#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
 2690 
#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE
2691 
#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
 2691 
#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE
2692 
#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
 2692 
#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
2693 
#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
 2693 
#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
2694 
#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
 2694 
#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
2695 
#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
 2695 
#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE
2696 
#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
 2696 
#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET
2697 
#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
 2697 
#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET
2698 
#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
 2698 
#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
2699 
#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
 2699 
#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
2700 
#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
 2700 
#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
2701 
#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
 2701 
#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
2702 
#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
 2702 
#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
2703 
#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
 2703 
#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
2704 
#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
 2704 
#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE
2705 
#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
 2705 
#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
2706 
#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
 2706 
#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE
2707 
#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
 2707 
#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE
2708 
#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
 2708 
#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET
2709 
#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
 2709 
#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET
2710 
#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
 2710 
#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
2711 
#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
 2711 
#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
2712 
#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
 2712 
#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
2713 
#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
 2713 
#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
2714 
#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
 2714 
#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET
2715 
#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
 2715 
#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET
2716 
#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
 2716 
#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET
2717 
#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
 2717 
#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET
2718 
#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
 2718 
#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET
2719 
#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
 2719 
#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET
2720 
#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
 2720 
#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET
2721 
#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
 2721 
#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET
2722 
#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
 2722 
#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET
2723 
#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
 2723 
#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
2724 
#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
 2724 
#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
2725 
#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
 2725 
#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
2726 
#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
 2726 
#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
2727 
#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
 2727 
#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
2728 
#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
 2728 
#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
2729 
#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
 2729 
#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET
2730 
#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
 2730 
#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE
2731 
#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
 2731 
#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE
2732 
#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
 2732 
#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE
2733 
#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
 2733 
#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE
2734 
#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
 2734 
#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET
2735 
#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
 2735 
#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET
2736 
#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
 2736 
#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE
2737 
#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
 2737 
#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE
2738 
#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
 2738 
#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET
2739 
#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
 2739 
#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET
2740 
#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
 2740 
#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE
2741 
#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
 2741 
#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE
2742 
#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
 2742 
#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET
2743 
#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
 2743 
#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET
2744 
#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
 2744 
#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE
2745 
#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
 2745 
#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE
2746 
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
 2746 
#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE
2747 
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
 2747 
#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE
2748 
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
 2748 
#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET
2749 
#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
 2749 
#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET
2750 
#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
 2750 
#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE
2751 
#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
 2751 
#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE
2752 
#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
 2752 
#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET
2753 
#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
 2753 
#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET
2754 
#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
 2754 
#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE
2755 
#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
 2755 
#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE
2756 
#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
 2756 
#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE
2757 
#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
 2757 
#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE
2758 
#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
 2758 
#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET
2759 
#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
 2759 
#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET
2760 
#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
 2760 
#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE
2761 
#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
 2761 
#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE
2762 
#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
 2762 
#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET
2763 
#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
 2763 
#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET
2764 
#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
 2764 
#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE
2765 
#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
 2765 
#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE
2766 
#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
 2766 
#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE
2767 
#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
 2767 
#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE
2768 
#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
 2768 
#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET
2769 
#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
 2769 
#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET
2770 
#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
 2770 
#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE
2771 
#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
 2771 
#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE
2772 
#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
 2772 
#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET
2773 
#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
 2773 
#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET
2774 
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
 2774 
#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE
2775 
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
 2775 
#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE
2776 
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
 2776 
#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE
2777 
 
 2777 
#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE
2778 
#if defined(STM32H7)
 2778 
#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET
2779 
#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
 2779 
#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET
2780 
#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
 2780 
#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE
2781 
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
 2781 
#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE
2782 
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
 2782 
#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE
2783 
 
 2783 
#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE
2784 
#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
 2784 
#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET
2785 
#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
 2785 
#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET
2786 
 
 2786 
#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE
2787 
 
 2787 
#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
2788 
#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
 2788 
#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE
2789 
#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
 2789 
#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE
2790 
#endif
 2790 
#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET
2791 
 
 2791 
#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET
2792 
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
 2792 
#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE
2793 
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
 2793 
#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE
2794 
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
 2794 
#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET
2795 
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
 2795 
#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET
2796 
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
 2796 
#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE
2797 
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
 2797 
#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE
2798 
 
 2798 
#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE
2799 
#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
 2799 
#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE
2800 
#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
 2800 
#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE
2801 
#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
 2801 
#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE
2802 
#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
 2802 
#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE
2803 
#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
 2803 
#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE
2804 
#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
 2804 
#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE
2805 
#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
 2805 
#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE
2806 
#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
 2806 
#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET
2807 
#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
 2807 
#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET
2808 
#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
 2808 
#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE
2809 
#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
 2809 
#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE
2810 
#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
 2810 
#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET
2811 
#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
 2811 
#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET
2812 
#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
 2812 
#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE
2813 
#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
 2813 
#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE
2814 
#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
 2814 
#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE
2815 
#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
 2815 
#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE
2816 
#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
 2816 
#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE
2817 
#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
 2817 
#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE
2818 
#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
 2818 
#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET
2819 
 
 2819 
#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET
2820 
#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
 2820 
#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE
2821 
#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
 2821 
#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE
2822 
#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
 2822 
#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE
2823 
#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
 2823 
#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE
2824 
#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
 2824 
#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE
2825 
#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
 2825 
#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE
2826 
#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
 2826 
#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET
2827 
#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
 2827 
#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET
2828 
#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
 2828 
#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE
2829 
#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
 2829 
#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE
2830 
#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
 2830 
#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE
2831 
#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
 2831 
#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE
2832 
#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
 2832 
#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET
2833 
#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
 2833 
#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET
2834 
#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
 2834 
#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE
2835 
#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
 2835 
#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE
2836 
#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
 2836 
#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE
2837 
#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
 2837 
#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE
2838 
#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
 2838 
#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET
2839 
#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
 2839 
#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET
2840 
#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
 2840 
#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE
2841 
#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
 2841 
#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE
2842 
#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
 2842 
#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE
2843 
#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
 2843 
#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE
2844 
#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
 2844 
#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET
2845 
#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
 2845 
#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET
2846 
#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
 2846 
#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE
2847 
#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
 2847 
#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE
2848 
#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
 2848 
#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE
2849 
#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
 2849 
#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE
2850 
#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
 2850 
#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET
2851 
#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
 2851 
#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET
2852 
#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
 2852 
#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE
2853 
#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
 2853 
#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE
2854 
#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
 2854 
#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE
2855 
#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
 2855 
#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE
2856 
#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
 2856 
#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET
2857 
#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
 2857 
#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET
2858 
#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
 2858 
#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE
2859 
#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
 2859 
#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE
2860 
#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
 2860 
#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE
2861 
#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
 2861 
#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE
2862 
#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
 2862 
#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET
2863 
#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
 2863 
#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET
2864 
#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
 2864 
#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE
2865 
#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
 2865 
#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE
2866 
#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
 2866 
#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE
2867 
#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
 2867 
#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE
2868 
#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
 2868 
#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET
2869 
#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
 2869 
#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET
2870 
#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
 2870 
#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE
2871 
#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
 2871 
#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE
2872 
#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
 2872 
#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE
2873 
#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
 2873 
#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE
2874 
#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
 2874 
#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET
2875 
#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
 2875 
#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET
2876 
#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
 2876 
#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE
2877 
#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
 2877 
#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE
2878 
#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
 2878 
#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE
2879 
#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
 2879 
#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE
2880 
#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
 2880 
#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET
2881 
#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
 2881 
#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET
2882 
#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
 2882 
#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE
2883 
#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
 2883 
#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE
2884 
#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
 2884 
#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE
2885 
#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
 2885 
#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE
2886 
#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
 2886 
#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET
2887 
#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
 2887 
#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET
2888 
#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
 2888 
#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE
2889 
#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
 2889 
#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE
2890 
#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
 2890 
#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE
2891 
#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
 2891 
#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE
2892 
#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
 2892 
#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET
2893 
#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
 2893 
#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET
2894 
#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
 2894 
#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE
2895 
#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
 2895 
#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE
2896 
#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
 2896 
#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE
2897 
#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
 2897 
#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE
2898 
#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
 2898 
#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET
2899 
#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
 2899 
#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET
2900 
#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
 2900 
#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE
2901 
#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
 2901 
#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE
2902 
#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
 2902 
#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE
2903 
#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
 2903 
#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE
2904 
#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
 2904 
#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET
2905 
#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
 2905 
#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET
2906 
#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
 2906 
#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE
2907 
#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
 2907 
#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE
2908 
#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
 2908 
#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE
2909 
#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
 2909 
#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE
2910 
#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
 2910 
#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET
2911 
#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
 2911 
#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET
2912 
#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
 2912 
#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE
2913 
#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
 2913 
#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE
2914 
#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
 2914 
#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE
2915 
#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
 2915 
#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE
2916 
#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
 2916 
#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET
2917 
#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
 2917 
#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET
2918 
#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
 2918 
#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE
2919 
#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
 2919 
#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE
2920 
#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
 2920 
#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE
2921 
#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
 2921 
#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE
2922 
#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
 2922 
#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET
2923 
#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
 2923 
#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET
2924 
#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
 2924 
#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE
2925 
#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
 2925 
#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE
2926 
#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
 2926 
#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE
2927 
#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
 2927 
#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE
2928 
#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
 2928 
#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET
2929 
#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
 2929 
#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET
2930 
#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
 2930 
#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE
2931 
#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
 2931 
#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE
2932 
#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
 2932 
#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE
2933 
#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
 2933 
#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
2934 
#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
 2934 
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
2935 
#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
 2935 
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
2936 
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
 2936 
 
2937 
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
 2937 
#if defined(STM32WB)
2938 
#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
 2938 
#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE
2939 
#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
 2939 
#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE
2940 
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
 2940 
#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
2941 
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
 2941 
#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
2942 
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
 2942 
#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET
2943 
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
 2943 
#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET
2944 
#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
 2944 
#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED
2945 
#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
 2945 
#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED
2946 
#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
 2946 
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
2947 
#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
 2947 
#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
2948 
#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
 2948 
#define QSPI_IRQHandler QUADSPI_IRQHandler
2949 
#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
 2949 
#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
2950 
#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
 2950 
 
2951 
#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
 2951 
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
2952 
#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
 2952 
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
2953 
#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
 2953 
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
2954 
#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
 2954 
#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE
2955 
#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
 2955 
#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET
2956 
#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
 2956 
#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET
2957 
#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
 2957 
#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE
2958 
#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
 2958 
#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE
2959 
#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
 2959 
#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE
2960 
#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
 2960 
#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE
2961 
#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
 2961 
#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET
2962 
#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
 2962 
#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET
2963 
#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
 2963 
#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE
2964 
#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
 2964 
#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE
2965 
#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
 2965 
#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE
2966 
#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
 2966 
#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE
2967 
 
 2967 
#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET
2968 
/* alias define maintained for legacy */
 2968 
#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET
2969 
#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
 2969 
#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE
2970 
#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
 2970 
#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE
2971 
 
 2971 
#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE
2972 
#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
 2972 
#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE
2973 
#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
 2973 
#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE
2974 
#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
 2974 
#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE
2975 
#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
 2975 
#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET
2976 
#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
 2976 
#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET
2977 
#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
 2977 
#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE
2978 
#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
 2978 
#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE
2979 
#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
 2979 
#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE
2980 
#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
 2980 
#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE
2981 
#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
 2981 
#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET
2982 
#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
 2982 
#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET
2983 
#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
 2983 
#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE
2984 
#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
 2984 
#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE
2985 
#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
 2985 
#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE
2986 
#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
 2986 
#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE
2987 
#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
 2987 
#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET
2988 
#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
 2988 
#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET
2989 
#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
 2989 
#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE
2990 
#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
 2990 
#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE
2991 
#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
 2991 
#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE
2992 
 
 2992 
#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE
2993 
#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
 2993 
#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET
2994 
#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
 2994 
#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET
2995 
#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
 2995 
#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE
2996 
#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
 2996 
#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE
2997 
#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
 2997 
#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE
2998 
#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
 2998 
#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE
2999 
#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
 2999 
#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE
3000 
#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
 3000 
#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE
3001 
#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
 3001 
#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE
3002 
#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
 3002 
#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE
3003 
#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
 3003 
#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE
3004 
#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
 3004 
#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE
3005 
#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
 3005 
#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET
3006 
#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
 3006 
#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET
3007 
#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
 3007 
#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE
3008 
#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
 3008 
#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE
3009 
#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
 3009 
#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE
3010 
#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
 3010 
#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE
3011 
#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
 3011 
#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET
3012 
#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
 3012 
#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET
3013 
 
 3013 
#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE
3014 
#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
 3014 
#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE
3015 
#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
 3015 
#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE
3016 
#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
 3016 
#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE
3017 
#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
 3017 
#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET
3018 
#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
 3018 
#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET
3019 
#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
 3019 
#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE
3020 
#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
 3020 
#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE
3021 
#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
 3021 
#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET
3022 
#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
 3022 
#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET
3023 
#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
 3023 
#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE
3024 
#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
 3024 
#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE
3025 
#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
 3025 
#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET
3026 
#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
 3026 
#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET
3027 
#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
 3027 
#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE
3028 
#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
 3028 
#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE
3029 
#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
 3029 
#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET
3030 
#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
 3030 
#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET
3031 
#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
 3031 
#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE
3032 
#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
 3032 
#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE
3033 
#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
 3033 
#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET
3034 
#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
 3034 
#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET
3035 
#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
 3035 
#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE
3036 
#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
 3036 
#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE
3037 
#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
 3037 
#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET
3038 
#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
 3038 
#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET
3039 
#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
 3039 
#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE
3040 
#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
 3040 
#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE
3041 
#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
 3041 
#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE
3042 
#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
 3042 
#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE
3043 
#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
 3043 
#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET
3044 
#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
 3044 
#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET
3045 
#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
 3045 
#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE
3046 
#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
 3046 
#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE
3047 
#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
 3047 
#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE
3048 
#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
 3048 
#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE
3049 
#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
 3049 
#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET
3050 
#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
 3050 
#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET
3051 
#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
 3051 
#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE
3052 
#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
 3052 
#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE
3053 
#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
 3053 
#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE
3054 
#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
 3054 
#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE
3055 
#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
 3055 
#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET
3056 
#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
 3056 
#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET
3057 
#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
 3057 
#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE
3058 
#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
 3058 
#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE
3059 
#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
 3059 
#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE
3060 
#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
 3060 
#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE
3061 
#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
 3061 
#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET
3062 
#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
 3062 
#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET
3063 
#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
 3063 
#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE
3064 
#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
 3064 
#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE
3065 
#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
 3065 
#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE
3066 
#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
 3066 
#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE
3067 
#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
 3067 
#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET
3068 
#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
 3068 
#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET
3069 
#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
 3069 
#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE
3070 
#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
 3070 
#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE
3071 
#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
 3071 
#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE
3072 
#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
 3072 
#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE
3073 
#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
 3073 
#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET
3074 
#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
 3074 
#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET
3075 
#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
 3075 
#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE
3076 
#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
 3076 
#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE
3077 
#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
 3077 
#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE
3078 
#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
 3078 
#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE
3079 
#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
 3079 
#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET
3080 
#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
 3080 
#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET
3081 
#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
 3081 
#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE
3082 
#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
 3082 
#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE
3083 
#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
 3083 
#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE
3084 
#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
 3084 
#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE
3085 
#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
 3085 
#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET
3086 
#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
 3086 
#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET
3087 
#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
 3087 
#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE
3088 
#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
 3088 
#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE
3089 
#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
 3089 
#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE
3090 
#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
 3090 
#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE
3091 
#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
 3091 
#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET
3092 
#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
 3092 
#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET
3093 
#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
 3093 
#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE
3094 
#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
 3094 
#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE
3095 
#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
 3095 
#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE
3096 
#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
 3096 
#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE
3097 
#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
 3097 
#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET
3098 
#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
 3098 
#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET
3099 
#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
 3099 
#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE
3100 
#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
 3100 
#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE
3101 
#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
 3101 
#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET
3102 
#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
 3102 
#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET
3103 
#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
 3103 
#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE
3104 
#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
 3104 
#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE
3105 
#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
 3105 
#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE
3106 
#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
 3106 
#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE
3107 
#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
 3107 
#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET
3108 
#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
 3108 
#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET
3109 
#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
 3109 
#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
3110 
#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
 3110 
#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
3111 
#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
 3111 
#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
3112 
#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
 3112 
#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
3113 
#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
 3113 
#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
3114 
#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
 3114 
#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
3115 
#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
 3115 
#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
3116 
#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
 3116 
#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
3117 
#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
 3117 
#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
3118 
#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
 3118 
#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
3119 
#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
 3119 
#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
3120 
#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
 3120 
#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
3121 
#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
 3121 
#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE
3122 
#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
 3122 
#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE
3123 
#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
 3123 
#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE
3124 
#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
 3124 
#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE
3125 
#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
 3125 
#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET
3126 
#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
 3126 
#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET
3127 
#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
 3127 
#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE
3128 
#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
 3128 
#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE
3129 
#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
 3129 
#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE
3130 
 
 3130 
#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE
3131 
#if defined(STM32L1)
 3131 
#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET
3132 
#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
 3132 
#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET
3133 
#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
 3133 
#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE
3134 
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
 3134 
#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE
3135 
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
 3135 
#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE
3136 
#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
 3136 
#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE
3137 
#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
 3137 
#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET
3138 
#endif /* STM32L1 */
 3138 
#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET
3139 
 
 3139 
#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE
3140 
#if defined(STM32F4)
 3140 
#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE
3141 
#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
 3141 
#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE
3142 
#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
 3142 
#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE
3143 
#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
 3143 
#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET
3144 
#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
 3144 
#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET
3145 
#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
 3145 
#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE
3146 
#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
 3146 
#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE
3147 
#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
 3147 
#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE
3148 
#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
 3148 
#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE
3149 
#define Sdmmc1ClockSelection               SdioClockSelection
 3149 
#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET
3150 
#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
 3150 
#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET
3151 
#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
 3151 
#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE
3152 
#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
 3152 
#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE
3153 
#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
 3153 
#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET
3154 
#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
 3154 
#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET
3155 
#endif
 3155 
#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE
3156 
 
 3156 
#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE
3157 
#if defined(STM32F7) || defined(STM32L4)
 3157 
#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET
3158 
#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
 3158 
#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET
3159 
#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
 3159 
#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE
3160 
#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
 3160 
#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE
3161 
#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
 3161 
#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET
3162 
#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
 3162 
#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE
3163 
#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
 3163 
#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE
3164 
#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
 3164 
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
3165 
#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
 3165 
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
3166 
#define SdioClockSelection                 Sdmmc1ClockSelection
 3166 
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
3167 
#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
 3167 
 
3168 
#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
 3168 
#if defined(STM32H7)
3169 
#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
 3169 
#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE
3170 
#endif
 3170 
#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE
3171 
 
 3171 
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
3172 
#if defined(STM32F7)
 3172 
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
3173 
#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
 3173 
 
3174 
#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
 3174 
#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/
3175 
#endif
 3175 
#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
3176 
 
 3176 
 
3177 
#if defined(STM32H7)
 3177 
 
3178 
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
 3178 
#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED
3179 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
 3179 
#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED
3180 
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
 3180 
#define  RCC_SPI4CLKSOURCE_D2PCLK1       RCC_SPI4CLKSOURCE_D2PCLK2
3181 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
 3181 
#define  RCC_SPI5CLKSOURCE_D2PCLK1       RCC_SPI5CLKSOURCE_D2PCLK2
3182 
#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
 3182 
#define  RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_D2PCLK2
3183 
#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
 3183 
#define  RCC_SPI45CLKSOURCE_CDPCLK1      RCC_SPI45CLKSOURCE_CDPCLK2
3184 
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
 3184 
#define  RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_PCLK2
3185 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
 3185 
#endif
3186 
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
 3186 
 
3187 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
 3187 
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
3188 
 
 3188 
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
3189 
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
 3189 
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
3190 
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
 3190 
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
3191 
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
 3191 
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
3192 
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
 3192 
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
3193 
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
 3193 
 
3194 
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
 3194 
#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE
3195 
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
 3195 
#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE
3196 
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
 3196 
#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET
3197 
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
 3197 
#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET
3198 
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
 3198 
#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE
3199 
#endif
 3199 
#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE
3200 
 
 3200 
#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE
3201 
#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
 3201 
#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE
3202 
#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
 3202 
#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET
3203 
 
 3203 
#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET
3204 
#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
 3204 
#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE
3205 
 
 3205 
#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE
3206 
#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
 3206 
#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE
3207 
#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
 3207 
#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE
3208 
#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
 3208 
#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE
3209 
#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
 3209 
#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE
3210 
#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
 3210 
#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET
3211 
 
 3211 
#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET
3212 
#define RCC_IT_HSI14                RCC_IT_HSI14RDY
 3212 
#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE
3213 
 
 3213 
#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE
3214 
#define RCC_IT_CSSLSE               RCC_IT_LSECSS
 3214 
 
3215 
#define RCC_IT_CSSHSE               RCC_IT_CSS
 3215 
#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET
3216 
 
 3216 
#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
3217 
#define RCC_PLLMUL_3                RCC_PLL_MUL3
 3217 
#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE
3218 
#define RCC_PLLMUL_4                RCC_PLL_MUL4
 3218 
#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE
3219 
#define RCC_PLLMUL_6                RCC_PLL_MUL6
 3219 
#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE
3220 
#define RCC_PLLMUL_8                RCC_PLL_MUL8
 3220 
#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE
3221 
#define RCC_PLLMUL_12               RCC_PLL_MUL12
 3221 
#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
3222 
#define RCC_PLLMUL_16               RCC_PLL_MUL16
 3222 
#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
3223 
#define RCC_PLLMUL_24               RCC_PLL_MUL24
 3223 
#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
3224 
#define RCC_PLLMUL_32               RCC_PLL_MUL32
 3224 
#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
3225 
#define RCC_PLLMUL_48               RCC_PLL_MUL48
 3225 
#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
3226 
 
 3226 
#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
3227 
#define RCC_PLLDIV_2                RCC_PLL_DIV2
 3227 
#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
3228 
#define RCC_PLLDIV_3                RCC_PLL_DIV3
 3228 
#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
3229 
#define RCC_PLLDIV_4                RCC_PLL_DIV4
 3229 
#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
3230 
 
 3230 
#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
3231 
#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
 3231 
#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE
3232 
#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
 3232 
#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE
3233 
#define RCC_MCO_NODIV               RCC_MCODIV_1
 3233 
#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE
3234 
#define RCC_MCO_DIV1                RCC_MCODIV_1
 3234 
#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET
3235 
#define RCC_MCO_DIV2                RCC_MCODIV_2
 3235 
#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET
3236 
#define RCC_MCO_DIV4                RCC_MCODIV_4
 3236 
#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE
3237 
#define RCC_MCO_DIV8                RCC_MCODIV_8
 3237 
#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE
3238 
#define RCC_MCO_DIV16               RCC_MCODIV_16
 3238 
#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE
3239 
#define RCC_MCO_DIV32               RCC_MCODIV_32
 3239 
#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE
3240 
#define RCC_MCO_DIV64               RCC_MCODIV_64
 3240 
#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE
3241 
#define RCC_MCO_DIV128              RCC_MCODIV_128
 3241 
#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET
3242 
#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
 3242 
#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET
3243 
#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
 3243 
#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
3244 
#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
 3244 
#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
3245 
#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
 3245 
#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE
3246 
#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
 3246 
#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE
3247 
#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
 3247 
#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET
3248 
#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
 3248 
#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET
3249 
#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
 3249 
#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
3250 
#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
 3250 
#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
3251 
#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
 3251 
#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE
3252 
#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
 3252 
#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE
3253 
 
 3253 
#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET
3254 
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
 3254 
#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET
3255 
#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
 3255 
#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
3256 
#else
 3256 
#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
3257 
#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
 3257 
#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
3258 
#endif
 3258 
#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
3259 
 
 3259 
#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
3260 
#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
 3260 
#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
3261 
#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
 3261 
#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
3262 
#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
 3262 
#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
3263 
#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
 3263 
#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
3264 
#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
 3264 
#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
3265 
#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
 3265 
#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
3266 
#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
 3266 
#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
3267 
#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
 3267 
#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
3268 
 
 3268 
#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE
3269 
#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
 3269 
#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE
3270 
#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
 3270 
#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
3271 
#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
 3271 
#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
3272 
#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
 3272 
#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
3273 
#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
 3273 
#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
3274 
#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
 3274 
#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE
3275 
#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
 3275 
#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE
3276 
#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
 3276 
#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET
3277 
#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
 3277 
#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET
3278 
#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
 3278 
#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE
3279 
#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
 3279 
#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE
3280 
#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
 3280 
#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE
3281 
#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
 3281 
#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE
3282 
#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
 3282 
#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET
3283 
#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
 3283 
#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET
3284 
#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
 3284 
#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
3285 
#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
 3285 
#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
3286 
#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
 3286 
#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE
3287 
#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
 3287 
#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE
3288 
#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
 3288 
#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET
3289 
#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
 3289 
#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET
3290 
#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
 3290 
#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
3291 
#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
 3291 
#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
3292 
#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
 3292 
#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE
3293 
#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
 3293 
#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE
3294 
#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
 3294 
#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET
3295 
#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
 3295 
#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET
3296 
#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
 3296 
#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
3297 
#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
 3297 
#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
3298 
#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
 3298 
#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE
3299 
#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
 3299 
#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE
3300 
#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
 3300 
#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET
3301 
 
 3301 
#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
3302 
#define CR_HSION_BB            RCC_CR_HSION_BB
 3302 
#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
3303 
#define CR_CSSON_BB            RCC_CR_CSSON_BB
 3303 
#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE
3304 
#define CR_PLLON_BB            RCC_CR_PLLON_BB
 3304 
#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE
3305 
#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
 3305 
#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE
3306 
#define CR_MSION_BB            RCC_CR_MSION_BB
 3306 
#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE
3307 
#define CSR_LSION_BB           RCC_CSR_LSION_BB
 3307 
#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET
3308 
#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
 3308 
#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET
3309 
#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
 3309 
#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
3310 
#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
 3310 
#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
3311 
#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
 3311 
#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE
3312 
#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
 3312 
#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE
3313 
#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
 3313 
#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET
3314 
#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
 3314 
#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET
3315 
#define CR_HSEON_BB            RCC_CR_HSEON_BB
 3315 
#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE
3316 
#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
 3316 
#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE
3317 
#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
 3317 
#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE
3318 
#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
 3318 
#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE
3319 
 
 3319 
#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET
3320 
#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
 3320 
#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET
3321 
#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
 3321 
#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE
3322 
#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
 3322 
#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE
3323 
#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
 3323 
#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
3324 
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
 3324 
#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
3325 
 
 3325 
#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
3326 
#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
 3326 
#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
3327 
 
 3327 
#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
3328 
#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
 3328 
#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
3329 
#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
 3329 
#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
3330 
 
 3330 
#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
3331 
#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
 3331 
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
3332 
#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
 3332 
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
3333 
#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
 3333 
#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET
3334 
#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
 3334 
#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET
3335 
#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
 3335 
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
3336 
#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
 3336 
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
3337 
 
 3337 
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
3338 
#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
 3338 
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
3339 
#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
 3339 
#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
3340 
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
 3340 
#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
3341 
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
 3341 
#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
3342 
#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
 3342 
#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE
3343 
#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
 3343 
#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE
3344 
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
 3344 
#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
3345 
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
 3345 
#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
3346 
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
 3346 
#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
3347 
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
 3347 
#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
3348 
#define DfsdmClockSelection         Dfsdm1ClockSelection
 3348 
#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET
3349 
#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
 3349 
#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET
3350 
#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
 3350 
#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
3351 
#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
 3351 
#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
3352 
#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
 3352 
#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET
3353 
#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
 3353 
#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET
3354 
#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
 3354 
#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
3355 
#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
 3355 
#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
3356 
#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
 3356 
#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE
3357 
#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
 3357 
#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE
3358 
 
 3358 
#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET
3359 
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
 3359 
#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET
3360 
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
 3360 
#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE
3361 
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
 3361 
#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE
3362 
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
 3362 
 
3363 
#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
 3363 
/* alias define maintained for legacy */
3364 
#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
 3364 
#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET
3365 
#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
 3365 
#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET
3366 
 
 3366 
 
3367 
/**
 3367 
#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE
3368 
  * @}
 3368 
#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE
3369 
  */
 3369 
#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE
3370 
 
 3370 
#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE
3371 
/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
 3371 
#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE
3372 
  * @{
 3372 
#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE
3373 
  */
 3373 
#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE
3374 
#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
 3374 
#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE
3375 
 
 3375 
#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE
3376 
/**
 3376 
#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE
3377 
  * @}
 3377 
#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE
3378 
  */
 3378 
#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE
3379 
 
 3379 
#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE
3380 
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
 3380 
#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE
3381 
  * @{
 3381 
#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE
3382 
  */
 3382 
#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE
3383 
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL)
 3383 
#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE
3384 
#else
 3384 
#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE
3385 
#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
 3385 
#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE
3386 
#endif
 3386 
#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE
3387 
#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
 3387 
 
3388 
#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
 3388 
#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET
3389 
 
 3389 
#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET
3390 
#if defined (STM32F1)
 3390 
#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET
3391 
#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
 3391 
#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET
3392 
 
 3392 
#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET
3393 
#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
 3393 
#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET
3394 
 
 3394 
#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET
3395 
#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
 3395 
#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET
3396 
 
 3396 
#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET
3397 
#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
 3397 
#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET
3398 
 
 3398 
#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET
3399 
#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
 3399 
#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET
3400 
#else
 3400 
#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET
3401 
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
 3401 
#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET
3402 
                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
 3402 
#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET
3403 
                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
 3403 
#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET
3404 
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
 3404 
#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET
3405 
                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
 3405 
#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET
3406 
                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
 3406 
#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET
3407 
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
 3407 
#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET
3408 
                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
 3408 
 
3409 
                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
 3409 
#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED
3410 
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
 3410 
#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED
3411 
                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
 3411 
#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED
3412 
                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
 3412 
#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED
3413 
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
 3413 
#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED
3414 
                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
 3414 
#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED
3415 
                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
 3415 
#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED
3416 
#endif   /* STM32F1 */
 3416 
#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED
3417 
 
 3417 
#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED
3418 
#define IS_ALARM                                  IS_RTC_ALARM
 3418 
#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED
3419 
#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
 3419 
#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED
3420 
#define IS_TAMPER                                 IS_RTC_TAMPER
 3420 
#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED
3421 
#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
 3421 
#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED
3422 
#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
 3422 
#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED
3423 
#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
 3423 
#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED
3424 
#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
 3424 
#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED
3425 
#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
 3425 
#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED
3426 
#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
 3426 
#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED
3427 
#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
 3427 
#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED
3428 
#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
 3428 
#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED
3429 
#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
 3429 
#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED
3430 
#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
 3430 
#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED
3431 
#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
 3431 
#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED
3432 
 
 3432 
#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED
3433 
#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
 3433 
#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED
3434 
#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
 3434 
#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED
3435 
 
 3435 
#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED
3436 
/**
 3436 
#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED
3437 
  * @}
 3437 
#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED
3438 
  */
 3438 
#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED
3439 
 
 3439 
#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED
3440 
/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose
 3440 
#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED
3441 
  * @{
 3441 
#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED
3442 
  */
 3442 
#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED
3443 
 
 3443 
#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED
3444 
#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
 3444 
#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED
3445 
#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
 3445 
#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED
3446 
 
 3446 
#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED
3447 
#if defined(STM32F4) || defined(STM32F2)
 3447 
#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED
3448 
#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
 3448 
#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED
3449 
#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
 3449 
#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED
3450 
#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
 3450 
#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED
3451 
#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
 3451 
#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED
3452 
#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
 3452 
#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED
3453 
#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
 3453 
#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED
3454 
#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
 3454 
#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED
3455 
#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
 3455 
#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED
3456 
#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
 3456 
#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED
3457 
#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
 3457 
#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED
3458 
#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
 3458 
#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED
3459 
#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
 3459 
#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED
3460 
#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
 3460 
#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED
3461 
#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
 3461 
#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED
3462 
#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
 3462 
#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED
3463 
#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
 3463 
#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED
3464 
#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
 3464 
#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED
3465 
#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
 3465 
#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED
3466 
#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
 3466 
#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED
3467 
#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
 3467 
#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED
3468 
/* alias CMSIS */
 3468 
#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED
3469 
#define  SDMMC1_IRQn                SDIO_IRQn
 3469 
#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED
3470 
#define  SDMMC1_IRQHandler          SDIO_IRQHandler
 3470 
#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED
3471 
#endif
 3471 
#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED
3472 
 
 3472 
#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED
3473 
#if defined(STM32F7) || defined(STM32L4)
 3473 
#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED
3474 
#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
 3474 
#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED
3475 
#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
 3475 
#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED
3476 
#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
 3476 
#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED
3477 
#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
 3477 
#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED
3478 
#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
 3478 
#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED
3479 
#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
 3479 
#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED
3480 
#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
 3480 
#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED
3481 
#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
 3481 
#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED
3482 
#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
 3482 
#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED
3483 
#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
 3483 
#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED
3484 
#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
 3484 
#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED
3485 
#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
 3485 
#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED
3486 
#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
 3486 
#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED
3487 
#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
 3487 
#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED
3488 
#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
 3488 
#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED
3489 
#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
 3489 
#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED
3490 
#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
 3490 
#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED
3491 
#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
 3491 
#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED
3492 
#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
 3492 
#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED
3493 
#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
 3493 
#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED
3494 
/* alias CMSIS for compatibilities */
 3494 
#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED
3495 
#define  SDIO_IRQn                  SDMMC1_IRQn
 3495 
#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED
3496 
#define  SDIO_IRQHandler            SDMMC1_IRQHandler
 3496 
#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED
3497 
#endif
 3497 
#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED
3498 
 
 3498 
#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED
3499 
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
 3499 
#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED
3500 
#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
 3500 
#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED
3501 
#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
 3501 
#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED
3502 
#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
 3502 
#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED
3503 
#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
 3503 
#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED
3504 
#endif
 3504 
#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED
3505 
 
 3505 
#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED
3506 
#if defined(STM32H7) || defined(STM32L5)
 3506 
#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED
3507 
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
 3507 
#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED
3508 
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
 3508 
#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED
3509 
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
 3509 
#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED
3510 
#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
 3510 
#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED
3511 
#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
 3511 
#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED
3512 
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
 3512 
#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED
3513 
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
 3513 
#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED
3514 
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
 3514 
#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED
3515 
#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
 3515 
#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED
3516 
#endif
 3516 
#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED
3517 
/**
 3517 
#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED
3518 
  * @}
 3518 
#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED
3519 
  */
 3519 
#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED
3520 
 
 3520 
#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED
3521 
/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
 3521 
#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED
3522 
  * @{
 3522 
#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED
3523 
  */
 3523 
#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED
3524 
 
 3524 
#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED
3525 
#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
 3525 
 
3526 
#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
 3526 
#if defined(STM32L1)
3527 
#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
 3527 
#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE
3528 
#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
 3528 
#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE
3529 
#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
 3529 
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE
3530 
#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
 3530 
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE
3531 
 
 3531 
#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET
3532 
#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
 3532 
#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET
3533 
#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
 3533 
#endif /* STM32L1 */
3534 
 
 3534 
 
3535 
#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
 3535 
#if defined(STM32F4)
3536 
 
 3536 
#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET
3537 
/**
 3537 
#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET
3538 
  * @}
 3538 
#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
3539 
  */
 3539 
#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
3540 
 
 3540 
#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE
3541 
/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
 3541 
#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE
3542 
  * @{
 3542 
#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED
3543 
  */
 3543 
#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED
3544 
#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
 3544 
#define Sdmmc1ClockSelection               SdioClockSelection
3545 
#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
 3545 
#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO
3546 
#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
 3546 
#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48
3547 
#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
 3547 
#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK
3548 
#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
 3548 
#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG
3549 
#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
 3549 
#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE
3550 
#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
 3550 
#endif
3551 
#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
 3551 
 
3552 
/**
 3552 
#if defined(STM32F7) || defined(STM32L4)
3553 
  * @}
 3553 
#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET
3554 
  */
 3554 
#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET
3555 
 
 3555 
#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE
3556 
/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
 3556 
#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE
3557 
  * @{
 3557 
#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE
3558 
  */
 3558 
#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE
3559 
 
 3559 
#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED
3560 
#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
 3560 
#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED
3561 
#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
 3561 
#define SdioClockSelection                 Sdmmc1ClockSelection
3562 
#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
 3562 
#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1
3563 
 
 3563 
#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG
3564 
/**
 3564 
#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE
3565 
  * @}
 3565 
#endif
3566 
  */
 3566 
 
3567 
 
 3567 
#if defined(STM32F7)
3568 
/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
 3568 
#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48
3569 
  * @{
 3569 
#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK
3570 
  */
 3570 
#endif
3571 
 
 3571 
 
3572 
#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
 3572 
#if defined(STM32H7)
3573 
#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
 3573 
#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
3574 
#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
 3574 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
3575 
#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
 3575 
#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
3576 
 
 3576 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
3577 
#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
 3577 
#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
3578 
 
 3578 
#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
3579 
#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
 3579 
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
3580 
#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
 3580 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
3581 
 
 3581 
#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
3582 
/**
 3582 
#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
3583 
  * @}
 3583 
 
3584 
  */
 3584 
#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
3585 
 
 3585 
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
3586 
 
 3586 
#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
3587 
/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
 3587 
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
3588 
  * @{
 3588 
#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
3589 
  */
 3589 
#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
3590 
 
 3590 
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
3591 
#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
 3591 
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
3592 
#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
 3592 
#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
3593 
#define __USART_ENABLE                  __HAL_USART_ENABLE
 3593 
#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
3594 
#define __USART_DISABLE                 __HAL_USART_DISABLE
 3594 
#endif
3595 
 
 3595 
 
3596 
#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
 3596 
#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG
3597 
#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
 3597 
#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG
3598 
 
 3598 
 
3599 
/**
 3599 
#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE
3600 
  * @}
 3600 
 
3601 
  */
 3601 
#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE
3602 
 
 3602 
#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE
3603 
/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
 3603 
#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK
3604 
  * @{
 3604 
#define IS_RCC_HCLK_DIV             IS_RCC_PCLK
3605 
  */
 3605 
#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK
3606 
#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
 3606 
 
3607 
 
 3607 
#define RCC_IT_HSI14                RCC_IT_HSI14RDY
3608 
#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
 3608 
 
3609 
#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
 3609 
#define RCC_IT_CSSLSE               RCC_IT_LSECSS
3610 
#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
 3610 
#define RCC_IT_CSSHSE               RCC_IT_CSS
3611 
#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
 3611 
 
3612 
 
 3612 
#define RCC_PLLMUL_3                RCC_PLL_MUL3
3613 
#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
 3613 
#define RCC_PLLMUL_4                RCC_PLL_MUL4
3614 
#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
 3614 
#define RCC_PLLMUL_6                RCC_PLL_MUL6
3615 
#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
 3615 
#define RCC_PLLMUL_8                RCC_PLL_MUL8
3616 
#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
 3616 
#define RCC_PLLMUL_12               RCC_PLL_MUL12
3617 
 
 3617 
#define RCC_PLLMUL_16               RCC_PLL_MUL16
3618 
#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
 3618 
#define RCC_PLLMUL_24               RCC_PLL_MUL24
3619 
#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
 3619 
#define RCC_PLLMUL_32               RCC_PLL_MUL32
3620 
#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
 3620 
#define RCC_PLLMUL_48               RCC_PLL_MUL48
3621 
#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
 3621 
 
3622 
#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
 3622 
#define RCC_PLLDIV_2                RCC_PLL_DIV2
3623 
#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
 3623 
#define RCC_PLLDIV_3                RCC_PLL_DIV3
3624 
#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
 3624 
#define RCC_PLLDIV_4                RCC_PLL_DIV4
3625 
 
 3625 
 
3626 
#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
 3626 
#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE
3627 
#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
 3627 
#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG
3628 
#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
 3628 
#define RCC_MCO_NODIV               RCC_MCODIV_1
3629 
#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
 3629 
#define RCC_MCO_DIV1                RCC_MCODIV_1
3630 
#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
 3630 
#define RCC_MCO_DIV2                RCC_MCODIV_2
3631 
#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
 3631 
#define RCC_MCO_DIV4                RCC_MCODIV_4
3632 
#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
 3632 
#define RCC_MCO_DIV8                RCC_MCODIV_8
3633 
#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
 3633 
#define RCC_MCO_DIV16               RCC_MCODIV_16
3634 
 
 3634 
#define RCC_MCO_DIV32               RCC_MCODIV_32
3635 
#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
 3635 
#define RCC_MCO_DIV64               RCC_MCODIV_64
3636 
#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
 3636 
#define RCC_MCO_DIV128              RCC_MCODIV_128
3637 
#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
 3637 
#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK
3638 
#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
 3638 
#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI
3639 
#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
 3639 
#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE
3640 
#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
 3640 
#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK
3641 
#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
 3641 
#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI
3642 
#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
 3642 
#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14
3643 
 
 3643 
#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48
3644 
#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
 3644 
#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE
3645 
#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
 3645 
#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK
3646 
 
 3646 
#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK
3647 
#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
 3647 
#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2
3648 
#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
 3648 
 
3649 
/**
 3649 
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
3650 
  * @}
 3650 
      defined(STM32WL) || defined(STM32C0)
3651 
  */
 3651 
#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE
3652 
 
 3652 
#else
3653 
/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
 3653 
#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK
3654 
  * @{
 3654 
#endif
3655 
  */
 3655 
 
3656 
#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
 3656 
#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1
3657 
#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
 3657 
#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL
3658 
 
 3658 
#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI
3659 
#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
 3659 
#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL
3660 
#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
 3660 
#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL
3661 
 
 3661 
#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5
3662 
#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
 3662 
#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2
3663 
 
 3663 
#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3
3664 
#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
 3664 
 
3665 
#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
 3665 
#define HSION_BitNumber        RCC_HSION_BIT_NUMBER
3666 
#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
 3666 
#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER
3667 
#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
 3667 
#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER
3668 
#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
 3668 
#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER
3669 
#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
 3669 
#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER
3670 
#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
 3670 
#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER
3671 
#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
 3671 
#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER
3672 
#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
 3672 
#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER
3673 
#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
 3673 
#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER
3674 
#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
 3674 
#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER
3675 
#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
 3675 
#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER
3676 
 
 3676 
#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER
3677 
#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
 3677 
#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER
3678 
/**
 3678 
#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER
3679 
  * @}
 3679 
#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER
3680 
  */
 3680 
#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER
3681 
 
 3681 
#define LSION_BitNumber        RCC_LSION_BIT_NUMBER
3682 
/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
 3682 
#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER
3683 
  * @{
 3683 
#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER
3684 
  */
 3684 
#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER
3685 
 
 3685 
#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER
3686 
#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
 3686 
#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER
3687 
#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
 3687 
#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER
3688 
#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
 3688 
#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER
3689 
#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
 3689 
#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER
3690 
#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
 3690 
#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER
3691 
#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
 3691 
#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS
3692 
#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
 3692 
#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS
3693 
 
 3693 
#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS
3694 
#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
 3694 
#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS
3695 
#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
 3695 
#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE
3696 
#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
 3696 
#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE
3697 
/**
 3697 
 
3698 
  * @}
 3698 
#define CR_HSION_BB            RCC_CR_HSION_BB
3699 
  */
 3699 
#define CR_CSSON_BB            RCC_CR_CSSON_BB
3700 
 
 3700 
#define CR_PLLON_BB            RCC_CR_PLLON_BB
3701 
/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
 3701 
#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB
3702 
  * @{
 3702 
#define CR_MSION_BB            RCC_CR_MSION_BB
3703 
  */
 3703 
#define CSR_LSION_BB           RCC_CSR_LSION_BB
3704 
#define __HAL_LTDC_LAYER LTDC_LAYER
 3704 
#define CSR_LSEON_BB           RCC_CSR_LSEON_BB
3705 
#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
 3705 
#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB
3706 
/**
 3706 
#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB
3707 
  * @}
 3707 
#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB
3708 
  */
 3708 
#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB
3709 
 
 3709 
#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB
3710 
/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
 3710 
#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB
3711 
  * @{
 3711 
#define CR_HSEON_BB            RCC_CR_HSEON_BB
3712 
  */
 3712 
#define CSR_RMVF_BB            RCC_CSR_RMVF_BB
3713 
#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
 3713 
#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB
3714 
#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
 3714 
#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB
3715 
#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
 3715 
 
3716 
#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
 3716 
#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE
3717 
#define SAI_STREOMODE                     SAI_STEREOMODE
 3717 
#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE
3718 
#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
 3718 
#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE
3719 
#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
 3719 
#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE
3720 
#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
 3720 
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE
3721 
#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
 3721 
 
3722 
#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
 3722 
#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT
3723 
#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
 3723 
 
3724 
#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
 3724 
#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN
3725 
#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
 3725 
#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF
3726 
#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
 3726 
 
3727 
/**
 3727 
#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48
3728 
  * @}
 3728 
#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ
3729 
  */
 3729 
#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP
3730 
 
 3730 
#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ
3731 
/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
 3731 
#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE
3732 
  * @{
 3732 
#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48
3733 
  */
 3733 
 
3734 
#if defined(STM32H7)
 3734 
#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE
3735 
#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
 3735 
#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE
3736 
#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
 3736 
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED
3737 
#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
 3737 
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED
3738 
#endif
 3738 
#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET
3739 
/**
 3739 
#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET
3740 
  * @}
 3740 
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
3741 
  */
 3741 
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
3742 
 
 3742 
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
3743 
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
 3743 
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
3744 
  * @{
 3744 
#define DfsdmClockSelection         Dfsdm1ClockSelection
3745 
  */
 3745 
#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1
3746 
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
 3746 
#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2
3747 
#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
 3747 
#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK
3748 
#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
 3748 
#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG
3749 
#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
 3749 
#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE
3750 
#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
 3750 
#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2
3751 
#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
 3751 
#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
3752 
#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
 3752 
#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
3753 
#endif
 3753 
#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
3754 
/**
 3754 
 
3755 
  * @}
 3755 
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
3756 
  */
 3756 
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
3757 
 
 3757 
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
3758 
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
 3758 
#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
3759 
  * @{
 3759 
#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
3760 
  */
 3760 
#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
3761 
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
 3761 
#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
3762 
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
 3762 
#if defined(STM32U5)
3763 
#endif /* STM32L4 || STM32F4 || STM32F7 */
 3763 
#define MSIKPLLModeSEL                        RCC_MSIKPLL_MODE_SEL
3764 
/**
 3764 
#define MSISPLLModeSEL                        RCC_MSISPLL_MODE_SEL
3765 
  * @}
 3765 
#define __HAL_RCC_AHB21_CLK_DISABLE           __HAL_RCC_AHB2_1_CLK_DISABLE
3766 
  */
 3766 
#define __HAL_RCC_AHB22_CLK_DISABLE           __HAL_RCC_AHB2_2_CLK_DISABLE
3767 
 
 3767 
#define __HAL_RCC_AHB1_CLK_Disable_Clear      __HAL_RCC_AHB1_CLK_ENABLE
3768 
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
 3768 
#define __HAL_RCC_AHB21_CLK_Disable_Clear     __HAL_RCC_AHB2_1_CLK_ENABLE
3769 
  * @{
 3769 
#define __HAL_RCC_AHB22_CLK_Disable_Clear     __HAL_RCC_AHB2_2_CLK_ENABLE
3770 
  */
 3770 
#define __HAL_RCC_AHB3_CLK_Disable_Clear      __HAL_RCC_AHB3_CLK_ENABLE
3771 
 
 3771 
#define __HAL_RCC_APB1_CLK_Disable_Clear      __HAL_RCC_APB1_CLK_ENABLE
3772 
/**
 3772 
#define __HAL_RCC_APB2_CLK_Disable_Clear      __HAL_RCC_APB2_CLK_ENABLE
3773 
  * @}
 3773 
#define __HAL_RCC_APB3_CLK_Disable_Clear      __HAL_RCC_APB3_CLK_ENABLE
3774 
  */
 3774 
#define IS_RCC_MSIPLLModeSelection            IS_RCC_MSIPLLMODE_SELECT
3775 
 
 3775 
#define RCC_PERIPHCLK_CLK48                   RCC_PERIPHCLK_ICLK
3776 
#ifdef __cplusplus
 3776 
#define RCC_CLK48CLKSOURCE_HSI48              RCC_ICLK_CLKSOURCE_HSI48
3777 
}
 3777 
#define RCC_CLK48CLKSOURCE_PLL2               RCC_ICLK_CLKSOURCE_PLL2
3778 
#endif
 3778 
#define RCC_CLK48CLKSOURCE_PLL1               RCC_ICLK_CLKSOURCE_PLL1
3779 
 
 3779 
#define RCC_CLK48CLKSOURCE_MSIK               RCC_ICLK_CLKSOURCE_MSIK
3780 
#endif /* STM32_HAL_LEGACY */
 3780 
#define __HAL_RCC_ADC1_CLK_ENABLE             __HAL_RCC_ADC12_CLK_ENABLE
3781 
 
 3781 
#define __HAL_RCC_ADC1_CLK_DISABLE            __HAL_RCC_ADC12_CLK_DISABLE
3782 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 3782 
#define __HAL_RCC_ADC1_IS_CLK_ENABLED         __HAL_RCC_ADC12_IS_CLK_ENABLED
3783 
 
 3783 
#define __HAL_RCC_ADC1_IS_CLK_DISABLED        __HAL_RCC_ADC12_IS_CLK_DISABLED
- 
 
 3784 
#define __HAL_RCC_ADC1_FORCE_RESET            __HAL_RCC_ADC12_FORCE_RESET
- 
 
 3785 
#define __HAL_RCC_ADC1_RELEASE_RESET          __HAL_RCC_ADC12_RELEASE_RESET
- 
 
 3786 
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE       __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
- 
 
 3787 
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE      __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
- 
 
 3788 
#define __HAL_RCC_GET_CLK48_SOURCE            __HAL_RCC_GET_ICLK_SOURCE
- 
 
 3789 
#define __HAL_RCC_PLLFRACN_ENABLE             __HAL_RCC_PLL_FRACN_ENABLE
- 
 
 3790 
#define __HAL_RCC_PLLFRACN_DISABLE            __HAL_RCC_PLL_FRACN_DISABLE
- 
 
 3791 
#define __HAL_RCC_PLLFRACN_CONFIG             __HAL_RCC_PLL_FRACN_CONFIG
- 
 
 3792 
#define IS_RCC_PLLFRACN_VALUE                 IS_RCC_PLL_FRACN_VALUE
- 
 
 3793 
#endif /* STM32U5 */
- 
 
 3794 
 
- 
 
 3795 
#if defined(STM32H5)
- 
 
 3796 
#define __HAL_RCC_PLLFRACN_ENABLE       __HAL_RCC_PLL_FRACN_ENABLE
- 
 
 3797 
#define __HAL_RCC_PLLFRACN_DISABLE      __HAL_RCC_PLL_FRACN_DISABLE
- 
 
 3798 
#define __HAL_RCC_PLLFRACN_CONFIG       __HAL_RCC_PLL_FRACN_CONFIG
- 
 
 3799 
#define IS_RCC_PLLFRACN_VALUE           IS_RCC_PLL_FRACN_VALUE
- 
 
 3800 
 
- 
 
 3801 
#define RCC_PLLSOURCE_NONE              RCC_PLL1_SOURCE_NONE
- 
 
 3802 
#define RCC_PLLSOURCE_HSI               RCC_PLL1_SOURCE_HSI
- 
 
 3803 
#define RCC_PLLSOURCE_CSI               RCC_PLL1_SOURCE_CSI
- 
 
 3804 
#define RCC_PLLSOURCE_HSE               RCC_PLL1_SOURCE_HSE
- 
 
 3805 
#define RCC_PLLVCIRANGE_0               RCC_PLL1_VCIRANGE_0
- 
 
 3806 
#define RCC_PLLVCIRANGE_1               RCC_PLL1_VCIRANGE_1
- 
 
 3807 
#define RCC_PLLVCIRANGE_2               RCC_PLL1_VCIRANGE_2
- 
 
 3808 
#define RCC_PLLVCIRANGE_3               RCC_PLL1_VCIRANGE_3
- 
 
 3809 
#define RCC_PLL1VCOWIDE                 RCC_PLL1_VCORANGE_WIDE
- 
 
 3810 
#define RCC_PLL1VCOMEDIUM               RCC_PLL1_VCORANGE_MEDIUM
- 
 
 3811 
 
- 
 
 3812 
#define IS_RCC_PLLSOURCE                IS_RCC_PLL1_SOURCE
- 
 
 3813 
#define IS_RCC_PLLRGE_VALUE             IS_RCC_PLL1_VCIRGE_VALUE
- 
 
 3814 
#define IS_RCC_PLLVCORGE_VALUE          IS_RCC_PLL1_VCORGE_VALUE
- 
 
 3815 
#define IS_RCC_PLLCLOCKOUT_VALUE        IS_RCC_PLL1_CLOCKOUT_VALUE
- 
 
 3816 
#define IS_RCC_PLL_FRACN_VALUE          IS_RCC_PLL1_FRACN_VALUE
- 
 
 3817 
#define IS_RCC_PLLM_VALUE               IS_RCC_PLL1_DIVM_VALUE
- 
 
 3818 
#define IS_RCC_PLLN_VALUE               IS_RCC_PLL1_MULN_VALUE
- 
 
 3819 
#define IS_RCC_PLLP_VALUE               IS_RCC_PLL1_DIVP_VALUE
- 
 
 3820 
#define IS_RCC_PLLQ_VALUE               IS_RCC_PLL1_DIVQ_VALUE
- 
 
 3821 
#define IS_RCC_PLLR_VALUE               IS_RCC_PLL1_DIVR_VALUE
- 
 
 3822 
 
- 
 
 3823 
#define __HAL_RCC_PLL_ENABLE            __HAL_RCC_PLL1_ENABLE
- 
 
 3824 
#define __HAL_RCC_PLL_DISABLE           __HAL_RCC_PLL1_DISABLE
- 
 
 3825 
#define __HAL_RCC_PLL_FRACN_ENABLE      __HAL_RCC_PLL1_FRACN_ENABLE
- 
 
 3826 
#define __HAL_RCC_PLL_FRACN_DISABLE     __HAL_RCC_PLL1_FRACN_DISABLE
- 
 
 3827 
#define __HAL_RCC_PLL_CONFIG            __HAL_RCC_PLL1_CONFIG
- 
 
 3828 
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG  __HAL_RCC_PLL1_PLLSOURCE_CONFIG
- 
 
 3829 
#define __HAL_RCC_PLL_DIVM_CONFIG       __HAL_RCC_PLL1_DIVM_CONFIG
- 
 
 3830 
#define __HAL_RCC_PLL_FRACN_CONFIG      __HAL_RCC_PLL1_FRACN_CONFIG
- 
 
 3831 
#define __HAL_RCC_PLL_VCIRANGE          __HAL_RCC_PLL1_VCIRANGE
- 
 
 3832 
#define __HAL_RCC_PLL_VCORANGE          __HAL_RCC_PLL1_VCORANGE
- 
 
 3833 
#define __HAL_RCC_GET_PLL_OSCSOURCE     __HAL_RCC_GET_PLL1_OSCSOURCE
- 
 
 3834 
#define __HAL_RCC_PLLCLKOUT_ENABLE      __HAL_RCC_PLL1_CLKOUT_ENABLE
- 
 
 3835 
#define __HAL_RCC_PLLCLKOUT_DISABLE     __HAL_RCC_PLL1_CLKOUT_DISABLE
- 
 
 3836 
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG  __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
- 
 
 3837 
 
- 
 
 3838 
#define __HAL_RCC_PLL2FRACN_ENABLE      __HAL_RCC_PLL2_FRACN_ENABLE
- 
 
 3839 
#define __HAL_RCC_PLL2FRACN_DISABLE     __HAL_RCC_PLL2_FRACN_DISABLE
- 
 
 3840 
#define __HAL_RCC_PLL2CLKOUT_ENABLE     __HAL_RCC_PLL2_CLKOUT_ENABLE
- 
 
 3841 
#define __HAL_RCC_PLL2CLKOUT_DISABLE    __HAL_RCC_PLL2_CLKOUT_DISABLE
- 
 
 3842 
#define __HAL_RCC_PLL2FRACN_CONFIG      __HAL_RCC_PLL2_FRACN_CONFIG
- 
 
 3843 
#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
- 
 
 3844 
 
- 
 
 3845 
#define __HAL_RCC_PLL3FRACN_ENABLE      __HAL_RCC_PLL3_FRACN_ENABLE
- 
 
 3846 
#define __HAL_RCC_PLL3FRACN_DISABLE     __HAL_RCC_PLL3_FRACN_DISABLE
- 
 
 3847 
#define __HAL_RCC_PLL3CLKOUT_ENABLE     __HAL_RCC_PLL3_CLKOUT_ENABLE
- 
 
 3848 
#define __HAL_RCC_PLL3CLKOUT_DISABLE    __HAL_RCC_PLL3_CLKOUT_DISABLE
- 
 
 3849 
#define __HAL_RCC_PLL3FRACN_CONFIG      __HAL_RCC_PLL3_FRACN_CONFIG
- 
 
 3850 
#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
- 
 
 3851 
 
- 
 
 3852 
#define RCC_PLL2VCIRANGE_0              RCC_PLL2_VCIRANGE_0
- 
 
 3853 
#define RCC_PLL2VCIRANGE_1              RCC_PLL2_VCIRANGE_1
- 
 
 3854 
#define RCC_PLL2VCIRANGE_2              RCC_PLL2_VCIRANGE_2
- 
 
 3855 
#define RCC_PLL2VCIRANGE_3              RCC_PLL2_VCIRANGE_3
- 
 
 3856 
 
- 
 
 3857 
#define RCC_PLL2VCOWIDE                 RCC_PLL2_VCORANGE_WIDE
- 
 
 3858 
#define RCC_PLL2VCOMEDIUM               RCC_PLL2_VCORANGE_MEDIUM
- 
 
 3859 
 
- 
 
 3860 
#define RCC_PLL2SOURCE_NONE             RCC_PLL2_SOURCE_NONE
- 
 
 3861 
#define RCC_PLL2SOURCE_HSI              RCC_PLL2_SOURCE_HSI
- 
 
 3862 
#define RCC_PLL2SOURCE_CSI              RCC_PLL2_SOURCE_CSI
- 
 
 3863 
#define RCC_PLL2SOURCE_HSE              RCC_PLL2_SOURCE_HSE
- 
 
 3864 
 
- 
 
 3865 
#define RCC_PLL3VCIRANGE_0              RCC_PLL3_VCIRANGE_0
- 
 
 3866 
#define RCC_PLL3VCIRANGE_1              RCC_PLL3_VCIRANGE_1
- 
 
 3867 
#define RCC_PLL3VCIRANGE_2              RCC_PLL3_VCIRANGE_2
- 
 
 3868 
#define RCC_PLL3VCIRANGE_3              RCC_PLL3_VCIRANGE_3
- 
 
 3869 
 
- 
 
 3870 
#define RCC_PLL3VCOWIDE                 RCC_PLL3_VCORANGE_WIDE
- 
 
 3871 
#define RCC_PLL3VCOMEDIUM               RCC_PLL3_VCORANGE_MEDIUM
- 
 
 3872 
 
- 
 
 3873 
#define RCC_PLL3SOURCE_NONE             RCC_PLL3_SOURCE_NONE
- 
 
 3874 
#define RCC_PLL3SOURCE_HSI              RCC_PLL3_SOURCE_HSI
- 
 
 3875 
#define RCC_PLL3SOURCE_CSI              RCC_PLL3_SOURCE_CSI
- 
 
 3876 
#define RCC_PLL3SOURCE_HSE              RCC_PLL3_SOURCE_HSE
- 
 
 3877 
 
- 
 
 3878 
 
- 
 
 3879 
#endif /* STM32H5 */
- 
 
 3880 
 
- 
 
 3881 
/**
- 
 
 3882 
  * @}
- 
 
 3883 
  */
- 
 
 3884 
 
- 
 
 3885 
/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
- 
 
 3886 
  * @{
- 
 
 3887 
  */
- 
 
 3888 
#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
- 
 
 3889 
 
- 
 
 3890 
/**
- 
 
 3891 
  * @}
- 
 
 3892 
  */
- 
 
 3893 
 
- 
 
 3894 
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
- 
 
 3895 
  * @{
- 
 
 3896 
  */
- 
 
 3897 
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
- 
 
 3898 
    defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
- 
 
 3899 
    defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
- 
 
 3900 
#else
- 
 
 3901 
#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG
- 
 
 3902 
#endif
- 
 
 3903 
#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT
- 
 
 3904 
#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT
- 
 
 3905 
 
- 
 
 3906 
#if defined (STM32F1)
- 
 
 3907 
#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()
- 
 
 3908 
 
- 
 
 3909 
#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()
- 
 
 3910 
 
- 
 
 3911 
#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()
- 
 
 3912 
 
- 
 
 3913 
#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()
- 
 
 3914 
 
- 
 
 3915 
#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()
- 
 
 3916 
#else
- 
 
 3917 
#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \
- 
 
 3918 
                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \
- 
 
 3919 
                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))
- 
 
 3920 
#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \
- 
 
 3921 
                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \
- 
 
 3922 
                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))
- 
 
 3923 
#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \
- 
 
 3924 
                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \
- 
 
 3925 
                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))
- 
 
 3926 
#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \
- 
 
 3927 
                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \
- 
 
 3928 
                                                    __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))
- 
 
 3929 
#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \
- 
 
 3930 
                                                       (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \
- 
 
 3931 
                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
- 
 
 3932 
#endif   /* STM32F1 */
- 
 
 3933 
 
- 
 
 3934 
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
- 
 
 3935 
    defined (STM32L0) || defined (STM32L1)
- 
 
 3936 
#define __HAL_RTC_TAMPER_GET_IT                   __HAL_RTC_TAMPER_GET_FLAG
- 
 
 3937 
#endif
- 
 
 3938 
 
- 
 
 3939 
#define IS_ALARM                                  IS_RTC_ALARM
- 
 
 3940 
#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK
- 
 
 3941 
#define IS_TAMPER                                 IS_RTC_TAMPER
- 
 
 3942 
#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE
- 
 
 3943 
#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER
- 
 
 3944 
#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT
- 
 
 3945 
#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE
- 
 
 3946 
#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION
- 
 
 3947 
#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE
- 
 
 3948 
#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ
- 
 
 3949 
#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION
- 
 
 3950 
#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER
- 
 
 3951 
#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK
- 
 
 3952 
#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER
- 
 
 3953 
 
- 
 
 3954 
#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE
- 
 
 3955 
#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE
- 
 
 3956 
 
- 
 
 3957 
#if defined (STM32H5)
- 
 
 3958 
#define __HAL_RCC_RTCAPB_CLK_ENABLE   __HAL_RCC_RTC_CLK_ENABLE
- 
 
 3959 
#define __HAL_RCC_RTCAPB_CLK_DISABLE  __HAL_RCC_RTC_CLK_DISABLE
- 
 
 3960 
#endif   /* STM32H5 */
- 
 
 3961 
 
- 
 
 3962 
/**
- 
 
 3963 
  * @}
- 
 
 3964 
  */
- 
 
 3965 
 
- 
 
 3966 
/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose
- 
 
 3967 
  * @{
- 
 
 3968 
  */
- 
 
 3969 
 
- 
 
 3970 
#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE
- 
 
 3971 
#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS
- 
 
 3972 
 
- 
 
 3973 
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
- 
 
 3974 
#define eMMC_HIGH_VOLTAGE_RANGE     EMMC_HIGH_VOLTAGE_RANGE
- 
 
 3975 
#define eMMC_DUAL_VOLTAGE_RANGE     EMMC_DUAL_VOLTAGE_RANGE
- 
 
 3976 
#define eMMC_LOW_VOLTAGE_RANGE      EMMC_LOW_VOLTAGE_RANGE
- 
 
 3977 
 
- 
 
 3978 
#define SDMMC_NSpeed_CLK_DIV        SDMMC_NSPEED_CLK_DIV
- 
 
 3979 
#define SDMMC_HSpeed_CLK_DIV        SDMMC_HSPEED_CLK_DIV
- 
 
 3980 
#endif
- 
 
 3981 
 
- 
 
 3982 
#if defined(STM32F4) || defined(STM32F2)
- 
 
 3983 
#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED
- 
 
 3984 
#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY
- 
 
 3985 
#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED
- 
 
 3986 
#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION
- 
 
 3987 
#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND
- 
 
 3988 
#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT
- 
 
 3989 
#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED
- 
 
 3990 
#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE
- 
 
 3991 
#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE
- 
 
 3992 
#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE
- 
 
 3993 
#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
- 
 
 3994 
#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT
- 
 
 3995 
#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT
- 
 
 3996 
#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG
- 
 
 3997 
#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG
- 
 
 3998 
#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT
- 
 
 3999 
#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT
- 
 
 4000 
#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS
- 
 
 4001 
#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT
- 
 
 4002 
#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND
- 
 
 4003 
/* alias CMSIS */
- 
 
 4004 
#define  SDMMC1_IRQn                SDIO_IRQn
- 
 
 4005 
#define  SDMMC1_IRQHandler          SDIO_IRQHandler
- 
 
 4006 
#endif
- 
 
 4007 
 
- 
 
 4008 
#if defined(STM32F7) || defined(STM32L4)
- 
 
 4009 
#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED
- 
 
 4010 
#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY
- 
 
 4011 
#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED
- 
 
 4012 
#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION
- 
 
 4013 
#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND
- 
 
 4014 
#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT
- 
 
 4015 
#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED
- 
 
 4016 
#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE
- 
 
 4017 
#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE
- 
 
 4018 
#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE
- 
 
 4019 
#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE
- 
 
 4020 
#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT
- 
 
 4021 
#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT
- 
 
 4022 
#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG
- 
 
 4023 
#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG
- 
 
 4024 
#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT
- 
 
 4025 
#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT
- 
 
 4026 
#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS
- 
 
 4027 
#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT
- 
 
 4028 
#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND
- 
 
 4029 
/* alias CMSIS for compatibilities */
- 
 
 4030 
#define  SDIO_IRQn                  SDMMC1_IRQn
- 
 
 4031 
#define  SDIO_IRQHandler            SDMMC1_IRQHandler
- 
 
 4032 
#endif
- 
 
 4033 
 
- 
 
 4034 
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
- 
 
 4035 
#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
- 
 
 4036 
#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
- 
 
 4037 
#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
- 
 
 4038 
#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
- 
 
 4039 
#endif
- 
 
 4040 
 
- 
 
 4041 
#if defined(STM32H7) || defined(STM32L5)
- 
 
 4042 
#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
- 
 
 4043 
#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
- 
 
 4044 
#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
- 
 
 4045 
#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
- 
 
 4046 
#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback
- 
 
 4047 
#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback
- 
 
 4048 
#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback
- 
 
 4049 
#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback
- 
 
 4050 
#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback
- 
 
 4051 
#endif
- 
 
 4052 
/**
- 
 
 4053 
  * @}
- 
 
 4054 
  */
- 
 
 4055 
 
- 
 
 4056 
/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose
- 
 
 4057 
  * @{
- 
 
 4058 
  */
- 
 
 4059 
 
- 
 
 4060 
#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT
- 
 
 4061 
#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT
- 
 
 4062 
#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE
- 
 
 4063 
#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE
- 
 
 4064 
#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE
- 
 
 4065 
#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE
- 
 
 4066 
 
- 
 
 4067 
#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE
- 
 
 4068 
#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE
- 
 
 4069 
 
- 
 
 4070 
#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE
- 
 
 4071 
 
- 
 
 4072 
/**
- 
 
 4073 
  * @}
- 
 
 4074 
  */
- 
 
 4075 
 
- 
 
 4076 
/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose
- 
 
 4077 
  * @{
- 
 
 4078 
  */
- 
 
 4079 
#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1
- 
 
 4080 
#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2
- 
 
 4081 
#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START
- 
 
 4082 
#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH
- 
 
 4083 
#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR
- 
 
 4084 
#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE
- 
 
 4085 
#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE
- 
 
 4086 
#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED
- 
 
 4087 
/**
- 
 
 4088 
  * @}
- 
 
 4089 
  */
- 
 
 4090 
 
- 
 
 4091 
/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose
- 
 
 4092 
  * @{
- 
 
 4093 
  */
- 
 
 4094 
 
- 
 
 4095 
#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX
- 
 
 4096 
#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX
- 
 
 4097 
#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC
- 
 
 4098 
 
- 
 
 4099 
/**
- 
 
 4100 
  * @}
- 
 
 4101 
  */
- 
 
 4102 
 
- 
 
 4103 
/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
- 
 
 4104 
  * @{
- 
 
 4105 
  */
- 
 
 4106 
 
- 
 
 4107 
#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE
- 
 
 4108 
#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION
- 
 
 4109 
#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE
- 
 
 4110 
#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION
- 
 
 4111 
 
- 
 
 4112 
#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD
- 
 
 4113 
 
- 
 
 4114 
#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE
- 
 
 4115 
#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE
- 
 
 4116 
 
- 
 
 4117 
/**
- 
 
 4118 
  * @}
- 
 
 4119 
  */
- 
 
 4120 
 
- 
 
 4121 
 
- 
 
 4122 
/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose
- 
 
 4123 
  * @{
- 
 
 4124 
  */
- 
 
 4125 
 
- 
 
 4126 
#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT
- 
 
 4127 
#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT
- 
 
 4128 
#define __USART_ENABLE                  __HAL_USART_ENABLE
- 
 
 4129 
#define __USART_DISABLE                 __HAL_USART_DISABLE
- 
 
 4130 
 
- 
 
 4131 
#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE
- 
 
 4132 
#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE
- 
 
 4133 
 
- 
 
 4134 
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7)
- 
 
 4135 
#define USART_OVERSAMPLING_16               0x00000000U
- 
 
 4136 
#define USART_OVERSAMPLING_8                USART_CR1_OVER8
- 
 
 4137 
 
- 
 
 4138 
#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \
- 
 
 4139 
                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))
- 
 
 4140 
#endif /* STM32F0 || STM32F3 || STM32F7 */
- 
 
 4141 
/**
- 
 
 4142 
  * @}
- 
 
 4143 
  */
- 
 
 4144 
 
- 
 
 4145 
/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose
- 
 
 4146 
  * @{
- 
 
 4147 
  */
- 
 
 4148 
#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE
- 
 
 4149 
 
- 
 
 4150 
#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE
- 
 
 4151 
#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE
- 
 
 4152 
#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE
- 
 
 4153 
#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE
- 
 
 4154 
 
- 
 
 4155 
#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE
- 
 
 4156 
#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE
- 
 
 4157 
#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE
- 
 
 4158 
#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE
- 
 
 4159 
 
- 
 
 4160 
#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT
- 
 
 4161 
#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT
- 
 
 4162 
#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG
- 
 
 4163 
#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG
- 
 
 4164 
#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE
- 
 
 4165 
#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE
- 
 
 4166 
#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
- 
 
 4167 
 
- 
 
 4168 
#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT
- 
 
 4169 
#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT
- 
 
 4170 
#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG
- 
 
 4171 
#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG
- 
 
 4172 
#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE
- 
 
 4173 
#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
- 
 
 4174 
#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
- 
 
 4175 
#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT
- 
 
 4176 
 
- 
 
 4177 
#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT
- 
 
 4178 
#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT
- 
 
 4179 
#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG
- 
 
 4180 
#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG
- 
 
 4181 
#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE
- 
 
 4182 
#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE
- 
 
 4183 
#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE
- 
 
 4184 
#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT
- 
 
 4185 
 
- 
 
 4186 
#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup
- 
 
 4187 
#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup
- 
 
 4188 
 
- 
 
 4189 
#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo
- 
 
 4190 
#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo
- 
 
 4191 
/**
- 
 
 4192 
  * @}
- 
 
 4193 
  */
- 
 
 4194 
 
- 
 
 4195 
/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose
- 
 
 4196 
  * @{
- 
 
 4197 
  */
- 
 
 4198 
#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE
- 
 
 4199 
#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE
- 
 
 4200 
 
- 
 
 4201 
#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE
- 
 
 4202 
#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT
- 
 
 4203 
 
- 
 
 4204 
#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE
- 
 
 4205 
 
- 
 
 4206 
#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN
- 
 
 4207 
#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER
- 
 
 4208 
#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER
- 
 
 4209 
#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER
- 
 
 4210 
#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD
- 
 
 4211 
#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD
- 
 
 4212 
#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION
- 
 
 4213 
#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION
- 
 
 4214 
#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER
- 
 
 4215 
#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER
- 
 
 4216 
#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE
- 
 
 4217 
#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE
- 
 
 4218 
 
- 
 
 4219 
#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1
- 
 
 4220 
/**
- 
 
 4221 
  * @}
- 
 
 4222 
  */
- 
 
 4223 
 
- 
 
 4224 
/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
- 
 
 4225 
  * @{
- 
 
 4226 
  */
- 
 
 4227 
 
- 
 
 4228 
#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
- 
 
 4229 
#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
- 
 
 4230 
#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG
- 
 
 4231 
#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG
- 
 
 4232 
#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER
- 
 
 4233 
#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
- 
 
 4234 
#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
- 
 
 4235 
 
- 
 
 4236 
#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE
- 
 
 4237 
#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE
- 
 
 4238 
#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE
- 
 
 4239 
/**
- 
 
 4240 
  * @}
- 
 
 4241 
  */
- 
 
 4242 
 
- 
 
 4243 
/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose
- 
 
 4244 
  * @{
- 
 
 4245 
  */
- 
 
 4246 
#define __HAL_LTDC_LAYER LTDC_LAYER
- 
 
 4247 
#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
- 
 
 4248 
/**
- 
 
 4249 
  * @}
- 
 
 4250 
  */
- 
 
 4251 
 
- 
 
 4252 
/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose
- 
 
 4253 
  * @{
- 
 
 4254 
  */
- 
 
 4255 
#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE
- 
 
 4256 
#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE
- 
 
 4257 
#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE
- 
 
 4258 
#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE
- 
 
 4259 
#define SAI_STREOMODE                     SAI_STEREOMODE
- 
 
 4260 
#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY
- 
 
 4261 
#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL
- 
 
 4262 
#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL
- 
 
 4263 
#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL
- 
 
 4264 
#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL
- 
 
 4265 
#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL
- 
 
 4266 
#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE
- 
 
 4267 
#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1
- 
 
 4268 
#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE
- 
 
 4269 
/**
- 
 
 4270 
  * @}
- 
 
 4271 
  */
- 
 
 4272 
 
- 
 
 4273 
/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
- 
 
 4274 
  * @{
- 
 
 4275 
  */
- 
 
 4276 
#if defined(STM32H7)
- 
 
 4277 
#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow
- 
 
 4278 
#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT
- 
 
 4279 
#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA
- 
 
 4280 
#endif
- 
 
 4281 
/**
- 
 
 4282 
  * @}
- 
 
 4283 
  */
- 
 
 4284 
 
- 
 
 4285 
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
- 
 
 4286 
  * @{
- 
 
 4287 
  */
- 
 
 4288 
#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
- 
 
 4289 
#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT
- 
 
 4290 
#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA
- 
 
 4291 
#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart
- 
 
 4292 
#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT
- 
 
 4293 
#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA
- 
 
 4294 
#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop
- 
 
 4295 
#endif
- 
 
 4296 
/**
- 
 
 4297 
  * @}
- 
 
 4298 
  */
- 
 
 4299 
 
- 
 
 4300 
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
- 
 
 4301 
  * @{
- 
 
 4302 
  */
- 
 
 4303 
#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)
- 
 
 4304 
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
- 
 
 4305 
#endif /* STM32L4 || STM32F4 || STM32F7 */
- 
 
 4306 
/**
- 
 
 4307 
  * @}
- 
 
 4308 
  */
- 
 
 4309 
 
- 
 
 4310 
/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
- 
 
 4311 
  * @{
- 
 
 4312 
  */
- 
 
 4313 
#if defined (STM32F7)
- 
 
 4314 
#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE
- 
 
 4315 
#endif /* STM32F7 */
- 
 
 4316 
/**
- 
 
 4317 
  * @}
- 
 
 4318 
  */
- 
 
 4319 
 
- 
 
 4320 
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
- 
 
 4321 
  * @{
- 
 
 4322 
  */
- 
 
 4323 
 
- 
 
 4324 
/**
- 
 
 4325 
  * @}
- 
 
 4326 
  */
- 
 
 4327 
 
- 
 
 4328 
#ifdef __cplusplus
- 
 
 4329 
}
- 
 
 4330 
#endif
- 
 
 4331 
 
- 
 
 4332 
#endif /* STM32_HAL_LEGACY */
- 
 
 4333 
 
- 
 
 4334