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| Rev 2 | Rev 6 | ||
|---|---|---|---|
| Line 474... | Line 474... | ||
| 474 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
474 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
| 475 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
475 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
| 476 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
476 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
| 477 | assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); |
477 | assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); |
| 478 | 478 | ||
| - | 479 | /* ADC group regular continuous mode and discontinuous mode */ |
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| - | 480 | /* can not be enabled simultenaeously */ |
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| - | 481 | assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) |
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| - | 482 | || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); |
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| - | 483 | ||
| 479 | /* Note: Hardware constraint (refer to description of this function): */ |
484 | /* Note: Hardware constraint (refer to description of this function): */ |
| 480 | /* ADC instance must be disabled. */ |
485 | /* ADC instance must be disabled. */ |
| 481 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
486 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| 482 | { |
487 | { |
| 483 | /* Configuration of ADC hierarchical scope: */ |
488 | /* Configuration of ADC hierarchical scope: */ |