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Line 53... Line 53...
53
               Interrupt and DMA request if needed (Note that One Timer is used to interface
53
               Interrupt and DMA request if needed (Note that One Timer is used to interface
54
               with the Hall sensor Interface and another Timer should be used to use
54
               with the Hall sensor Interface and another Timer should be used to use
55
               the commutation event).
55
               the commutation event).
56
 
56
 
57
     (#) Activate the TIM peripheral using one of the start functions:
57
     (#) Activate the TIM peripheral using one of the start functions:
58
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
58
           (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(),
-
 
59
                HAL_TIMEx_OCN_Start_IT()
59
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
60
           (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(),
-
 
61
                HAL_TIMEx_PWMN_Start_IT()
60
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
62
           (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
61
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
63
           (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(),
-
 
64
                HAL_TIMEx_HallSensor_Start_IT().
62
 
65
 
63
  @endverbatim
66
  @endverbatim
64
  ******************************************************************************
67
  ******************************************************************************
65
  * @attention
68
  * @attention
66
  *
69
  *
Line 89... Line 92...
89
 
92
 
90
#ifdef HAL_TIM_MODULE_ENABLED
93
#ifdef HAL_TIM_MODULE_ENABLED
91
 
94
 
92
/* Private typedef -----------------------------------------------------------*/
95
/* Private typedef -----------------------------------------------------------*/
93
/* Private define ------------------------------------------------------------*/
96
/* Private define ------------------------------------------------------------*/
94
/* Private macro -------------------------------------------------------------*/
97
/* Private macros ------------------------------------------------------------*/
95
/* Private variables ---------------------------------------------------------*/
98
/* Private variables ---------------------------------------------------------*/
96
/* Private function prototypes -----------------------------------------------*/
99
/* Private function prototypes -----------------------------------------------*/
-
 
100
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma);
-
 
101
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma);
97
static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
102
static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState);
98
 
103
 
99
/* Exported functions --------------------------------------------------------*/
104
/* Exported functions --------------------------------------------------------*/
100
/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
105
/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions
101
  * @{
106
  * @{
Line 122... Line 127...
122
@endverbatim
127
@endverbatim
123
  * @{
128
  * @{
124
  */
129
  */
125
/**
130
/**
126
  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
131
  * @brief  Initializes the TIM Hall Sensor Interface and initialize the associated handle.
-
 
132
  * @note   When the timer instance is initialized in Hall Sensor Interface mode,
-
 
133
  *         timer channels 1 and channel 2 are reserved and cannot be used for
-
 
134
  *         other purpose.
127
  * @param  htim TIM Hall Sensor Interface handle
135
  * @param  htim TIM Hall Sensor Interface handle
128
  * @param  sConfig TIM Hall Sensor configuration structure
136
  * @param  sConfig TIM Hall Sensor configuration structure
129
  * @retval HAL status
137
  * @retval HAL status
130
  */
138
  */
131
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
139
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig)
Line 207... Line 215...
207
  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
215
  /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
208
    register to 101 */
216
    register to 101 */
209
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
217
  htim->Instance->CR2 &= ~TIM_CR2_MMS;
210
  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
218
  htim->Instance->CR2 |= TIM_TRGO_OC2REF;
211
 
219
 
-
 
220
  /* Initialize the DMA burst operation state */
-
 
221
  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
-
 
222
 
-
 
223
  /* Initialize the TIM channels state */
-
 
224
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
225
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
226
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
227
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
228
 
212
  /* Initialize the TIM state*/
229
  /* Initialize the TIM state*/
213
  htim->State = HAL_TIM_STATE_READY;
230
  htim->State = HAL_TIM_STATE_READY;
214
 
231
 
215
  return HAL_OK;
232
  return HAL_OK;
216
}
233
}
Line 240... Line 257...
240
#else
257
#else
241
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
258
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
242
  HAL_TIMEx_HallSensor_MspDeInit(htim);
259
  HAL_TIMEx_HallSensor_MspDeInit(htim);
243
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
260
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
244
 
261
 
-
 
262
  /* Change the DMA burst operation state */
-
 
263
  htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
-
 
264
 
-
 
265
  /* Change the TIM channels state */
-
 
266
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
-
 
267
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
 
268
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
-
 
269
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
-
 
270
 
245
  /* Change TIM state */
271
  /* Change TIM state */
246
  htim->State = HAL_TIM_STATE_RESET;
272
  htim->State = HAL_TIM_STATE_RESET;
247
 
273
 
248
  /* Release Lock */
274
  /* Release Lock */
249
  __HAL_UNLOCK(htim);
275
  __HAL_UNLOCK(htim);
Line 287... Line 313...
287
  * @retval HAL status
313
  * @retval HAL status
288
  */
314
  */
289
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
315
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
290
{
316
{
291
  uint32_t tmpsmcr;
317
  uint32_t tmpsmcr;
-
 
318
  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-
 
319
  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
 
320
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
-
 
321
  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
292
 
322
 
293
  /* Check the parameters */
323
  /* Check the parameters */
294
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
324
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
295
 
325
 
-
 
326
  /* Check the TIM channels state */
-
 
327
  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
328
      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
329
      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
330
      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-
 
331
  {
-
 
332
    return HAL_ERROR;
-
 
333
  }
-
 
334
 
-
 
335
  /* Set the TIM channels state */
-
 
336
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
337
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
338
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
339
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
340
 
296
  /* Enable the Input Capture channel 1
341
  /* Enable the Input Capture channel 1
297
    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
342
  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
-
 
343
  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
298
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
344
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
299
 
345
 
300
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
346
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-
 
347
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-
 
348
  {
301
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
349
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
302
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
350
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-
 
351
    {
-
 
352
      __HAL_TIM_ENABLE(htim);
-
 
353
    }
-
 
354
  }
-
 
355
  else
303
  {
356
  {
304
    __HAL_TIM_ENABLE(htim);
357
    __HAL_TIM_ENABLE(htim);
305
  }
358
  }
306
 
359
 
307
  /* Return function status */
360
  /* Return function status */
Line 317... Line 370...
317
{
370
{
318
  /* Check the parameters */
371
  /* Check the parameters */
319
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
372
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
320
 
373
 
321
  /* Disable the Input Capture channels 1, 2 and 3
374
  /* Disable the Input Capture channels 1, 2 and 3
322
    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
375
  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
-
 
376
  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
323
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
377
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
324
 
378
 
325
  /* Disable the Peripheral */
379
  /* Disable the Peripheral */
326
  __HAL_TIM_DISABLE(htim);
380
  __HAL_TIM_DISABLE(htim);
327
 
381
 
-
 
382
  /* Set the TIM channels state */
-
 
383
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
384
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
385
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
386
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
387
 
328
  /* Return function status */
388
  /* Return function status */
329
  return HAL_OK;
389
  return HAL_OK;
330
}
390
}
331
 
391
 
332
/**
392
/**
Line 335... Line 395...
335
  * @retval HAL status
395
  * @retval HAL status
336
  */
396
  */
337
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
397
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
338
{
398
{
339
  uint32_t tmpsmcr;
399
  uint32_t tmpsmcr;
-
 
400
  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-
 
401
  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
 
402
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
-
 
403
  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
340
 
404
 
341
  /* Check the parameters */
405
  /* Check the parameters */
342
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
406
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
343
 
407
 
-
 
408
  /* Check the TIM channels state */
-
 
409
  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
410
      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
411
      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
412
      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-
 
413
  {
-
 
414
    return HAL_ERROR;
-
 
415
  }
-
 
416
 
-
 
417
  /* Set the TIM channels state */
-
 
418
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
419
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
420
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
421
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
422
 
344
  /* Enable the capture compare Interrupts 1 event */
423
  /* Enable the capture compare Interrupts 1 event */
345
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
424
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
346
 
425
 
347
  /* Enable the Input Capture channel 1
426
  /* Enable the Input Capture channel 1
348
    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
427
  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
-
 
428
  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
349
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
429
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
350
 
430
 
351
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
431
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-
 
432
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-
 
433
  {
352
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
434
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
353
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
435
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-
 
436
    {
-
 
437
      __HAL_TIM_ENABLE(htim);
-
 
438
    }
-
 
439
  }
-
 
440
  else
354
  {
441
  {
355
    __HAL_TIM_ENABLE(htim);
442
    __HAL_TIM_ENABLE(htim);
356
  }
443
  }
357
 
444
 
358
  /* Return function status */
445
  /* Return function status */
Line 368... Line 455...
368
{
455
{
369
  /* Check the parameters */
456
  /* Check the parameters */
370
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
457
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
371
 
458
 
372
  /* Disable the Input Capture channel 1
459
  /* Disable the Input Capture channel 1
373
    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
460
  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
-
 
461
  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
374
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
462
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
375
 
463
 
376
  /* Disable the capture compare Interrupts event */
464
  /* Disable the capture compare Interrupts event */
377
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
465
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
378
 
466
 
379
  /* Disable the Peripheral */
467
  /* Disable the Peripheral */
380
  __HAL_TIM_DISABLE(htim);
468
  __HAL_TIM_DISABLE(htim);
381
 
469
 
-
 
470
  /* Set the TIM channels state */
-
 
471
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
472
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
473
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
474
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
475
 
382
  /* Return function status */
476
  /* Return function status */
383
  return HAL_OK;
477
  return HAL_OK;
384
}
478
}
385
 
479
 
386
/**
480
/**
Line 391... Line 485...
391
  * @retval HAL status
485
  * @retval HAL status
392
  */
486
  */
393
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
487
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
394
{
488
{
395
  uint32_t tmpsmcr;
489
  uint32_t tmpsmcr;
-
 
490
  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-
 
491
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
396
 
492
 
397
  /* Check the parameters */
493
  /* Check the parameters */
398
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
494
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
399
 
495
 
-
 
496
  /* Set the TIM channel state */
400
  if (htim->State == HAL_TIM_STATE_BUSY)
497
  if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
-
 
498
      || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
401
  {
499
  {
402
    return HAL_BUSY;
500
    return HAL_BUSY;
403
  }
501
  }
404
  else if (htim->State == HAL_TIM_STATE_READY)
502
  else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
-
 
503
           && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
405
  {
504
  {
406
    if (((uint32_t)pData == 0U) && (Length > 0U))
505
    if ((pData == NULL) && (Length > 0U))
407
    {
506
    {
408
      return HAL_ERROR;
507
      return HAL_ERROR;
409
    }
508
    }
410
    else
509
    else
411
    {
510
    {
412
      htim->State = HAL_TIM_STATE_BUSY;
511
      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
512
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
413
    }
513
    }
414
  }
514
  }
415
  else
515
  else
416
  {
516
  {
417
    /* nothing to do */
517
    return HAL_ERROR;
418
  }
518
  }
-
 
519
 
419
  /* Enable the Input Capture channel 1
520
  /* Enable the Input Capture channel 1
420
    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
521
  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
-
 
522
  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
421
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
523
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
422
 
524
 
423
  /* Set the DMA Input Capture 1 Callbacks */
525
  /* Set the DMA Input Capture 1 Callbacks */
424
  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
526
  htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
425
  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
527
  htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
Line 427... Line 529...
427
  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
529
  htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
428
 
530
 
429
  /* Enable the DMA channel for Capture 1*/
531
  /* Enable the DMA channel for Capture 1*/
430
  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
532
  if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
431
  {
533
  {
-
 
534
    /* Return error status */
432
    return HAL_ERROR;
535
    return HAL_ERROR;
433
  }
536
  }
434
  /* Enable the capture compare 1 Interrupt */
537
  /* Enable the capture compare 1 Interrupt */
435
  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
538
  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
436
 
539
 
437
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
540
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-
 
541
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-
 
542
  {
438
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
543
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
439
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
544
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-
 
545
    {
-
 
546
      __HAL_TIM_ENABLE(htim);
-
 
547
    }
-
 
548
  }
-
 
549
  else
440
  {
550
  {
441
    __HAL_TIM_ENABLE(htim);
551
    __HAL_TIM_ENABLE(htim);
442
  }
552
  }
443
 
553
 
444
  /* Return function status */
554
  /* Return function status */
Line 454... Line 564...
454
{
564
{
455
  /* Check the parameters */
565
  /* Check the parameters */
456
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
566
  assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance));
457
 
567
 
458
  /* Disable the Input Capture channel 1
568
  /* Disable the Input Capture channel 1
459
    (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
569
  (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1,
-
 
570
  TIM_CHANNEL_2 and TIM_CHANNEL_3) */
460
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
571
  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
461
 
572
 
462
 
573
 
463
  /* Disable the capture compare Interrupts 1 event */
574
  /* Disable the capture compare Interrupts 1 event */
464
  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
575
  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
465
 
576
 
466
  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
577
  (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
-
 
578
 
467
  /* Disable the Peripheral */
579
  /* Disable the Peripheral */
468
  __HAL_TIM_DISABLE(htim);
580
  __HAL_TIM_DISABLE(htim);
469
 
581
 
-
 
582
  /* Set the TIM channel state */
-
 
583
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
584
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
585
 
470
  /* Return function status */
586
  /* Return function status */
471
  return HAL_OK;
587
  return HAL_OK;
472
}
588
}
473
 
589
 
474
/**
590
/**
Line 511... Line 627...
511
  uint32_t tmpsmcr;
627
  uint32_t tmpsmcr;
512
 
628
 
513
  /* Check the parameters */
629
  /* Check the parameters */
514
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
630
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
515
 
631
 
-
 
632
  /* Check the TIM complementary channel state */
-
 
633
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-
 
634
  {
-
 
635
    return HAL_ERROR;
-
 
636
  }
-
 
637
 
-
 
638
  /* Set the TIM complementary channel state */
-
 
639
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
640
 
516
  /* Enable the Capture compare channel N */
641
  /* Enable the Capture compare channel N */
517
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
642
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
518
 
643
 
519
  /* Enable the Main Output */
644
  /* Enable the Main Output */
520
  __HAL_TIM_MOE_ENABLE(htim);
645
  __HAL_TIM_MOE_ENABLE(htim);
521
 
646
 
522
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
647
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-
 
648
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-
 
649
  {
523
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
650
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
524
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
651
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-
 
652
    {
-
 
653
      __HAL_TIM_ENABLE(htim);
-
 
654
    }
-
 
655
  }
-
 
656
  else
525
  {
657
  {
526
    __HAL_TIM_ENABLE(htim);
658
    __HAL_TIM_ENABLE(htim);
527
  }
659
  }
528
 
660
 
529
  /* Return function status */
661
  /* Return function status */
Line 553... Line 685...
553
  __HAL_TIM_MOE_DISABLE(htim);
685
  __HAL_TIM_MOE_DISABLE(htim);
554
 
686
 
555
  /* Disable the Peripheral */
687
  /* Disable the Peripheral */
556
  __HAL_TIM_DISABLE(htim);
688
  __HAL_TIM_DISABLE(htim);
557
 
689
 
-
 
690
  /* Set the TIM complementary channel state */
-
 
691
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
 
692
 
558
  /* Return function status */
693
  /* Return function status */
559
  return HAL_OK;
694
  return HAL_OK;
560
}
695
}
561
 
696
 
562
/**
697
/**
Line 570... Line 705...
570
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
705
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
571
  * @retval HAL status
706
  * @retval HAL status
572
  */
707
  */
573
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
708
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
574
{
709
{
-
 
710
  HAL_StatusTypeDef status = HAL_OK;
575
  uint32_t tmpsmcr;
711
  uint32_t tmpsmcr;
576
 
712
 
577
  /* Check the parameters */
713
  /* Check the parameters */
578
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
714
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
579
 
715
 
-
 
716
  /* Check the TIM complementary channel state */
-
 
717
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-
 
718
  {
-
 
719
    return HAL_ERROR;
-
 
720
  }
-
 
721
 
-
 
722
  /* Set the TIM complementary channel state */
-
 
723
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
724
 
580
  switch (Channel)
725
  switch (Channel)
581
  {
726
  {
582
    case TIM_CHANNEL_1:
727
    case TIM_CHANNEL_1:
583
    {
728
    {
584
      /* Enable the TIM Output Compare interrupt */
729
      /* Enable the TIM Output Compare interrupt */
Line 600... Line 745...
600
      break;
745
      break;
601
    }
746
    }
602
 
747
 
603
 
748
 
604
    default:
749
    default:
-
 
750
      status = HAL_ERROR;
605
      break;
751
      break;
606
  }
752
  }
607
 
753
 
-
 
754
  if (status == HAL_OK)
-
 
755
  {
608
  /* Enable the TIM Break interrupt */
756
    /* Enable the TIM Break interrupt */
609
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
757
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
610
 
758
 
611
  /* Enable the Capture compare channel N */
759
    /* Enable the Capture compare channel N */
612
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
760
    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
613
 
761
 
614
  /* Enable the Main Output */
762
    /* Enable the Main Output */
615
  __HAL_TIM_MOE_ENABLE(htim);
763
    __HAL_TIM_MOE_ENABLE(htim);
616
 
764
 
617
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
765
    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-
 
766
    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-
 
767
    {
618
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
768
      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
619
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
769
      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-
 
770
      {
-
 
771
        __HAL_TIM_ENABLE(htim);
-
 
772
      }
-
 
773
    }
-
 
774
    else
620
  {
775
    {
621
    __HAL_TIM_ENABLE(htim);
776
      __HAL_TIM_ENABLE(htim);
-
 
777
    }
622
  }
778
  }
623
 
779
 
624
  /* Return function status */
780
  /* Return function status */
625
  return HAL_OK;
781
  return status;
626
}
782
}
627
 
783
 
628
/**
784
/**
629
  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
785
  * @brief  Stops the TIM Output Compare signal generation in interrupt mode
630
  *         on the complementary output.
786
  *         on the complementary output.
Line 636... Line 792...
636
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
792
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
637
  * @retval HAL status
793
  * @retval HAL status
638
  */
794
  */
639
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
795
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
640
{
796
{
-
 
797
  HAL_StatusTypeDef status = HAL_OK;
641
  uint32_t tmpccer;
798
  uint32_t tmpccer;
-
 
799
 
642
  /* Check the parameters */
800
  /* Check the parameters */
643
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
801
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
644
 
802
 
645
  switch (Channel)
803
  switch (Channel)
646
  {
804
  {
Line 664... Line 822...
664
      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
822
      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
665
      break;
823
      break;
666
    }
824
    }
667
 
825
 
668
    default:
826
    default:
-
 
827
      status = HAL_ERROR;
669
      break;
828
      break;
670
  }
829
  }
671
 
830
 
672
  /* Disable the Capture compare channel N */
-
 
673
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
 
674
 
-
 
675
  /* Disable the TIM Break interrupt (only if no more channel is active) */
-
 
676
  tmpccer = htim->Instance->CCER;
831
  if (status == HAL_OK)
677
  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
-
 
678
  {
832
  {
-
 
833
    /* Disable the Capture compare channel N */
679
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
834
    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
680
  }
-
 
681
 
835
 
-
 
836
    /* Disable the TIM Break interrupt (only if no more channel is active) */
682
  /* Disable the Main Output */
837
    tmpccer = htim->Instance->CCER;
-
 
838
    if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
-
 
839
    {
683
  __HAL_TIM_MOE_DISABLE(htim);
840
      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
-
 
841
    }
684
 
842
 
-
 
843
    /* Disable the Main Output */
-
 
844
    __HAL_TIM_MOE_DISABLE(htim);
-
 
845
 
685
  /* Disable the Peripheral */
846
    /* Disable the Peripheral */
686
  __HAL_TIM_DISABLE(htim);
847
    __HAL_TIM_DISABLE(htim);
-
 
848
 
-
 
849
    /* Set the TIM complementary channel state */
-
 
850
    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
 
851
  }
687
 
852
 
688
  /* Return function status */
853
  /* Return function status */
689
  return HAL_OK;
854
  return status;
690
}
855
}
691
 
856
 
692
/**
857
/**
693
  * @brief  Starts the TIM Output Compare signal generation in DMA mode
858
  * @brief  Starts the TIM Output Compare signal generation in DMA mode
694
  *         on the complementary output.
859
  *         on the complementary output.
Line 702... Line 867...
702
  * @param  Length The length of data to be transferred from memory to TIM peripheral
867
  * @param  Length The length of data to be transferred from memory to TIM peripheral
703
  * @retval HAL status
868
  * @retval HAL status
704
  */
869
  */
705
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
870
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
706
{
871
{
-
 
872
  HAL_StatusTypeDef status = HAL_OK;
707
  uint32_t tmpsmcr;
873
  uint32_t tmpsmcr;
708
 
874
 
709
  /* Check the parameters */
875
  /* Check the parameters */
710
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
876
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
711
 
877
 
-
 
878
  /* Set the TIM complementary channel state */
712
  if (htim->State == HAL_TIM_STATE_BUSY)
879
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
713
  {
880
  {
714
    return HAL_BUSY;
881
    return HAL_BUSY;
715
  }
882
  }
716
  else if (htim->State == HAL_TIM_STATE_READY)
883
  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
717
  {
884
  {
718
    if (((uint32_t)pData == 0U) && (Length > 0U))
885
    if ((pData == NULL) && (Length > 0U))
719
    {
886
    {
720
      return HAL_ERROR;
887
      return HAL_ERROR;
721
    }
888
    }
722
    else
889
    else
723
    {
890
    {
724
      htim->State = HAL_TIM_STATE_BUSY;
891
      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
725
    }
892
    }
726
  }
893
  }
727
  else
894
  else
728
  {
895
  {
729
    /* nothing to do  */
896
    return HAL_ERROR;
730
  }
897
  }
731
 
898
 
732
  switch (Channel)
899
  switch (Channel)
733
  {
900
  {
734
    case TIM_CHANNEL_1:
901
    case TIM_CHANNEL_1:
735
    {
902
    {
736
      /* Set the DMA compare callbacks */
903
      /* Set the DMA compare callbacks */
737
      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
904
      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
738
      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
905
      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
739
 
906
 
740
      /* Set the DMA error callback */
907
      /* Set the DMA error callback */
741
      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
908
      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
742
 
909
 
743
      /* Enable the DMA channel */
910
      /* Enable the DMA channel */
744
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
911
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
-
 
912
                           Length) != HAL_OK)
745
      {
913
      {
-
 
914
        /* Return error status */
746
        return HAL_ERROR;
915
        return HAL_ERROR;
747
      }
916
      }
748
      /* Enable the TIM Output Compare DMA request */
917
      /* Enable the TIM Output Compare DMA request */
749
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
918
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
750
      break;
919
      break;
751
    }
920
    }
752
 
921
 
753
    case TIM_CHANNEL_2:
922
    case TIM_CHANNEL_2:
754
    {
923
    {
755
      /* Set the DMA compare callbacks */
924
      /* Set the DMA compare callbacks */
756
      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
925
      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
757
      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
926
      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
758
 
927
 
759
      /* Set the DMA error callback */
928
      /* Set the DMA error callback */
760
      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
929
      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
761
 
930
 
762
      /* Enable the DMA channel */
931
      /* Enable the DMA channel */
763
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
932
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
-
 
933
                           Length) != HAL_OK)
764
      {
934
      {
-
 
935
        /* Return error status */
765
        return HAL_ERROR;
936
        return HAL_ERROR;
766
      }
937
      }
767
      /* Enable the TIM Output Compare DMA request */
938
      /* Enable the TIM Output Compare DMA request */
768
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
939
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
769
      break;
940
      break;
770
    }
941
    }
771
 
942
 
772
    case TIM_CHANNEL_3:
943
    case TIM_CHANNEL_3:
773
    {
944
    {
774
      /* Set the DMA compare callbacks */
945
      /* Set the DMA compare callbacks */
775
      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
946
      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
776
      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
947
      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
777
 
948
 
778
      /* Set the DMA error callback */
949
      /* Set the DMA error callback */
779
      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
950
      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
780
 
951
 
781
      /* Enable the DMA channel */
952
      /* Enable the DMA channel */
782
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
953
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
-
 
954
                           Length) != HAL_OK)
783
      {
955
      {
-
 
956
        /* Return error status */
784
        return HAL_ERROR;
957
        return HAL_ERROR;
785
      }
958
      }
786
      /* Enable the TIM Output Compare DMA request */
959
      /* Enable the TIM Output Compare DMA request */
787
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
960
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
788
      break;
961
      break;
789
    }
962
    }
790
 
963
 
791
    default:
964
    default:
-
 
965
      status = HAL_ERROR;
792
      break;
966
      break;
793
  }
967
  }
794
 
968
 
-
 
969
  if (status == HAL_OK)
-
 
970
  {
795
  /* Enable the Capture compare channel N */
971
    /* Enable the Capture compare channel N */
796
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
972
    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
797
 
973
 
798
  /* Enable the Main Output */
974
    /* Enable the Main Output */
799
  __HAL_TIM_MOE_ENABLE(htim);
975
    __HAL_TIM_MOE_ENABLE(htim);
800
 
976
 
801
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
977
    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-
 
978
    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-
 
979
    {
802
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
980
      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
803
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
981
      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-
 
982
      {
-
 
983
        __HAL_TIM_ENABLE(htim);
-
 
984
      }
-
 
985
    }
-
 
986
    else
804
  {
987
    {
805
    __HAL_TIM_ENABLE(htim);
988
      __HAL_TIM_ENABLE(htim);
-
 
989
    }
806
  }
990
  }
807
 
991
 
808
  /* Return function status */
992
  /* Return function status */
809
  return HAL_OK;
993
  return status;
810
}
994
}
811
 
995
 
812
/**
996
/**
813
  * @brief  Stops the TIM Output Compare signal generation in DMA mode
997
  * @brief  Stops the TIM Output Compare signal generation in DMA mode
814
  *         on the complementary output.
998
  *         on the complementary output.
Line 820... Line 1004...
820
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1004
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
821
  * @retval HAL status
1005
  * @retval HAL status
822
  */
1006
  */
823
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1007
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
824
{
1008
{
-
 
1009
  HAL_StatusTypeDef status = HAL_OK;
-
 
1010
 
825
  /* Check the parameters */
1011
  /* Check the parameters */
826
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1012
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
827
 
1013
 
828
  switch (Channel)
1014
  switch (Channel)
829
  {
1015
  {
Line 850... Line 1036...
850
      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1036
      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
851
      break;
1037
      break;
852
    }
1038
    }
853
 
1039
 
854
    default:
1040
    default:
-
 
1041
      status = HAL_ERROR;
855
      break;
1042
      break;
856
  }
1043
  }
857
 
1044
 
-
 
1045
  if (status == HAL_OK)
-
 
1046
  {
858
  /* Disable the Capture compare channel N */
1047
    /* Disable the Capture compare channel N */
859
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1048
    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
860
 
1049
 
861
  /* Disable the Main Output */
1050
    /* Disable the Main Output */
862
  __HAL_TIM_MOE_DISABLE(htim);
1051
    __HAL_TIM_MOE_DISABLE(htim);
863
 
1052
 
864
  /* Disable the Peripheral */
1053
    /* Disable the Peripheral */
865
  __HAL_TIM_DISABLE(htim);
1054
    __HAL_TIM_DISABLE(htim);
866
 
1055
 
867
  /* Change the htim state */
1056
    /* Set the TIM complementary channel state */
868
  htim->State = HAL_TIM_STATE_READY;
1057
    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
 
1058
  }
869
 
1059
 
870
  /* Return function status */
1060
  /* Return function status */
871
  return HAL_OK;
1061
  return status;
872
}
1062
}
873
 
1063
 
874
/**
1064
/**
875
  * @}
1065
  * @}
876
  */
1066
  */
Line 920... Line 1110...
920
  uint32_t tmpsmcr;
1110
  uint32_t tmpsmcr;
921
 
1111
 
922
  /* Check the parameters */
1112
  /* Check the parameters */
923
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1113
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
924
 
1114
 
-
 
1115
  /* Check the TIM complementary channel state */
-
 
1116
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-
 
1117
  {
-
 
1118
    return HAL_ERROR;
-
 
1119
  }
-
 
1120
 
-
 
1121
  /* Set the TIM complementary channel state */
-
 
1122
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
1123
 
925
  /* Enable the complementary PWM output  */
1124
  /* Enable the complementary PWM output  */
926
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1125
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
927
 
1126
 
928
  /* Enable the Main Output */
1127
  /* Enable the Main Output */
929
  __HAL_TIM_MOE_ENABLE(htim);
1128
  __HAL_TIM_MOE_ENABLE(htim);
930
 
1129
 
931
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1130
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-
 
1131
  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-
 
1132
  {
932
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1133
    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
933
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1134
    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-
 
1135
    {
-
 
1136
      __HAL_TIM_ENABLE(htim);
-
 
1137
    }
-
 
1138
  }
-
 
1139
  else
934
  {
1140
  {
935
    __HAL_TIM_ENABLE(htim);
1141
    __HAL_TIM_ENABLE(htim);
936
  }
1142
  }
937
 
1143
 
938
  /* Return function status */
1144
  /* Return function status */
Line 961... Line 1167...
961
  __HAL_TIM_MOE_DISABLE(htim);
1167
  __HAL_TIM_MOE_DISABLE(htim);
962
 
1168
 
963
  /* Disable the Peripheral */
1169
  /* Disable the Peripheral */
964
  __HAL_TIM_DISABLE(htim);
1170
  __HAL_TIM_DISABLE(htim);
965
 
1171
 
-
 
1172
  /* Set the TIM complementary channel state */
-
 
1173
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
 
1174
 
966
  /* Return function status */
1175
  /* Return function status */
967
  return HAL_OK;
1176
  return HAL_OK;
968
}
1177
}
969
 
1178
 
970
/**
1179
/**
Line 978... Line 1187...
978
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1187
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
979
  * @retval HAL status
1188
  * @retval HAL status
980
  */
1189
  */
981
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1190
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
982
{
1191
{
-
 
1192
  HAL_StatusTypeDef status = HAL_OK;
983
  uint32_t tmpsmcr;
1193
  uint32_t tmpsmcr;
984
 
1194
 
985
  /* Check the parameters */
1195
  /* Check the parameters */
986
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1196
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
987
 
1197
 
-
 
1198
  /* Check the TIM complementary channel state */
-
 
1199
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
-
 
1200
  {
-
 
1201
    return HAL_ERROR;
-
 
1202
  }
-
 
1203
 
-
 
1204
  /* Set the TIM complementary channel state */
-
 
1205
  TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
1206
 
988
  switch (Channel)
1207
  switch (Channel)
989
  {
1208
  {
990
    case TIM_CHANNEL_1:
1209
    case TIM_CHANNEL_1:
991
    {
1210
    {
992
      /* Enable the TIM Capture/Compare 1 interrupt */
1211
      /* Enable the TIM Capture/Compare 1 interrupt */
Line 1007... Line 1226...
1007
      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1226
      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1008
      break;
1227
      break;
1009
    }
1228
    }
1010
 
1229
 
1011
    default:
1230
    default:
-
 
1231
      status = HAL_ERROR;
1012
      break;
1232
      break;
1013
  }
1233
  }
1014
 
1234
 
-
 
1235
  if (status == HAL_OK)
-
 
1236
  {
1015
  /* Enable the TIM Break interrupt */
1237
    /* Enable the TIM Break interrupt */
1016
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1238
    __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
1017
 
1239
 
1018
  /* Enable the complementary PWM output  */
1240
    /* Enable the complementary PWM output  */
1019
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1241
    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1020
 
1242
 
1021
  /* Enable the Main Output */
1243
    /* Enable the Main Output */
1022
  __HAL_TIM_MOE_ENABLE(htim);
1244
    __HAL_TIM_MOE_ENABLE(htim);
1023
 
1245
 
1024
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1246
    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-
 
1247
    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-
 
1248
    {
1025
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1249
      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1026
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1250
      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-
 
1251
      {
-
 
1252
        __HAL_TIM_ENABLE(htim);
-
 
1253
      }
-
 
1254
    }
-
 
1255
    else
1027
  {
1256
    {
1028
    __HAL_TIM_ENABLE(htim);
1257
      __HAL_TIM_ENABLE(htim);
-
 
1258
    }
1029
  }
1259
  }
1030
 
1260
 
1031
  /* Return function status */
1261
  /* Return function status */
1032
  return HAL_OK;
1262
  return status;
1033
}
1263
}
1034
 
1264
 
1035
/**
1265
/**
1036
  * @brief  Stops the PWM signal generation in interrupt mode on the
1266
  * @brief  Stops the PWM signal generation in interrupt mode on the
1037
  *         complementary output.
1267
  *         complementary output.
Line 1043... Line 1273...
1043
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1273
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1044
  * @retval HAL status
1274
  * @retval HAL status
1045
  */
1275
  */
1046
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1276
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1047
{
1277
{
-
 
1278
  HAL_StatusTypeDef status = HAL_OK;
1048
  uint32_t tmpccer;
1279
  uint32_t tmpccer;
1049
 
1280
 
1050
  /* Check the parameters */
1281
  /* Check the parameters */
1051
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1282
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1052
 
1283
 
Line 1072... Line 1303...
1072
      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1303
      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1073
      break;
1304
      break;
1074
    }
1305
    }
1075
 
1306
 
1076
    default:
1307
    default:
-
 
1308
      status = HAL_ERROR;
1077
      break;
1309
      break;
1078
  }
1310
  }
1079
 
1311
 
1080
  /* Disable the complementary PWM output  */
-
 
1081
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
-
 
1082
 
-
 
1083
  /* Disable the TIM Break interrupt (only if no more channel is active) */
-
 
1084
  tmpccer = htim->Instance->CCER;
1312
  if (status == HAL_OK)
1085
  if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
-
 
1086
  {
1313
  {
1087
    __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
1314
    /* Disable the complementary PWM output  */
1088
  }
-
 
-
 
1315
    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1089
 
1316
 
-
 
1317
    /* Disable the TIM Break interrupt (only if no more channel is active) */
1090
  /* Disable the Main Output */
1318
    tmpccer = htim->Instance->CCER;
-
 
1319
    if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
-
 
1320
    {
1091
  __HAL_TIM_MOE_DISABLE(htim);
1321
      __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
-
 
1322
    }
1092
 
1323
 
-
 
1324
    /* Disable the Main Output */
-
 
1325
    __HAL_TIM_MOE_DISABLE(htim);
-
 
1326
 
1093
  /* Disable the Peripheral */
1327
    /* Disable the Peripheral */
1094
  __HAL_TIM_DISABLE(htim);
1328
    __HAL_TIM_DISABLE(htim);
-
 
1329
 
-
 
1330
    /* Set the TIM complementary channel state */
-
 
1331
    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
 
1332
  }
1095
 
1333
 
1096
  /* Return function status */
1334
  /* Return function status */
1097
  return HAL_OK;
1335
  return status;
1098
}
1336
}
1099
 
1337
 
1100
/**
1338
/**
1101
  * @brief  Starts the TIM PWM signal generation in DMA mode on the
1339
  * @brief  Starts the TIM PWM signal generation in DMA mode on the
1102
  *         complementary output
1340
  *         complementary output
Line 1110... Line 1348...
1110
  * @param  Length The length of data to be transferred from memory to TIM peripheral
1348
  * @param  Length The length of data to be transferred from memory to TIM peripheral
1111
  * @retval HAL status
1349
  * @retval HAL status
1112
  */
1350
  */
1113
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1351
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1114
{
1352
{
-
 
1353
  HAL_StatusTypeDef status = HAL_OK;
1115
  uint32_t tmpsmcr;
1354
  uint32_t tmpsmcr;
1116
 
1355
 
1117
  /* Check the parameters */
1356
  /* Check the parameters */
1118
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1357
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1119
 
1358
 
-
 
1359
  /* Set the TIM complementary channel state */
1120
  if (htim->State == HAL_TIM_STATE_BUSY)
1360
  if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1121
  {
1361
  {
1122
    return HAL_BUSY;
1362
    return HAL_BUSY;
1123
  }
1363
  }
1124
  else if (htim->State == HAL_TIM_STATE_READY)
1364
  else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1125
  {
1365
  {
1126
    if (((uint32_t)pData == 0U) && (Length > 0U))
1366
    if ((pData == NULL) && (Length > 0U))
1127
    {
1367
    {
1128
      return HAL_ERROR;
1368
      return HAL_ERROR;
1129
    }
1369
    }
1130
    else
1370
    else
1131
    {
1371
    {
1132
      htim->State = HAL_TIM_STATE_BUSY;
1372
      TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1133
    }
1373
    }
1134
  }
1374
  }
1135
  else
1375
  else
1136
  {
1376
  {
1137
    /* nothing to do */
1377
    return HAL_ERROR;
1138
  }
1378
  }
-
 
1379
 
1139
  switch (Channel)
1380
  switch (Channel)
1140
  {
1381
  {
1141
    case TIM_CHANNEL_1:
1382
    case TIM_CHANNEL_1:
1142
    {
1383
    {
1143
      /* Set the DMA compare callbacks */
1384
      /* Set the DMA compare callbacks */
1144
      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1385
      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1145
      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1386
      htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1146
 
1387
 
1147
      /* Set the DMA error callback */
1388
      /* Set the DMA error callback */
1148
      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1389
      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ;
1149
 
1390
 
1150
      /* Enable the DMA channel */
1391
      /* Enable the DMA channel */
1151
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1392
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1,
-
 
1393
                           Length) != HAL_OK)
1152
      {
1394
      {
-
 
1395
        /* Return error status */
1153
        return HAL_ERROR;
1396
        return HAL_ERROR;
1154
      }
1397
      }
1155
      /* Enable the TIM Capture/Compare 1 DMA request */
1398
      /* Enable the TIM Capture/Compare 1 DMA request */
1156
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1399
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1157
      break;
1400
      break;
1158
    }
1401
    }
1159
 
1402
 
1160
    case TIM_CHANNEL_2:
1403
    case TIM_CHANNEL_2:
1161
    {
1404
    {
1162
      /* Set the DMA compare callbacks */
1405
      /* Set the DMA compare callbacks */
1163
      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1406
      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1164
      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1407
      htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1165
 
1408
 
1166
      /* Set the DMA error callback */
1409
      /* Set the DMA error callback */
1167
      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1410
      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ;
1168
 
1411
 
1169
      /* Enable the DMA channel */
1412
      /* Enable the DMA channel */
1170
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1413
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2,
-
 
1414
                           Length) != HAL_OK)
1171
      {
1415
      {
-
 
1416
        /* Return error status */
1172
        return HAL_ERROR;
1417
        return HAL_ERROR;
1173
      }
1418
      }
1174
      /* Enable the TIM Capture/Compare 2 DMA request */
1419
      /* Enable the TIM Capture/Compare 2 DMA request */
1175
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1420
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1176
      break;
1421
      break;
1177
    }
1422
    }
1178
 
1423
 
1179
    case TIM_CHANNEL_3:
1424
    case TIM_CHANNEL_3:
1180
    {
1425
    {
1181
      /* Set the DMA compare callbacks */
1426
      /* Set the DMA compare callbacks */
1182
      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1427
      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt;
1183
      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1428
      htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1184
 
1429
 
1185
      /* Set the DMA error callback */
1430
      /* Set the DMA error callback */
1186
      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1431
      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ;
1187
 
1432
 
1188
      /* Enable the DMA channel */
1433
      /* Enable the DMA channel */
1189
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1434
      if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,
-
 
1435
                           Length) != HAL_OK)
1190
      {
1436
      {
-
 
1437
        /* Return error status */
1191
        return HAL_ERROR;
1438
        return HAL_ERROR;
1192
      }
1439
      }
1193
      /* Enable the TIM Capture/Compare 3 DMA request */
1440
      /* Enable the TIM Capture/Compare 3 DMA request */
1194
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1441
      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1195
      break;
1442
      break;
1196
    }
1443
    }
1197
 
1444
 
1198
    default:
1445
    default:
-
 
1446
      status = HAL_ERROR;
1199
      break;
1447
      break;
1200
  }
1448
  }
1201
 
1449
 
-
 
1450
  if (status == HAL_OK)
-
 
1451
  {
1202
  /* Enable the complementary PWM output  */
1452
    /* Enable the complementary PWM output  */
1203
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1453
    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
1204
 
1454
 
1205
  /* Enable the Main Output */
1455
    /* Enable the Main Output */
1206
  __HAL_TIM_MOE_ENABLE(htim);
1456
    __HAL_TIM_MOE_ENABLE(htim);
1207
 
1457
 
1208
  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1458
    /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-
 
1459
    if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
-
 
1460
    {
1209
  tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1461
      tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1210
  if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1462
      if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
-
 
1463
      {
-
 
1464
        __HAL_TIM_ENABLE(htim);
-
 
1465
      }
-
 
1466
    }
-
 
1467
    else
1211
  {
1468
    {
1212
    __HAL_TIM_ENABLE(htim);
1469
      __HAL_TIM_ENABLE(htim);
-
 
1470
    }
1213
  }
1471
  }
1214
 
1472
 
1215
  /* Return function status */
1473
  /* Return function status */
1216
  return HAL_OK;
1474
  return status;
1217
}
1475
}
1218
 
1476
 
1219
/**
1477
/**
1220
  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
1478
  * @brief  Stops the TIM PWM signal generation in DMA mode on the complementary
1221
  *         output
1479
  *         output
Line 1227... Line 1485...
1227
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1485
  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
1228
  * @retval HAL status
1486
  * @retval HAL status
1229
  */
1487
  */
1230
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1488
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1231
{
1489
{
-
 
1490
  HAL_StatusTypeDef status = HAL_OK;
-
 
1491
 
1232
  /* Check the parameters */
1492
  /* Check the parameters */
1233
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1493
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
1234
 
1494
 
1235
  switch (Channel)
1495
  switch (Channel)
1236
  {
1496
  {
Line 1257... Line 1517...
1257
      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1517
      (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1258
      break;
1518
      break;
1259
    }
1519
    }
1260
 
1520
 
1261
    default:
1521
    default:
-
 
1522
      status = HAL_ERROR;
1262
      break;
1523
      break;
1263
  }
1524
  }
1264
 
1525
 
-
 
1526
  if (status == HAL_OK)
-
 
1527
  {
1265
  /* Disable the complementary PWM output */
1528
    /* Disable the complementary PWM output */
1266
  TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1529
    TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
1267
 
1530
 
1268
  /* Disable the Main Output */
1531
    /* Disable the Main Output */
1269
  __HAL_TIM_MOE_DISABLE(htim);
1532
    __HAL_TIM_MOE_DISABLE(htim);
1270
 
1533
 
1271
  /* Disable the Peripheral */
1534
    /* Disable the Peripheral */
1272
  __HAL_TIM_DISABLE(htim);
1535
    __HAL_TIM_DISABLE(htim);
1273
 
1536
 
1274
  /* Change the htim state */
1537
    /* Set the TIM complementary channel state */
1275
  htim->State = HAL_TIM_STATE_READY;
1538
    TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
-
 
1539
  }
1276
 
1540
 
1277
  /* Return function status */
1541
  /* Return function status */
1278
  return HAL_OK;
1542
  return status;
1279
}
1543
}
1280
 
1544
 
1281
/**
1545
/**
1282
  * @}
1546
  * @}
1283
  */
1547
  */
Line 1301... Line 1565...
1301
  */
1565
  */
1302
 
1566
 
1303
/**
1567
/**
1304
  * @brief  Starts the TIM One Pulse signal generation on the complementary
1568
  * @brief  Starts the TIM One Pulse signal generation on the complementary
1305
  *         output.
1569
  *         output.
-
 
1570
  * @note OutputChannel must match the pulse output channel chosen when calling
-
 
1571
  *       @ref HAL_TIM_OnePulse_ConfigChannel().
1306
  * @param  htim TIM One Pulse handle
1572
  * @param  htim TIM One Pulse handle
1307
  * @param  OutputChannel TIM Channel to be enabled
1573
  * @param  OutputChannel pulse output channel to enable
1308
  *          This parameter can be one of the following values:
1574
  *          This parameter can be one of the following values:
1309
  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1575
  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1310
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1576
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1311
  * @retval HAL status
1577
  * @retval HAL status
1312
  */
1578
  */
1313
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1579
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1314
{
1580
{
-
 
1581
  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
-
 
1582
  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-
 
1583
  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
 
1584
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
-
 
1585
  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
 
1586
 
1315
  /* Check the parameters */
1587
  /* Check the parameters */
1316
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1588
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1317
 
1589
 
-
 
1590
  /* Check the TIM channels state */
-
 
1591
  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
1592
      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
1593
      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
1594
      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-
 
1595
  {
-
 
1596
    return HAL_ERROR;
-
 
1597
  }
-
 
1598
 
-
 
1599
  /* Set the TIM channels state */
-
 
1600
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
1601
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
1602
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
1603
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
1604
 
1318
  /* Enable the complementary One Pulse output */
1605
  /* Enable the complementary One Pulse output channel and the Input Capture channel */
1319
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1606
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
 
1607
  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1320
 
1608
 
1321
  /* Enable the Main Output */
1609
  /* Enable the Main Output */
1322
  __HAL_TIM_MOE_ENABLE(htim);
1610
  __HAL_TIM_MOE_ENABLE(htim);
1323
 
1611
 
1324
  /* Return function status */
1612
  /* Return function status */
Line 1326... Line 1614...
1326
}
1614
}
1327
 
1615
 
1328
/**
1616
/**
1329
  * @brief  Stops the TIM One Pulse signal generation on the complementary
1617
  * @brief  Stops the TIM One Pulse signal generation on the complementary
1330
  *         output.
1618
  *         output.
-
 
1619
  * @note OutputChannel must match the pulse output channel chosen when calling
-
 
1620
  *       @ref HAL_TIM_OnePulse_ConfigChannel().
1331
  * @param  htim TIM One Pulse handle
1621
  * @param  htim TIM One Pulse handle
1332
  * @param  OutputChannel TIM Channel to be disabled
1622
  * @param  OutputChannel pulse output channel to disable
1333
  *          This parameter can be one of the following values:
1623
  *          This parameter can be one of the following values:
1334
  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1624
  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1335
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1625
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1336
  * @retval HAL status
1626
  * @retval HAL status
1337
  */
1627
  */
1338
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1628
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1339
{
1629
{
-
 
1630
  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
1340
 
1631
 
1341
  /* Check the parameters */
1632
  /* Check the parameters */
1342
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1633
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1343
 
1634
 
1344
  /* Disable the complementary One Pulse output */
1635
  /* Disable the complementary One Pulse output channel and the Input Capture channel */
1345
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1636
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
 
1637
  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1346
 
1638
 
1347
  /* Disable the Main Output */
1639
  /* Disable the Main Output */
1348
  __HAL_TIM_MOE_DISABLE(htim);
1640
  __HAL_TIM_MOE_DISABLE(htim);
1349
 
1641
 
1350
  /* Disable the Peripheral */
1642
  /* Disable the Peripheral */
1351
  __HAL_TIM_DISABLE(htim);
1643
  __HAL_TIM_DISABLE(htim);
1352
 
1644
 
-
 
1645
  /* Set the TIM  channels state */
-
 
1646
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
1647
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
1648
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
1649
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
1650
 
1353
  /* Return function status */
1651
  /* Return function status */
1354
  return HAL_OK;
1652
  return HAL_OK;
1355
}
1653
}
1356
 
1654
 
1357
/**
1655
/**
1358
  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
1656
  * @brief  Starts the TIM One Pulse signal generation in interrupt mode on the
1359
  *         complementary channel.
1657
  *         complementary channel.
-
 
1658
  * @note OutputChannel must match the pulse output channel chosen when calling
-
 
1659
  *       @ref HAL_TIM_OnePulse_ConfigChannel().
1360
  * @param  htim TIM One Pulse handle
1660
  * @param  htim TIM One Pulse handle
1361
  * @param  OutputChannel TIM Channel to be enabled
1661
  * @param  OutputChannel pulse output channel to enable
1362
  *          This parameter can be one of the following values:
1662
  *          This parameter can be one of the following values:
1363
  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1663
  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1364
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1664
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1365
  * @retval HAL status
1665
  * @retval HAL status
1366
  */
1666
  */
1367
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1667
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1368
{
1668
{
-
 
1669
  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
-
 
1670
  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
-
 
1671
  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
-
 
1672
  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
-
 
1673
  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
-
 
1674
 
1369
  /* Check the parameters */
1675
  /* Check the parameters */
1370
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1676
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1371
 
1677
 
-
 
1678
  /* Check the TIM channels state */
-
 
1679
  if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
1680
      || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
1681
      || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
-
 
1682
      || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
-
 
1683
  {
-
 
1684
    return HAL_ERROR;
-
 
1685
  }
-
 
1686
 
-
 
1687
  /* Set the TIM channels state */
-
 
1688
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
1689
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
1690
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
1691
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
-
 
1692
 
1372
  /* Enable the TIM Capture/Compare 1 interrupt */
1693
  /* Enable the TIM Capture/Compare 1 interrupt */
1373
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1694
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1374
 
1695
 
1375
  /* Enable the TIM Capture/Compare 2 interrupt */
1696
  /* Enable the TIM Capture/Compare 2 interrupt */
1376
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1697
  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1377
 
1698
 
1378
  /* Enable the complementary One Pulse output */
1699
  /* Enable the complementary One Pulse output channel and the Input Capture channel */
1379
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
1700
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
-
 
1701
  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE);
1380
 
1702
 
1381
  /* Enable the Main Output */
1703
  /* Enable the Main Output */
1382
  __HAL_TIM_MOE_ENABLE(htim);
1704
  __HAL_TIM_MOE_ENABLE(htim);
1383
 
1705
 
1384
  /* Return function status */
1706
  /* Return function status */
Line 1386... Line 1708...
1386
}
1708
}
1387
 
1709
 
1388
/**
1710
/**
1389
  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
1711
  * @brief  Stops the TIM One Pulse signal generation in interrupt mode on the
1390
  *         complementary channel.
1712
  *         complementary channel.
-
 
1713
  * @note OutputChannel must match the pulse output channel chosen when calling
-
 
1714
  *       @ref HAL_TIM_OnePulse_ConfigChannel().
1391
  * @param  htim TIM One Pulse handle
1715
  * @param  htim TIM One Pulse handle
1392
  * @param  OutputChannel TIM Channel to be disabled
1716
  * @param  OutputChannel pulse output channel to disable
1393
  *          This parameter can be one of the following values:
1717
  *          This parameter can be one of the following values:
1394
  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1718
  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
1395
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1719
  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
1396
  * @retval HAL status
1720
  * @retval HAL status
1397
  */
1721
  */
1398
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1722
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
1399
{
1723
{
-
 
1724
  uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1;
-
 
1725
 
1400
  /* Check the parameters */
1726
  /* Check the parameters */
1401
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1727
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
1402
 
1728
 
1403
  /* Disable the TIM Capture/Compare 1 interrupt */
1729
  /* Disable the TIM Capture/Compare 1 interrupt */
1404
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1730
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1405
 
1731
 
1406
  /* Disable the TIM Capture/Compare 2 interrupt */
1732
  /* Disable the TIM Capture/Compare 2 interrupt */
1407
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1733
  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1408
 
1734
 
1409
  /* Disable the complementary One Pulse output */
1735
  /* Disable the complementary One Pulse output channel and the Input Capture channel */
1410
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
1736
  TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
-
 
1737
  TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE);
1411
 
1738
 
1412
  /* Disable the Main Output */
1739
  /* Disable the Main Output */
1413
  __HAL_TIM_MOE_DISABLE(htim);
1740
  __HAL_TIM_MOE_DISABLE(htim);
1414
 
1741
 
1415
  /* Disable the Peripheral */
1742
  /* Disable the Peripheral */
1416
  __HAL_TIM_DISABLE(htim);
1743
  __HAL_TIM_DISABLE(htim);
1417
 
1744
 
-
 
1745
  /* Set the TIM  channels state */
-
 
1746
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
1747
  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
1748
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
1749
  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
1750
 
1418
  /* Return function status */
1751
  /* Return function status */
1419
  return HAL_OK;
1752
  return HAL_OK;
1420
}
1753
}
1421
 
1754
 
1422
/**
1755
/**
Line 1846... Line 2179...
1846
{
2179
{
1847
  return htim->State;
2180
  return htim->State;
1848
}
2181
}
1849
 
2182
 
1850
/**
2183
/**
-
 
2184
  * @brief  Return actual state of the TIM complementary channel.
-
 
2185
  * @param  htim TIM handle
-
 
2186
  * @param  ChannelN TIM Complementary channel
-
 
2187
  *          This parameter can be one of the following values:
-
 
2188
  *            @arg TIM_CHANNEL_1: TIM Channel 1
-
 
2189
  *            @arg TIM_CHANNEL_2: TIM Channel 2
-
 
2190
  *            @arg TIM_CHANNEL_3: TIM Channel 3
-
 
2191
  * @retval TIM Complementary channel state
-
 
2192
  */
-
 
2193
HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(TIM_HandleTypeDef *htim,  uint32_t ChannelN)
-
 
2194
{
-
 
2195
  HAL_TIM_ChannelStateTypeDef channel_state;
-
 
2196
 
-
 
2197
  /* Check the parameters */
-
 
2198
  assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN));
-
 
2199
 
-
 
2200
  channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN);
-
 
2201
 
-
 
2202
  return channel_state;
-
 
2203
}
-
 
2204
/**
1851
  * @}
2205
  * @}
1852
  */
2206
  */
1853
 
2207
 
1854
/**
2208
/**
1855
  * @}
2209
  * @}
Line 1898... Line 2252...
1898
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2252
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1899
}
2253
}
1900
 
2254
 
1901
 
2255
 
1902
/**
2256
/**
-
 
2257
  * @brief  TIM DMA Delay Pulse complete callback (complementary channel).
-
 
2258
  * @param  hdma pointer to DMA handle.
-
 
2259
  * @retval None
-
 
2260
  */
-
 
2261
static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
-
 
2262
{
-
 
2263
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
 
2264
 
-
 
2265
  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-
 
2266
  {
-
 
2267
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
 
2268
 
-
 
2269
    if (hdma->Init.Mode == DMA_NORMAL)
-
 
2270
    {
-
 
2271
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
2272
    }
-
 
2273
  }
-
 
2274
  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-
 
2275
  {
-
 
2276
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
 
2277
 
-
 
2278
    if (hdma->Init.Mode == DMA_NORMAL)
-
 
2279
    {
-
 
2280
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
2281
    }
-
 
2282
  }
-
 
2283
  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-
 
2284
  {
-
 
2285
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
 
2286
 
-
 
2287
    if (hdma->Init.Mode == DMA_NORMAL)
-
 
2288
    {
-
 
2289
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
-
 
2290
    }
-
 
2291
  }
-
 
2292
  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-
 
2293
  {
-
 
2294
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-
 
2295
 
-
 
2296
    if (hdma->Init.Mode == DMA_NORMAL)
-
 
2297
    {
-
 
2298
      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
-
 
2299
    }
-
 
2300
  }
-
 
2301
  else
-
 
2302
  {
-
 
2303
    /* nothing to do */
-
 
2304
  }
-
 
2305
 
-
 
2306
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-
 
2307
  htim->PWM_PulseFinishedCallback(htim);
-
 
2308
#else
-
 
2309
  HAL_TIM_PWM_PulseFinishedCallback(htim);
-
 
2310
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
 
2311
 
-
 
2312
  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-
 
2313
}
-
 
2314
 
-
 
2315
/**
-
 
2316
  * @brief  TIM DMA error callback (complementary channel)
-
 
2317
  * @param  hdma pointer to DMA handle.
-
 
2318
  * @retval None
-
 
2319
  */
-
 
2320
static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma)
-
 
2321
{
-
 
2322
  TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
-
 
2323
 
-
 
2324
  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-
 
2325
  {
-
 
2326
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
 
2327
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
-
 
2328
  }
-
 
2329
  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-
 
2330
  {
-
 
2331
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-
 
2332
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
-
 
2333
  }
-
 
2334
  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-
 
2335
  {
-
 
2336
    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-
 
2337
    TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
-
 
2338
  }
-
 
2339
  else
-
 
2340
  {
-
 
2341
    /* nothing to do */
-
 
2342
  }
-
 
2343
 
-
 
2344
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-
 
2345
  htim->ErrorCallback(htim);
-
 
2346
#else
-
 
2347
  HAL_TIM_ErrorCallback(htim);
-
 
2348
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-
 
2349
 
-
 
2350
  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-
 
2351
}
-
 
2352
 
-
 
2353
/**
1903
  * @brief  Enables or disables the TIM Capture Compare Channel xN.
2354
  * @brief  Enables or disables the TIM Capture Compare Channel xN.
1904
  * @param  TIMx to select the TIM peripheral
2355
  * @param  TIMx to select the TIM peripheral
1905
  * @param  Channel specifies the TIM Channel
2356
  * @param  Channel specifies the TIM Channel
1906
  *          This parameter can be one of the following values:
2357
  *          This parameter can be one of the following values:
1907
  *            @arg TIM_CHANNEL_1: TIM Channel 1
2358
  *            @arg TIM_CHANNEL_1: TIM Channel 1