WebSVN – FuelGauge – Diff – /trunk/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c



  ==============================================================================
                      ##### RCC specific features #####
  ==============================================================================
    [..]  
      After reset the device is running from Internal High Speed oscillator
      (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled,
      and all peripherals are off except internal SRAM, Flash and JTAG.
      (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
          all peripherals mapped on these buses are running at HSI speed.
      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
      (+) All GPIOs are in input floating state, except the JTAG pins which

          The AHB clock (HCLK) is derived from System clock through configurable
          prescaler and used to clock the CPU, memory and peripherals mapped
          on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived
          from AHB clock through configurable prescalers and used to clock
          the peripherals mapped on these buses. You can use
          "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
 
      (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
        (++) The FLASH program/erase clock  which is always HSI 8MHz clock.
        (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
        (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.

Subversion Repositories FuelGauge

(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Src/stm32f0xx_hal_rcc.c – Rev 2 → 6

Rev 2		Rev 6
Line 12...		Line 12...
12	==============================================================================	12	==============================================================================
13	##### RCC specific features #####	13	##### RCC specific features #####
14	==============================================================================	14	==============================================================================
15	[..]	15	[..]
16	After reset the device is running from Internal High Speed oscillator	16	After reset the device is running from Internal High Speed oscillator
17	(HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,	17	(HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is disabled,
18	and all peripherals are off except internal SRAM, Flash and JTAG.	18	and all peripherals are off except internal SRAM, Flash and JTAG.
19	(+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;	19	(+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
20	all peripherals mapped on these buses are running at HSI speed.	20	all peripherals mapped on these buses are running at HSI speed.
21	(+) The clock for all peripherals is switched off, except the SRAM and FLASH.	21	(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
22	(+) All GPIOs are in input floating state, except the JTAG pins which	22	(+) All GPIOs are in input floating state, except the JTAG pins which
Line 158...		Line 158...
158	The AHB clock (HCLK) is derived from System clock through configurable	158	The AHB clock (HCLK) is derived from System clock through configurable
159	prescaler and used to clock the CPU, memory and peripherals mapped	159	prescaler and used to clock the CPU, memory and peripherals mapped
160	on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived	160	on AHB bus (DMA, GPIO...). APB1 (PCLK1) clock is derived
161	from AHB clock through configurable prescalers and used to clock	161	from AHB clock through configurable prescalers and used to clock
162	the peripherals mapped on these buses. You can use	162	the peripherals mapped on these buses. You can use
163	"@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.	163	"HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
164		164
165	(#) All the peripheral clocks are derived from the System clock (SYSCLK) except:	165	(#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
166	(++) The FLASH program/erase clock which is always HSI 8MHz clock.	166	(++) The FLASH program/erase clock which is always HSI 8MHz clock.
167	(++) The USB 48 MHz clock which is derived from the PLL VCO clock.	167	(++) The USB 48 MHz clock which is derived from the PLL VCO clock.
168	(++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.	168	(++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.