WebSVN – FuelGauge – Diff – /trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_spi.h



  */
 
/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
  * @{
  */
#define LL_SPI_RX_FIFO_TH_HALF             0x00000000U               /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */
#define LL_SPI_RX_FIFO_TH_QUARTER          (SPI_CR2_FRXTH)           /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit)  */
/**
  * @}
  */
 
/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level

  *         @arg @ref LL_SPI_NSS_HARD_INPUT
  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT
  */
__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
{
  uint32_t Ssm  = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
  uint32_t Ssoe = (READ_BIT(SPIx->CR2,  SPI_CR2_SSOE) << 16U);
  return (Ssm | Ssoe);
}
 
/**
  * @brief  Enable NSS pulse management

  * @param  SPIx SPI Instance
  * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
  */
__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
{
  return (*((__IO uint8_t *)&SPIx->DR));
}
 
/**
  * @brief  Read 16-Bits in the data register
  * @rmtoll DR           DR            LL_SPI_ReceiveData16

  */
 
/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
  * @{
  */
#define LL_I2S_DATAFORMAT_16B              0x00000000U                                   /*!< Data length 16 bits, Channel length 16bit */
#define LL_I2S_DATAFORMAT_16B_EXTENDED     (SPI_I2SCFGR_CHLEN)                           /*!< Data length 16 bits, Channel length 32bit */
#define LL_I2S_DATAFORMAT_24B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)    /*!< Data length 24 bits, Channel length 32bit */
#define LL_I2S_DATAFORMAT_32B              (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)    /*!< Data length 16 bits, Channel length 32bit */
/**
  * @}
  */
 
/** @defgroup I2S_LL_EC_POLARITY Clock Polarity

{
  return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
}
 
/**
  * @brief  Enable the master clock output (Pin MCK)
  * @rmtoll I2SPR        MCKOE         LL_I2S_EnableMasterClock
  * @param  SPIx SPI Instance
  * @retval None
  */
__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
{
  SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
}
 
/**
  * @brief  Disable the master clock output (Pin MCK)
  * @rmtoll I2SPR        MCKOE         LL_I2S_DisableMasterClock
  * @param  SPIx SPI Instance
  * @retval None
  */
__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
{
  CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
}
 
/**
  * @brief  Check if the master clock output (Pin MCK) is enabled
  * @rmtoll I2SPR        MCKOE         LL_I2S_IsEnabledMasterClock
  * @param  SPIx SPI Instance
  * @retval State of bit (1 or 0).
  */
__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)

Subversion Repositories FuelGauge

(root)/trunk/Drivers/STM32F0xx_HAL_Driver/Inc/stm32f0xx_ll_spi.h – Rev 2 → 6

Rev 2		Rev 6
Line 264...		Line 264...
264	*/	264	*/
265		265
266	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold	266	/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold
267	* @{	267	* @{
268	*/	268	*/
269	#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) /	269	#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) /
270	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) /	270	#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) /
271	/**	271	/**
272	* @}	272	* @}
273	*/	273	*/
274		274
275	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level	275	/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level
Line 846...		Line 846...
846	* @arg @ref LL_SPI_NSS_HARD_INPUT	846	* @arg @ref LL_SPI_NSS_HARD_INPUT
847	* @arg @ref LL_SPI_NSS_HARD_OUTPUT	847	* @arg @ref LL_SPI_NSS_HARD_OUTPUT
848	*/	848	*/
849	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)	849	__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)
850	{	850	{
851	register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));	851	uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM));
852	register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);	852	uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U);
853	return (Ssm \| Ssoe);	853	return (Ssm \| Ssoe);
854	}	854	}
855		855
856	/**	856	/**
857	* @brief Enable NSS pulse management	857	* @brief Enable NSS pulse management
Line 1331...		Line 1331...
1331	* @param SPIx SPI Instance	1331	* @param SPIx SPI Instance
1332	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF	1332	* @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF
1333	*/	1333	*/
1334	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)	1334	__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)
1335	{	1335	{
1336	return (uint8_t)(READ_REG(SPIx->DR));	1336	return (((__IO uint8_t )&SPIx->DR));
1337	}	1337	}
1338		1338
1339	/**	1339	/**
1340	* @brief Read 16-Bits in the data register	1340	* @brief Read 16-Bits in the data register
1341	* @rmtoll DR DR LL_SPI_ReceiveData16	1341	* @rmtoll DR DR LL_SPI_ReceiveData16
Line 1499...		Line 1499...
1499	*/	1499	*/
1500		1500
1501	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format	1501	/** @defgroup I2S_LL_EC_DATA_FORMAT Data format
1502	* @{	1502	* @{
1503	*/	1503	*/
1504	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel lenght 16bit /	1504	#define LL_I2S_DATAFORMAT_16B 0x00000000U /!< Data length 16 bits, Channel length 16bit /
1505	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel lenght 32bit /	1505	#define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /!< Data length 16 bits, Channel length 32bit /
1506	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel lenght 32bit /	1506	#define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_0) /!< Data length 24 bits, Channel length 32bit /
1507	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel lenght 32bit /	1507	#define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN \| SPI_I2SCFGR_DATLEN_1) /!< Data length 16 bits, Channel length 32bit /
1508	/**	1508	/**
1509	* @}	1509	* @}
1510	*/	1510	*/
1511		1511
1512	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity	1512	/** @defgroup I2S_LL_EC_POLARITY Clock Polarity
Line 1837...		Line 1837...
1837	{	1837	{
1838	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);	1838	return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U);
1839	}	1839	}
1840		1840
1841	/**	1841	/**
1842	* @brief Enable the master clock ouput (Pin MCK)	1842	* @brief Enable the master clock output (Pin MCK)
1843	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock	1843	* @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock
1844	* @param SPIx SPI Instance	1844	* @param SPIx SPI Instance
1845	* @retval None	1845	* @retval None
1846	*/	1846	*/
1847	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)	1847	__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)
1848	{	1848	{
1849	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);	1849	SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1850	}	1850	}
1851		1851
1852	/**	1852	/**
1853	* @brief Disable the master clock ouput (Pin MCK)	1853	* @brief Disable the master clock output (Pin MCK)
1854	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock	1854	* @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock
1855	* @param SPIx SPI Instance	1855	* @param SPIx SPI Instance
1856	* @retval None	1856	* @retval None
1857	*/	1857	*/
1858	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)	1858	__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)
1859	{	1859	{
1860	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);	1860	CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE);
1861	}	1861	}
1862		1862
1863	/**	1863	/**
1864	* @brief Check if the master clock ouput (Pin MCK) is enabled	1864	* @brief Check if the master clock output (Pin MCK) is enabled
1865	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock	1865	* @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock
1866	* @param SPIx SPI Instance	1866	* @param SPIx SPI Instance
1867	* @retval State of bit (1 or 0).	1867	* @retval State of bit (1 or 0).
1868	*/	1868	*/
1869	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)	1869	__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)