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| Rev 2 | Rev 6 | ||
|---|---|---|---|
| Line 1408... | Line 1408... | ||
| 1408 | * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA |
1408 | * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA |
| 1409 | * @retval ADC register address |
1409 | * @retval ADC register address |
| 1410 | */ |
1410 | */ |
| 1411 | __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) |
1411 | __STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) |
| 1412 | { |
1412 | { |
| - | 1413 | /* Prevent unused argument compilation warning */ |
|
| - | 1414 | (void)Register; |
|
| - | 1415 | ||
| 1413 | /* Retrieve address of register DR */ |
1416 | /* Retrieve address of register DR */ |
| 1414 | return (uint32_t)&(ADCx->DR); |
1417 | return (uint32_t)&(ADCx->DR); |
| 1415 | } |
1418 | } |
| 1416 | 1419 | ||
| 1417 | /** |
1420 | /** |
| Line 1858... | Line 1861... | ||
| 1858 | * |
1861 | * |
| 1859 | * (1) On STM32F0, parameter not available on all devices |
1862 | * (1) On STM32F0, parameter not available on all devices |
| 1860 | */ |
1863 | */ |
| 1861 | __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) |
1864 | __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) |
| 1862 | { |
1865 | { |
| 1863 | register uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); |
1866 | uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); |
| 1864 | 1867 | ||
| 1865 | /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ |
1868 | /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ |
| 1866 | /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ |
1869 | /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ |
| 1867 | register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); |
1870 | uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); |
| 1868 | 1871 | ||
| 1869 | /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ |
1872 | /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ |
| 1870 | /* to match with triggers literals definition. */ |
1873 | /* to match with triggers literals definition. */ |
| 1871 | return ((TriggerSource |
1874 | return ((TriggerSource |
| 1872 | & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL) |
1875 | & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL) |
| Line 2300... | Line 2303... | ||
| 2300 | * |
2303 | * |
| 2301 | * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB. |
2304 | * (1) On STM32F0, parameter not available on all devices: all devices except STM32F030x6, STM32F030x8, STM32F030xC, STM32F070x6, STM32F070xB. |
| 2302 | */ |
2305 | */ |
| 2303 | __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) |
2306 | __STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) |
| 2304 | { |
2307 | { |
| 2305 | register uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); |
2308 | uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); |
| 2306 | 2309 | ||
| 2307 | return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) |
2310 | return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) |
| 2308 | | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) |
2311 | | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) |
| 2309 | | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) |
2312 | | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) |
| 2310 | | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) |
2313 | | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) |
| Line 2600... | Line 2603... | ||
| 2600 | * @arg @ref LL_ADC_AWD_CHANNEL_17_REG |
2603 | * @arg @ref LL_ADC_AWD_CHANNEL_17_REG |
| 2601 | * @arg @ref LL_ADC_AWD_CHANNEL_18_REG |
2604 | * @arg @ref LL_ADC_AWD_CHANNEL_18_REG |
| 2602 | */ |
2605 | */ |
| 2603 | __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) |
2606 | __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) |
| 2604 | { |
2607 | { |
| 2605 | register uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)); |
2608 | uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)); |
| 2606 | 2609 | ||
| 2607 | /* Note: Set variable according to channel definition including channel ID */ |
2610 | /* Note: Set variable according to channel definition including channel ID */ |
| 2608 | /* with bitfield. */ |
2611 | /* with bitfield. */ |
| 2609 | register uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS); |
2612 | uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS); |
| 2610 | register uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)); |
2613 | uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)); |
| 2611 | 2614 | ||
| 2612 | return (AWDChannelGroup | (AWDChannelBitField * AWDChannelSingle)); |
2615 | return (AWDChannelGroup | (AWDChannelBitField * AWDChannelSingle)); |
| 2613 | } |
2616 | } |
| 2614 | 2617 | ||
| 2615 | /** |
2618 | /** |