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| Rev 2 | Rev 6 | ||
|---|---|---|---|
| Line 63... | Line 63... | ||
| 63 | reaches zero, an update event is generated and counting restarts |
63 | reaches zero, an update event is generated and counting restarts |
| 64 | from the RCR value (N). |
64 | from the RCR value (N). |
| 65 | This means in PWM mode that (N+1) corresponds to: |
65 | This means in PWM mode that (N+1) corresponds to: |
| 66 | - the number of PWM periods in edge-aligned mode |
66 | - the number of PWM periods in edge-aligned mode |
| 67 | - the number of half PWM period in center-aligned mode |
67 | - the number of half PWM period in center-aligned mode |
| 68 | GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. |
68 | GP timers: this parameter must be a number between Min_Data = 0x00 and |
| - | 69 | Max_Data = 0xFF. |
|
| 69 | Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
70 | Advanced timers: this parameter must be a number between Min_Data = 0x0000 and |
| - | 71 | Max_Data = 0xFFFF. */ |
|
| 70 | 72 | ||
| 71 | uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. |
73 | uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. |
| 72 | This parameter can be a value of @ref TIM_AutoReloadPreload */ |
74 | This parameter can be a value of @ref TIM_AutoReloadPreload */ |
| 73 | } TIM_Base_InitTypeDef; |
75 | } TIM_Base_InitTypeDef; |
| 74 | 76 | ||
| Line 216... | Line 218... | ||
| 216 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
218 | uint32_t ClearInputSource; /*!< TIM clear Input sources |
| 217 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
219 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
| 218 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
220 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity |
| 219 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
221 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
| 220 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
222 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler |
| 221 | This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */ |
223 | This parameter must be 0: When OCRef clear feature is used with ETR source, |
| - | 224 | ETR prescaler must be off */ |
|
| 222 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
225 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter |
| 223 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
226 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 224 | } TIM_ClearInputConfigTypeDef; |
227 | } TIM_ClearInputConfigTypeDef; |
| 225 | 228 | ||
| 226 | /** |
229 | /** |
| Line 262... | Line 265... | ||
| 262 | * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable |
265 | * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable |
| 263 | * filter and polarity. |
266 | * filter and polarity. |
| 264 | */ |
267 | */ |
| 265 | typedef struct |
268 | typedef struct |
| 266 | { |
269 | { |
| 267 | uint32_t OffStateRunMode; /*!< TIM off state in run mode |
- | |
| 268 | This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ |
270 | uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ |
| 269 | uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode |
- | |
| - | 271 | ||
| 270 | This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ |
272 | uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ |
| 271 | uint32_t LockLevel; /*!< TIM Lock level |
- | |
| - | 273 | ||
| 272 | This parameter can be a value of @ref TIM_Lock_level */ |
274 | uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ |
| 273 | uint32_t DeadTime; /*!< TIM dead Time |
- | |
| - | 275 | ||
| 274 | This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
276 | uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ |
| 275 | uint32_t BreakState; /*!< TIM Break State |
- | |
| - | 277 | ||
| 276 | This parameter can be a value of @ref TIM_Break_Input_enable_disable */ |
278 | uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ |
| 277 | uint32_t BreakPolarity; /*!< TIM Break input polarity |
- | |
| - | 279 | ||
| 278 | This parameter can be a value of @ref TIM_Break_Polarity */ |
280 | uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ |
| 279 | uint32_t BreakFilter; /*!< Specifies the break input filter. |
- | |
| - | 281 | ||
| 280 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
282 | uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
| 281 | uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state |
- | |
| - | 283 | ||
| 282 | This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
284 | uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ |
| - | 285 | ||
| 283 | } TIM_BreakDeadTimeConfigTypeDef; |
286 | } TIM_BreakDeadTimeConfigTypeDef; |
| 284 | 287 | ||
| 285 | /** |
288 | /** |
| 286 | * @brief HAL State structures definition |
289 | * @brief HAL State structures definition |
| 287 | */ |
290 | */ |
| Line 293... | Line 296... | ||
| 293 | HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
296 | HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
| 294 | HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ |
297 | HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ |
| 295 | } HAL_TIM_StateTypeDef; |
298 | } HAL_TIM_StateTypeDef; |
| 296 | 299 | ||
| 297 | /** |
300 | /** |
| - | 301 | * @brief TIM Channel States definition |
|
| - | 302 | */ |
|
| - | 303 | typedef enum |
|
| - | 304 | { |
|
| - | 305 | HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ |
|
| - | 306 | HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ |
|
| - | 307 | HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ |
|
| - | 308 | } HAL_TIM_ChannelStateTypeDef; |
|
| - | 309 | ||
| - | 310 | /** |
|
| - | 311 | * @brief DMA Burst States definition |
|
| - | 312 | */ |
|
| - | 313 | typedef enum |
|
| - | 314 | { |
|
| - | 315 | HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ |
|
| - | 316 | HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ |
|
| - | 317 | HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ |
|
| - | 318 | } HAL_TIM_DMABurstStateTypeDef; |
|
| - | 319 | ||
| - | 320 | /** |
|
| 298 | * @brief HAL Active channel structures definition |
321 | * @brief HAL Active channel structures definition |
| 299 | */ |
322 | */ |
| 300 | typedef enum |
323 | typedef enum |
| 301 | { |
324 | { |
| 302 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ |
325 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ |
| Line 313... | Line 336... | ||
| 313 | typedef struct __TIM_HandleTypeDef |
336 | typedef struct __TIM_HandleTypeDef |
| 314 | #else |
337 | #else |
| 315 | typedef struct |
338 | typedef struct |
| 316 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
339 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| 317 | { |
340 | { |
| 318 | TIM_TypeDef *Instance; /*!< Register base address */ |
341 | TIM_TypeDef *Instance; /*!< Register base address */ |
| 319 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
342 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
| 320 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
343 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
| 321 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
344 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
| 322 | This array is accessed by a @ref DMA_Handle_index */ |
345 | This array is accessed by a @ref DMA_Handle_index */ |
| 323 | HAL_LockTypeDef Lock; /*!< Locking object */ |
346 | HAL_LockTypeDef Lock; /*!< Locking object */ |
| 324 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
347 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
| - | 348 | __IO HAL_TIM_ChannelStateTypeDef ChannelState[4]; /*!< TIM channel operation state */ |
|
| - | 349 | __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ |
|
| - | 350 | __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ |
|
| 325 | 351 | ||
| 326 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
352 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| 327 | void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ |
353 | void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ |
| 328 | void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ |
354 | void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ |
| 329 | void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ |
355 | void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ |
| Line 358... | Line 384... | ||
| 358 | /** |
384 | /** |
| 359 | * @brief HAL TIM Callback ID enumeration definition |
385 | * @brief HAL TIM Callback ID enumeration definition |
| 360 | */ |
386 | */ |
| 361 | typedef enum |
387 | typedef enum |
| 362 | { |
388 | { |
| 363 | HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ |
389 | HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ |
| 364 | ,HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ |
390 | , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ |
| 365 | ,HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ |
391 | , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ |
| 366 | ,HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ |
392 | , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ |
| 367 | ,HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ |
393 | , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ |
| 368 | ,HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ |
394 | , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ |
| 369 | ,HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ |
395 | , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ |
| 370 | ,HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ |
396 | , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ |
| 371 | ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ |
397 | , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ |
| 372 | ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ |
398 | , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ |
| 373 | ,HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ |
399 | , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ |
| 374 | ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ |
400 | , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ |
| 375 | ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ |
401 | , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ |
| 376 | ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ |
402 | , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ |
| 377 | ,HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ |
403 | , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ |
| 378 | ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ |
404 | , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ |
| 379 | ,HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ |
405 | , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ |
| 380 | ,HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ |
406 | , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ |
| 381 | 407 | ||
| 382 | ,HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ |
408 | , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ |
| 383 | ,HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ |
409 | , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ |
| 384 | ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ |
410 | , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ |
| 385 | ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ |
411 | , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ |
| 386 | ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ |
412 | , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ |
| 387 | ,HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ |
413 | , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ |
| 388 | ,HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ |
414 | , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ |
| 389 | ,HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ |
415 | , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ |
| 390 | ,HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ |
416 | , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ |
| 391 | } HAL_TIM_CallbackIDTypeDef; |
417 | } HAL_TIM_CallbackIDTypeDef; |
| 392 | 418 | ||
| 393 | /** |
419 | /** |
| 394 | * @brief HAL TIM Callback pointer definition |
420 | * @brief HAL TIM Callback pointer definition |
| 395 | */ |
421 | */ |
| Line 604... | Line 630... | ||
| 604 | */ |
630 | */ |
| 605 | 631 | ||
| 606 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
632 | /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection |
| 607 | * @{ |
633 | * @{ |
| 608 | */ |
634 | */ |
| 609 | #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be |
635 | #define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ |
| 610 | connected to IC1, IC2, IC3 or IC4, respectively */ |
- | |
| 611 | #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be |
636 | #define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ |
| 612 | connected to IC2, IC1, IC4 or IC3, respectively */ |
- | |
| 613 | #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
637 | #define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
| 614 | /** |
638 | /** |
| 615 | * @} |
639 | * @} |
| 616 | */ |
640 | */ |
| 617 | 641 | ||
| Line 822... | Line 846... | ||
| 822 | 846 | ||
| 823 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable |
847 | /** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable |
| 824 | * @{ |
848 | * @{ |
| 825 | */ |
849 | */ |
| 826 | #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ |
850 | #define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ |
| 827 | #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event |
851 | #define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ |
| 828 | (if none of the break inputs BRK and BRK2 is active) */ |
- | |
| 829 | /** |
852 | /** |
| 830 | * @} |
853 | * @} |
| 831 | */ |
854 | */ |
| 832 | 855 | ||
| 833 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
856 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
| Line 930... | Line 953... | ||
| 930 | */ |
953 | */ |
| 931 | 954 | ||
| 932 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
955 | /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length |
| 933 | * @{ |
956 | * @{ |
| 934 | */ |
957 | */ |
| 935 | #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
958 | #define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 936 | #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
959 | #define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 937 | #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
960 | #define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 938 | #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
961 | #define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 939 | #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
962 | #define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 940 | #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
963 | #define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 941 | #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
964 | #define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 942 | #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
965 | #define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 943 | #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
966 | #define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 944 | #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
967 | #define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 945 | #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
968 | #define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 946 | #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
969 | #define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 947 | #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
970 | #define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 948 | #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
971 | #define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 949 | #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
972 | #define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 950 | #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
973 | #define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 951 | #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
974 | #define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 952 | #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */ |
975 | #define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ |
| 953 | /** |
976 | /** |
| 954 | * @} |
977 | * @} |
| 955 | */ |
978 | */ |
| 956 | 979 | ||
| 957 | /** @defgroup DMA_Handle_index TIM DMA Handle Index |
980 | /** @defgroup DMA_Handle_index TIM DMA Handle Index |
| Line 992... | Line 1015... | ||
| 992 | /** @brief Reset TIM handle state. |
1015 | /** @brief Reset TIM handle state. |
| 993 | * @param __HANDLE__ TIM handle. |
1016 | * @param __HANDLE__ TIM handle. |
| 994 | * @retval None |
1017 | * @retval None |
| 995 | */ |
1018 | */ |
| 996 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
1019 | #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) |
| 997 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
1020 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
| 998 | (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ |
1021 | (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ |
| - | 1022 | (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1023 | (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1024 | (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1025 | (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1026 | (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1027 | (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1028 | (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1029 | (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1030 | (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ |
|
| 999 | (__HANDLE__)->Base_MspInitCallback = NULL; \ |
1031 | (__HANDLE__)->Base_MspInitCallback = NULL; \ |
| 1000 | (__HANDLE__)->Base_MspDeInitCallback = NULL; \ |
1032 | (__HANDLE__)->Base_MspDeInitCallback = NULL; \ |
| 1001 | (__HANDLE__)->IC_MspInitCallback = NULL; \ |
1033 | (__HANDLE__)->IC_MspInitCallback = NULL; \ |
| 1002 | (__HANDLE__)->IC_MspDeInitCallback = NULL; \ |
1034 | (__HANDLE__)->IC_MspDeInitCallback = NULL; \ |
| 1003 | (__HANDLE__)->OC_MspInitCallback = NULL; \ |
1035 | (__HANDLE__)->OC_MspInitCallback = NULL; \ |
| 1004 | (__HANDLE__)->OC_MspDeInitCallback = NULL; \ |
1036 | (__HANDLE__)->OC_MspDeInitCallback = NULL; \ |
| 1005 | (__HANDLE__)->PWM_MspInitCallback = NULL; \ |
1037 | (__HANDLE__)->PWM_MspInitCallback = NULL; \ |
| 1006 | (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ |
1038 | (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ |
| 1007 | (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ |
1039 | (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ |
| 1008 | (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ |
1040 | (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ |
| 1009 | (__HANDLE__)->Encoder_MspInitCallback = NULL; \ |
1041 | (__HANDLE__)->Encoder_MspInitCallback = NULL; \ |
| 1010 | (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ |
1042 | (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ |
| 1011 | (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ |
1043 | (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ |
| 1012 | (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ |
1044 | (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ |
| 1013 | } while(0) |
1045 | } while(0) |
| 1014 | #else |
1046 | #else |
| 1015 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
1047 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ |
| - | 1048 | (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ |
|
| - | 1049 | (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1050 | (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1051 | (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1052 | (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1053 | (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1054 | (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1055 | (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1056 | (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ |
|
| - | 1057 | (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ |
|
| - | 1058 | } while(0) |
|
| 1016 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
1059 | #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ |
| 1017 | 1060 | ||
| 1018 | /** |
1061 | /** |
| 1019 | * @brief Enable the TIM peripheral. |
1062 | * @brief Enable the TIM peripheral. |
| 1020 | * @param __HANDLE__ TIM handle |
1063 | * @param __HANDLE__ TIM handle |
| Line 1047... | Line 1090... | ||
| 1047 | 1090 | ||
| 1048 | /** |
1091 | /** |
| 1049 | * @brief Disable the TIM main Output. |
1092 | * @brief Disable the TIM main Output. |
| 1050 | * @param __HANDLE__ TIM handle |
1093 | * @param __HANDLE__ TIM handle |
| 1051 | * @retval None |
1094 | * @retval None |
| 1052 | * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled |
1095 | * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been |
| - | 1096 | * disabled |
|
| 1053 | */ |
1097 | */ |
| 1054 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
1098 | #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ |
| 1055 | do { \ |
1099 | do { \ |
| 1056 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ |
1100 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ |
| 1057 | { \ |
1101 | { \ |
| Line 1208... | Line 1252... | ||
| 1208 | 1252 | ||
| 1209 | /** |
1253 | /** |
| 1210 | * @brief Indicates whether or not the TIM Counter is used as downcounter. |
1254 | * @brief Indicates whether or not the TIM Counter is used as downcounter. |
| 1211 | * @param __HANDLE__ TIM handle. |
1255 | * @param __HANDLE__ TIM handle. |
| 1212 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
1256 | * @retval False (Counter used as upcounter) or True (Counter used as downcounter) |
| 1213 | * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder |
1257 | * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode |
| 1214 | mode. |
1258 | * or Encoder mode. |
| 1215 | */ |
1259 | */ |
| 1216 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
1260 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
| 1217 | 1261 | ||
| 1218 | /** |
1262 | /** |
| 1219 | * @brief Set the TIM Prescaler on runtime. |
1263 | * @brief Set the TIM Prescaler on runtime. |
| Line 1283... | Line 1327... | ||
| 1283 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
1327 | * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT |
| 1284 | */ |
1328 | */ |
| 1285 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
1329 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
| 1286 | 1330 | ||
| 1287 | /** |
1331 | /** |
| 1288 | * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. |
1332 | * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() |
| - | 1333 | * function. |
|
| 1289 | * @param __HANDLE__ TIM handle. |
1334 | * @param __HANDLE__ TIM handle. |
| 1290 | * @param __CHANNEL__ TIM Channels to be configured. |
1335 | * @param __CHANNEL__ TIM Channels to be configured. |
| 1291 | * This parameter can be one of the following values: |
1336 | * This parameter can be one of the following values: |
| 1292 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
1337 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
| 1293 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
1338 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
| Line 1710... | Line 1755... | ||
| 1710 | #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
1755 | #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
| 1711 | 1756 | ||
| 1712 | #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ |
1757 | #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ |
| 1713 | ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) |
1758 | ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) |
| 1714 | 1759 | ||
| 1715 | #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
1760 | #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ |
| 1716 | ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
1761 | ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
| 1717 | ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
1762 | ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
| 1718 | ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
1763 | ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
| 1719 | ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
1764 | ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
| 1720 | ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
1765 | ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
| 1721 | ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
1766 | ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
| 1722 | ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
1767 | ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
| 1723 | ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
1768 | ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ |
| 1724 | ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
1769 | ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
| 1725 | ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
1770 | ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ |
| 1726 | ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
1771 | ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
| 1727 | ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
1772 | ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
| 1728 | ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
1773 | ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
| Line 1761... | Line 1806... | ||
| 1761 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
1806 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
| 1762 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
1807 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
| 1763 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
1808 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
| 1764 | ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) |
1809 | ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) |
| 1765 | 1810 | ||
| - | 1811 | #define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ |
|
| - | 1812 | (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ |
|
| - | 1813 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ |
|
| - | 1814 | ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ |
|
| - | 1815 | (__HANDLE__)->ChannelState[3]) |
|
| - | 1816 | ||
| - | 1817 | #define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ |
|
| - | 1818 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ |
|
| - | 1819 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ |
|
| - | 1820 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ |
|
| - | 1821 | ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__))) |
|
| - | 1822 | ||
| - | 1823 | #define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ |
|
| - | 1824 | (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ |
|
| - | 1825 | (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ |
|
| - | 1826 | (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ |
|
| - | 1827 | (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ |
|
| - | 1828 | } while(0) |
|
| - | 1829 | ||
| - | 1830 | #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ |
|
| - | 1831 | (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ |
|
| - | 1832 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ |
|
| - | 1833 | ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ |
|
| - | 1834 | (__HANDLE__)->ChannelNState[3]) |
|
| - | 1835 | ||
| - | 1836 | #define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ |
|
| - | 1837 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ |
|
| - | 1838 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ |
|
| - | 1839 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ |
|
| - | 1840 | ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) |
|
| - | 1841 | ||
| - | 1842 | #define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ |
|
| - | 1843 | (__HANDLE__)->ChannelNState[0] = \ |
|
| - | 1844 | (__CHANNEL_STATE__); \ |
|
| - | 1845 | (__HANDLE__)->ChannelNState[1] = \ |
|
| - | 1846 | (__CHANNEL_STATE__); \ |
|
| - | 1847 | (__HANDLE__)->ChannelNState[2] = \ |
|
| - | 1848 | (__CHANNEL_STATE__); \ |
|
| - | 1849 | (__HANDLE__)->ChannelNState[3] = \ |
|
| - | 1850 | (__CHANNEL_STATE__); \ |
|
| - | 1851 | } while(0) |
|
| - | 1852 | ||
| 1766 | /** |
1853 | /** |
| 1767 | * @} |
1854 | * @} |
| 1768 | */ |
1855 | */ |
| 1769 | /* End of private macros -----------------------------------------------------*/ |
1856 | /* End of private macros -----------------------------------------------------*/ |
| 1770 | 1857 | ||
| Line 1933... | Line 2020... | ||
| 1933 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); |
2020 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); |
| 1934 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); |
2021 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); |
| 1935 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
2022 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
| 1936 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); |
2023 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); |
| 1937 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
2024 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
| 1938 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, |
2025 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, |
| 1939 | uint32_t DataLength); |
2026 | uint32_t BurstLength, uint32_t DataLength); |
| 1940 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
2027 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
| 1941 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
2028 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
| 1942 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); |
2029 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); |
| 1943 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
2030 | HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, |
| 1944 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength, |
2031 | uint32_t BurstRequestSrc, uint32_t *BurstBuffer, |
| 1945 | uint32_t DataLength); |
2032 | uint32_t BurstLength, uint32_t DataLength); |
| 1946 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
2033 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
| 1947 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
2034 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
| 1948 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
2035 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
| 1949 | /** |
2036 | /** |
| 1950 | * @} |
2037 | * @} |
| Line 1986... | Line 2073... | ||
| 1986 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
2073 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
| 1987 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
2074 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
| 1988 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
2075 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
| 1989 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
2076 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
| 1990 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
2077 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
| - | 2078 | ||
| - | 2079 | /* Peripheral Channel state functions ************************************************/ |
|
| - | 2080 | HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim); |
|
| - | 2081 | HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel); |
|
| - | 2082 | HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim); |
|
| 1991 | /** |
2083 | /** |
| 1992 | * @} |
2084 | * @} |
| 1993 | */ |
2085 | */ |
| 1994 | 2086 | ||
| 1995 | /** |
2087 | /** |
| Line 2005... | Line 2097... | ||
| 2005 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
2097 | void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); |
| 2006 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
2098 | void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); |
| 2007 | void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, |
2099 | void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, |
| 2008 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); |
2100 | uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); |
| 2009 | 2101 | ||
| 2010 | void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
- | |
| 2011 | void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); |
2102 | void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); |
| 2012 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
2103 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
| 2013 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
2104 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
| 2014 | void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); |
2105 | void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); |
| 2015 | void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); |
2106 | void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); |