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| 46 | * @{ |
46 | * @{ |
| 47 | */ |
47 | */ |
| 48 | typedef struct |
48 | typedef struct |
| 49 | { |
49 | { |
| 50 | uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. |
50 | uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. |
| 51 | This parameter calculated by referring to SMBUS initialization |
51 | This parameter calculated by referring to SMBUS initialization section |
| 52 | section in Reference manual */ |
52 | in Reference manual */ |
| 53 | uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. |
53 | uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. |
| 54 | This parameter can be a value of @ref SMBUS_Analog_Filter */ |
54 | This parameter can be a value of @ref SMBUS_Analog_Filter */ |
| 55 | 55 | ||
| 56 | uint32_t OwnAddress1; /*!< Specifies the first device own address. |
56 | uint32_t OwnAddress1; /*!< Specifies the first device own address. |
| 57 | This parameter can be a 7-bit or 10-bit address. */ |
57 | This parameter can be a 7-bit or 10-bit address. */ |
| 58 | 58 | ||
| 59 | uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. |
59 | uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. |
| 60 | This parameter can be a value of @ref SMBUS_addressing_mode */ |
60 | This parameter can be a value of @ref SMBUS_addressing_mode */ |
| 61 | 61 | ||
| 62 | uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. |
62 | uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. |
| 63 | This parameter can be a value of @ref SMBUS_dual_addressing_mode */ |
63 | This parameter can be a value of @ref SMBUS_dual_addressing_mode */ |
| 64 | 64 | ||
| 65 | uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected |
65 | uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected |
| 66 | This parameter can be a 7-bit address. */ |
66 | This parameter can be a 7-bit address. */ |
| 67 | 67 | ||
| 68 | uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected |
68 | uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address |
| - | 69 | if dual addressing mode is selected |
|
| 69 | This parameter can be a value of @ref SMBUS_own_address2_masks. */ |
70 | This parameter can be a value of @ref SMBUS_own_address2_masks. */ |
| 70 | 71 | ||
| 71 | uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. |
72 | uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. |
| 72 | This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ |
73 | This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ |
| 73 | 74 | ||
| 74 | uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. |
75 | uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. |
| 75 | This parameter can be a value of @ref SMBUS_nostretch_mode */ |
76 | This parameter can be a value of @ref SMBUS_nostretch_mode */ |
| 76 | 77 | ||
| 77 | uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. |
78 | uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. |
| 78 | This parameter can be a value of @ref SMBUS_packet_error_check_mode */ |
79 | This parameter can be a value of @ref SMBUS_packet_error_check_mode */ |
| 79 | 80 | ||
| 80 | uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. |
81 | uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. |
| 81 | This parameter can be a value of @ref SMBUS_peripheral_mode */ |
82 | This parameter can be a value of @ref SMBUS_peripheral_mode */ |
| 82 | 83 | ||
| 83 | uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. |
84 | uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. |
| 84 | (Enable bits and different timeout values) |
85 | (Enable bits and different timeout values) |
| 85 | This parameter calculated by referring to SMBUS initialization |
86 | This parameter calculated by referring to SMBUS initialization section |
| 86 | section in Reference manual */ |
87 | in Reference manual */ |
| 87 | } SMBUS_InitTypeDef; |
88 | } SMBUS_InitTypeDef; |
| 88 | /** |
89 | /** |
| 89 | * @} |
90 | * @} |
| 90 | */ |
91 | */ |
| 91 | 92 | ||
| Line 100... | Line 101... | ||
| 100 | #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ |
101 | #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ |
| 101 | #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ |
102 | #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ |
| 102 | #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ |
103 | #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ |
| 103 | #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ |
104 | #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ |
| 104 | #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ |
105 | #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ |
| 105 | #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ |
106 | #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ |
| 106 | /** |
107 | /** |
| 107 | * @} |
108 | * @} |
| 108 | */ |
109 | */ |
| 109 | 110 | ||
| 110 | /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition |
111 | /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition |
| Line 119... | Line 120... | ||
| 119 | #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ |
120 | #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ |
| 120 | #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ |
121 | #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ |
| 121 | #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ |
122 | #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ |
| 122 | #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ |
123 | #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ |
| 123 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
124 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
| 124 | #define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ |
125 | #define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ |
| 125 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
126 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
| 126 | #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ |
127 | #define HAL_SMBUS_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ |
| 127 | /** |
128 | /** |
| 128 | * @} |
129 | * @} |
| 129 | */ |
130 | */ |
| 130 | 131 | ||
| 131 | /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition |
132 | /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition |
| 132 | * @brief SMBUS handle Structure definition |
133 | * @brief SMBUS handle Structure definition |
| 133 | * @{ |
134 | * @{ |
| 134 | */ |
135 | */ |
| - | 136 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
|
| 135 | typedef struct __SMBUS_HandleTypeDef |
137 | typedef struct __SMBUS_HandleTypeDef |
| - | 138 | #else |
|
| - | 139 | typedef struct |
|
| - | 140 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
|
| 136 | { |
141 | { |
| 137 | I2C_TypeDef *Instance; /*!< SMBUS registers base address */ |
142 | I2C_TypeDef *Instance; /*!< SMBUS registers base address */ |
| 138 | 143 | ||
| 139 | SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ |
144 | SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ |
| 140 | 145 | ||
| Line 153... | Line 158... | ||
| 153 | __IO uint32_t State; /*!< SMBUS communication state */ |
158 | __IO uint32_t State; /*!< SMBUS communication state */ |
| 154 | 159 | ||
| 155 | __IO uint32_t ErrorCode; /*!< SMBUS Error code */ |
160 | __IO uint32_t ErrorCode; /*!< SMBUS Error code */ |
| 156 | 161 | ||
| 157 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
162 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
| 158 | void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ |
163 | void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
| - | 164 | /*!< SMBUS Master Tx Transfer completed callback */ |
|
| 159 | void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ |
165 | void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
| - | 166 | /*!< SMBUS Master Rx Transfer completed callback */ |
|
| 160 | void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ |
167 | void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
| - | 168 | /*!< SMBUS Slave Tx Transfer completed callback */ |
|
| 161 | void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ |
169 | void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
| - | 170 | /*!< SMBUS Slave Rx Transfer completed callback */ |
|
| 162 | void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ |
171 | void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
| - | 172 | /*!< SMBUS Listen Complete callback */ |
|
| 163 | void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ |
173 | void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
| - | 174 | /*!< SMBUS Error callback */ |
|
| 164 | 175 | ||
| 165 | void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ |
176 | void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); |
| - | 177 | /*!< SMBUS Slave Address Match callback */ |
|
| 166 | 178 | ||
| 167 | void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ |
179 | void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
| - | 180 | /*!< SMBUS Msp Init callback */ |
|
| 168 | void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ |
181 | void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); |
| - | 182 | /*!< SMBUS Msp DeInit callback */ |
|
| 169 | 183 | ||
| 170 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
184 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
| 171 | } SMBUS_HandleTypeDef; |
185 | } SMBUS_HandleTypeDef; |
| 172 | 186 | ||
| 173 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
187 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
| Line 189... | Line 203... | ||
| 189 | } HAL_SMBUS_CallbackIDTypeDef; |
203 | } HAL_SMBUS_CallbackIDTypeDef; |
| 190 | 204 | ||
| 191 | /** |
205 | /** |
| 192 | * @brief HAL SMBUS Callback pointer definition |
206 | * @brief HAL SMBUS Callback pointer definition |
| 193 | */ |
207 | */ |
| 194 | typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */ |
208 | typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); |
| - | 209 | /*!< pointer to an SMBUS callback function */ |
|
| 195 | typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */ |
210 | typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, |
| - | 211 | uint16_t AddrMatchCode); |
|
| - | 212 | /*!< pointer to an SMBUS Address Match callback function */ |
|
| 196 | 213 | ||
| 197 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
214 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
| 198 | /** |
215 | /** |
| 199 | * @} |
216 | * @} |
| 200 | */ |
217 | */ |
| Line 324... | Line 341... | ||
| 324 | */ |
341 | */ |
| 325 | #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE |
342 | #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE |
| 326 | #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) |
343 | #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) |
| 327 | #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
344 | #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
| 328 | #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
345 | #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE |
| - | 346 | #define SMBUS_FIRST_FRAME_WITH_PEC ((uint32_t)(SMBUS_SOFTEND_MODE | SMBUS_SENDPEC_MODE)) |
|
| 329 | #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
347 | #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
| 330 | #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
348 | #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) |
| 331 | 349 | ||
| 332 | /* List of XferOptions in usage of : |
350 | /* List of XferOptions in usage of : |
| 333 | * 1- Restart condition in all use cases (direction change or not) |
351 | * 1- Restart condition in all use cases (direction change or not) |
| Line 351... | Line 369... | ||
| 351 | #define SMBUS_IT_STOPI I2C_CR1_STOPIE |
369 | #define SMBUS_IT_STOPI I2C_CR1_STOPIE |
| 352 | #define SMBUS_IT_NACKI I2C_CR1_NACKIE |
370 | #define SMBUS_IT_NACKI I2C_CR1_NACKIE |
| 353 | #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE |
371 | #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE |
| 354 | #define SMBUS_IT_RXI I2C_CR1_RXIE |
372 | #define SMBUS_IT_RXI I2C_CR1_RXIE |
| 355 | #define SMBUS_IT_TXI I2C_CR1_TXIE |
373 | #define SMBUS_IT_TXI I2C_CR1_TXIE |
| 356 | #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) |
374 | #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | \ |
| - | 375 | SMBUS_IT_NACKI | SMBUS_IT_TXI) |
|
| 357 | #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) |
376 | #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | \ |
| - | 377 | SMBUS_IT_RXI) |
|
| 358 | #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) |
378 | #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) |
| 359 | #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) |
379 | #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) |
| 360 | /** |
380 | /** |
| 361 | * @} |
381 | * @} |
| 362 | */ |
382 | */ |
| Line 400... | Line 420... | ||
| 400 | /** @brief Reset SMBUS handle state. |
420 | /** @brief Reset SMBUS handle state. |
| 401 | * @param __HANDLE__ specifies the SMBUS Handle. |
421 | * @param __HANDLE__ specifies the SMBUS Handle. |
| 402 | * @retval None |
422 | * @retval None |
| 403 | */ |
423 | */ |
| 404 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
424 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
| 405 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
425 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ |
| 406 | (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ |
426 | (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ |
| 407 | (__HANDLE__)->MspInitCallback = NULL; \ |
427 | (__HANDLE__)->MspInitCallback = NULL; \ |
| 408 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
428 | (__HANDLE__)->MspDeInitCallback = NULL; \ |
| 409 | } while(0) |
429 | } while(0) |
| 410 | #else |
430 | #else |
| 411 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) |
431 | #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) |
| 412 | #endif |
432 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
| 413 | 433 | ||
| 414 | /** @brief Enable the specified SMBUS interrupts. |
434 | /** @brief Enable the specified SMBUS interrupts. |
| 415 | * @param __HANDLE__ specifies the SMBUS Handle. |
435 | * @param __HANDLE__ specifies the SMBUS Handle. |
| 416 | * @param __INTERRUPT__ specifies the interrupt source to enable. |
436 | * @param __INTERRUPT__ specifies the interrupt source to enable. |
| 417 | * This parameter can be one of the following values: |
437 | * This parameter can be one of the following values: |
| Line 455... | Line 475... | ||
| 455 | * @arg @ref SMBUS_IT_RXI RX interrupt enable |
475 | * @arg @ref SMBUS_IT_RXI RX interrupt enable |
| 456 | * @arg @ref SMBUS_IT_TXI TX interrupt enable |
476 | * @arg @ref SMBUS_IT_TXI TX interrupt enable |
| 457 | * |
477 | * |
| 458 | * @retval The new state of __IT__ (SET or RESET). |
478 | * @retval The new state of __IT__ (SET or RESET). |
| 459 | */ |
479 | */ |
| - | 480 | #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ |
|
| 460 | #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
481 | ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
| 461 | 482 | ||
| 462 | /** @brief Check whether the specified SMBUS flag is set or not. |
483 | /** @brief Check whether the specified SMBUS flag is set or not. |
| 463 | * @param __HANDLE__ specifies the SMBUS Handle. |
484 | * @param __HANDLE__ specifies the SMBUS Handle. |
| 464 | * @param __FLAG__ specifies the flag to check. |
485 | * @param __FLAG__ specifies the flag to check. |
| 465 | * This parameter can be one of the following values: |
486 | * This parameter can be one of the following values: |
| Line 481... | Line 502... | ||
| 481 | * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) |
502 | * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) |
| 482 | * |
503 | * |
| 483 | * @retval The new state of __FLAG__ (SET or RESET). |
504 | * @retval The new state of __FLAG__ (SET or RESET). |
| 484 | */ |
505 | */ |
| 485 | #define SMBUS_FLAG_MASK (0x0001FFFFU) |
506 | #define SMBUS_FLAG_MASK (0x0001FFFFU) |
| - | 507 | #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) \ |
|
| 486 | #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) |
508 | (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ |
| - | 509 | ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) |
|
| 487 | 510 | ||
| 488 | /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. |
511 | /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. |
| 489 | * @param __HANDLE__ specifies the SMBUS Handle. |
512 | * @param __HANDLE__ specifies the SMBUS Handle. |
| 490 | * @param __FLAG__ specifies the flag to clear. |
513 | * @param __FLAG__ specifies the flag to clear. |
| 491 | * This parameter can be any combination of the following values: |
514 | * This parameter can be any combination of the following values: |
| Line 532... | Line 555... | ||
| 532 | /** @defgroup SMBUS_Private_Macro SMBUS Private Macros |
555 | /** @defgroup SMBUS_Private_Macro SMBUS Private Macros |
| 533 | * @{ |
556 | * @{ |
| 534 | */ |
557 | */ |
| 535 | 558 | ||
| 536 | #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ |
559 | #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ |
| 537 | ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) |
560 | ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) |
| 538 | 561 | ||
| 539 | #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) |
562 | #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) |
| 540 | 563 | ||
| 541 | #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ |
564 | #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ |
| 542 | ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) |
565 | ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) |
| 543 | 566 | ||
| 544 | #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ |
567 | #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ |
| 545 | ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) |
568 | ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) |
| 546 | 569 | ||
| 547 | #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ |
570 | #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ |
| 548 | ((MASK) == SMBUS_OA2_MASK01) || \ |
571 | ((MASK) == SMBUS_OA2_MASK01) || \ |
| 549 | ((MASK) == SMBUS_OA2_MASK02) || \ |
572 | ((MASK) == SMBUS_OA2_MASK02) || \ |
| 550 | ((MASK) == SMBUS_OA2_MASK03) || \ |
573 | ((MASK) == SMBUS_OA2_MASK03) || \ |
| Line 558... | Line 581... | ||
| 558 | 581 | ||
| 559 | #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ |
582 | #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ |
| 560 | ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) |
583 | ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) |
| 561 | 584 | ||
| 562 | #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ |
585 | #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ |
| 563 | ((PEC) == SMBUS_PEC_ENABLE)) |
586 | ((PEC) == SMBUS_PEC_ENABLE)) |
| 564 | 587 | ||
| 565 | #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ |
588 | #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ |
| 566 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ |
589 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ |
| 567 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) |
590 | ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) |
| 568 | 591 | ||
| 569 | #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ |
592 | #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ |
| 570 | ((MODE) == SMBUS_AUTOEND_MODE) || \ |
593 | ((MODE) == SMBUS_AUTOEND_MODE) || \ |
| 571 | ((MODE) == SMBUS_SOFTEND_MODE) || \ |
594 | ((MODE) == SMBUS_SOFTEND_MODE) || \ |
| 572 | ((MODE) == SMBUS_SENDPEC_MODE) || \ |
595 | ((MODE) == SMBUS_SENDPEC_MODE) || \ |
| 573 | ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ |
596 | ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ |
| 574 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ |
597 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ |
| 575 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ |
598 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ |
| 576 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) |
599 | ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | \ |
| - | 600 | SMBUS_RELOAD_MODE ))) |
|
| 577 | 601 | ||
| 578 | 602 | ||
| 579 | #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ |
603 | #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ |
| 580 | ((REQUEST) == SMBUS_GENERATE_START_READ) || \ |
604 | ((REQUEST) == SMBUS_GENERATE_START_READ) || \ |
| 581 | ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ |
605 | ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ |
| 582 | ((REQUEST) == SMBUS_NO_STARTSTOP)) |
606 | ((REQUEST) == SMBUS_NO_STARTSTOP)) |
| 583 | 607 | ||
| 584 | 608 | ||
| 585 | #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ |
609 | #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) || \ |
| 586 | ((REQUEST) == SMBUS_FIRST_FRAME) || \ |
610 | ((REQUEST) == SMBUS_FIRST_FRAME) || \ |
| 587 | ((REQUEST) == SMBUS_NEXT_FRAME) || \ |
611 | ((REQUEST) == SMBUS_NEXT_FRAME) || \ |
| 588 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ |
612 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ |
| 589 | ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ |
613 | ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ |
| - | 614 | ((REQUEST) == SMBUS_FIRST_FRAME_WITH_PEC) || \ |
|
| 590 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ |
615 | ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ |
| 591 | ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) |
616 | ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)) |
| 592 | 617 | ||
| 593 | #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ |
618 | #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ |
| 594 | ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ |
619 | ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ |
| 595 | ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ |
620 | ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ |
| 596 | ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) |
621 | ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) |
| 597 | 622 | ||
| - | 623 | #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= \ |
|
| 598 | #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) |
624 | (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | \ |
| - | 625 | I2C_CR1_PECEN))) |
|
| - | 626 | #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ |
|
| 599 | #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) |
627 | (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ |
| - | 628 | I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ |
|
| - | 629 | I2C_CR2_RD_WRN))) |
|
| 600 | 630 | ||
| 601 | #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ |
631 | #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? \ |
| 602 | (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) |
632 | (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ |
| - | 633 | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ |
|
| - | 634 | (~I2C_CR2_RD_WRN)) : \ |
|
| - | 635 | (uint32_t)((((uint32_t)(__ADDRESS__) & \ |
|
| - | 636 | (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | \ |
|
| - | 637 | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) |
|
| 603 | 638 | ||
| 604 | #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) |
639 | #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) |
| 605 | #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) |
640 | #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) |
| 606 | #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) |
641 | #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) |
| 607 | #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) |
642 | #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) |
| 608 | #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) |
643 | #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) |
| 609 | 644 | ||
| 610 | #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) |
645 | #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == \ |
| - | 646 | ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET) |
|
| 611 | #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) |
647 | #define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) |
| 612 | 648 | ||
| 613 | #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) |
649 | #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) |
| 614 | #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) |
650 | #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) |
| 615 | 651 | ||
| 616 | /** |
652 | /** |
| 617 | * @} |
653 | * @} |
| 618 | */ |
654 | */ |
| 619 | 655 | ||
| - | 656 | ||
| 620 | /* Exported functions --------------------------------------------------------*/ |
657 | /* Exported functions --------------------------------------------------------*/ |
| 621 | /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions |
658 | /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions |
| 622 | * @{ |
659 | * @{ |
| 623 | */ |
660 | */ |
| 624 | 661 | ||
| 625 | /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions |
662 | /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions |
| 626 | * @{ |
663 | * @{ |
| 627 | */ |
664 | */ |
| 628 | 665 | ||
| 629 | /* Initialization and de-initialization functions ****************************/ |
666 | /* Initialization and de-initialization functions ****************************/ |
| 630 | HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); |
667 | HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); |
| 631 | HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); |
668 | HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); |
| 632 | void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); |
669 | void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); |
| Line 634... | Line 671... | ||
| 634 | HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); |
671 | HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); |
| 635 | HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); |
672 | HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); |
| 636 | 673 | ||
| 637 | /* Callbacks Register/UnRegister functions ***********************************/ |
674 | /* Callbacks Register/UnRegister functions ***********************************/ |
| 638 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
675 | #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) |
| 639 | HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); |
676 | HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, |
| - | 677 | HAL_SMBUS_CallbackIDTypeDef CallbackID, |
|
| - | 678 | pSMBUS_CallbackTypeDef pCallback); |
|
| 640 | HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); |
679 | HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, |
| - | 680 | HAL_SMBUS_CallbackIDTypeDef CallbackID); |
|
| 641 | 681 | ||
| 642 | HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); |
682 | HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, |
| - | 683 | pSMBUS_AddrCallbackTypeDef pCallback); |
|
| 643 | HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); |
684 | HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); |
| 644 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
685 | #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ |
| 645 | /** |
686 | /** |
| 646 | * @} |
687 | * @} |
| 647 | */ |
688 | */ |
| 648 | 689 | ||
| 649 | /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions |
690 | /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions |
| 650 | * @{ |
691 | * @{ |
| 651 | */ |
692 | */ |
| 652 | 693 | ||
| 653 | /* IO operation functions *****************************************************/ |
694 | /* IO operation functions *****************************************************/ |
| 654 | /** @addtogroup Blocking_mode_Polling Blocking mode Polling |
695 | /** @addtogroup Blocking_mode_Polling Blocking mode Polling |
| 655 | * @{ |
696 | * @{ |
| 656 | */ |
697 | */ |
| 657 | /******* Blocking mode: Polling */ |
698 | /******* Blocking mode: Polling */ |
| 658 | HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); |
699 | HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, |
| - | 700 | uint32_t Timeout); |
|
| 659 | /** |
701 | /** |
| 660 | * @} |
702 | * @} |
| 661 | */ |
703 | */ |
| 662 | 704 | ||
| 663 | /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt |
705 | /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt |
| 664 | * @{ |
706 | * @{ |
| 665 | */ |
707 | */ |
| 666 | /******* Non-Blocking mode: Interrupt */ |
708 | /******* Non-Blocking mode: Interrupt */ |
| 667 | HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
709 | HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, |
| - | 710 | uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|
| 668 | HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
711 | HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, |
| - | 712 | uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
|
| 669 | HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); |
713 | HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); |
| 670 | HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
714 | HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, |
| - | 715 | uint32_t XferOptions); |
|
| 671 | HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); |
716 | HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, |
| - | 717 | uint32_t XferOptions); |
|
| 672 | 718 | ||
| 673 | HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
719 | HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
| 674 | HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
720 | HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); |
| 675 | HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
721 | HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
| 676 | HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
722 | HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); |
| 677 | /** |
723 | /** |
| 678 | * @} |
724 | * @} |
| 679 | */ |
725 | */ |
| 680 | 726 | ||
| 681 | /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
727 | /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks |
| 682 | * @{ |
728 | * @{ |
| 683 | */ |
729 | */ |
| 684 | /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ |
730 | /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ |
| 685 | void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
731 | void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
| 686 | void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
732 | void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); |
| 687 | void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
733 | void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| 688 | void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
734 | void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); |
| Line 695... | Line 741... | ||
| 695 | /** |
741 | /** |
| 696 | * @} |
742 | * @} |
| 697 | */ |
743 | */ |
| 698 | 744 | ||
| 699 | /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions |
745 | /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions |
| 700 | * @{ |
746 | * @{ |
| 701 | */ |
747 | */ |
| 702 | 748 | ||
| 703 | /* Peripheral State and Errors functions **************************************************/ |
749 | /* Peripheral State and Errors functions **************************************************/ |
| 704 | uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); |
750 | uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); |
| 705 | uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); |
751 | uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); |
| 706 | 752 | ||