Subversion Repositories LedShow

Rev

Rev 2 | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 2 Rev 9
Line 1... Line 1...
1 
/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    system_stm32f1xx.c
 3 
  * @file    system_stm32f1xx.c
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @version V4.2.0
 - 
 
6 
  * @date    31-March-2017
 - 
 
7 
  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
 5 
  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
8 
  *
 6 
  *
9 
  * 1.  This file provides two functions and one global variable to be called from
 7 
  * 1.  This file provides two functions and one global variable to be called from
10 
  *     user application:
 8 
  *     user application:
11 
  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
 9 
  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
Line 33... Line 31...
33 
  *    configuration.
 31 
  *    configuration.
34 
  *        
 32 
  *        
35 
  ******************************************************************************
 33 
  ******************************************************************************
36 
  * @attention
 34 
  * @attention
37 
  *
 35 
  *
38 
  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
 36 
  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
- 
 
 37 
  * All rights reserved.</center></h2>
39 
  *
 38 
  *
40 
  * Redistribution and use in source and binary forms, with or without modification,
 39 
  * This software component is licensed by ST under BSD 3-Clause license,
41 
  * are permitted provided that the following conditions are met:
 40 
  * the "License"; You may not use this file except in compliance with the
42 
  *   1. Redistributions of source code must retain the above copyright notice,
 - 
 
43 
  *      this list of conditions and the following disclaimer.
 - 
 
44 
  *   2. Redistributions in binary form must reproduce the above copyright notice,
 - 
 
45 
  *      this list of conditions and the following disclaimer in the documentation
 - 
 
46 
  *      and/or other materials provided with the distribution.
 41 
  * License. You may obtain a copy of the License at:
47 
  *   3. Neither the name of STMicroelectronics nor the names of its contributors
 - 
 
48 
  *      may be used to endorse or promote products derived from this software
 42 
  *                        opensource.org/licenses/BSD-3-Clause
49 
  *      without specific prior written permission.
 - 
 
50 
  *
 - 
 
51 
  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 - 
 
52 
  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 - 
 
53 
  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 - 
 
54 
  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 - 
 
55 
  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 - 
 
56 
  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 - 
 
57 
  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 - 
 
58 
  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 - 
 
59 
  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 - 
 
60 
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 - 
 
61 
  *
 43 
  *
62 
  ******************************************************************************
 44 
  ******************************************************************************
63 
  */
 45 
  */
64 
 
 46 
 
65 
/** @addtogroup CMSIS
 47 
/** @addtogroup CMSIS
Line 105... Line 87...
105 
/*!< Uncomment the following line if you need to use external SRAM  */
 87 
/*!< Uncomment the following line if you need to use external SRAM  */
106 
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
 88 
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
107 
/* #define DATA_IN_ExtSRAM */
 89 
/* #define DATA_IN_ExtSRAM */
108 
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
 90 
#endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
109 
 
 91 
 
- 
 
 92 
/* Note: Following vector table addresses must be defined in line with linker
- 
 
 93 
         configuration. */
110 
/*!< Uncomment the following line if you need to relocate your vector Table in
 94 
/*!< Uncomment the following line if you need to relocate the vector table
- 
 
 95 
     anywhere in Flash or Sram, else the vector table is kept at the automatic
111 
     Internal SRAM. */
 96 
     remap of boot address selected */
- 
 
 97 
/* #define USER_VECT_TAB_ADDRESS */
- 
 
 98 
 
- 
 
 99 
#if defined(USER_VECT_TAB_ADDRESS)
- 
 
 100 
/*!< Uncomment the following line if you need to relocate your vector Table
- 
 
 101 
     in Sram else user remap will be done in Flash. */
112 
/* #define VECT_TAB_SRAM */
 102 
/* #define VECT_TAB_SRAM */
- 
 
 103 
#if defined(VECT_TAB_SRAM)
- 
 
 104 
#define VECT_TAB_BASE_ADDRESS   SRAM_BASE       /*!< Vector Table base address field.
- 
 
 105 
                                                     This value must be a multiple of 0x200. */
113 
#define VECT_TAB_OFFSET  0x00000000U /*!< Vector Table base offset field.
106 
#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
- 
 
 107 
                                                     This value must be a multiple of 0x200. */
- 
 
 108 
#else
- 
 
 109 
#define VECT_TAB_BASE_ADDRESS   FLASH_BASE      /*!< Vector Table base address field.
- 
 
 110 
                                                     This value must be a multiple of 0x200. */
- 
 
 111 
#define VECT_TAB_OFFSET         0x00000000U     /*!< Vector Table base offset field.
114 
                                  This value must be a multiple of 0x200. */
 112 
                                                     This value must be a multiple of 0x200. */
- 
 
 113 
#endif /* VECT_TAB_SRAM */
- 
 
 114 
#endif /* USER_VECT_TAB_ADDRESS */
115 
 
 115 
 
- 
 
 116 
/******************************************************************************/
116 
 
 117 
 
117 
/**
 118 
/**
118 
  * @}
 119 
  * @}
119 
  */
 120 
  */
120 
 
 121 
 
Line 128... Line 129...
128 
 
 129 
 
129 
/** @addtogroup STM32F1xx_System_Private_Variables
 130 
/** @addtogroup STM32F1xx_System_Private_Variables
130 
  * @{
 131 
  * @{
131 
  */
 132 
  */
132 
 
 133 
 
133 
/*******************************************************************************
 - 
 
134 
*  Clock Definitions
 134 
  /* This variable is updated in three ways:
135 
*******************************************************************************/
 135 
      1) by calling CMSIS function SystemCoreClockUpdate()
136 
#if defined(STM32F100xB) ||defined(STM32F100xE)
 136 
      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
137 
  uint32_t SystemCoreClock         = 24000000U;        /*!< System Clock Frequency (Core Clock) */
 137 
      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
138 
#else /*!< HSI Selected as System Clock source */
 138 
         Note: If you use this function to configure the system clock; then there
139 
  uint32_t SystemCoreClock         = 72000000U;        /*!< System Clock Frequency (Core Clock) */
 139 
               is no need to call the 2 first functions listed above, since SystemCoreClock
- 
 
 140 
               variable is updated automatically.
140 
#endif
 141 
  */
141 
 
 - 
 
- 
 
 142 
uint32_t SystemCoreClock = 16000000;
142 
const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 143 
const uint8_t AHBPrescTable[16U] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
143 
const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
 144 
const uint8_t APBPrescTable[8U] =  {0, 0, 0, 0, 1, 2, 3, 4};
144 
 
 145 
 
145 
/**
 146 
/**
146 
  * @}
 147 
  * @}
Line 172... Line 173...
172 
  * @param  None
 173 
  * @param  None
173 
  * @retval None
 174 
  * @retval None
174 
  */
 175 
  */
175 
void SystemInit (void)
 176 
void SystemInit (void)
176 
{
 177 
{
177 
  /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
 - 
 
178 
  /* Set HSION bit */
 - 
 
179 
  RCC->CR |= 0x00000001U;
 - 
 
180 
 
 - 
 
181 
  /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
 - 
 
182 
#if !defined(STM32F105xC) && !defined(STM32F107xC)
 - 
 
183 
  RCC->CFGR &= 0xF8FF0000U;
 - 
 
184 
#else
 - 
 
185 
  RCC->CFGR &= 0xF0FF0000U;
 - 
 
186 
#endif /* STM32F105xC */  
- 
 
187 
 
 - 
 
188 
  /* Reset HSEON, CSSON and PLLON bits */
 - 
 
189 
  RCC->CR &= 0xFEF6FFFFU;
 - 
 
190 
 
 - 
 
191 
  /* Reset HSEBYP bit */
 - 
 
192 
  RCC->CR &= 0xFFFBFFFFU;
 - 
 
193 
 
 - 
 
194 
  /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
 - 
 
195 
  RCC->CFGR &= 0xFF80FFFFU;
 - 
 
196 
 
 - 
 
197 
#if defined(STM32F105xC) || defined(STM32F107xC)
 - 
 
198 
  /* Reset PLL2ON and PLL3ON bits */
 - 
 
199 
  RCC->CR &= 0xEBFFFFFFU;
 - 
 
200 
 
 - 
 
201 
  /* Disable all interrupts and clear pending bits  */
 - 
 
202 
  RCC->CIR = 0x00FF0000U;
 - 
 
203 
 
 - 
 
204 
  /* Reset CFGR2 register */
 - 
 
205 
  RCC->CFGR2 = 0x00000000U;
 - 
 
206 
#elif defined(STM32F100xB) || defined(STM32F100xE)
 - 
 
207 
  /* Disable all interrupts and clear pending bits  */
 - 
 
208 
  RCC->CIR = 0x009F0000U;
 - 
 
209 
 
 - 
 
210 
  /* Reset CFGR2 register */
 - 
 
211 
  RCC->CFGR2 = 0x00000000U;      
 - 
 
212 
#else
 - 
 
213 
  /* Disable all interrupts and clear pending bits  */
 - 
 
214 
  RCC->CIR = 0x009F0000U;
 - 
 
215 
#endif /* STM32F105xC */
 - 
 
216 
   
 - 
 
217 
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
 178 
#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
218 
  #ifdef DATA_IN_ExtSRAM
 179 
  #ifdef DATA_IN_ExtSRAM
219 
    SystemInit_ExtMemCtl();
 180 
    SystemInit_ExtMemCtl();
220 
  #endif /* DATA_IN_ExtSRAM */
 181 
  #endif /* DATA_IN_ExtSRAM */
221 
#endif
182 
#endif
222 
 
 183 
 
- 
 
 184 
  /* Configure the Vector Table location -------------------------------------*/
223 
#ifdef VECT_TAB_SRAM
 185 
#if defined(USER_VECT_TAB_ADDRESS)
224 
  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
 186 
  SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
225 
#else
 - 
 
226 
  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
 187 
#endif /* USER_VECT_TAB_ADDRESS */
227 
#endif
- 
 
228 
}
 188 
}
229 
 
 189 
 
230 
/**
 190 
/**
231 
  * @brief  Update SystemCoreClock variable according to Clock Register Values.
 191 
  * @brief  Update SystemCoreClock variable according to Clock Register Values.
232 
  *         The SystemCoreClock variable contains the core clock (HCLK), it can
 192 
  *         The SystemCoreClock variable contains the core clock (HCLK), it can