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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32f107xc.h |
3 | * @file stm32f107xc.h |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. |
5 | * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File. |
| 6 | * This file contains all the peripheral register's definitions, bits |
6 | * This file contains all the peripheral register's definitions, bits |
| 7 | * definitions and memory mapping for STM32F1xx devices. |
7 | * definitions and memory mapping for STM32F1xx devices. |
| 8 | * |
8 | * |
| 9 | * This file contains: |
9 | * This file contains: |
| 10 | * - Data structures and the address mapping for all peripherals |
10 | * - Data structures and the address mapping for all peripherals |
| 11 | * - Peripheral's registers declarations and bits definition |
11 | * - Peripheral's registers declarations and bits definition |
| 12 | * - Macros to access peripheralÂ’s registers hardware |
12 | * - Macros to access peripheral's registers hardware |
| 13 | * |
13 | * |
| 14 | ****************************************************************************** |
14 | ****************************************************************************** |
| 15 | * @attention |
15 | * @attention |
| 16 | * |
16 | * |
| 17 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
17 | * Copyright (c) 2017-2021 STMicroelectronics. |
| 18 | * All rights reserved.</center></h2> |
18 | * All rights reserved. |
| 19 | * |
19 | * |
| 20 | * This software component is licensed by ST under BSD 3-Clause license, |
20 | * This software is licensed under terms that can be found in the LICENSE file |
| 21 | * the "License"; You may not use this file except in compliance with the |
21 | * in the root directory of this software component. |
| 22 | * License. You may obtain a copy of the License at: |
22 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 23 | * opensource.org/licenses/BSD-3-Clause |
23 | * |
| 24 | * |
24 | ****************************************************************************** |
| 25 | ****************************************************************************** |
25 | */ |
| 26 | */ |
26 | |
| 27 | 27 | ||
| 28 | 28 | /** @addtogroup CMSIS |
|
| 29 | /** @addtogroup CMSIS |
29 | * @{ |
| 30 | * @{ |
30 | */ |
| 31 | */ |
31 | |
| 32 | 32 | /** @addtogroup stm32f107xc |
|
| 33 | /** @addtogroup stm32f107xc |
33 | * @{ |
| 34 | * @{ |
34 | */ |
| 35 | */ |
35 | |
| 36 | 36 | #ifndef __STM32F107xC_H |
|
| 37 | #ifndef __STM32F107xC_H |
37 | #define __STM32F107xC_H |
| 38 | #define __STM32F107xC_H |
38 | |
| 39 | 39 | #ifdef __cplusplus |
|
| 40 | #ifdef __cplusplus |
40 | extern "C" { |
| 41 | extern "C" { |
41 | #endif |
| 42 | #endif |
42 | |
| 43 | 43 | /** @addtogroup Configuration_section_for_CMSIS |
|
| 44 | /** @addtogroup Configuration_section_for_CMSIS |
44 | * @{ |
| 45 | * @{ |
45 | */ |
| 46 | */ |
46 | /** |
| 47 | /** |
47 | * @brief Configuration of the Cortex-M3 Processor and Core Peripherals |
| 48 | * @brief Configuration of the Cortex-M3 Processor and Core Peripherals |
48 | */ |
| 49 | */ |
49 | #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ |
| 50 | #define __CM3_REV 0x0200U /*!< Core Revision r2p0 */ |
50 | #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ |
| 51 | #define __MPU_PRESENT 0U /*!< Other STM32 devices does not provide an MPU */ |
51 | #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ |
| 52 | #define __NVIC_PRIO_BITS 4U /*!< STM32 uses 4 Bits for the Priority Levels */ |
52 | #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ |
| 53 | #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ |
53 | |
| 54 | 54 | /** |
|
| 55 | /** |
55 | * @} |
| 56 | * @} |
56 | */ |
| 57 | */ |
57 | |
| 58 | 58 | /** @addtogroup Peripheral_interrupt_number_definition |
|
| 59 | /** @addtogroup Peripheral_interrupt_number_definition |
59 | * @{ |
| 60 | * @{ |
60 | */ |
| 61 | */ |
61 | |
| 62 | 62 | /** |
|
| 63 | /** |
63 | * @brief STM32F10x Interrupt Number Definition, according to the selected device |
| 64 | * @brief STM32F10x Interrupt Number Definition, according to the selected device |
64 | * in @ref Library_configuration_section |
| 65 | * in @ref Library_configuration_section |
65 | */ |
| 66 | */ |
66 | |
| 67 | 67 | /*!< Interrupt Number Definition */ |
|
| 68 | /*!< Interrupt Number Definition */ |
68 | typedef enum |
| 69 | typedef enum |
69 | { |
| 70 | { |
70 | /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
| 71 | /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| 72 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ |
| 73 | HardFault_IRQn = -13, /*!< 3 Cortex-M3 Hard Fault Interrupt */ |
73 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
| 74 | MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */ |
74 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
| 75 | BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */ |
75 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
| 76 | UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */ |
76 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
| 77 | SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */ |
77 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
| 78 | DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */ |
78 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
| 79 | PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */ |
79 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
| 80 | SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */ |
80 | |
| 81 | 81 | /****** STM32 specific Interrupt Numbers *********************************************************/ |
|
| 82 | /****** STM32 specific Interrupt Numbers *********************************************************/ |
82 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
| 83 | WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ |
83 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
| 84 | PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */ |
84 | TAMPER_IRQn = 2, /*!< Tamper Interrupt */ |
| 85 | TAMPER_IRQn = 2, /*!< Tamper Interrupt */ |
85 | RTC_IRQn = 3, /*!< RTC global Interrupt */ |
| 86 | RTC_IRQn = 3, /*!< RTC global Interrupt */ |
86 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
| 87 | FLASH_IRQn = 4, /*!< FLASH global Interrupt */ |
87 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
| 88 | RCC_IRQn = 5, /*!< RCC global Interrupt */ |
88 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
| 89 | EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */ |
89 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
| 90 | EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */ |
90 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
| 91 | EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */ |
91 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
| 92 | EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */ |
92 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
| 93 | EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */ |
93 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
| 94 | DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */ |
94 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
| 95 | DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */ |
95 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
| 96 | DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */ |
96 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
| 97 | DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */ |
97 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
| 98 | DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */ |
98 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
| 99 | DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */ |
99 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
| 100 | DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */ |
100 | ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
| 101 | ADC1_2_IRQn = 18, /*!< ADC1 and ADC2 global Interrupt */ |
101 | CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */ |
| 102 | CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */ |
102 | CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */ |
| 103 | CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */ |
103 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
| 104 | CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */ |
104 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
| 105 | CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */ |
105 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
| 106 | EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */ |
106 | TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
| 107 | TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */ |
107 | TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
| 108 | TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */ |
108 | TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
| 109 | TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */ |
109 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
| 110 | TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */ |
110 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
| 111 | TIM2_IRQn = 28, /*!< TIM2 global Interrupt */ |
111 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
| 112 | TIM3_IRQn = 29, /*!< TIM3 global Interrupt */ |
112 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
| 113 | TIM4_IRQn = 30, /*!< TIM4 global Interrupt */ |
113 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
| 114 | I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */ |
114 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
| 115 | I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */ |
115 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
| 116 | I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */ |
116 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
| 117 | I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */ |
117 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
| 118 | SPI1_IRQn = 35, /*!< SPI1 global Interrupt */ |
118 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
| 119 | SPI2_IRQn = 36, /*!< SPI2 global Interrupt */ |
119 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
| 120 | USART1_IRQn = 37, /*!< USART1 global Interrupt */ |
120 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
| 121 | USART2_IRQn = 38, /*!< USART2 global Interrupt */ |
121 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
| 122 | USART3_IRQn = 39, /*!< USART3 global Interrupt */ |
122 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
| 123 | EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */ |
123 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
| 124 | RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */ |
124 | OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ |
| 125 | OTG_FS_WKUP_IRQn = 42, /*!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt */ |
125 | TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
| 126 | TIM5_IRQn = 50, /*!< TIM5 global Interrupt */ |
126 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
| 127 | SPI3_IRQn = 51, /*!< SPI3 global Interrupt */ |
127 | UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
| 128 | UART4_IRQn = 52, /*!< UART4 global Interrupt */ |
128 | UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
| 129 | UART5_IRQn = 53, /*!< UART5 global Interrupt */ |
129 | TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
| 130 | TIM6_IRQn = 54, /*!< TIM6 global Interrupt */ |
130 | TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
| 131 | TIM7_IRQn = 55, /*!< TIM7 global Interrupt */ |
131 | DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
| 132 | DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */ |
132 | DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
| 133 | DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */ |
133 | DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
| 134 | DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */ |
134 | DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ |
| 135 | DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */ |
135 | DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ |
| 136 | DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */ |
136 | ETH_IRQn = 61, /*!< Ethernet global Interrupt */ |
| 137 | ETH_IRQn = 61, /*!< Ethernet global Interrupt */ |
137 | ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ |
| 138 | ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */ |
138 | CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ |
| 139 | CAN2_TX_IRQn = 63, /*!< CAN2 TX Interrupt */ |
139 | CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ |
| 140 | CAN2_RX0_IRQn = 64, /*!< CAN2 RX0 Interrupt */ |
140 | CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ |
| 141 | CAN2_RX1_IRQn = 65, /*!< CAN2 RX1 Interrupt */ |
141 | CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ |
| 142 | CAN2_SCE_IRQn = 66, /*!< CAN2 SCE Interrupt */ |
142 | OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ |
| 143 | OTG_FS_IRQn = 67 /*!< USB OTG FS global Interrupt */ |
143 | } IRQn_Type; |
| 144 | } IRQn_Type; |
144 | |
| 145 | 145 | /** |
|
| 146 | /** |
146 | * @} |
| 147 | * @} |
147 | */ |
| 148 | */ |
148 | |
| 149 | 149 | #include "core_cm3.h" |
|
| 150 | #include "core_cm3.h" |
150 | #include "system_stm32f1xx.h" |
| 151 | #include "system_stm32f1xx.h" |
151 | #include <stdint.h> |
| 152 | #include <stdint.h> |
152 | |
| 153 | 153 | /** @addtogroup Peripheral_registers_structures |
|
| 154 | /** @addtogroup Peripheral_registers_structures |
154 | * @{ |
| 155 | * @{ |
155 | */ |
| 156 | */ |
156 | |
| 157 | 157 | /** |
|
| 158 | /** |
158 | * @brief Analog to Digital Converter |
| 159 | * @brief Analog to Digital Converter |
159 | */ |
| 160 | */ |
160 | |
| 161 | 161 | typedef struct |
|
| 162 | typedef struct |
162 | { |
| 163 | { |
163 | __IO uint32_t SR; |
| 164 | __IO uint32_t SR; |
164 | __IO uint32_t CR1; |
| 165 | __IO uint32_t CR1; |
165 | __IO uint32_t CR2; |
| 166 | __IO uint32_t CR2; |
166 | __IO uint32_t SMPR1; |
| 167 | __IO uint32_t SMPR1; |
167 | __IO uint32_t SMPR2; |
| 168 | __IO uint32_t SMPR2; |
168 | __IO uint32_t JOFR1; |
| 169 | __IO uint32_t JOFR1; |
169 | __IO uint32_t JOFR2; |
| 170 | __IO uint32_t JOFR2; |
170 | __IO uint32_t JOFR3; |
| 171 | __IO uint32_t JOFR3; |
171 | __IO uint32_t JOFR4; |
| 172 | __IO uint32_t JOFR4; |
172 | __IO uint32_t HTR; |
| 173 | __IO uint32_t HTR; |
173 | __IO uint32_t LTR; |
| 174 | __IO uint32_t LTR; |
174 | __IO uint32_t SQR1; |
| 175 | __IO uint32_t SQR1; |
175 | __IO uint32_t SQR2; |
| 176 | __IO uint32_t SQR2; |
176 | __IO uint32_t SQR3; |
| 177 | __IO uint32_t SQR3; |
177 | __IO uint32_t JSQR; |
| 178 | __IO uint32_t JSQR; |
178 | __IO uint32_t JDR1; |
| 179 | __IO uint32_t JDR1; |
179 | __IO uint32_t JDR2; |
| 180 | __IO uint32_t JDR2; |
180 | __IO uint32_t JDR3; |
| 181 | __IO uint32_t JDR3; |
181 | __IO uint32_t JDR4; |
| 182 | __IO uint32_t JDR4; |
182 | __IO uint32_t DR; |
| 183 | __IO uint32_t DR; |
183 | } ADC_TypeDef; |
| 184 | } ADC_TypeDef; |
184 | |
| 185 | 185 | typedef struct |
|
| 186 | typedef struct |
186 | { |
| 187 | { |
187 | __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ |
| 188 | __IO uint32_t SR; /*!< ADC status register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address */ |
188 | __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ |
| 189 | __IO uint32_t CR1; /*!< ADC control register 1, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x04 */ |
189 | __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ |
| 190 | __IO uint32_t CR2; /*!< ADC control register 2, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x08 */ |
190 | uint32_t RESERVED[16]; |
| 191 | uint32_t RESERVED[16]; |
191 | __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ |
| 192 | __IO uint32_t DR; /*!< ADC data register, used for ADC multimode (bits common to several ADC instances). Address offset: ADC1 base address + 0x4C */ |
192 | } ADC_Common_TypeDef; |
| 193 | } ADC_Common_TypeDef; |
193 | |
| 194 | 194 | /** |
|
| 195 | /** |
195 | * @brief Backup Registers |
| 196 | * @brief Backup Registers |
196 | */ |
| 197 | */ |
197 | |
| 198 | 198 | typedef struct |
|
| 199 | typedef struct |
199 | { |
| 200 | { |
200 | uint32_t RESERVED0; |
| 201 | uint32_t RESERVED0; |
201 | __IO uint32_t DR1; |
| 202 | __IO uint32_t DR1; |
202 | __IO uint32_t DR2; |
| 203 | __IO uint32_t DR2; |
203 | __IO uint32_t DR3; |
| 204 | __IO uint32_t DR3; |
204 | __IO uint32_t DR4; |
| 205 | __IO uint32_t DR4; |
205 | __IO uint32_t DR5; |
| 206 | __IO uint32_t DR5; |
206 | __IO uint32_t DR6; |
| 207 | __IO uint32_t DR6; |
207 | __IO uint32_t DR7; |
| 208 | __IO uint32_t DR7; |
208 | __IO uint32_t DR8; |
| 209 | __IO uint32_t DR8; |
209 | __IO uint32_t DR9; |
| 210 | __IO uint32_t DR9; |
210 | __IO uint32_t DR10; |
| 211 | __IO uint32_t DR10; |
211 | __IO uint32_t RTCCR; |
| 212 | __IO uint32_t RTCCR; |
212 | __IO uint32_t CR; |
| 213 | __IO uint32_t CR; |
213 | __IO uint32_t CSR; |
| 214 | __IO uint32_t CSR; |
214 | uint32_t RESERVED13[2]; |
| 215 | uint32_t RESERVED13[2]; |
215 | __IO uint32_t DR11; |
| 216 | __IO uint32_t DR11; |
216 | __IO uint32_t DR12; |
| 217 | __IO uint32_t DR12; |
217 | __IO uint32_t DR13; |
| 218 | __IO uint32_t DR13; |
218 | __IO uint32_t DR14; |
| 219 | __IO uint32_t DR14; |
219 | __IO uint32_t DR15; |
| 220 | __IO uint32_t DR15; |
220 | __IO uint32_t DR16; |
| 221 | __IO uint32_t DR16; |
221 | __IO uint32_t DR17; |
| 222 | __IO uint32_t DR17; |
222 | __IO uint32_t DR18; |
| 223 | __IO uint32_t DR18; |
223 | __IO uint32_t DR19; |
| 224 | __IO uint32_t DR19; |
224 | __IO uint32_t DR20; |
| 225 | __IO uint32_t DR20; |
225 | __IO uint32_t DR21; |
| 226 | __IO uint32_t DR21; |
226 | __IO uint32_t DR22; |
| 227 | __IO uint32_t DR22; |
227 | __IO uint32_t DR23; |
| 228 | __IO uint32_t DR23; |
228 | __IO uint32_t DR24; |
| 229 | __IO uint32_t DR24; |
229 | __IO uint32_t DR25; |
| 230 | __IO uint32_t DR25; |
230 | __IO uint32_t DR26; |
| 231 | __IO uint32_t DR26; |
231 | __IO uint32_t DR27; |
| 232 | __IO uint32_t DR27; |
232 | __IO uint32_t DR28; |
| 233 | __IO uint32_t DR28; |
233 | __IO uint32_t DR29; |
| 234 | __IO uint32_t DR29; |
234 | __IO uint32_t DR30; |
| 235 | __IO uint32_t DR30; |
235 | __IO uint32_t DR31; |
| 236 | __IO uint32_t DR31; |
236 | __IO uint32_t DR32; |
| 237 | __IO uint32_t DR32; |
237 | __IO uint32_t DR33; |
| 238 | __IO uint32_t DR33; |
238 | __IO uint32_t DR34; |
| 239 | __IO uint32_t DR34; |
239 | __IO uint32_t DR35; |
| 240 | __IO uint32_t DR35; |
240 | __IO uint32_t DR36; |
| 241 | __IO uint32_t DR36; |
241 | __IO uint32_t DR37; |
| 242 | __IO uint32_t DR37; |
242 | __IO uint32_t DR38; |
| 243 | __IO uint32_t DR38; |
243 | __IO uint32_t DR39; |
| 244 | __IO uint32_t DR39; |
244 | __IO uint32_t DR40; |
| 245 | __IO uint32_t DR40; |
245 | __IO uint32_t DR41; |
| 246 | __IO uint32_t DR41; |
246 | __IO uint32_t DR42; |
| 247 | __IO uint32_t DR42; |
247 | } BKP_TypeDef; |
| 248 | } BKP_TypeDef; |
248 | |
| 249 | 249 | /** |
|
| 250 | /** |
250 | * @brief Controller Area Network TxMailBox |
| 251 | * @brief Controller Area Network TxMailBox |
251 | */ |
| 252 | */ |
252 | |
| 253 | 253 | typedef struct |
|
| 254 | typedef struct |
254 | { |
| 255 | { |
255 | __IO uint32_t TIR; |
| 256 | __IO uint32_t TIR; |
256 | __IO uint32_t TDTR; |
| 257 | __IO uint32_t TDTR; |
257 | __IO uint32_t TDLR; |
| 258 | __IO uint32_t TDLR; |
258 | __IO uint32_t TDHR; |
| 259 | __IO uint32_t TDHR; |
259 | } CAN_TxMailBox_TypeDef; |
| 260 | } CAN_TxMailBox_TypeDef; |
260 | |
| 261 | 261 | /** |
|
| 262 | /** |
262 | * @brief Controller Area Network FIFOMailBox |
| 263 | * @brief Controller Area Network FIFOMailBox |
263 | */ |
| 264 | */ |
264 | |
| 265 | 265 | typedef struct |
|
| 266 | typedef struct |
266 | { |
| 267 | { |
267 | __IO uint32_t RIR; |
| 268 | __IO uint32_t RIR; |
268 | __IO uint32_t RDTR; |
| 269 | __IO uint32_t RDTR; |
269 | __IO uint32_t RDLR; |
| 270 | __IO uint32_t RDLR; |
270 | __IO uint32_t RDHR; |
| 271 | __IO uint32_t RDHR; |
271 | } CAN_FIFOMailBox_TypeDef; |
| 272 | } CAN_FIFOMailBox_TypeDef; |
272 | |
| 273 | 273 | /** |
|
| 274 | /** |
274 | * @brief Controller Area Network FilterRegister |
| 275 | * @brief Controller Area Network FilterRegister |
275 | */ |
| 276 | */ |
276 | |
| 277 | 277 | typedef struct |
|
| 278 | typedef struct |
278 | { |
| 279 | { |
279 | __IO uint32_t FR1; |
| 280 | __IO uint32_t FR1; |
280 | __IO uint32_t FR2; |
| 281 | __IO uint32_t FR2; |
281 | } CAN_FilterRegister_TypeDef; |
| 282 | } CAN_FilterRegister_TypeDef; |
282 | |
| 283 | 283 | /** |
|
| 284 | /** |
284 | * @brief Controller Area Network |
| 285 | * @brief Controller Area Network |
285 | */ |
| 286 | */ |
286 | |
| 287 | 287 | typedef struct |
|
| 288 | typedef struct |
288 | { |
| 289 | { |
289 | __IO uint32_t MCR; |
| 290 | __IO uint32_t MCR; |
290 | __IO uint32_t MSR; |
| 291 | __IO uint32_t MSR; |
291 | __IO uint32_t TSR; |
| 292 | __IO uint32_t TSR; |
292 | __IO uint32_t RF0R; |
| 293 | __IO uint32_t RF0R; |
293 | __IO uint32_t RF1R; |
| 294 | __IO uint32_t RF1R; |
294 | __IO uint32_t IER; |
| 295 | __IO uint32_t IER; |
295 | __IO uint32_t ESR; |
| 296 | __IO uint32_t ESR; |
296 | __IO uint32_t BTR; |
| 297 | __IO uint32_t BTR; |
297 | uint32_t RESERVED0[88]; |
| 298 | uint32_t RESERVED0[88]; |
298 | CAN_TxMailBox_TypeDef sTxMailBox[3]; |
| 299 | CAN_TxMailBox_TypeDef sTxMailBox[3]; |
299 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; |
| 300 | CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; |
300 | uint32_t RESERVED1[12]; |
| 301 | uint32_t RESERVED1[12]; |
301 | __IO uint32_t FMR; |
| 302 | __IO uint32_t FMR; |
302 | __IO uint32_t FM1R; |
| 303 | __IO uint32_t FM1R; |
303 | uint32_t RESERVED2; |
| 304 | uint32_t RESERVED2; |
304 | __IO uint32_t FS1R; |
| 305 | __IO uint32_t FS1R; |
305 | uint32_t RESERVED3; |
| 306 | uint32_t RESERVED3; |
306 | __IO uint32_t FFA1R; |
| 307 | __IO uint32_t FFA1R; |
307 | uint32_t RESERVED4; |
| 308 | uint32_t RESERVED4; |
308 | __IO uint32_t FA1R; |
| 309 | __IO uint32_t FA1R; |
309 | uint32_t RESERVED5[8]; |
| 310 | uint32_t RESERVED5[8]; |
310 | CAN_FilterRegister_TypeDef sFilterRegister[28]; |
| 311 | CAN_FilterRegister_TypeDef sFilterRegister[28]; |
311 | } CAN_TypeDef; |
| 312 | } CAN_TypeDef; |
312 | |
| 313 | 313 | /** |
|
| 314 | /** |
314 | * @brief CRC calculation unit |
| 315 | * @brief CRC calculation unit |
315 | */ |
| 316 | */ |
316 | |
| 317 | 317 | typedef struct |
|
| 318 | typedef struct |
318 | { |
| 319 | { |
319 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
| 320 | __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ |
320 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
| 321 | __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ |
321 | uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ |
| 322 | uint8_t RESERVED0; /*!< Reserved, Address offset: 0x05 */ |
322 | uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ |
| 323 | uint16_t RESERVED1; /*!< Reserved, Address offset: 0x06 */ |
323 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
| 324 | __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ |
324 | } CRC_TypeDef; |
| 325 | } CRC_TypeDef; |
325 | |
| 326 | 326 | /** |
|
| 327 | /** |
327 | * @brief Digital to Analog Converter |
| 328 | * @brief Digital to Analog Converter |
328 | */ |
| 329 | */ |
329 | |
| 330 | 330 | typedef struct |
|
| 331 | typedef struct |
331 | { |
| 332 | { |
332 | __IO uint32_t CR; |
| 333 | __IO uint32_t CR; |
333 | __IO uint32_t SWTRIGR; |
| 334 | __IO uint32_t SWTRIGR; |
334 | __IO uint32_t DHR12R1; |
| 335 | __IO uint32_t DHR12R1; |
335 | __IO uint32_t DHR12L1; |
| 336 | __IO uint32_t DHR12L1; |
336 | __IO uint32_t DHR8R1; |
| 337 | __IO uint32_t DHR8R1; |
337 | __IO uint32_t DHR12R2; |
| 338 | __IO uint32_t DHR12R2; |
338 | __IO uint32_t DHR12L2; |
| 339 | __IO uint32_t DHR12L2; |
339 | __IO uint32_t DHR8R2; |
| 340 | __IO uint32_t DHR8R2; |
340 | __IO uint32_t DHR12RD; |
| 341 | __IO uint32_t DHR12RD; |
341 | __IO uint32_t DHR12LD; |
| 342 | __IO uint32_t DHR12LD; |
342 | __IO uint32_t DHR8RD; |
| 343 | __IO uint32_t DHR8RD; |
343 | __IO uint32_t DOR1; |
| 344 | __IO uint32_t DOR1; |
344 | __IO uint32_t DOR2; |
| 345 | __IO uint32_t DOR2; |
345 | } DAC_TypeDef; |
| 346 | } DAC_TypeDef; |
346 | |
| 347 | 347 | /** |
|
| 348 | /** |
348 | * @brief Debug MCU |
| 349 | * @brief Debug MCU |
349 | */ |
| 350 | */ |
350 | |
| 351 | 351 | typedef struct |
|
| 352 | typedef struct |
352 | { |
| 353 | { |
353 | __IO uint32_t IDCODE; |
| 354 | __IO uint32_t IDCODE; |
354 | __IO uint32_t CR; |
| 355 | __IO uint32_t CR; |
355 | }DBGMCU_TypeDef; |
| 356 | }DBGMCU_TypeDef; |
356 | |
| 357 | 357 | /** |
|
| 358 | /** |
358 | * @brief DMA Controller |
| 359 | * @brief DMA Controller |
359 | */ |
| 360 | */ |
360 | |
| 361 | 361 | typedef struct |
|
| 362 | typedef struct |
362 | { |
| 363 | { |
363 | __IO uint32_t CCR; |
| 364 | __IO uint32_t CCR; |
364 | __IO uint32_t CNDTR; |
| 365 | __IO uint32_t CNDTR; |
365 | __IO uint32_t CPAR; |
| 366 | __IO uint32_t CPAR; |
366 | __IO uint32_t CMAR; |
| 367 | __IO uint32_t CMAR; |
367 | } DMA_Channel_TypeDef; |
| 368 | } DMA_Channel_TypeDef; |
368 | |
| 369 | 369 | typedef struct |
|
| 370 | typedef struct |
370 | { |
| 371 | { |
371 | __IO uint32_t ISR; |
| 372 | __IO uint32_t ISR; |
372 | __IO uint32_t IFCR; |
| 373 | __IO uint32_t IFCR; |
373 | } DMA_TypeDef; |
| 374 | } DMA_TypeDef; |
374 | |
| 375 | 375 | ||
| 376 | 376 | ||
| 377 | 377 | /** |
|
| 378 | /** |
378 | * @brief Ethernet MAC |
| 379 | * @brief Ethernet MAC |
379 | */ |
| 380 | */ |
380 | |
| 381 | 381 | typedef struct |
|
| 382 | typedef struct |
382 | { |
| 383 | { |
383 | __IO uint32_t MACCR; |
| 384 | __IO uint32_t MACCR; |
384 | __IO uint32_t MACFFR; |
| 385 | __IO uint32_t MACFFR; |
385 | __IO uint32_t MACHTHR; |
| 386 | __IO uint32_t MACHTHR; |
386 | __IO uint32_t MACHTLR; |
| 387 | __IO uint32_t MACHTLR; |
387 | __IO uint32_t MACMIIAR; |
| 388 | __IO uint32_t MACMIIAR; |
388 | __IO uint32_t MACMIIDR; |
| 389 | __IO uint32_t MACMIIDR; |
389 | __IO uint32_t MACFCR; |
| 390 | __IO uint32_t MACFCR; |
390 | __IO uint32_t MACVLANTR; /* 8 */ |
| 391 | __IO uint32_t MACVLANTR; /* 8 */ |
391 | uint32_t RESERVED0[2]; |
| 392 | uint32_t RESERVED0[2]; |
392 | __IO uint32_t MACRWUFFR; /* 11 */ |
| 393 | __IO uint32_t MACRWUFFR; /* 11 */ |
393 | __IO uint32_t MACPMTCSR; |
| 394 | __IO uint32_t MACPMTCSR; |
394 | uint32_t RESERVED1[2]; |
| 395 | uint32_t RESERVED1[2]; |
395 | __IO uint32_t MACSR; /* 15 */ |
| 396 | __IO uint32_t MACSR; /* 15 */ |
396 | __IO uint32_t MACIMR; |
| 397 | __IO uint32_t MACIMR; |
397 | __IO uint32_t MACA0HR; |
| 398 | __IO uint32_t MACA0HR; |
398 | __IO uint32_t MACA0LR; |
| 399 | __IO uint32_t MACA0LR; |
399 | __IO uint32_t MACA1HR; |
| 400 | __IO uint32_t MACA1HR; |
400 | __IO uint32_t MACA1LR; |
| 401 | __IO uint32_t MACA1LR; |
401 | __IO uint32_t MACA2HR; |
| 402 | __IO uint32_t MACA2HR; |
402 | __IO uint32_t MACA2LR; |
| 403 | __IO uint32_t MACA2LR; |
403 | __IO uint32_t MACA3HR; |
| 404 | __IO uint32_t MACA3HR; |
404 | __IO uint32_t MACA3LR; /* 24 */ |
| 405 | __IO uint32_t MACA3LR; /* 24 */ |
405 | uint32_t RESERVED2[40]; |
| 406 | uint32_t RESERVED2[40]; |
406 | __IO uint32_t MMCCR; /* 65 */ |
| 407 | __IO uint32_t MMCCR; /* 65 */ |
407 | __IO uint32_t MMCRIR; |
| 408 | __IO uint32_t MMCRIR; |
408 | __IO uint32_t MMCTIR; |
| 409 | __IO uint32_t MMCTIR; |
409 | __IO uint32_t MMCRIMR; |
| 410 | __IO uint32_t MMCRIMR; |
410 | __IO uint32_t MMCTIMR; /* 69 */ |
| 411 | __IO uint32_t MMCTIMR; /* 69 */ |
411 | uint32_t RESERVED3[14]; |
| 412 | uint32_t RESERVED3[14]; |
412 | __IO uint32_t MMCTGFSCCR; /* 84 */ |
| 413 | __IO uint32_t MMCTGFSCCR; /* 84 */ |
413 | __IO uint32_t MMCTGFMSCCR; |
| 414 | __IO uint32_t MMCTGFMSCCR; |
414 | uint32_t RESERVED4[5]; |
| 415 | uint32_t RESERVED4[5]; |
415 | __IO uint32_t MMCTGFCR; |
| 416 | __IO uint32_t MMCTGFCR; |
416 | uint32_t RESERVED5[10]; |
| 417 | uint32_t RESERVED5[10]; |
417 | __IO uint32_t MMCRFCECR; |
| 418 | __IO uint32_t MMCRFCECR; |
418 | __IO uint32_t MMCRFAECR; |
| 419 | __IO uint32_t MMCRFAECR; |
419 | uint32_t RESERVED6[10]; |
| 420 | uint32_t RESERVED6[10]; |
420 | __IO uint32_t MMCRGUFCR; |
| 421 | __IO uint32_t MMCRGUFCR; |
421 | uint32_t RESERVED7[334]; |
| 422 | uint32_t RESERVED7[334]; |
422 | __IO uint32_t PTPTSCR; |
| 423 | __IO uint32_t PTPTSCR; |
423 | __IO uint32_t PTPSSIR; |
| 424 | __IO uint32_t PTPSSIR; |
424 | __IO uint32_t PTPTSHR; |
| 425 | __IO uint32_t PTPTSHR; |
425 | __IO uint32_t PTPTSLR; |
| 426 | __IO uint32_t PTPTSLR; |
426 | __IO uint32_t PTPTSHUR; |
| 427 | __IO uint32_t PTPTSHUR; |
427 | __IO uint32_t PTPTSLUR; |
| 428 | __IO uint32_t PTPTSLUR; |
428 | __IO uint32_t PTPTSAR; |
| 429 | __IO uint32_t PTPTSAR; |
429 | __IO uint32_t PTPTTHR; |
| 430 | __IO uint32_t PTPTTHR; |
430 | __IO uint32_t PTPTTLR; |
| 431 | __IO uint32_t PTPTTLR; |
431 | uint32_t RESERVED8[567]; |
| 432 | uint32_t RESERVED8[567]; |
432 | __IO uint32_t DMABMR; |
| 433 | __IO uint32_t DMABMR; |
433 | __IO uint32_t DMATPDR; |
| 434 | __IO uint32_t DMATPDR; |
434 | __IO uint32_t DMARPDR; |
| 435 | __IO uint32_t DMARPDR; |
435 | __IO uint32_t DMARDLAR; |
| 436 | __IO uint32_t DMARDLAR; |
436 | __IO uint32_t DMATDLAR; |
| 437 | __IO uint32_t DMATDLAR; |
437 | __IO uint32_t DMASR; |
| 438 | __IO uint32_t DMASR; |
438 | __IO uint32_t DMAOMR; |
| 439 | __IO uint32_t DMAOMR; |
439 | __IO uint32_t DMAIER; |
| 440 | __IO uint32_t DMAIER; |
440 | __IO uint32_t DMAMFBOCR; |
| 441 | __IO uint32_t DMAMFBOCR; |
441 | uint32_t RESERVED9[9]; |
| 442 | uint32_t RESERVED9[9]; |
442 | __IO uint32_t DMACHTDR; |
| 443 | __IO uint32_t DMACHTDR; |
443 | __IO uint32_t DMACHRDR; |
| 444 | __IO uint32_t DMACHRDR; |
444 | __IO uint32_t DMACHTBAR; |
| 445 | __IO uint32_t DMACHTBAR; |
445 | __IO uint32_t DMACHRBAR; |
| 446 | __IO uint32_t DMACHRBAR; |
446 | } ETH_TypeDef; |
| 447 | } ETH_TypeDef; |
447 | |
| 448 | 448 | ||
| 449 | 449 | /** |
|
| 450 | /** |
450 | * @brief External Interrupt/Event Controller |
| 451 | * @brief External Interrupt/Event Controller |
451 | */ |
| 452 | */ |
452 | |
| 453 | 453 | typedef struct |
|
| 454 | typedef struct |
454 | { |
| 455 | { |
455 | __IO uint32_t IMR; |
| 456 | __IO uint32_t IMR; |
456 | __IO uint32_t EMR; |
| 457 | __IO uint32_t EMR; |
457 | __IO uint32_t RTSR; |
| 458 | __IO uint32_t RTSR; |
458 | __IO uint32_t FTSR; |
| 459 | __IO uint32_t FTSR; |
459 | __IO uint32_t SWIER; |
| 460 | __IO uint32_t SWIER; |
460 | __IO uint32_t PR; |
| 461 | __IO uint32_t PR; |
461 | } EXTI_TypeDef; |
| 462 | } EXTI_TypeDef; |
462 | |
| 463 | 463 | /** |
|
| 464 | /** |
464 | * @brief FLASH Registers |
| 465 | * @brief FLASH Registers |
465 | */ |
| 466 | */ |
466 | |
| 467 | 467 | typedef struct |
|
| 468 | typedef struct |
468 | { |
| 469 | { |
469 | __IO uint32_t ACR; |
| 470 | __IO uint32_t ACR; |
470 | __IO uint32_t KEYR; |
| 471 | __IO uint32_t KEYR; |
471 | __IO uint32_t OPTKEYR; |
| 472 | __IO uint32_t OPTKEYR; |
472 | __IO uint32_t SR; |
| 473 | __IO uint32_t SR; |
473 | __IO uint32_t CR; |
| 474 | __IO uint32_t CR; |
474 | __IO uint32_t AR; |
| 475 | __IO uint32_t AR; |
475 | __IO uint32_t RESERVED; |
| 476 | __IO uint32_t RESERVED; |
476 | __IO uint32_t OBR; |
| 477 | __IO uint32_t OBR; |
477 | __IO uint32_t WRPR; |
| 478 | __IO uint32_t WRPR; |
478 | } FLASH_TypeDef; |
| 479 | } FLASH_TypeDef; |
479 | |
| 480 | 480 | /** |
|
| 481 | /** |
481 | * @brief Option Bytes Registers |
| 482 | * @brief Option Bytes Registers |
482 | */ |
| 483 | */ |
483 | |
| 484 | 484 | typedef struct |
|
| 485 | typedef struct |
485 | { |
| 486 | { |
486 | __IO uint16_t RDP; |
| 487 | __IO uint16_t RDP; |
487 | __IO uint16_t USER; |
| 488 | __IO uint16_t USER; |
488 | __IO uint16_t Data0; |
| 489 | __IO uint16_t Data0; |
489 | __IO uint16_t Data1; |
| 490 | __IO uint16_t Data1; |
490 | __IO uint16_t WRP0; |
| 491 | __IO uint16_t WRP0; |
491 | __IO uint16_t WRP1; |
| 492 | __IO uint16_t WRP1; |
492 | __IO uint16_t WRP2; |
| 493 | __IO uint16_t WRP2; |
493 | __IO uint16_t WRP3; |
| 494 | __IO uint16_t WRP3; |
494 | } OB_TypeDef; |
| 495 | } OB_TypeDef; |
495 | |
| 496 | 496 | /** |
|
| 497 | /** |
497 | * @brief General Purpose I/O |
| 498 | * @brief General Purpose I/O |
498 | */ |
| 499 | */ |
499 | |
| 500 | 500 | typedef struct |
|
| 501 | typedef struct |
501 | { |
| 502 | { |
502 | __IO uint32_t CRL; |
| 503 | __IO uint32_t CRL; |
503 | __IO uint32_t CRH; |
| 504 | __IO uint32_t CRH; |
504 | __IO uint32_t IDR; |
| 505 | __IO uint32_t IDR; |
505 | __IO uint32_t ODR; |
| 506 | __IO uint32_t ODR; |
506 | __IO uint32_t BSRR; |
| 507 | __IO uint32_t BSRR; |
507 | __IO uint32_t BRR; |
| 508 | __IO uint32_t BRR; |
508 | __IO uint32_t LCKR; |
| 509 | __IO uint32_t LCKR; |
509 | } GPIO_TypeDef; |
| 510 | } GPIO_TypeDef; |
510 | |
| 511 | 511 | /** |
|
| 512 | /** |
512 | * @brief Alternate Function I/O |
| 513 | * @brief Alternate Function I/O |
513 | */ |
| 514 | */ |
514 | |
| 515 | 515 | typedef struct |
|
| 516 | typedef struct |
516 | { |
| 517 | { |
517 | __IO uint32_t EVCR; |
| 518 | __IO uint32_t EVCR; |
518 | __IO uint32_t MAPR; |
| 519 | __IO uint32_t MAPR; |
519 | __IO uint32_t EXTICR[4]; |
| 520 | __IO uint32_t EXTICR[4]; |
520 | uint32_t RESERVED0; |
| 521 | uint32_t RESERVED0; |
521 | __IO uint32_t MAPR2; |
| 522 | __IO uint32_t MAPR2; |
522 | } AFIO_TypeDef; |
| 523 | } AFIO_TypeDef; |
523 | /** |
| 524 | /** |
524 | * @brief Inter Integrated Circuit Interface |
| 525 | * @brief Inter Integrated Circuit Interface |
525 | */ |
| 526 | */ |
526 | |
| 527 | 527 | typedef struct |
|
| 528 | typedef struct |
528 | { |
| 529 | { |
529 | __IO uint32_t CR1; |
| 530 | __IO uint32_t CR1; |
530 | __IO uint32_t CR2; |
| 531 | __IO uint32_t CR2; |
531 | __IO uint32_t OAR1; |
| 532 | __IO uint32_t OAR1; |
532 | __IO uint32_t OAR2; |
| 533 | __IO uint32_t OAR2; |
533 | __IO uint32_t DR; |
| 534 | __IO uint32_t DR; |
534 | __IO uint32_t SR1; |
| 535 | __IO uint32_t SR1; |
535 | __IO uint32_t SR2; |
| 536 | __IO uint32_t SR2; |
536 | __IO uint32_t CCR; |
| 537 | __IO uint32_t CCR; |
537 | __IO uint32_t TRISE; |
| 538 | __IO uint32_t TRISE; |
538 | } I2C_TypeDef; |
| 539 | } I2C_TypeDef; |
539 | |
| 540 | 540 | /** |
|
| 541 | /** |
541 | * @brief Independent WATCHDOG |
| 542 | * @brief Independent WATCHDOG |
542 | */ |
| 543 | */ |
543 | |
| 544 | 544 | typedef struct |
|
| 545 | typedef struct |
545 | { |
| 546 | { |
546 | __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ |
| 547 | __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */ |
547 | __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ |
| 548 | __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */ |
548 | __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ |
| 549 | __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */ |
549 | __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ |
| 550 | __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */ |
550 | } IWDG_TypeDef; |
| 551 | } IWDG_TypeDef; |
551 | |
| 552 | 552 | /** |
|
| 553 | /** |
553 | * @brief Power Control |
| 554 | * @brief Power Control |
554 | */ |
| 555 | */ |
555 | |
| 556 | 556 | typedef struct |
|
| 557 | typedef struct |
557 | { |
| 558 | { |
558 | __IO uint32_t CR; |
| 559 | __IO uint32_t CR; |
559 | __IO uint32_t CSR; |
| 560 | __IO uint32_t CSR; |
560 | } PWR_TypeDef; |
| 561 | } PWR_TypeDef; |
561 | |
| 562 | 562 | /** |
|
| 563 | /** |
563 | * @brief Reset and Clock Control |
| 564 | * @brief Reset and Clock Control |
564 | */ |
| 565 | */ |
565 | |
| 566 | 566 | typedef struct |
|
| 567 | typedef struct |
567 | { |
| 568 | { |
568 | __IO uint32_t CR; |
| 569 | __IO uint32_t CR; |
569 | __IO uint32_t CFGR; |
| 570 | __IO uint32_t CFGR; |
570 | __IO uint32_t CIR; |
| 571 | __IO uint32_t CIR; |
571 | __IO uint32_t APB2RSTR; |
| 572 | __IO uint32_t APB2RSTR; |
572 | __IO uint32_t APB1RSTR; |
| 573 | __IO uint32_t APB1RSTR; |
573 | __IO uint32_t AHBENR; |
| 574 | __IO uint32_t AHBENR; |
574 | __IO uint32_t APB2ENR; |
| 575 | __IO uint32_t APB2ENR; |
575 | __IO uint32_t APB1ENR; |
| 576 | __IO uint32_t APB1ENR; |
576 | __IO uint32_t BDCR; |
| 577 | __IO uint32_t BDCR; |
577 | __IO uint32_t CSR; |
| 578 | __IO uint32_t CSR; |
578 | |
| 579 | 579 | __IO uint32_t AHBRSTR; |
|
| 580 | __IO uint32_t AHBRSTR; |
580 | __IO uint32_t CFGR2; |
| 581 | __IO uint32_t CFGR2; |
581 | |
| 582 | 582 | } RCC_TypeDef; |
|
| 583 | } RCC_TypeDef; |
583 | |
| 584 | 584 | /** |
|
| 585 | /** |
585 | * @brief Real-Time Clock |
| 586 | * @brief Real-Time Clock |
586 | */ |
| 587 | */ |
587 | |
| 588 | 588 | typedef struct |
|
| 589 | typedef struct |
589 | { |
| 590 | { |
590 | __IO uint32_t CRH; |
| 591 | __IO uint32_t CRH; |
591 | __IO uint32_t CRL; |
| 592 | __IO uint32_t CRL; |
592 | __IO uint32_t PRLH; |
| 593 | __IO uint32_t PRLH; |
593 | __IO uint32_t PRLL; |
| 594 | __IO uint32_t PRLL; |
594 | __IO uint32_t DIVH; |
| 595 | __IO uint32_t DIVH; |
595 | __IO uint32_t DIVL; |
| 596 | __IO uint32_t DIVL; |
596 | __IO uint32_t CNTH; |
| 597 | __IO uint32_t CNTH; |
597 | __IO uint32_t CNTL; |
| 598 | __IO uint32_t CNTL; |
598 | __IO uint32_t ALRH; |
| 599 | __IO uint32_t ALRH; |
599 | __IO uint32_t ALRL; |
| 600 | __IO uint32_t ALRL; |
600 | } RTC_TypeDef; |
| 601 | } RTC_TypeDef; |
601 | |
| 602 | 602 | /** |
|
| 603 | /** |
603 | * @brief Serial Peripheral Interface |
| 604 | * @brief Serial Peripheral Interface |
604 | */ |
| 605 | */ |
605 | |
| 606 | 606 | typedef struct |
|
| 607 | typedef struct |
607 | { |
| 608 | { |
608 | __IO uint32_t CR1; |
| 609 | __IO uint32_t CR1; |
609 | __IO uint32_t CR2; |
| 610 | __IO uint32_t CR2; |
610 | __IO uint32_t SR; |
| 611 | __IO uint32_t SR; |
611 | __IO uint32_t DR; |
| 612 | __IO uint32_t DR; |
612 | __IO uint32_t CRCPR; |
| 613 | __IO uint32_t CRCPR; |
613 | __IO uint32_t RXCRCR; |
| 614 | __IO uint32_t RXCRCR; |
614 | __IO uint32_t TXCRCR; |
| 615 | __IO uint32_t TXCRCR; |
615 | __IO uint32_t I2SCFGR; |
| 616 | __IO uint32_t I2SCFGR; |
616 | __IO uint32_t I2SPR; |
| 617 | __IO uint32_t I2SPR; |
617 | } SPI_TypeDef; |
| 618 | } SPI_TypeDef; |
618 | |
| 619 | 619 | /** |
|
| 620 | /** |
620 | * @brief TIM Timers |
| 621 | * @brief TIM Timers |
621 | */ |
| 622 | */ |
622 | typedef struct |
| 623 | typedef struct |
623 | { |
| 624 | { |
624 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
| 625 | __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ |
625 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
| 626 | __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ |
626 | __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ |
| 627 | __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */ |
627 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
| 628 | __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ |
628 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
| 629 | __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ |
629 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
| 630 | __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ |
630 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
| 631 | __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ |
631 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
| 632 | __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ |
632 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
| 633 | __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ |
633 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
| 634 | __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ |
634 | __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ |
| 635 | __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ |
635 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
| 636 | __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ |
636 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
| 637 | __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ |
637 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
| 638 | __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ |
638 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
| 639 | __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ |
639 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
| 640 | __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ |
640 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
| 641 | __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ |
641 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
| 642 | __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ |
642 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
| 643 | __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ |
643 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ |
| 644 | __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */ |
644 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
| 645 | __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ |
645 | }TIM_TypeDef; |
| 646 | }TIM_TypeDef; |
646 | |
| 647 | 647 | ||
| 648 | 648 | /** |
|
| 649 | /** |
649 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
| 650 | * @brief Universal Synchronous Asynchronous Receiver Transmitter |
650 | */ |
| 651 | */ |
651 | |
| 652 | 652 | typedef struct |
|
| 653 | typedef struct |
653 | { |
| 654 | { |
654 | __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ |
| 655 | __IO uint32_t SR; /*!< USART Status register, Address offset: 0x00 */ |
655 | __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ |
| 656 | __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ |
656 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ |
| 657 | __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ |
657 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ |
| 658 | __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ |
658 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ |
| 659 | __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ |
659 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ |
| 660 | __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ |
660 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ |
| 661 | __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ |
661 | } USART_TypeDef; |
| 662 | } USART_TypeDef; |
662 | |
| 663 | 663 | ||
| 664 | 664 | /** |
|
| 665 | /** |
665 | * @brief __USB_OTG_Core_register |
| 666 | * @brief __USB_OTG_Core_register |
666 | */ |
| 667 | */ |
667 | |
| 668 | 668 | typedef struct |
|
| 669 | typedef struct |
669 | { |
| 670 | { |
670 | __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset: 000h */ |
| 671 | __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register Address offset: 000h */ |
671 | __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset: 004h */ |
| 672 | __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register Address offset: 004h */ |
672 | __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset: 008h */ |
| 673 | __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register Address offset: 008h */ |
673 | __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset: 00Ch */ |
| 674 | __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register Address offset: 00Ch */ |
674 | __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */ |
| 675 | __IO uint32_t GRSTCTL; /*!< Core Reset Register Address offset: 010h */ |
675 | __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset: 014h */ |
| 676 | __IO uint32_t GINTSTS; /*!< Core Interrupt Register Address offset: 014h */ |
676 | __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset: 018h */ |
| 677 | __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register Address offset: 018h */ |
677 | __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset: 01Ch */ |
| 678 | __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register Address offset: 01Ch */ |
678 | __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */ |
| 679 | __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register Address offset: 020h */ |
679 | __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register Address offset: 024h */ |
| 680 | __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register Address offset: 024h */ |
680 | __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */ |
| 681 | __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register Address offset: 028h */ |
681 | __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */ |
| 682 | __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg Address offset: 02Ch */ |
682 | uint32_t Reserved30[2]; /*!< Reserved 030h*/ |
| 683 | uint32_t Reserved30[2]; /*!< Reserved 030h*/ |
683 | __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */ |
| 684 | __IO uint32_t GCCFG; /*!< General Purpose IO Register Address offset: 038h */ |
684 | __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */ |
| 685 | __IO uint32_t CID; /*!< User ID Register Address offset: 03Ch */ |
685 | uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ |
| 686 | uint32_t Reserved40[48]; /*!< Reserved 040h-0FFh */ |
686 | __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */ |
| 687 | __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg Address offset: 100h */ |
687 | __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */ |
| 688 | __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 0x104 */ |
688 | } USB_OTG_GlobalTypeDef; |
| 689 | } USB_OTG_GlobalTypeDef; |
689 | |
| 690 | 690 | /** |
|
| 691 | /** |
691 | * @brief __device_Registers |
| 692 | * @brief __device_Registers |
692 | */ |
| 693 | */ |
693 | |
| 694 | 694 | typedef struct |
|
| 695 | typedef struct |
695 | { |
| 696 | { |
696 | __IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/ |
| 697 | __IO uint32_t DCFG; /*!< dev Configuration Register Address offset: 800h*/ |
697 | __IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/ |
| 698 | __IO uint32_t DCTL; /*!< dev Control Register Address offset: 804h*/ |
698 | __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset: 808h*/ |
| 699 | __IO uint32_t DSTS; /*!< dev Status Register (RO) Address offset: 808h*/ |
699 | uint32_t Reserved0C; /*!< Reserved 80Ch*/ |
| 700 | uint32_t Reserved0C; /*!< Reserved 80Ch*/ |
700 | __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset: 810h*/ |
| 701 | __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask Address offset: 810h*/ |
701 | __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset: 814h*/ |
| 702 | __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask Address offset: 814h*/ |
702 | __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/ |
| 703 | __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg Address offset: 818h*/ |
703 | __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/ |
| 704 | __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask Address offset: 81Ch*/ |
704 | uint32_t Reserved20; /*!< Reserved 820h*/ |
| 705 | uint32_t Reserved20; /*!< Reserved 820h*/ |
705 | uint32_t Reserved9; /*!< Reserved 824h*/ |
| 706 | uint32_t Reserved9; /*!< Reserved 824h*/ |
706 | __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset: 828h*/ |
| 707 | __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register Address offset: 828h*/ |
707 | __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset: 82Ch*/ |
| 708 | __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register Address offset: 82Ch*/ |
708 | __IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/ |
| 709 | __IO uint32_t DTHRCTL; /*!< dev thr Address offset: 830h*/ |
709 | __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/ |
| 710 | __IO uint32_t DIEPEMPMSK; /*!< dev empty msk Address offset: 834h*/ |
710 | __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/ |
| 711 | __IO uint32_t DEACHINT; /*!< dedicated EP interrupt Address offset: 838h*/ |
711 | __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/ |
| 712 | __IO uint32_t DEACHMSK; /*!< dedicated EP msk Address offset: 83Ch*/ |
712 | uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/ |
| 713 | uint32_t Reserved40; /*!< dedicated EP mask Address offset: 840h*/ |
713 | __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/ |
| 714 | __IO uint32_t DINEP1MSK; /*!< dedicated EP mask Address offset: 844h*/ |
714 | uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/ |
| 715 | uint32_t Reserved44[15]; /*!< Reserved 844-87Ch*/ |
715 | __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/ |
| 716 | __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk Address offset: 884h*/ |
716 | } USB_OTG_DeviceTypeDef; |
| 717 | } USB_OTG_DeviceTypeDef; |
717 | |
| 718 | 718 | /** |
|
| 719 | /** |
719 | * @brief __IN_Endpoint-Specific_Register |
| 720 | * @brief __IN_Endpoint-Specific_Register |
720 | */ |
| 721 | */ |
721 | |
| 722 | 722 | typedef struct |
|
| 723 | typedef struct |
723 | { |
| 724 | { |
724 | __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ |
| 725 | __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/ |
725 | uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/ |
| 726 | uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h*/ |
726 | __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ |
| 727 | __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/ |
727 | uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/ |
| 728 | uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch*/ |
728 | __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ |
| 729 | __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/ |
729 | __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ |
| 730 | __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h*/ |
730 | __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ |
| 731 | __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/ |
731 | uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ |
| 732 | uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/ |
732 | } USB_OTG_INEndpointTypeDef; |
| 733 | } USB_OTG_INEndpointTypeDef; |
733 | |
| 734 | 734 | /** |
|
| 735 | /** |
735 | * @brief __OUT_Endpoint-Specific_Registers |
| 736 | * @brief __OUT_Endpoint-Specific_Registers |
736 | */ |
| 737 | */ |
737 | |
| 738 | 738 | typedef struct |
|
| 739 | typedef struct |
739 | { |
| 740 | { |
740 | __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ |
| 741 | __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/ |
741 | uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/ |
| 742 | uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h*/ |
742 | __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ |
| 743 | __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/ |
743 | uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/ |
| 744 | uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch*/ |
744 | __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ |
| 745 | __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/ |
745 | __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ |
| 746 | __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h*/ |
746 | uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ |
| 747 | uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch*/ |
747 | } USB_OTG_OUTEndpointTypeDef; |
| 748 | } USB_OTG_OUTEndpointTypeDef; |
748 | |
| 749 | 749 | /** |
|
| 750 | /** |
750 | * @brief __Host_Mode_Register_Structures |
| 751 | * @brief __Host_Mode_Register_Structures |
751 | */ |
| 752 | */ |
752 | |
| 753 | 753 | typedef struct |
|
| 754 | typedef struct |
754 | { |
| 755 | { |
755 | __IO uint32_t HCFG; /*!< Host Configuration Register 400h*/ |
| 756 | __IO uint32_t HCFG; /*!< Host Configuration Register 400h*/ |
756 | __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h*/ |
| 757 | __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h*/ |
757 | __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h*/ |
| 758 | __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h*/ |
758 | uint32_t Reserved40C; /*!< Reserved 40Ch*/ |
| 759 | uint32_t Reserved40C; /*!< Reserved 40Ch*/ |
759 | __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/ |
| 760 | __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h*/ |
760 | __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h*/ |
| 761 | __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h*/ |
761 | __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h*/ |
| 762 | __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h*/ |
762 | } USB_OTG_HostTypeDef; |
| 763 | } USB_OTG_HostTypeDef; |
763 | |
| 764 | 764 | /** |
|
| 765 | /** |
765 | * @brief __Host_Channel_Specific_Registers |
| 766 | * @brief __Host_Channel_Specific_Registers |
766 | */ |
| 767 | */ |
767 | |
| 768 | 768 | typedef struct |
|
| 769 | typedef struct |
769 | { |
| 770 | { |
770 | __IO uint32_t HCCHAR; |
| 771 | __IO uint32_t HCCHAR; |
771 | __IO uint32_t HCSPLT; |
| 772 | __IO uint32_t HCSPLT; |
772 | __IO uint32_t HCINT; |
| 773 | __IO uint32_t HCINT; |
773 | __IO uint32_t HCINTMSK; |
| 774 | __IO uint32_t HCINTMSK; |
774 | __IO uint32_t HCTSIZ; |
| 775 | __IO uint32_t HCTSIZ; |
775 | __IO uint32_t HCDMA; |
| 776 | __IO uint32_t HCDMA; |
776 | uint32_t Reserved[2]; |
| 777 | uint32_t Reserved[2]; |
777 | } USB_OTG_HostChannelTypeDef; |
| 778 | } USB_OTG_HostChannelTypeDef; |
778 | |
| 779 | 779 | /** |
|
| 780 | /** |
780 | * @brief Window WATCHDOG |
| 781 | * @brief Window WATCHDOG |
781 | */ |
| 782 | */ |
782 | |
| 783 | 783 | typedef struct |
|
| 784 | typedef struct |
784 | { |
| 785 | { |
785 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
| 786 | __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ |
786 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
| 787 | __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ |
787 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
| 788 | __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ |
788 | } WWDG_TypeDef; |
| 789 | } WWDG_TypeDef; |
789 | |
| 790 | 790 | /** |
|
| 791 | /** |
791 | * @} |
| 792 | * @} |
792 | */ |
| 793 | */ |
793 | |
| 794 | 794 | /** @addtogroup Peripheral_memory_map |
|
| 795 | /** @addtogroup Peripheral_memory_map |
795 | * @{ |
| 796 | * @{ |
796 | */ |
| 797 | */ |
797 | |
| 798 | 798 | ||
| 799 | 799 | #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ |
|
| 800 | #define FLASH_BASE 0x08000000UL /*!< FLASH base address in the alias region */ |
800 | #define FLASH_BANK1_END 0x0803FFFFUL /*!< FLASH END address of bank1 */ |
| 801 | #define FLASH_BANK1_END 0x0803FFFFUL /*!< FLASH END address of bank1 */ |
801 | #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ |
| 802 | #define SRAM_BASE 0x20000000UL /*!< SRAM base address in the alias region */ |
802 | #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ |
| 803 | #define PERIPH_BASE 0x40000000UL /*!< Peripheral base address in the alias region */ |
803 | |
| 804 | 804 | #define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ |
|
| 805 | #define SRAM_BB_BASE 0x22000000UL /*!< SRAM base address in the bit-band region */ |
805 | #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ |
| 806 | #define PERIPH_BB_BASE 0x42000000UL /*!< Peripheral base address in the bit-band region */ |
806 | |
| 807 | 807 | ||
| 808 | 808 | /*!< Peripheral memory map */ |
|
| 809 | /*!< Peripheral memory map */ |
809 | #define APB1PERIPH_BASE PERIPH_BASE |
| 810 | #define APB1PERIPH_BASE PERIPH_BASE |
810 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
| 811 | #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) |
811 | #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
| 812 | #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) |
812 | |
| 813 | 813 | #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) |
|
| 814 | #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL) |
814 | #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) |
| 815 | #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL) |
815 | #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) |
| 816 | #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL) |
816 | #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL) |
| 817 | #define TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL) |
817 | #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) |
| 818 | #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL) |
818 | #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) |
| 819 | #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL) |
819 | #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) |
| 820 | #define RTC_BASE (APB1PERIPH_BASE + 0x00002800UL) |
820 | #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) |
| 821 | #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL) |
821 | #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) |
| 822 | #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL) |
822 | #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) |
| 823 | #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL) |
823 | #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) |
| 824 | #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL) |
824 | #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) |
| 825 | #define USART2_BASE (APB1PERIPH_BASE + 0x00004400UL) |
825 | #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) |
| 826 | #define USART3_BASE (APB1PERIPH_BASE + 0x00004800UL) |
826 | #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) |
| 827 | #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL) |
827 | #define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) |
| 828 | #define UART5_BASE (APB1PERIPH_BASE + 0x00005000UL) |
828 | #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) |
| 829 | #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL) |
829 | #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) |
| 830 | #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL) |
830 | #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) |
| 831 | #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL) |
831 | #define CAN2_BASE (APB1PERIPH_BASE + 0x00006800UL) |
| 832 | #define CAN2_BASE (APB1PERIPH_BASE + 0x00006800UL) |
832 | #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) |
| 833 | #define BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL) |
833 | #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) |
| 834 | #define PWR_BASE (APB1PERIPH_BASE + 0x00007000UL) |
834 | #define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) |
| 835 | #define DAC_BASE (APB1PERIPH_BASE + 0x00007400UL) |
835 | #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) |
| 836 | #define AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL) |
836 | #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) |
| 837 | #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL) |
837 | #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) |
| 838 | #define GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL) |
838 | #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) |
| 839 | #define GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL) |
839 | #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) |
| 840 | #define GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL) |
840 | #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) |
| 841 | #define GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL) |
841 | #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL) |
| 842 | #define GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL) |
842 | #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) |
| 843 | #define ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL) |
843 | #define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL) |
| 844 | #define ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL) |
844 | #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) |
| 845 | #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL) |
845 | #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) |
| 846 | #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL) |
846 | #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) |
| 847 | #define USART1_BASE (APB2PERIPH_BASE + 0x00003800UL) |
847 | |
| 848 | 848 | ||
| 849 | 849 | #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) |
|
| 850 | #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) |
850 | #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) |
| 851 | #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL) |
851 | #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) |
| 852 | #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL) |
852 | #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) |
| 853 | #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL) |
853 | #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) |
| 854 | #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL) |
854 | #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) |
| 855 | #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL) |
855 | #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) |
| 856 | #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL) |
856 | #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) |
| 857 | #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL) |
857 | #define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL) |
| 858 | #define DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL) |
858 | #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL) |
| 859 | #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL) |
859 | #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL) |
| 860 | #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL) |
860 | #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL) |
| 861 | #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL) |
861 | #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL) |
| 862 | #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL) |
862 | #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL) |
| 863 | #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL) |
863 | #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) |
| 864 | #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) |
864 | #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) |
| 865 | #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) |
865 | |
| 866 | 866 | #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ |
|
| 867 | #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< Flash registers base address */ |
867 | #define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */ |
| 868 | #define FLASHSIZE_BASE 0x1FFFF7E0UL /*!< FLASH Size register base address */ |
868 | #define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */ |
| 869 | #define UID_BASE 0x1FFFF7E8UL /*!< Unique device ID register base address */ |
869 | #define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ |
| 870 | #define OB_BASE 0x1FFFF800UL /*!< Flash Option Bytes base address */ |
870 | |
| 871 | 871 | #define ETH_BASE (AHBPERIPH_BASE + 0x00008000UL) |
|
| 872 | #define ETH_BASE (AHBPERIPH_BASE + 0x00008000UL) |
872 | #define ETH_MAC_BASE (ETH_BASE) |
| 873 | #define ETH_MAC_BASE (ETH_BASE) |
873 | #define ETH_MMC_BASE (ETH_BASE + 0x00000100UL) |
| 874 | #define ETH_MMC_BASE (ETH_BASE + 0x00000100UL) |
874 | #define ETH_PTP_BASE (ETH_BASE + 0x00000700UL) |
| 875 | #define ETH_PTP_BASE (ETH_BASE + 0x00000700UL) |
875 | #define ETH_DMA_BASE (ETH_BASE + 0x00001000UL) |
| 876 | #define ETH_DMA_BASE (ETH_BASE + 0x00001000UL) |
876 | |
| 877 | 877 | ||
| 878 | 878 | #define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ |
|
| 879 | #define DBGMCU_BASE 0xE0042000UL /*!< Debug MCU registers base address */ |
879 | |
| 880 | 880 | ||
| 881 | 881 | /*!< USB registers base address */ |
|
| 882 | /*!< USB registers base address */ |
882 | #define USB_OTG_FS_PERIPH_BASE 0x50000000UL |
| 883 | #define USB_OTG_FS_PERIPH_BASE 0x50000000UL |
883 | |
| 884 | 884 | #define USB_OTG_GLOBAL_BASE 0x00000000UL |
|
| 885 | #define USB_OTG_GLOBAL_BASE 0x00000000UL |
885 | #define USB_OTG_DEVICE_BASE 0x00000800UL |
| 886 | #define USB_OTG_DEVICE_BASE 0x00000800UL |
886 | #define USB_OTG_IN_ENDPOINT_BASE 0x00000900UL |
| 887 | #define USB_OTG_IN_ENDPOINT_BASE 0x00000900UL |
887 | #define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00UL |
| 888 | #define USB_OTG_OUT_ENDPOINT_BASE 0x00000B00UL |
888 | #define USB_OTG_EP_REG_SIZE 0x00000020UL |
| 889 | #define USB_OTG_EP_REG_SIZE 0x00000020UL |
889 | #define USB_OTG_HOST_BASE 0x00000400UL |
| 890 | #define USB_OTG_HOST_BASE 0x00000400UL |
890 | #define USB_OTG_HOST_PORT_BASE 0x00000440UL |
| 891 | #define USB_OTG_HOST_PORT_BASE 0x00000440UL |
891 | #define USB_OTG_HOST_CHANNEL_BASE 0x00000500UL |
| 892 | #define USB_OTG_HOST_CHANNEL_BASE 0x00000500UL |
892 | #define USB_OTG_HOST_CHANNEL_SIZE 0x00000020UL |
| 893 | #define USB_OTG_HOST_CHANNEL_SIZE 0x00000020UL |
893 | #define USB_OTG_PCGCCTL_BASE 0x00000E00UL |
| 894 | #define USB_OTG_PCGCCTL_BASE 0x00000E00UL |
894 | #define USB_OTG_FIFO_BASE 0x00001000UL |
| 895 | #define USB_OTG_FIFO_BASE 0x00001000UL |
895 | #define USB_OTG_FIFO_SIZE 0x00001000UL |
| 896 | #define USB_OTG_FIFO_SIZE 0x00001000UL |
896 | |
| 897 | 897 | /** |
|
| 898 | /** |
898 | * @} |
| 899 | * @} |
899 | */ |
| 900 | */ |
900 | |
| 901 | 901 | /** @addtogroup Peripheral_declaration |
|
| 902 | /** @addtogroup Peripheral_declaration |
902 | * @{ |
| 903 | * @{ |
903 | */ |
| 904 | */ |
904 | |
| 905 | 905 | #define TIM2 ((TIM_TypeDef *)TIM2_BASE) |
|
| 906 | #define TIM2 ((TIM_TypeDef *)TIM2_BASE) |
906 | #define TIM3 ((TIM_TypeDef *)TIM3_BASE) |
| 907 | #define TIM3 ((TIM_TypeDef *)TIM3_BASE) |
907 | #define TIM4 ((TIM_TypeDef *)TIM4_BASE) |
| 908 | #define TIM4 ((TIM_TypeDef *)TIM4_BASE) |
908 | #define TIM5 ((TIM_TypeDef *)TIM5_BASE) |
| 909 | #define TIM5 ((TIM_TypeDef *)TIM5_BASE) |
909 | #define TIM6 ((TIM_TypeDef *)TIM6_BASE) |
| 910 | #define TIM6 ((TIM_TypeDef *)TIM6_BASE) |
910 | #define TIM7 ((TIM_TypeDef *)TIM7_BASE) |
| 911 | #define TIM7 ((TIM_TypeDef *)TIM7_BASE) |
911 | #define RTC ((RTC_TypeDef *)RTC_BASE) |
| 912 | #define RTC ((RTC_TypeDef *)RTC_BASE) |
912 | #define WWDG ((WWDG_TypeDef *)WWDG_BASE) |
| 913 | #define WWDG ((WWDG_TypeDef *)WWDG_BASE) |
913 | #define IWDG ((IWDG_TypeDef *)IWDG_BASE) |
| 914 | #define IWDG ((IWDG_TypeDef *)IWDG_BASE) |
914 | #define SPI2 ((SPI_TypeDef *)SPI2_BASE) |
| 915 | #define SPI2 ((SPI_TypeDef *)SPI2_BASE) |
915 | #define SPI3 ((SPI_TypeDef *)SPI3_BASE) |
| 916 | #define SPI3 ((SPI_TypeDef *)SPI3_BASE) |
916 | #define USART2 ((USART_TypeDef *)USART2_BASE) |
| 917 | #define USART2 ((USART_TypeDef *)USART2_BASE) |
917 | #define USART3 ((USART_TypeDef *)USART3_BASE) |
| 918 | #define USART3 ((USART_TypeDef *)USART3_BASE) |
918 | #define UART4 ((USART_TypeDef *)UART4_BASE) |
| 919 | #define UART4 ((USART_TypeDef *)UART4_BASE) |
919 | #define UART5 ((USART_TypeDef *)UART5_BASE) |
| 920 | #define UART5 ((USART_TypeDef *)UART5_BASE) |
920 | #define I2C1 ((I2C_TypeDef *)I2C1_BASE) |
| 921 | #define I2C1 ((I2C_TypeDef *)I2C1_BASE) |
921 | #define I2C2 ((I2C_TypeDef *)I2C2_BASE) |
| 922 | #define I2C2 ((I2C_TypeDef *)I2C2_BASE) |
922 | #define CAN1 ((CAN_TypeDef *)CAN1_BASE) |
| 923 | #define CAN1 ((CAN_TypeDef *)CAN1_BASE) |
923 | #define CAN2 ((CAN_TypeDef *)CAN2_BASE) |
| 924 | #define CAN2 ((CAN_TypeDef *)CAN2_BASE) |
924 | #define BKP ((BKP_TypeDef *)BKP_BASE) |
| 925 | #define BKP ((BKP_TypeDef *)BKP_BASE) |
925 | #define PWR ((PWR_TypeDef *)PWR_BASE) |
| 926 | #define PWR ((PWR_TypeDef *)PWR_BASE) |
926 | #define DAC1 ((DAC_TypeDef *)DAC_BASE) |
| 927 | #define DAC1 ((DAC_TypeDef *)DAC_BASE) |
927 | #define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */ |
| 928 | #define DAC ((DAC_TypeDef *)DAC_BASE) /* Kept for legacy purpose */ |
928 | #define AFIO ((AFIO_TypeDef *)AFIO_BASE) |
| 929 | #define AFIO ((AFIO_TypeDef *)AFIO_BASE) |
929 | #define EXTI ((EXTI_TypeDef *)EXTI_BASE) |
| 930 | #define EXTI ((EXTI_TypeDef *)EXTI_BASE) |
930 | #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) |
| 931 | #define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) |
931 | #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) |
| 932 | #define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) |
932 | #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) |
| 933 | #define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) |
933 | #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) |
| 934 | #define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) |
934 | #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) |
| 935 | #define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) |
935 | #define ADC1 ((ADC_TypeDef *)ADC1_BASE) |
| 936 | #define ADC1 ((ADC_TypeDef *)ADC1_BASE) |
936 | #define ADC2 ((ADC_TypeDef *)ADC2_BASE) |
| 937 | #define ADC2 ((ADC_TypeDef *)ADC2_BASE) |
937 | #define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) |
| 938 | #define ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE) |
938 | #define TIM1 ((TIM_TypeDef *)TIM1_BASE) |
| 939 | #define TIM1 ((TIM_TypeDef *)TIM1_BASE) |
939 | #define SPI1 ((SPI_TypeDef *)SPI1_BASE) |
| 940 | #define SPI1 ((SPI_TypeDef *)SPI1_BASE) |
940 | #define USART1 ((USART_TypeDef *)USART1_BASE) |
| 941 | #define USART1 ((USART_TypeDef *)USART1_BASE) |
941 | #define DMA1 ((DMA_TypeDef *)DMA1_BASE) |
| 942 | #define DMA1 ((DMA_TypeDef *)DMA1_BASE) |
942 | #define DMA2 ((DMA_TypeDef *)DMA2_BASE) |
| 943 | #define DMA2 ((DMA_TypeDef *)DMA2_BASE) |
943 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) |
| 944 | #define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) |
944 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) |
| 945 | #define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) |
945 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) |
| 946 | #define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) |
946 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) |
| 947 | #define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) |
947 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) |
| 948 | #define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) |
948 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) |
| 949 | #define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) |
949 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) |
| 950 | #define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) |
950 | #define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) |
| 951 | #define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) |
951 | #define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) |
| 952 | #define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) |
952 | #define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) |
| 953 | #define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) |
953 | #define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) |
| 954 | #define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) |
954 | #define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) |
| 955 | #define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) |
955 | #define RCC ((RCC_TypeDef *)RCC_BASE) |
| 956 | #define RCC ((RCC_TypeDef *)RCC_BASE) |
956 | #define CRC ((CRC_TypeDef *)CRC_BASE) |
| 957 | #define CRC ((CRC_TypeDef *)CRC_BASE) |
957 | #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) |
| 958 | #define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) |
958 | #define OB ((OB_TypeDef *)OB_BASE) |
| 959 | #define OB ((OB_TypeDef *)OB_BASE) |
959 | #define ETH ((ETH_TypeDef *) ETH_BASE) |
| 960 | #define ETH ((ETH_TypeDef *) ETH_BASE) |
960 | #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) |
| 961 | #define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) |
961 | |
| 962 | 962 | #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE) |
|
| 963 | #define USB_OTG_FS ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE) |
963 | |
| 964 | 964 | /** |
|
| 965 | /** |
965 | * @} |
| 966 | * @} |
966 | */ |
| 967 | */ |
967 | |
| 968 | 968 | /** @addtogroup Exported_constants |
|
| 969 | /** @addtogroup Exported_constants |
969 | * @{ |
| 970 | * @{ |
970 | */ |
| 971 | */ |
971 | |
| 972 | 972 | /** @addtogroup Hardware_Constant_Definition |
|
| 973 | /** @addtogroup Hardware_Constant_Definition |
973 | * @{ |
| 974 | * @{ |
974 | */ |
| 975 | */ |
975 | #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
| 976 | #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
976 | /** |
| 977 | /** |
977 | * @} |
| 978 | * @} |
978 | */ |
| 979 | */ |
979 | |
| 980 | 980 | /** @addtogroup Peripheral_Registers_Bits_Definition |
|
| 981 | /** @addtogroup Peripheral_Registers_Bits_Definition |
981 | * @{ |
| 982 | * @{ |
982 | */ |
| 983 | */ |
983 | |
| 984 | 984 | /******************************************************************************/ |
|
| 985 | /******************************************************************************/ |
985 | /* Peripheral Registers_Bits_Definition */ |
| 986 | /* Peripheral Registers_Bits_Definition */ |
986 | /******************************************************************************/ |
| 987 | /******************************************************************************/ |
987 | |
| 988 | 988 | /******************************************************************************/ |
|
| 989 | /******************************************************************************/ |
989 | /* */ |
| 990 | /* */ |
990 | /* CRC calculation unit (CRC) */ |
| 991 | /* CRC calculation unit (CRC) */ |
991 | /* */ |
| 992 | /* */ |
992 | /******************************************************************************/ |
| 993 | /******************************************************************************/ |
993 | |
| 994 | 994 | /******************* Bit definition for CRC_DR register *********************/ |
|
| 995 | /******************* Bit definition for CRC_DR register *********************/ |
995 | #define CRC_DR_DR_Pos (0U) |
| 996 | #define CRC_DR_DR_Pos (0U) |
996 | #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ |
| 997 | #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ |
997 | #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ |
| 998 | #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ |
998 | |
| 999 | 999 | /******************* Bit definition for CRC_IDR register ********************/ |
|
| 1000 | /******************* Bit definition for CRC_IDR register ********************/ |
1000 | #define CRC_IDR_IDR_Pos (0U) |
| 1001 | #define CRC_IDR_IDR_Pos (0U) |
1001 | #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ |
| 1002 | #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0x000000FF */ |
1002 | #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ |
| 1003 | #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ |
1003 | |
| 1004 | 1004 | /******************** Bit definition for CRC_CR register ********************/ |
|
| 1005 | /******************** Bit definition for CRC_CR register ********************/ |
1005 | #define CRC_CR_RESET_Pos (0U) |
| 1006 | #define CRC_CR_RESET_Pos (0U) |
1006 | #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ |
| 1007 | #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ |
1007 | #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ |
| 1008 | #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET bit */ |
1008 | |
| 1009 | 1009 | /******************************************************************************/ |
|
| 1010 | /******************************************************************************/ |
1010 | /* */ |
| 1011 | /* */ |
1011 | /* Power Control */ |
| 1012 | /* Power Control */ |
1012 | /* */ |
| 1013 | /* */ |
1013 | /******************************************************************************/ |
| 1014 | /******************************************************************************/ |
1014 | |
| 1015 | 1015 | /******************** Bit definition for PWR_CR register ********************/ |
|
| 1016 | /******************** Bit definition for PWR_CR register ********************/ |
1016 | #define PWR_CR_LPDS_Pos (0U) |
| 1017 | #define PWR_CR_LPDS_Pos (0U) |
1017 | #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ |
| 1018 | #define PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos) /*!< 0x00000001 */ |
1018 | #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ |
| 1019 | #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-Power Deepsleep */ |
1019 | #define PWR_CR_PDDS_Pos (1U) |
| 1020 | #define PWR_CR_PDDS_Pos (1U) |
1020 | #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ |
| 1021 | #define PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos) /*!< 0x00000002 */ |
1021 | #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ |
| 1022 | #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */ |
1022 | #define PWR_CR_CWUF_Pos (2U) |
| 1023 | #define PWR_CR_CWUF_Pos (2U) |
1023 | #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ |
| 1024 | #define PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos) /*!< 0x00000004 */ |
1024 | #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ |
| 1025 | #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */ |
1025 | #define PWR_CR_CSBF_Pos (3U) |
| 1026 | #define PWR_CR_CSBF_Pos (3U) |
1026 | #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ |
| 1027 | #define PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos) /*!< 0x00000008 */ |
1027 | #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ |
| 1028 | #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */ |
1028 | #define PWR_CR_PVDE_Pos (4U) |
| 1029 | #define PWR_CR_PVDE_Pos (4U) |
1029 | #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ |
| 1030 | #define PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos) /*!< 0x00000010 */ |
1030 | #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ |
| 1031 | #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */ |
1031 | |
| 1032 | 1032 | #define PWR_CR_PLS_Pos (5U) |
|
| 1033 | #define PWR_CR_PLS_Pos (5U) |
1033 | #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ |
| 1034 | #define PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos) /*!< 0x000000E0 */ |
1034 | #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ |
| 1035 | #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */ |
1035 | #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ |
| 1036 | #define PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos) /*!< 0x00000020 */ |
1036 | #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ |
| 1037 | #define PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos) /*!< 0x00000040 */ |
1037 | #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ |
| 1038 | #define PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos) /*!< 0x00000080 */ |
1038 | |
| 1039 | 1039 | /*!< PVD level configuration */ |
|
| 1040 | /*!< PVD level configuration */ |
1040 | #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ |
| 1041 | #define PWR_CR_PLS_LEV0 0x00000000U /*!< PVD level 2.2V */ |
1041 | #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ |
| 1042 | #define PWR_CR_PLS_LEV1 0x00000020U /*!< PVD level 2.3V */ |
1042 | #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ |
| 1043 | #define PWR_CR_PLS_LEV2 0x00000040U /*!< PVD level 2.4V */ |
1043 | #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ |
| 1044 | #define PWR_CR_PLS_LEV3 0x00000060U /*!< PVD level 2.5V */ |
1044 | #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ |
| 1045 | #define PWR_CR_PLS_LEV4 0x00000080U /*!< PVD level 2.6V */ |
1045 | #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ |
| 1046 | #define PWR_CR_PLS_LEV5 0x000000A0U /*!< PVD level 2.7V */ |
1046 | #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ |
| 1047 | #define PWR_CR_PLS_LEV6 0x000000C0U /*!< PVD level 2.8V */ |
1047 | #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ |
| 1048 | #define PWR_CR_PLS_LEV7 0x000000E0U /*!< PVD level 2.9V */ |
1048 | |
| 1049 | 1049 | /* Legacy defines */ |
|
| 1050 | /* Legacy defines */ |
1050 | #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 |
| 1051 | #define PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0 |
1051 | #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 |
| 1052 | #define PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1 |
1052 | #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 |
| 1053 | #define PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2 |
1053 | #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 |
| 1054 | #define PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3 |
1054 | #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 |
| 1055 | #define PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4 |
1055 | #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 |
| 1056 | #define PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5 |
1056 | #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 |
| 1057 | #define PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6 |
1057 | #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 |
| 1058 | #define PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7 |
1058 | |
| 1059 | 1059 | #define PWR_CR_DBP_Pos (8U) |
|
| 1060 | #define PWR_CR_DBP_Pos (8U) |
1060 | #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ |
| 1061 | #define PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos) /*!< 0x00000100 */ |
1061 | #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ |
| 1062 | #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */ |
1062 | |
| 1063 | 1063 | ||
| 1064 | 1064 | /******************* Bit definition for PWR_CSR register ********************/ |
|
| 1065 | /******************* Bit definition for PWR_CSR register ********************/ |
1065 | #define PWR_CSR_WUF_Pos (0U) |
| 1066 | #define PWR_CSR_WUF_Pos (0U) |
1066 | #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ |
| 1067 | #define PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos) /*!< 0x00000001 */ |
1067 | #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ |
| 1068 | #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */ |
1068 | #define PWR_CSR_SBF_Pos (1U) |
| 1069 | #define PWR_CSR_SBF_Pos (1U) |
1069 | #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ |
| 1070 | #define PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos) /*!< 0x00000002 */ |
1070 | #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ |
| 1071 | #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */ |
1071 | #define PWR_CSR_PVDO_Pos (2U) |
| 1072 | #define PWR_CSR_PVDO_Pos (2U) |
1072 | #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ |
| 1073 | #define PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */ |
1073 | #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ |
| 1074 | #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */ |
1074 | #define PWR_CSR_EWUP_Pos (8U) |
| 1075 | #define PWR_CSR_EWUP_Pos (8U) |
1075 | #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ |
| 1076 | #define PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ |
1076 | #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ |
| 1077 | #define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ |
1077 | |
| 1078 | 1078 | /******************************************************************************/ |
|
| 1079 | /******************************************************************************/ |
1079 | /* */ |
| 1080 | /* */ |
1080 | /* Backup registers */ |
| 1081 | /* Backup registers */ |
1081 | /* */ |
| 1082 | /* */ |
1082 | /******************************************************************************/ |
| 1083 | /******************************************************************************/ |
1083 | |
| 1084 | 1084 | /******************* Bit definition for BKP_DR1 register ********************/ |
|
| 1085 | /******************* Bit definition for BKP_DR1 register ********************/ |
1085 | #define BKP_DR1_D_Pos (0U) |
| 1086 | #define BKP_DR1_D_Pos (0U) |
1086 | #define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ |
| 1087 | #define BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos) /*!< 0x0000FFFF */ |
1087 | #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ |
| 1088 | #define BKP_DR1_D BKP_DR1_D_Msk /*!< Backup data */ |
1088 | |
| 1089 | 1089 | /******************* Bit definition for BKP_DR2 register ********************/ |
|
| 1090 | /******************* Bit definition for BKP_DR2 register ********************/ |
1090 | #define BKP_DR2_D_Pos (0U) |
| 1091 | #define BKP_DR2_D_Pos (0U) |
1091 | #define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ |
| 1092 | #define BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos) /*!< 0x0000FFFF */ |
1092 | #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ |
| 1093 | #define BKP_DR2_D BKP_DR2_D_Msk /*!< Backup data */ |
1093 | |
| 1094 | 1094 | /******************* Bit definition for BKP_DR3 register ********************/ |
|
| 1095 | /******************* Bit definition for BKP_DR3 register ********************/ |
1095 | #define BKP_DR3_D_Pos (0U) |
| 1096 | #define BKP_DR3_D_Pos (0U) |
1096 | #define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ |
| 1097 | #define BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos) /*!< 0x0000FFFF */ |
1097 | #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ |
| 1098 | #define BKP_DR3_D BKP_DR3_D_Msk /*!< Backup data */ |
1098 | |
| 1099 | 1099 | /******************* Bit definition for BKP_DR4 register ********************/ |
|
| 1100 | /******************* Bit definition for BKP_DR4 register ********************/ |
1100 | #define BKP_DR4_D_Pos (0U) |
| 1101 | #define BKP_DR4_D_Pos (0U) |
1101 | #define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ |
| 1102 | #define BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos) /*!< 0x0000FFFF */ |
1102 | #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ |
| 1103 | #define BKP_DR4_D BKP_DR4_D_Msk /*!< Backup data */ |
1103 | |
| 1104 | 1104 | /******************* Bit definition for BKP_DR5 register ********************/ |
|
| 1105 | /******************* Bit definition for BKP_DR5 register ********************/ |
1105 | #define BKP_DR5_D_Pos (0U) |
| 1106 | #define BKP_DR5_D_Pos (0U) |
1106 | #define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ |
| 1107 | #define BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos) /*!< 0x0000FFFF */ |
1107 | #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ |
| 1108 | #define BKP_DR5_D BKP_DR5_D_Msk /*!< Backup data */ |
1108 | |
| 1109 | 1109 | /******************* Bit definition for BKP_DR6 register ********************/ |
|
| 1110 | /******************* Bit definition for BKP_DR6 register ********************/ |
1110 | #define BKP_DR6_D_Pos (0U) |
| 1111 | #define BKP_DR6_D_Pos (0U) |
1111 | #define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ |
| 1112 | #define BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos) /*!< 0x0000FFFF */ |
1112 | #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ |
| 1113 | #define BKP_DR6_D BKP_DR6_D_Msk /*!< Backup data */ |
1113 | |
| 1114 | 1114 | /******************* Bit definition for BKP_DR7 register ********************/ |
|
| 1115 | /******************* Bit definition for BKP_DR7 register ********************/ |
1115 | #define BKP_DR7_D_Pos (0U) |
| 1116 | #define BKP_DR7_D_Pos (0U) |
1116 | #define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ |
| 1117 | #define BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos) /*!< 0x0000FFFF */ |
1117 | #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ |
| 1118 | #define BKP_DR7_D BKP_DR7_D_Msk /*!< Backup data */ |
1118 | |
| 1119 | 1119 | /******************* Bit definition for BKP_DR8 register ********************/ |
|
| 1120 | /******************* Bit definition for BKP_DR8 register ********************/ |
1120 | #define BKP_DR8_D_Pos (0U) |
| 1121 | #define BKP_DR8_D_Pos (0U) |
1121 | #define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ |
| 1122 | #define BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos) /*!< 0x0000FFFF */ |
1122 | #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ |
| 1123 | #define BKP_DR8_D BKP_DR8_D_Msk /*!< Backup data */ |
1123 | |
| 1124 | 1124 | /******************* Bit definition for BKP_DR9 register ********************/ |
|
| 1125 | /******************* Bit definition for BKP_DR9 register ********************/ |
1125 | #define BKP_DR9_D_Pos (0U) |
| 1126 | #define BKP_DR9_D_Pos (0U) |
1126 | #define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ |
| 1127 | #define BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos) /*!< 0x0000FFFF */ |
1127 | #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ |
| 1128 | #define BKP_DR9_D BKP_DR9_D_Msk /*!< Backup data */ |
1128 | |
| 1129 | 1129 | /******************* Bit definition for BKP_DR10 register *******************/ |
|
| 1130 | /******************* Bit definition for BKP_DR10 register *******************/ |
1130 | #define BKP_DR10_D_Pos (0U) |
| 1131 | #define BKP_DR10_D_Pos (0U) |
1131 | #define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ |
| 1132 | #define BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos) /*!< 0x0000FFFF */ |
1132 | #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ |
| 1133 | #define BKP_DR10_D BKP_DR10_D_Msk /*!< Backup data */ |
1133 | |
| 1134 | 1134 | /******************* Bit definition for BKP_DR11 register *******************/ |
|
| 1135 | /******************* Bit definition for BKP_DR11 register *******************/ |
1135 | #define BKP_DR11_D_Pos (0U) |
| 1136 | #define BKP_DR11_D_Pos (0U) |
1136 | #define BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos) /*!< 0x0000FFFF */ |
| 1137 | #define BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos) /*!< 0x0000FFFF */ |
1137 | #define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */ |
| 1138 | #define BKP_DR11_D BKP_DR11_D_Msk /*!< Backup data */ |
1138 | |
| 1139 | 1139 | /******************* Bit definition for BKP_DR12 register *******************/ |
|
| 1140 | /******************* Bit definition for BKP_DR12 register *******************/ |
1140 | #define BKP_DR12_D_Pos (0U) |
| 1141 | #define BKP_DR12_D_Pos (0U) |
1141 | #define BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos) /*!< 0x0000FFFF */ |
| 1142 | #define BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos) /*!< 0x0000FFFF */ |
1142 | #define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */ |
| 1143 | #define BKP_DR12_D BKP_DR12_D_Msk /*!< Backup data */ |
1143 | |
| 1144 | 1144 | /******************* Bit definition for BKP_DR13 register *******************/ |
|
| 1145 | /******************* Bit definition for BKP_DR13 register *******************/ |
1145 | #define BKP_DR13_D_Pos (0U) |
| 1146 | #define BKP_DR13_D_Pos (0U) |
1146 | #define BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos) /*!< 0x0000FFFF */ |
| 1147 | #define BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos) /*!< 0x0000FFFF */ |
1147 | #define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */ |
| 1148 | #define BKP_DR13_D BKP_DR13_D_Msk /*!< Backup data */ |
1148 | |
| 1149 | 1149 | /******************* Bit definition for BKP_DR14 register *******************/ |
|
| 1150 | /******************* Bit definition for BKP_DR14 register *******************/ |
1150 | #define BKP_DR14_D_Pos (0U) |
| 1151 | #define BKP_DR14_D_Pos (0U) |
1151 | #define BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos) /*!< 0x0000FFFF */ |
| 1152 | #define BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos) /*!< 0x0000FFFF */ |
1152 | #define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */ |
| 1153 | #define BKP_DR14_D BKP_DR14_D_Msk /*!< Backup data */ |
1153 | |
| 1154 | 1154 | /******************* Bit definition for BKP_DR15 register *******************/ |
|
| 1155 | /******************* Bit definition for BKP_DR15 register *******************/ |
1155 | #define BKP_DR15_D_Pos (0U) |
| 1156 | #define BKP_DR15_D_Pos (0U) |
1156 | #define BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos) /*!< 0x0000FFFF */ |
| 1157 | #define BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos) /*!< 0x0000FFFF */ |
1157 | #define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */ |
| 1158 | #define BKP_DR15_D BKP_DR15_D_Msk /*!< Backup data */ |
1158 | |
| 1159 | 1159 | /******************* Bit definition for BKP_DR16 register *******************/ |
|
| 1160 | /******************* Bit definition for BKP_DR16 register *******************/ |
1160 | #define BKP_DR16_D_Pos (0U) |
| 1161 | #define BKP_DR16_D_Pos (0U) |
1161 | #define BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos) /*!< 0x0000FFFF */ |
| 1162 | #define BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos) /*!< 0x0000FFFF */ |
1162 | #define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */ |
| 1163 | #define BKP_DR16_D BKP_DR16_D_Msk /*!< Backup data */ |
1163 | |
| 1164 | 1164 | /******************* Bit definition for BKP_DR17 register *******************/ |
|
| 1165 | /******************* Bit definition for BKP_DR17 register *******************/ |
1165 | #define BKP_DR17_D_Pos (0U) |
| 1166 | #define BKP_DR17_D_Pos (0U) |
1166 | #define BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos) /*!< 0x0000FFFF */ |
| 1167 | #define BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos) /*!< 0x0000FFFF */ |
1167 | #define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */ |
| 1168 | #define BKP_DR17_D BKP_DR17_D_Msk /*!< Backup data */ |
1168 | |
| 1169 | 1169 | /****************** Bit definition for BKP_DR18 register ********************/ |
|
| 1170 | /****************** Bit definition for BKP_DR18 register ********************/ |
1170 | #define BKP_DR18_D_Pos (0U) |
| 1171 | #define BKP_DR18_D_Pos (0U) |
1171 | #define BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos) /*!< 0x0000FFFF */ |
| 1172 | #define BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos) /*!< 0x0000FFFF */ |
1172 | #define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */ |
| 1173 | #define BKP_DR18_D BKP_DR18_D_Msk /*!< Backup data */ |
1173 | |
| 1174 | 1174 | /******************* Bit definition for BKP_DR19 register *******************/ |
|
| 1175 | /******************* Bit definition for BKP_DR19 register *******************/ |
1175 | #define BKP_DR19_D_Pos (0U) |
| 1176 | #define BKP_DR19_D_Pos (0U) |
1176 | #define BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos) /*!< 0x0000FFFF */ |
| 1177 | #define BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos) /*!< 0x0000FFFF */ |
1177 | #define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */ |
| 1178 | #define BKP_DR19_D BKP_DR19_D_Msk /*!< Backup data */ |
1178 | |
| 1179 | 1179 | /******************* Bit definition for BKP_DR20 register *******************/ |
|
| 1180 | /******************* Bit definition for BKP_DR20 register *******************/ |
1180 | #define BKP_DR20_D_Pos (0U) |
| 1181 | #define BKP_DR20_D_Pos (0U) |
1181 | #define BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos) /*!< 0x0000FFFF */ |
| 1182 | #define BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos) /*!< 0x0000FFFF */ |
1182 | #define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */ |
| 1183 | #define BKP_DR20_D BKP_DR20_D_Msk /*!< Backup data */ |
1183 | |
| 1184 | 1184 | /******************* Bit definition for BKP_DR21 register *******************/ |
|
| 1185 | /******************* Bit definition for BKP_DR21 register *******************/ |
1185 | #define BKP_DR21_D_Pos (0U) |
| 1186 | #define BKP_DR21_D_Pos (0U) |
1186 | #define BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos) /*!< 0x0000FFFF */ |
| 1187 | #define BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos) /*!< 0x0000FFFF */ |
1187 | #define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */ |
| 1188 | #define BKP_DR21_D BKP_DR21_D_Msk /*!< Backup data */ |
1188 | |
| 1189 | 1189 | /******************* Bit definition for BKP_DR22 register *******************/ |
|
| 1190 | /******************* Bit definition for BKP_DR22 register *******************/ |
1190 | #define BKP_DR22_D_Pos (0U) |
| 1191 | #define BKP_DR22_D_Pos (0U) |
1191 | #define BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos) /*!< 0x0000FFFF */ |
| 1192 | #define BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos) /*!< 0x0000FFFF */ |
1192 | #define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */ |
| 1193 | #define BKP_DR22_D BKP_DR22_D_Msk /*!< Backup data */ |
1193 | |
| 1194 | 1194 | /******************* Bit definition for BKP_DR23 register *******************/ |
|
| 1195 | /******************* Bit definition for BKP_DR23 register *******************/ |
1195 | #define BKP_DR23_D_Pos (0U) |
| 1196 | #define BKP_DR23_D_Pos (0U) |
1196 | #define BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos) /*!< 0x0000FFFF */ |
| 1197 | #define BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos) /*!< 0x0000FFFF */ |
1197 | #define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */ |
| 1198 | #define BKP_DR23_D BKP_DR23_D_Msk /*!< Backup data */ |
1198 | |
| 1199 | 1199 | /******************* Bit definition for BKP_DR24 register *******************/ |
|
| 1200 | /******************* Bit definition for BKP_DR24 register *******************/ |
1200 | #define BKP_DR24_D_Pos (0U) |
| 1201 | #define BKP_DR24_D_Pos (0U) |
1201 | #define BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos) /*!< 0x0000FFFF */ |
| 1202 | #define BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos) /*!< 0x0000FFFF */ |
1202 | #define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */ |
| 1203 | #define BKP_DR24_D BKP_DR24_D_Msk /*!< Backup data */ |
1203 | |
| 1204 | 1204 | /******************* Bit definition for BKP_DR25 register *******************/ |
|
| 1205 | /******************* Bit definition for BKP_DR25 register *******************/ |
1205 | #define BKP_DR25_D_Pos (0U) |
| 1206 | #define BKP_DR25_D_Pos (0U) |
1206 | #define BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos) /*!< 0x0000FFFF */ |
| 1207 | #define BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos) /*!< 0x0000FFFF */ |
1207 | #define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */ |
| 1208 | #define BKP_DR25_D BKP_DR25_D_Msk /*!< Backup data */ |
1208 | |
| 1209 | 1209 | /******************* Bit definition for BKP_DR26 register *******************/ |
|
| 1210 | /******************* Bit definition for BKP_DR26 register *******************/ |
1210 | #define BKP_DR26_D_Pos (0U) |
| 1211 | #define BKP_DR26_D_Pos (0U) |
1211 | #define BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos) /*!< 0x0000FFFF */ |
| 1212 | #define BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos) /*!< 0x0000FFFF */ |
1212 | #define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */ |
| 1213 | #define BKP_DR26_D BKP_DR26_D_Msk /*!< Backup data */ |
1213 | |
| 1214 | 1214 | /******************* Bit definition for BKP_DR27 register *******************/ |
|
| 1215 | /******************* Bit definition for BKP_DR27 register *******************/ |
1215 | #define BKP_DR27_D_Pos (0U) |
| 1216 | #define BKP_DR27_D_Pos (0U) |
1216 | #define BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos) /*!< 0x0000FFFF */ |
| 1217 | #define BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos) /*!< 0x0000FFFF */ |
1217 | #define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */ |
| 1218 | #define BKP_DR27_D BKP_DR27_D_Msk /*!< Backup data */ |
1218 | |
| 1219 | 1219 | /******************* Bit definition for BKP_DR28 register *******************/ |
|
| 1220 | /******************* Bit definition for BKP_DR28 register *******************/ |
1220 | #define BKP_DR28_D_Pos (0U) |
| 1221 | #define BKP_DR28_D_Pos (0U) |
1221 | #define BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos) /*!< 0x0000FFFF */ |
| 1222 | #define BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos) /*!< 0x0000FFFF */ |
1222 | #define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */ |
| 1223 | #define BKP_DR28_D BKP_DR28_D_Msk /*!< Backup data */ |
1223 | |
| 1224 | 1224 | /******************* Bit definition for BKP_DR29 register *******************/ |
|
| 1225 | /******************* Bit definition for BKP_DR29 register *******************/ |
1225 | #define BKP_DR29_D_Pos (0U) |
| 1226 | #define BKP_DR29_D_Pos (0U) |
1226 | #define BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos) /*!< 0x0000FFFF */ |
| 1227 | #define BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos) /*!< 0x0000FFFF */ |
1227 | #define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */ |
| 1228 | #define BKP_DR29_D BKP_DR29_D_Msk /*!< Backup data */ |
1228 | |
| 1229 | 1229 | /******************* Bit definition for BKP_DR30 register *******************/ |
|
| 1230 | /******************* Bit definition for BKP_DR30 register *******************/ |
1230 | #define BKP_DR30_D_Pos (0U) |
| 1231 | #define BKP_DR30_D_Pos (0U) |
1231 | #define BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos) /*!< 0x0000FFFF */ |
| 1232 | #define BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos) /*!< 0x0000FFFF */ |
1232 | #define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */ |
| 1233 | #define BKP_DR30_D BKP_DR30_D_Msk /*!< Backup data */ |
1233 | |
| 1234 | 1234 | /******************* Bit definition for BKP_DR31 register *******************/ |
|
| 1235 | /******************* Bit definition for BKP_DR31 register *******************/ |
1235 | #define BKP_DR31_D_Pos (0U) |
| 1236 | #define BKP_DR31_D_Pos (0U) |
1236 | #define BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos) /*!< 0x0000FFFF */ |
| 1237 | #define BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos) /*!< 0x0000FFFF */ |
1237 | #define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */ |
| 1238 | #define BKP_DR31_D BKP_DR31_D_Msk /*!< Backup data */ |
1238 | |
| 1239 | 1239 | /******************* Bit definition for BKP_DR32 register *******************/ |
|
| 1240 | /******************* Bit definition for BKP_DR32 register *******************/ |
1240 | #define BKP_DR32_D_Pos (0U) |
| 1241 | #define BKP_DR32_D_Pos (0U) |
1241 | #define BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos) /*!< 0x0000FFFF */ |
| 1242 | #define BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos) /*!< 0x0000FFFF */ |
1242 | #define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */ |
| 1243 | #define BKP_DR32_D BKP_DR32_D_Msk /*!< Backup data */ |
1243 | |
| 1244 | 1244 | /******************* Bit definition for BKP_DR33 register *******************/ |
|
| 1245 | /******************* Bit definition for BKP_DR33 register *******************/ |
1245 | #define BKP_DR33_D_Pos (0U) |
| 1246 | #define BKP_DR33_D_Pos (0U) |
1246 | #define BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos) /*!< 0x0000FFFF */ |
| 1247 | #define BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos) /*!< 0x0000FFFF */ |
1247 | #define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */ |
| 1248 | #define BKP_DR33_D BKP_DR33_D_Msk /*!< Backup data */ |
1248 | |
| 1249 | 1249 | /******************* Bit definition for BKP_DR34 register *******************/ |
|
| 1250 | /******************* Bit definition for BKP_DR34 register *******************/ |
1250 | #define BKP_DR34_D_Pos (0U) |
| 1251 | #define BKP_DR34_D_Pos (0U) |
1251 | #define BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos) /*!< 0x0000FFFF */ |
| 1252 | #define BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos) /*!< 0x0000FFFF */ |
1252 | #define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */ |
| 1253 | #define BKP_DR34_D BKP_DR34_D_Msk /*!< Backup data */ |
1253 | |
| 1254 | 1254 | /******************* Bit definition for BKP_DR35 register *******************/ |
|
| 1255 | /******************* Bit definition for BKP_DR35 register *******************/ |
1255 | #define BKP_DR35_D_Pos (0U) |
| 1256 | #define BKP_DR35_D_Pos (0U) |
1256 | #define BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos) /*!< 0x0000FFFF */ |
| 1257 | #define BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos) /*!< 0x0000FFFF */ |
1257 | #define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */ |
| 1258 | #define BKP_DR35_D BKP_DR35_D_Msk /*!< Backup data */ |
1258 | |
| 1259 | 1259 | /******************* Bit definition for BKP_DR36 register *******************/ |
|
| 1260 | /******************* Bit definition for BKP_DR36 register *******************/ |
1260 | #define BKP_DR36_D_Pos (0U) |
| 1261 | #define BKP_DR36_D_Pos (0U) |
1261 | #define BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos) /*!< 0x0000FFFF */ |
| 1262 | #define BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos) /*!< 0x0000FFFF */ |
1262 | #define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */ |
| 1263 | #define BKP_DR36_D BKP_DR36_D_Msk /*!< Backup data */ |
1263 | |
| 1264 | 1264 | /******************* Bit definition for BKP_DR37 register *******************/ |
|
| 1265 | /******************* Bit definition for BKP_DR37 register *******************/ |
1265 | #define BKP_DR37_D_Pos (0U) |
| 1266 | #define BKP_DR37_D_Pos (0U) |
1266 | #define BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos) /*!< 0x0000FFFF */ |
| 1267 | #define BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos) /*!< 0x0000FFFF */ |
1267 | #define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */ |
| 1268 | #define BKP_DR37_D BKP_DR37_D_Msk /*!< Backup data */ |
1268 | |
| 1269 | 1269 | /******************* Bit definition for BKP_DR38 register *******************/ |
|
| 1270 | /******************* Bit definition for BKP_DR38 register *******************/ |
1270 | #define BKP_DR38_D_Pos (0U) |
| 1271 | #define BKP_DR38_D_Pos (0U) |
1271 | #define BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos) /*!< 0x0000FFFF */ |
| 1272 | #define BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos) /*!< 0x0000FFFF */ |
1272 | #define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */ |
| 1273 | #define BKP_DR38_D BKP_DR38_D_Msk /*!< Backup data */ |
1273 | |
| 1274 | 1274 | /******************* Bit definition for BKP_DR39 register *******************/ |
|
| 1275 | /******************* Bit definition for BKP_DR39 register *******************/ |
1275 | #define BKP_DR39_D_Pos (0U) |
| 1276 | #define BKP_DR39_D_Pos (0U) |
1276 | #define BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos) /*!< 0x0000FFFF */ |
| 1277 | #define BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos) /*!< 0x0000FFFF */ |
1277 | #define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */ |
| 1278 | #define BKP_DR39_D BKP_DR39_D_Msk /*!< Backup data */ |
1278 | |
| 1279 | 1279 | /******************* Bit definition for BKP_DR40 register *******************/ |
|
| 1280 | /******************* Bit definition for BKP_DR40 register *******************/ |
1280 | #define BKP_DR40_D_Pos (0U) |
| 1281 | #define BKP_DR40_D_Pos (0U) |
1281 | #define BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos) /*!< 0x0000FFFF */ |
| 1282 | #define BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos) /*!< 0x0000FFFF */ |
1282 | #define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */ |
| 1283 | #define BKP_DR40_D BKP_DR40_D_Msk /*!< Backup data */ |
1283 | |
| 1284 | 1284 | /******************* Bit definition for BKP_DR41 register *******************/ |
|
| 1285 | /******************* Bit definition for BKP_DR41 register *******************/ |
1285 | #define BKP_DR41_D_Pos (0U) |
| 1286 | #define BKP_DR41_D_Pos (0U) |
1286 | #define BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos) /*!< 0x0000FFFF */ |
| 1287 | #define BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos) /*!< 0x0000FFFF */ |
1287 | #define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */ |
| 1288 | #define BKP_DR41_D BKP_DR41_D_Msk /*!< Backup data */ |
1288 | |
| 1289 | 1289 | /******************* Bit definition for BKP_DR42 register *******************/ |
|
| 1290 | /******************* Bit definition for BKP_DR42 register *******************/ |
1290 | #define BKP_DR42_D_Pos (0U) |
| 1291 | #define BKP_DR42_D_Pos (0U) |
1291 | #define BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos) /*!< 0x0000FFFF */ |
| 1292 | #define BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos) /*!< 0x0000FFFF */ |
1292 | #define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */ |
| 1293 | #define BKP_DR42_D BKP_DR42_D_Msk /*!< Backup data */ |
1293 | |
| 1294 | 1294 | #define RTC_BKP_NUMBER 42 |
|
| 1295 | #define RTC_BKP_NUMBER 42 |
1295 | |
| 1296 | 1296 | /****************** Bit definition for BKP_RTCCR register *******************/ |
|
| 1297 | /****************** Bit definition for BKP_RTCCR register *******************/ |
1297 | #define BKP_RTCCR_CAL_Pos (0U) |
| 1298 | #define BKP_RTCCR_CAL_Pos (0U) |
1298 | #define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ |
| 1299 | #define BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos) /*!< 0x0000007F */ |
1299 | #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ |
| 1300 | #define BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk /*!< Calibration value */ |
1300 | #define BKP_RTCCR_CCO_Pos (7U) |
| 1301 | #define BKP_RTCCR_CCO_Pos (7U) |
1301 | #define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ |
| 1302 | #define BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos) /*!< 0x00000080 */ |
1302 | #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ |
| 1303 | #define BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk /*!< Calibration Clock Output */ |
1303 | #define BKP_RTCCR_ASOE_Pos (8U) |
| 1304 | #define BKP_RTCCR_ASOE_Pos (8U) |
1304 | #define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ |
| 1305 | #define BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos) /*!< 0x00000100 */ |
1305 | #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ |
| 1306 | #define BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk /*!< Alarm or Second Output Enable */ |
1306 | #define BKP_RTCCR_ASOS_Pos (9U) |
| 1307 | #define BKP_RTCCR_ASOS_Pos (9U) |
1307 | #define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ |
| 1308 | #define BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos) /*!< 0x00000200 */ |
1308 | #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ |
| 1309 | #define BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk /*!< Alarm or Second Output Selection */ |
1309 | |
| 1310 | 1310 | /******************** Bit definition for BKP_CR register ********************/ |
|
| 1311 | /******************** Bit definition for BKP_CR register ********************/ |
1311 | #define BKP_CR_TPE_Pos (0U) |
| 1312 | #define BKP_CR_TPE_Pos (0U) |
1312 | #define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */ |
| 1313 | #define BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos) /*!< 0x00000001 */ |
1313 | #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ |
| 1314 | #define BKP_CR_TPE BKP_CR_TPE_Msk /*!< TAMPER pin enable */ |
1314 | #define BKP_CR_TPAL_Pos (1U) |
| 1315 | #define BKP_CR_TPAL_Pos (1U) |
1315 | #define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ |
| 1316 | #define BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos) /*!< 0x00000002 */ |
1316 | #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ |
| 1317 | #define BKP_CR_TPAL BKP_CR_TPAL_Msk /*!< TAMPER pin active level */ |
1317 | |
| 1318 | 1318 | /******************* Bit definition for BKP_CSR register ********************/ |
|
| 1319 | /******************* Bit definition for BKP_CSR register ********************/ |
1319 | #define BKP_CSR_CTE_Pos (0U) |
| 1320 | #define BKP_CSR_CTE_Pos (0U) |
1320 | #define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ |
| 1321 | #define BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos) /*!< 0x00000001 */ |
1321 | #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ |
| 1322 | #define BKP_CSR_CTE BKP_CSR_CTE_Msk /*!< Clear Tamper event */ |
1322 | #define BKP_CSR_CTI_Pos (1U) |
| 1323 | #define BKP_CSR_CTI_Pos (1U) |
1323 | #define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ |
| 1324 | #define BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos) /*!< 0x00000002 */ |
1324 | #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ |
| 1325 | #define BKP_CSR_CTI BKP_CSR_CTI_Msk /*!< Clear Tamper Interrupt */ |
1325 | #define BKP_CSR_TPIE_Pos (2U) |
| 1326 | #define BKP_CSR_TPIE_Pos (2U) |
1326 | #define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ |
| 1327 | #define BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos) /*!< 0x00000004 */ |
1327 | #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ |
| 1328 | #define BKP_CSR_TPIE BKP_CSR_TPIE_Msk /*!< TAMPER Pin interrupt enable */ |
1328 | #define BKP_CSR_TEF_Pos (8U) |
| 1329 | #define BKP_CSR_TEF_Pos (8U) |
1329 | #define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ |
| 1330 | #define BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos) /*!< 0x00000100 */ |
1330 | #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ |
| 1331 | #define BKP_CSR_TEF BKP_CSR_TEF_Msk /*!< Tamper Event Flag */ |
1331 | #define BKP_CSR_TIF_Pos (9U) |
| 1332 | #define BKP_CSR_TIF_Pos (9U) |
1332 | #define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ |
| 1333 | #define BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos) /*!< 0x00000200 */ |
1333 | #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ |
| 1334 | #define BKP_CSR_TIF BKP_CSR_TIF_Msk /*!< Tamper Interrupt Flag */ |
1334 | |
| 1335 | 1335 | /******************************************************************************/ |
|
| 1336 | /******************************************************************************/ |
1336 | /* */ |
| 1337 | /* */ |
1337 | /* Reset and Clock Control */ |
| 1338 | /* Reset and Clock Control */ |
1338 | /* */ |
| 1339 | /* */ |
1339 | /******************************************************************************/ |
| 1340 | /******************************************************************************/ |
1340 | /* |
| 1341 | /* |
1341 | * @brief Specific device feature definitions (not present on all devices in the STM32F1 series) |
| 1342 | * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie) |
1342 | */ |
| 1343 | */ |
1343 | #define RCC_PLL2_SUPPORT /*!< Support PLL2 */ |
| 1344 | #define RCC_PLL2_SUPPORT /*!< Support PLL2 */ |
1344 | #define RCC_PLLI2S_SUPPORT |
| 1345 | #define RCC_PLLI2S_SUPPORT |
1345 | |
| 1346 | 1346 | /******************** Bit definition for RCC_CR register ********************/ |
|
| 1347 | /******************** Bit definition for RCC_CR register ********************/ |
1347 | #define RCC_CR_HSION_Pos (0U) |
| 1348 | #define RCC_CR_HSION_Pos (0U) |
1348 | #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ |
| 1349 | #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */ |
1349 | #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ |
| 1350 | #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */ |
1350 | #define RCC_CR_HSIRDY_Pos (1U) |
| 1351 | #define RCC_CR_HSIRDY_Pos (1U) |
1351 | #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ |
| 1352 | #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */ |
1352 | #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ |
| 1353 | #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ |
1353 | #define RCC_CR_HSITRIM_Pos (3U) |
| 1354 | #define RCC_CR_HSITRIM_Pos (3U) |
1354 | #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ |
| 1355 | #define RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */ |
1355 | #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ |
| 1356 | #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */ |
1356 | #define RCC_CR_HSICAL_Pos (8U) |
| 1357 | #define RCC_CR_HSICAL_Pos (8U) |
1357 | #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ |
| 1358 | #define RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */ |
1358 | #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ |
| 1359 | #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */ |
1359 | #define RCC_CR_HSEON_Pos (16U) |
| 1360 | #define RCC_CR_HSEON_Pos (16U) |
1360 | #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ |
| 1361 | #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */ |
1361 | #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ |
| 1362 | #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */ |
1362 | #define RCC_CR_HSERDY_Pos (17U) |
| 1363 | #define RCC_CR_HSERDY_Pos (17U) |
1363 | #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ |
| 1364 | #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */ |
1364 | #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ |
| 1365 | #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */ |
1365 | #define RCC_CR_HSEBYP_Pos (18U) |
| 1366 | #define RCC_CR_HSEBYP_Pos (18U) |
1366 | #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ |
| 1367 | #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */ |
1367 | #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ |
| 1368 | #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */ |
1368 | #define RCC_CR_CSSON_Pos (19U) |
| 1369 | #define RCC_CR_CSSON_Pos (19U) |
1369 | #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ |
| 1370 | #define RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos) /*!< 0x00080000 */ |
1370 | #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ |
| 1371 | #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */ |
1371 | #define RCC_CR_PLLON_Pos (24U) |
| 1372 | #define RCC_CR_PLLON_Pos (24U) |
1372 | #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ |
| 1373 | #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */ |
1373 | #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ |
| 1374 | #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */ |
1374 | #define RCC_CR_PLLRDY_Pos (25U) |
| 1375 | #define RCC_CR_PLLRDY_Pos (25U) |
1375 | #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ |
| 1376 | #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ |
1376 | #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ |
| 1377 | #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */ |
1377 | |
| 1378 | 1378 | #define RCC_CR_PLL2ON_Pos (26U) |
|
| 1379 | #define RCC_CR_PLL2ON_Pos (26U) |
1379 | #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ |
| 1380 | #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */ |
1380 | #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ |
| 1381 | #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< PLL2 enable */ |
1381 | #define RCC_CR_PLL2RDY_Pos (27U) |
| 1382 | #define RCC_CR_PLL2RDY_Pos (27U) |
1382 | #define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ |
| 1383 | #define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */ |
1383 | #define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ |
| 1384 | #define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< PLL2 clock ready flag */ |
1384 | |
| 1385 | 1385 | #define RCC_CR_PLL3ON_Pos (28U) |
|
| 1386 | #define RCC_CR_PLL3ON_Pos (28U) |
1386 | #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ |
| 1387 | #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */ |
1387 | #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ |
| 1388 | #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< PLL3 enable */ |
1388 | #define RCC_CR_PLL3RDY_Pos (29U) |
| 1389 | #define RCC_CR_PLL3RDY_Pos (29U) |
1389 | #define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */ |
| 1390 | #define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */ |
1390 | #define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ |
| 1391 | #define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< PLL3 clock ready flag */ |
1391 | |
| 1392 | 1392 | /******************* Bit definition for RCC_CFGR register *******************/ |
|
| 1393 | /******************* Bit definition for RCC_CFGR register *******************/ |
1393 | /*!< SW configuration */ |
| 1394 | /*!< SW configuration */ |
1394 | #define RCC_CFGR_SW_Pos (0U) |
| 1395 | #define RCC_CFGR_SW_Pos (0U) |
1395 | #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ |
| 1396 | #define RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos) /*!< 0x00000003 */ |
1396 | #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ |
| 1397 | #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */ |
1397 | #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ |
| 1398 | #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */ |
1398 | #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ |
| 1399 | #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */ |
1399 | |
| 1400 | 1400 | #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ |
|
| 1401 | #define RCC_CFGR_SW_HSI 0x00000000U /*!< HSI selected as system clock */ |
1401 | #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ |
| 1402 | #define RCC_CFGR_SW_HSE 0x00000001U /*!< HSE selected as system clock */ |
1402 | #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ |
| 1403 | #define RCC_CFGR_SW_PLL 0x00000002U /*!< PLL selected as system clock */ |
1403 | |
| 1404 | 1404 | /*!< SWS configuration */ |
|
| 1405 | /*!< SWS configuration */ |
1405 | #define RCC_CFGR_SWS_Pos (2U) |
| 1406 | #define RCC_CFGR_SWS_Pos (2U) |
1406 | #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ |
| 1407 | #define RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */ |
1407 | #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ |
| 1408 | #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */ |
1408 | #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ |
| 1409 | #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */ |
1409 | #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ |
| 1410 | #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */ |
1410 | |
| 1411 | 1411 | #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ |
|
| 1412 | #define RCC_CFGR_SWS_HSI 0x00000000U /*!< HSI oscillator used as system clock */ |
1412 | #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ |
| 1413 | #define RCC_CFGR_SWS_HSE 0x00000004U /*!< HSE oscillator used as system clock */ |
1413 | #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ |
| 1414 | #define RCC_CFGR_SWS_PLL 0x00000008U /*!< PLL used as system clock */ |
1414 | |
| 1415 | 1415 | /*!< HPRE configuration */ |
|
| 1416 | /*!< HPRE configuration */ |
1416 | #define RCC_CFGR_HPRE_Pos (4U) |
| 1417 | #define RCC_CFGR_HPRE_Pos (4U) |
1417 | #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ |
| 1418 | #define RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */ |
1418 | #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ |
| 1419 | #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */ |
1419 | #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ |
| 1420 | #define RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */ |
1420 | #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ |
| 1421 | #define RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */ |
1421 | #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ |
| 1422 | #define RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */ |
1422 | #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ |
| 1423 | #define RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */ |
1423 | |
| 1424 | 1424 | #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ |
|
| 1425 | #define RCC_CFGR_HPRE_DIV1 0x00000000U /*!< SYSCLK not divided */ |
1425 | #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ |
| 1426 | #define RCC_CFGR_HPRE_DIV2 0x00000080U /*!< SYSCLK divided by 2 */ |
1426 | #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ |
| 1427 | #define RCC_CFGR_HPRE_DIV4 0x00000090U /*!< SYSCLK divided by 4 */ |
1427 | #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ |
| 1428 | #define RCC_CFGR_HPRE_DIV8 0x000000A0U /*!< SYSCLK divided by 8 */ |
1428 | #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ |
| 1429 | #define RCC_CFGR_HPRE_DIV16 0x000000B0U /*!< SYSCLK divided by 16 */ |
1429 | #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ |
| 1430 | #define RCC_CFGR_HPRE_DIV64 0x000000C0U /*!< SYSCLK divided by 64 */ |
1430 | #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ |
| 1431 | #define RCC_CFGR_HPRE_DIV128 0x000000D0U /*!< SYSCLK divided by 128 */ |
1431 | #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ |
| 1432 | #define RCC_CFGR_HPRE_DIV256 0x000000E0U /*!< SYSCLK divided by 256 */ |
1432 | #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ |
| 1433 | #define RCC_CFGR_HPRE_DIV512 0x000000F0U /*!< SYSCLK divided by 512 */ |
1433 | |
| 1434 | 1434 | /*!< PPRE1 configuration */ |
|
| 1435 | /*!< PPRE1 configuration */ |
1435 | #define RCC_CFGR_PPRE1_Pos (8U) |
| 1436 | #define RCC_CFGR_PPRE1_Pos (8U) |
1436 | #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ |
| 1437 | #define RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000700 */ |
1437 | #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ |
| 1438 | #define RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk /*!< PRE1[2:0] bits (APB1 prescaler) */ |
1438 | #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ |
| 1439 | #define RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000100 */ |
1439 | #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ |
| 1440 | #define RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000200 */ |
1440 | #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ |
| 1441 | #define RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos) /*!< 0x00000400 */ |
1441 | |
| 1442 | 1442 | #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ |
|
| 1443 | #define RCC_CFGR_PPRE1_DIV1 0x00000000U /*!< HCLK not divided */ |
1443 | #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ |
| 1444 | #define RCC_CFGR_PPRE1_DIV2 0x00000400U /*!< HCLK divided by 2 */ |
1444 | #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ |
| 1445 | #define RCC_CFGR_PPRE1_DIV4 0x00000500U /*!< HCLK divided by 4 */ |
1445 | #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ |
| 1446 | #define RCC_CFGR_PPRE1_DIV8 0x00000600U /*!< HCLK divided by 8 */ |
1446 | #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ |
| 1447 | #define RCC_CFGR_PPRE1_DIV16 0x00000700U /*!< HCLK divided by 16 */ |
1447 | |
| 1448 | 1448 | /*!< PPRE2 configuration */ |
|
| 1449 | /*!< PPRE2 configuration */ |
1449 | #define RCC_CFGR_PPRE2_Pos (11U) |
| 1450 | #define RCC_CFGR_PPRE2_Pos (11U) |
1450 | #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ |
| 1451 | #define RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00003800 */ |
1451 | #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ |
| 1452 | #define RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk /*!< PRE2[2:0] bits (APB2 prescaler) */ |
1452 | #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ |
| 1453 | #define RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00000800 */ |
1453 | #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ |
| 1454 | #define RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00001000 */ |
1454 | #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ |
| 1455 | #define RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos) /*!< 0x00002000 */ |
1455 | |
| 1456 | 1456 | #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ |
|
| 1457 | #define RCC_CFGR_PPRE2_DIV1 0x00000000U /*!< HCLK not divided */ |
1457 | #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ |
| 1458 | #define RCC_CFGR_PPRE2_DIV2 0x00002000U /*!< HCLK divided by 2 */ |
1458 | #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ |
| 1459 | #define RCC_CFGR_PPRE2_DIV4 0x00002800U /*!< HCLK divided by 4 */ |
1459 | #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ |
| 1460 | #define RCC_CFGR_PPRE2_DIV8 0x00003000U /*!< HCLK divided by 8 */ |
1460 | #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ |
| 1461 | #define RCC_CFGR_PPRE2_DIV16 0x00003800U /*!< HCLK divided by 16 */ |
1461 | |
| 1462 | 1462 | /*!< ADCPPRE configuration */ |
|
| 1463 | /*!< ADCPPRE configuration */ |
1463 | #define RCC_CFGR_ADCPRE_Pos (14U) |
| 1464 | #define RCC_CFGR_ADCPRE_Pos (14U) |
1464 | #define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ |
| 1465 | #define RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x0000C000 */ |
1465 | #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ |
| 1466 | #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE[1:0] bits (ADC prescaler) */ |
1466 | #define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ |
| 1467 | #define RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */ |
1467 | #define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ |
| 1468 | #define RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos) /*!< 0x00008000 */ |
1468 | |
| 1469 | 1469 | #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ |
|
| 1470 | #define RCC_CFGR_ADCPRE_DIV2 0x00000000U /*!< PCLK2 divided by 2 */ |
1470 | #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ |
| 1471 | #define RCC_CFGR_ADCPRE_DIV4 0x00004000U /*!< PCLK2 divided by 4 */ |
1471 | #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ |
| 1472 | #define RCC_CFGR_ADCPRE_DIV6 0x00008000U /*!< PCLK2 divided by 6 */ |
1472 | #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ |
| 1473 | #define RCC_CFGR_ADCPRE_DIV8 0x0000C000U /*!< PCLK2 divided by 8 */ |
1473 | |
| 1474 | 1474 | #define RCC_CFGR_PLLSRC_Pos (16U) |
|
| 1475 | #define RCC_CFGR_PLLSRC_Pos (16U) |
1475 | #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ |
| 1476 | #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ |
1476 | #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ |
| 1477 | #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ |
1477 | |
| 1478 | 1478 | #define RCC_CFGR_PLLXTPRE_Pos (17U) |
|
| 1479 | #define RCC_CFGR_PLLXTPRE_Pos (17U) |
1479 | #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ |
| 1480 | #define RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */ |
1480 | #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ |
| 1481 | #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */ |
1481 | |
| 1482 | 1482 | /*!< PLLMUL configuration */ |
|
| 1483 | /*!< PLLMUL configuration */ |
1483 | #define RCC_CFGR_PLLMULL_Pos (18U) |
| 1484 | #define RCC_CFGR_PLLMULL_Pos (18U) |
1484 | #define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ |
| 1485 | #define RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos) /*!< 0x003C0000 */ |
1485 | #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
| 1486 | #define RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */ |
1486 | #define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ |
| 1487 | #define RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00040000 */ |
1487 | #define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ |
| 1488 | #define RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00080000 */ |
1488 | #define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ |
| 1489 | #define RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00100000 */ |
1489 | #define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ |
| 1490 | #define RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos) /*!< 0x00200000 */ |
1490 | |
| 1491 | 1491 | #define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */ |
|
| 1492 | #define RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U /*!< PREDIV1 clock not divided for PLL entry */ |
1492 | #define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */ |
| 1493 | #define RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U /*!< PREDIV1 clock divided by 2 for PLL entry */ |
1493 | |
| 1494 | 1494 | #define RCC_CFGR_PLLMULL4_Pos (19U) |
|
| 1495 | #define RCC_CFGR_PLLMULL4_Pos (19U) |
1495 | #define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ |
| 1496 | #define RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos) /*!< 0x00080000 */ |
1496 | #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock * 4 */ |
| 1497 | #define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk /*!< PLL input clock * 4 */ |
1497 | #define RCC_CFGR_PLLMULL5_Pos (18U) |
| 1498 | #define RCC_CFGR_PLLMULL5_Pos (18U) |
1498 | #define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ |
| 1499 | #define RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos) /*!< 0x000C0000 */ |
1499 | #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock * 5 */ |
| 1500 | #define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk /*!< PLL input clock * 5 */ |
1500 | #define RCC_CFGR_PLLMULL6_Pos (20U) |
| 1501 | #define RCC_CFGR_PLLMULL6_Pos (20U) |
1501 | #define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ |
| 1502 | #define RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos) /*!< 0x00100000 */ |
1502 | #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock * 6 */ |
| 1503 | #define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk /*!< PLL input clock * 6 */ |
1503 | #define RCC_CFGR_PLLMULL7_Pos (18U) |
| 1504 | #define RCC_CFGR_PLLMULL7_Pos (18U) |
1504 | #define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ |
| 1505 | #define RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos) /*!< 0x00140000 */ |
1505 | #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock * 7 */ |
| 1506 | #define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk /*!< PLL input clock * 7 */ |
1506 | #define RCC_CFGR_PLLMULL8_Pos (19U) |
| 1507 | #define RCC_CFGR_PLLMULL8_Pos (19U) |
1507 | #define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ |
| 1508 | #define RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos) /*!< 0x00180000 */ |
1508 | #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock * 8 */ |
| 1509 | #define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk /*!< PLL input clock * 8 */ |
1509 | #define RCC_CFGR_PLLMULL9_Pos (18U) |
| 1510 | #define RCC_CFGR_PLLMULL9_Pos (18U) |
1510 | #define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ |
| 1511 | #define RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos) /*!< 0x001C0000 */ |
1511 | #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock * 9 */ |
| 1512 | #define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk /*!< PLL input clock * 9 */ |
1512 | #define RCC_CFGR_PLLMULL6_5 0x00340000U /*!< PLL input clock * 6.5 */ |
| 1513 | #define RCC_CFGR_PLLMULL6_5 0x00340000U /*!< PLL input clock * 6.5 */ |
1513 | |
| 1514 | 1514 | #define RCC_CFGR_OTGFSPRE_Pos (22U) |
|
| 1515 | #define RCC_CFGR_OTGFSPRE_Pos (22U) |
1515 | #define RCC_CFGR_OTGFSPRE_Msk (0x1UL << RCC_CFGR_OTGFSPRE_Pos) /*!< 0x00400000 */ |
| 1516 | #define RCC_CFGR_OTGFSPRE_Msk (0x1UL << RCC_CFGR_OTGFSPRE_Pos) /*!< 0x00400000 */ |
1516 | #define RCC_CFGR_OTGFSPRE RCC_CFGR_OTGFSPRE_Msk /*!< USB OTG FS prescaler */ |
| 1517 | #define RCC_CFGR_OTGFSPRE RCC_CFGR_OTGFSPRE_Msk /*!< USB OTG FS prescaler */ |
1517 | |
| 1518 | 1518 | /*!< MCO configuration */ |
|
| 1519 | /*!< MCO configuration */ |
1519 | #define RCC_CFGR_MCO_Pos (24U) |
| 1520 | #define RCC_CFGR_MCO_Pos (24U) |
1520 | #define RCC_CFGR_MCO_Msk (0xFUL << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */ |
| 1521 | #define RCC_CFGR_MCO_Msk (0xFUL << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */ |
1521 | #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ |
| 1522 | #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */ |
1522 | #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ |
| 1523 | #define RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */ |
1523 | #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ |
| 1524 | #define RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */ |
1524 | #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ |
| 1525 | #define RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */ |
1525 | #define RCC_CFGR_MCO_3 (0x8UL << RCC_CFGR_MCO_Pos) /*!< 0x08000000 */ |
| 1526 | #define RCC_CFGR_MCO_3 (0x8UL << RCC_CFGR_MCO_Pos) /*!< 0x08000000 */ |
1526 | |
| 1527 | 1527 | #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ |
|
| 1528 | #define RCC_CFGR_MCO_NOCLOCK 0x00000000U /*!< No clock */ |
1528 | #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ |
| 1529 | #define RCC_CFGR_MCO_SYSCLK 0x04000000U /*!< System clock selected as MCO source */ |
1529 | #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ |
| 1530 | #define RCC_CFGR_MCO_HSI 0x05000000U /*!< HSI clock selected as MCO source */ |
1530 | #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ |
| 1531 | #define RCC_CFGR_MCO_HSE 0x06000000U /*!< HSE clock selected as MCO source */ |
1531 | #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ |
| 1532 | #define RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U /*!< PLL clock divided by 2 selected as MCO source */ |
1532 | #define RCC_CFGR_MCO_PLL2CLK 0x08000000U /*!< PLL2 clock selected as MCO source*/ |
| 1533 | #define RCC_CFGR_MCO_PLL2CLK 0x08000000U /*!< PLL2 clock selected as MCO source*/ |
1533 | #define RCC_CFGR_MCO_PLL3CLK_DIV2 0x09000000U /*!< PLL3 clock divided by 2 selected as MCO source*/ |
| 1534 | #define RCC_CFGR_MCO_PLL3CLK_DIV2 0x09000000U /*!< PLL3 clock divided by 2 selected as MCO source*/ |
1534 | #define RCC_CFGR_MCO_EXT_HSE 0x0A000000U /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ |
| 1535 | #define RCC_CFGR_MCO_EXT_HSE 0x0A000000U /*!< XT1 external 3-25 MHz oscillator clock selected as MCO source */ |
1535 | #define RCC_CFGR_MCO_PLL3CLK 0x0B000000U /*!< PLL3 clock selected as MCO source */ |
| 1536 | #define RCC_CFGR_MCO_PLL3CLK 0x0B000000U /*!< PLL3 clock selected as MCO source */ |
1536 | |
| 1537 | 1537 | /* Reference defines */ |
|
| 1538 | /* Reference defines */ |
1538 | #define RCC_CFGR_MCOSEL RCC_CFGR_MCO |
| 1539 | #define RCC_CFGR_MCOSEL RCC_CFGR_MCO |
1539 | #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 |
| 1540 | #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0 |
1540 | #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 |
| 1541 | #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1 |
1541 | #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 |
| 1542 | #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2 |
1542 | #define RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3 |
| 1543 | #define RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3 |
1543 | #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK |
| 1544 | #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK |
1544 | #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK |
| 1545 | #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK |
1545 | #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI |
| 1546 | #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI |
1546 | #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE |
| 1547 | #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE |
1547 | #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 |
| 1548 | #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2 |
1548 | #define RCC_CFGR_MCOSEL_PLL2 RCC_CFGR_MCO_PLL2CLK |
| 1549 | #define RCC_CFGR_MCOSEL_PLL2 RCC_CFGR_MCO_PLL2CLK |
1549 | #define RCC_CFGR_MCOSEL_PLL3_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 |
| 1550 | #define RCC_CFGR_MCOSEL_PLL3_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2 |
1550 | #define RCC_CFGR_MCOSEL_EXT_HSE RCC_CFGR_MCO_EXT_HSE |
| 1551 | #define RCC_CFGR_MCOSEL_EXT_HSE RCC_CFGR_MCO_EXT_HSE |
1551 | #define RCC_CFGR_MCOSEL_PLL3CLK RCC_CFGR_MCO_PLL3CLK |
| 1552 | #define RCC_CFGR_MCOSEL_PLL3CLK RCC_CFGR_MCO_PLL3CLK |
1552 | |
| 1553 | 1553 | /*!<****************** Bit definition for RCC_CIR register ********************/ |
|
| 1554 | /*!<****************** Bit definition for RCC_CIR register ********************/ |
1554 | #define RCC_CIR_LSIRDYF_Pos (0U) |
| 1555 | #define RCC_CIR_LSIRDYF_Pos (0U) |
1555 | #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ |
| 1556 | #define RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */ |
1556 | #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ |
| 1557 | #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */ |
1557 | #define RCC_CIR_LSERDYF_Pos (1U) |
| 1558 | #define RCC_CIR_LSERDYF_Pos (1U) |
1558 | #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ |
| 1559 | #define RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */ |
1559 | #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ |
| 1560 | #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */ |
1560 | #define RCC_CIR_HSIRDYF_Pos (2U) |
| 1561 | #define RCC_CIR_HSIRDYF_Pos (2U) |
1561 | #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ |
| 1562 | #define RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */ |
1562 | #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ |
| 1563 | #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */ |
1563 | #define RCC_CIR_HSERDYF_Pos (3U) |
| 1564 | #define RCC_CIR_HSERDYF_Pos (3U) |
1564 | #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ |
| 1565 | #define RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */ |
1565 | #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ |
| 1566 | #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */ |
1566 | #define RCC_CIR_PLLRDYF_Pos (4U) |
| 1567 | #define RCC_CIR_PLLRDYF_Pos (4U) |
1567 | #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ |
| 1568 | #define RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */ |
1568 | #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ |
| 1569 | #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */ |
1569 | #define RCC_CIR_CSSF_Pos (7U) |
| 1570 | #define RCC_CIR_CSSF_Pos (7U) |
1570 | #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ |
| 1571 | #define RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */ |
1571 | #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ |
| 1572 | #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */ |
1572 | #define RCC_CIR_LSIRDYIE_Pos (8U) |
| 1573 | #define RCC_CIR_LSIRDYIE_Pos (8U) |
1573 | #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ |
| 1574 | #define RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */ |
1574 | #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ |
| 1575 | #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */ |
1575 | #define RCC_CIR_LSERDYIE_Pos (9U) |
| 1576 | #define RCC_CIR_LSERDYIE_Pos (9U) |
1576 | #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ |
| 1577 | #define RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */ |
1577 | #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ |
| 1578 | #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */ |
1578 | #define RCC_CIR_HSIRDYIE_Pos (10U) |
| 1579 | #define RCC_CIR_HSIRDYIE_Pos (10U) |
1579 | #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ |
| 1580 | #define RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */ |
1580 | #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ |
| 1581 | #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */ |
1581 | #define RCC_CIR_HSERDYIE_Pos (11U) |
| 1582 | #define RCC_CIR_HSERDYIE_Pos (11U) |
1582 | #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ |
| 1583 | #define RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */ |
1583 | #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ |
| 1584 | #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */ |
1584 | #define RCC_CIR_PLLRDYIE_Pos (12U) |
| 1585 | #define RCC_CIR_PLLRDYIE_Pos (12U) |
1585 | #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ |
| 1586 | #define RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */ |
1586 | #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ |
| 1587 | #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */ |
1587 | #define RCC_CIR_LSIRDYC_Pos (16U) |
| 1588 | #define RCC_CIR_LSIRDYC_Pos (16U) |
1588 | #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ |
| 1589 | #define RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */ |
1589 | #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ |
| 1590 | #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */ |
1590 | #define RCC_CIR_LSERDYC_Pos (17U) |
| 1591 | #define RCC_CIR_LSERDYC_Pos (17U) |
1591 | #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ |
| 1592 | #define RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */ |
1592 | #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ |
| 1593 | #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */ |
1593 | #define RCC_CIR_HSIRDYC_Pos (18U) |
| 1594 | #define RCC_CIR_HSIRDYC_Pos (18U) |
1594 | #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ |
| 1595 | #define RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */ |
1595 | #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ |
| 1596 | #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */ |
1596 | #define RCC_CIR_HSERDYC_Pos (19U) |
| 1597 | #define RCC_CIR_HSERDYC_Pos (19U) |
1597 | #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ |
| 1598 | #define RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */ |
1598 | #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ |
| 1599 | #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */ |
1599 | #define RCC_CIR_PLLRDYC_Pos (20U) |
| 1600 | #define RCC_CIR_PLLRDYC_Pos (20U) |
1600 | #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ |
| 1601 | #define RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */ |
1601 | #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ |
| 1602 | #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */ |
1602 | #define RCC_CIR_CSSC_Pos (23U) |
| 1603 | #define RCC_CIR_CSSC_Pos (23U) |
1603 | #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ |
| 1604 | #define RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */ |
1604 | #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ |
| 1605 | #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */ |
1605 | |
| 1606 | 1606 | #define RCC_CIR_PLL2RDYF_Pos (5U) |
|
| 1607 | #define RCC_CIR_PLL2RDYF_Pos (5U) |
1607 | #define RCC_CIR_PLL2RDYF_Msk (0x1UL << RCC_CIR_PLL2RDYF_Pos) /*!< 0x00000020 */ |
| 1608 | #define RCC_CIR_PLL2RDYF_Msk (0x1UL << RCC_CIR_PLL2RDYF_Pos) /*!< 0x00000020 */ |
1608 | #define RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF_Msk /*!< PLL2 Ready Interrupt flag */ |
| 1609 | #define RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF_Msk /*!< PLL2 Ready Interrupt flag */ |
1609 | #define RCC_CIR_PLL3RDYF_Pos (6U) |
| 1610 | #define RCC_CIR_PLL3RDYF_Pos (6U) |
1610 | #define RCC_CIR_PLL3RDYF_Msk (0x1UL << RCC_CIR_PLL3RDYF_Pos) /*!< 0x00000040 */ |
| 1611 | #define RCC_CIR_PLL3RDYF_Msk (0x1UL << RCC_CIR_PLL3RDYF_Pos) /*!< 0x00000040 */ |
1611 | #define RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF_Msk /*!< PLL3 Ready Interrupt flag */ |
| 1612 | #define RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF_Msk /*!< PLL3 Ready Interrupt flag */ |
1612 | #define RCC_CIR_PLL2RDYIE_Pos (13U) |
| 1613 | #define RCC_CIR_PLL2RDYIE_Pos (13U) |
1613 | #define RCC_CIR_PLL2RDYIE_Msk (0x1UL << RCC_CIR_PLL2RDYIE_Pos) /*!< 0x00002000 */ |
| 1614 | #define RCC_CIR_PLL2RDYIE_Msk (0x1UL << RCC_CIR_PLL2RDYIE_Pos) /*!< 0x00002000 */ |
1614 | #define RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE_Msk /*!< PLL2 Ready Interrupt Enable */ |
| 1615 | #define RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE_Msk /*!< PLL2 Ready Interrupt Enable */ |
1615 | #define RCC_CIR_PLL3RDYIE_Pos (14U) |
| 1616 | #define RCC_CIR_PLL3RDYIE_Pos (14U) |
1616 | #define RCC_CIR_PLL3RDYIE_Msk (0x1UL << RCC_CIR_PLL3RDYIE_Pos) /*!< 0x00004000 */ |
| 1617 | #define RCC_CIR_PLL3RDYIE_Msk (0x1UL << RCC_CIR_PLL3RDYIE_Pos) /*!< 0x00004000 */ |
1617 | #define RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE_Msk /*!< PLL3 Ready Interrupt Enable */ |
| 1618 | #define RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE_Msk /*!< PLL3 Ready Interrupt Enable */ |
1618 | #define RCC_CIR_PLL2RDYC_Pos (21U) |
| 1619 | #define RCC_CIR_PLL2RDYC_Pos (21U) |
1619 | #define RCC_CIR_PLL2RDYC_Msk (0x1UL << RCC_CIR_PLL2RDYC_Pos) /*!< 0x00200000 */ |
| 1620 | #define RCC_CIR_PLL2RDYC_Msk (0x1UL << RCC_CIR_PLL2RDYC_Pos) /*!< 0x00200000 */ |
1620 | #define RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC_Msk /*!< PLL2 Ready Interrupt Clear */ |
| 1621 | #define RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC_Msk /*!< PLL2 Ready Interrupt Clear */ |
1621 | #define RCC_CIR_PLL3RDYC_Pos (22U) |
| 1622 | #define RCC_CIR_PLL3RDYC_Pos (22U) |
1622 | #define RCC_CIR_PLL3RDYC_Msk (0x1UL << RCC_CIR_PLL3RDYC_Pos) /*!< 0x00400000 */ |
| 1623 | #define RCC_CIR_PLL3RDYC_Msk (0x1UL << RCC_CIR_PLL3RDYC_Pos) /*!< 0x00400000 */ |
1623 | #define RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC_Msk /*!< PLL3 Ready Interrupt Clear */ |
| 1624 | #define RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC_Msk /*!< PLL3 Ready Interrupt Clear */ |
1624 | |
| 1625 | 1625 | /***************** Bit definition for RCC_APB2RSTR register *****************/ |
|
| 1626 | /***************** Bit definition for RCC_APB2RSTR register *****************/ |
1626 | #define RCC_APB2RSTR_AFIORST_Pos (0U) |
| 1627 | #define RCC_APB2RSTR_AFIORST_Pos (0U) |
1627 | #define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ |
| 1628 | #define RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos) /*!< 0x00000001 */ |
1628 | #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ |
| 1629 | #define RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk /*!< Alternate Function I/O reset */ |
1629 | #define RCC_APB2RSTR_IOPARST_Pos (2U) |
| 1630 | #define RCC_APB2RSTR_IOPARST_Pos (2U) |
1630 | #define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ |
| 1631 | #define RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos) /*!< 0x00000004 */ |
1631 | #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ |
| 1632 | #define RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk /*!< I/O port A reset */ |
1632 | #define RCC_APB2RSTR_IOPBRST_Pos (3U) |
| 1633 | #define RCC_APB2RSTR_IOPBRST_Pos (3U) |
1633 | #define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ |
| 1634 | #define RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos) /*!< 0x00000008 */ |
1634 | #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ |
| 1635 | #define RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk /*!< I/O port B reset */ |
1635 | #define RCC_APB2RSTR_IOPCRST_Pos (4U) |
| 1636 | #define RCC_APB2RSTR_IOPCRST_Pos (4U) |
1636 | #define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ |
| 1637 | #define RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos) /*!< 0x00000010 */ |
1637 | #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ |
| 1638 | #define RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk /*!< I/O port C reset */ |
1638 | #define RCC_APB2RSTR_IOPDRST_Pos (5U) |
| 1639 | #define RCC_APB2RSTR_IOPDRST_Pos (5U) |
1639 | #define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ |
| 1640 | #define RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos) /*!< 0x00000020 */ |
1640 | #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ |
| 1641 | #define RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk /*!< I/O port D reset */ |
1641 | #define RCC_APB2RSTR_ADC1RST_Pos (9U) |
| 1642 | #define RCC_APB2RSTR_ADC1RST_Pos (9U) |
1642 | #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ |
| 1643 | #define RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos) /*!< 0x00000200 */ |
1643 | #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ |
| 1644 | #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk /*!< ADC 1 interface reset */ |
1644 | |
| 1645 | 1645 | #define RCC_APB2RSTR_ADC2RST_Pos (10U) |
|
| 1646 | #define RCC_APB2RSTR_ADC2RST_Pos (10U) |
1646 | #define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ |
| 1647 | #define RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos) /*!< 0x00000400 */ |
1647 | #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ |
| 1648 | #define RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk /*!< ADC 2 interface reset */ |
1648 | |
| 1649 | 1649 | #define RCC_APB2RSTR_TIM1RST_Pos (11U) |
|
| 1650 | #define RCC_APB2RSTR_TIM1RST_Pos (11U) |
1650 | #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ |
| 1651 | #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */ |
1651 | #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ |
| 1652 | #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 Timer reset */ |
1652 | #define RCC_APB2RSTR_SPI1RST_Pos (12U) |
| 1653 | #define RCC_APB2RSTR_SPI1RST_Pos (12U) |
1653 | #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ |
| 1654 | #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */ |
1654 | #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ |
| 1655 | #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI 1 reset */ |
1655 | #define RCC_APB2RSTR_USART1RST_Pos (14U) |
| 1656 | #define RCC_APB2RSTR_USART1RST_Pos (14U) |
1656 | #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ |
| 1657 | #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */ |
1657 | #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ |
| 1658 | #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */ |
1658 | |
| 1659 | 1659 | ||
| 1660 | 1660 | #define RCC_APB2RSTR_IOPERST_Pos (6U) |
|
| 1661 | #define RCC_APB2RSTR_IOPERST_Pos (6U) |
1661 | #define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ |
| 1662 | #define RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos) /*!< 0x00000040 */ |
1662 | #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ |
| 1663 | #define RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk /*!< I/O port E reset */ |
1663 | |
| 1664 | 1664 | ||
| 1665 | 1665 | ||
| 1666 | 1666 | ||
| 1667 | 1667 | /***************** Bit definition for RCC_APB1RSTR register *****************/ |
|
| 1668 | /***************** Bit definition for RCC_APB1RSTR register *****************/ |
1668 | #define RCC_APB1RSTR_TIM2RST_Pos (0U) |
| 1669 | #define RCC_APB1RSTR_TIM2RST_Pos (0U) |
1669 | #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ |
| 1670 | #define RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */ |
1670 | #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ |
| 1671 | #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */ |
1671 | #define RCC_APB1RSTR_TIM3RST_Pos (1U) |
| 1672 | #define RCC_APB1RSTR_TIM3RST_Pos (1U) |
1672 | #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ |
| 1673 | #define RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */ |
1673 | #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ |
| 1674 | #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */ |
1674 | #define RCC_APB1RSTR_WWDGRST_Pos (11U) |
| 1675 | #define RCC_APB1RSTR_WWDGRST_Pos (11U) |
1675 | #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ |
| 1676 | #define RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */ |
1676 | #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ |
| 1677 | #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */ |
1677 | #define RCC_APB1RSTR_USART2RST_Pos (17U) |
| 1678 | #define RCC_APB1RSTR_USART2RST_Pos (17U) |
1678 | #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ |
| 1679 | #define RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos) /*!< 0x00020000 */ |
1679 | #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ |
| 1680 | #define RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk /*!< USART 2 reset */ |
1680 | #define RCC_APB1RSTR_I2C1RST_Pos (21U) |
| 1681 | #define RCC_APB1RSTR_I2C1RST_Pos (21U) |
1681 | #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ |
| 1682 | #define RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */ |
1682 | #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ |
| 1683 | #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */ |
1683 | |
| 1684 | 1684 | #define RCC_APB1RSTR_CAN1RST_Pos (25U) |
|
| 1685 | #define RCC_APB1RSTR_CAN1RST_Pos (25U) |
1685 | #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ |
| 1686 | #define RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos) /*!< 0x02000000 */ |
1686 | #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ |
| 1687 | #define RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk /*!< CAN1 reset */ |
1687 | |
| 1688 | 1688 | #define RCC_APB1RSTR_BKPRST_Pos (27U) |
|
| 1689 | #define RCC_APB1RSTR_BKPRST_Pos (27U) |
1689 | #define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ |
| 1690 | #define RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos) /*!< 0x08000000 */ |
1690 | #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ |
| 1691 | #define RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk /*!< Backup interface reset */ |
1691 | #define RCC_APB1RSTR_PWRRST_Pos (28U) |
| 1692 | #define RCC_APB1RSTR_PWRRST_Pos (28U) |
1692 | #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ |
| 1693 | #define RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */ |
1693 | #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ |
| 1694 | #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< Power interface reset */ |
1694 | |
| 1695 | 1695 | #define RCC_APB1RSTR_TIM4RST_Pos (2U) |
|
| 1696 | #define RCC_APB1RSTR_TIM4RST_Pos (2U) |
1696 | #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ |
| 1697 | #define RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos) /*!< 0x00000004 */ |
1697 | #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ |
| 1698 | #define RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk /*!< Timer 4 reset */ |
1698 | #define RCC_APB1RSTR_SPI2RST_Pos (14U) |
| 1699 | #define RCC_APB1RSTR_SPI2RST_Pos (14U) |
1699 | #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ |
| 1700 | #define RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos) /*!< 0x00004000 */ |
1700 | #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ |
| 1701 | #define RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk /*!< SPI 2 reset */ |
1701 | #define RCC_APB1RSTR_USART3RST_Pos (18U) |
| 1702 | #define RCC_APB1RSTR_USART3RST_Pos (18U) |
1702 | #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ |
| 1703 | #define RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos) /*!< 0x00040000 */ |
1703 | #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ |
| 1704 | #define RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk /*!< USART 3 reset */ |
1704 | #define RCC_APB1RSTR_I2C2RST_Pos (22U) |
| 1705 | #define RCC_APB1RSTR_I2C2RST_Pos (22U) |
1705 | #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ |
| 1706 | #define RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos) /*!< 0x00400000 */ |
1706 | #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ |
| 1707 | #define RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk /*!< I2C 2 reset */ |
1707 | |
| 1708 | 1708 | ||
| 1709 | 1709 | #define RCC_APB1RSTR_TIM5RST_Pos (3U) |
|
| 1710 | #define RCC_APB1RSTR_TIM5RST_Pos (3U) |
1710 | #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ |
| 1711 | #define RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos) /*!< 0x00000008 */ |
1711 | #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */ |
| 1712 | #define RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk /*!< Timer 5 reset */ |
1712 | #define RCC_APB1RSTR_TIM6RST_Pos (4U) |
| 1713 | #define RCC_APB1RSTR_TIM6RST_Pos (4U) |
1713 | #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ |
| 1714 | #define RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos) /*!< 0x00000010 */ |
1714 | #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ |
| 1715 | #define RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk /*!< Timer 6 reset */ |
1715 | #define RCC_APB1RSTR_TIM7RST_Pos (5U) |
| 1716 | #define RCC_APB1RSTR_TIM7RST_Pos (5U) |
1716 | #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ |
| 1717 | #define RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos) /*!< 0x00000020 */ |
1717 | #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ |
| 1718 | #define RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk /*!< Timer 7 reset */ |
1718 | #define RCC_APB1RSTR_SPI3RST_Pos (15U) |
| 1719 | #define RCC_APB1RSTR_SPI3RST_Pos (15U) |
1719 | #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ |
| 1720 | #define RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos) /*!< 0x00008000 */ |
1720 | #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */ |
| 1721 | #define RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk /*!< SPI 3 reset */ |
1721 | #define RCC_APB1RSTR_UART4RST_Pos (19U) |
| 1722 | #define RCC_APB1RSTR_UART4RST_Pos (19U) |
1722 | #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ |
| 1723 | #define RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos) /*!< 0x00080000 */ |
1723 | #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */ |
| 1724 | #define RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk /*!< UART 4 reset */ |
1724 | #define RCC_APB1RSTR_UART5RST_Pos (20U) |
| 1725 | #define RCC_APB1RSTR_UART5RST_Pos (20U) |
1725 | #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ |
| 1726 | #define RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos) /*!< 0x00100000 */ |
1726 | #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */ |
| 1727 | #define RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk /*!< UART 5 reset */ |
1727 | |
| 1728 | 1728 | ||
| 1729 | 1729 | ||
| 1730 | 1730 | #define RCC_APB1RSTR_CAN2RST_Pos (26U) |
|
| 1731 | #define RCC_APB1RSTR_CAN2RST_Pos (26U) |
1731 | #define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */ |
| 1732 | #define RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos) /*!< 0x04000000 */ |
1732 | #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk /*!< CAN2 reset */ |
| 1733 | #define RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk /*!< CAN2 reset */ |
1733 | |
| 1734 | 1734 | #define RCC_APB1RSTR_DACRST_Pos (29U) |
|
| 1735 | #define RCC_APB1RSTR_DACRST_Pos (29U) |
1735 | #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ |
| 1736 | #define RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos) /*!< 0x20000000 */ |
1736 | #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ |
| 1737 | #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk /*!< DAC interface reset */ |
1737 | |
| 1738 | 1738 | /****************** Bit definition for RCC_AHBENR register ******************/ |
|
| 1739 | /****************** Bit definition for RCC_AHBENR register ******************/ |
1739 | #define RCC_AHBENR_DMA1EN_Pos (0U) |
| 1740 | #define RCC_AHBENR_DMA1EN_Pos (0U) |
1740 | #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ |
| 1741 | #define RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos) /*!< 0x00000001 */ |
1741 | #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ |
| 1742 | #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk /*!< DMA1 clock enable */ |
1742 | #define RCC_AHBENR_SRAMEN_Pos (2U) |
| 1743 | #define RCC_AHBENR_SRAMEN_Pos (2U) |
1743 | #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ |
| 1744 | #define RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */ |
1744 | #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ |
| 1745 | #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */ |
1745 | #define RCC_AHBENR_FLITFEN_Pos (4U) |
| 1746 | #define RCC_AHBENR_FLITFEN_Pos (4U) |
1746 | #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ |
| 1747 | #define RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */ |
1747 | #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ |
| 1748 | #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */ |
1748 | #define RCC_AHBENR_CRCEN_Pos (6U) |
| 1749 | #define RCC_AHBENR_CRCEN_Pos (6U) |
1749 | #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ |
| 1750 | #define RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */ |
1750 | #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ |
| 1751 | #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */ |
1751 | |
| 1752 | 1752 | #define RCC_AHBENR_DMA2EN_Pos (1U) |
|
| 1753 | #define RCC_AHBENR_DMA2EN_Pos (1U) |
1753 | #define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */ |
| 1754 | #define RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos) /*!< 0x00000002 */ |
1754 | #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ |
| 1755 | #define RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk /*!< DMA2 clock enable */ |
1755 | |
| 1756 | 1756 | ||
| 1757 | 1757 | #define RCC_AHBENR_OTGFSEN_Pos (12U) |
|
| 1758 | #define RCC_AHBENR_OTGFSEN_Pos (12U) |
1758 | #define RCC_AHBENR_OTGFSEN_Msk (0x1UL << RCC_AHBENR_OTGFSEN_Pos) /*!< 0x00001000 */ |
| 1759 | #define RCC_AHBENR_OTGFSEN_Msk (0x1UL << RCC_AHBENR_OTGFSEN_Pos) /*!< 0x00001000 */ |
1759 | #define RCC_AHBENR_OTGFSEN RCC_AHBENR_OTGFSEN_Msk /*!< USB OTG FS clock enable */ |
| 1760 | #define RCC_AHBENR_OTGFSEN RCC_AHBENR_OTGFSEN_Msk /*!< USB OTG FS clock enable */ |
1760 | #define RCC_AHBENR_ETHMACEN_Pos (14U) |
| 1761 | #define RCC_AHBENR_ETHMACEN_Pos (14U) |
1761 | #define RCC_AHBENR_ETHMACEN_Msk (0x1UL << RCC_AHBENR_ETHMACEN_Pos) /*!< 0x00004000 */ |
| 1762 | #define RCC_AHBENR_ETHMACEN_Msk (0x1UL << RCC_AHBENR_ETHMACEN_Pos) /*!< 0x00004000 */ |
1762 | #define RCC_AHBENR_ETHMACEN RCC_AHBENR_ETHMACEN_Msk /*!< ETHERNET MAC clock enable */ |
| 1763 | #define RCC_AHBENR_ETHMACEN RCC_AHBENR_ETHMACEN_Msk /*!< ETHERNET MAC clock enable */ |
1763 | #define RCC_AHBENR_ETHMACTXEN_Pos (15U) |
| 1764 | #define RCC_AHBENR_ETHMACTXEN_Pos (15U) |
1764 | #define RCC_AHBENR_ETHMACTXEN_Msk (0x1UL << RCC_AHBENR_ETHMACTXEN_Pos) /*!< 0x00008000 */ |
| 1765 | #define RCC_AHBENR_ETHMACTXEN_Msk (0x1UL << RCC_AHBENR_ETHMACTXEN_Pos) /*!< 0x00008000 */ |
1765 | #define RCC_AHBENR_ETHMACTXEN RCC_AHBENR_ETHMACTXEN_Msk /*!< ETHERNET MAC Tx clock enable */ |
| 1766 | #define RCC_AHBENR_ETHMACTXEN RCC_AHBENR_ETHMACTXEN_Msk /*!< ETHERNET MAC Tx clock enable */ |
1766 | #define RCC_AHBENR_ETHMACRXEN_Pos (16U) |
| 1767 | #define RCC_AHBENR_ETHMACRXEN_Pos (16U) |
1767 | #define RCC_AHBENR_ETHMACRXEN_Msk (0x1UL << RCC_AHBENR_ETHMACRXEN_Pos) /*!< 0x00010000 */ |
| 1768 | #define RCC_AHBENR_ETHMACRXEN_Msk (0x1UL << RCC_AHBENR_ETHMACRXEN_Pos) /*!< 0x00010000 */ |
1768 | #define RCC_AHBENR_ETHMACRXEN RCC_AHBENR_ETHMACRXEN_Msk /*!< ETHERNET MAC Rx clock enable */ |
| 1769 | #define RCC_AHBENR_ETHMACRXEN RCC_AHBENR_ETHMACRXEN_Msk /*!< ETHERNET MAC Rx clock enable */ |
1769 | |
| 1770 | 1770 | /****************** Bit definition for RCC_APB2ENR register *****************/ |
|
| 1771 | /****************** Bit definition for RCC_APB2ENR register *****************/ |
1771 | #define RCC_APB2ENR_AFIOEN_Pos (0U) |
| 1772 | #define RCC_APB2ENR_AFIOEN_Pos (0U) |
1772 | #define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ |
| 1773 | #define RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos) /*!< 0x00000001 */ |
1773 | #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ |
| 1774 | #define RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk /*!< Alternate Function I/O clock enable */ |
1774 | #define RCC_APB2ENR_IOPAEN_Pos (2U) |
| 1775 | #define RCC_APB2ENR_IOPAEN_Pos (2U) |
1775 | #define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ |
| 1776 | #define RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos) /*!< 0x00000004 */ |
1776 | #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ |
| 1777 | #define RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk /*!< I/O port A clock enable */ |
1777 | #define RCC_APB2ENR_IOPBEN_Pos (3U) |
| 1778 | #define RCC_APB2ENR_IOPBEN_Pos (3U) |
1778 | #define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ |
| 1779 | #define RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos) /*!< 0x00000008 */ |
1779 | #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ |
| 1780 | #define RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk /*!< I/O port B clock enable */ |
1780 | #define RCC_APB2ENR_IOPCEN_Pos (4U) |
| 1781 | #define RCC_APB2ENR_IOPCEN_Pos (4U) |
1781 | #define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ |
| 1782 | #define RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos) /*!< 0x00000010 */ |
1782 | #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ |
| 1783 | #define RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk /*!< I/O port C clock enable */ |
1783 | #define RCC_APB2ENR_IOPDEN_Pos (5U) |
| 1784 | #define RCC_APB2ENR_IOPDEN_Pos (5U) |
1784 | #define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ |
| 1785 | #define RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos) /*!< 0x00000020 */ |
1785 | #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ |
| 1786 | #define RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk /*!< I/O port D clock enable */ |
1786 | #define RCC_APB2ENR_ADC1EN_Pos (9U) |
| 1787 | #define RCC_APB2ENR_ADC1EN_Pos (9U) |
1787 | #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ |
| 1788 | #define RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos) /*!< 0x00000200 */ |
1788 | #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ |
| 1789 | #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk /*!< ADC 1 interface clock enable */ |
1789 | |
| 1790 | 1790 | #define RCC_APB2ENR_ADC2EN_Pos (10U) |
|
| 1791 | #define RCC_APB2ENR_ADC2EN_Pos (10U) |
1791 | #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ |
| 1792 | #define RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos) /*!< 0x00000400 */ |
1792 | #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ |
| 1793 | #define RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk /*!< ADC 2 interface clock enable */ |
1793 | |
| 1794 | 1794 | #define RCC_APB2ENR_TIM1EN_Pos (11U) |
|
| 1795 | #define RCC_APB2ENR_TIM1EN_Pos (11U) |
1795 | #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ |
| 1796 | #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */ |
1796 | #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ |
| 1797 | #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 Timer clock enable */ |
1797 | #define RCC_APB2ENR_SPI1EN_Pos (12U) |
| 1798 | #define RCC_APB2ENR_SPI1EN_Pos (12U) |
1798 | #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ |
| 1799 | #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */ |
1799 | #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ |
| 1800 | #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI 1 clock enable */ |
1800 | #define RCC_APB2ENR_USART1EN_Pos (14U) |
| 1801 | #define RCC_APB2ENR_USART1EN_Pos (14U) |
1801 | #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ |
| 1802 | #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */ |
1802 | #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ |
| 1803 | #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */ |
1803 | |
| 1804 | 1804 | ||
| 1805 | 1805 | #define RCC_APB2ENR_IOPEEN_Pos (6U) |
|
| 1806 | #define RCC_APB2ENR_IOPEEN_Pos (6U) |
1806 | #define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ |
| 1807 | #define RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos) /*!< 0x00000040 */ |
1807 | #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ |
| 1808 | #define RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk /*!< I/O port E clock enable */ |
1808 | |
| 1809 | 1809 | ||
| 1810 | 1810 | ||
| 1811 | 1811 | ||
| 1812 | 1812 | /***************** Bit definition for RCC_APB1ENR register ******************/ |
|
| 1813 | /***************** Bit definition for RCC_APB1ENR register ******************/ |
1813 | #define RCC_APB1ENR_TIM2EN_Pos (0U) |
| 1814 | #define RCC_APB1ENR_TIM2EN_Pos (0U) |
1814 | #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ |
| 1815 | #define RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */ |
1815 | #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ |
| 1816 | #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enabled*/ |
1816 | #define RCC_APB1ENR_TIM3EN_Pos (1U) |
| 1817 | #define RCC_APB1ENR_TIM3EN_Pos (1U) |
1817 | #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ |
| 1818 | #define RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */ |
1818 | #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ |
| 1819 | #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */ |
1819 | #define RCC_APB1ENR_WWDGEN_Pos (11U) |
| 1820 | #define RCC_APB1ENR_WWDGEN_Pos (11U) |
1820 | #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ |
| 1821 | #define RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */ |
1821 | #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ |
| 1822 | #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */ |
1822 | #define RCC_APB1ENR_USART2EN_Pos (17U) |
| 1823 | #define RCC_APB1ENR_USART2EN_Pos (17U) |
1823 | #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ |
| 1824 | #define RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos) /*!< 0x00020000 */ |
1824 | #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ |
| 1825 | #define RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk /*!< USART 2 clock enable */ |
1825 | #define RCC_APB1ENR_I2C1EN_Pos (21U) |
| 1826 | #define RCC_APB1ENR_I2C1EN_Pos (21U) |
1826 | #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ |
| 1827 | #define RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */ |
1827 | #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ |
| 1828 | #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C 1 clock enable */ |
1828 | |
| 1829 | 1829 | #define RCC_APB1ENR_CAN1EN_Pos (25U) |
|
| 1830 | #define RCC_APB1ENR_CAN1EN_Pos (25U) |
1830 | #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ |
| 1831 | #define RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos) /*!< 0x02000000 */ |
1831 | #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ |
| 1832 | #define RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk /*!< CAN1 clock enable */ |
1832 | |
| 1833 | 1833 | #define RCC_APB1ENR_BKPEN_Pos (27U) |
|
| 1834 | #define RCC_APB1ENR_BKPEN_Pos (27U) |
1834 | #define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ |
| 1835 | #define RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos) /*!< 0x08000000 */ |
1835 | #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ |
| 1836 | #define RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk /*!< Backup interface clock enable */ |
1836 | #define RCC_APB1ENR_PWREN_Pos (28U) |
| 1837 | #define RCC_APB1ENR_PWREN_Pos (28U) |
1837 | #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ |
| 1838 | #define RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */ |
1838 | #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ |
| 1839 | #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< Power interface clock enable */ |
1839 | |
| 1840 | 1840 | #define RCC_APB1ENR_TIM4EN_Pos (2U) |
|
| 1841 | #define RCC_APB1ENR_TIM4EN_Pos (2U) |
1841 | #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ |
| 1842 | #define RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos) /*!< 0x00000004 */ |
1842 | #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ |
| 1843 | #define RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk /*!< Timer 4 clock enable */ |
1843 | #define RCC_APB1ENR_SPI2EN_Pos (14U) |
| 1844 | #define RCC_APB1ENR_SPI2EN_Pos (14U) |
1844 | #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ |
| 1845 | #define RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos) /*!< 0x00004000 */ |
1845 | #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ |
| 1846 | #define RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk /*!< SPI 2 clock enable */ |
1846 | #define RCC_APB1ENR_USART3EN_Pos (18U) |
| 1847 | #define RCC_APB1ENR_USART3EN_Pos (18U) |
1847 | #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ |
| 1848 | #define RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos) /*!< 0x00040000 */ |
1848 | #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ |
| 1849 | #define RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk /*!< USART 3 clock enable */ |
1849 | #define RCC_APB1ENR_I2C2EN_Pos (22U) |
| 1850 | #define RCC_APB1ENR_I2C2EN_Pos (22U) |
1850 | #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ |
| 1851 | #define RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos) /*!< 0x00400000 */ |
1851 | #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ |
| 1852 | #define RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk /*!< I2C 2 clock enable */ |
1852 | |
| 1853 | 1853 | ||
| 1854 | 1854 | #define RCC_APB1ENR_TIM5EN_Pos (3U) |
|
| 1855 | #define RCC_APB1ENR_TIM5EN_Pos (3U) |
1855 | #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ |
| 1856 | #define RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos) /*!< 0x00000008 */ |
1856 | #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */ |
| 1857 | #define RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk /*!< Timer 5 clock enable */ |
1857 | #define RCC_APB1ENR_TIM6EN_Pos (4U) |
| 1858 | #define RCC_APB1ENR_TIM6EN_Pos (4U) |
1858 | #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ |
| 1859 | #define RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos) /*!< 0x00000010 */ |
1859 | #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ |
| 1860 | #define RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk /*!< Timer 6 clock enable */ |
1860 | #define RCC_APB1ENR_TIM7EN_Pos (5U) |
| 1861 | #define RCC_APB1ENR_TIM7EN_Pos (5U) |
1861 | #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ |
| 1862 | #define RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos) /*!< 0x00000020 */ |
1862 | #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ |
| 1863 | #define RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk /*!< Timer 7 clock enable */ |
1863 | #define RCC_APB1ENR_SPI3EN_Pos (15U) |
| 1864 | #define RCC_APB1ENR_SPI3EN_Pos (15U) |
1864 | #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ |
| 1865 | #define RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos) /*!< 0x00008000 */ |
1865 | #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */ |
| 1866 | #define RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk /*!< SPI 3 clock enable */ |
1866 | #define RCC_APB1ENR_UART4EN_Pos (19U) |
| 1867 | #define RCC_APB1ENR_UART4EN_Pos (19U) |
1867 | #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ |
| 1868 | #define RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos) /*!< 0x00080000 */ |
1868 | #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */ |
| 1869 | #define RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk /*!< UART 4 clock enable */ |
1869 | #define RCC_APB1ENR_UART5EN_Pos (20U) |
| 1870 | #define RCC_APB1ENR_UART5EN_Pos (20U) |
1870 | #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ |
| 1871 | #define RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos) /*!< 0x00100000 */ |
1871 | #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */ |
| 1872 | #define RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk /*!< UART 5 clock enable */ |
1872 | |
| 1873 | 1873 | ||
| 1874 | 1874 | ||
| 1875 | 1875 | #define RCC_APB1ENR_CAN2EN_Pos (26U) |
|
| 1876 | #define RCC_APB1ENR_CAN2EN_Pos (26U) |
1876 | #define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */ |
| 1877 | #define RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos) /*!< 0x04000000 */ |
1877 | #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk /*!< CAN2 clock enable */ |
| 1878 | #define RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk /*!< CAN2 clock enable */ |
1878 | |
| 1879 | 1879 | #define RCC_APB1ENR_DACEN_Pos (29U) |
|
| 1880 | #define RCC_APB1ENR_DACEN_Pos (29U) |
1880 | #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ |
| 1881 | #define RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos) /*!< 0x20000000 */ |
1881 | #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ |
| 1882 | #define RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk /*!< DAC interface clock enable */ |
1882 | |
| 1883 | 1883 | /******************* Bit definition for RCC_BDCR register *******************/ |
|
| 1884 | /******************* Bit definition for RCC_BDCR register *******************/ |
1884 | #define RCC_BDCR_LSEON_Pos (0U) |
| 1885 | #define RCC_BDCR_LSEON_Pos (0U) |
1885 | #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ |
| 1886 | #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */ |
1886 | #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ |
| 1887 | #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */ |
1887 | #define RCC_BDCR_LSERDY_Pos (1U) |
| 1888 | #define RCC_BDCR_LSERDY_Pos (1U) |
1888 | #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ |
| 1889 | #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */ |
1889 | #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ |
| 1890 | #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */ |
1890 | #define RCC_BDCR_LSEBYP_Pos (2U) |
| 1891 | #define RCC_BDCR_LSEBYP_Pos (2U) |
1891 | #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ |
| 1892 | #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */ |
1892 | #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ |
| 1893 | #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */ |
1893 | |
| 1894 | 1894 | #define RCC_BDCR_RTCSEL_Pos (8U) |
|
| 1895 | #define RCC_BDCR_RTCSEL_Pos (8U) |
1895 | #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ |
| 1896 | #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */ |
1896 | #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
| 1897 | #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */ |
1897 | #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ |
| 1898 | #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */ |
1898 | #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ |
| 1899 | #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */ |
1899 | |
| 1900 | 1900 | /*!< RTC configuration */ |
|
| 1901 | /*!< RTC congiguration */ |
1901 | #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ |
| 1902 | #define RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U /*!< No clock */ |
1902 | #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ |
| 1903 | #define RCC_BDCR_RTCSEL_LSE 0x00000100U /*!< LSE oscillator clock used as RTC clock */ |
1903 | #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ |
| 1904 | #define RCC_BDCR_RTCSEL_LSI 0x00000200U /*!< LSI oscillator clock used as RTC clock */ |
1904 | #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
| 1905 | #define RCC_BDCR_RTCSEL_HSE 0x00000300U /*!< HSE oscillator clock divided by 128 used as RTC clock */ |
1905 | |
| 1906 | 1906 | #define RCC_BDCR_RTCEN_Pos (15U) |
|
| 1907 | #define RCC_BDCR_RTCEN_Pos (15U) |
1907 | #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ |
| 1908 | #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */ |
1908 | #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ |
| 1909 | #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */ |
1909 | #define RCC_BDCR_BDRST_Pos (16U) |
| 1910 | #define RCC_BDCR_BDRST_Pos (16U) |
1910 | #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ |
| 1911 | #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */ |
1911 | #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ |
| 1912 | #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */ |
1912 | |
| 1913 | 1913 | /******************* Bit definition for RCC_CSR register ********************/ |
|
| 1914 | /******************* Bit definition for RCC_CSR register ********************/ |
1914 | #define RCC_CSR_LSION_Pos (0U) |
| 1915 | #define RCC_CSR_LSION_Pos (0U) |
1915 | #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ |
| 1916 | #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */ |
1916 | #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ |
| 1917 | #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */ |
1917 | #define RCC_CSR_LSIRDY_Pos (1U) |
| 1918 | #define RCC_CSR_LSIRDY_Pos (1U) |
1918 | #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ |
| 1919 | #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */ |
1919 | #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ |
| 1920 | #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */ |
1920 | #define RCC_CSR_RMVF_Pos (24U) |
| 1921 | #define RCC_CSR_RMVF_Pos (24U) |
1921 | #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ |
| 1922 | #define RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */ |
1922 | #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ |
| 1923 | #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */ |
1923 | #define RCC_CSR_PINRSTF_Pos (26U) |
| 1924 | #define RCC_CSR_PINRSTF_Pos (26U) |
1924 | #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ |
| 1925 | #define RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */ |
1925 | #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ |
| 1926 | #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */ |
1926 | #define RCC_CSR_PORRSTF_Pos (27U) |
| 1927 | #define RCC_CSR_PORRSTF_Pos (27U) |
1927 | #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ |
| 1928 | #define RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */ |
1928 | #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ |
| 1929 | #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */ |
1929 | #define RCC_CSR_SFTRSTF_Pos (28U) |
| 1930 | #define RCC_CSR_SFTRSTF_Pos (28U) |
1930 | #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ |
| 1931 | #define RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */ |
1931 | #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ |
| 1932 | #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */ |
1932 | #define RCC_CSR_IWDGRSTF_Pos (29U) |
| 1933 | #define RCC_CSR_IWDGRSTF_Pos (29U) |
1933 | #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ |
| 1934 | #define RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */ |
1934 | #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ |
| 1935 | #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */ |
1935 | #define RCC_CSR_WWDGRSTF_Pos (30U) |
| 1936 | #define RCC_CSR_WWDGRSTF_Pos (30U) |
1936 | #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ |
| 1937 | #define RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */ |
1937 | #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ |
| 1938 | #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */ |
1938 | #define RCC_CSR_LPWRRSTF_Pos (31U) |
| 1939 | #define RCC_CSR_LPWRRSTF_Pos (31U) |
1939 | #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ |
| 1940 | #define RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */ |
1940 | #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ |
| 1941 | #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */ |
1941 | |
| 1942 | 1942 | /******************* Bit definition for RCC_AHBRSTR register ****************/ |
|
| 1943 | /******************* Bit definition for RCC_AHBRSTR register ****************/ |
1943 | #define RCC_AHBRSTR_OTGFSRST_Pos (12U) |
| 1944 | #define RCC_AHBRSTR_OTGFSRST_Pos (12U) |
1944 | #define RCC_AHBRSTR_OTGFSRST_Msk (0x1UL << RCC_AHBRSTR_OTGFSRST_Pos) /*!< 0x00001000 */ |
| 1945 | #define RCC_AHBRSTR_OTGFSRST_Msk (0x1UL << RCC_AHBRSTR_OTGFSRST_Pos) /*!< 0x00001000 */ |
1945 | #define RCC_AHBRSTR_OTGFSRST RCC_AHBRSTR_OTGFSRST_Msk /*!< USB OTG FS reset */ |
| 1946 | #define RCC_AHBRSTR_OTGFSRST RCC_AHBRSTR_OTGFSRST_Msk /*!< USB OTG FS reset */ |
1946 | #define RCC_AHBRSTR_ETHMACRST_Pos (14U) |
| 1947 | #define RCC_AHBRSTR_ETHMACRST_Pos (14U) |
1947 | #define RCC_AHBRSTR_ETHMACRST_Msk (0x1UL << RCC_AHBRSTR_ETHMACRST_Pos) /*!< 0x00004000 */ |
| 1948 | #define RCC_AHBRSTR_ETHMACRST_Msk (0x1UL << RCC_AHBRSTR_ETHMACRST_Pos) /*!< 0x00004000 */ |
1948 | #define RCC_AHBRSTR_ETHMACRST RCC_AHBRSTR_ETHMACRST_Msk /*!< ETHERNET MAC reset */ |
| 1949 | #define RCC_AHBRSTR_ETHMACRST RCC_AHBRSTR_ETHMACRST_Msk /*!< ETHERNET MAC reset */ |
1949 | |
| 1950 | 1950 | /******************* Bit definition for RCC_CFGR2 register ******************/ |
|
| 1951 | /******************* Bit definition for RCC_CFGR2 register ******************/ |
1951 | /*!< PREDIV1 configuration */ |
| 1952 | /*!< PREDIV1 configuration */ |
1952 | #define RCC_CFGR2_PREDIV1_Pos (0U) |
| 1953 | #define RCC_CFGR2_PREDIV1_Pos (0U) |
1953 | #define RCC_CFGR2_PREDIV1_Msk (0xFUL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */ |
| 1954 | #define RCC_CFGR2_PREDIV1_Msk (0xFUL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x0000000F */ |
1954 | #define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */ |
| 1955 | #define RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk /*!< PREDIV1[3:0] bits */ |
1955 | #define RCC_CFGR2_PREDIV1_0 (0x1UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */ |
| 1956 | #define RCC_CFGR2_PREDIV1_0 (0x1UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000001 */ |
1956 | #define RCC_CFGR2_PREDIV1_1 (0x2UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */ |
| 1957 | #define RCC_CFGR2_PREDIV1_1 (0x2UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000002 */ |
1957 | #define RCC_CFGR2_PREDIV1_2 (0x4UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */ |
| 1958 | #define RCC_CFGR2_PREDIV1_2 (0x4UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000004 */ |
1958 | #define RCC_CFGR2_PREDIV1_3 (0x8UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */ |
| 1959 | #define RCC_CFGR2_PREDIV1_3 (0x8UL << RCC_CFGR2_PREDIV1_Pos) /*!< 0x00000008 */ |
1959 | |
| 1960 | 1960 | #define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */ |
|
| 1961 | #define RCC_CFGR2_PREDIV1_DIV1 0x00000000U /*!< PREDIV1 input clock not divided */ |
1961 | #define RCC_CFGR2_PREDIV1_DIV2_Pos (0U) |
| 1962 | #define RCC_CFGR2_PREDIV1_DIV2_Pos (0U) |
1962 | #define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */ |
| 1963 | #define RCC_CFGR2_PREDIV1_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV2_Pos) /*!< 0x00000001 */ |
1963 | #define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */ |
| 1964 | #define RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk /*!< PREDIV1 input clock divided by 2 */ |
1964 | #define RCC_CFGR2_PREDIV1_DIV3_Pos (1U) |
| 1965 | #define RCC_CFGR2_PREDIV1_DIV3_Pos (1U) |
1965 | #define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */ |
| 1966 | #define RCC_CFGR2_PREDIV1_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV3_Pos) /*!< 0x00000002 */ |
1966 | #define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */ |
| 1967 | #define RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk /*!< PREDIV1 input clock divided by 3 */ |
1967 | #define RCC_CFGR2_PREDIV1_DIV4_Pos (0U) |
| 1968 | #define RCC_CFGR2_PREDIV1_DIV4_Pos (0U) |
1968 | #define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */ |
| 1969 | #define RCC_CFGR2_PREDIV1_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV4_Pos) /*!< 0x00000003 */ |
1969 | #define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */ |
| 1970 | #define RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk /*!< PREDIV1 input clock divided by 4 */ |
1970 | #define RCC_CFGR2_PREDIV1_DIV5_Pos (2U) |
| 1971 | #define RCC_CFGR2_PREDIV1_DIV5_Pos (2U) |
1971 | #define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */ |
| 1972 | #define RCC_CFGR2_PREDIV1_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV5_Pos) /*!< 0x00000004 */ |
1972 | #define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */ |
| 1973 | #define RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk /*!< PREDIV1 input clock divided by 5 */ |
1973 | #define RCC_CFGR2_PREDIV1_DIV6_Pos (0U) |
| 1974 | #define RCC_CFGR2_PREDIV1_DIV6_Pos (0U) |
1974 | #define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */ |
| 1975 | #define RCC_CFGR2_PREDIV1_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV6_Pos) /*!< 0x00000005 */ |
1975 | #define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */ |
| 1976 | #define RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk /*!< PREDIV1 input clock divided by 6 */ |
1976 | #define RCC_CFGR2_PREDIV1_DIV7_Pos (1U) |
| 1977 | #define RCC_CFGR2_PREDIV1_DIV7_Pos (1U) |
1977 | #define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */ |
| 1978 | #define RCC_CFGR2_PREDIV1_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV7_Pos) /*!< 0x00000006 */ |
1978 | #define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */ |
| 1979 | #define RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk /*!< PREDIV1 input clock divided by 7 */ |
1979 | #define RCC_CFGR2_PREDIV1_DIV8_Pos (0U) |
| 1980 | #define RCC_CFGR2_PREDIV1_DIV8_Pos (0U) |
1980 | #define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */ |
| 1981 | #define RCC_CFGR2_PREDIV1_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV8_Pos) /*!< 0x00000007 */ |
1981 | #define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */ |
| 1982 | #define RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk /*!< PREDIV1 input clock divided by 8 */ |
1982 | #define RCC_CFGR2_PREDIV1_DIV9_Pos (3U) |
| 1983 | #define RCC_CFGR2_PREDIV1_DIV9_Pos (3U) |
1983 | #define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */ |
| 1984 | #define RCC_CFGR2_PREDIV1_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV9_Pos) /*!< 0x00000008 */ |
1984 | #define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */ |
| 1985 | #define RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk /*!< PREDIV1 input clock divided by 9 */ |
1985 | #define RCC_CFGR2_PREDIV1_DIV10_Pos (0U) |
| 1986 | #define RCC_CFGR2_PREDIV1_DIV10_Pos (0U) |
1986 | #define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */ |
| 1987 | #define RCC_CFGR2_PREDIV1_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV1_DIV10_Pos) /*!< 0x00000009 */ |
1987 | #define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */ |
| 1988 | #define RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk /*!< PREDIV1 input clock divided by 10 */ |
1988 | #define RCC_CFGR2_PREDIV1_DIV11_Pos (1U) |
| 1989 | #define RCC_CFGR2_PREDIV1_DIV11_Pos (1U) |
1989 | #define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */ |
| 1990 | #define RCC_CFGR2_PREDIV1_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV11_Pos) /*!< 0x0000000A */ |
1990 | #define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */ |
| 1991 | #define RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk /*!< PREDIV1 input clock divided by 11 */ |
1991 | #define RCC_CFGR2_PREDIV1_DIV12_Pos (0U) |
| 1992 | #define RCC_CFGR2_PREDIV1_DIV12_Pos (0U) |
1992 | #define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */ |
| 1993 | #define RCC_CFGR2_PREDIV1_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV1_DIV12_Pos) /*!< 0x0000000B */ |
1993 | #define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */ |
| 1994 | #define RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk /*!< PREDIV1 input clock divided by 12 */ |
1994 | #define RCC_CFGR2_PREDIV1_DIV13_Pos (2U) |
| 1995 | #define RCC_CFGR2_PREDIV1_DIV13_Pos (2U) |
1995 | #define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */ |
| 1996 | #define RCC_CFGR2_PREDIV1_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV13_Pos) /*!< 0x0000000C */ |
1996 | #define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */ |
| 1997 | #define RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk /*!< PREDIV1 input clock divided by 13 */ |
1997 | #define RCC_CFGR2_PREDIV1_DIV14_Pos (0U) |
| 1998 | #define RCC_CFGR2_PREDIV1_DIV14_Pos (0U) |
1998 | #define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */ |
| 1999 | #define RCC_CFGR2_PREDIV1_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV1_DIV14_Pos) /*!< 0x0000000D */ |
1999 | #define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */ |
| 2000 | #define RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk /*!< PREDIV1 input clock divided by 14 */ |
2000 | #define RCC_CFGR2_PREDIV1_DIV15_Pos (1U) |
| 2001 | #define RCC_CFGR2_PREDIV1_DIV15_Pos (1U) |
2001 | #define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */ |
| 2002 | #define RCC_CFGR2_PREDIV1_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV15_Pos) /*!< 0x0000000E */ |
2002 | #define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */ |
| 2003 | #define RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk /*!< PREDIV1 input clock divided by 15 */ |
2003 | #define RCC_CFGR2_PREDIV1_DIV16_Pos (0U) |
| 2004 | #define RCC_CFGR2_PREDIV1_DIV16_Pos (0U) |
2004 | #define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */ |
| 2005 | #define RCC_CFGR2_PREDIV1_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV1_DIV16_Pos) /*!< 0x0000000F */ |
2005 | #define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */ |
| 2006 | #define RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk /*!< PREDIV1 input clock divided by 16 */ |
2006 | |
| 2007 | 2007 | /*!< PREDIV2 configuration */ |
|
| 2008 | /*!< PREDIV2 configuration */ |
2008 | #define RCC_CFGR2_PREDIV2_Pos (4U) |
| 2009 | #define RCC_CFGR2_PREDIV2_Pos (4U) |
2009 | #define RCC_CFGR2_PREDIV2_Msk (0xFUL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x000000F0 */ |
| 2010 | #define RCC_CFGR2_PREDIV2_Msk (0xFUL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x000000F0 */ |
2010 | #define RCC_CFGR2_PREDIV2 RCC_CFGR2_PREDIV2_Msk /*!< PREDIV2[3:0] bits */ |
| 2011 | #define RCC_CFGR2_PREDIV2 RCC_CFGR2_PREDIV2_Msk /*!< PREDIV2[3:0] bits */ |
2011 | #define RCC_CFGR2_PREDIV2_0 (0x1UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000010 */ |
| 2012 | #define RCC_CFGR2_PREDIV2_0 (0x1UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000010 */ |
2012 | #define RCC_CFGR2_PREDIV2_1 (0x2UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000020 */ |
| 2013 | #define RCC_CFGR2_PREDIV2_1 (0x2UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000020 */ |
2013 | #define RCC_CFGR2_PREDIV2_2 (0x4UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000040 */ |
| 2014 | #define RCC_CFGR2_PREDIV2_2 (0x4UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000040 */ |
2014 | #define RCC_CFGR2_PREDIV2_3 (0x8UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000080 */ |
| 2015 | #define RCC_CFGR2_PREDIV2_3 (0x8UL << RCC_CFGR2_PREDIV2_Pos) /*!< 0x00000080 */ |
2015 | |
| 2016 | 2016 | #define RCC_CFGR2_PREDIV2_DIV1 0x00000000U /*!< PREDIV2 input clock not divided */ |
|
| 2017 | #define RCC_CFGR2_PREDIV2_DIV1 0x00000000U /*!< PREDIV2 input clock not divided */ |
2017 | #define RCC_CFGR2_PREDIV2_DIV2_Pos (4U) |
| 2018 | #define RCC_CFGR2_PREDIV2_DIV2_Pos (4U) |
2018 | #define RCC_CFGR2_PREDIV2_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV2_Pos) /*!< 0x00000010 */ |
| 2019 | #define RCC_CFGR2_PREDIV2_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV2_Pos) /*!< 0x00000010 */ |
2019 | #define RCC_CFGR2_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2_Msk /*!< PREDIV2 input clock divided by 2 */ |
| 2020 | #define RCC_CFGR2_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2_Msk /*!< PREDIV2 input clock divided by 2 */ |
2020 | #define RCC_CFGR2_PREDIV2_DIV3_Pos (5U) |
| 2021 | #define RCC_CFGR2_PREDIV2_DIV3_Pos (5U) |
2021 | #define RCC_CFGR2_PREDIV2_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV3_Pos) /*!< 0x00000020 */ |
| 2022 | #define RCC_CFGR2_PREDIV2_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV3_Pos) /*!< 0x00000020 */ |
2022 | #define RCC_CFGR2_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3_Msk /*!< PREDIV2 input clock divided by 3 */ |
| 2023 | #define RCC_CFGR2_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3_Msk /*!< PREDIV2 input clock divided by 3 */ |
2023 | #define RCC_CFGR2_PREDIV2_DIV4_Pos (4U) |
| 2024 | #define RCC_CFGR2_PREDIV2_DIV4_Pos (4U) |
2024 | #define RCC_CFGR2_PREDIV2_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV4_Pos) /*!< 0x00000030 */ |
| 2025 | #define RCC_CFGR2_PREDIV2_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV4_Pos) /*!< 0x00000030 */ |
2025 | #define RCC_CFGR2_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4_Msk /*!< PREDIV2 input clock divided by 4 */ |
| 2026 | #define RCC_CFGR2_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4_Msk /*!< PREDIV2 input clock divided by 4 */ |
2026 | #define RCC_CFGR2_PREDIV2_DIV5_Pos (6U) |
| 2027 | #define RCC_CFGR2_PREDIV2_DIV5_Pos (6U) |
2027 | #define RCC_CFGR2_PREDIV2_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV5_Pos) /*!< 0x00000040 */ |
| 2028 | #define RCC_CFGR2_PREDIV2_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV5_Pos) /*!< 0x00000040 */ |
2028 | #define RCC_CFGR2_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5_Msk /*!< PREDIV2 input clock divided by 5 */ |
| 2029 | #define RCC_CFGR2_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5_Msk /*!< PREDIV2 input clock divided by 5 */ |
2029 | #define RCC_CFGR2_PREDIV2_DIV6_Pos (4U) |
| 2030 | #define RCC_CFGR2_PREDIV2_DIV6_Pos (4U) |
2030 | #define RCC_CFGR2_PREDIV2_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV6_Pos) /*!< 0x00000050 */ |
| 2031 | #define RCC_CFGR2_PREDIV2_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV6_Pos) /*!< 0x00000050 */ |
2031 | #define RCC_CFGR2_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6_Msk /*!< PREDIV2 input clock divided by 6 */ |
| 2032 | #define RCC_CFGR2_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6_Msk /*!< PREDIV2 input clock divided by 6 */ |
2032 | #define RCC_CFGR2_PREDIV2_DIV7_Pos (5U) |
| 2033 | #define RCC_CFGR2_PREDIV2_DIV7_Pos (5U) |
2033 | #define RCC_CFGR2_PREDIV2_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV7_Pos) /*!< 0x00000060 */ |
| 2034 | #define RCC_CFGR2_PREDIV2_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV7_Pos) /*!< 0x00000060 */ |
2034 | #define RCC_CFGR2_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7_Msk /*!< PREDIV2 input clock divided by 7 */ |
| 2035 | #define RCC_CFGR2_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7_Msk /*!< PREDIV2 input clock divided by 7 */ |
2035 | #define RCC_CFGR2_PREDIV2_DIV8_Pos (4U) |
| 2036 | #define RCC_CFGR2_PREDIV2_DIV8_Pos (4U) |
2036 | #define RCC_CFGR2_PREDIV2_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV8_Pos) /*!< 0x00000070 */ |
| 2037 | #define RCC_CFGR2_PREDIV2_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV8_Pos) /*!< 0x00000070 */ |
2037 | #define RCC_CFGR2_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8_Msk /*!< PREDIV2 input clock divided by 8 */ |
| 2038 | #define RCC_CFGR2_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8_Msk /*!< PREDIV2 input clock divided by 8 */ |
2038 | #define RCC_CFGR2_PREDIV2_DIV9_Pos (7U) |
| 2039 | #define RCC_CFGR2_PREDIV2_DIV9_Pos (7U) |
2039 | #define RCC_CFGR2_PREDIV2_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV9_Pos) /*!< 0x00000080 */ |
| 2040 | #define RCC_CFGR2_PREDIV2_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV9_Pos) /*!< 0x00000080 */ |
2040 | #define RCC_CFGR2_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9_Msk /*!< PREDIV2 input clock divided by 9 */ |
| 2041 | #define RCC_CFGR2_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9_Msk /*!< PREDIV2 input clock divided by 9 */ |
2041 | #define RCC_CFGR2_PREDIV2_DIV10_Pos (4U) |
| 2042 | #define RCC_CFGR2_PREDIV2_DIV10_Pos (4U) |
2042 | #define RCC_CFGR2_PREDIV2_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV2_DIV10_Pos) /*!< 0x00000090 */ |
| 2043 | #define RCC_CFGR2_PREDIV2_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV2_DIV10_Pos) /*!< 0x00000090 */ |
2043 | #define RCC_CFGR2_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10_Msk /*!< PREDIV2 input clock divided by 10 */ |
| 2044 | #define RCC_CFGR2_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10_Msk /*!< PREDIV2 input clock divided by 10 */ |
2044 | #define RCC_CFGR2_PREDIV2_DIV11_Pos (5U) |
| 2045 | #define RCC_CFGR2_PREDIV2_DIV11_Pos (5U) |
2045 | #define RCC_CFGR2_PREDIV2_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV11_Pos) /*!< 0x000000A0 */ |
| 2046 | #define RCC_CFGR2_PREDIV2_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV11_Pos) /*!< 0x000000A0 */ |
2046 | #define RCC_CFGR2_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11_Msk /*!< PREDIV2 input clock divided by 11 */ |
| 2047 | #define RCC_CFGR2_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11_Msk /*!< PREDIV2 input clock divided by 11 */ |
2047 | #define RCC_CFGR2_PREDIV2_DIV12_Pos (4U) |
| 2048 | #define RCC_CFGR2_PREDIV2_DIV12_Pos (4U) |
2048 | #define RCC_CFGR2_PREDIV2_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV2_DIV12_Pos) /*!< 0x000000B0 */ |
| 2049 | #define RCC_CFGR2_PREDIV2_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV2_DIV12_Pos) /*!< 0x000000B0 */ |
2049 | #define RCC_CFGR2_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12_Msk /*!< PREDIV2 input clock divided by 12 */ |
| 2050 | #define RCC_CFGR2_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12_Msk /*!< PREDIV2 input clock divided by 12 */ |
2050 | #define RCC_CFGR2_PREDIV2_DIV13_Pos (6U) |
| 2051 | #define RCC_CFGR2_PREDIV2_DIV13_Pos (6U) |
2051 | #define RCC_CFGR2_PREDIV2_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV13_Pos) /*!< 0x000000C0 */ |
| 2052 | #define RCC_CFGR2_PREDIV2_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV13_Pos) /*!< 0x000000C0 */ |
2052 | #define RCC_CFGR2_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13_Msk /*!< PREDIV2 input clock divided by 13 */ |
| 2053 | #define RCC_CFGR2_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13_Msk /*!< PREDIV2 input clock divided by 13 */ |
2053 | #define RCC_CFGR2_PREDIV2_DIV14_Pos (4U) |
| 2054 | #define RCC_CFGR2_PREDIV2_DIV14_Pos (4U) |
2054 | #define RCC_CFGR2_PREDIV2_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV2_DIV14_Pos) /*!< 0x000000D0 */ |
| 2055 | #define RCC_CFGR2_PREDIV2_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV2_DIV14_Pos) /*!< 0x000000D0 */ |
2055 | #define RCC_CFGR2_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14_Msk /*!< PREDIV2 input clock divided by 14 */ |
| 2056 | #define RCC_CFGR2_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14_Msk /*!< PREDIV2 input clock divided by 14 */ |
2056 | #define RCC_CFGR2_PREDIV2_DIV15_Pos (5U) |
| 2057 | #define RCC_CFGR2_PREDIV2_DIV15_Pos (5U) |
2057 | #define RCC_CFGR2_PREDIV2_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV15_Pos) /*!< 0x000000E0 */ |
| 2058 | #define RCC_CFGR2_PREDIV2_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV15_Pos) /*!< 0x000000E0 */ |
2058 | #define RCC_CFGR2_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15_Msk /*!< PREDIV2 input clock divided by 15 */ |
| 2059 | #define RCC_CFGR2_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15_Msk /*!< PREDIV2 input clock divided by 15 */ |
2059 | #define RCC_CFGR2_PREDIV2_DIV16_Pos (4U) |
| 2060 | #define RCC_CFGR2_PREDIV2_DIV16_Pos (4U) |
2060 | #define RCC_CFGR2_PREDIV2_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV2_DIV16_Pos) /*!< 0x000000F0 */ |
| 2061 | #define RCC_CFGR2_PREDIV2_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV2_DIV16_Pos) /*!< 0x000000F0 */ |
2061 | #define RCC_CFGR2_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16_Msk /*!< PREDIV2 input clock divided by 16 */ |
| 2062 | #define RCC_CFGR2_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16_Msk /*!< PREDIV2 input clock divided by 16 */ |
2062 | |
| 2063 | 2063 | /*!< PLL2MUL configuration */ |
|
| 2064 | /*!< PLL2MUL configuration */ |
2064 | #define RCC_CFGR2_PLL2MUL_Pos (8U) |
| 2065 | #define RCC_CFGR2_PLL2MUL_Pos (8U) |
2065 | #define RCC_CFGR2_PLL2MUL_Msk (0xFUL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000F00 */ |
| 2066 | #define RCC_CFGR2_PLL2MUL_Msk (0xFUL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000F00 */ |
2066 | #define RCC_CFGR2_PLL2MUL RCC_CFGR2_PLL2MUL_Msk /*!< PLL2MUL[3:0] bits */ |
| 2067 | #define RCC_CFGR2_PLL2MUL RCC_CFGR2_PLL2MUL_Msk /*!< PLL2MUL[3:0] bits */ |
2067 | #define RCC_CFGR2_PLL2MUL_0 (0x1UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000100 */ |
| 2068 | #define RCC_CFGR2_PLL2MUL_0 (0x1UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000100 */ |
2068 | #define RCC_CFGR2_PLL2MUL_1 (0x2UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000200 */ |
| 2069 | #define RCC_CFGR2_PLL2MUL_1 (0x2UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000200 */ |
2069 | #define RCC_CFGR2_PLL2MUL_2 (0x4UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000400 */ |
| 2070 | #define RCC_CFGR2_PLL2MUL_2 (0x4UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000400 */ |
2070 | #define RCC_CFGR2_PLL2MUL_3 (0x8UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000800 */ |
| 2071 | #define RCC_CFGR2_PLL2MUL_3 (0x8UL << RCC_CFGR2_PLL2MUL_Pos) /*!< 0x00000800 */ |
2071 | |
| 2072 | 2072 | #define RCC_CFGR2_PLL2MUL8_Pos (9U) |
|
| 2073 | #define RCC_CFGR2_PLL2MUL8_Pos (9U) |
2073 | #define RCC_CFGR2_PLL2MUL8_Msk (0x3UL << RCC_CFGR2_PLL2MUL8_Pos) /*!< 0x00000600 */ |
| 2074 | #define RCC_CFGR2_PLL2MUL8_Msk (0x3UL << RCC_CFGR2_PLL2MUL8_Pos) /*!< 0x00000600 */ |
2074 | #define RCC_CFGR2_PLL2MUL8 RCC_CFGR2_PLL2MUL8_Msk /*!< PLL2 input clock * 8 */ |
| 2075 | #define RCC_CFGR2_PLL2MUL8 RCC_CFGR2_PLL2MUL8_Msk /*!< PLL2 input clock * 8 */ |
2075 | #define RCC_CFGR2_PLL2MUL9_Pos (8U) |
| 2076 | #define RCC_CFGR2_PLL2MUL9_Pos (8U) |
2076 | #define RCC_CFGR2_PLL2MUL9_Msk (0x7UL << RCC_CFGR2_PLL2MUL9_Pos) /*!< 0x00000700 */ |
| 2077 | #define RCC_CFGR2_PLL2MUL9_Msk (0x7UL << RCC_CFGR2_PLL2MUL9_Pos) /*!< 0x00000700 */ |
2077 | #define RCC_CFGR2_PLL2MUL9 RCC_CFGR2_PLL2MUL9_Msk /*!< PLL2 input clock * 9 */ |
| 2078 | #define RCC_CFGR2_PLL2MUL9 RCC_CFGR2_PLL2MUL9_Msk /*!< PLL2 input clock * 9 */ |
2078 | #define RCC_CFGR2_PLL2MUL10_Pos (11U) |
| 2079 | #define RCC_CFGR2_PLL2MUL10_Pos (11U) |
2079 | #define RCC_CFGR2_PLL2MUL10_Msk (0x1UL << RCC_CFGR2_PLL2MUL10_Pos) /*!< 0x00000800 */ |
| 2080 | #define RCC_CFGR2_PLL2MUL10_Msk (0x1UL << RCC_CFGR2_PLL2MUL10_Pos) /*!< 0x00000800 */ |
2080 | #define RCC_CFGR2_PLL2MUL10 RCC_CFGR2_PLL2MUL10_Msk /*!< PLL2 input clock * 10 */ |
| 2081 | #define RCC_CFGR2_PLL2MUL10 RCC_CFGR2_PLL2MUL10_Msk /*!< PLL2 input clock * 10 */ |
2081 | #define RCC_CFGR2_PLL2MUL11_Pos (8U) |
| 2082 | #define RCC_CFGR2_PLL2MUL11_Pos (8U) |
2082 | #define RCC_CFGR2_PLL2MUL11_Msk (0x9UL << RCC_CFGR2_PLL2MUL11_Pos) /*!< 0x00000900 */ |
| 2083 | #define RCC_CFGR2_PLL2MUL11_Msk (0x9UL << RCC_CFGR2_PLL2MUL11_Pos) /*!< 0x00000900 */ |
2083 | #define RCC_CFGR2_PLL2MUL11 RCC_CFGR2_PLL2MUL11_Msk /*!< PLL2 input clock * 11 */ |
| 2084 | #define RCC_CFGR2_PLL2MUL11 RCC_CFGR2_PLL2MUL11_Msk /*!< PLL2 input clock * 11 */ |
2084 | #define RCC_CFGR2_PLL2MUL12_Pos (9U) |
| 2085 | #define RCC_CFGR2_PLL2MUL12_Pos (9U) |
2085 | #define RCC_CFGR2_PLL2MUL12_Msk (0x5UL << RCC_CFGR2_PLL2MUL12_Pos) /*!< 0x00000A00 */ |
| 2086 | #define RCC_CFGR2_PLL2MUL12_Msk (0x5UL << RCC_CFGR2_PLL2MUL12_Pos) /*!< 0x00000A00 */ |
2086 | #define RCC_CFGR2_PLL2MUL12 RCC_CFGR2_PLL2MUL12_Msk /*!< PLL2 input clock * 12 */ |
| 2087 | #define RCC_CFGR2_PLL2MUL12 RCC_CFGR2_PLL2MUL12_Msk /*!< PLL2 input clock * 12 */ |
2087 | #define RCC_CFGR2_PLL2MUL13_Pos (8U) |
| 2088 | #define RCC_CFGR2_PLL2MUL13_Pos (8U) |
2088 | #define RCC_CFGR2_PLL2MUL13_Msk (0xBUL << RCC_CFGR2_PLL2MUL13_Pos) /*!< 0x00000B00 */ |
| 2089 | #define RCC_CFGR2_PLL2MUL13_Msk (0xBUL << RCC_CFGR2_PLL2MUL13_Pos) /*!< 0x00000B00 */ |
2089 | #define RCC_CFGR2_PLL2MUL13 RCC_CFGR2_PLL2MUL13_Msk /*!< PLL2 input clock * 13 */ |
| 2090 | #define RCC_CFGR2_PLL2MUL13 RCC_CFGR2_PLL2MUL13_Msk /*!< PLL2 input clock * 13 */ |
2090 | #define RCC_CFGR2_PLL2MUL14_Pos (10U) |
| 2091 | #define RCC_CFGR2_PLL2MUL14_Pos (10U) |
2091 | #define RCC_CFGR2_PLL2MUL14_Msk (0x3UL << RCC_CFGR2_PLL2MUL14_Pos) /*!< 0x00000C00 */ |
| 2092 | #define RCC_CFGR2_PLL2MUL14_Msk (0x3UL << RCC_CFGR2_PLL2MUL14_Pos) /*!< 0x00000C00 */ |
2092 | #define RCC_CFGR2_PLL2MUL14 RCC_CFGR2_PLL2MUL14_Msk /*!< PLL2 input clock * 14 */ |
| 2093 | #define RCC_CFGR2_PLL2MUL14 RCC_CFGR2_PLL2MUL14_Msk /*!< PLL2 input clock * 14 */ |
2093 | #define RCC_CFGR2_PLL2MUL16_Pos (9U) |
| 2094 | #define RCC_CFGR2_PLL2MUL16_Pos (9U) |
2094 | #define RCC_CFGR2_PLL2MUL16_Msk (0x7UL << RCC_CFGR2_PLL2MUL16_Pos) /*!< 0x00000E00 */ |
| 2095 | #define RCC_CFGR2_PLL2MUL16_Msk (0x7UL << RCC_CFGR2_PLL2MUL16_Pos) /*!< 0x00000E00 */ |
2095 | #define RCC_CFGR2_PLL2MUL16 RCC_CFGR2_PLL2MUL16_Msk /*!< PLL2 input clock * 16 */ |
| 2096 | #define RCC_CFGR2_PLL2MUL16 RCC_CFGR2_PLL2MUL16_Msk /*!< PLL2 input clock * 16 */ |
2096 | #define RCC_CFGR2_PLL2MUL20_Pos (8U) |
| 2097 | #define RCC_CFGR2_PLL2MUL20_Pos (8U) |
2097 | #define RCC_CFGR2_PLL2MUL20_Msk (0xFUL << RCC_CFGR2_PLL2MUL20_Pos) /*!< 0x00000F00 */ |
| 2098 | #define RCC_CFGR2_PLL2MUL20_Msk (0xFUL << RCC_CFGR2_PLL2MUL20_Pos) /*!< 0x00000F00 */ |
2098 | #define RCC_CFGR2_PLL2MUL20 RCC_CFGR2_PLL2MUL20_Msk /*!< PLL2 input clock * 20 */ |
| 2099 | #define RCC_CFGR2_PLL2MUL20 RCC_CFGR2_PLL2MUL20_Msk /*!< PLL2 input clock * 20 */ |
2099 | |
| 2100 | 2100 | /*!< PLL3MUL configuration */ |
|
| 2101 | /*!< PLL3MUL configuration */ |
2101 | #define RCC_CFGR2_PLL3MUL_Pos (12U) |
| 2102 | #define RCC_CFGR2_PLL3MUL_Pos (12U) |
2102 | #define RCC_CFGR2_PLL3MUL_Msk (0xFUL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x0000F000 */ |
| 2103 | #define RCC_CFGR2_PLL3MUL_Msk (0xFUL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x0000F000 */ |
2103 | #define RCC_CFGR2_PLL3MUL RCC_CFGR2_PLL3MUL_Msk /*!< PLL3MUL[3:0] bits */ |
| 2104 | #define RCC_CFGR2_PLL3MUL RCC_CFGR2_PLL3MUL_Msk /*!< PLL3MUL[3:0] bits */ |
2104 | #define RCC_CFGR2_PLL3MUL_0 (0x1UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00001000 */ |
| 2105 | #define RCC_CFGR2_PLL3MUL_0 (0x1UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00001000 */ |
2105 | #define RCC_CFGR2_PLL3MUL_1 (0x2UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00002000 */ |
| 2106 | #define RCC_CFGR2_PLL3MUL_1 (0x2UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00002000 */ |
2106 | #define RCC_CFGR2_PLL3MUL_2 (0x4UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00004000 */ |
| 2107 | #define RCC_CFGR2_PLL3MUL_2 (0x4UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00004000 */ |
2107 | #define RCC_CFGR2_PLL3MUL_3 (0x8UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00008000 */ |
| 2108 | #define RCC_CFGR2_PLL3MUL_3 (0x8UL << RCC_CFGR2_PLL3MUL_Pos) /*!< 0x00008000 */ |
2108 | |
| 2109 | 2109 | #define RCC_CFGR2_PLL3MUL8_Pos (13U) |
|
| 2110 | #define RCC_CFGR2_PLL3MUL8_Pos (13U) |
2110 | #define RCC_CFGR2_PLL3MUL8_Msk (0x3UL << RCC_CFGR2_PLL3MUL8_Pos) /*!< 0x00006000 */ |
| 2111 | #define RCC_CFGR2_PLL3MUL8_Msk (0x3UL << RCC_CFGR2_PLL3MUL8_Pos) /*!< 0x00006000 */ |
2111 | #define RCC_CFGR2_PLL3MUL8 RCC_CFGR2_PLL3MUL8_Msk /*!< PLL3 input clock * 8 */ |
| 2112 | #define RCC_CFGR2_PLL3MUL8 RCC_CFGR2_PLL3MUL8_Msk /*!< PLL3 input clock * 8 */ |
2112 | #define RCC_CFGR2_PLL3MUL9_Pos (12U) |
| 2113 | #define RCC_CFGR2_PLL3MUL9_Pos (12U) |
2113 | #define RCC_CFGR2_PLL3MUL9_Msk (0x7UL << RCC_CFGR2_PLL3MUL9_Pos) /*!< 0x00007000 */ |
| 2114 | #define RCC_CFGR2_PLL3MUL9_Msk (0x7UL << RCC_CFGR2_PLL3MUL9_Pos) /*!< 0x00007000 */ |
2114 | #define RCC_CFGR2_PLL3MUL9 RCC_CFGR2_PLL3MUL9_Msk /*!< PLL3 input clock * 9 */ |
| 2115 | #define RCC_CFGR2_PLL3MUL9 RCC_CFGR2_PLL3MUL9_Msk /*!< PLL3 input clock * 9 */ |
2115 | #define RCC_CFGR2_PLL3MUL10_Pos (15U) |
| 2116 | #define RCC_CFGR2_PLL3MUL10_Pos (15U) |
2116 | #define RCC_CFGR2_PLL3MUL10_Msk (0x1UL << RCC_CFGR2_PLL3MUL10_Pos) /*!< 0x00008000 */ |
| 2117 | #define RCC_CFGR2_PLL3MUL10_Msk (0x1UL << RCC_CFGR2_PLL3MUL10_Pos) /*!< 0x00008000 */ |
2117 | #define RCC_CFGR2_PLL3MUL10 RCC_CFGR2_PLL3MUL10_Msk /*!< PLL3 input clock * 10 */ |
| 2118 | #define RCC_CFGR2_PLL3MUL10 RCC_CFGR2_PLL3MUL10_Msk /*!< PLL3 input clock * 10 */ |
2118 | #define RCC_CFGR2_PLL3MUL11_Pos (12U) |
| 2119 | #define RCC_CFGR2_PLL3MUL11_Pos (12U) |
2119 | #define RCC_CFGR2_PLL3MUL11_Msk (0x9UL << RCC_CFGR2_PLL3MUL11_Pos) /*!< 0x00009000 */ |
| 2120 | #define RCC_CFGR2_PLL3MUL11_Msk (0x9UL << RCC_CFGR2_PLL3MUL11_Pos) /*!< 0x00009000 */ |
2120 | #define RCC_CFGR2_PLL3MUL11 RCC_CFGR2_PLL3MUL11_Msk /*!< PLL3 input clock * 11 */ |
| 2121 | #define RCC_CFGR2_PLL3MUL11 RCC_CFGR2_PLL3MUL11_Msk /*!< PLL3 input clock * 11 */ |
2121 | #define RCC_CFGR2_PLL3MUL12_Pos (13U) |
| 2122 | #define RCC_CFGR2_PLL3MUL12_Pos (13U) |
2122 | #define RCC_CFGR2_PLL3MUL12_Msk (0x5UL << RCC_CFGR2_PLL3MUL12_Pos) /*!< 0x0000A000 */ |
| 2123 | #define RCC_CFGR2_PLL3MUL12_Msk (0x5UL << RCC_CFGR2_PLL3MUL12_Pos) /*!< 0x0000A000 */ |
2123 | #define RCC_CFGR2_PLL3MUL12 RCC_CFGR2_PLL3MUL12_Msk /*!< PLL3 input clock * 12 */ |
| 2124 | #define RCC_CFGR2_PLL3MUL12 RCC_CFGR2_PLL3MUL12_Msk /*!< PLL3 input clock * 12 */ |
2124 | #define RCC_CFGR2_PLL3MUL13_Pos (12U) |
| 2125 | #define RCC_CFGR2_PLL3MUL13_Pos (12U) |
2125 | #define RCC_CFGR2_PLL3MUL13_Msk (0xBUL << RCC_CFGR2_PLL3MUL13_Pos) /*!< 0x0000B000 */ |
| 2126 | #define RCC_CFGR2_PLL3MUL13_Msk (0xBUL << RCC_CFGR2_PLL3MUL13_Pos) /*!< 0x0000B000 */ |
2126 | #define RCC_CFGR2_PLL3MUL13 RCC_CFGR2_PLL3MUL13_Msk /*!< PLL3 input clock * 13 */ |
| 2127 | #define RCC_CFGR2_PLL3MUL13 RCC_CFGR2_PLL3MUL13_Msk /*!< PLL3 input clock * 13 */ |
2127 | #define RCC_CFGR2_PLL3MUL14_Pos (14U) |
| 2128 | #define RCC_CFGR2_PLL3MUL14_Pos (14U) |
2128 | #define RCC_CFGR2_PLL3MUL14_Msk (0x3UL << RCC_CFGR2_PLL3MUL14_Pos) /*!< 0x0000C000 */ |
| 2129 | #define RCC_CFGR2_PLL3MUL14_Msk (0x3UL << RCC_CFGR2_PLL3MUL14_Pos) /*!< 0x0000C000 */ |
2129 | #define RCC_CFGR2_PLL3MUL14 RCC_CFGR2_PLL3MUL14_Msk /*!< PLL3 input clock * 14 */ |
| 2130 | #define RCC_CFGR2_PLL3MUL14 RCC_CFGR2_PLL3MUL14_Msk /*!< PLL3 input clock * 14 */ |
2130 | #define RCC_CFGR2_PLL3MUL16_Pos (13U) |
| 2131 | #define RCC_CFGR2_PLL3MUL16_Pos (13U) |
2131 | #define RCC_CFGR2_PLL3MUL16_Msk (0x7UL << RCC_CFGR2_PLL3MUL16_Pos) /*!< 0x0000E000 */ |
| 2132 | #define RCC_CFGR2_PLL3MUL16_Msk (0x7UL << RCC_CFGR2_PLL3MUL16_Pos) /*!< 0x0000E000 */ |
2132 | #define RCC_CFGR2_PLL3MUL16 RCC_CFGR2_PLL3MUL16_Msk /*!< PLL3 input clock * 16 */ |
| 2133 | #define RCC_CFGR2_PLL3MUL16 RCC_CFGR2_PLL3MUL16_Msk /*!< PLL3 input clock * 16 */ |
2133 | #define RCC_CFGR2_PLL3MUL20_Pos (12U) |
| 2134 | #define RCC_CFGR2_PLL3MUL20_Pos (12U) |
2134 | #define RCC_CFGR2_PLL3MUL20_Msk (0xFUL << RCC_CFGR2_PLL3MUL20_Pos) /*!< 0x0000F000 */ |
| 2135 | #define RCC_CFGR2_PLL3MUL20_Msk (0xFUL << RCC_CFGR2_PLL3MUL20_Pos) /*!< 0x0000F000 */ |
2135 | #define RCC_CFGR2_PLL3MUL20 RCC_CFGR2_PLL3MUL20_Msk /*!< PLL3 input clock * 20 */ |
| 2136 | #define RCC_CFGR2_PLL3MUL20 RCC_CFGR2_PLL3MUL20_Msk /*!< PLL3 input clock * 20 */ |
2136 | |
| 2137 | 2137 | #define RCC_CFGR2_PREDIV1SRC_Pos (16U) |
|
| 2138 | #define RCC_CFGR2_PREDIV1SRC_Pos (16U) |
2138 | #define RCC_CFGR2_PREDIV1SRC_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_Pos) /*!< 0x00010000 */ |
| 2139 | #define RCC_CFGR2_PREDIV1SRC_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_Pos) /*!< 0x00010000 */ |
2139 | #define RCC_CFGR2_PREDIV1SRC RCC_CFGR2_PREDIV1SRC_Msk /*!< PREDIV1 entry clock source */ |
| 2140 | #define RCC_CFGR2_PREDIV1SRC RCC_CFGR2_PREDIV1SRC_Msk /*!< PREDIV1 entry clock source */ |
2140 | #define RCC_CFGR2_PREDIV1SRC_PLL2_Pos (16U) |
| 2141 | #define RCC_CFGR2_PREDIV1SRC_PLL2_Pos (16U) |
2141 | #define RCC_CFGR2_PREDIV1SRC_PLL2_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */ |
| 2142 | #define RCC_CFGR2_PREDIV1SRC_PLL2_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_PLL2_Pos) /*!< 0x00010000 */ |
2142 | #define RCC_CFGR2_PREDIV1SRC_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2_Msk /*!< PLL2 selected as PREDIV1 entry clock source */ |
| 2143 | #define RCC_CFGR2_PREDIV1SRC_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2_Msk /*!< PLL2 selected as PREDIV1 entry clock source */ |
2143 | #define RCC_CFGR2_PREDIV1SRC_HSE 0x00000000U /*!< HSE selected as PREDIV1 entry clock source */ |
| 2144 | #define RCC_CFGR2_PREDIV1SRC_HSE 0x00000000U /*!< HSE selected as PREDIV1 entry clock source */ |
2144 | #define RCC_CFGR2_I2S2SRC_Pos (17U) |
| 2145 | #define RCC_CFGR2_I2S2SRC_Pos (17U) |
2145 | #define RCC_CFGR2_I2S2SRC_Msk (0x1UL << RCC_CFGR2_I2S2SRC_Pos) /*!< 0x00020000 */ |
| 2146 | #define RCC_CFGR2_I2S2SRC_Msk (0x1UL << RCC_CFGR2_I2S2SRC_Pos) /*!< 0x00020000 */ |
2146 | #define RCC_CFGR2_I2S2SRC RCC_CFGR2_I2S2SRC_Msk /*!< I2S2 entry clock source */ |
| 2147 | #define RCC_CFGR2_I2S2SRC RCC_CFGR2_I2S2SRC_Msk /*!< I2S2 entry clock source */ |
2147 | #define RCC_CFGR2_I2S3SRC_Pos (18U) |
| 2148 | #define RCC_CFGR2_I2S3SRC_Pos (18U) |
2148 | #define RCC_CFGR2_I2S3SRC_Msk (0x1UL << RCC_CFGR2_I2S3SRC_Pos) /*!< 0x00040000 */ |
| 2149 | #define RCC_CFGR2_I2S3SRC_Msk (0x1UL << RCC_CFGR2_I2S3SRC_Pos) /*!< 0x00040000 */ |
2149 | #define RCC_CFGR2_I2S3SRC RCC_CFGR2_I2S3SRC_Msk /*!< I2S3 clock source */ |
| 2150 | #define RCC_CFGR2_I2S3SRC RCC_CFGR2_I2S3SRC_Msk /*!< I2S3 clock source */ |
2150 | |
| 2151 | 2151 | ||
| 2152 | 2152 | /******************************************************************************/ |
|
| 2153 | /******************************************************************************/ |
2153 | /* */ |
| 2154 | /* */ |
2154 | /* General Purpose and Alternate Function I/O */ |
| 2155 | /* General Purpose and Alternate Function I/O */ |
2155 | /* */ |
| 2156 | /* */ |
2156 | /******************************************************************************/ |
| 2157 | /******************************************************************************/ |
2157 | |
| 2158 | 2158 | /******************* Bit definition for GPIO_CRL register *******************/ |
|
| 2159 | /******************* Bit definition for GPIO_CRL register *******************/ |
2159 | #define GPIO_CRL_MODE_Pos (0U) |
| 2160 | #define GPIO_CRL_MODE_Pos (0U) |
2160 | #define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ |
| 2161 | #define GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos) /*!< 0x33333333 */ |
2161 | #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ |
| 2162 | #define GPIO_CRL_MODE GPIO_CRL_MODE_Msk /*!< Port x mode bits */ |
2162 | |
| 2163 | 2163 | #define GPIO_CRL_MODE0_Pos (0U) |
|
| 2164 | #define GPIO_CRL_MODE0_Pos (0U) |
2164 | #define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ |
| 2165 | #define GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000003 */ |
2165 | #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ |
| 2166 | #define GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk /*!< MODE0[1:0] bits (Port x mode bits, pin 0) */ |
2166 | #define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ |
| 2167 | #define GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000001 */ |
2167 | #define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ |
| 2168 | #define GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos) /*!< 0x00000002 */ |
2168 | |
| 2169 | 2169 | #define GPIO_CRL_MODE1_Pos (4U) |
|
| 2170 | #define GPIO_CRL_MODE1_Pos (4U) |
2170 | #define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ |
| 2171 | #define GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000030 */ |
2171 | #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ |
| 2172 | #define GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk /*!< MODE1[1:0] bits (Port x mode bits, pin 1) */ |
2172 | #define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ |
| 2173 | #define GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000010 */ |
2173 | #define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ |
| 2174 | #define GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos) /*!< 0x00000020 */ |
2174 | |
| 2175 | 2175 | #define GPIO_CRL_MODE2_Pos (8U) |
|
| 2176 | #define GPIO_CRL_MODE2_Pos (8U) |
2176 | #define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ |
| 2177 | #define GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000300 */ |
2177 | #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ |
| 2178 | #define GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk /*!< MODE2[1:0] bits (Port x mode bits, pin 2) */ |
2178 | #define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ |
| 2179 | #define GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000100 */ |
2179 | #define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ |
| 2180 | #define GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos) /*!< 0x00000200 */ |
2180 | |
| 2181 | 2181 | #define GPIO_CRL_MODE3_Pos (12U) |
|
| 2182 | #define GPIO_CRL_MODE3_Pos (12U) |
2182 | #define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ |
| 2183 | #define GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos) /*!< 0x00003000 */ |
2183 | #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ |
| 2184 | #define GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk /*!< MODE3[1:0] bits (Port x mode bits, pin 3) */ |
2184 | #define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ |
| 2185 | #define GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos) /*!< 0x00001000 */ |
2185 | #define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ |
| 2186 | #define GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos) /*!< 0x00002000 */ |
2186 | |
| 2187 | 2187 | #define GPIO_CRL_MODE4_Pos (16U) |
|
| 2188 | #define GPIO_CRL_MODE4_Pos (16U) |
2188 | #define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ |
| 2189 | #define GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos) /*!< 0x00030000 */ |
2189 | #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ |
| 2190 | #define GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk /*!< MODE4[1:0] bits (Port x mode bits, pin 4) */ |
2190 | #define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ |
| 2191 | #define GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos) /*!< 0x00010000 */ |
2191 | #define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ |
| 2192 | #define GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos) /*!< 0x00020000 */ |
2192 | |
| 2193 | 2193 | #define GPIO_CRL_MODE5_Pos (20U) |
|
| 2194 | #define GPIO_CRL_MODE5_Pos (20U) |
2194 | #define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ |
| 2195 | #define GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos) /*!< 0x00300000 */ |
2195 | #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ |
| 2196 | #define GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk /*!< MODE5[1:0] bits (Port x mode bits, pin 5) */ |
2196 | #define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ |
| 2197 | #define GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos) /*!< 0x00100000 */ |
2197 | #define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ |
| 2198 | #define GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos) /*!< 0x00200000 */ |
2198 | |
| 2199 | 2199 | #define GPIO_CRL_MODE6_Pos (24U) |
|
| 2200 | #define GPIO_CRL_MODE6_Pos (24U) |
2200 | #define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ |
| 2201 | #define GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos) /*!< 0x03000000 */ |
2201 | #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ |
| 2202 | #define GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk /*!< MODE6[1:0] bits (Port x mode bits, pin 6) */ |
2202 | #define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ |
| 2203 | #define GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos) /*!< 0x01000000 */ |
2203 | #define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ |
| 2204 | #define GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos) /*!< 0x02000000 */ |
2204 | |
| 2205 | 2205 | #define GPIO_CRL_MODE7_Pos (28U) |
|
| 2206 | #define GPIO_CRL_MODE7_Pos (28U) |
2206 | #define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ |
| 2207 | #define GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos) /*!< 0x30000000 */ |
2207 | #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ |
| 2208 | #define GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk /*!< MODE7[1:0] bits (Port x mode bits, pin 7) */ |
2208 | #define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ |
| 2209 | #define GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos) /*!< 0x10000000 */ |
2209 | #define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ |
| 2210 | #define GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos) /*!< 0x20000000 */ |
2210 | |
| 2211 | 2211 | #define GPIO_CRL_CNF_Pos (2U) |
|
| 2212 | #define GPIO_CRL_CNF_Pos (2U) |
2212 | #define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ |
| 2213 | #define GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos) /*!< 0xCCCCCCCC */ |
2213 | #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ |
| 2214 | #define GPIO_CRL_CNF GPIO_CRL_CNF_Msk /*!< Port x configuration bits */ |
2214 | |
| 2215 | 2215 | #define GPIO_CRL_CNF0_Pos (2U) |
|
| 2216 | #define GPIO_CRL_CNF0_Pos (2U) |
2216 | #define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ |
| 2217 | #define GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos) /*!< 0x0000000C */ |
2217 | #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ |
| 2218 | #define GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk /*!< CNF0[1:0] bits (Port x configuration bits, pin 0) */ |
2218 | #define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ |
| 2219 | #define GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000004 */ |
2219 | #define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ |
| 2220 | #define GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos) /*!< 0x00000008 */ |
2220 | |
| 2221 | 2221 | #define GPIO_CRL_CNF1_Pos (6U) |
|
| 2222 | #define GPIO_CRL_CNF1_Pos (6U) |
2222 | #define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ |
| 2223 | #define GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos) /*!< 0x000000C0 */ |
2223 | #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ |
| 2224 | #define GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk /*!< CNF1[1:0] bits (Port x configuration bits, pin 1) */ |
2224 | #define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ |
| 2225 | #define GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000040 */ |
2225 | #define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ |
| 2226 | #define GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos) /*!< 0x00000080 */ |
2226 | |
| 2227 | 2227 | #define GPIO_CRL_CNF2_Pos (10U) |
|
| 2228 | #define GPIO_CRL_CNF2_Pos (10U) |
2228 | #define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ |
| 2229 | #define GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000C00 */ |
2229 | #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ |
| 2230 | #define GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk /*!< CNF2[1:0] bits (Port x configuration bits, pin 2) */ |
2230 | #define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ |
| 2231 | #define GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000400 */ |
2231 | #define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ |
| 2232 | #define GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos) /*!< 0x00000800 */ |
2232 | |
| 2233 | 2233 | #define GPIO_CRL_CNF3_Pos (14U) |
|
| 2234 | #define GPIO_CRL_CNF3_Pos (14U) |
2234 | #define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ |
| 2235 | #define GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos) /*!< 0x0000C000 */ |
2235 | #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ |
| 2236 | #define GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk /*!< CNF3[1:0] bits (Port x configuration bits, pin 3) */ |
2236 | #define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ |
| 2237 | #define GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos) /*!< 0x00004000 */ |
2237 | #define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ |
| 2238 | #define GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos) /*!< 0x00008000 */ |
2238 | |
| 2239 | 2239 | #define GPIO_CRL_CNF4_Pos (18U) |
|
| 2240 | #define GPIO_CRL_CNF4_Pos (18U) |
2240 | #define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ |
| 2241 | #define GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos) /*!< 0x000C0000 */ |
2241 | #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ |
| 2242 | #define GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk /*!< CNF4[1:0] bits (Port x configuration bits, pin 4) */ |
2242 | #define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ |
| 2243 | #define GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos) /*!< 0x00040000 */ |
2243 | #define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ |
| 2244 | #define GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos) /*!< 0x00080000 */ |
2244 | |
| 2245 | 2245 | #define GPIO_CRL_CNF5_Pos (22U) |
|
| 2246 | #define GPIO_CRL_CNF5_Pos (22U) |
2246 | #define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ |
| 2247 | #define GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos) /*!< 0x00C00000 */ |
2247 | #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ |
| 2248 | #define GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk /*!< CNF5[1:0] bits (Port x configuration bits, pin 5) */ |
2248 | #define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ |
| 2249 | #define GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos) /*!< 0x00400000 */ |
2249 | #define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ |
| 2250 | #define GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos) /*!< 0x00800000 */ |
2250 | |
| 2251 | 2251 | #define GPIO_CRL_CNF6_Pos (26U) |
|
| 2252 | #define GPIO_CRL_CNF6_Pos (26U) |
2252 | #define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ |
| 2253 | #define GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos) /*!< 0x0C000000 */ |
2253 | #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ |
| 2254 | #define GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk /*!< CNF6[1:0] bits (Port x configuration bits, pin 6) */ |
2254 | #define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ |
| 2255 | #define GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos) /*!< 0x04000000 */ |
2255 | #define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ |
| 2256 | #define GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos) /*!< 0x08000000 */ |
2256 | |
| 2257 | 2257 | #define GPIO_CRL_CNF7_Pos (30U) |
|
| 2258 | #define GPIO_CRL_CNF7_Pos (30U) |
2258 | #define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ |
| 2259 | #define GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos) /*!< 0xC0000000 */ |
2259 | #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ |
| 2260 | #define GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk /*!< CNF7[1:0] bits (Port x configuration bits, pin 7) */ |
2260 | #define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ |
| 2261 | #define GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos) /*!< 0x40000000 */ |
2261 | #define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ |
| 2262 | #define GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos) /*!< 0x80000000 */ |
2262 | |
| 2263 | 2263 | /******************* Bit definition for GPIO_CRH register *******************/ |
|
| 2264 | /******************* Bit definition for GPIO_CRH register *******************/ |
2264 | #define GPIO_CRH_MODE_Pos (0U) |
| 2265 | #define GPIO_CRH_MODE_Pos (0U) |
2265 | #define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ |
| 2266 | #define GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos) /*!< 0x33333333 */ |
2266 | #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ |
| 2267 | #define GPIO_CRH_MODE GPIO_CRH_MODE_Msk /*!< Port x mode bits */ |
2267 | |
| 2268 | 2268 | #define GPIO_CRH_MODE8_Pos (0U) |
|
| 2269 | #define GPIO_CRH_MODE8_Pos (0U) |
2269 | #define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ |
| 2270 | #define GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000003 */ |
2270 | #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ |
| 2271 | #define GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk /*!< MODE8[1:0] bits (Port x mode bits, pin 8) */ |
2271 | #define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ |
| 2272 | #define GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000001 */ |
2272 | #define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ |
| 2273 | #define GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos) /*!< 0x00000002 */ |
2273 | |
| 2274 | 2274 | #define GPIO_CRH_MODE9_Pos (4U) |
|
| 2275 | #define GPIO_CRH_MODE9_Pos (4U) |
2275 | #define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ |
| 2276 | #define GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000030 */ |
2276 | #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ |
| 2277 | #define GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk /*!< MODE9[1:0] bits (Port x mode bits, pin 9) */ |
2277 | #define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ |
| 2278 | #define GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000010 */ |
2278 | #define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ |
| 2279 | #define GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos) /*!< 0x00000020 */ |
2279 | |
| 2280 | 2280 | #define GPIO_CRH_MODE10_Pos (8U) |
|
| 2281 | #define GPIO_CRH_MODE10_Pos (8U) |
2281 | #define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ |
| 2282 | #define GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000300 */ |
2282 | #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ |
| 2283 | #define GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk /*!< MODE10[1:0] bits (Port x mode bits, pin 10) */ |
2283 | #define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ |
| 2284 | #define GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000100 */ |
2284 | #define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ |
| 2285 | #define GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos) /*!< 0x00000200 */ |
2285 | |
| 2286 | 2286 | #define GPIO_CRH_MODE11_Pos (12U) |
|
| 2287 | #define GPIO_CRH_MODE11_Pos (12U) |
2287 | #define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ |
| 2288 | #define GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos) /*!< 0x00003000 */ |
2288 | #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ |
| 2289 | #define GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk /*!< MODE11[1:0] bits (Port x mode bits, pin 11) */ |
2289 | #define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ |
| 2290 | #define GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos) /*!< 0x00001000 */ |
2290 | #define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ |
| 2291 | #define GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos) /*!< 0x00002000 */ |
2291 | |
| 2292 | 2292 | #define GPIO_CRH_MODE12_Pos (16U) |
|
| 2293 | #define GPIO_CRH_MODE12_Pos (16U) |
2293 | #define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ |
| 2294 | #define GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos) /*!< 0x00030000 */ |
2294 | #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ |
| 2295 | #define GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk /*!< MODE12[1:0] bits (Port x mode bits, pin 12) */ |
2295 | #define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ |
| 2296 | #define GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos) /*!< 0x00010000 */ |
2296 | #define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ |
| 2297 | #define GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos) /*!< 0x00020000 */ |
2297 | |
| 2298 | 2298 | #define GPIO_CRH_MODE13_Pos (20U) |
|
| 2299 | #define GPIO_CRH_MODE13_Pos (20U) |
2299 | #define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ |
| 2300 | #define GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos) /*!< 0x00300000 */ |
2300 | #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ |
| 2301 | #define GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk /*!< MODE13[1:0] bits (Port x mode bits, pin 13) */ |
2301 | #define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ |
| 2302 | #define GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos) /*!< 0x00100000 */ |
2302 | #define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ |
| 2303 | #define GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos) /*!< 0x00200000 */ |
2303 | |
| 2304 | 2304 | #define GPIO_CRH_MODE14_Pos (24U) |
|
| 2305 | #define GPIO_CRH_MODE14_Pos (24U) |
2305 | #define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ |
| 2306 | #define GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos) /*!< 0x03000000 */ |
2306 | #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ |
| 2307 | #define GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk /*!< MODE14[1:0] bits (Port x mode bits, pin 14) */ |
2307 | #define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ |
| 2308 | #define GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos) /*!< 0x01000000 */ |
2308 | #define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ |
| 2309 | #define GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos) /*!< 0x02000000 */ |
2309 | |
| 2310 | 2310 | #define GPIO_CRH_MODE15_Pos (28U) |
|
| 2311 | #define GPIO_CRH_MODE15_Pos (28U) |
2311 | #define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ |
| 2312 | #define GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos) /*!< 0x30000000 */ |
2312 | #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ |
| 2313 | #define GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk /*!< MODE15[1:0] bits (Port x mode bits, pin 15) */ |
2313 | #define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ |
| 2314 | #define GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos) /*!< 0x10000000 */ |
2314 | #define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ |
| 2315 | #define GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos) /*!< 0x20000000 */ |
2315 | |
| 2316 | 2316 | #define GPIO_CRH_CNF_Pos (2U) |
|
| 2317 | #define GPIO_CRH_CNF_Pos (2U) |
2317 | #define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ |
| 2318 | #define GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos) /*!< 0xCCCCCCCC */ |
2318 | #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ |
| 2319 | #define GPIO_CRH_CNF GPIO_CRH_CNF_Msk /*!< Port x configuration bits */ |
2319 | |
| 2320 | 2320 | #define GPIO_CRH_CNF8_Pos (2U) |
|
| 2321 | #define GPIO_CRH_CNF8_Pos (2U) |
2321 | #define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ |
| 2322 | #define GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos) /*!< 0x0000000C */ |
2322 | #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ |
| 2323 | #define GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk /*!< CNF8[1:0] bits (Port x configuration bits, pin 8) */ |
2323 | #define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ |
| 2324 | #define GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000004 */ |
2324 | #define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ |
| 2325 | #define GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos) /*!< 0x00000008 */ |
2325 | |
| 2326 | 2326 | #define GPIO_CRH_CNF9_Pos (6U) |
|
| 2327 | #define GPIO_CRH_CNF9_Pos (6U) |
2327 | #define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ |
| 2328 | #define GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos) /*!< 0x000000C0 */ |
2328 | #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ |
| 2329 | #define GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk /*!< CNF9[1:0] bits (Port x configuration bits, pin 9) */ |
2329 | #define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ |
| 2330 | #define GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000040 */ |
2330 | #define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ |
| 2331 | #define GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos) /*!< 0x00000080 */ |
2331 | |
| 2332 | 2332 | #define GPIO_CRH_CNF10_Pos (10U) |
|
| 2333 | #define GPIO_CRH_CNF10_Pos (10U) |
2333 | #define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ |
| 2334 | #define GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000C00 */ |
2334 | #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ |
| 2335 | #define GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk /*!< CNF10[1:0] bits (Port x configuration bits, pin 10) */ |
2335 | #define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ |
| 2336 | #define GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000400 */ |
2336 | #define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ |
| 2337 | #define GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos) /*!< 0x00000800 */ |
2337 | |
| 2338 | 2338 | #define GPIO_CRH_CNF11_Pos (14U) |
|
| 2339 | #define GPIO_CRH_CNF11_Pos (14U) |
2339 | #define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ |
| 2340 | #define GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos) /*!< 0x0000C000 */ |
2340 | #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ |
| 2341 | #define GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk /*!< CNF11[1:0] bits (Port x configuration bits, pin 11) */ |
2341 | #define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ |
| 2342 | #define GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos) /*!< 0x00004000 */ |
2342 | #define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ |
| 2343 | #define GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos) /*!< 0x00008000 */ |
2343 | |
| 2344 | 2344 | #define GPIO_CRH_CNF12_Pos (18U) |
|
| 2345 | #define GPIO_CRH_CNF12_Pos (18U) |
2345 | #define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ |
| 2346 | #define GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos) /*!< 0x000C0000 */ |
2346 | #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ |
| 2347 | #define GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk /*!< CNF12[1:0] bits (Port x configuration bits, pin 12) */ |
2347 | #define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ |
| 2348 | #define GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos) /*!< 0x00040000 */ |
2348 | #define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ |
| 2349 | #define GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos) /*!< 0x00080000 */ |
2349 | |
| 2350 | 2350 | #define GPIO_CRH_CNF13_Pos (22U) |
|
| 2351 | #define GPIO_CRH_CNF13_Pos (22U) |
2351 | #define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ |
| 2352 | #define GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos) /*!< 0x00C00000 */ |
2352 | #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ |
| 2353 | #define GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk /*!< CNF13[1:0] bits (Port x configuration bits, pin 13) */ |
2353 | #define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ |
| 2354 | #define GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos) /*!< 0x00400000 */ |
2354 | #define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ |
| 2355 | #define GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos) /*!< 0x00800000 */ |
2355 | |
| 2356 | 2356 | #define GPIO_CRH_CNF14_Pos (26U) |
|
| 2357 | #define GPIO_CRH_CNF14_Pos (26U) |
2357 | #define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ |
| 2358 | #define GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos) /*!< 0x0C000000 */ |
2358 | #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ |
| 2359 | #define GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk /*!< CNF14[1:0] bits (Port x configuration bits, pin 14) */ |
2359 | #define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ |
| 2360 | #define GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos) /*!< 0x04000000 */ |
2360 | #define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ |
| 2361 | #define GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos) /*!< 0x08000000 */ |
2361 | |
| 2362 | 2362 | #define GPIO_CRH_CNF15_Pos (30U) |
|
| 2363 | #define GPIO_CRH_CNF15_Pos (30U) |
2363 | #define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ |
| 2364 | #define GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos) /*!< 0xC0000000 */ |
2364 | #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ |
| 2365 | #define GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk /*!< CNF15[1:0] bits (Port x configuration bits, pin 15) */ |
2365 | #define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ |
| 2366 | #define GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos) /*!< 0x40000000 */ |
2366 | #define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ |
| 2367 | #define GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos) /*!< 0x80000000 */ |
2367 | |
| 2368 | 2368 | /*!<****************** Bit definition for GPIO_IDR register *******************/ |
|
| 2369 | /*!<****************** Bit definition for GPIO_IDR register *******************/ |
2369 | #define GPIO_IDR_IDR0_Pos (0U) |
| 2370 | #define GPIO_IDR_IDR0_Pos (0U) |
2370 | #define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ |
| 2371 | #define GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos) /*!< 0x00000001 */ |
2371 | #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ |
| 2372 | #define GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk /*!< Port input data, bit 0 */ |
2372 | #define GPIO_IDR_IDR1_Pos (1U) |
| 2373 | #define GPIO_IDR_IDR1_Pos (1U) |
2373 | #define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ |
| 2374 | #define GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos) /*!< 0x00000002 */ |
2374 | #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ |
| 2375 | #define GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk /*!< Port input data, bit 1 */ |
2375 | #define GPIO_IDR_IDR2_Pos (2U) |
| 2376 | #define GPIO_IDR_IDR2_Pos (2U) |
2376 | #define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ |
| 2377 | #define GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos) /*!< 0x00000004 */ |
2377 | #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ |
| 2378 | #define GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk /*!< Port input data, bit 2 */ |
2378 | #define GPIO_IDR_IDR3_Pos (3U) |
| 2379 | #define GPIO_IDR_IDR3_Pos (3U) |
2379 | #define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ |
| 2380 | #define GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos) /*!< 0x00000008 */ |
2380 | #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ |
| 2381 | #define GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk /*!< Port input data, bit 3 */ |
2381 | #define GPIO_IDR_IDR4_Pos (4U) |
| 2382 | #define GPIO_IDR_IDR4_Pos (4U) |
2382 | #define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ |
| 2383 | #define GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos) /*!< 0x00000010 */ |
2383 | #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ |
| 2384 | #define GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk /*!< Port input data, bit 4 */ |
2384 | #define GPIO_IDR_IDR5_Pos (5U) |
| 2385 | #define GPIO_IDR_IDR5_Pos (5U) |
2385 | #define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ |
| 2386 | #define GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos) /*!< 0x00000020 */ |
2386 | #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ |
| 2387 | #define GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk /*!< Port input data, bit 5 */ |
2387 | #define GPIO_IDR_IDR6_Pos (6U) |
| 2388 | #define GPIO_IDR_IDR6_Pos (6U) |
2388 | #define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ |
| 2389 | #define GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos) /*!< 0x00000040 */ |
2389 | #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ |
| 2390 | #define GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk /*!< Port input data, bit 6 */ |
2390 | #define GPIO_IDR_IDR7_Pos (7U) |
| 2391 | #define GPIO_IDR_IDR7_Pos (7U) |
2391 | #define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ |
| 2392 | #define GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos) /*!< 0x00000080 */ |
2392 | #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ |
| 2393 | #define GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk /*!< Port input data, bit 7 */ |
2393 | #define GPIO_IDR_IDR8_Pos (8U) |
| 2394 | #define GPIO_IDR_IDR8_Pos (8U) |
2394 | #define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ |
| 2395 | #define GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos) /*!< 0x00000100 */ |
2395 | #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ |
| 2396 | #define GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk /*!< Port input data, bit 8 */ |
2396 | #define GPIO_IDR_IDR9_Pos (9U) |
| 2397 | #define GPIO_IDR_IDR9_Pos (9U) |
2397 | #define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ |
| 2398 | #define GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos) /*!< 0x00000200 */ |
2398 | #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ |
| 2399 | #define GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk /*!< Port input data, bit 9 */ |
2399 | #define GPIO_IDR_IDR10_Pos (10U) |
| 2400 | #define GPIO_IDR_IDR10_Pos (10U) |
2400 | #define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ |
| 2401 | #define GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos) /*!< 0x00000400 */ |
2401 | #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ |
| 2402 | #define GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk /*!< Port input data, bit 10 */ |
2402 | #define GPIO_IDR_IDR11_Pos (11U) |
| 2403 | #define GPIO_IDR_IDR11_Pos (11U) |
2403 | #define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ |
| 2404 | #define GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos) /*!< 0x00000800 */ |
2404 | #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ |
| 2405 | #define GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk /*!< Port input data, bit 11 */ |
2405 | #define GPIO_IDR_IDR12_Pos (12U) |
| 2406 | #define GPIO_IDR_IDR12_Pos (12U) |
2406 | #define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ |
| 2407 | #define GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos) /*!< 0x00001000 */ |
2407 | #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ |
| 2408 | #define GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk /*!< Port input data, bit 12 */ |
2408 | #define GPIO_IDR_IDR13_Pos (13U) |
| 2409 | #define GPIO_IDR_IDR13_Pos (13U) |
2409 | #define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ |
| 2410 | #define GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos) /*!< 0x00002000 */ |
2410 | #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ |
| 2411 | #define GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk /*!< Port input data, bit 13 */ |
2411 | #define GPIO_IDR_IDR14_Pos (14U) |
| 2412 | #define GPIO_IDR_IDR14_Pos (14U) |
2412 | #define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ |
| 2413 | #define GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos) /*!< 0x00004000 */ |
2413 | #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ |
| 2414 | #define GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk /*!< Port input data, bit 14 */ |
2414 | #define GPIO_IDR_IDR15_Pos (15U) |
| 2415 | #define GPIO_IDR_IDR15_Pos (15U) |
2415 | #define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ |
| 2416 | #define GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos) /*!< 0x00008000 */ |
2416 | #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ |
| 2417 | #define GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk /*!< Port input data, bit 15 */ |
2417 | |
| 2418 | 2418 | /******************* Bit definition for GPIO_ODR register *******************/ |
|
| 2419 | /******************* Bit definition for GPIO_ODR register *******************/ |
2419 | #define GPIO_ODR_ODR0_Pos (0U) |
| 2420 | #define GPIO_ODR_ODR0_Pos (0U) |
2420 | #define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ |
| 2421 | #define GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos) /*!< 0x00000001 */ |
2421 | #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ |
| 2422 | #define GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk /*!< Port output data, bit 0 */ |
2422 | #define GPIO_ODR_ODR1_Pos (1U) |
| 2423 | #define GPIO_ODR_ODR1_Pos (1U) |
2423 | #define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ |
| 2424 | #define GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos) /*!< 0x00000002 */ |
2424 | #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ |
| 2425 | #define GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk /*!< Port output data, bit 1 */ |
2425 | #define GPIO_ODR_ODR2_Pos (2U) |
| 2426 | #define GPIO_ODR_ODR2_Pos (2U) |
2426 | #define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ |
| 2427 | #define GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos) /*!< 0x00000004 */ |
2427 | #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ |
| 2428 | #define GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk /*!< Port output data, bit 2 */ |
2428 | #define GPIO_ODR_ODR3_Pos (3U) |
| 2429 | #define GPIO_ODR_ODR3_Pos (3U) |
2429 | #define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ |
| 2430 | #define GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos) /*!< 0x00000008 */ |
2430 | #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ |
| 2431 | #define GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk /*!< Port output data, bit 3 */ |
2431 | #define GPIO_ODR_ODR4_Pos (4U) |
| 2432 | #define GPIO_ODR_ODR4_Pos (4U) |
2432 | #define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ |
| 2433 | #define GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos) /*!< 0x00000010 */ |
2433 | #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ |
| 2434 | #define GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk /*!< Port output data, bit 4 */ |
2434 | #define GPIO_ODR_ODR5_Pos (5U) |
| 2435 | #define GPIO_ODR_ODR5_Pos (5U) |
2435 | #define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ |
| 2436 | #define GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos) /*!< 0x00000020 */ |
2436 | #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ |
| 2437 | #define GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk /*!< Port output data, bit 5 */ |
2437 | #define GPIO_ODR_ODR6_Pos (6U) |
| 2438 | #define GPIO_ODR_ODR6_Pos (6U) |
2438 | #define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ |
| 2439 | #define GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos) /*!< 0x00000040 */ |
2439 | #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ |
| 2440 | #define GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk /*!< Port output data, bit 6 */ |
2440 | #define GPIO_ODR_ODR7_Pos (7U) |
| 2441 | #define GPIO_ODR_ODR7_Pos (7U) |
2441 | #define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ |
| 2442 | #define GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos) /*!< 0x00000080 */ |
2442 | #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ |
| 2443 | #define GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk /*!< Port output data, bit 7 */ |
2443 | #define GPIO_ODR_ODR8_Pos (8U) |
| 2444 | #define GPIO_ODR_ODR8_Pos (8U) |
2444 | #define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ |
| 2445 | #define GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos) /*!< 0x00000100 */ |
2445 | #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ |
| 2446 | #define GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk /*!< Port output data, bit 8 */ |
2446 | #define GPIO_ODR_ODR9_Pos (9U) |
| 2447 | #define GPIO_ODR_ODR9_Pos (9U) |
2447 | #define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ |
| 2448 | #define GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos) /*!< 0x00000200 */ |
2448 | #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ |
| 2449 | #define GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk /*!< Port output data, bit 9 */ |
2449 | #define GPIO_ODR_ODR10_Pos (10U) |
| 2450 | #define GPIO_ODR_ODR10_Pos (10U) |
2450 | #define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ |
| 2451 | #define GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos) /*!< 0x00000400 */ |
2451 | #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ |
| 2452 | #define GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk /*!< Port output data, bit 10 */ |
2452 | #define GPIO_ODR_ODR11_Pos (11U) |
| 2453 | #define GPIO_ODR_ODR11_Pos (11U) |
2453 | #define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ |
| 2454 | #define GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos) /*!< 0x00000800 */ |
2454 | #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ |
| 2455 | #define GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk /*!< Port output data, bit 11 */ |
2455 | #define GPIO_ODR_ODR12_Pos (12U) |
| 2456 | #define GPIO_ODR_ODR12_Pos (12U) |
2456 | #define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ |
| 2457 | #define GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos) /*!< 0x00001000 */ |
2457 | #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ |
| 2458 | #define GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk /*!< Port output data, bit 12 */ |
2458 | #define GPIO_ODR_ODR13_Pos (13U) |
| 2459 | #define GPIO_ODR_ODR13_Pos (13U) |
2459 | #define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ |
| 2460 | #define GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos) /*!< 0x00002000 */ |
2460 | #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ |
| 2461 | #define GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk /*!< Port output data, bit 13 */ |
2461 | #define GPIO_ODR_ODR14_Pos (14U) |
| 2462 | #define GPIO_ODR_ODR14_Pos (14U) |
2462 | #define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ |
| 2463 | #define GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos) /*!< 0x00004000 */ |
2463 | #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ |
| 2464 | #define GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk /*!< Port output data, bit 14 */ |
2464 | #define GPIO_ODR_ODR15_Pos (15U) |
| 2465 | #define GPIO_ODR_ODR15_Pos (15U) |
2465 | #define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ |
| 2466 | #define GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos) /*!< 0x00008000 */ |
2466 | #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ |
| 2467 | #define GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk /*!< Port output data, bit 15 */ |
2467 | |
| 2468 | 2468 | /****************** Bit definition for GPIO_BSRR register *******************/ |
|
| 2469 | /****************** Bit definition for GPIO_BSRR register *******************/ |
2469 | #define GPIO_BSRR_BS0_Pos (0U) |
| 2470 | #define GPIO_BSRR_BS0_Pos (0U) |
2470 | #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ |
| 2471 | #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ |
2471 | #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ |
| 2472 | #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk /*!< Port x Set bit 0 */ |
2472 | #define GPIO_BSRR_BS1_Pos (1U) |
| 2473 | #define GPIO_BSRR_BS1_Pos (1U) |
2473 | #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ |
| 2474 | #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ |
2474 | #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ |
| 2475 | #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk /*!< Port x Set bit 1 */ |
2475 | #define GPIO_BSRR_BS2_Pos (2U) |
| 2476 | #define GPIO_BSRR_BS2_Pos (2U) |
2476 | #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ |
| 2477 | #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ |
2477 | #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ |
| 2478 | #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk /*!< Port x Set bit 2 */ |
2478 | #define GPIO_BSRR_BS3_Pos (3U) |
| 2479 | #define GPIO_BSRR_BS3_Pos (3U) |
2479 | #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ |
| 2480 | #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ |
2480 | #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ |
| 2481 | #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk /*!< Port x Set bit 3 */ |
2481 | #define GPIO_BSRR_BS4_Pos (4U) |
| 2482 | #define GPIO_BSRR_BS4_Pos (4U) |
2482 | #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ |
| 2483 | #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ |
2483 | #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ |
| 2484 | #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk /*!< Port x Set bit 4 */ |
2484 | #define GPIO_BSRR_BS5_Pos (5U) |
| 2485 | #define GPIO_BSRR_BS5_Pos (5U) |
2485 | #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ |
| 2486 | #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ |
2486 | #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ |
| 2487 | #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk /*!< Port x Set bit 5 */ |
2487 | #define GPIO_BSRR_BS6_Pos (6U) |
| 2488 | #define GPIO_BSRR_BS6_Pos (6U) |
2488 | #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ |
| 2489 | #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ |
2489 | #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ |
| 2490 | #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk /*!< Port x Set bit 6 */ |
2490 | #define GPIO_BSRR_BS7_Pos (7U) |
| 2491 | #define GPIO_BSRR_BS7_Pos (7U) |
2491 | #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ |
| 2492 | #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ |
2492 | #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ |
| 2493 | #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk /*!< Port x Set bit 7 */ |
2493 | #define GPIO_BSRR_BS8_Pos (8U) |
| 2494 | #define GPIO_BSRR_BS8_Pos (8U) |
2494 | #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ |
| 2495 | #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ |
2495 | #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ |
| 2496 | #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk /*!< Port x Set bit 8 */ |
2496 | #define GPIO_BSRR_BS9_Pos (9U) |
| 2497 | #define GPIO_BSRR_BS9_Pos (9U) |
2497 | #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ |
| 2498 | #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ |
2498 | #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ |
| 2499 | #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk /*!< Port x Set bit 9 */ |
2499 | #define GPIO_BSRR_BS10_Pos (10U) |
| 2500 | #define GPIO_BSRR_BS10_Pos (10U) |
2500 | #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ |
| 2501 | #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ |
2501 | #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ |
| 2502 | #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk /*!< Port x Set bit 10 */ |
2502 | #define GPIO_BSRR_BS11_Pos (11U) |
| 2503 | #define GPIO_BSRR_BS11_Pos (11U) |
2503 | #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ |
| 2504 | #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ |
2504 | #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ |
| 2505 | #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk /*!< Port x Set bit 11 */ |
2505 | #define GPIO_BSRR_BS12_Pos (12U) |
| 2506 | #define GPIO_BSRR_BS12_Pos (12U) |
2506 | #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ |
| 2507 | #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ |
2507 | #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ |
| 2508 | #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk /*!< Port x Set bit 12 */ |
2508 | #define GPIO_BSRR_BS13_Pos (13U) |
| 2509 | #define GPIO_BSRR_BS13_Pos (13U) |
2509 | #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ |
| 2510 | #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ |
2510 | #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ |
| 2511 | #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk /*!< Port x Set bit 13 */ |
2511 | #define GPIO_BSRR_BS14_Pos (14U) |
| 2512 | #define GPIO_BSRR_BS14_Pos (14U) |
2512 | #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ |
| 2513 | #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ |
2513 | #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ |
| 2514 | #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk /*!< Port x Set bit 14 */ |
2514 | #define GPIO_BSRR_BS15_Pos (15U) |
| 2515 | #define GPIO_BSRR_BS15_Pos (15U) |
2515 | #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ |
| 2516 | #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ |
2516 | #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ |
| 2517 | #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk /*!< Port x Set bit 15 */ |
2517 | |
| 2518 | 2518 | #define GPIO_BSRR_BR0_Pos (16U) |
|
| 2519 | #define GPIO_BSRR_BR0_Pos (16U) |
2519 | #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ |
| 2520 | #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ |
2520 | #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ |
| 2521 | #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk /*!< Port x Reset bit 0 */ |
2521 | #define GPIO_BSRR_BR1_Pos (17U) |
| 2522 | #define GPIO_BSRR_BR1_Pos (17U) |
2522 | #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ |
| 2523 | #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ |
2523 | #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ |
| 2524 | #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk /*!< Port x Reset bit 1 */ |
2524 | #define GPIO_BSRR_BR2_Pos (18U) |
| 2525 | #define GPIO_BSRR_BR2_Pos (18U) |
2525 | #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ |
| 2526 | #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ |
2526 | #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ |
| 2527 | #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk /*!< Port x Reset bit 2 */ |
2527 | #define GPIO_BSRR_BR3_Pos (19U) |
| 2528 | #define GPIO_BSRR_BR3_Pos (19U) |
2528 | #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ |
| 2529 | #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ |
2529 | #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ |
| 2530 | #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk /*!< Port x Reset bit 3 */ |
2530 | #define GPIO_BSRR_BR4_Pos (20U) |
| 2531 | #define GPIO_BSRR_BR4_Pos (20U) |
2531 | #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ |
| 2532 | #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ |
2532 | #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ |
| 2533 | #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk /*!< Port x Reset bit 4 */ |
2533 | #define GPIO_BSRR_BR5_Pos (21U) |
| 2534 | #define GPIO_BSRR_BR5_Pos (21U) |
2534 | #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ |
| 2535 | #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ |
2535 | #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ |
| 2536 | #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk /*!< Port x Reset bit 5 */ |
2536 | #define GPIO_BSRR_BR6_Pos (22U) |
| 2537 | #define GPIO_BSRR_BR6_Pos (22U) |
2537 | #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ |
| 2538 | #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ |
2538 | #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ |
| 2539 | #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk /*!< Port x Reset bit 6 */ |
2539 | #define GPIO_BSRR_BR7_Pos (23U) |
| 2540 | #define GPIO_BSRR_BR7_Pos (23U) |
2540 | #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ |
| 2541 | #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ |
2541 | #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ |
| 2542 | #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk /*!< Port x Reset bit 7 */ |
2542 | #define GPIO_BSRR_BR8_Pos (24U) |
| 2543 | #define GPIO_BSRR_BR8_Pos (24U) |
2543 | #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ |
| 2544 | #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ |
2544 | #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ |
| 2545 | #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk /*!< Port x Reset bit 8 */ |
2545 | #define GPIO_BSRR_BR9_Pos (25U) |
| 2546 | #define GPIO_BSRR_BR9_Pos (25U) |
2546 | #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ |
| 2547 | #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ |
2547 | #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ |
| 2548 | #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk /*!< Port x Reset bit 9 */ |
2548 | #define GPIO_BSRR_BR10_Pos (26U) |
| 2549 | #define GPIO_BSRR_BR10_Pos (26U) |
2549 | #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ |
| 2550 | #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ |
2550 | #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ |
| 2551 | #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk /*!< Port x Reset bit 10 */ |
2551 | #define GPIO_BSRR_BR11_Pos (27U) |
| 2552 | #define GPIO_BSRR_BR11_Pos (27U) |
2552 | #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ |
| 2553 | #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ |
2553 | #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ |
| 2554 | #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk /*!< Port x Reset bit 11 */ |
2554 | #define GPIO_BSRR_BR12_Pos (28U) |
| 2555 | #define GPIO_BSRR_BR12_Pos (28U) |
2555 | #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ |
| 2556 | #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ |
2556 | #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ |
| 2557 | #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk /*!< Port x Reset bit 12 */ |
2557 | #define GPIO_BSRR_BR13_Pos (29U) |
| 2558 | #define GPIO_BSRR_BR13_Pos (29U) |
2558 | #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ |
| 2559 | #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ |
2559 | #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ |
| 2560 | #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk /*!< Port x Reset bit 13 */ |
2560 | #define GPIO_BSRR_BR14_Pos (30U) |
| 2561 | #define GPIO_BSRR_BR14_Pos (30U) |
2561 | #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ |
| 2562 | #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ |
2562 | #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ |
| 2563 | #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk /*!< Port x Reset bit 14 */ |
2563 | #define GPIO_BSRR_BR15_Pos (31U) |
| 2564 | #define GPIO_BSRR_BR15_Pos (31U) |
2564 | #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ |
| 2565 | #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ |
2565 | #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ |
| 2566 | #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk /*!< Port x Reset bit 15 */ |
2566 | |
| 2567 | 2567 | /******************* Bit definition for GPIO_BRR register *******************/ |
|
| 2568 | /******************* Bit definition for GPIO_BRR register *******************/ |
2568 | #define GPIO_BRR_BR0_Pos (0U) |
| 2569 | #define GPIO_BRR_BR0_Pos (0U) |
2569 | #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ |
| 2570 | #define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ |
2570 | #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ |
| 2571 | #define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk /*!< Port x Reset bit 0 */ |
2571 | #define GPIO_BRR_BR1_Pos (1U) |
| 2572 | #define GPIO_BRR_BR1_Pos (1U) |
2572 | #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ |
| 2573 | #define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ |
2573 | #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ |
| 2574 | #define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk /*!< Port x Reset bit 1 */ |
2574 | #define GPIO_BRR_BR2_Pos (2U) |
| 2575 | #define GPIO_BRR_BR2_Pos (2U) |
2575 | #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ |
| 2576 | #define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ |
2576 | #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ |
| 2577 | #define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk /*!< Port x Reset bit 2 */ |
2577 | #define GPIO_BRR_BR3_Pos (3U) |
| 2578 | #define GPIO_BRR_BR3_Pos (3U) |
2578 | #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ |
| 2579 | #define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ |
2579 | #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ |
| 2580 | #define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk /*!< Port x Reset bit 3 */ |
2580 | #define GPIO_BRR_BR4_Pos (4U) |
| 2581 | #define GPIO_BRR_BR4_Pos (4U) |
2581 | #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ |
| 2582 | #define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ |
2582 | #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ |
| 2583 | #define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk /*!< Port x Reset bit 4 */ |
2583 | #define GPIO_BRR_BR5_Pos (5U) |
| 2584 | #define GPIO_BRR_BR5_Pos (5U) |
2584 | #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ |
| 2585 | #define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ |
2585 | #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ |
| 2586 | #define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk /*!< Port x Reset bit 5 */ |
2586 | #define GPIO_BRR_BR6_Pos (6U) |
| 2587 | #define GPIO_BRR_BR6_Pos (6U) |
2587 | #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ |
| 2588 | #define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ |
2588 | #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ |
| 2589 | #define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk /*!< Port x Reset bit 6 */ |
2589 | #define GPIO_BRR_BR7_Pos (7U) |
| 2590 | #define GPIO_BRR_BR7_Pos (7U) |
2590 | #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ |
| 2591 | #define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ |
2591 | #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ |
| 2592 | #define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk /*!< Port x Reset bit 7 */ |
2592 | #define GPIO_BRR_BR8_Pos (8U) |
| 2593 | #define GPIO_BRR_BR8_Pos (8U) |
2593 | #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ |
| 2594 | #define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ |
2594 | #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ |
| 2595 | #define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk /*!< Port x Reset bit 8 */ |
2595 | #define GPIO_BRR_BR9_Pos (9U) |
| 2596 | #define GPIO_BRR_BR9_Pos (9U) |
2596 | #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ |
| 2597 | #define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ |
2597 | #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ |
| 2598 | #define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk /*!< Port x Reset bit 9 */ |
2598 | #define GPIO_BRR_BR10_Pos (10U) |
| 2599 | #define GPIO_BRR_BR10_Pos (10U) |
2599 | #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ |
| 2600 | #define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ |
2600 | #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ |
| 2601 | #define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk /*!< Port x Reset bit 10 */ |
2601 | #define GPIO_BRR_BR11_Pos (11U) |
| 2602 | #define GPIO_BRR_BR11_Pos (11U) |
2602 | #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ |
| 2603 | #define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ |
2603 | #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ |
| 2604 | #define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk /*!< Port x Reset bit 11 */ |
2604 | #define GPIO_BRR_BR12_Pos (12U) |
| 2605 | #define GPIO_BRR_BR12_Pos (12U) |
2605 | #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ |
| 2606 | #define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ |
2606 | #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ |
| 2607 | #define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk /*!< Port x Reset bit 12 */ |
2607 | #define GPIO_BRR_BR13_Pos (13U) |
| 2608 | #define GPIO_BRR_BR13_Pos (13U) |
2608 | #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ |
| 2609 | #define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ |
2609 | #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ |
| 2610 | #define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk /*!< Port x Reset bit 13 */ |
2610 | #define GPIO_BRR_BR14_Pos (14U) |
| 2611 | #define GPIO_BRR_BR14_Pos (14U) |
2611 | #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ |
| 2612 | #define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ |
2612 | #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ |
| 2613 | #define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk /*!< Port x Reset bit 14 */ |
2613 | #define GPIO_BRR_BR15_Pos (15U) |
| 2614 | #define GPIO_BRR_BR15_Pos (15U) |
2614 | #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ |
| 2615 | #define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ |
2615 | #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ |
| 2616 | #define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk /*!< Port x Reset bit 15 */ |
2616 | |
| 2617 | 2617 | /****************** Bit definition for GPIO_LCKR register *******************/ |
|
| 2618 | /****************** Bit definition for GPIO_LCKR register *******************/ |
2618 | #define GPIO_LCKR_LCK0_Pos (0U) |
| 2619 | #define GPIO_LCKR_LCK0_Pos (0U) |
2619 | #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ |
| 2620 | #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ |
2620 | #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ |
| 2621 | #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk /*!< Port x Lock bit 0 */ |
2621 | #define GPIO_LCKR_LCK1_Pos (1U) |
| 2622 | #define GPIO_LCKR_LCK1_Pos (1U) |
2622 | #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ |
| 2623 | #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ |
2623 | #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ |
| 2624 | #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk /*!< Port x Lock bit 1 */ |
2624 | #define GPIO_LCKR_LCK2_Pos (2U) |
| 2625 | #define GPIO_LCKR_LCK2_Pos (2U) |
2625 | #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ |
| 2626 | #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ |
2626 | #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ |
| 2627 | #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk /*!< Port x Lock bit 2 */ |
2627 | #define GPIO_LCKR_LCK3_Pos (3U) |
| 2628 | #define GPIO_LCKR_LCK3_Pos (3U) |
2628 | #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ |
| 2629 | #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ |
2629 | #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ |
| 2630 | #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk /*!< Port x Lock bit 3 */ |
2630 | #define GPIO_LCKR_LCK4_Pos (4U) |
| 2631 | #define GPIO_LCKR_LCK4_Pos (4U) |
2631 | #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ |
| 2632 | #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ |
2632 | #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ |
| 2633 | #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk /*!< Port x Lock bit 4 */ |
2633 | #define GPIO_LCKR_LCK5_Pos (5U) |
| 2634 | #define GPIO_LCKR_LCK5_Pos (5U) |
2634 | #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ |
| 2635 | #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ |
2635 | #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ |
| 2636 | #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk /*!< Port x Lock bit 5 */ |
2636 | #define GPIO_LCKR_LCK6_Pos (6U) |
| 2637 | #define GPIO_LCKR_LCK6_Pos (6U) |
2637 | #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ |
| 2638 | #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ |
2638 | #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ |
| 2639 | #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk /*!< Port x Lock bit 6 */ |
2639 | #define GPIO_LCKR_LCK7_Pos (7U) |
| 2640 | #define GPIO_LCKR_LCK7_Pos (7U) |
2640 | #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ |
| 2641 | #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ |
2641 | #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ |
| 2642 | #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk /*!< Port x Lock bit 7 */ |
2642 | #define GPIO_LCKR_LCK8_Pos (8U) |
| 2643 | #define GPIO_LCKR_LCK8_Pos (8U) |
2643 | #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ |
| 2644 | #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ |
2644 | #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ |
| 2645 | #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk /*!< Port x Lock bit 8 */ |
2645 | #define GPIO_LCKR_LCK9_Pos (9U) |
| 2646 | #define GPIO_LCKR_LCK9_Pos (9U) |
2646 | #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ |
| 2647 | #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ |
2647 | #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ |
| 2648 | #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk /*!< Port x Lock bit 9 */ |
2648 | #define GPIO_LCKR_LCK10_Pos (10U) |
| 2649 | #define GPIO_LCKR_LCK10_Pos (10U) |
2649 | #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ |
| 2650 | #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ |
2650 | #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ |
| 2651 | #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk /*!< Port x Lock bit 10 */ |
2651 | #define GPIO_LCKR_LCK11_Pos (11U) |
| 2652 | #define GPIO_LCKR_LCK11_Pos (11U) |
2652 | #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ |
| 2653 | #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ |
2653 | #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ |
| 2654 | #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk /*!< Port x Lock bit 11 */ |
2654 | #define GPIO_LCKR_LCK12_Pos (12U) |
| 2655 | #define GPIO_LCKR_LCK12_Pos (12U) |
2655 | #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ |
| 2656 | #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ |
2656 | #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ |
| 2657 | #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk /*!< Port x Lock bit 12 */ |
2657 | #define GPIO_LCKR_LCK13_Pos (13U) |
| 2658 | #define GPIO_LCKR_LCK13_Pos (13U) |
2658 | #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ |
| 2659 | #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ |
2659 | #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ |
| 2660 | #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk /*!< Port x Lock bit 13 */ |
2660 | #define GPIO_LCKR_LCK14_Pos (14U) |
| 2661 | #define GPIO_LCKR_LCK14_Pos (14U) |
2661 | #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ |
| 2662 | #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ |
2662 | #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ |
| 2663 | #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk /*!< Port x Lock bit 14 */ |
2663 | #define GPIO_LCKR_LCK15_Pos (15U) |
| 2664 | #define GPIO_LCKR_LCK15_Pos (15U) |
2664 | #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ |
| 2665 | #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ |
2665 | #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ |
| 2666 | #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk /*!< Port x Lock bit 15 */ |
2666 | #define GPIO_LCKR_LCKK_Pos (16U) |
| 2667 | #define GPIO_LCKR_LCKK_Pos (16U) |
2667 | #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ |
| 2668 | #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ |
2668 | #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ |
| 2669 | #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk /*!< Lock key */ |
2669 | |
| 2670 | 2670 | /*----------------------------------------------------------------------------*/ |
|
| 2671 | /*----------------------------------------------------------------------------*/ |
2671 | |
| 2672 | 2672 | /****************** Bit definition for AFIO_EVCR register *******************/ |
|
| 2673 | /****************** Bit definition for AFIO_EVCR register *******************/ |
2673 | #define AFIO_EVCR_PIN_Pos (0U) |
| 2674 | #define AFIO_EVCR_PIN_Pos (0U) |
2674 | #define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ |
| 2675 | #define AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos) /*!< 0x0000000F */ |
2675 | #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ |
| 2676 | #define AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk /*!< PIN[3:0] bits (Pin selection) */ |
2676 | #define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ |
| 2677 | #define AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000001 */ |
2677 | #define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ |
| 2678 | #define AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000002 */ |
2678 | #define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ |
| 2679 | #define AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000004 */ |
2679 | #define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ |
| 2680 | #define AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos) /*!< 0x00000008 */ |
2680 | |
| 2681 | 2681 | /*!< PIN configuration */ |
|
| 2682 | /*!< PIN configuration */ |
2682 | #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ |
| 2683 | #define AFIO_EVCR_PIN_PX0 0x00000000U /*!< Pin 0 selected */ |
2683 | #define AFIO_EVCR_PIN_PX1_Pos (0U) |
| 2684 | #define AFIO_EVCR_PIN_PX1_Pos (0U) |
2684 | #define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ |
| 2685 | #define AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos) /*!< 0x00000001 */ |
2685 | #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ |
| 2686 | #define AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk /*!< Pin 1 selected */ |
2686 | #define AFIO_EVCR_PIN_PX2_Pos (1U) |
| 2687 | #define AFIO_EVCR_PIN_PX2_Pos (1U) |
2687 | #define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ |
| 2688 | #define AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos) /*!< 0x00000002 */ |
2688 | #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ |
| 2689 | #define AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk /*!< Pin 2 selected */ |
2689 | #define AFIO_EVCR_PIN_PX3_Pos (0U) |
| 2690 | #define AFIO_EVCR_PIN_PX3_Pos (0U) |
2690 | #define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ |
| 2691 | #define AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos) /*!< 0x00000003 */ |
2691 | #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ |
| 2692 | #define AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk /*!< Pin 3 selected */ |
2692 | #define AFIO_EVCR_PIN_PX4_Pos (2U) |
| 2693 | #define AFIO_EVCR_PIN_PX4_Pos (2U) |
2693 | #define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ |
| 2694 | #define AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos) /*!< 0x00000004 */ |
2694 | #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ |
| 2695 | #define AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk /*!< Pin 4 selected */ |
2695 | #define AFIO_EVCR_PIN_PX5_Pos (0U) |
| 2696 | #define AFIO_EVCR_PIN_PX5_Pos (0U) |
2696 | #define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ |
| 2697 | #define AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos) /*!< 0x00000005 */ |
2697 | #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ |
| 2698 | #define AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk /*!< Pin 5 selected */ |
2698 | #define AFIO_EVCR_PIN_PX6_Pos (1U) |
| 2699 | #define AFIO_EVCR_PIN_PX6_Pos (1U) |
2699 | #define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ |
| 2700 | #define AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos) /*!< 0x00000006 */ |
2700 | #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ |
| 2701 | #define AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk /*!< Pin 6 selected */ |
2701 | #define AFIO_EVCR_PIN_PX7_Pos (0U) |
| 2702 | #define AFIO_EVCR_PIN_PX7_Pos (0U) |
2702 | #define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ |
| 2703 | #define AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos) /*!< 0x00000007 */ |
2703 | #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ |
| 2704 | #define AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk /*!< Pin 7 selected */ |
2704 | #define AFIO_EVCR_PIN_PX8_Pos (3U) |
| 2705 | #define AFIO_EVCR_PIN_PX8_Pos (3U) |
2705 | #define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ |
| 2706 | #define AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos) /*!< 0x00000008 */ |
2706 | #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ |
| 2707 | #define AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk /*!< Pin 8 selected */ |
2707 | #define AFIO_EVCR_PIN_PX9_Pos (0U) |
| 2708 | #define AFIO_EVCR_PIN_PX9_Pos (0U) |
2708 | #define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ |
| 2709 | #define AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos) /*!< 0x00000009 */ |
2709 | #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ |
| 2710 | #define AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk /*!< Pin 9 selected */ |
2710 | #define AFIO_EVCR_PIN_PX10_Pos (1U) |
| 2711 | #define AFIO_EVCR_PIN_PX10_Pos (1U) |
2711 | #define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ |
| 2712 | #define AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos) /*!< 0x0000000A */ |
2712 | #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ |
| 2713 | #define AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk /*!< Pin 10 selected */ |
2713 | #define AFIO_EVCR_PIN_PX11_Pos (0U) |
| 2714 | #define AFIO_EVCR_PIN_PX11_Pos (0U) |
2714 | #define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ |
| 2715 | #define AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos) /*!< 0x0000000B */ |
2715 | #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ |
| 2716 | #define AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk /*!< Pin 11 selected */ |
2716 | #define AFIO_EVCR_PIN_PX12_Pos (2U) |
| 2717 | #define AFIO_EVCR_PIN_PX12_Pos (2U) |
2717 | #define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ |
| 2718 | #define AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos) /*!< 0x0000000C */ |
2718 | #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ |
| 2719 | #define AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk /*!< Pin 12 selected */ |
2719 | #define AFIO_EVCR_PIN_PX13_Pos (0U) |
| 2720 | #define AFIO_EVCR_PIN_PX13_Pos (0U) |
2720 | #define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ |
| 2721 | #define AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos) /*!< 0x0000000D */ |
2721 | #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ |
| 2722 | #define AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk /*!< Pin 13 selected */ |
2722 | #define AFIO_EVCR_PIN_PX14_Pos (1U) |
| 2723 | #define AFIO_EVCR_PIN_PX14_Pos (1U) |
2723 | #define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ |
| 2724 | #define AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos) /*!< 0x0000000E */ |
2724 | #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ |
| 2725 | #define AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk /*!< Pin 14 selected */ |
2725 | #define AFIO_EVCR_PIN_PX15_Pos (0U) |
| 2726 | #define AFIO_EVCR_PIN_PX15_Pos (0U) |
2726 | #define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ |
| 2727 | #define AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos) /*!< 0x0000000F */ |
2727 | #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ |
| 2728 | #define AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk /*!< Pin 15 selected */ |
2728 | |
| 2729 | 2729 | #define AFIO_EVCR_PORT_Pos (4U) |
|
| 2730 | #define AFIO_EVCR_PORT_Pos (4U) |
2730 | #define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ |
| 2731 | #define AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000070 */ |
2731 | #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ |
| 2732 | #define AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk /*!< PORT[2:0] bits (Port selection) */ |
2732 | #define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ |
| 2733 | #define AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000010 */ |
2733 | #define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ |
| 2734 | #define AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000020 */ |
2734 | #define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ |
| 2735 | #define AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos) /*!< 0x00000040 */ |
2735 | |
| 2736 | 2736 | /*!< PORT configuration */ |
|
| 2737 | /*!< PORT configuration */ |
2737 | #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ |
| 2738 | #define AFIO_EVCR_PORT_PA 0x00000000 /*!< Port A selected */ |
2738 | #define AFIO_EVCR_PORT_PB_Pos (4U) |
| 2739 | #define AFIO_EVCR_PORT_PB_Pos (4U) |
2739 | #define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ |
| 2740 | #define AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos) /*!< 0x00000010 */ |
2740 | #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ |
| 2741 | #define AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk /*!< Port B selected */ |
2741 | #define AFIO_EVCR_PORT_PC_Pos (5U) |
| 2742 | #define AFIO_EVCR_PORT_PC_Pos (5U) |
2742 | #define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ |
| 2743 | #define AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos) /*!< 0x00000020 */ |
2743 | #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ |
| 2744 | #define AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk /*!< Port C selected */ |
2744 | #define AFIO_EVCR_PORT_PD_Pos (4U) |
| 2745 | #define AFIO_EVCR_PORT_PD_Pos (4U) |
2745 | #define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ |
| 2746 | #define AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos) /*!< 0x00000030 */ |
2746 | #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ |
| 2747 | #define AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk /*!< Port D selected */ |
2747 | #define AFIO_EVCR_PORT_PE_Pos (6U) |
| 2748 | #define AFIO_EVCR_PORT_PE_Pos (6U) |
2748 | #define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ |
| 2749 | #define AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos) /*!< 0x00000040 */ |
2749 | #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ |
| 2750 | #define AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk /*!< Port E selected */ |
2750 | |
| 2751 | 2751 | #define AFIO_EVCR_EVOE_Pos (7U) |
|
| 2752 | #define AFIO_EVCR_EVOE_Pos (7U) |
2752 | #define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ |
| 2753 | #define AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos) /*!< 0x00000080 */ |
2753 | #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ |
| 2754 | #define AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk /*!< Event Output Enable */ |
2754 | |
| 2755 | 2755 | /****************** Bit definition for AFIO_MAPR register *******************/ |
|
| 2756 | /****************** Bit definition for AFIO_MAPR register *******************/ |
2756 | #define AFIO_MAPR_SPI1_REMAP_Pos (0U) |
| 2757 | #define AFIO_MAPR_SPI1_REMAP_Pos (0U) |
2757 | #define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ |
| 2758 | #define AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos) /*!< 0x00000001 */ |
2758 | #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ |
| 2759 | #define AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk /*!< SPI1 remapping */ |
2759 | #define AFIO_MAPR_I2C1_REMAP_Pos (1U) |
| 2760 | #define AFIO_MAPR_I2C1_REMAP_Pos (1U) |
2760 | #define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ |
| 2761 | #define AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos) /*!< 0x00000002 */ |
2761 | #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ |
| 2762 | #define AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk /*!< I2C1 remapping */ |
2762 | #define AFIO_MAPR_USART1_REMAP_Pos (2U) |
| 2763 | #define AFIO_MAPR_USART1_REMAP_Pos (2U) |
2763 | #define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ |
| 2764 | #define AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos) /*!< 0x00000004 */ |
2764 | #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ |
| 2765 | #define AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk /*!< USART1 remapping */ |
2765 | #define AFIO_MAPR_USART2_REMAP_Pos (3U) |
| 2766 | #define AFIO_MAPR_USART2_REMAP_Pos (3U) |
2766 | #define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ |
| 2767 | #define AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos) /*!< 0x00000008 */ |
2767 | #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ |
| 2768 | #define AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk /*!< USART2 remapping */ |
2768 | |
| 2769 | 2769 | #define AFIO_MAPR_USART3_REMAP_Pos (4U) |
|
| 2770 | #define AFIO_MAPR_USART3_REMAP_Pos (4U) |
2770 | #define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ |
| 2771 | #define AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000030 */ |
2771 | #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ |
| 2772 | #define AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk /*!< USART3_REMAP[1:0] bits (USART3 remapping) */ |
2772 | #define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ |
| 2773 | #define AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000010 */ |
2773 | #define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ |
| 2774 | #define AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos) /*!< 0x00000020 */ |
2774 | |
| 2775 | 2775 | /* USART3_REMAP configuration */ |
|
| 2776 | /* USART3_REMAP configuration */ |
2776 | #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ |
| 2777 | #define AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U /*!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ |
2777 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) |
| 2778 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U) |
2778 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ |
| 2779 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000010 */ |
2779 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ |
| 2780 | #define AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ |
2780 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) |
| 2781 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U) |
2781 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ |
| 2782 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos) /*!< 0x00000030 */ |
2782 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ |
| 2783 | #define AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk /*!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ |
2783 | |
| 2784 | 2784 | #define AFIO_MAPR_TIM1_REMAP_Pos (6U) |
|
| 2785 | #define AFIO_MAPR_TIM1_REMAP_Pos (6U) |
2785 | #define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ |
| 2786 | #define AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x000000C0 */ |
2786 | #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ |
| 2787 | #define AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk /*!< TIM1_REMAP[1:0] bits (TIM1 remapping) */ |
2787 | #define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ |
| 2788 | #define AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000040 */ |
2788 | #define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ |
| 2789 | #define AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos) /*!< 0x00000080 */ |
2789 | |
| 2790 | 2790 | /*!< TIM1_REMAP configuration */ |
|
| 2791 | /*!< TIM1_REMAP configuration */ |
2791 | #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ |
| 2792 | #define AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U /*!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ |
2792 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) |
| 2793 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U) |
2793 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ |
| 2794 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos) /*!< 0x00000040 */ |
2794 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ |
| 2795 | #define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk /*!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ |
2795 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) |
| 2796 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U) |
2796 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ |
| 2797 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos) /*!< 0x000000C0 */ |
2797 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ |
| 2798 | #define AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk /*!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ |
2798 | |
| 2799 | 2799 | #define AFIO_MAPR_TIM2_REMAP_Pos (8U) |
|
| 2800 | #define AFIO_MAPR_TIM2_REMAP_Pos (8U) |
2800 | #define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ |
| 2801 | #define AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000300 */ |
2801 | #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ |
| 2802 | #define AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk /*!< TIM2_REMAP[1:0] bits (TIM2 remapping) */ |
2802 | #define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ |
| 2803 | #define AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000100 */ |
2803 | #define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ |
| 2804 | #define AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos) /*!< 0x00000200 */ |
2804 | |
| 2805 | 2805 | /*!< TIM2_REMAP configuration */ |
|
| 2806 | /*!< TIM2_REMAP configuration */ |
2806 | #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ |
| 2807 | #define AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ |
2807 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) |
| 2808 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U) |
2808 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ |
| 2809 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos) /*!< 0x00000100 */ |
2809 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ |
| 2810 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk /*!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ |
2810 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) |
| 2811 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U) |
2811 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ |
| 2812 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos) /*!< 0x00000200 */ |
2812 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ |
| 2813 | #define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk /*!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ |
2813 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) |
| 2814 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U) |
2814 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ |
| 2815 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos) /*!< 0x00000300 */ |
2815 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ |
| 2816 | #define AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ |
2816 | |
| 2817 | 2817 | #define AFIO_MAPR_TIM3_REMAP_Pos (10U) |
|
| 2818 | #define AFIO_MAPR_TIM3_REMAP_Pos (10U) |
2818 | #define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ |
| 2819 | #define AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000C00 */ |
2819 | #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ |
| 2820 | #define AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk /*!< TIM3_REMAP[1:0] bits (TIM3 remapping) */ |
2820 | #define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ |
| 2821 | #define AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000400 */ |
2821 | #define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ |
| 2822 | #define AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos) /*!< 0x00000800 */ |
2822 | |
| 2823 | 2823 | /*!< TIM3_REMAP configuration */ |
|
| 2824 | /*!< TIM3_REMAP configuration */ |
2824 | #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ |
| 2825 | #define AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U /*!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ |
2825 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) |
| 2826 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U) |
2826 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ |
| 2827 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos) /*!< 0x00000800 */ |
2827 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ |
| 2828 | #define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk /*!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ |
2828 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) |
| 2829 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U) |
2829 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ |
| 2830 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos) /*!< 0x00000C00 */ |
2830 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ |
| 2831 | #define AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk /*!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ |
2831 | |
| 2832 | 2832 | #define AFIO_MAPR_TIM4_REMAP_Pos (12U) |
|
| 2833 | #define AFIO_MAPR_TIM4_REMAP_Pos (12U) |
2833 | #define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ |
| 2834 | #define AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos) /*!< 0x00001000 */ |
2834 | #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ |
| 2835 | #define AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk /*!< TIM4_REMAP bit (TIM4 remapping) */ |
2835 | |
| 2836 | 2836 | #define AFIO_MAPR_CAN_REMAP_Pos (13U) |
|
| 2837 | #define AFIO_MAPR_CAN_REMAP_Pos (13U) |
2837 | #define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ |
| 2838 | #define AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00006000 */ |
2838 | #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ |
| 2839 | #define AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk /*!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ |
2839 | #define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ |
| 2840 | #define AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00002000 */ |
2840 | #define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ |
| 2841 | #define AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos) /*!< 0x00004000 */ |
2841 | |
| 2842 | 2842 | /*!< CAN_REMAP configuration */ |
|
| 2843 | /*!< CAN_REMAP configuration */ |
2843 | #define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ |
| 2844 | #define AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U /*!< CANRX mapped to PA11, CANTX mapped to PA12 */ |
2844 | #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) |
| 2845 | #define AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U) |
2845 | #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ |
| 2846 | #define AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos) /*!< 0x00004000 */ |
2846 | #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ |
| 2847 | #define AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk /*!< CANRX mapped to PB8, CANTX mapped to PB9 */ |
2847 | #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) |
| 2848 | #define AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U) |
2848 | #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ |
| 2849 | #define AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos) /*!< 0x00006000 */ |
2849 | #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ |
| 2850 | #define AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk /*!< CANRX mapped to PD0, CANTX mapped to PD1 */ |
2850 | |
| 2851 | 2851 | #define AFIO_MAPR_PD01_REMAP_Pos (15U) |
|
| 2852 | #define AFIO_MAPR_PD01_REMAP_Pos (15U) |
2852 | #define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ |
| 2853 | #define AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos) /*!< 0x00008000 */ |
2853 | #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ |
| 2854 | #define AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk /*!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ |
2854 | #define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U) |
| 2855 | #define AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U) |
2855 | #define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */ |
| 2856 | #define AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos) /*!< 0x00010000 */ |
2856 | #define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */ |
| 2857 | #define AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk /*!< TIM5 Channel4 Internal Remap */ |
2857 | |
| 2858 | 2858 | /*!< SWJ_CFG configuration */ |
|
| 2859 | /*!< SWJ_CFG configuration */ |
2859 | #define AFIO_MAPR_SWJ_CFG_Pos (24U) |
| 2860 | #define AFIO_MAPR_SWJ_CFG_Pos (24U) |
2860 | #define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ |
| 2861 | #define AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x07000000 */ |
2861 | #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ |
| 2862 | #define AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk /*!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ |
2862 | #define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ |
| 2863 | #define AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x01000000 */ |
2863 | #define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ |
| 2864 | #define AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x02000000 */ |
2864 | #define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ |
| 2865 | #define AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos) /*!< 0x04000000 */ |
2865 | |
| 2866 | 2866 | #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ |
|
| 2867 | #define AFIO_MAPR_SWJ_CFG_RESET 0x00000000U /*!< Full SWJ (JTAG-DP + SW-DP) : Reset State */ |
2867 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) |
| 2868 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U) |
2868 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ |
| 2869 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos) /*!< 0x01000000 */ |
2869 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ |
| 2870 | #define AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk /*!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ |
2870 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) |
| 2871 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U) |
2871 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ |
| 2872 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos) /*!< 0x02000000 */ |
2872 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ |
| 2873 | #define AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Enabled */ |
2873 | #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) |
| 2874 | #define AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U) |
2874 | #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ |
| 2875 | #define AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos) /*!< 0x04000000 */ |
2875 | #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ |
| 2876 | #define AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk /*!< JTAG-DP Disabled and SW-DP Disabled */ |
2876 | |
| 2877 | 2877 | /*!< ETH_REMAP configuration */ |
|
| 2878 | /*!< ETH_REMAP configuration */ |
2878 | #define AFIO_MAPR_ETH_REMAP_Pos (21U) |
| 2879 | #define AFIO_MAPR_ETH_REMAP_Pos (21U) |
2879 | #define AFIO_MAPR_ETH_REMAP_Msk (0x1UL << AFIO_MAPR_ETH_REMAP_Pos) /*!< 0x00200000 */ |
| 2880 | #define AFIO_MAPR_ETH_REMAP_Msk (0x1UL << AFIO_MAPR_ETH_REMAP_Pos) /*!< 0x00200000 */ |
2880 | #define AFIO_MAPR_ETH_REMAP AFIO_MAPR_ETH_REMAP_Msk /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ |
| 2881 | #define AFIO_MAPR_ETH_REMAP AFIO_MAPR_ETH_REMAP_Msk /*!< SPI3_REMAP bit (Ethernet MAC I/O remapping) */ |
2881 | |
| 2882 | 2882 | /*!< CAN2_REMAP configuration */ |
|
| 2883 | /*!< CAN2_REMAP configuration */ |
2883 | #define AFIO_MAPR_CAN2_REMAP_Pos (22U) |
| 2884 | #define AFIO_MAPR_CAN2_REMAP_Pos (22U) |
2884 | #define AFIO_MAPR_CAN2_REMAP_Msk (0x1UL << AFIO_MAPR_CAN2_REMAP_Pos) /*!< 0x00400000 */ |
| 2885 | #define AFIO_MAPR_CAN2_REMAP_Msk (0x1UL << AFIO_MAPR_CAN2_REMAP_Pos) /*!< 0x00400000 */ |
2885 | #define AFIO_MAPR_CAN2_REMAP AFIO_MAPR_CAN2_REMAP_Msk /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ |
| 2886 | #define AFIO_MAPR_CAN2_REMAP AFIO_MAPR_CAN2_REMAP_Msk /*!< CAN2_REMAP bit (CAN2 I/O remapping) */ |
2886 | |
| 2887 | 2887 | /*!< MII_RMII_SEL configuration */ |
|
| 2888 | /*!< MII_RMII_SEL configuration */ |
2888 | #define AFIO_MAPR_MII_RMII_SEL_Pos (23U) |
| 2889 | #define AFIO_MAPR_MII_RMII_SEL_Pos (23U) |
2889 | #define AFIO_MAPR_MII_RMII_SEL_Msk (0x1UL << AFIO_MAPR_MII_RMII_SEL_Pos) /*!< 0x00800000 */ |
| 2890 | #define AFIO_MAPR_MII_RMII_SEL_Msk (0x1UL << AFIO_MAPR_MII_RMII_SEL_Pos) /*!< 0x00800000 */ |
2890 | #define AFIO_MAPR_MII_RMII_SEL AFIO_MAPR_MII_RMII_SEL_Msk /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ |
| 2891 | #define AFIO_MAPR_MII_RMII_SEL AFIO_MAPR_MII_RMII_SEL_Msk /*!< MII_RMII_SEL bit (Ethernet MII or RMII selection) */ |
2891 | |
| 2892 | 2892 | /*!< SPI3_REMAP configuration */ |
|
| 2893 | /*!< SPI3_REMAP configuration */ |
2893 | #define AFIO_MAPR_SPI3_REMAP_Pos (28U) |
| 2894 | #define AFIO_MAPR_SPI3_REMAP_Pos (28U) |
2894 | #define AFIO_MAPR_SPI3_REMAP_Msk (0x1UL << AFIO_MAPR_SPI3_REMAP_Pos) /*!< 0x10000000 */ |
| 2895 | #define AFIO_MAPR_SPI3_REMAP_Msk (0x1UL << AFIO_MAPR_SPI3_REMAP_Pos) /*!< 0x10000000 */ |
2895 | #define AFIO_MAPR_SPI3_REMAP AFIO_MAPR_SPI3_REMAP_Msk /*!< SPI3_REMAP bit (SPI3 remapping) */ |
| 2896 | #define AFIO_MAPR_SPI3_REMAP AFIO_MAPR_SPI3_REMAP_Msk /*!< SPI3_REMAP bit (SPI3 remapping) */ |
2896 | |
| 2897 | 2897 | /*!< TIM2ITR1_IREMAP configuration */ |
|
| 2898 | /*!< TIM2ITR1_IREMAP configuration */ |
2898 | #define AFIO_MAPR_TIM2ITR1_IREMAP_Pos (29U) |
| 2899 | #define AFIO_MAPR_TIM2ITR1_IREMAP_Pos (29U) |
2899 | #define AFIO_MAPR_TIM2ITR1_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM2ITR1_IREMAP_Pos) /*!< 0x20000000 */ |
| 2900 | #define AFIO_MAPR_TIM2ITR1_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM2ITR1_IREMAP_Pos) /*!< 0x20000000 */ |
2900 | #define AFIO_MAPR_TIM2ITR1_IREMAP AFIO_MAPR_TIM2ITR1_IREMAP_Msk /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ |
| 2901 | #define AFIO_MAPR_TIM2ITR1_IREMAP AFIO_MAPR_TIM2ITR1_IREMAP_Msk /*!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) */ |
2901 | |
| 2902 | 2902 | /*!< PTP_PPS_REMAP configuration */ |
|
| 2903 | /*!< PTP_PPS_REMAP configuration */ |
2903 | #define AFIO_MAPR_PTP_PPS_REMAP_Pos (30U) |
| 2904 | #define AFIO_MAPR_PTP_PPS_REMAP_Pos (30U) |
2904 | #define AFIO_MAPR_PTP_PPS_REMAP_Msk (0x1UL << AFIO_MAPR_PTP_PPS_REMAP_Pos) /*!< 0x40000000 */ |
| 2905 | #define AFIO_MAPR_PTP_PPS_REMAP_Msk (0x1UL << AFIO_MAPR_PTP_PPS_REMAP_Pos) /*!< 0x40000000 */ |
2905 | #define AFIO_MAPR_PTP_PPS_REMAP AFIO_MAPR_PTP_PPS_REMAP_Msk /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ |
| 2906 | #define AFIO_MAPR_PTP_PPS_REMAP AFIO_MAPR_PTP_PPS_REMAP_Msk /*!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) */ |
2906 | |
| 2907 | 2907 | /***************** Bit definition for AFIO_EXTICR1 register *****************/ |
|
| 2908 | /***************** Bit definition for AFIO_EXTICR1 register *****************/ |
2908 | #define AFIO_EXTICR1_EXTI0_Pos (0U) |
| 2909 | #define AFIO_EXTICR1_EXTI0_Pos (0U) |
2909 | #define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ |
| 2910 | #define AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */ |
2910 | #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ |
| 2911 | #define AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */ |
2911 | #define AFIO_EXTICR1_EXTI1_Pos (4U) |
| 2912 | #define AFIO_EXTICR1_EXTI1_Pos (4U) |
2912 | #define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ |
| 2913 | #define AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */ |
2913 | #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ |
| 2914 | #define AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */ |
2914 | #define AFIO_EXTICR1_EXTI2_Pos (8U) |
| 2915 | #define AFIO_EXTICR1_EXTI2_Pos (8U) |
2915 | #define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ |
| 2916 | #define AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */ |
2916 | #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ |
| 2917 | #define AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */ |
2917 | #define AFIO_EXTICR1_EXTI3_Pos (12U) |
| 2918 | #define AFIO_EXTICR1_EXTI3_Pos (12U) |
2918 | #define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ |
| 2919 | #define AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */ |
2919 | #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ |
| 2920 | #define AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */ |
2920 | |
| 2921 | 2921 | /*!< EXTI0 configuration */ |
|
| 2922 | /*!< EXTI0 configuration */ |
2922 | #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ |
| 2923 | #define AFIO_EXTICR1_EXTI0_PA 0x00000000U /*!< PA[0] pin */ |
2923 | #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) |
| 2924 | #define AFIO_EXTICR1_EXTI0_PB_Pos (0U) |
2924 | #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ |
| 2925 | #define AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos) /*!< 0x00000001 */ |
2925 | #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ |
| 2926 | #define AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk /*!< PB[0] pin */ |
2926 | #define AFIO_EXTICR1_EXTI0_PC_Pos (1U) |
| 2927 | #define AFIO_EXTICR1_EXTI0_PC_Pos (1U) |
2927 | #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ |
| 2928 | #define AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos) /*!< 0x00000002 */ |
2928 | #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ |
| 2929 | #define AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk /*!< PC[0] pin */ |
2929 | #define AFIO_EXTICR1_EXTI0_PD_Pos (0U) |
| 2930 | #define AFIO_EXTICR1_EXTI0_PD_Pos (0U) |
2930 | #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ |
| 2931 | #define AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos) /*!< 0x00000003 */ |
2931 | #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ |
| 2932 | #define AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk /*!< PD[0] pin */ |
2932 | #define AFIO_EXTICR1_EXTI0_PE_Pos (2U) |
| 2933 | #define AFIO_EXTICR1_EXTI0_PE_Pos (2U) |
2933 | #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ |
| 2934 | #define AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos) /*!< 0x00000004 */ |
2934 | #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ |
| 2935 | #define AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk /*!< PE[0] pin */ |
2935 | #define AFIO_EXTICR1_EXTI0_PF_Pos (0U) |
| 2936 | #define AFIO_EXTICR1_EXTI0_PF_Pos (0U) |
2936 | #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ |
| 2937 | #define AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos) /*!< 0x00000005 */ |
2937 | #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ |
| 2938 | #define AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk /*!< PF[0] pin */ |
2938 | #define AFIO_EXTICR1_EXTI0_PG_Pos (1U) |
| 2939 | #define AFIO_EXTICR1_EXTI0_PG_Pos (1U) |
2939 | #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ |
| 2940 | #define AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos) /*!< 0x00000006 */ |
2940 | #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ |
| 2941 | #define AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk /*!< PG[0] pin */ |
2941 | |
| 2942 | 2942 | /*!< EXTI1 configuration */ |
|
| 2943 | /*!< EXTI1 configuration */ |
2943 | #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ |
| 2944 | #define AFIO_EXTICR1_EXTI1_PA 0x00000000U /*!< PA[1] pin */ |
2944 | #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) |
| 2945 | #define AFIO_EXTICR1_EXTI1_PB_Pos (4U) |
2945 | #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ |
| 2946 | #define AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos) /*!< 0x00000010 */ |
2946 | #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ |
| 2947 | #define AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk /*!< PB[1] pin */ |
2947 | #define AFIO_EXTICR1_EXTI1_PC_Pos (5U) |
| 2948 | #define AFIO_EXTICR1_EXTI1_PC_Pos (5U) |
2948 | #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ |
| 2949 | #define AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos) /*!< 0x00000020 */ |
2949 | #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ |
| 2950 | #define AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk /*!< PC[1] pin */ |
2950 | #define AFIO_EXTICR1_EXTI1_PD_Pos (4U) |
| 2951 | #define AFIO_EXTICR1_EXTI1_PD_Pos (4U) |
2951 | #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ |
| 2952 | #define AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos) /*!< 0x00000030 */ |
2952 | #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ |
| 2953 | #define AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk /*!< PD[1] pin */ |
2953 | #define AFIO_EXTICR1_EXTI1_PE_Pos (6U) |
| 2954 | #define AFIO_EXTICR1_EXTI1_PE_Pos (6U) |
2954 | #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ |
| 2955 | #define AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos) /*!< 0x00000040 */ |
2955 | #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ |
| 2956 | #define AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk /*!< PE[1] pin */ |
2956 | #define AFIO_EXTICR1_EXTI1_PF_Pos (4U) |
| 2957 | #define AFIO_EXTICR1_EXTI1_PF_Pos (4U) |
2957 | #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ |
| 2958 | #define AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos) /*!< 0x00000050 */ |
2958 | #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ |
| 2959 | #define AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk /*!< PF[1] pin */ |
2959 | #define AFIO_EXTICR1_EXTI1_PG_Pos (5U) |
| 2960 | #define AFIO_EXTICR1_EXTI1_PG_Pos (5U) |
2960 | #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ |
| 2961 | #define AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos) /*!< 0x00000060 */ |
2961 | #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ |
| 2962 | #define AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk /*!< PG[1] pin */ |
2962 | |
| 2963 | 2963 | /*!< EXTI2 configuration */ |
|
| 2964 | /*!< EXTI2 configuration */ |
2964 | #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ |
| 2965 | #define AFIO_EXTICR1_EXTI2_PA 0x00000000U /*!< PA[2] pin */ |
2965 | #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) |
| 2966 | #define AFIO_EXTICR1_EXTI2_PB_Pos (8U) |
2966 | #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ |
| 2967 | #define AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos) /*!< 0x00000100 */ |
2967 | #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ |
| 2968 | #define AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk /*!< PB[2] pin */ |
2968 | #define AFIO_EXTICR1_EXTI2_PC_Pos (9U) |
| 2969 | #define AFIO_EXTICR1_EXTI2_PC_Pos (9U) |
2969 | #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ |
| 2970 | #define AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos) /*!< 0x00000200 */ |
2970 | #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ |
| 2971 | #define AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk /*!< PC[2] pin */ |
2971 | #define AFIO_EXTICR1_EXTI2_PD_Pos (8U) |
| 2972 | #define AFIO_EXTICR1_EXTI2_PD_Pos (8U) |
2972 | #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ |
| 2973 | #define AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos) /*!< 0x00000300 */ |
2973 | #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ |
| 2974 | #define AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk /*!< PD[2] pin */ |
2974 | #define AFIO_EXTICR1_EXTI2_PE_Pos (10U) |
| 2975 | #define AFIO_EXTICR1_EXTI2_PE_Pos (10U) |
2975 | #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ |
| 2976 | #define AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos) /*!< 0x00000400 */ |
2976 | #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ |
| 2977 | #define AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk /*!< PE[2] pin */ |
2977 | #define AFIO_EXTICR1_EXTI2_PF_Pos (8U) |
| 2978 | #define AFIO_EXTICR1_EXTI2_PF_Pos (8U) |
2978 | #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ |
| 2979 | #define AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos) /*!< 0x00000500 */ |
2979 | #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ |
| 2980 | #define AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk /*!< PF[2] pin */ |
2980 | #define AFIO_EXTICR1_EXTI2_PG_Pos (9U) |
| 2981 | #define AFIO_EXTICR1_EXTI2_PG_Pos (9U) |
2981 | #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ |
| 2982 | #define AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos) /*!< 0x00000600 */ |
2982 | #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ |
| 2983 | #define AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk /*!< PG[2] pin */ |
2983 | |
| 2984 | 2984 | /*!< EXTI3 configuration */ |
|
| 2985 | /*!< EXTI3 configuration */ |
2985 | #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ |
| 2986 | #define AFIO_EXTICR1_EXTI3_PA 0x00000000U /*!< PA[3] pin */ |
2986 | #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) |
| 2987 | #define AFIO_EXTICR1_EXTI3_PB_Pos (12U) |
2987 | #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ |
| 2988 | #define AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos) /*!< 0x00001000 */ |
2988 | #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ |
| 2989 | #define AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk /*!< PB[3] pin */ |
2989 | #define AFIO_EXTICR1_EXTI3_PC_Pos (13U) |
| 2990 | #define AFIO_EXTICR1_EXTI3_PC_Pos (13U) |
2990 | #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ |
| 2991 | #define AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos) /*!< 0x00002000 */ |
2991 | #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ |
| 2992 | #define AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk /*!< PC[3] pin */ |
2992 | #define AFIO_EXTICR1_EXTI3_PD_Pos (12U) |
| 2993 | #define AFIO_EXTICR1_EXTI3_PD_Pos (12U) |
2993 | #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ |
| 2994 | #define AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos) /*!< 0x00003000 */ |
2994 | #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ |
| 2995 | #define AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk /*!< PD[3] pin */ |
2995 | #define AFIO_EXTICR1_EXTI3_PE_Pos (14U) |
| 2996 | #define AFIO_EXTICR1_EXTI3_PE_Pos (14U) |
2996 | #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ |
| 2997 | #define AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos) /*!< 0x00004000 */ |
2997 | #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ |
| 2998 | #define AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk /*!< PE[3] pin */ |
2998 | #define AFIO_EXTICR1_EXTI3_PF_Pos (12U) |
| 2999 | #define AFIO_EXTICR1_EXTI3_PF_Pos (12U) |
2999 | #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ |
| 3000 | #define AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos) /*!< 0x00005000 */ |
3000 | #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ |
| 3001 | #define AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk /*!< PF[3] pin */ |
3001 | #define AFIO_EXTICR1_EXTI3_PG_Pos (13U) |
| 3002 | #define AFIO_EXTICR1_EXTI3_PG_Pos (13U) |
3002 | #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ |
| 3003 | #define AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos) /*!< 0x00006000 */ |
3003 | #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ |
| 3004 | #define AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk /*!< PG[3] pin */ |
3004 | |
| 3005 | 3005 | /***************** Bit definition for AFIO_EXTICR2 register *****************/ |
|
| 3006 | /***************** Bit definition for AFIO_EXTICR2 register *****************/ |
3006 | #define AFIO_EXTICR2_EXTI4_Pos (0U) |
| 3007 | #define AFIO_EXTICR2_EXTI4_Pos (0U) |
3007 | #define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
| 3008 | #define AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */ |
3008 | #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
| 3009 | #define AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */ |
3009 | #define AFIO_EXTICR2_EXTI5_Pos (4U) |
| 3010 | #define AFIO_EXTICR2_EXTI5_Pos (4U) |
3010 | #define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ |
| 3011 | #define AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */ |
3011 | #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ |
| 3012 | #define AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */ |
3012 | #define AFIO_EXTICR2_EXTI6_Pos (8U) |
| 3013 | #define AFIO_EXTICR2_EXTI6_Pos (8U) |
3013 | #define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ |
| 3014 | #define AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */ |
3014 | #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ |
| 3015 | #define AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */ |
3015 | #define AFIO_EXTICR2_EXTI7_Pos (12U) |
| 3016 | #define AFIO_EXTICR2_EXTI7_Pos (12U) |
3016 | #define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ |
| 3017 | #define AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */ |
3017 | #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ |
| 3018 | #define AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */ |
3018 | |
| 3019 | 3019 | /*!< EXTI4 configuration */ |
|
| 3020 | /*!< EXTI4 configuration */ |
3020 | #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ |
| 3021 | #define AFIO_EXTICR2_EXTI4_PA 0x00000000U /*!< PA[4] pin */ |
3021 | #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) |
| 3022 | #define AFIO_EXTICR2_EXTI4_PB_Pos (0U) |
3022 | #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ |
| 3023 | #define AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos) /*!< 0x00000001 */ |
3023 | #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ |
| 3024 | #define AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk /*!< PB[4] pin */ |
3024 | #define AFIO_EXTICR2_EXTI4_PC_Pos (1U) |
| 3025 | #define AFIO_EXTICR2_EXTI4_PC_Pos (1U) |
3025 | #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ |
| 3026 | #define AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos) /*!< 0x00000002 */ |
3026 | #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ |
| 3027 | #define AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk /*!< PC[4] pin */ |
3027 | #define AFIO_EXTICR2_EXTI4_PD_Pos (0U) |
| 3028 | #define AFIO_EXTICR2_EXTI4_PD_Pos (0U) |
3028 | #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ |
| 3029 | #define AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos) /*!< 0x00000003 */ |
3029 | #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ |
| 3030 | #define AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk /*!< PD[4] pin */ |
3030 | #define AFIO_EXTICR2_EXTI4_PE_Pos (2U) |
| 3031 | #define AFIO_EXTICR2_EXTI4_PE_Pos (2U) |
3031 | #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ |
| 3032 | #define AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos) /*!< 0x00000004 */ |
3032 | #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ |
| 3033 | #define AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk /*!< PE[4] pin */ |
3033 | #define AFIO_EXTICR2_EXTI4_PF_Pos (0U) |
| 3034 | #define AFIO_EXTICR2_EXTI4_PF_Pos (0U) |
3034 | #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ |
| 3035 | #define AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos) /*!< 0x00000005 */ |
3035 | #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ |
| 3036 | #define AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk /*!< PF[4] pin */ |
3036 | #define AFIO_EXTICR2_EXTI4_PG_Pos (1U) |
| 3037 | #define AFIO_EXTICR2_EXTI4_PG_Pos (1U) |
3037 | #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ |
| 3038 | #define AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos) /*!< 0x00000006 */ |
3038 | #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ |
| 3039 | #define AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk /*!< PG[4] pin */ |
3039 | |
| 3040 | 3040 | /* EXTI5 configuration */ |
|
| 3041 | /* EXTI5 configuration */ |
3041 | #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ |
| 3042 | #define AFIO_EXTICR2_EXTI5_PA 0x00000000U /*!< PA[5] pin */ |
3042 | #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) |
| 3043 | #define AFIO_EXTICR2_EXTI5_PB_Pos (4U) |
3043 | #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ |
| 3044 | #define AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos) /*!< 0x00000010 */ |
3044 | #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ |
| 3045 | #define AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk /*!< PB[5] pin */ |
3045 | #define AFIO_EXTICR2_EXTI5_PC_Pos (5U) |
| 3046 | #define AFIO_EXTICR2_EXTI5_PC_Pos (5U) |
3046 | #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ |
| 3047 | #define AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos) /*!< 0x00000020 */ |
3047 | #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ |
| 3048 | #define AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk /*!< PC[5] pin */ |
3048 | #define AFIO_EXTICR2_EXTI5_PD_Pos (4U) |
| 3049 | #define AFIO_EXTICR2_EXTI5_PD_Pos (4U) |
3049 | #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ |
| 3050 | #define AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos) /*!< 0x00000030 */ |
3050 | #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ |
| 3051 | #define AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk /*!< PD[5] pin */ |
3051 | #define AFIO_EXTICR2_EXTI5_PE_Pos (6U) |
| 3052 | #define AFIO_EXTICR2_EXTI5_PE_Pos (6U) |
3052 | #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ |
| 3053 | #define AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos) /*!< 0x00000040 */ |
3053 | #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ |
| 3054 | #define AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk /*!< PE[5] pin */ |
3054 | #define AFIO_EXTICR2_EXTI5_PF_Pos (4U) |
| 3055 | #define AFIO_EXTICR2_EXTI5_PF_Pos (4U) |
3055 | #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ |
| 3056 | #define AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos) /*!< 0x00000050 */ |
3056 | #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ |
| 3057 | #define AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk /*!< PF[5] pin */ |
3057 | #define AFIO_EXTICR2_EXTI5_PG_Pos (5U) |
| 3058 | #define AFIO_EXTICR2_EXTI5_PG_Pos (5U) |
3058 | #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ |
| 3059 | #define AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos) /*!< 0x00000060 */ |
3059 | #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ |
| 3060 | #define AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk /*!< PG[5] pin */ |
3060 | |
| 3061 | 3061 | /*!< EXTI6 configuration */ |
|
| 3062 | /*!< EXTI6 configuration */ |
3062 | #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ |
| 3063 | #define AFIO_EXTICR2_EXTI6_PA 0x00000000U /*!< PA[6] pin */ |
3063 | #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) |
| 3064 | #define AFIO_EXTICR2_EXTI6_PB_Pos (8U) |
3064 | #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ |
| 3065 | #define AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos) /*!< 0x00000100 */ |
3065 | #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ |
| 3066 | #define AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk /*!< PB[6] pin */ |
3066 | #define AFIO_EXTICR2_EXTI6_PC_Pos (9U) |
| 3067 | #define AFIO_EXTICR2_EXTI6_PC_Pos (9U) |
3067 | #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ |
| 3068 | #define AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos) /*!< 0x00000200 */ |
3068 | #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ |
| 3069 | #define AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk /*!< PC[6] pin */ |
3069 | #define AFIO_EXTICR2_EXTI6_PD_Pos (8U) |
| 3070 | #define AFIO_EXTICR2_EXTI6_PD_Pos (8U) |
3070 | #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ |
| 3071 | #define AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos) /*!< 0x00000300 */ |
3071 | #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ |
| 3072 | #define AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk /*!< PD[6] pin */ |
3072 | #define AFIO_EXTICR2_EXTI6_PE_Pos (10U) |
| 3073 | #define AFIO_EXTICR2_EXTI6_PE_Pos (10U) |
3073 | #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ |
| 3074 | #define AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos) /*!< 0x00000400 */ |
3074 | #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ |
| 3075 | #define AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk /*!< PE[6] pin */ |
3075 | #define AFIO_EXTICR2_EXTI6_PF_Pos (8U) |
| 3076 | #define AFIO_EXTICR2_EXTI6_PF_Pos (8U) |
3076 | #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ |
| 3077 | #define AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos) /*!< 0x00000500 */ |
3077 | #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ |
| 3078 | #define AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk /*!< PF[6] pin */ |
3078 | #define AFIO_EXTICR2_EXTI6_PG_Pos (9U) |
| 3079 | #define AFIO_EXTICR2_EXTI6_PG_Pos (9U) |
3079 | #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ |
| 3080 | #define AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos) /*!< 0x00000600 */ |
3080 | #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ |
| 3081 | #define AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk /*!< PG[6] pin */ |
3081 | |
| 3082 | 3082 | /*!< EXTI7 configuration */ |
|
| 3083 | /*!< EXTI7 configuration */ |
3083 | #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ |
| 3084 | #define AFIO_EXTICR2_EXTI7_PA 0x00000000U /*!< PA[7] pin */ |
3084 | #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) |
| 3085 | #define AFIO_EXTICR2_EXTI7_PB_Pos (12U) |
3085 | #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ |
| 3086 | #define AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos) /*!< 0x00001000 */ |
3086 | #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ |
| 3087 | #define AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk /*!< PB[7] pin */ |
3087 | #define AFIO_EXTICR2_EXTI7_PC_Pos (13U) |
| 3088 | #define AFIO_EXTICR2_EXTI7_PC_Pos (13U) |
3088 | #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ |
| 3089 | #define AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos) /*!< 0x00002000 */ |
3089 | #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ |
| 3090 | #define AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk /*!< PC[7] pin */ |
3090 | #define AFIO_EXTICR2_EXTI7_PD_Pos (12U) |
| 3091 | #define AFIO_EXTICR2_EXTI7_PD_Pos (12U) |
3091 | #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ |
| 3092 | #define AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos) /*!< 0x00003000 */ |
3092 | #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ |
| 3093 | #define AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk /*!< PD[7] pin */ |
3093 | #define AFIO_EXTICR2_EXTI7_PE_Pos (14U) |
| 3094 | #define AFIO_EXTICR2_EXTI7_PE_Pos (14U) |
3094 | #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ |
| 3095 | #define AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos) /*!< 0x00004000 */ |
3095 | #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ |
| 3096 | #define AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk /*!< PE[7] pin */ |
3096 | #define AFIO_EXTICR2_EXTI7_PF_Pos (12U) |
| 3097 | #define AFIO_EXTICR2_EXTI7_PF_Pos (12U) |
3097 | #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ |
| 3098 | #define AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos) /*!< 0x00005000 */ |
3098 | #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ |
| 3099 | #define AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk /*!< PF[7] pin */ |
3099 | #define AFIO_EXTICR2_EXTI7_PG_Pos (13U) |
| 3100 | #define AFIO_EXTICR2_EXTI7_PG_Pos (13U) |
3100 | #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ |
| 3101 | #define AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos) /*!< 0x00006000 */ |
3101 | #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ |
| 3102 | #define AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk /*!< PG[7] pin */ |
3102 | |
| 3103 | 3103 | /***************** Bit definition for AFIO_EXTICR3 register *****************/ |
|
| 3104 | /***************** Bit definition for AFIO_EXTICR3 register *****************/ |
3104 | #define AFIO_EXTICR3_EXTI8_Pos (0U) |
| 3105 | #define AFIO_EXTICR3_EXTI8_Pos (0U) |
3105 | #define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ |
| 3106 | #define AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */ |
3106 | #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ |
| 3107 | #define AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */ |
3107 | #define AFIO_EXTICR3_EXTI9_Pos (4U) |
| 3108 | #define AFIO_EXTICR3_EXTI9_Pos (4U) |
3108 | #define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ |
| 3109 | #define AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */ |
3109 | #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ |
| 3110 | #define AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */ |
3110 | #define AFIO_EXTICR3_EXTI10_Pos (8U) |
| 3111 | #define AFIO_EXTICR3_EXTI10_Pos (8U) |
3111 | #define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ |
| 3112 | #define AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */ |
3112 | #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ |
| 3113 | #define AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */ |
3113 | #define AFIO_EXTICR3_EXTI11_Pos (12U) |
| 3114 | #define AFIO_EXTICR3_EXTI11_Pos (12U) |
3114 | #define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ |
| 3115 | #define AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */ |
3115 | #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ |
| 3116 | #define AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */ |
3116 | |
| 3117 | 3117 | /*!< EXTI8 configuration */ |
|
| 3118 | /*!< EXTI8 configuration */ |
3118 | #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ |
| 3119 | #define AFIO_EXTICR3_EXTI8_PA 0x00000000U /*!< PA[8] pin */ |
3119 | #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) |
| 3120 | #define AFIO_EXTICR3_EXTI8_PB_Pos (0U) |
3120 | #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ |
| 3121 | #define AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos) /*!< 0x00000001 */ |
3121 | #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ |
| 3122 | #define AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk /*!< PB[8] pin */ |
3122 | #define AFIO_EXTICR3_EXTI8_PC_Pos (1U) |
| 3123 | #define AFIO_EXTICR3_EXTI8_PC_Pos (1U) |
3123 | #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ |
| 3124 | #define AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos) /*!< 0x00000002 */ |
3124 | #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ |
| 3125 | #define AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk /*!< PC[8] pin */ |
3125 | #define AFIO_EXTICR3_EXTI8_PD_Pos (0U) |
| 3126 | #define AFIO_EXTICR3_EXTI8_PD_Pos (0U) |
3126 | #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ |
| 3127 | #define AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos) /*!< 0x00000003 */ |
3127 | #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ |
| 3128 | #define AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk /*!< PD[8] pin */ |
3128 | #define AFIO_EXTICR3_EXTI8_PE_Pos (2U) |
| 3129 | #define AFIO_EXTICR3_EXTI8_PE_Pos (2U) |
3129 | #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ |
| 3130 | #define AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos) /*!< 0x00000004 */ |
3130 | #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ |
| 3131 | #define AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk /*!< PE[8] pin */ |
3131 | #define AFIO_EXTICR3_EXTI8_PF_Pos (0U) |
| 3132 | #define AFIO_EXTICR3_EXTI8_PF_Pos (0U) |
3132 | #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ |
| 3133 | #define AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos) /*!< 0x00000005 */ |
3133 | #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ |
| 3134 | #define AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk /*!< PF[8] pin */ |
3134 | #define AFIO_EXTICR3_EXTI8_PG_Pos (1U) |
| 3135 | #define AFIO_EXTICR3_EXTI8_PG_Pos (1U) |
3135 | #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ |
| 3136 | #define AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos) /*!< 0x00000006 */ |
3136 | #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ |
| 3137 | #define AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk /*!< PG[8] pin */ |
3137 | |
| 3138 | 3138 | /*!< EXTI9 configuration */ |
|
| 3139 | /*!< EXTI9 configuration */ |
3139 | #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ |
| 3140 | #define AFIO_EXTICR3_EXTI9_PA 0x00000000U /*!< PA[9] pin */ |
3140 | #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) |
| 3141 | #define AFIO_EXTICR3_EXTI9_PB_Pos (4U) |
3141 | #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ |
| 3142 | #define AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos) /*!< 0x00000010 */ |
3142 | #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ |
| 3143 | #define AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk /*!< PB[9] pin */ |
3143 | #define AFIO_EXTICR3_EXTI9_PC_Pos (5U) |
| 3144 | #define AFIO_EXTICR3_EXTI9_PC_Pos (5U) |
3144 | #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ |
| 3145 | #define AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos) /*!< 0x00000020 */ |
3145 | #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ |
| 3146 | #define AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk /*!< PC[9] pin */ |
3146 | #define AFIO_EXTICR3_EXTI9_PD_Pos (4U) |
| 3147 | #define AFIO_EXTICR3_EXTI9_PD_Pos (4U) |
3147 | #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ |
| 3148 | #define AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos) /*!< 0x00000030 */ |
3148 | #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ |
| 3149 | #define AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk /*!< PD[9] pin */ |
3149 | #define AFIO_EXTICR3_EXTI9_PE_Pos (6U) |
| 3150 | #define AFIO_EXTICR3_EXTI9_PE_Pos (6U) |
3150 | #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ |
| 3151 | #define AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos) /*!< 0x00000040 */ |
3151 | #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ |
| 3152 | #define AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk /*!< PE[9] pin */ |
3152 | #define AFIO_EXTICR3_EXTI9_PF_Pos (4U) |
| 3153 | #define AFIO_EXTICR3_EXTI9_PF_Pos (4U) |
3153 | #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ |
| 3154 | #define AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos) /*!< 0x00000050 */ |
3154 | #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ |
| 3155 | #define AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk /*!< PF[9] pin */ |
3155 | #define AFIO_EXTICR3_EXTI9_PG_Pos (5U) |
| 3156 | #define AFIO_EXTICR3_EXTI9_PG_Pos (5U) |
3156 | #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ |
| 3157 | #define AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos) /*!< 0x00000060 */ |
3157 | #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ |
| 3158 | #define AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk /*!< PG[9] pin */ |
3158 | |
| 3159 | 3159 | /*!< EXTI10 configuration */ |
|
| 3160 | /*!< EXTI10 configuration */ |
3160 | #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ |
| 3161 | #define AFIO_EXTICR3_EXTI10_PA 0x00000000U /*!< PA[10] pin */ |
3161 | #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) |
| 3162 | #define AFIO_EXTICR3_EXTI10_PB_Pos (8U) |
3162 | #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ |
| 3163 | #define AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos) /*!< 0x00000100 */ |
3163 | #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ |
| 3164 | #define AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk /*!< PB[10] pin */ |
3164 | #define AFIO_EXTICR3_EXTI10_PC_Pos (9U) |
| 3165 | #define AFIO_EXTICR3_EXTI10_PC_Pos (9U) |
3165 | #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ |
| 3166 | #define AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos) /*!< 0x00000200 */ |
3166 | #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ |
| 3167 | #define AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk /*!< PC[10] pin */ |
3167 | #define AFIO_EXTICR3_EXTI10_PD_Pos (8U) |
| 3168 | #define AFIO_EXTICR3_EXTI10_PD_Pos (8U) |
3168 | #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ |
| 3169 | #define AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos) /*!< 0x00000300 */ |
3169 | #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ |
| 3170 | #define AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk /*!< PD[10] pin */ |
3170 | #define AFIO_EXTICR3_EXTI10_PE_Pos (10U) |
| 3171 | #define AFIO_EXTICR3_EXTI10_PE_Pos (10U) |
3171 | #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ |
| 3172 | #define AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos) /*!< 0x00000400 */ |
3172 | #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ |
| 3173 | #define AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk /*!< PE[10] pin */ |
3173 | #define AFIO_EXTICR3_EXTI10_PF_Pos (8U) |
| 3174 | #define AFIO_EXTICR3_EXTI10_PF_Pos (8U) |
3174 | #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ |
| 3175 | #define AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos) /*!< 0x00000500 */ |
3175 | #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ |
| 3176 | #define AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk /*!< PF[10] pin */ |
3176 | #define AFIO_EXTICR3_EXTI10_PG_Pos (9U) |
| 3177 | #define AFIO_EXTICR3_EXTI10_PG_Pos (9U) |
3177 | #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ |
| 3178 | #define AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos) /*!< 0x00000600 */ |
3178 | #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ |
| 3179 | #define AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk /*!< PG[10] pin */ |
3179 | |
| 3180 | 3180 | /*!< EXTI11 configuration */ |
|
| 3181 | /*!< EXTI11 configuration */ |
3181 | #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ |
| 3182 | #define AFIO_EXTICR3_EXTI11_PA 0x00000000U /*!< PA[11] pin */ |
3182 | #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) |
| 3183 | #define AFIO_EXTICR3_EXTI11_PB_Pos (12U) |
3183 | #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ |
| 3184 | #define AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos) /*!< 0x00001000 */ |
3184 | #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ |
| 3185 | #define AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk /*!< PB[11] pin */ |
3185 | #define AFIO_EXTICR3_EXTI11_PC_Pos (13U) |
| 3186 | #define AFIO_EXTICR3_EXTI11_PC_Pos (13U) |
3186 | #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ |
| 3187 | #define AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos) /*!< 0x00002000 */ |
3187 | #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ |
| 3188 | #define AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk /*!< PC[11] pin */ |
3188 | #define AFIO_EXTICR3_EXTI11_PD_Pos (12U) |
| 3189 | #define AFIO_EXTICR3_EXTI11_PD_Pos (12U) |
3189 | #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ |
| 3190 | #define AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos) /*!< 0x00003000 */ |
3190 | #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ |
| 3191 | #define AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk /*!< PD[11] pin */ |
3191 | #define AFIO_EXTICR3_EXTI11_PE_Pos (14U) |
| 3192 | #define AFIO_EXTICR3_EXTI11_PE_Pos (14U) |
3192 | #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ |
| 3193 | #define AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos) /*!< 0x00004000 */ |
3193 | #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ |
| 3194 | #define AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk /*!< PE[11] pin */ |
3194 | #define AFIO_EXTICR3_EXTI11_PF_Pos (12U) |
| 3195 | #define AFIO_EXTICR3_EXTI11_PF_Pos (12U) |
3195 | #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ |
| 3196 | #define AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos) /*!< 0x00005000 */ |
3196 | #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ |
| 3197 | #define AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk /*!< PF[11] pin */ |
3197 | #define AFIO_EXTICR3_EXTI11_PG_Pos (13U) |
| 3198 | #define AFIO_EXTICR3_EXTI11_PG_Pos (13U) |
3198 | #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ |
| 3199 | #define AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos) /*!< 0x00006000 */ |
3199 | #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ |
| 3200 | #define AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk /*!< PG[11] pin */ |
3200 | |
| 3201 | 3201 | /***************** Bit definition for AFIO_EXTICR4 register *****************/ |
|
| 3202 | /***************** Bit definition for AFIO_EXTICR4 register *****************/ |
3202 | #define AFIO_EXTICR4_EXTI12_Pos (0U) |
| 3203 | #define AFIO_EXTICR4_EXTI12_Pos (0U) |
3203 | #define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ |
| 3204 | #define AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */ |
3204 | #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ |
| 3205 | #define AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */ |
3205 | #define AFIO_EXTICR4_EXTI13_Pos (4U) |
| 3206 | #define AFIO_EXTICR4_EXTI13_Pos (4U) |
3206 | #define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ |
| 3207 | #define AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */ |
3207 | #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ |
| 3208 | #define AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */ |
3208 | #define AFIO_EXTICR4_EXTI14_Pos (8U) |
| 3209 | #define AFIO_EXTICR4_EXTI14_Pos (8U) |
3209 | #define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ |
| 3210 | #define AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */ |
3210 | #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ |
| 3211 | #define AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */ |
3211 | #define AFIO_EXTICR4_EXTI15_Pos (12U) |
| 3212 | #define AFIO_EXTICR4_EXTI15_Pos (12U) |
3212 | #define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ |
| 3213 | #define AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */ |
3213 | #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ |
| 3214 | #define AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */ |
3214 | |
| 3215 | 3215 | /* EXTI12 configuration */ |
|
| 3216 | /* EXTI12 configuration */ |
3216 | #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ |
| 3217 | #define AFIO_EXTICR4_EXTI12_PA 0x00000000U /*!< PA[12] pin */ |
3217 | #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) |
| 3218 | #define AFIO_EXTICR4_EXTI12_PB_Pos (0U) |
3218 | #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ |
| 3219 | #define AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos) /*!< 0x00000001 */ |
3219 | #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ |
| 3220 | #define AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk /*!< PB[12] pin */ |
3220 | #define AFIO_EXTICR4_EXTI12_PC_Pos (1U) |
| 3221 | #define AFIO_EXTICR4_EXTI12_PC_Pos (1U) |
3221 | #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ |
| 3222 | #define AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos) /*!< 0x00000002 */ |
3222 | #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ |
| 3223 | #define AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk /*!< PC[12] pin */ |
3223 | #define AFIO_EXTICR4_EXTI12_PD_Pos (0U) |
| 3224 | #define AFIO_EXTICR4_EXTI12_PD_Pos (0U) |
3224 | #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ |
| 3225 | #define AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos) /*!< 0x00000003 */ |
3225 | #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ |
| 3226 | #define AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk /*!< PD[12] pin */ |
3226 | #define AFIO_EXTICR4_EXTI12_PE_Pos (2U) |
| 3227 | #define AFIO_EXTICR4_EXTI12_PE_Pos (2U) |
3227 | #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ |
| 3228 | #define AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos) /*!< 0x00000004 */ |
3228 | #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ |
| 3229 | #define AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk /*!< PE[12] pin */ |
3229 | #define AFIO_EXTICR4_EXTI12_PF_Pos (0U) |
| 3230 | #define AFIO_EXTICR4_EXTI12_PF_Pos (0U) |
3230 | #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ |
| 3231 | #define AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos) /*!< 0x00000005 */ |
3231 | #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ |
| 3232 | #define AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk /*!< PF[12] pin */ |
3232 | #define AFIO_EXTICR4_EXTI12_PG_Pos (1U) |
| 3233 | #define AFIO_EXTICR4_EXTI12_PG_Pos (1U) |
3233 | #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ |
| 3234 | #define AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos) /*!< 0x00000006 */ |
3234 | #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ |
| 3235 | #define AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk /*!< PG[12] pin */ |
3235 | |
| 3236 | 3236 | /* EXTI13 configuration */ |
|
| 3237 | /* EXTI13 configuration */ |
3237 | #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ |
| 3238 | #define AFIO_EXTICR4_EXTI13_PA 0x00000000U /*!< PA[13] pin */ |
3238 | #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) |
| 3239 | #define AFIO_EXTICR4_EXTI13_PB_Pos (4U) |
3239 | #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ |
| 3240 | #define AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos) /*!< 0x00000010 */ |
3240 | #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ |
| 3241 | #define AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk /*!< PB[13] pin */ |
3241 | #define AFIO_EXTICR4_EXTI13_PC_Pos (5U) |
| 3242 | #define AFIO_EXTICR4_EXTI13_PC_Pos (5U) |
3242 | #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ |
| 3243 | #define AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos) /*!< 0x00000020 */ |
3243 | #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ |
| 3244 | #define AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk /*!< PC[13] pin */ |
3244 | #define AFIO_EXTICR4_EXTI13_PD_Pos (4U) |
| 3245 | #define AFIO_EXTICR4_EXTI13_PD_Pos (4U) |
3245 | #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ |
| 3246 | #define AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos) /*!< 0x00000030 */ |
3246 | #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ |
| 3247 | #define AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk /*!< PD[13] pin */ |
3247 | #define AFIO_EXTICR4_EXTI13_PE_Pos (6U) |
| 3248 | #define AFIO_EXTICR4_EXTI13_PE_Pos (6U) |
3248 | #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ |
| 3249 | #define AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos) /*!< 0x00000040 */ |
3249 | #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ |
| 3250 | #define AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk /*!< PE[13] pin */ |
3250 | #define AFIO_EXTICR4_EXTI13_PF_Pos (4U) |
| 3251 | #define AFIO_EXTICR4_EXTI13_PF_Pos (4U) |
3251 | #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ |
| 3252 | #define AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos) /*!< 0x00000050 */ |
3252 | #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ |
| 3253 | #define AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk /*!< PF[13] pin */ |
3253 | #define AFIO_EXTICR4_EXTI13_PG_Pos (5U) |
| 3254 | #define AFIO_EXTICR4_EXTI13_PG_Pos (5U) |
3254 | #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ |
| 3255 | #define AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos) /*!< 0x00000060 */ |
3255 | #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ |
| 3256 | #define AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk /*!< PG[13] pin */ |
3256 | |
| 3257 | 3257 | /*!< EXTI14 configuration */ |
|
| 3258 | /*!< EXTI14 configuration */ |
3258 | #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ |
| 3259 | #define AFIO_EXTICR4_EXTI14_PA 0x00000000U /*!< PA[14] pin */ |
3259 | #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) |
| 3260 | #define AFIO_EXTICR4_EXTI14_PB_Pos (8U) |
3260 | #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ |
| 3261 | #define AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos) /*!< 0x00000100 */ |
3261 | #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ |
| 3262 | #define AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk /*!< PB[14] pin */ |
3262 | #define AFIO_EXTICR4_EXTI14_PC_Pos (9U) |
| 3263 | #define AFIO_EXTICR4_EXTI14_PC_Pos (9U) |
3263 | #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ |
| 3264 | #define AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos) /*!< 0x00000200 */ |
3264 | #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ |
| 3265 | #define AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk /*!< PC[14] pin */ |
3265 | #define AFIO_EXTICR4_EXTI14_PD_Pos (8U) |
| 3266 | #define AFIO_EXTICR4_EXTI14_PD_Pos (8U) |
3266 | #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ |
| 3267 | #define AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos) /*!< 0x00000300 */ |
3267 | #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ |
| 3268 | #define AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk /*!< PD[14] pin */ |
3268 | #define AFIO_EXTICR4_EXTI14_PE_Pos (10U) |
| 3269 | #define AFIO_EXTICR4_EXTI14_PE_Pos (10U) |
3269 | #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ |
| 3270 | #define AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos) /*!< 0x00000400 */ |
3270 | #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ |
| 3271 | #define AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk /*!< PE[14] pin */ |
3271 | #define AFIO_EXTICR4_EXTI14_PF_Pos (8U) |
| 3272 | #define AFIO_EXTICR4_EXTI14_PF_Pos (8U) |
3272 | #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ |
| 3273 | #define AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos) /*!< 0x00000500 */ |
3273 | #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ |
| 3274 | #define AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk /*!< PF[14] pin */ |
3274 | #define AFIO_EXTICR4_EXTI14_PG_Pos (9U) |
| 3275 | #define AFIO_EXTICR4_EXTI14_PG_Pos (9U) |
3275 | #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ |
| 3276 | #define AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos) /*!< 0x00000600 */ |
3276 | #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ |
| 3277 | #define AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk /*!< PG[14] pin */ |
3277 | |
| 3278 | 3278 | /*!< EXTI15 configuration */ |
|
| 3279 | /*!< EXTI15 configuration */ |
3279 | #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ |
| 3280 | #define AFIO_EXTICR4_EXTI15_PA 0x00000000U /*!< PA[15] pin */ |
3280 | #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) |
| 3281 | #define AFIO_EXTICR4_EXTI15_PB_Pos (12U) |
3281 | #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ |
| 3282 | #define AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos) /*!< 0x00001000 */ |
3282 | #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ |
| 3283 | #define AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk /*!< PB[15] pin */ |
3283 | #define AFIO_EXTICR4_EXTI15_PC_Pos (13U) |
| 3284 | #define AFIO_EXTICR4_EXTI15_PC_Pos (13U) |
3284 | #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ |
| 3285 | #define AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos) /*!< 0x00002000 */ |
3285 | #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ |
| 3286 | #define AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk /*!< PC[15] pin */ |
3286 | #define AFIO_EXTICR4_EXTI15_PD_Pos (12U) |
| 3287 | #define AFIO_EXTICR4_EXTI15_PD_Pos (12U) |
3287 | #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ |
| 3288 | #define AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos) /*!< 0x00003000 */ |
3288 | #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ |
| 3289 | #define AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk /*!< PD[15] pin */ |
3289 | #define AFIO_EXTICR4_EXTI15_PE_Pos (14U) |
| 3290 | #define AFIO_EXTICR4_EXTI15_PE_Pos (14U) |
3290 | #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ |
| 3291 | #define AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos) /*!< 0x00004000 */ |
3291 | #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ |
| 3292 | #define AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk /*!< PE[15] pin */ |
3292 | #define AFIO_EXTICR4_EXTI15_PF_Pos (12U) |
| 3293 | #define AFIO_EXTICR4_EXTI15_PF_Pos (12U) |
3293 | #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ |
| 3294 | #define AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos) /*!< 0x00005000 */ |
3294 | #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ |
| 3295 | #define AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk /*!< PF[15] pin */ |
3295 | #define AFIO_EXTICR4_EXTI15_PG_Pos (13U) |
| 3296 | #define AFIO_EXTICR4_EXTI15_PG_Pos (13U) |
3296 | #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ |
| 3297 | #define AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos) /*!< 0x00006000 */ |
3297 | #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ |
| 3298 | #define AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk /*!< PG[15] pin */ |
3298 | |
| 3299 | 3299 | /****************** Bit definition for AFIO_MAPR2 register ******************/ |
|
| 3300 | /****************** Bit definition for AFIO_MAPR2 register ******************/ |
3300 | |
| 3301 | 3301 | ||
| 3302 | 3302 | ||
| 3303 | 3303 | /******************************************************************************/ |
|
| 3304 | /******************************************************************************/ |
3304 | /* */ |
| 3305 | /* */ |
3305 | /* External Interrupt/Event Controller */ |
| 3306 | /* External Interrupt/Event Controller */ |
3306 | /* */ |
| 3307 | /* */ |
3307 | /******************************************************************************/ |
| 3308 | /******************************************************************************/ |
3308 | |
| 3309 | 3309 | /******************* Bit definition for EXTI_IMR register *******************/ |
|
| 3310 | /******************* Bit definition for EXTI_IMR register *******************/ |
3310 | #define EXTI_IMR_MR0_Pos (0U) |
| 3311 | #define EXTI_IMR_MR0_Pos (0U) |
3311 | #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ |
| 3312 | #define EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */ |
3312 | #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ |
| 3313 | #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */ |
3313 | #define EXTI_IMR_MR1_Pos (1U) |
| 3314 | #define EXTI_IMR_MR1_Pos (1U) |
3314 | #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ |
| 3315 | #define EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */ |
3315 | #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ |
| 3316 | #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */ |
3316 | #define EXTI_IMR_MR2_Pos (2U) |
| 3317 | #define EXTI_IMR_MR2_Pos (2U) |
3317 | #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ |
| 3318 | #define EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */ |
3318 | #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ |
| 3319 | #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */ |
3319 | #define EXTI_IMR_MR3_Pos (3U) |
| 3320 | #define EXTI_IMR_MR3_Pos (3U) |
3320 | #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ |
| 3321 | #define EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */ |
3321 | #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ |
| 3322 | #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */ |
3322 | #define EXTI_IMR_MR4_Pos (4U) |
| 3323 | #define EXTI_IMR_MR4_Pos (4U) |
3323 | #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ |
| 3324 | #define EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */ |
3324 | #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ |
| 3325 | #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */ |
3325 | #define EXTI_IMR_MR5_Pos (5U) |
| 3326 | #define EXTI_IMR_MR5_Pos (5U) |
3326 | #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ |
| 3327 | #define EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */ |
3327 | #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ |
| 3328 | #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */ |
3328 | #define EXTI_IMR_MR6_Pos (6U) |
| 3329 | #define EXTI_IMR_MR6_Pos (6U) |
3329 | #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ |
| 3330 | #define EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */ |
3330 | #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ |
| 3331 | #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */ |
3331 | #define EXTI_IMR_MR7_Pos (7U) |
| 3332 | #define EXTI_IMR_MR7_Pos (7U) |
3332 | #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ |
| 3333 | #define EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */ |
3333 | #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ |
| 3334 | #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */ |
3334 | #define EXTI_IMR_MR8_Pos (8U) |
| 3335 | #define EXTI_IMR_MR8_Pos (8U) |
3335 | #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ |
| 3336 | #define EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */ |
3336 | #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ |
| 3337 | #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */ |
3337 | #define EXTI_IMR_MR9_Pos (9U) |
| 3338 | #define EXTI_IMR_MR9_Pos (9U) |
3338 | #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ |
| 3339 | #define EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */ |
3339 | #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ |
| 3340 | #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */ |
3340 | #define EXTI_IMR_MR10_Pos (10U) |
| 3341 | #define EXTI_IMR_MR10_Pos (10U) |
3341 | #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ |
| 3342 | #define EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */ |
3342 | #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ |
| 3343 | #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */ |
3343 | #define EXTI_IMR_MR11_Pos (11U) |
| 3344 | #define EXTI_IMR_MR11_Pos (11U) |
3344 | #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ |
| 3345 | #define EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */ |
3345 | #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ |
| 3346 | #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */ |
3346 | #define EXTI_IMR_MR12_Pos (12U) |
| 3347 | #define EXTI_IMR_MR12_Pos (12U) |
3347 | #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ |
| 3348 | #define EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */ |
3348 | #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ |
| 3349 | #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */ |
3349 | #define EXTI_IMR_MR13_Pos (13U) |
| 3350 | #define EXTI_IMR_MR13_Pos (13U) |
3350 | #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ |
| 3351 | #define EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */ |
3351 | #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ |
| 3352 | #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */ |
3352 | #define EXTI_IMR_MR14_Pos (14U) |
| 3353 | #define EXTI_IMR_MR14_Pos (14U) |
3353 | #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ |
| 3354 | #define EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */ |
3354 | #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ |
| 3355 | #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */ |
3355 | #define EXTI_IMR_MR15_Pos (15U) |
| 3356 | #define EXTI_IMR_MR15_Pos (15U) |
3356 | #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ |
| 3357 | #define EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */ |
3357 | #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ |
| 3358 | #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */ |
3358 | #define EXTI_IMR_MR16_Pos (16U) |
| 3359 | #define EXTI_IMR_MR16_Pos (16U) |
3359 | #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ |
| 3360 | #define EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */ |
3360 | #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ |
| 3361 | #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */ |
3361 | #define EXTI_IMR_MR17_Pos (17U) |
| 3362 | #define EXTI_IMR_MR17_Pos (17U) |
3362 | #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ |
| 3363 | #define EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */ |
3363 | #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ |
| 3364 | #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */ |
3364 | #define EXTI_IMR_MR18_Pos (18U) |
| 3365 | #define EXTI_IMR_MR18_Pos (18U) |
3365 | #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ |
| 3366 | #define EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */ |
3366 | #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ |
| 3367 | #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */ |
3367 | #define EXTI_IMR_MR19_Pos (19U) |
| 3368 | #define EXTI_IMR_MR19_Pos (19U) |
3368 | #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ |
| 3369 | #define EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */ |
3369 | #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ |
| 3370 | #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */ |
3370 | |
| 3371 | 3371 | /* References Defines */ |
|
| 3372 | /* References Defines */ |
3372 | #define EXTI_IMR_IM0 EXTI_IMR_MR0 |
| 3373 | #define EXTI_IMR_IM0 EXTI_IMR_MR0 |
3373 | #define EXTI_IMR_IM1 EXTI_IMR_MR1 |
| 3374 | #define EXTI_IMR_IM1 EXTI_IMR_MR1 |
3374 | #define EXTI_IMR_IM2 EXTI_IMR_MR2 |
| 3375 | #define EXTI_IMR_IM2 EXTI_IMR_MR2 |
3375 | #define EXTI_IMR_IM3 EXTI_IMR_MR3 |
| 3376 | #define EXTI_IMR_IM3 EXTI_IMR_MR3 |
3376 | #define EXTI_IMR_IM4 EXTI_IMR_MR4 |
| 3377 | #define EXTI_IMR_IM4 EXTI_IMR_MR4 |
3377 | #define EXTI_IMR_IM5 EXTI_IMR_MR5 |
| 3378 | #define EXTI_IMR_IM5 EXTI_IMR_MR5 |
3378 | #define EXTI_IMR_IM6 EXTI_IMR_MR6 |
| 3379 | #define EXTI_IMR_IM6 EXTI_IMR_MR6 |
3379 | #define EXTI_IMR_IM7 EXTI_IMR_MR7 |
| 3380 | #define EXTI_IMR_IM7 EXTI_IMR_MR7 |
3380 | #define EXTI_IMR_IM8 EXTI_IMR_MR8 |
| 3381 | #define EXTI_IMR_IM8 EXTI_IMR_MR8 |
3381 | #define EXTI_IMR_IM9 EXTI_IMR_MR9 |
| 3382 | #define EXTI_IMR_IM9 EXTI_IMR_MR9 |
3382 | #define EXTI_IMR_IM10 EXTI_IMR_MR10 |
| 3383 | #define EXTI_IMR_IM10 EXTI_IMR_MR10 |
3383 | #define EXTI_IMR_IM11 EXTI_IMR_MR11 |
| 3384 | #define EXTI_IMR_IM11 EXTI_IMR_MR11 |
3384 | #define EXTI_IMR_IM12 EXTI_IMR_MR12 |
| 3385 | #define EXTI_IMR_IM12 EXTI_IMR_MR12 |
3385 | #define EXTI_IMR_IM13 EXTI_IMR_MR13 |
| 3386 | #define EXTI_IMR_IM13 EXTI_IMR_MR13 |
3386 | #define EXTI_IMR_IM14 EXTI_IMR_MR14 |
| 3387 | #define EXTI_IMR_IM14 EXTI_IMR_MR14 |
3387 | #define EXTI_IMR_IM15 EXTI_IMR_MR15 |
| 3388 | #define EXTI_IMR_IM15 EXTI_IMR_MR15 |
3388 | #define EXTI_IMR_IM16 EXTI_IMR_MR16 |
| 3389 | #define EXTI_IMR_IM16 EXTI_IMR_MR16 |
3389 | #define EXTI_IMR_IM17 EXTI_IMR_MR17 |
| 3390 | #define EXTI_IMR_IM17 EXTI_IMR_MR17 |
3390 | #define EXTI_IMR_IM18 EXTI_IMR_MR18 |
| 3391 | #define EXTI_IMR_IM18 EXTI_IMR_MR18 |
3391 | #define EXTI_IMR_IM19 EXTI_IMR_MR19 |
| 3392 | #define EXTI_IMR_IM19 EXTI_IMR_MR19 |
3392 | #define EXTI_IMR_IM 0x000FFFFFU /*!< Interrupt Mask All */ |
| 3393 | #define EXTI_IMR_IM 0x000FFFFFU /*!< Interrupt Mask All */ |
3393 | |
| 3394 | 3394 | /******************* Bit definition for EXTI_EMR register *******************/ |
|
| 3395 | /******************* Bit definition for EXTI_EMR register *******************/ |
3395 | #define EXTI_EMR_MR0_Pos (0U) |
| 3396 | #define EXTI_EMR_MR0_Pos (0U) |
3396 | #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ |
| 3397 | #define EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */ |
3397 | #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ |
| 3398 | #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */ |
3398 | #define EXTI_EMR_MR1_Pos (1U) |
| 3399 | #define EXTI_EMR_MR1_Pos (1U) |
3399 | #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ |
| 3400 | #define EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */ |
3400 | #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ |
| 3401 | #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */ |
3401 | #define EXTI_EMR_MR2_Pos (2U) |
| 3402 | #define EXTI_EMR_MR2_Pos (2U) |
3402 | #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ |
| 3403 | #define EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */ |
3403 | #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ |
| 3404 | #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */ |
3404 | #define EXTI_EMR_MR3_Pos (3U) |
| 3405 | #define EXTI_EMR_MR3_Pos (3U) |
3405 | #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ |
| 3406 | #define EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */ |
3406 | #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ |
| 3407 | #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */ |
3407 | #define EXTI_EMR_MR4_Pos (4U) |
| 3408 | #define EXTI_EMR_MR4_Pos (4U) |
3408 | #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ |
| 3409 | #define EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */ |
3409 | #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ |
| 3410 | #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */ |
3410 | #define EXTI_EMR_MR5_Pos (5U) |
| 3411 | #define EXTI_EMR_MR5_Pos (5U) |
3411 | #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ |
| 3412 | #define EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */ |
3412 | #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ |
| 3413 | #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */ |
3413 | #define EXTI_EMR_MR6_Pos (6U) |
| 3414 | #define EXTI_EMR_MR6_Pos (6U) |
3414 | #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ |
| 3415 | #define EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */ |
3415 | #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ |
| 3416 | #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */ |
3416 | #define EXTI_EMR_MR7_Pos (7U) |
| 3417 | #define EXTI_EMR_MR7_Pos (7U) |
3417 | #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ |
| 3418 | #define EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */ |
3418 | #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ |
| 3419 | #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */ |
3419 | #define EXTI_EMR_MR8_Pos (8U) |
| 3420 | #define EXTI_EMR_MR8_Pos (8U) |
3420 | #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ |
| 3421 | #define EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */ |
3421 | #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ |
| 3422 | #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */ |
3422 | #define EXTI_EMR_MR9_Pos (9U) |
| 3423 | #define EXTI_EMR_MR9_Pos (9U) |
3423 | #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ |
| 3424 | #define EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */ |
3424 | #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ |
| 3425 | #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */ |
3425 | #define EXTI_EMR_MR10_Pos (10U) |
| 3426 | #define EXTI_EMR_MR10_Pos (10U) |
3426 | #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ |
| 3427 | #define EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */ |
3427 | #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ |
| 3428 | #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */ |
3428 | #define EXTI_EMR_MR11_Pos (11U) |
| 3429 | #define EXTI_EMR_MR11_Pos (11U) |
3429 | #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ |
| 3430 | #define EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */ |
3430 | #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ |
| 3431 | #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */ |
3431 | #define EXTI_EMR_MR12_Pos (12U) |
| 3432 | #define EXTI_EMR_MR12_Pos (12U) |
3432 | #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ |
| 3433 | #define EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */ |
3433 | #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ |
| 3434 | #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */ |
3434 | #define EXTI_EMR_MR13_Pos (13U) |
| 3435 | #define EXTI_EMR_MR13_Pos (13U) |
3435 | #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ |
| 3436 | #define EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */ |
3436 | #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ |
| 3437 | #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */ |
3437 | #define EXTI_EMR_MR14_Pos (14U) |
| 3438 | #define EXTI_EMR_MR14_Pos (14U) |
3438 | #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ |
| 3439 | #define EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */ |
3439 | #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ |
| 3440 | #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */ |
3440 | #define EXTI_EMR_MR15_Pos (15U) |
| 3441 | #define EXTI_EMR_MR15_Pos (15U) |
3441 | #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ |
| 3442 | #define EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */ |
3442 | #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ |
| 3443 | #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */ |
3443 | #define EXTI_EMR_MR16_Pos (16U) |
| 3444 | #define EXTI_EMR_MR16_Pos (16U) |
3444 | #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ |
| 3445 | #define EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */ |
3445 | #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ |
| 3446 | #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */ |
3446 | #define EXTI_EMR_MR17_Pos (17U) |
| 3447 | #define EXTI_EMR_MR17_Pos (17U) |
3447 | #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ |
| 3448 | #define EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */ |
3448 | #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ |
| 3449 | #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */ |
3449 | #define EXTI_EMR_MR18_Pos (18U) |
| 3450 | #define EXTI_EMR_MR18_Pos (18U) |
3450 | #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ |
| 3451 | #define EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */ |
3451 | #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ |
| 3452 | #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */ |
3452 | #define EXTI_EMR_MR19_Pos (19U) |
| 3453 | #define EXTI_EMR_MR19_Pos (19U) |
3453 | #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ |
| 3454 | #define EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */ |
3454 | #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ |
| 3455 | #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */ |
3455 | |
| 3456 | 3456 | /* References Defines */ |
|
| 3457 | /* References Defines */ |
3457 | #define EXTI_EMR_EM0 EXTI_EMR_MR0 |
| 3458 | #define EXTI_EMR_EM0 EXTI_EMR_MR0 |
3458 | #define EXTI_EMR_EM1 EXTI_EMR_MR1 |
| 3459 | #define EXTI_EMR_EM1 EXTI_EMR_MR1 |
3459 | #define EXTI_EMR_EM2 EXTI_EMR_MR2 |
| 3460 | #define EXTI_EMR_EM2 EXTI_EMR_MR2 |
3460 | #define EXTI_EMR_EM3 EXTI_EMR_MR3 |
| 3461 | #define EXTI_EMR_EM3 EXTI_EMR_MR3 |
3461 | #define EXTI_EMR_EM4 EXTI_EMR_MR4 |
| 3462 | #define EXTI_EMR_EM4 EXTI_EMR_MR4 |
3462 | #define EXTI_EMR_EM5 EXTI_EMR_MR5 |
| 3463 | #define EXTI_EMR_EM5 EXTI_EMR_MR5 |
3463 | #define EXTI_EMR_EM6 EXTI_EMR_MR6 |
| 3464 | #define EXTI_EMR_EM6 EXTI_EMR_MR6 |
3464 | #define EXTI_EMR_EM7 EXTI_EMR_MR7 |
| 3465 | #define EXTI_EMR_EM7 EXTI_EMR_MR7 |
3465 | #define EXTI_EMR_EM8 EXTI_EMR_MR8 |
| 3466 | #define EXTI_EMR_EM8 EXTI_EMR_MR8 |
3466 | #define EXTI_EMR_EM9 EXTI_EMR_MR9 |
| 3467 | #define EXTI_EMR_EM9 EXTI_EMR_MR9 |
3467 | #define EXTI_EMR_EM10 EXTI_EMR_MR10 |
| 3468 | #define EXTI_EMR_EM10 EXTI_EMR_MR10 |
3468 | #define EXTI_EMR_EM11 EXTI_EMR_MR11 |
| 3469 | #define EXTI_EMR_EM11 EXTI_EMR_MR11 |
3469 | #define EXTI_EMR_EM12 EXTI_EMR_MR12 |
| 3470 | #define EXTI_EMR_EM12 EXTI_EMR_MR12 |
3470 | #define EXTI_EMR_EM13 EXTI_EMR_MR13 |
| 3471 | #define EXTI_EMR_EM13 EXTI_EMR_MR13 |
3471 | #define EXTI_EMR_EM14 EXTI_EMR_MR14 |
| 3472 | #define EXTI_EMR_EM14 EXTI_EMR_MR14 |
3472 | #define EXTI_EMR_EM15 EXTI_EMR_MR15 |
| 3473 | #define EXTI_EMR_EM15 EXTI_EMR_MR15 |
3473 | #define EXTI_EMR_EM16 EXTI_EMR_MR16 |
| 3474 | #define EXTI_EMR_EM16 EXTI_EMR_MR16 |
3474 | #define EXTI_EMR_EM17 EXTI_EMR_MR17 |
| 3475 | #define EXTI_EMR_EM17 EXTI_EMR_MR17 |
3475 | #define EXTI_EMR_EM18 EXTI_EMR_MR18 |
| 3476 | #define EXTI_EMR_EM18 EXTI_EMR_MR18 |
3476 | #define EXTI_EMR_EM19 EXTI_EMR_MR19 |
| 3477 | #define EXTI_EMR_EM19 EXTI_EMR_MR19 |
3477 | |
| 3478 | 3478 | /****************** Bit definition for EXTI_RTSR register *******************/ |
|
| 3479 | /****************** Bit definition for EXTI_RTSR register *******************/ |
3479 | #define EXTI_RTSR_TR0_Pos (0U) |
| 3480 | #define EXTI_RTSR_TR0_Pos (0U) |
3480 | #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ |
| 3481 | #define EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */ |
3481 | #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ |
| 3482 | #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */ |
3482 | #define EXTI_RTSR_TR1_Pos (1U) |
| 3483 | #define EXTI_RTSR_TR1_Pos (1U) |
3483 | #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ |
| 3484 | #define EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */ |
3484 | #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ |
| 3485 | #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */ |
3485 | #define EXTI_RTSR_TR2_Pos (2U) |
| 3486 | #define EXTI_RTSR_TR2_Pos (2U) |
3486 | #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ |
| 3487 | #define EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */ |
3487 | #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ |
| 3488 | #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */ |
3488 | #define EXTI_RTSR_TR3_Pos (3U) |
| 3489 | #define EXTI_RTSR_TR3_Pos (3U) |
3489 | #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ |
| 3490 | #define EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */ |
3490 | #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ |
| 3491 | #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */ |
3491 | #define EXTI_RTSR_TR4_Pos (4U) |
| 3492 | #define EXTI_RTSR_TR4_Pos (4U) |
3492 | #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ |
| 3493 | #define EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */ |
3493 | #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ |
| 3494 | #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */ |
3494 | #define EXTI_RTSR_TR5_Pos (5U) |
| 3495 | #define EXTI_RTSR_TR5_Pos (5U) |
3495 | #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ |
| 3496 | #define EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */ |
3496 | #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ |
| 3497 | #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */ |
3497 | #define EXTI_RTSR_TR6_Pos (6U) |
| 3498 | #define EXTI_RTSR_TR6_Pos (6U) |
3498 | #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ |
| 3499 | #define EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */ |
3499 | #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ |
| 3500 | #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */ |
3500 | #define EXTI_RTSR_TR7_Pos (7U) |
| 3501 | #define EXTI_RTSR_TR7_Pos (7U) |
3501 | #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ |
| 3502 | #define EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */ |
3502 | #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ |
| 3503 | #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */ |
3503 | #define EXTI_RTSR_TR8_Pos (8U) |
| 3504 | #define EXTI_RTSR_TR8_Pos (8U) |
3504 | #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ |
| 3505 | #define EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */ |
3505 | #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ |
| 3506 | #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */ |
3506 | #define EXTI_RTSR_TR9_Pos (9U) |
| 3507 | #define EXTI_RTSR_TR9_Pos (9U) |
3507 | #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ |
| 3508 | #define EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */ |
3508 | #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ |
| 3509 | #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */ |
3509 | #define EXTI_RTSR_TR10_Pos (10U) |
| 3510 | #define EXTI_RTSR_TR10_Pos (10U) |
3510 | #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ |
| 3511 | #define EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */ |
3511 | #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ |
| 3512 | #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */ |
3512 | #define EXTI_RTSR_TR11_Pos (11U) |
| 3513 | #define EXTI_RTSR_TR11_Pos (11U) |
3513 | #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ |
| 3514 | #define EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */ |
3514 | #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ |
| 3515 | #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */ |
3515 | #define EXTI_RTSR_TR12_Pos (12U) |
| 3516 | #define EXTI_RTSR_TR12_Pos (12U) |
3516 | #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ |
| 3517 | #define EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */ |
3517 | #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ |
| 3518 | #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */ |
3518 | #define EXTI_RTSR_TR13_Pos (13U) |
| 3519 | #define EXTI_RTSR_TR13_Pos (13U) |
3519 | #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ |
| 3520 | #define EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */ |
3520 | #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ |
| 3521 | #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */ |
3521 | #define EXTI_RTSR_TR14_Pos (14U) |
| 3522 | #define EXTI_RTSR_TR14_Pos (14U) |
3522 | #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ |
| 3523 | #define EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */ |
3523 | #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ |
| 3524 | #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */ |
3524 | #define EXTI_RTSR_TR15_Pos (15U) |
| 3525 | #define EXTI_RTSR_TR15_Pos (15U) |
3525 | #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ |
| 3526 | #define EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */ |
3526 | #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ |
| 3527 | #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */ |
3527 | #define EXTI_RTSR_TR16_Pos (16U) |
| 3528 | #define EXTI_RTSR_TR16_Pos (16U) |
3528 | #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ |
| 3529 | #define EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */ |
3529 | #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ |
| 3530 | #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */ |
3530 | #define EXTI_RTSR_TR17_Pos (17U) |
| 3531 | #define EXTI_RTSR_TR17_Pos (17U) |
3531 | #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ |
| 3532 | #define EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */ |
3532 | #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ |
| 3533 | #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */ |
3533 | #define EXTI_RTSR_TR18_Pos (18U) |
| 3534 | #define EXTI_RTSR_TR18_Pos (18U) |
3534 | #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ |
| 3535 | #define EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos) /*!< 0x00040000 */ |
3535 | #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ |
| 3536 | #define EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */ |
3536 | #define EXTI_RTSR_TR19_Pos (19U) |
| 3537 | #define EXTI_RTSR_TR19_Pos (19U) |
3537 | #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ |
| 3538 | #define EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */ |
3538 | #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ |
| 3539 | #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */ |
3539 | |
| 3540 | 3540 | /* References Defines */ |
|
| 3541 | /* References Defines */ |
3541 | #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 |
| 3542 | #define EXTI_RTSR_RT0 EXTI_RTSR_TR0 |
3542 | #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 |
| 3543 | #define EXTI_RTSR_RT1 EXTI_RTSR_TR1 |
3543 | #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 |
| 3544 | #define EXTI_RTSR_RT2 EXTI_RTSR_TR2 |
3544 | #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 |
| 3545 | #define EXTI_RTSR_RT3 EXTI_RTSR_TR3 |
3545 | #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 |
| 3546 | #define EXTI_RTSR_RT4 EXTI_RTSR_TR4 |
3546 | #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 |
| 3547 | #define EXTI_RTSR_RT5 EXTI_RTSR_TR5 |
3547 | #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 |
| 3548 | #define EXTI_RTSR_RT6 EXTI_RTSR_TR6 |
3548 | #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 |
| 3549 | #define EXTI_RTSR_RT7 EXTI_RTSR_TR7 |
3549 | #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 |
| 3550 | #define EXTI_RTSR_RT8 EXTI_RTSR_TR8 |
3550 | #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 |
| 3551 | #define EXTI_RTSR_RT9 EXTI_RTSR_TR9 |
3551 | #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 |
| 3552 | #define EXTI_RTSR_RT10 EXTI_RTSR_TR10 |
3552 | #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 |
| 3553 | #define EXTI_RTSR_RT11 EXTI_RTSR_TR11 |
3553 | #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 |
| 3554 | #define EXTI_RTSR_RT12 EXTI_RTSR_TR12 |
3554 | #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 |
| 3555 | #define EXTI_RTSR_RT13 EXTI_RTSR_TR13 |
3555 | #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 |
| 3556 | #define EXTI_RTSR_RT14 EXTI_RTSR_TR14 |
3556 | #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 |
| 3557 | #define EXTI_RTSR_RT15 EXTI_RTSR_TR15 |
3557 | #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 |
| 3558 | #define EXTI_RTSR_RT16 EXTI_RTSR_TR16 |
3558 | #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 |
| 3559 | #define EXTI_RTSR_RT17 EXTI_RTSR_TR17 |
3559 | #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 |
| 3560 | #define EXTI_RTSR_RT18 EXTI_RTSR_TR18 |
3560 | #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 |
| 3561 | #define EXTI_RTSR_RT19 EXTI_RTSR_TR19 |
3561 | |
| 3562 | 3562 | /****************** Bit definition for EXTI_FTSR register *******************/ |
|
| 3563 | /****************** Bit definition for EXTI_FTSR register *******************/ |
3563 | #define EXTI_FTSR_TR0_Pos (0U) |
| 3564 | #define EXTI_FTSR_TR0_Pos (0U) |
3564 | #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ |
| 3565 | #define EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */ |
3565 | #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ |
| 3566 | #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */ |
3566 | #define EXTI_FTSR_TR1_Pos (1U) |
| 3567 | #define EXTI_FTSR_TR1_Pos (1U) |
3567 | #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ |
| 3568 | #define EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */ |
3568 | #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ |
| 3569 | #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */ |
3569 | #define EXTI_FTSR_TR2_Pos (2U) |
| 3570 | #define EXTI_FTSR_TR2_Pos (2U) |
3570 | #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ |
| 3571 | #define EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */ |
3571 | #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ |
| 3572 | #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */ |
3572 | #define EXTI_FTSR_TR3_Pos (3U) |
| 3573 | #define EXTI_FTSR_TR3_Pos (3U) |
3573 | #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ |
| 3574 | #define EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */ |
3574 | #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ |
| 3575 | #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */ |
3575 | #define EXTI_FTSR_TR4_Pos (4U) |
| 3576 | #define EXTI_FTSR_TR4_Pos (4U) |
3576 | #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ |
| 3577 | #define EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */ |
3577 | #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ |
| 3578 | #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */ |
3578 | #define EXTI_FTSR_TR5_Pos (5U) |
| 3579 | #define EXTI_FTSR_TR5_Pos (5U) |
3579 | #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ |
| 3580 | #define EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */ |
3580 | #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ |
| 3581 | #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */ |
3581 | #define EXTI_FTSR_TR6_Pos (6U) |
| 3582 | #define EXTI_FTSR_TR6_Pos (6U) |
3582 | #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ |
| 3583 | #define EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */ |
3583 | #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ |
| 3584 | #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */ |
3584 | #define EXTI_FTSR_TR7_Pos (7U) |
| 3585 | #define EXTI_FTSR_TR7_Pos (7U) |
3585 | #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ |
| 3586 | #define EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */ |
3586 | #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ |
| 3587 | #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */ |
3587 | #define EXTI_FTSR_TR8_Pos (8U) |
| 3588 | #define EXTI_FTSR_TR8_Pos (8U) |
3588 | #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ |
| 3589 | #define EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */ |
3589 | #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ |
| 3590 | #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */ |
3590 | #define EXTI_FTSR_TR9_Pos (9U) |
| 3591 | #define EXTI_FTSR_TR9_Pos (9U) |
3591 | #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ |
| 3592 | #define EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */ |
3592 | #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ |
| 3593 | #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */ |
3593 | #define EXTI_FTSR_TR10_Pos (10U) |
| 3594 | #define EXTI_FTSR_TR10_Pos (10U) |
3594 | #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ |
| 3595 | #define EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */ |
3595 | #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ |
| 3596 | #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */ |
3596 | #define EXTI_FTSR_TR11_Pos (11U) |
| 3597 | #define EXTI_FTSR_TR11_Pos (11U) |
3597 | #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ |
| 3598 | #define EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */ |
3598 | #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ |
| 3599 | #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */ |
3599 | #define EXTI_FTSR_TR12_Pos (12U) |
| 3600 | #define EXTI_FTSR_TR12_Pos (12U) |
3600 | #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ |
| 3601 | #define EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */ |
3601 | #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ |
| 3602 | #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */ |
3602 | #define EXTI_FTSR_TR13_Pos (13U) |
| 3603 | #define EXTI_FTSR_TR13_Pos (13U) |
3603 | #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ |
| 3604 | #define EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */ |
3604 | #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ |
| 3605 | #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */ |
3605 | #define EXTI_FTSR_TR14_Pos (14U) |
| 3606 | #define EXTI_FTSR_TR14_Pos (14U) |
3606 | #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ |
| 3607 | #define EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */ |
3607 | #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ |
| 3608 | #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */ |
3608 | #define EXTI_FTSR_TR15_Pos (15U) |
| 3609 | #define EXTI_FTSR_TR15_Pos (15U) |
3609 | #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ |
| 3610 | #define EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */ |
3610 | #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ |
| 3611 | #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */ |
3611 | #define EXTI_FTSR_TR16_Pos (16U) |
| 3612 | #define EXTI_FTSR_TR16_Pos (16U) |
3612 | #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ |
| 3613 | #define EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */ |
3613 | #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ |
| 3614 | #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */ |
3614 | #define EXTI_FTSR_TR17_Pos (17U) |
| 3615 | #define EXTI_FTSR_TR17_Pos (17U) |
3615 | #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ |
| 3616 | #define EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */ |
3616 | #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ |
| 3617 | #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */ |
3617 | #define EXTI_FTSR_TR18_Pos (18U) |
| 3618 | #define EXTI_FTSR_TR18_Pos (18U) |
3618 | #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ |
| 3619 | #define EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos) /*!< 0x00040000 */ |
3619 | #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ |
| 3620 | #define EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */ |
3620 | #define EXTI_FTSR_TR19_Pos (19U) |
| 3621 | #define EXTI_FTSR_TR19_Pos (19U) |
3621 | #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ |
| 3622 | #define EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */ |
3622 | #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ |
| 3623 | #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */ |
3623 | |
| 3624 | 3624 | /* References Defines */ |
|
| 3625 | /* References Defines */ |
3625 | #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 |
| 3626 | #define EXTI_FTSR_FT0 EXTI_FTSR_TR0 |
3626 | #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 |
| 3627 | #define EXTI_FTSR_FT1 EXTI_FTSR_TR1 |
3627 | #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 |
| 3628 | #define EXTI_FTSR_FT2 EXTI_FTSR_TR2 |
3628 | #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 |
| 3629 | #define EXTI_FTSR_FT3 EXTI_FTSR_TR3 |
3629 | #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 |
| 3630 | #define EXTI_FTSR_FT4 EXTI_FTSR_TR4 |
3630 | #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 |
| 3631 | #define EXTI_FTSR_FT5 EXTI_FTSR_TR5 |
3631 | #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 |
| 3632 | #define EXTI_FTSR_FT6 EXTI_FTSR_TR6 |
3632 | #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 |
| 3633 | #define EXTI_FTSR_FT7 EXTI_FTSR_TR7 |
3633 | #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 |
| 3634 | #define EXTI_FTSR_FT8 EXTI_FTSR_TR8 |
3634 | #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 |
| 3635 | #define EXTI_FTSR_FT9 EXTI_FTSR_TR9 |
3635 | #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 |
| 3636 | #define EXTI_FTSR_FT10 EXTI_FTSR_TR10 |
3636 | #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 |
| 3637 | #define EXTI_FTSR_FT11 EXTI_FTSR_TR11 |
3637 | #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 |
| 3638 | #define EXTI_FTSR_FT12 EXTI_FTSR_TR12 |
3638 | #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 |
| 3639 | #define EXTI_FTSR_FT13 EXTI_FTSR_TR13 |
3639 | #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 |
| 3640 | #define EXTI_FTSR_FT14 EXTI_FTSR_TR14 |
3640 | #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 |
| 3641 | #define EXTI_FTSR_FT15 EXTI_FTSR_TR15 |
3641 | #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 |
| 3642 | #define EXTI_FTSR_FT16 EXTI_FTSR_TR16 |
3642 | #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 |
| 3643 | #define EXTI_FTSR_FT17 EXTI_FTSR_TR17 |
3643 | #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 |
| 3644 | #define EXTI_FTSR_FT18 EXTI_FTSR_TR18 |
3644 | #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 |
| 3645 | #define EXTI_FTSR_FT19 EXTI_FTSR_TR19 |
3645 | |
| 3646 | 3646 | /****************** Bit definition for EXTI_SWIER register ******************/ |
|
| 3647 | /****************** Bit definition for EXTI_SWIER register ******************/ |
3647 | #define EXTI_SWIER_SWIER0_Pos (0U) |
| 3648 | #define EXTI_SWIER_SWIER0_Pos (0U) |
3648 | #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ |
| 3649 | #define EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */ |
3649 | #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ |
| 3650 | #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */ |
3650 | #define EXTI_SWIER_SWIER1_Pos (1U) |
| 3651 | #define EXTI_SWIER_SWIER1_Pos (1U) |
3651 | #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ |
| 3652 | #define EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */ |
3652 | #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ |
| 3653 | #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */ |
3653 | #define EXTI_SWIER_SWIER2_Pos (2U) |
| 3654 | #define EXTI_SWIER_SWIER2_Pos (2U) |
3654 | #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ |
| 3655 | #define EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */ |
3655 | #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ |
| 3656 | #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */ |
3656 | #define EXTI_SWIER_SWIER3_Pos (3U) |
| 3657 | #define EXTI_SWIER_SWIER3_Pos (3U) |
3657 | #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ |
| 3658 | #define EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */ |
3658 | #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ |
| 3659 | #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */ |
3659 | #define EXTI_SWIER_SWIER4_Pos (4U) |
| 3660 | #define EXTI_SWIER_SWIER4_Pos (4U) |
3660 | #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ |
| 3661 | #define EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */ |
3661 | #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ |
| 3662 | #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */ |
3662 | #define EXTI_SWIER_SWIER5_Pos (5U) |
| 3663 | #define EXTI_SWIER_SWIER5_Pos (5U) |
3663 | #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ |
| 3664 | #define EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */ |
3664 | #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ |
| 3665 | #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */ |
3665 | #define EXTI_SWIER_SWIER6_Pos (6U) |
| 3666 | #define EXTI_SWIER_SWIER6_Pos (6U) |
3666 | #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ |
| 3667 | #define EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */ |
3667 | #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ |
| 3668 | #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */ |
3668 | #define EXTI_SWIER_SWIER7_Pos (7U) |
| 3669 | #define EXTI_SWIER_SWIER7_Pos (7U) |
3669 | #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ |
| 3670 | #define EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */ |
3670 | #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ |
| 3671 | #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */ |
3671 | #define EXTI_SWIER_SWIER8_Pos (8U) |
| 3672 | #define EXTI_SWIER_SWIER8_Pos (8U) |
3672 | #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ |
| 3673 | #define EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */ |
3673 | #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ |
| 3674 | #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */ |
3674 | #define EXTI_SWIER_SWIER9_Pos (9U) |
| 3675 | #define EXTI_SWIER_SWIER9_Pos (9U) |
3675 | #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ |
| 3676 | #define EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */ |
3676 | #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ |
| 3677 | #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */ |
3677 | #define EXTI_SWIER_SWIER10_Pos (10U) |
| 3678 | #define EXTI_SWIER_SWIER10_Pos (10U) |
3678 | #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ |
| 3679 | #define EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */ |
3679 | #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ |
| 3680 | #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */ |
3680 | #define EXTI_SWIER_SWIER11_Pos (11U) |
| 3681 | #define EXTI_SWIER_SWIER11_Pos (11U) |
3681 | #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ |
| 3682 | #define EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */ |
3682 | #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ |
| 3683 | #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */ |
3683 | #define EXTI_SWIER_SWIER12_Pos (12U) |
| 3684 | #define EXTI_SWIER_SWIER12_Pos (12U) |
3684 | #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ |
| 3685 | #define EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */ |
3685 | #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ |
| 3686 | #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */ |
3686 | #define EXTI_SWIER_SWIER13_Pos (13U) |
| 3687 | #define EXTI_SWIER_SWIER13_Pos (13U) |
3687 | #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ |
| 3688 | #define EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */ |
3688 | #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ |
| 3689 | #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */ |
3689 | #define EXTI_SWIER_SWIER14_Pos (14U) |
| 3690 | #define EXTI_SWIER_SWIER14_Pos (14U) |
3690 | #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ |
| 3691 | #define EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */ |
3691 | #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ |
| 3692 | #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */ |
3692 | #define EXTI_SWIER_SWIER15_Pos (15U) |
| 3693 | #define EXTI_SWIER_SWIER15_Pos (15U) |
3693 | #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ |
| 3694 | #define EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */ |
3694 | #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ |
| 3695 | #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */ |
3695 | #define EXTI_SWIER_SWIER16_Pos (16U) |
| 3696 | #define EXTI_SWIER_SWIER16_Pos (16U) |
3696 | #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ |
| 3697 | #define EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */ |
3697 | #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ |
| 3698 | #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */ |
3698 | #define EXTI_SWIER_SWIER17_Pos (17U) |
| 3699 | #define EXTI_SWIER_SWIER17_Pos (17U) |
3699 | #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ |
| 3700 | #define EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */ |
3700 | #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ |
| 3701 | #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */ |
3701 | #define EXTI_SWIER_SWIER18_Pos (18U) |
| 3702 | #define EXTI_SWIER_SWIER18_Pos (18U) |
3702 | #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ |
| 3703 | #define EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos) /*!< 0x00040000 */ |
3703 | #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ |
| 3704 | #define EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk /*!< Software Interrupt on line 18 */ |
3704 | #define EXTI_SWIER_SWIER19_Pos (19U) |
| 3705 | #define EXTI_SWIER_SWIER19_Pos (19U) |
3705 | #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ |
| 3706 | #define EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */ |
3706 | #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ |
| 3707 | #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */ |
3707 | |
| 3708 | 3708 | /* References Defines */ |
|
| 3709 | /* References Defines */ |
3709 | #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 |
| 3710 | #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0 |
3710 | #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 |
| 3711 | #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1 |
3711 | #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 |
| 3712 | #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2 |
3712 | #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 |
| 3713 | #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3 |
3713 | #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 |
| 3714 | #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4 |
3714 | #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 |
| 3715 | #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5 |
3715 | #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 |
| 3716 | #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6 |
3716 | #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 |
| 3717 | #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7 |
3717 | #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 |
| 3718 | #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8 |
3718 | #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 |
| 3719 | #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9 |
3719 | #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 |
| 3720 | #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10 |
3720 | #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 |
| 3721 | #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11 |
3721 | #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 |
| 3722 | #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12 |
3722 | #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 |
| 3723 | #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13 |
3723 | #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 |
| 3724 | #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14 |
3724 | #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 |
| 3725 | #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15 |
3725 | #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 |
| 3726 | #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16 |
3726 | #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 |
| 3727 | #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17 |
3727 | #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 |
| 3728 | #define EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18 |
3728 | #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 |
| 3729 | #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19 |
3729 | |
| 3730 | 3730 | /******************* Bit definition for EXTI_PR register ********************/ |
|
| 3731 | /******************* Bit definition for EXTI_PR register ********************/ |
3731 | #define EXTI_PR_PR0_Pos (0U) |
| 3732 | #define EXTI_PR_PR0_Pos (0U) |
3732 | #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ |
| 3733 | #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ |
3733 | #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ |
| 3734 | #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit for line 0 */ |
3734 | #define EXTI_PR_PR1_Pos (1U) |
| 3735 | #define EXTI_PR_PR1_Pos (1U) |
3735 | #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ |
| 3736 | #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ |
3736 | #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ |
| 3737 | #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit for line 1 */ |
3737 | #define EXTI_PR_PR2_Pos (2U) |
| 3738 | #define EXTI_PR_PR2_Pos (2U) |
3738 | #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ |
| 3739 | #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ |
3739 | #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ |
| 3740 | #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit for line 2 */ |
3740 | #define EXTI_PR_PR3_Pos (3U) |
| 3741 | #define EXTI_PR_PR3_Pos (3U) |
3741 | #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ |
| 3742 | #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ |
3742 | #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ |
| 3743 | #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit for line 3 */ |
3743 | #define EXTI_PR_PR4_Pos (4U) |
| 3744 | #define EXTI_PR_PR4_Pos (4U) |
3744 | #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ |
| 3745 | #define EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos) /*!< 0x00000010 */ |
3745 | #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ |
| 3746 | #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit for line 4 */ |
3746 | #define EXTI_PR_PR5_Pos (5U) |
| 3747 | #define EXTI_PR_PR5_Pos (5U) |
3747 | #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ |
| 3748 | #define EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos) /*!< 0x00000020 */ |
3748 | #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ |
| 3749 | #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit for line 5 */ |
3749 | #define EXTI_PR_PR6_Pos (6U) |
| 3750 | #define EXTI_PR_PR6_Pos (6U) |
3750 | #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ |
| 3751 | #define EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos) /*!< 0x00000040 */ |
3751 | #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ |
| 3752 | #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit for line 6 */ |
3752 | #define EXTI_PR_PR7_Pos (7U) |
| 3753 | #define EXTI_PR_PR7_Pos (7U) |
3753 | #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ |
| 3754 | #define EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos) /*!< 0x00000080 */ |
3754 | #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ |
| 3755 | #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit for line 7 */ |
3755 | #define EXTI_PR_PR8_Pos (8U) |
| 3756 | #define EXTI_PR_PR8_Pos (8U) |
3756 | #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ |
| 3757 | #define EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos) /*!< 0x00000100 */ |
3757 | #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ |
| 3758 | #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit for line 8 */ |
3758 | #define EXTI_PR_PR9_Pos (9U) |
| 3759 | #define EXTI_PR_PR9_Pos (9U) |
3759 | #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ |
| 3760 | #define EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos) /*!< 0x00000200 */ |
3760 | #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ |
| 3761 | #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit for line 9 */ |
3761 | #define EXTI_PR_PR10_Pos (10U) |
| 3762 | #define EXTI_PR_PR10_Pos (10U) |
3762 | #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ |
| 3763 | #define EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos) /*!< 0x00000400 */ |
3763 | #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ |
| 3764 | #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit for line 10 */ |
3764 | #define EXTI_PR_PR11_Pos (11U) |
| 3765 | #define EXTI_PR_PR11_Pos (11U) |
3765 | #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ |
| 3766 | #define EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos) /*!< 0x00000800 */ |
3766 | #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ |
| 3767 | #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit for line 11 */ |
3767 | #define EXTI_PR_PR12_Pos (12U) |
| 3768 | #define EXTI_PR_PR12_Pos (12U) |
3768 | #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ |
| 3769 | #define EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos) /*!< 0x00001000 */ |
3769 | #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ |
| 3770 | #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit for line 12 */ |
3770 | #define EXTI_PR_PR13_Pos (13U) |
| 3771 | #define EXTI_PR_PR13_Pos (13U) |
3771 | #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ |
| 3772 | #define EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos) /*!< 0x00002000 */ |
3772 | #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ |
| 3773 | #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit for line 13 */ |
3773 | #define EXTI_PR_PR14_Pos (14U) |
| 3774 | #define EXTI_PR_PR14_Pos (14U) |
3774 | #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ |
| 3775 | #define EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos) /*!< 0x00004000 */ |
3775 | #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ |
| 3776 | #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit for line 14 */ |
3776 | #define EXTI_PR_PR15_Pos (15U) |
| 3777 | #define EXTI_PR_PR15_Pos (15U) |
3777 | #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ |
| 3778 | #define EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos) /*!< 0x00008000 */ |
3778 | #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ |
| 3779 | #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit for line 15 */ |
3779 | #define EXTI_PR_PR16_Pos (16U) |
| 3780 | #define EXTI_PR_PR16_Pos (16U) |
3780 | #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ |
| 3781 | #define EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos) /*!< 0x00010000 */ |
3781 | #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ |
| 3782 | #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit for line 16 */ |
3782 | #define EXTI_PR_PR17_Pos (17U) |
| 3783 | #define EXTI_PR_PR17_Pos (17U) |
3783 | #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ |
| 3784 | #define EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos) /*!< 0x00020000 */ |
3784 | #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ |
| 3785 | #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit for line 17 */ |
3785 | #define EXTI_PR_PR18_Pos (18U) |
| 3786 | #define EXTI_PR_PR18_Pos (18U) |
3786 | #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ |
| 3787 | #define EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos) /*!< 0x00040000 */ |
3787 | #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ |
| 3788 | #define EXTI_PR_PR18 EXTI_PR_PR18_Msk /*!< Pending bit for line 18 */ |
3788 | #define EXTI_PR_PR19_Pos (19U) |
| 3789 | #define EXTI_PR_PR19_Pos (19U) |
3789 | #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ |
| 3790 | #define EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos) /*!< 0x00080000 */ |
3790 | #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ |
| 3791 | #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit for line 19 */ |
3791 | |
| 3792 | 3792 | /* References Defines */ |
|
| 3793 | /* References Defines */ |
3793 | #define EXTI_PR_PIF0 EXTI_PR_PR0 |
| 3794 | #define EXTI_PR_PIF0 EXTI_PR_PR0 |
3794 | #define EXTI_PR_PIF1 EXTI_PR_PR1 |
| 3795 | #define EXTI_PR_PIF1 EXTI_PR_PR1 |
3795 | #define EXTI_PR_PIF2 EXTI_PR_PR2 |
| 3796 | #define EXTI_PR_PIF2 EXTI_PR_PR2 |
3796 | #define EXTI_PR_PIF3 EXTI_PR_PR3 |
| 3797 | #define EXTI_PR_PIF3 EXTI_PR_PR3 |
3797 | #define EXTI_PR_PIF4 EXTI_PR_PR4 |
| 3798 | #define EXTI_PR_PIF4 EXTI_PR_PR4 |
3798 | #define EXTI_PR_PIF5 EXTI_PR_PR5 |
| 3799 | #define EXTI_PR_PIF5 EXTI_PR_PR5 |
3799 | #define EXTI_PR_PIF6 EXTI_PR_PR6 |
| 3800 | #define EXTI_PR_PIF6 EXTI_PR_PR6 |
3800 | #define EXTI_PR_PIF7 EXTI_PR_PR7 |
| 3801 | #define EXTI_PR_PIF7 EXTI_PR_PR7 |
3801 | #define EXTI_PR_PIF8 EXTI_PR_PR8 |
| 3802 | #define EXTI_PR_PIF8 EXTI_PR_PR8 |
3802 | #define EXTI_PR_PIF9 EXTI_PR_PR9 |
| 3803 | #define EXTI_PR_PIF9 EXTI_PR_PR9 |
3803 | #define EXTI_PR_PIF10 EXTI_PR_PR10 |
| 3804 | #define EXTI_PR_PIF10 EXTI_PR_PR10 |
3804 | #define EXTI_PR_PIF11 EXTI_PR_PR11 |
| 3805 | #define EXTI_PR_PIF11 EXTI_PR_PR11 |
3805 | #define EXTI_PR_PIF12 EXTI_PR_PR12 |
| 3806 | #define EXTI_PR_PIF12 EXTI_PR_PR12 |
3806 | #define EXTI_PR_PIF13 EXTI_PR_PR13 |
| 3807 | #define EXTI_PR_PIF13 EXTI_PR_PR13 |
3807 | #define EXTI_PR_PIF14 EXTI_PR_PR14 |
| 3808 | #define EXTI_PR_PIF14 EXTI_PR_PR14 |
3808 | #define EXTI_PR_PIF15 EXTI_PR_PR15 |
| 3809 | #define EXTI_PR_PIF15 EXTI_PR_PR15 |
3809 | #define EXTI_PR_PIF16 EXTI_PR_PR16 |
| 3810 | #define EXTI_PR_PIF16 EXTI_PR_PR16 |
3810 | #define EXTI_PR_PIF17 EXTI_PR_PR17 |
| 3811 | #define EXTI_PR_PIF17 EXTI_PR_PR17 |
3811 | #define EXTI_PR_PIF18 EXTI_PR_PR18 |
| 3812 | #define EXTI_PR_PIF18 EXTI_PR_PR18 |
3812 | #define EXTI_PR_PIF19 EXTI_PR_PR19 |
| 3813 | #define EXTI_PR_PIF19 EXTI_PR_PR19 |
3813 | |
| 3814 | 3814 | /******************************************************************************/ |
|
| 3815 | /******************************************************************************/ |
3815 | /* */ |
| 3816 | /* */ |
3816 | /* DMA Controller */ |
| 3817 | /* DMA Controller */ |
3817 | /* */ |
| 3818 | /* */ |
3818 | /******************************************************************************/ |
| 3819 | /******************************************************************************/ |
3819 | |
| 3820 | 3820 | /******************* Bit definition for DMA_ISR register ********************/ |
|
| 3821 | /******************* Bit definition for DMA_ISR register ********************/ |
3821 | #define DMA_ISR_GIF1_Pos (0U) |
| 3822 | #define DMA_ISR_GIF1_Pos (0U) |
3822 | #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ |
| 3823 | #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ |
3823 | #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ |
| 3824 | #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ |
3824 | #define DMA_ISR_TCIF1_Pos (1U) |
| 3825 | #define DMA_ISR_TCIF1_Pos (1U) |
3825 | #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ |
| 3826 | #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ |
3826 | #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ |
| 3827 | #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ |
3827 | #define DMA_ISR_HTIF1_Pos (2U) |
| 3828 | #define DMA_ISR_HTIF1_Pos (2U) |
3828 | #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ |
| 3829 | #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ |
3829 | #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ |
| 3830 | #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ |
3830 | #define DMA_ISR_TEIF1_Pos (3U) |
| 3831 | #define DMA_ISR_TEIF1_Pos (3U) |
3831 | #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ |
| 3832 | #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ |
3832 | #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ |
| 3833 | #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ |
3833 | #define DMA_ISR_GIF2_Pos (4U) |
| 3834 | #define DMA_ISR_GIF2_Pos (4U) |
3834 | #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ |
| 3835 | #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ |
3835 | #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ |
| 3836 | #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ |
3836 | #define DMA_ISR_TCIF2_Pos (5U) |
| 3837 | #define DMA_ISR_TCIF2_Pos (5U) |
3837 | #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ |
| 3838 | #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ |
3838 | #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ |
| 3839 | #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ |
3839 | #define DMA_ISR_HTIF2_Pos (6U) |
| 3840 | #define DMA_ISR_HTIF2_Pos (6U) |
3840 | #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ |
| 3841 | #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ |
3841 | #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ |
| 3842 | #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ |
3842 | #define DMA_ISR_TEIF2_Pos (7U) |
| 3843 | #define DMA_ISR_TEIF2_Pos (7U) |
3843 | #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ |
| 3844 | #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ |
3844 | #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ |
| 3845 | #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ |
3845 | #define DMA_ISR_GIF3_Pos (8U) |
| 3846 | #define DMA_ISR_GIF3_Pos (8U) |
3846 | #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ |
| 3847 | #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ |
3847 | #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ |
| 3848 | #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ |
3848 | #define DMA_ISR_TCIF3_Pos (9U) |
| 3849 | #define DMA_ISR_TCIF3_Pos (9U) |
3849 | #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ |
| 3850 | #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ |
3850 | #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ |
| 3851 | #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ |
3851 | #define DMA_ISR_HTIF3_Pos (10U) |
| 3852 | #define DMA_ISR_HTIF3_Pos (10U) |
3852 | #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ |
| 3853 | #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ |
3853 | #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ |
| 3854 | #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ |
3854 | #define DMA_ISR_TEIF3_Pos (11U) |
| 3855 | #define DMA_ISR_TEIF3_Pos (11U) |
3855 | #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ |
| 3856 | #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ |
3856 | #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ |
| 3857 | #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ |
3857 | #define DMA_ISR_GIF4_Pos (12U) |
| 3858 | #define DMA_ISR_GIF4_Pos (12U) |
3858 | #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ |
| 3859 | #define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ |
3859 | #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ |
| 3860 | #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ |
3860 | #define DMA_ISR_TCIF4_Pos (13U) |
| 3861 | #define DMA_ISR_TCIF4_Pos (13U) |
3861 | #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ |
| 3862 | #define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ |
3862 | #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ |
| 3863 | #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ |
3863 | #define DMA_ISR_HTIF4_Pos (14U) |
| 3864 | #define DMA_ISR_HTIF4_Pos (14U) |
3864 | #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ |
| 3865 | #define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ |
3865 | #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ |
| 3866 | #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ |
3866 | #define DMA_ISR_TEIF4_Pos (15U) |
| 3867 | #define DMA_ISR_TEIF4_Pos (15U) |
3867 | #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ |
| 3868 | #define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ |
3868 | #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ |
| 3869 | #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ |
3869 | #define DMA_ISR_GIF5_Pos (16U) |
| 3870 | #define DMA_ISR_GIF5_Pos (16U) |
3870 | #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ |
| 3871 | #define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ |
3871 | #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ |
| 3872 | #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ |
3872 | #define DMA_ISR_TCIF5_Pos (17U) |
| 3873 | #define DMA_ISR_TCIF5_Pos (17U) |
3873 | #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ |
| 3874 | #define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ |
3874 | #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ |
| 3875 | #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ |
3875 | #define DMA_ISR_HTIF5_Pos (18U) |
| 3876 | #define DMA_ISR_HTIF5_Pos (18U) |
3876 | #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ |
| 3877 | #define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ |
3877 | #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ |
| 3878 | #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ |
3878 | #define DMA_ISR_TEIF5_Pos (19U) |
| 3879 | #define DMA_ISR_TEIF5_Pos (19U) |
3879 | #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ |
| 3880 | #define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ |
3880 | #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ |
| 3881 | #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ |
3881 | #define DMA_ISR_GIF6_Pos (20U) |
| 3882 | #define DMA_ISR_GIF6_Pos (20U) |
3882 | #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ |
| 3883 | #define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ |
3883 | #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ |
| 3884 | #define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ |
3884 | #define DMA_ISR_TCIF6_Pos (21U) |
| 3885 | #define DMA_ISR_TCIF6_Pos (21U) |
3885 | #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ |
| 3886 | #define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ |
3886 | #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ |
| 3887 | #define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ |
3887 | #define DMA_ISR_HTIF6_Pos (22U) |
| 3888 | #define DMA_ISR_HTIF6_Pos (22U) |
3888 | #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ |
| 3889 | #define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ |
3889 | #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ |
| 3890 | #define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ |
3890 | #define DMA_ISR_TEIF6_Pos (23U) |
| 3891 | #define DMA_ISR_TEIF6_Pos (23U) |
3891 | #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ |
| 3892 | #define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ |
3892 | #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ |
| 3893 | #define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ |
3893 | #define DMA_ISR_GIF7_Pos (24U) |
| 3894 | #define DMA_ISR_GIF7_Pos (24U) |
3894 | #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ |
| 3895 | #define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ |
3895 | #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ |
| 3896 | #define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ |
3896 | #define DMA_ISR_TCIF7_Pos (25U) |
| 3897 | #define DMA_ISR_TCIF7_Pos (25U) |
3897 | #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ |
| 3898 | #define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ |
3898 | #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ |
| 3899 | #define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ |
3899 | #define DMA_ISR_HTIF7_Pos (26U) |
| 3900 | #define DMA_ISR_HTIF7_Pos (26U) |
3900 | #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ |
| 3901 | #define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ |
3901 | #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ |
| 3902 | #define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ |
3902 | #define DMA_ISR_TEIF7_Pos (27U) |
| 3903 | #define DMA_ISR_TEIF7_Pos (27U) |
3903 | #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ |
| 3904 | #define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ |
3904 | #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ |
| 3905 | #define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ |
3905 | |
| 3906 | 3906 | /******************* Bit definition for DMA_IFCR register *******************/ |
|
| 3907 | /******************* Bit definition for DMA_IFCR register *******************/ |
3907 | #define DMA_IFCR_CGIF1_Pos (0U) |
| 3908 | #define DMA_IFCR_CGIF1_Pos (0U) |
3908 | #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ |
| 3909 | #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ |
3909 | #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ |
| 3910 | #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ |
3910 | #define DMA_IFCR_CTCIF1_Pos (1U) |
| 3911 | #define DMA_IFCR_CTCIF1_Pos (1U) |
3911 | #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ |
| 3912 | #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ |
3912 | #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ |
| 3913 | #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ |
3913 | #define DMA_IFCR_CHTIF1_Pos (2U) |
| 3914 | #define DMA_IFCR_CHTIF1_Pos (2U) |
3914 | #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ |
| 3915 | #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ |
3915 | #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ |
| 3916 | #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ |
3916 | #define DMA_IFCR_CTEIF1_Pos (3U) |
| 3917 | #define DMA_IFCR_CTEIF1_Pos (3U) |
3917 | #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ |
| 3918 | #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ |
3918 | #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ |
| 3919 | #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ |
3919 | #define DMA_IFCR_CGIF2_Pos (4U) |
| 3920 | #define DMA_IFCR_CGIF2_Pos (4U) |
3920 | #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ |
| 3921 | #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ |
3921 | #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ |
| 3922 | #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ |
3922 | #define DMA_IFCR_CTCIF2_Pos (5U) |
| 3923 | #define DMA_IFCR_CTCIF2_Pos (5U) |
3923 | #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ |
| 3924 | #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ |
3924 | #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ |
| 3925 | #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ |
3925 | #define DMA_IFCR_CHTIF2_Pos (6U) |
| 3926 | #define DMA_IFCR_CHTIF2_Pos (6U) |
3926 | #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ |
| 3927 | #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ |
3927 | #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ |
| 3928 | #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ |
3928 | #define DMA_IFCR_CTEIF2_Pos (7U) |
| 3929 | #define DMA_IFCR_CTEIF2_Pos (7U) |
3929 | #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ |
| 3930 | #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ |
3930 | #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ |
| 3931 | #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ |
3931 | #define DMA_IFCR_CGIF3_Pos (8U) |
| 3932 | #define DMA_IFCR_CGIF3_Pos (8U) |
3932 | #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ |
| 3933 | #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ |
3933 | #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ |
| 3934 | #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ |
3934 | #define DMA_IFCR_CTCIF3_Pos (9U) |
| 3935 | #define DMA_IFCR_CTCIF3_Pos (9U) |
3935 | #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ |
| 3936 | #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ |
3936 | #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ |
| 3937 | #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ |
3937 | #define DMA_IFCR_CHTIF3_Pos (10U) |
| 3938 | #define DMA_IFCR_CHTIF3_Pos (10U) |
3938 | #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ |
| 3939 | #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ |
3939 | #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ |
| 3940 | #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ |
3940 | #define DMA_IFCR_CTEIF3_Pos (11U) |
| 3941 | #define DMA_IFCR_CTEIF3_Pos (11U) |
3941 | #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ |
| 3942 | #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ |
3942 | #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ |
| 3943 | #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ |
3943 | #define DMA_IFCR_CGIF4_Pos (12U) |
| 3944 | #define DMA_IFCR_CGIF4_Pos (12U) |
3944 | #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ |
| 3945 | #define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ |
3945 | #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ |
| 3946 | #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ |
3946 | #define DMA_IFCR_CTCIF4_Pos (13U) |
| 3947 | #define DMA_IFCR_CTCIF4_Pos (13U) |
3947 | #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ |
| 3948 | #define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ |
3948 | #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ |
| 3949 | #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ |
3949 | #define DMA_IFCR_CHTIF4_Pos (14U) |
| 3950 | #define DMA_IFCR_CHTIF4_Pos (14U) |
3950 | #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ |
| 3951 | #define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ |
3951 | #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ |
| 3952 | #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ |
3952 | #define DMA_IFCR_CTEIF4_Pos (15U) |
| 3953 | #define DMA_IFCR_CTEIF4_Pos (15U) |
3953 | #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ |
| 3954 | #define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ |
3954 | #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ |
| 3955 | #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ |
3955 | #define DMA_IFCR_CGIF5_Pos (16U) |
| 3956 | #define DMA_IFCR_CGIF5_Pos (16U) |
3956 | #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ |
| 3957 | #define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ |
3957 | #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ |
| 3958 | #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ |
3958 | #define DMA_IFCR_CTCIF5_Pos (17U) |
| 3959 | #define DMA_IFCR_CTCIF5_Pos (17U) |
3959 | #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ |
| 3960 | #define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ |
3960 | #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ |
| 3961 | #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ |
3961 | #define DMA_IFCR_CHTIF5_Pos (18U) |
| 3962 | #define DMA_IFCR_CHTIF5_Pos (18U) |
3962 | #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ |
| 3963 | #define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ |
3963 | #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ |
| 3964 | #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ |
3964 | #define DMA_IFCR_CTEIF5_Pos (19U) |
| 3965 | #define DMA_IFCR_CTEIF5_Pos (19U) |
3965 | #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ |
| 3966 | #define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ |
3966 | #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ |
| 3967 | #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ |
3967 | #define DMA_IFCR_CGIF6_Pos (20U) |
| 3968 | #define DMA_IFCR_CGIF6_Pos (20U) |
3968 | #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ |
| 3969 | #define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ |
3969 | #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ |
| 3970 | #define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ |
3970 | #define DMA_IFCR_CTCIF6_Pos (21U) |
| 3971 | #define DMA_IFCR_CTCIF6_Pos (21U) |
3971 | #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ |
| 3972 | #define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ |
3972 | #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ |
| 3973 | #define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ |
3973 | #define DMA_IFCR_CHTIF6_Pos (22U) |
| 3974 | #define DMA_IFCR_CHTIF6_Pos (22U) |
3974 | #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ |
| 3975 | #define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ |
3975 | #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ |
| 3976 | #define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ |
3976 | #define DMA_IFCR_CTEIF6_Pos (23U) |
| 3977 | #define DMA_IFCR_CTEIF6_Pos (23U) |
3977 | #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ |
| 3978 | #define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ |
3978 | #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ |
| 3979 | #define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ |
3979 | #define DMA_IFCR_CGIF7_Pos (24U) |
| 3980 | #define DMA_IFCR_CGIF7_Pos (24U) |
3980 | #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ |
| 3981 | #define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ |
3981 | #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ |
| 3982 | #define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ |
3982 | #define DMA_IFCR_CTCIF7_Pos (25U) |
| 3983 | #define DMA_IFCR_CTCIF7_Pos (25U) |
3983 | #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ |
| 3984 | #define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ |
3984 | #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ |
| 3985 | #define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ |
3985 | #define DMA_IFCR_CHTIF7_Pos (26U) |
| 3986 | #define DMA_IFCR_CHTIF7_Pos (26U) |
3986 | #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ |
| 3987 | #define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ |
3987 | #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ |
| 3988 | #define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ |
3988 | #define DMA_IFCR_CTEIF7_Pos (27U) |
| 3989 | #define DMA_IFCR_CTEIF7_Pos (27U) |
3989 | #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ |
| 3990 | #define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ |
3990 | #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ |
| 3991 | #define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ |
3991 | |
| 3992 | 3992 | /******************* Bit definition for DMA_CCR register *******************/ |
|
| 3993 | /******************* Bit definition for DMA_CCR register *******************/ |
3993 | #define DMA_CCR_EN_Pos (0U) |
| 3994 | #define DMA_CCR_EN_Pos (0U) |
3994 | #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ |
| 3995 | #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ |
3995 | #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ |
| 3996 | #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ |
3996 | #define DMA_CCR_TCIE_Pos (1U) |
| 3997 | #define DMA_CCR_TCIE_Pos (1U) |
3997 | #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ |
| 3998 | #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ |
3998 | #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ |
| 3999 | #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ |
3999 | #define DMA_CCR_HTIE_Pos (2U) |
| 4000 | #define DMA_CCR_HTIE_Pos (2U) |
4000 | #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ |
| 4001 | #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ |
4001 | #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ |
| 4002 | #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ |
4002 | #define DMA_CCR_TEIE_Pos (3U) |
| 4003 | #define DMA_CCR_TEIE_Pos (3U) |
4003 | #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ |
| 4004 | #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ |
4004 | #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ |
| 4005 | #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ |
4005 | #define DMA_CCR_DIR_Pos (4U) |
| 4006 | #define DMA_CCR_DIR_Pos (4U) |
4006 | #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ |
| 4007 | #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ |
4007 | #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ |
| 4008 | #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ |
4008 | #define DMA_CCR_CIRC_Pos (5U) |
| 4009 | #define DMA_CCR_CIRC_Pos (5U) |
4009 | #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ |
| 4010 | #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ |
4010 | #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ |
| 4011 | #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ |
4011 | #define DMA_CCR_PINC_Pos (6U) |
| 4012 | #define DMA_CCR_PINC_Pos (6U) |
4012 | #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ |
| 4013 | #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ |
4013 | #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ |
| 4014 | #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ |
4014 | #define DMA_CCR_MINC_Pos (7U) |
| 4015 | #define DMA_CCR_MINC_Pos (7U) |
4015 | #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ |
| 4016 | #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ |
4016 | #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ |
| 4017 | #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ |
4017 | |
| 4018 | 4018 | #define DMA_CCR_PSIZE_Pos (8U) |
|
| 4019 | #define DMA_CCR_PSIZE_Pos (8U) |
4019 | #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ |
| 4020 | #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ |
4020 | #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ |
| 4021 | #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ |
4021 | #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ |
| 4022 | #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ |
4022 | #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ |
| 4023 | #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ |
4023 | |
| 4024 | 4024 | #define DMA_CCR_MSIZE_Pos (10U) |
|
| 4025 | #define DMA_CCR_MSIZE_Pos (10U) |
4025 | #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ |
| 4026 | #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ |
4026 | #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ |
| 4027 | #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ |
4027 | #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ |
| 4028 | #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ |
4028 | #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ |
| 4029 | #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ |
4029 | |
| 4030 | 4030 | #define DMA_CCR_PL_Pos (12U) |
|
| 4031 | #define DMA_CCR_PL_Pos (12U) |
4031 | #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ |
| 4032 | #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ |
4032 | #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ |
| 4033 | #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level) */ |
4033 | #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ |
| 4034 | #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ |
4034 | #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ |
| 4035 | #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ |
4035 | |
| 4036 | 4036 | #define DMA_CCR_MEM2MEM_Pos (14U) |
|
| 4037 | #define DMA_CCR_MEM2MEM_Pos (14U) |
4037 | #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ |
| 4038 | #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ |
4038 | #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ |
| 4039 | #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ |
4039 | |
| 4040 | 4040 | /****************** Bit definition for DMA_CNDTR register ******************/ |
|
| 4041 | /****************** Bit definition for DMA_CNDTR register ******************/ |
4041 | #define DMA_CNDTR_NDT_Pos (0U) |
| 4042 | #define DMA_CNDTR_NDT_Pos (0U) |
4042 | #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ |
| 4043 | #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ |
4043 | #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ |
| 4044 | #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ |
4044 | |
| 4045 | 4045 | /****************** Bit definition for DMA_CPAR register *******************/ |
|
| 4046 | /****************** Bit definition for DMA_CPAR register *******************/ |
4046 | #define DMA_CPAR_PA_Pos (0U) |
| 4047 | #define DMA_CPAR_PA_Pos (0U) |
4047 | #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ |
| 4048 | #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ |
4048 | #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ |
| 4049 | #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ |
4049 | |
| 4050 | 4050 | /****************** Bit definition for DMA_CMAR register *******************/ |
|
| 4051 | /****************** Bit definition for DMA_CMAR register *******************/ |
4051 | #define DMA_CMAR_MA_Pos (0U) |
| 4052 | #define DMA_CMAR_MA_Pos (0U) |
4052 | #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
| 4053 | #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ |
4053 | #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ |
| 4054 | #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ |
4054 | |
| 4055 | 4055 | /******************************************************************************/ |
|
| 4056 | /******************************************************************************/ |
4056 | /* */ |
| 4057 | /* */ |
4057 | /* Analog to Digital Converter (ADC) */ |
| 4058 | /* Analog to Digital Converter (ADC) */ |
4058 | /* */ |
| 4059 | /* */ |
4059 | /******************************************************************************/ |
| 4060 | /******************************************************************************/ |
4060 | |
| 4061 | 4061 | /* |
|
| 4062 | /* |
4062 | * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) |
| 4063 | * @brief Specific device feature definitions (not present on all devices in the STM32F1 family) |
4063 | */ |
| 4064 | */ |
4064 | #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ |
| 4065 | #define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ |
4065 | |
| 4066 | 4066 | /******************** Bit definition for ADC_SR register ********************/ |
|
| 4067 | /******************** Bit definition for ADC_SR register ********************/ |
4067 | #define ADC_SR_AWD_Pos (0U) |
| 4068 | #define ADC_SR_AWD_Pos (0U) |
4068 | #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ |
| 4069 | #define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000001 */ |
4069 | #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ |
| 4070 | #define ADC_SR_AWD ADC_SR_AWD_Msk /*!< ADC analog watchdog 1 flag */ |
4070 | #define ADC_SR_EOS_Pos (1U) |
| 4071 | #define ADC_SR_EOS_Pos (1U) |
4071 | #define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */ |
| 4072 | #define ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos) /*!< 0x00000002 */ |
4072 | #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ |
| 4073 | #define ADC_SR_EOS ADC_SR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ |
4073 | #define ADC_SR_JEOS_Pos (2U) |
| 4074 | #define ADC_SR_JEOS_Pos (2U) |
4074 | #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ |
| 4075 | #define ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos) /*!< 0x00000004 */ |
4075 | #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ |
| 4076 | #define ADC_SR_JEOS ADC_SR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ |
4076 | #define ADC_SR_JSTRT_Pos (3U) |
| 4077 | #define ADC_SR_JSTRT_Pos (3U) |
4077 | #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ |
| 4078 | #define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000008 */ |
4078 | #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ |
| 4079 | #define ADC_SR_JSTRT ADC_SR_JSTRT_Msk /*!< ADC group injected conversion start flag */ |
4079 | #define ADC_SR_STRT_Pos (4U) |
| 4080 | #define ADC_SR_STRT_Pos (4U) |
4080 | #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ |
| 4081 | #define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000010 */ |
4081 | #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ |
| 4082 | #define ADC_SR_STRT ADC_SR_STRT_Msk /*!< ADC group regular conversion start flag */ |
4082 | |
| 4083 | 4083 | /* Legacy defines */ |
|
| 4084 | /* Legacy defines */ |
4084 | #define ADC_SR_EOC (ADC_SR_EOS) |
| 4085 | #define ADC_SR_EOC (ADC_SR_EOS) |
4085 | #define ADC_SR_JEOC (ADC_SR_JEOS) |
| 4086 | #define ADC_SR_JEOC (ADC_SR_JEOS) |
4086 | |
| 4087 | 4087 | /******************* Bit definition for ADC_CR1 register ********************/ |
|
| 4088 | /******************* Bit definition for ADC_CR1 register ********************/ |
4088 | #define ADC_CR1_AWDCH_Pos (0U) |
| 4089 | #define ADC_CR1_AWDCH_Pos (0U) |
4089 | #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ |
| 4090 | #define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ |
4090 | #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ |
| 4091 | #define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ |
4091 | #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ |
| 4092 | #define ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ |
4092 | #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ |
| 4093 | #define ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ |
4093 | #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ |
| 4094 | #define ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ |
4094 | #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ |
| 4095 | #define ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ |
4095 | #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ |
| 4096 | #define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ |
4096 | |
| 4097 | 4097 | #define ADC_CR1_EOSIE_Pos (5U) |
|
| 4098 | #define ADC_CR1_EOSIE_Pos (5U) |
4098 | #define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ |
| 4099 | #define ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos) /*!< 0x00000020 */ |
4099 | #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ |
| 4100 | #define ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ |
4100 | #define ADC_CR1_AWDIE_Pos (6U) |
| 4101 | #define ADC_CR1_AWDIE_Pos (6U) |
4101 | #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ |
| 4102 | #define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ |
4102 | #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ |
| 4103 | #define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ |
4103 | #define ADC_CR1_JEOSIE_Pos (7U) |
| 4104 | #define ADC_CR1_JEOSIE_Pos (7U) |
4104 | #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ |
| 4105 | #define ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos) /*!< 0x00000080 */ |
4105 | #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ |
| 4106 | #define ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ |
4106 | #define ADC_CR1_SCAN_Pos (8U) |
| 4107 | #define ADC_CR1_SCAN_Pos (8U) |
4107 | #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ |
| 4108 | #define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ |
4108 | #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ |
| 4109 | #define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< ADC scan mode */ |
4109 | #define ADC_CR1_AWDSGL_Pos (9U) |
| 4110 | #define ADC_CR1_AWDSGL_Pos (9U) |
4110 | #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ |
| 4111 | #define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ |
4111 | #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ |
| 4112 | #define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ |
4112 | #define ADC_CR1_JAUTO_Pos (10U) |
| 4113 | #define ADC_CR1_JAUTO_Pos (10U) |
4113 | #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ |
| 4114 | #define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ |
4114 | #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ |
| 4115 | #define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ |
4115 | #define ADC_CR1_DISCEN_Pos (11U) |
| 4116 | #define ADC_CR1_DISCEN_Pos (11U) |
4116 | #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ |
| 4117 | #define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ |
4117 | #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ |
| 4118 | #define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ |
4118 | #define ADC_CR1_JDISCEN_Pos (12U) |
| 4119 | #define ADC_CR1_JDISCEN_Pos (12U) |
4119 | #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ |
| 4120 | #define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ |
4120 | #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ |
| 4121 | #define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ |
4121 | |
| 4122 | 4122 | #define ADC_CR1_DISCNUM_Pos (13U) |
|
| 4123 | #define ADC_CR1_DISCNUM_Pos (13U) |
4123 | #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ |
| 4124 | #define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ |
4124 | #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ |
| 4125 | #define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ |
4125 | #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ |
| 4126 | #define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ |
4126 | #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ |
| 4127 | #define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ |
4127 | #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ |
| 4128 | #define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ |
4128 | |
| 4129 | 4129 | #define ADC_CR1_DUALMOD_Pos (16U) |
|
| 4130 | #define ADC_CR1_DUALMOD_Pos (16U) |
4130 | #define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ |
| 4131 | #define ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos) /*!< 0x000F0000 */ |
4131 | #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ |
| 4132 | #define ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk /*!< ADC multimode mode selection */ |
4132 | #define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ |
| 4133 | #define ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00010000 */ |
4133 | #define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ |
| 4134 | #define ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00020000 */ |
4134 | #define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ |
| 4135 | #define ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00040000 */ |
4135 | #define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ |
| 4136 | #define ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos) /*!< 0x00080000 */ |
4136 | |
| 4137 | 4137 | #define ADC_CR1_JAWDEN_Pos (22U) |
|
| 4138 | #define ADC_CR1_JAWDEN_Pos (22U) |
4138 | #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ |
| 4139 | #define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ |
4139 | #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ |
| 4140 | #define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ |
4140 | #define ADC_CR1_AWDEN_Pos (23U) |
| 4141 | #define ADC_CR1_AWDEN_Pos (23U) |
4141 | #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ |
| 4142 | #define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ |
4142 | #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ |
| 4143 | #define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ |
4143 | |
| 4144 | 4144 | /* Legacy defines */ |
|
| 4145 | /* Legacy defines */ |
4145 | #define ADC_CR1_EOCIE (ADC_CR1_EOSIE) |
| 4146 | #define ADC_CR1_EOCIE (ADC_CR1_EOSIE) |
4146 | #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) |
| 4147 | #define ADC_CR1_JEOCIE (ADC_CR1_JEOSIE) |
4147 | |
| 4148 | 4148 | /******************* Bit definition for ADC_CR2 register ********************/ |
|
| 4149 | /******************* Bit definition for ADC_CR2 register ********************/ |
4149 | #define ADC_CR2_ADON_Pos (0U) |
| 4150 | #define ADC_CR2_ADON_Pos (0U) |
4150 | #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ |
| 4151 | #define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ |
4151 | #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ |
| 4152 | #define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< ADC enable */ |
4152 | #define ADC_CR2_CONT_Pos (1U) |
| 4153 | #define ADC_CR2_CONT_Pos (1U) |
4153 | #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ |
| 4154 | #define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ |
4154 | #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ |
| 4155 | #define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< ADC group regular continuous conversion mode */ |
4155 | #define ADC_CR2_CAL_Pos (2U) |
| 4156 | #define ADC_CR2_CAL_Pos (2U) |
4156 | #define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ |
| 4157 | #define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ |
4157 | #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ |
| 4158 | #define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< ADC calibration start */ |
4158 | #define ADC_CR2_RSTCAL_Pos (3U) |
| 4159 | #define ADC_CR2_RSTCAL_Pos (3U) |
4159 | #define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ |
| 4160 | #define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ |
4160 | #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ |
| 4161 | #define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk /*!< ADC calibration reset */ |
4161 | #define ADC_CR2_DMA_Pos (8U) |
| 4162 | #define ADC_CR2_DMA_Pos (8U) |
4162 | #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ |
| 4163 | #define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ |
4163 | #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ |
| 4164 | #define ADC_CR2_DMA ADC_CR2_DMA_Msk /*!< ADC DMA transfer enable */ |
4164 | #define ADC_CR2_ALIGN_Pos (11U) |
| 4165 | #define ADC_CR2_ALIGN_Pos (11U) |
4165 | #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ |
| 4166 | #define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ |
4166 | #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignment */ |
| 4167 | #define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< ADC data alignement */ |
4167 | |
| 4168 | 4168 | #define ADC_CR2_JEXTSEL_Pos (12U) |
|
| 4169 | #define ADC_CR2_JEXTSEL_Pos (12U) |
4169 | #define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ |
| 4170 | #define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ |
4170 | #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ |
| 4171 | #define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< ADC group injected external trigger source */ |
4171 | #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ |
| 4172 | #define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ |
4172 | #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ |
| 4173 | #define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ |
4173 | #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ |
| 4174 | #define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ |
4174 | |
| 4175 | 4175 | #define ADC_CR2_JEXTTRIG_Pos (15U) |
|
| 4176 | #define ADC_CR2_JEXTTRIG_Pos (15U) |
4176 | #define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ |
| 4177 | #define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ |
4177 | #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ |
| 4178 | #define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< ADC group injected external trigger enable */ |
4178 | |
| 4179 | 4179 | #define ADC_CR2_EXTSEL_Pos (17U) |
|
| 4180 | #define ADC_CR2_EXTSEL_Pos (17U) |
4180 | #define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ |
| 4181 | #define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ |
4181 | #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ |
| 4182 | #define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< ADC group regular external trigger source */ |
4182 | #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ |
| 4183 | #define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ |
4183 | #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ |
| 4184 | #define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ |
4184 | #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ |
| 4185 | #define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ |
4185 | |
| 4186 | 4186 | #define ADC_CR2_EXTTRIG_Pos (20U) |
|
| 4187 | #define ADC_CR2_EXTTRIG_Pos (20U) |
4187 | #define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ |
| 4188 | #define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ |
4188 | #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ |
| 4189 | #define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< ADC group regular external trigger enable */ |
4189 | #define ADC_CR2_JSWSTART_Pos (21U) |
| 4190 | #define ADC_CR2_JSWSTART_Pos (21U) |
4190 | #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ |
| 4191 | #define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ |
4191 | #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ |
| 4192 | #define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< ADC group injected conversion start */ |
4192 | #define ADC_CR2_SWSTART_Pos (22U) |
| 4193 | #define ADC_CR2_SWSTART_Pos (22U) |
4193 | #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ |
| 4194 | #define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ |
4194 | #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ |
| 4195 | #define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< ADC group regular conversion start */ |
4195 | #define ADC_CR2_TSVREFE_Pos (23U) |
| 4196 | #define ADC_CR2_TSVREFE_Pos (23U) |
4196 | #define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ |
| 4197 | #define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ |
4197 | #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ |
| 4198 | #define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk /*!< ADC internal path to VrefInt and temperature sensor enable */ |
4198 | |
| 4199 | 4199 | /****************** Bit definition for ADC_SMPR1 register *******************/ |
|
| 4200 | /****************** Bit definition for ADC_SMPR1 register *******************/ |
4200 | #define ADC_SMPR1_SMP10_Pos (0U) |
| 4201 | #define ADC_SMPR1_SMP10_Pos (0U) |
4201 | #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ |
| 4202 | #define ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000007 */ |
4202 | #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ |
| 4203 | #define ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk /*!< ADC channel 10 sampling time selection */ |
4203 | #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ |
| 4204 | #define ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000001 */ |
4204 | #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ |
| 4205 | #define ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000002 */ |
4205 | #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ |
| 4206 | #define ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos) /*!< 0x00000004 */ |
4206 | |
| 4207 | 4207 | #define ADC_SMPR1_SMP11_Pos (3U) |
|
| 4208 | #define ADC_SMPR1_SMP11_Pos (3U) |
4208 | #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ |
| 4209 | #define ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000038 */ |
4209 | #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ |
| 4210 | #define ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk /*!< ADC channel 11 sampling time selection */ |
4210 | #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ |
| 4211 | #define ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000008 */ |
4211 | #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ |
| 4212 | #define ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000010 */ |
4212 | #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ |
| 4213 | #define ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos) /*!< 0x00000020 */ |
4213 | |
| 4214 | 4214 | #define ADC_SMPR1_SMP12_Pos (6U) |
|
| 4215 | #define ADC_SMPR1_SMP12_Pos (6U) |
4215 | #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ |
| 4216 | #define ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos) /*!< 0x000001C0 */ |
4216 | #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ |
| 4217 | #define ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk /*!< ADC channel 12 sampling time selection */ |
4217 | #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ |
| 4218 | #define ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000040 */ |
4218 | #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ |
| 4219 | #define ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000080 */ |
4219 | #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ |
| 4220 | #define ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos) /*!< 0x00000100 */ |
4220 | |
| 4221 | 4221 | #define ADC_SMPR1_SMP13_Pos (9U) |
|
| 4222 | #define ADC_SMPR1_SMP13_Pos (9U) |
4222 | #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ |
| 4223 | #define ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000E00 */ |
4223 | #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ |
| 4224 | #define ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk /*!< ADC channel 13 sampling time selection */ |
4224 | #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ |
| 4225 | #define ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000200 */ |
4225 | #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ |
| 4226 | #define ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000400 */ |
4226 | #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ |
| 4227 | #define ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos) /*!< 0x00000800 */ |
4227 | |
| 4228 | 4228 | #define ADC_SMPR1_SMP14_Pos (12U) |
|
| 4229 | #define ADC_SMPR1_SMP14_Pos (12U) |
4229 | #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ |
| 4230 | #define ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00007000 */ |
4230 | #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ |
| 4231 | #define ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk /*!< ADC channel 14 sampling time selection */ |
4231 | #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ |
| 4232 | #define ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00001000 */ |
4232 | #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ |
| 4233 | #define ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00002000 */ |
4233 | #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ |
| 4234 | #define ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos) /*!< 0x00004000 */ |
4234 | |
| 4235 | 4235 | #define ADC_SMPR1_SMP15_Pos (15U) |
|
| 4236 | #define ADC_SMPR1_SMP15_Pos (15U) |
4236 | #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ |
| 4237 | #define ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00038000 */ |
4237 | #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ |
| 4238 | #define ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk /*!< ADC channel 15 sampling time selection */ |
4238 | #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ |
| 4239 | #define ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00008000 */ |
4239 | #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ |
| 4240 | #define ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00010000 */ |
4240 | #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ |
| 4241 | #define ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos) /*!< 0x00020000 */ |
4241 | |
| 4242 | 4242 | #define ADC_SMPR1_SMP16_Pos (18U) |
|
| 4243 | #define ADC_SMPR1_SMP16_Pos (18U) |
4243 | #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ |
| 4244 | #define ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos) /*!< 0x001C0000 */ |
4244 | #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ |
| 4245 | #define ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk /*!< ADC channel 16 sampling time selection */ |
4245 | #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ |
| 4246 | #define ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00040000 */ |
4246 | #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ |
| 4247 | #define ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00080000 */ |
4247 | #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ |
| 4248 | #define ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos) /*!< 0x00100000 */ |
4248 | |
| 4249 | 4249 | #define ADC_SMPR1_SMP17_Pos (21U) |
|
| 4250 | #define ADC_SMPR1_SMP17_Pos (21U) |
4250 | #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ |
| 4251 | #define ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00E00000 */ |
4251 | #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ |
| 4252 | #define ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk /*!< ADC channel 17 sampling time selection */ |
4252 | #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ |
| 4253 | #define ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00200000 */ |
4253 | #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ |
| 4254 | #define ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00400000 */ |
4254 | #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ |
| 4255 | #define ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos) /*!< 0x00800000 */ |
4255 | |
| 4256 | 4256 | /****************** Bit definition for ADC_SMPR2 register *******************/ |
|
| 4257 | /****************** Bit definition for ADC_SMPR2 register *******************/ |
4257 | #define ADC_SMPR2_SMP0_Pos (0U) |
| 4258 | #define ADC_SMPR2_SMP0_Pos (0U) |
4258 | #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ |
| 4259 | #define ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000007 */ |
4259 | #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ |
| 4260 | #define ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk /*!< ADC channel 0 sampling time selection */ |
4260 | #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ |
| 4261 | #define ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000001 */ |
4261 | #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ |
| 4262 | #define ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000002 */ |
4262 | #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ |
| 4263 | #define ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos) /*!< 0x00000004 */ |
4263 | |
| 4264 | 4264 | #define ADC_SMPR2_SMP1_Pos (3U) |
|
| 4265 | #define ADC_SMPR2_SMP1_Pos (3U) |
4265 | #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ |
| 4266 | #define ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000038 */ |
4266 | #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ |
| 4267 | #define ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk /*!< ADC channel 1 sampling time selection */ |
4267 | #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ |
| 4268 | #define ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000008 */ |
4268 | #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ |
| 4269 | #define ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000010 */ |
4269 | #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ |
| 4270 | #define ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos) /*!< 0x00000020 */ |
4270 | |
| 4271 | 4271 | #define ADC_SMPR2_SMP2_Pos (6U) |
|
| 4272 | #define ADC_SMPR2_SMP2_Pos (6U) |
4272 | #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ |
| 4273 | #define ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos) /*!< 0x000001C0 */ |
4273 | #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ |
| 4274 | #define ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk /*!< ADC channel 2 sampling time selection */ |
4274 | #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ |
| 4275 | #define ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000040 */ |
4275 | #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ |
| 4276 | #define ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000080 */ |
4276 | #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ |
| 4277 | #define ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos) /*!< 0x00000100 */ |
4277 | |
| 4278 | 4278 | #define ADC_SMPR2_SMP3_Pos (9U) |
|
| 4279 | #define ADC_SMPR2_SMP3_Pos (9U) |
4279 | #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ |
| 4280 | #define ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000E00 */ |
4280 | #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ |
| 4281 | #define ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk /*!< ADC channel 3 sampling time selection */ |
4281 | #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ |
| 4282 | #define ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000200 */ |
4282 | #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ |
| 4283 | #define ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000400 */ |
4283 | #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ |
| 4284 | #define ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos) /*!< 0x00000800 */ |
4284 | |
| 4285 | 4285 | #define ADC_SMPR2_SMP4_Pos (12U) |
|
| 4286 | #define ADC_SMPR2_SMP4_Pos (12U) |
4286 | #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ |
| 4287 | #define ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00007000 */ |
4287 | #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ |
| 4288 | #define ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk /*!< ADC channel 4 sampling time selection */ |
4288 | #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ |
| 4289 | #define ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00001000 */ |
4289 | #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ |
| 4290 | #define ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00002000 */ |
4290 | #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ |
| 4291 | #define ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos) /*!< 0x00004000 */ |
4291 | |
| 4292 | 4292 | #define ADC_SMPR2_SMP5_Pos (15U) |
|
| 4293 | #define ADC_SMPR2_SMP5_Pos (15U) |
4293 | #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ |
| 4294 | #define ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00038000 */ |
4294 | #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ |
| 4295 | #define ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk /*!< ADC channel 5 sampling time selection */ |
4295 | #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ |
| 4296 | #define ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00008000 */ |
4296 | #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ |
| 4297 | #define ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00010000 */ |
4297 | #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ |
| 4298 | #define ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos) /*!< 0x00020000 */ |
4298 | |
| 4299 | 4299 | #define ADC_SMPR2_SMP6_Pos (18U) |
|
| 4300 | #define ADC_SMPR2_SMP6_Pos (18U) |
4300 | #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ |
| 4301 | #define ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos) /*!< 0x001C0000 */ |
4301 | #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ |
| 4302 | #define ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk /*!< ADC channel 6 sampling time selection */ |
4302 | #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ |
| 4303 | #define ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00040000 */ |
4303 | #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ |
| 4304 | #define ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00080000 */ |
4304 | #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ |
| 4305 | #define ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos) /*!< 0x00100000 */ |
4305 | |
| 4306 | 4306 | #define ADC_SMPR2_SMP7_Pos (21U) |
|
| 4307 | #define ADC_SMPR2_SMP7_Pos (21U) |
4307 | #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ |
| 4308 | #define ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00E00000 */ |
4308 | #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ |
| 4309 | #define ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk /*!< ADC channel 7 sampling time selection */ |
4309 | #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ |
| 4310 | #define ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00200000 */ |
4310 | #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ |
| 4311 | #define ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00400000 */ |
4311 | #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ |
| 4312 | #define ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos) /*!< 0x00800000 */ |
4312 | |
| 4313 | 4313 | #define ADC_SMPR2_SMP8_Pos (24U) |
|
| 4314 | #define ADC_SMPR2_SMP8_Pos (24U) |
4314 | #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ |
| 4315 | #define ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos) /*!< 0x07000000 */ |
4315 | #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ |
| 4316 | #define ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk /*!< ADC channel 8 sampling time selection */ |
4316 | #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ |
| 4317 | #define ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos) /*!< 0x01000000 */ |
4317 | #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ |
| 4318 | #define ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos) /*!< 0x02000000 */ |
4318 | #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ |
| 4319 | #define ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos) /*!< 0x04000000 */ |
4319 | |
| 4320 | 4320 | #define ADC_SMPR2_SMP9_Pos (27U) |
|
| 4321 | #define ADC_SMPR2_SMP9_Pos (27U) |
4321 | #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ |
| 4322 | #define ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos) /*!< 0x38000000 */ |
4322 | #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ |
| 4323 | #define ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk /*!< ADC channel 9 sampling time selection */ |
4323 | #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ |
| 4324 | #define ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos) /*!< 0x08000000 */ |
4324 | #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ |
| 4325 | #define ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos) /*!< 0x10000000 */ |
4325 | #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ |
| 4326 | #define ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos) /*!< 0x20000000 */ |
4326 | |
| 4327 | 4327 | /****************** Bit definition for ADC_JOFR1 register *******************/ |
|
| 4328 | /****************** Bit definition for ADC_JOFR1 register *******************/ |
4328 | #define ADC_JOFR1_JOFFSET1_Pos (0U) |
| 4329 | #define ADC_JOFR1_JOFFSET1_Pos (0U) |
4329 | #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ |
| 4330 | #define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ |
4330 | #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ |
| 4331 | #define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< ADC group injected sequencer rank 1 offset value */ |
4331 | |
| 4332 | 4332 | /****************** Bit definition for ADC_JOFR2 register *******************/ |
|
| 4333 | /****************** Bit definition for ADC_JOFR2 register *******************/ |
4333 | #define ADC_JOFR2_JOFFSET2_Pos (0U) |
| 4334 | #define ADC_JOFR2_JOFFSET2_Pos (0U) |
4334 | #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ |
| 4335 | #define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ |
4335 | #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ |
| 4336 | #define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< ADC group injected sequencer rank 2 offset value */ |
4336 | |
| 4337 | 4337 | /****************** Bit definition for ADC_JOFR3 register *******************/ |
|
| 4338 | /****************** Bit definition for ADC_JOFR3 register *******************/ |
4338 | #define ADC_JOFR3_JOFFSET3_Pos (0U) |
| 4339 | #define ADC_JOFR3_JOFFSET3_Pos (0U) |
4339 | #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ |
| 4340 | #define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ |
4340 | #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ |
| 4341 | #define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< ADC group injected sequencer rank 3 offset value */ |
4341 | |
| 4342 | 4342 | /****************** Bit definition for ADC_JOFR4 register *******************/ |
|
| 4343 | /****************** Bit definition for ADC_JOFR4 register *******************/ |
4343 | #define ADC_JOFR4_JOFFSET4_Pos (0U) |
| 4344 | #define ADC_JOFR4_JOFFSET4_Pos (0U) |
4344 | #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ |
| 4345 | #define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ |
4345 | #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ |
| 4346 | #define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< ADC group injected sequencer rank 4 offset value */ |
4346 | |
| 4347 | 4347 | /******************* Bit definition for ADC_HTR register ********************/ |
|
| 4348 | /******************* Bit definition for ADC_HTR register ********************/ |
4348 | #define ADC_HTR_HT_Pos (0U) |
| 4349 | #define ADC_HTR_HT_Pos (0U) |
4349 | #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ |
| 4350 | #define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ |
4350 | #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ |
| 4351 | #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC analog watchdog 1 threshold high */ |
4351 | |
| 4352 | 4352 | /******************* Bit definition for ADC_LTR register ********************/ |
|
| 4353 | /******************* Bit definition for ADC_LTR register ********************/ |
4353 | #define ADC_LTR_LT_Pos (0U) |
| 4354 | #define ADC_LTR_LT_Pos (0U) |
4354 | #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ |
| 4355 | #define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ |
4355 | #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ |
| 4356 | #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ |
4356 | |
| 4357 | 4357 | /******************* Bit definition for ADC_SQR1 register *******************/ |
|
| 4358 | /******************* Bit definition for ADC_SQR1 register *******************/ |
4358 | #define ADC_SQR1_SQ13_Pos (0U) |
| 4359 | #define ADC_SQR1_SQ13_Pos (0U) |
4359 | #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ |
| 4360 | #define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ |
4360 | #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ |
| 4361 | #define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ |
4361 | #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ |
| 4362 | #define ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ |
4362 | #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ |
| 4363 | #define ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ |
4363 | #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ |
| 4364 | #define ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ |
4364 | #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ |
| 4365 | #define ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ |
4365 | #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ |
| 4366 | #define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ |
4366 | |
| 4367 | 4367 | #define ADC_SQR1_SQ14_Pos (5U) |
|
| 4368 | #define ADC_SQR1_SQ14_Pos (5U) |
4368 | #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ |
| 4369 | #define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ |
4369 | #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ |
| 4370 | #define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ |
4370 | #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ |
| 4371 | #define ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ |
4371 | #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ |
| 4372 | #define ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ |
4372 | #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ |
| 4373 | #define ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ |
4373 | #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ |
| 4374 | #define ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ |
4374 | #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ |
| 4375 | #define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ |
4375 | |
| 4376 | 4376 | #define ADC_SQR1_SQ15_Pos (10U) |
|
| 4377 | #define ADC_SQR1_SQ15_Pos (10U) |
4377 | #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ |
| 4378 | #define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ |
4378 | #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ |
| 4379 | #define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ |
4379 | #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ |
| 4380 | #define ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ |
4380 | #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ |
| 4381 | #define ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ |
4381 | #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ |
| 4382 | #define ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ |
4382 | #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ |
| 4383 | #define ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ |
4383 | #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ |
| 4384 | #define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ |
4384 | |
| 4385 | 4385 | #define ADC_SQR1_SQ16_Pos (15U) |
|
| 4386 | #define ADC_SQR1_SQ16_Pos (15U) |
4386 | #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ |
| 4387 | #define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ |
4387 | #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ |
| 4388 | #define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ |
4388 | #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ |
| 4389 | #define ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ |
4389 | #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ |
| 4390 | #define ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ |
4390 | #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ |
| 4391 | #define ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ |
4391 | #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ |
| 4392 | #define ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ |
4392 | #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ |
| 4393 | #define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ |
4393 | |
| 4394 | 4394 | #define ADC_SQR1_L_Pos (20U) |
|
| 4395 | #define ADC_SQR1_L_Pos (20U) |
4395 | #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ |
| 4396 | #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ |
4396 | #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ |
| 4397 | #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ |
4397 | #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ |
| 4398 | #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ |
4398 | #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ |
| 4399 | #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ |
4399 | #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ |
| 4400 | #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ |
4400 | #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ |
| 4401 | #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00800000 */ |
4401 | |
| 4402 | 4402 | /******************* Bit definition for ADC_SQR2 register *******************/ |
|
| 4403 | /******************* Bit definition for ADC_SQR2 register *******************/ |
4403 | #define ADC_SQR2_SQ7_Pos (0U) |
| 4404 | #define ADC_SQR2_SQ7_Pos (0U) |
4404 | #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ |
| 4405 | #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ |
4405 | #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ |
| 4406 | #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ |
4406 | #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ |
| 4407 | #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ |
4407 | #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ |
| 4408 | #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ |
4408 | #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ |
| 4409 | #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ |
4409 | #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ |
| 4410 | #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ |
4410 | #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ |
| 4411 | #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ |
4411 | |
| 4412 | 4412 | #define ADC_SQR2_SQ8_Pos (5U) |
|
| 4413 | #define ADC_SQR2_SQ8_Pos (5U) |
4413 | #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ |
| 4414 | #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ |
4414 | #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ |
| 4415 | #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ |
4415 | #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ |
| 4416 | #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ |
4416 | #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ |
| 4417 | #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ |
4417 | #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ |
| 4418 | #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ |
4418 | #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ |
| 4419 | #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ |
4419 | #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ |
| 4420 | #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ |
4420 | |
| 4421 | 4421 | #define ADC_SQR2_SQ9_Pos (10U) |
|
| 4422 | #define ADC_SQR2_SQ9_Pos (10U) |
4422 | #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ |
| 4423 | #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ |
4423 | #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ |
| 4424 | #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ |
4424 | #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ |
| 4425 | #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ |
4425 | #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ |
| 4426 | #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ |
4426 | #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ |
| 4427 | #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ |
4427 | #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ |
| 4428 | #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ |
4428 | #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ |
| 4429 | #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ |
4429 | |
| 4430 | 4430 | #define ADC_SQR2_SQ10_Pos (15U) |
|
| 4431 | #define ADC_SQR2_SQ10_Pos (15U) |
4431 | #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ |
| 4432 | #define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ |
4432 | #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ |
| 4433 | #define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ |
4433 | #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ |
| 4434 | #define ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ |
4434 | #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ |
| 4435 | #define ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ |
4435 | #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ |
| 4436 | #define ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ |
4436 | #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ |
| 4437 | #define ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ |
4437 | #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ |
| 4438 | #define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ |
4438 | |
| 4439 | 4439 | #define ADC_SQR2_SQ11_Pos (20U) |
|
| 4440 | #define ADC_SQR2_SQ11_Pos (20U) |
4440 | #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ |
| 4441 | #define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ |
4441 | #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ |
| 4442 | #define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< ADC group regular sequencer rank 1 */ |
4442 | #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ |
| 4443 | #define ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ |
4443 | #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ |
| 4444 | #define ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ |
4444 | #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ |
| 4445 | #define ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ |
4445 | #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ |
| 4446 | #define ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ |
4446 | #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ |
| 4447 | #define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ |
4447 | |
| 4448 | 4448 | #define ADC_SQR2_SQ12_Pos (25U) |
|
| 4449 | #define ADC_SQR2_SQ12_Pos (25U) |
4449 | #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ |
| 4450 | #define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ |
4450 | #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ |
| 4451 | #define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ |
4451 | #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ |
| 4452 | #define ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ |
4452 | #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ |
| 4453 | #define ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ |
4453 | #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ |
| 4454 | #define ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ |
4454 | #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ |
| 4455 | #define ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ |
4455 | #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ |
| 4456 | #define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ |
4456 | |
| 4457 | 4457 | /******************* Bit definition for ADC_SQR3 register *******************/ |
|
| 4458 | /******************* Bit definition for ADC_SQR3 register *******************/ |
4458 | #define ADC_SQR3_SQ1_Pos (0U) |
| 4459 | #define ADC_SQR3_SQ1_Pos (0U) |
4459 | #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ |
| 4460 | #define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ |
4460 | #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ |
| 4461 | #define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ |
4461 | #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ |
| 4462 | #define ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ |
4462 | #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ |
| 4463 | #define ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ |
4463 | #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ |
| 4464 | #define ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ |
4464 | #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ |
| 4465 | #define ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ |
4465 | #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ |
| 4466 | #define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ |
4466 | |
| 4467 | 4467 | #define ADC_SQR3_SQ2_Pos (5U) |
|
| 4468 | #define ADC_SQR3_SQ2_Pos (5U) |
4468 | #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ |
| 4469 | #define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ |
4469 | #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ |
| 4470 | #define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ |
4470 | #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ |
| 4471 | #define ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ |
4471 | #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ |
| 4472 | #define ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ |
4472 | #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ |
| 4473 | #define ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ |
4473 | #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ |
| 4474 | #define ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ |
4474 | #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ |
| 4475 | #define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ |
4475 | |
| 4476 | 4476 | #define ADC_SQR3_SQ3_Pos (10U) |
|
| 4477 | #define ADC_SQR3_SQ3_Pos (10U) |
4477 | #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ |
| 4478 | #define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ |
4478 | #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ |
| 4479 | #define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ |
4479 | #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ |
| 4480 | #define ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ |
4480 | #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ |
| 4481 | #define ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ |
4481 | #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ |
| 4482 | #define ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ |
4482 | #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ |
| 4483 | #define ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ |
4483 | #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ |
| 4484 | #define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ |
4484 | |
| 4485 | 4485 | #define ADC_SQR3_SQ4_Pos (15U) |
|
| 4486 | #define ADC_SQR3_SQ4_Pos (15U) |
4486 | #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ |
| 4487 | #define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ |
4487 | #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ |
| 4488 | #define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ |
4488 | #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ |
| 4489 | #define ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ |
4489 | #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ |
| 4490 | #define ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ |
4490 | #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ |
| 4491 | #define ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ |
4491 | #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ |
| 4492 | #define ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ |
4492 | #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ |
| 4493 | #define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) /*!< 0x00080000 */ |
4493 | |
| 4494 | 4494 | #define ADC_SQR3_SQ5_Pos (20U) |
|
| 4495 | #define ADC_SQR3_SQ5_Pos (20U) |
4495 | #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ |
| 4496 | #define ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos) /*!< 0x01F00000 */ |
4496 | #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ |
| 4497 | #define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ |
4497 | #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ |
| 4498 | #define ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos) /*!< 0x00100000 */ |
4498 | #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ |
| 4499 | #define ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos) /*!< 0x00200000 */ |
4499 | #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ |
| 4500 | #define ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos) /*!< 0x00400000 */ |
4500 | #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ |
| 4501 | #define ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos) /*!< 0x00800000 */ |
4501 | #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ |
| 4502 | #define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ |
4502 | |
| 4503 | 4503 | #define ADC_SQR3_SQ6_Pos (25U) |
|
| 4504 | #define ADC_SQR3_SQ6_Pos (25U) |
4504 | #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ |
| 4505 | #define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ |
4505 | #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ |
| 4506 | #define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ |
4506 | #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ |
| 4507 | #define ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ |
4507 | #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ |
| 4508 | #define ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ |
4508 | #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ |
| 4509 | #define ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ |
4509 | #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ |
| 4510 | #define ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ |
4510 | #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ |
| 4511 | #define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) /*!< 0x20000000 */ |
4511 | |
| 4512 | 4512 | /******************* Bit definition for ADC_JSQR register *******************/ |
|
| 4513 | /******************* Bit definition for ADC_JSQR register *******************/ |
4513 | #define ADC_JSQR_JSQ1_Pos (0U) |
| 4514 | #define ADC_JSQR_JSQ1_Pos (0U) |
4514 | #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ |
| 4515 | #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ |
4515 | #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ |
| 4516 | #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ |
4516 | #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ |
| 4517 | #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ |
4517 | #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ |
| 4518 | #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ |
4518 | #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ |
| 4519 | #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ |
4519 | #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ |
| 4520 | #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ |
4520 | #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ |
| 4521 | #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ |
4521 | |
| 4522 | 4522 | #define ADC_JSQR_JSQ2_Pos (5U) |
|
| 4523 | #define ADC_JSQR_JSQ2_Pos (5U) |
4523 | #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ |
| 4524 | #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ |
4524 | #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ |
| 4525 | #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ |
4525 | #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ |
| 4526 | #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ |
4526 | #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ |
| 4527 | #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ |
4527 | #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ |
| 4528 | #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ |
4528 | #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ |
| 4529 | #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ |
4529 | #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ |
| 4530 | #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ |
4530 | |
| 4531 | 4531 | #define ADC_JSQR_JSQ3_Pos (10U) |
|
| 4532 | #define ADC_JSQR_JSQ3_Pos (10U) |
4532 | #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ |
| 4533 | #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ |
4533 | #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ |
| 4534 | #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ |
4534 | #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ |
| 4535 | #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ |
4535 | #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ |
| 4536 | #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ |
4536 | #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ |
| 4537 | #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ |
4537 | #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ |
| 4538 | #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ |
4538 | #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ |
| 4539 | #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ |
4539 | |
| 4540 | 4540 | #define ADC_JSQR_JSQ4_Pos (15U) |
|
| 4541 | #define ADC_JSQR_JSQ4_Pos (15U) |
4541 | #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ |
| 4542 | #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ |
4542 | #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ |
| 4543 | #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ |
4543 | #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ |
| 4544 | #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ |
4544 | #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ |
| 4545 | #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ |
4545 | #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ |
| 4546 | #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ |
4546 | #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ |
| 4547 | #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ |
4547 | #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ |
| 4548 | #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ |
4548 | |
| 4549 | 4549 | #define ADC_JSQR_JL_Pos (20U) |
|
| 4550 | #define ADC_JSQR_JL_Pos (20U) |
4550 | #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ |
| 4551 | #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ |
4551 | #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ |
| 4552 | #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ |
4552 | #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ |
| 4553 | #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ |
4553 | #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ |
| 4554 | #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ |
4554 | |
| 4555 | 4555 | /******************* Bit definition for ADC_JDR1 register *******************/ |
|
| 4556 | /******************* Bit definition for ADC_JDR1 register *******************/ |
4556 | #define ADC_JDR1_JDATA_Pos (0U) |
| 4557 | #define ADC_JDR1_JDATA_Pos (0U) |
4557 | #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ |
| 4558 | #define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ |
4558 | #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ |
| 4559 | #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ |
4559 | |
| 4560 | 4560 | /******************* Bit definition for ADC_JDR2 register *******************/ |
|
| 4561 | /******************* Bit definition for ADC_JDR2 register *******************/ |
4561 | #define ADC_JDR2_JDATA_Pos (0U) |
| 4562 | #define ADC_JDR2_JDATA_Pos (0U) |
4562 | #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ |
| 4563 | #define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ |
4563 | #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ |
| 4564 | #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ |
4564 | |
| 4565 | 4565 | /******************* Bit definition for ADC_JDR3 register *******************/ |
|
| 4566 | /******************* Bit definition for ADC_JDR3 register *******************/ |
4566 | #define ADC_JDR3_JDATA_Pos (0U) |
| 4567 | #define ADC_JDR3_JDATA_Pos (0U) |
4567 | #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ |
| 4568 | #define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ |
4568 | #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ |
| 4569 | #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ |
4569 | |
| 4570 | 4570 | /******************* Bit definition for ADC_JDR4 register *******************/ |
|
| 4571 | /******************* Bit definition for ADC_JDR4 register *******************/ |
4571 | #define ADC_JDR4_JDATA_Pos (0U) |
| 4572 | #define ADC_JDR4_JDATA_Pos (0U) |
4572 | #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ |
| 4573 | #define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ |
4573 | #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ |
| 4574 | #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ |
4574 | |
| 4575 | 4575 | /******************** Bit definition for ADC_DR register ********************/ |
|
| 4576 | /******************** Bit definition for ADC_DR register ********************/ |
4576 | #define ADC_DR_DATA_Pos (0U) |
| 4577 | #define ADC_DR_DATA_Pos (0U) |
4577 | #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ |
| 4578 | #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ |
4578 | #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ |
| 4579 | #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ |
4579 | #define ADC_DR_ADC2DATA_Pos (16U) |
| 4580 | #define ADC_DR_ADC2DATA_Pos (16U) |
4580 | #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ |
| 4581 | #define ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos) /*!< 0xFFFF0000 */ |
4581 | #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ |
| 4582 | #define ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk /*!< ADC group regular conversion data for ADC slave, in multimode */ |
4582 | /******************************************************************************/ |
| 4583 | /******************************************************************************/ |
4583 | /* */ |
| 4584 | /* */ |
4584 | /* Digital to Analog Converter */ |
| 4585 | /* Digital to Analog Converter */ |
4585 | /* */ |
| 4586 | /* */ |
4586 | /******************************************************************************/ |
| 4587 | /******************************************************************************/ |
4587 | |
| 4588 | 4588 | /******************** Bit definition for DAC_CR register ********************/ |
|
| 4589 | /******************** Bit definition for DAC_CR register ********************/ |
4589 | #define DAC_CR_EN1_Pos (0U) |
| 4590 | #define DAC_CR_EN1_Pos (0U) |
4590 | #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ |
| 4591 | #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ |
4591 | #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ |
| 4592 | #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< DAC channel1 enable */ |
4592 | #define DAC_CR_BOFF1_Pos (1U) |
| 4593 | #define DAC_CR_BOFF1_Pos (1U) |
4593 | #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ |
| 4594 | #define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ |
4594 | #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ |
| 4595 | #define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< DAC channel1 output buffer disable */ |
4595 | #define DAC_CR_TEN1_Pos (2U) |
| 4596 | #define DAC_CR_TEN1_Pos (2U) |
4596 | #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ |
| 4597 | #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ |
4597 | #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ |
| 4598 | #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< DAC channel1 Trigger enable */ |
4598 | |
| 4599 | 4599 | #define DAC_CR_TSEL1_Pos (3U) |
|
| 4600 | #define DAC_CR_TSEL1_Pos (3U) |
4600 | #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ |
| 4601 | #define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ |
4601 | #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ |
| 4602 | #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */ |
4602 | #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ |
| 4603 | #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ |
4603 | #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ |
| 4604 | #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ |
4604 | #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ |
| 4605 | #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ |
4605 | |
| 4606 | 4606 | #define DAC_CR_WAVE1_Pos (6U) |
|
| 4607 | #define DAC_CR_WAVE1_Pos (6U) |
4607 | #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ |
| 4608 | #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ |
4608 | #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
| 4609 | #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ |
4609 | #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ |
| 4610 | #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ |
4610 | #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ |
| 4611 | #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ |
4611 | |
| 4612 | 4612 | #define DAC_CR_MAMP1_Pos (8U) |
|
| 4613 | #define DAC_CR_MAMP1_Pos (8U) |
4613 | #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ |
| 4614 | #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ |
4614 | #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
| 4615 | #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ |
4615 | #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ |
| 4616 | #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ |
4616 | #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ |
| 4617 | #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ |
4617 | #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ |
| 4618 | #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ |
4618 | #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ |
| 4619 | #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ |
4619 | |
| 4620 | 4620 | #define DAC_CR_DMAEN1_Pos (12U) |
|
| 4621 | #define DAC_CR_DMAEN1_Pos (12U) |
4621 | #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ |
| 4622 | #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ |
4622 | #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ |
| 4623 | #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< DAC channel1 DMA enable */ |
4623 | #define DAC_CR_EN2_Pos (16U) |
| 4624 | #define DAC_CR_EN2_Pos (16U) |
4624 | #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ |
| 4625 | #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ |
4625 | #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ |
| 4626 | #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< DAC channel2 enable */ |
4626 | #define DAC_CR_BOFF2_Pos (17U) |
| 4627 | #define DAC_CR_BOFF2_Pos (17U) |
4627 | #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ |
| 4628 | #define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ |
4628 | #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ |
| 4629 | #define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< DAC channel2 output buffer disable */ |
4629 | #define DAC_CR_TEN2_Pos (18U) |
| 4630 | #define DAC_CR_TEN2_Pos (18U) |
4630 | #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ |
| 4631 | #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ |
4631 | #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ |
| 4632 | #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< DAC channel2 Trigger enable */ |
4632 | |
| 4633 | 4633 | #define DAC_CR_TSEL2_Pos (19U) |
|
| 4634 | #define DAC_CR_TSEL2_Pos (19U) |
4634 | #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ |
| 4635 | #define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ |
4635 | #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ |
| 4636 | #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */ |
4636 | #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ |
| 4637 | #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ |
4637 | #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ |
| 4638 | #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ |
4638 | #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ |
| 4639 | #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ |
4639 | |
| 4640 | 4640 | #define DAC_CR_WAVE2_Pos (22U) |
|
| 4641 | #define DAC_CR_WAVE2_Pos (22U) |
4641 | #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ |
| 4642 | #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ |
4642 | #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
| 4643 | #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ |
4643 | #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ |
| 4644 | #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ |
4644 | #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ |
| 4645 | #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ |
4645 | |
| 4646 | 4646 | #define DAC_CR_MAMP2_Pos (24U) |
|
| 4647 | #define DAC_CR_MAMP2_Pos (24U) |
4647 | #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ |
| 4648 | #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ |
4648 | #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
| 4649 | #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ |
4649 | #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ |
| 4650 | #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ |
4650 | #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ |
| 4651 | #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ |
4651 | #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ |
| 4652 | #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ |
4652 | #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ |
| 4653 | #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ |
4653 | |
| 4654 | 4654 | #define DAC_CR_DMAEN2_Pos (28U) |
|
| 4655 | #define DAC_CR_DMAEN2_Pos (28U) |
4655 | #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ |
| 4656 | #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ |
4656 | #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ |
| 4657 | #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< DAC channel2 DMA enabled */ |
4657 | |
| 4658 | 4658 | ||
| 4659 | 4659 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
|
| 4660 | /***************** Bit definition for DAC_SWTRIGR register ******************/ |
4660 | #define DAC_SWTRIGR_SWTRIG1_Pos (0U) |
| 4661 | #define DAC_SWTRIGR_SWTRIG1_Pos (0U) |
4661 | #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ |
| 4662 | #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ |
4662 | #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ |
| 4663 | #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< DAC channel1 software trigger */ |
4663 | #define DAC_SWTRIGR_SWTRIG2_Pos (1U) |
| 4664 | #define DAC_SWTRIGR_SWTRIG2_Pos (1U) |
4664 | #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ |
| 4665 | #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ |
4665 | #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ |
| 4666 | #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< DAC channel2 software trigger */ |
4666 | |
| 4667 | 4667 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
|
| 4668 | /***************** Bit definition for DAC_DHR12R1 register ******************/ |
4668 | #define DAC_DHR12R1_DACC1DHR_Pos (0U) |
| 4669 | #define DAC_DHR12R1_DACC1DHR_Pos (0U) |
4669 | #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ |
| 4670 | #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ |
4670 | #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ |
| 4671 | #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ |
4671 | |
| 4672 | 4672 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
|
| 4673 | /***************** Bit definition for DAC_DHR12L1 register ******************/ |
4673 | #define DAC_DHR12L1_DACC1DHR_Pos (4U) |
| 4674 | #define DAC_DHR12L1_DACC1DHR_Pos (4U) |
4674 | #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
| 4675 | #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
4675 | #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ |
| 4676 | #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ |
4676 | |
| 4677 | 4677 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
|
| 4678 | /****************** Bit definition for DAC_DHR8R1 register ******************/ |
4678 | #define DAC_DHR8R1_DACC1DHR_Pos (0U) |
| 4679 | #define DAC_DHR8R1_DACC1DHR_Pos (0U) |
4679 | #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ |
| 4680 | #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ |
4680 | #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ |
| 4681 | #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ |
4681 | |
| 4682 | 4682 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
|
| 4683 | /***************** Bit definition for DAC_DHR12R2 register ******************/ |
4683 | #define DAC_DHR12R2_DACC2DHR_Pos (0U) |
| 4684 | #define DAC_DHR12R2_DACC2DHR_Pos (0U) |
4684 | #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ |
| 4685 | #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ |
4685 | #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ |
| 4686 | #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ |
4686 | |
| 4687 | 4687 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
|
| 4688 | /***************** Bit definition for DAC_DHR12L2 register ******************/ |
4688 | #define DAC_DHR12L2_DACC2DHR_Pos (4U) |
| 4689 | #define DAC_DHR12L2_DACC2DHR_Pos (4U) |
4689 | #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ |
| 4690 | #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ |
4690 | #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ |
| 4691 | #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ |
4691 | |
| 4692 | 4692 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
|
| 4693 | /****************** Bit definition for DAC_DHR8R2 register ******************/ |
4693 | #define DAC_DHR8R2_DACC2DHR_Pos (0U) |
| 4694 | #define DAC_DHR8R2_DACC2DHR_Pos (0U) |
4694 | #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ |
| 4695 | #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ |
4695 | #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ |
| 4696 | #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ |
4696 | |
| 4697 | 4697 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
|
| 4698 | /***************** Bit definition for DAC_DHR12RD register ******************/ |
4698 | #define DAC_DHR12RD_DACC1DHR_Pos (0U) |
| 4699 | #define DAC_DHR12RD_DACC1DHR_Pos (0U) |
4699 | #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ |
| 4700 | #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ |
4700 | #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ |
| 4701 | #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DAC channel1 12-bit Right aligned data */ |
4701 | #define DAC_DHR12RD_DACC2DHR_Pos (16U) |
| 4702 | #define DAC_DHR12RD_DACC2DHR_Pos (16U) |
4702 | #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ |
| 4703 | #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ |
4703 | #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ |
| 4704 | #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DAC channel2 12-bit Right aligned data */ |
4704 | |
| 4705 | 4705 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
|
| 4706 | /***************** Bit definition for DAC_DHR12LD register ******************/ |
4706 | #define DAC_DHR12LD_DACC1DHR_Pos (4U) |
| 4707 | #define DAC_DHR12LD_DACC1DHR_Pos (4U) |
4707 | #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
| 4708 | #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ |
4708 | #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ |
| 4709 | #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DAC channel1 12-bit Left aligned data */ |
4709 | #define DAC_DHR12LD_DACC2DHR_Pos (20U) |
| 4710 | #define DAC_DHR12LD_DACC2DHR_Pos (20U) |
4710 | #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ |
| 4711 | #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ |
4711 | #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ |
| 4712 | #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DAC channel2 12-bit Left aligned data */ |
4712 | |
| 4713 | 4713 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
|
| 4714 | /****************** Bit definition for DAC_DHR8RD register ******************/ |
4714 | #define DAC_DHR8RD_DACC1DHR_Pos (0U) |
| 4715 | #define DAC_DHR8RD_DACC1DHR_Pos (0U) |
4715 | #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ |
| 4716 | #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ |
4716 | #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ |
| 4717 | #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DAC channel1 8-bit Right aligned data */ |
4717 | #define DAC_DHR8RD_DACC2DHR_Pos (8U) |
| 4718 | #define DAC_DHR8RD_DACC2DHR_Pos (8U) |
4718 | #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ |
| 4719 | #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ |
4719 | #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ |
| 4720 | #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DAC channel2 8-bit Right aligned data */ |
4720 | |
| 4721 | 4721 | /******************* Bit definition for DAC_DOR1 register *******************/ |
|
| 4722 | /******************* Bit definition for DAC_DOR1 register *******************/ |
4722 | #define DAC_DOR1_DACC1DOR_Pos (0U) |
| 4723 | #define DAC_DOR1_DACC1DOR_Pos (0U) |
4723 | #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ |
| 4724 | #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ |
4724 | #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ |
| 4725 | #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DAC channel1 data output */ |
4725 | |
| 4726 | 4726 | /******************* Bit definition for DAC_DOR2 register *******************/ |
|
| 4727 | /******************* Bit definition for DAC_DOR2 register *******************/ |
4727 | #define DAC_DOR2_DACC2DOR_Pos (0U) |
| 4728 | #define DAC_DOR2_DACC2DOR_Pos (0U) |
4728 | #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ |
| 4729 | #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ |
4729 | #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ |
| 4730 | #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DAC channel2 data output */ |
4730 | |
| 4731 | 4731 | ||
| 4732 | 4732 | ||
| 4733 | 4733 | /*****************************************************************************/ |
|
| 4734 | /*****************************************************************************/ |
4734 | /* */ |
| 4735 | /* */ |
4735 | /* Timers (TIM) */ |
| 4736 | /* Timers (TIM) */ |
4736 | /* */ |
| 4737 | /* */ |
4737 | /*****************************************************************************/ |
| 4738 | /*****************************************************************************/ |
4738 | /******************* Bit definition for TIM_CR1 register *******************/ |
| 4739 | /******************* Bit definition for TIM_CR1 register *******************/ |
4739 | #define TIM_CR1_CEN_Pos (0U) |
| 4740 | #define TIM_CR1_CEN_Pos (0U) |
4740 | #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ |
| 4741 | #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ |
4741 | #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ |
| 4742 | #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */ |
4742 | #define TIM_CR1_UDIS_Pos (1U) |
| 4743 | #define TIM_CR1_UDIS_Pos (1U) |
4743 | #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ |
| 4744 | #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */ |
4744 | #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ |
| 4745 | #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */ |
4745 | #define TIM_CR1_URS_Pos (2U) |
| 4746 | #define TIM_CR1_URS_Pos (2U) |
4746 | #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ |
| 4747 | #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */ |
4747 | #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ |
| 4748 | #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */ |
4748 | #define TIM_CR1_OPM_Pos (3U) |
| 4749 | #define TIM_CR1_OPM_Pos (3U) |
4749 | #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ |
| 4750 | #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */ |
4750 | #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ |
| 4751 | #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */ |
4751 | #define TIM_CR1_DIR_Pos (4U) |
| 4752 | #define TIM_CR1_DIR_Pos (4U) |
4752 | #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ |
| 4753 | #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */ |
4753 | #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ |
| 4754 | #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */ |
4754 | |
| 4755 | 4755 | #define TIM_CR1_CMS_Pos (5U) |
|
| 4756 | #define TIM_CR1_CMS_Pos (5U) |
4756 | #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ |
| 4757 | #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */ |
4757 | #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
| 4758 | #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */ |
4758 | #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ |
| 4759 | #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */ |
4759 | #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ |
| 4760 | #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */ |
4760 | |
| 4761 | 4761 | #define TIM_CR1_ARPE_Pos (7U) |
|
| 4762 | #define TIM_CR1_ARPE_Pos (7U) |
4762 | #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ |
| 4763 | #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */ |
4763 | #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ |
| 4764 | #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */ |
4764 | |
| 4765 | 4765 | #define TIM_CR1_CKD_Pos (8U) |
|
| 4766 | #define TIM_CR1_CKD_Pos (8U) |
4766 | #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ |
| 4767 | #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */ |
4767 | #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ |
| 4768 | #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */ |
4768 | #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ |
| 4769 | #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */ |
4769 | #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ |
| 4770 | #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */ |
4770 | |
| 4771 | 4771 | /******************* Bit definition for TIM_CR2 register *******************/ |
|
| 4772 | /******************* Bit definition for TIM_CR2 register *******************/ |
4772 | #define TIM_CR2_CCPC_Pos (0U) |
| 4773 | #define TIM_CR2_CCPC_Pos (0U) |
4773 | #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ |
| 4774 | #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */ |
4774 | #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ |
| 4775 | #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */ |
4775 | #define TIM_CR2_CCUS_Pos (2U) |
| 4776 | #define TIM_CR2_CCUS_Pos (2U) |
4776 | #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ |
| 4777 | #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */ |
4777 | #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ |
| 4778 | #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */ |
4778 | #define TIM_CR2_CCDS_Pos (3U) |
| 4779 | #define TIM_CR2_CCDS_Pos (3U) |
4779 | #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ |
| 4780 | #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */ |
4780 | #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ |
| 4781 | #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */ |
4781 | |
| 4782 | 4782 | #define TIM_CR2_MMS_Pos (4U) |
|
| 4783 | #define TIM_CR2_MMS_Pos (4U) |
4783 | #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ |
| 4784 | #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */ |
4784 | #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ |
| 4785 | #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */ |
4785 | #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ |
| 4786 | #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */ |
4786 | #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ |
| 4787 | #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */ |
4787 | #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ |
| 4788 | #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */ |
4788 | |
| 4789 | 4789 | #define TIM_CR2_TI1S_Pos (7U) |
|
| 4790 | #define TIM_CR2_TI1S_Pos (7U) |
4790 | #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ |
| 4791 | #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */ |
4791 | #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ |
| 4792 | #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */ |
4792 | #define TIM_CR2_OIS1_Pos (8U) |
| 4793 | #define TIM_CR2_OIS1_Pos (8U) |
4793 | #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ |
| 4794 | #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */ |
4794 | #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ |
| 4795 | #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */ |
4795 | #define TIM_CR2_OIS1N_Pos (9U) |
| 4796 | #define TIM_CR2_OIS1N_Pos (9U) |
4796 | #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ |
| 4797 | #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */ |
4797 | #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ |
| 4798 | #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */ |
4798 | #define TIM_CR2_OIS2_Pos (10U) |
| 4799 | #define TIM_CR2_OIS2_Pos (10U) |
4799 | #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ |
| 4800 | #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */ |
4800 | #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ |
| 4801 | #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */ |
4801 | #define TIM_CR2_OIS2N_Pos (11U) |
| 4802 | #define TIM_CR2_OIS2N_Pos (11U) |
4802 | #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ |
| 4803 | #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */ |
4803 | #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ |
| 4804 | #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */ |
4804 | #define TIM_CR2_OIS3_Pos (12U) |
| 4805 | #define TIM_CR2_OIS3_Pos (12U) |
4805 | #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ |
| 4806 | #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */ |
4806 | #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ |
| 4807 | #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */ |
4807 | #define TIM_CR2_OIS3N_Pos (13U) |
| 4808 | #define TIM_CR2_OIS3N_Pos (13U) |
4808 | #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ |
| 4809 | #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */ |
4809 | #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ |
| 4810 | #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */ |
4810 | #define TIM_CR2_OIS4_Pos (14U) |
| 4811 | #define TIM_CR2_OIS4_Pos (14U) |
4811 | #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ |
| 4812 | #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */ |
4812 | #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ |
| 4813 | #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */ |
4813 | |
| 4814 | 4814 | /******************* Bit definition for TIM_SMCR register ******************/ |
|
| 4815 | /******************* Bit definition for TIM_SMCR register ******************/ |
4815 | #define TIM_SMCR_SMS_Pos (0U) |
| 4816 | #define TIM_SMCR_SMS_Pos (0U) |
4816 | #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ |
| 4817 | #define TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */ |
4817 | #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ |
| 4818 | #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */ |
4818 | #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ |
| 4819 | #define TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */ |
4819 | #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ |
| 4820 | #define TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */ |
4820 | #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ |
| 4821 | #define TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */ |
4821 | |
| 4822 | 4822 | #define TIM_SMCR_TS_Pos (4U) |
|
| 4823 | #define TIM_SMCR_TS_Pos (4U) |
4823 | #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ |
| 4824 | #define TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos) /*!< 0x00000070 */ |
4824 | #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ |
| 4825 | #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */ |
4825 | #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ |
| 4826 | #define TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */ |
4826 | #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ |
| 4827 | #define TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */ |
4827 | #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ |
| 4828 | #define TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */ |
4828 | |
| 4829 | 4829 | #define TIM_SMCR_MSM_Pos (7U) |
|
| 4830 | #define TIM_SMCR_MSM_Pos (7U) |
4830 | #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ |
| 4831 | #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */ |
4831 | #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ |
| 4832 | #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */ |
4832 | |
| 4833 | 4833 | #define TIM_SMCR_ETF_Pos (8U) |
|
| 4834 | #define TIM_SMCR_ETF_Pos (8U) |
4834 | #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ |
| 4835 | #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */ |
4835 | #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ |
| 4836 | #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */ |
4836 | #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ |
| 4837 | #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */ |
4837 | #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ |
| 4838 | #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */ |
4838 | #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ |
| 4839 | #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */ |
4839 | #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ |
| 4840 | #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */ |
4840 | |
| 4841 | 4841 | #define TIM_SMCR_ETPS_Pos (12U) |
|
| 4842 | #define TIM_SMCR_ETPS_Pos (12U) |
4842 | #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ |
| 4843 | #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */ |
4843 | #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ |
| 4844 | #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */ |
4844 | #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ |
| 4845 | #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */ |
4845 | #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ |
| 4846 | #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */ |
4846 | |
| 4847 | 4847 | #define TIM_SMCR_ECE_Pos (14U) |
|
| 4848 | #define TIM_SMCR_ECE_Pos (14U) |
4848 | #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ |
| 4849 | #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */ |
4849 | #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ |
| 4850 | #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */ |
4850 | #define TIM_SMCR_ETP_Pos (15U) |
| 4851 | #define TIM_SMCR_ETP_Pos (15U) |
4851 | #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ |
| 4852 | #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */ |
4852 | #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ |
| 4853 | #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */ |
4853 | |
| 4854 | 4854 | /******************* Bit definition for TIM_DIER register ******************/ |
|
| 4855 | /******************* Bit definition for TIM_DIER register ******************/ |
4855 | #define TIM_DIER_UIE_Pos (0U) |
| 4856 | #define TIM_DIER_UIE_Pos (0U) |
4856 | #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ |
| 4857 | #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */ |
4857 | #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ |
| 4858 | #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */ |
4858 | #define TIM_DIER_CC1IE_Pos (1U) |
| 4859 | #define TIM_DIER_CC1IE_Pos (1U) |
4859 | #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ |
| 4860 | #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */ |
4860 | #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ |
| 4861 | #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */ |
4861 | #define TIM_DIER_CC2IE_Pos (2U) |
| 4862 | #define TIM_DIER_CC2IE_Pos (2U) |
4862 | #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ |
| 4863 | #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */ |
4863 | #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ |
| 4864 | #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */ |
4864 | #define TIM_DIER_CC3IE_Pos (3U) |
| 4865 | #define TIM_DIER_CC3IE_Pos (3U) |
4865 | #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ |
| 4866 | #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */ |
4866 | #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ |
| 4867 | #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */ |
4867 | #define TIM_DIER_CC4IE_Pos (4U) |
| 4868 | #define TIM_DIER_CC4IE_Pos (4U) |
4868 | #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ |
| 4869 | #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */ |
4869 | #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ |
| 4870 | #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */ |
4870 | #define TIM_DIER_COMIE_Pos (5U) |
| 4871 | #define TIM_DIER_COMIE_Pos (5U) |
4871 | #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ |
| 4872 | #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */ |
4872 | #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ |
| 4873 | #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */ |
4873 | #define TIM_DIER_TIE_Pos (6U) |
| 4874 | #define TIM_DIER_TIE_Pos (6U) |
4874 | #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ |
| 4875 | #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */ |
4875 | #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ |
| 4876 | #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */ |
4876 | #define TIM_DIER_BIE_Pos (7U) |
| 4877 | #define TIM_DIER_BIE_Pos (7U) |
4877 | #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ |
| 4878 | #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */ |
4878 | #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ |
| 4879 | #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */ |
4879 | #define TIM_DIER_UDE_Pos (8U) |
| 4880 | #define TIM_DIER_UDE_Pos (8U) |
4880 | #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ |
| 4881 | #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */ |
4881 | #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ |
| 4882 | #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */ |
4882 | #define TIM_DIER_CC1DE_Pos (9U) |
| 4883 | #define TIM_DIER_CC1DE_Pos (9U) |
4883 | #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ |
| 4884 | #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */ |
4884 | #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ |
| 4885 | #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */ |
4885 | #define TIM_DIER_CC2DE_Pos (10U) |
| 4886 | #define TIM_DIER_CC2DE_Pos (10U) |
4886 | #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ |
| 4887 | #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */ |
4887 | #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ |
| 4888 | #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */ |
4888 | #define TIM_DIER_CC3DE_Pos (11U) |
| 4889 | #define TIM_DIER_CC3DE_Pos (11U) |
4889 | #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ |
| 4890 | #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */ |
4890 | #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ |
| 4891 | #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */ |
4891 | #define TIM_DIER_CC4DE_Pos (12U) |
| 4892 | #define TIM_DIER_CC4DE_Pos (12U) |
4892 | #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ |
| 4893 | #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */ |
4893 | #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ |
| 4894 | #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */ |
4894 | #define TIM_DIER_COMDE_Pos (13U) |
| 4895 | #define TIM_DIER_COMDE_Pos (13U) |
4895 | #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ |
| 4896 | #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */ |
4896 | #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ |
| 4897 | #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */ |
4897 | #define TIM_DIER_TDE_Pos (14U) |
| 4898 | #define TIM_DIER_TDE_Pos (14U) |
4898 | #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ |
| 4899 | #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */ |
4899 | #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ |
| 4900 | #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */ |
4900 | |
| 4901 | 4901 | /******************** Bit definition for TIM_SR register *******************/ |
|
| 4902 | /******************** Bit definition for TIM_SR register *******************/ |
4902 | #define TIM_SR_UIF_Pos (0U) |
| 4903 | #define TIM_SR_UIF_Pos (0U) |
4903 | #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ |
| 4904 | #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */ |
4904 | #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ |
| 4905 | #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */ |
4905 | #define TIM_SR_CC1IF_Pos (1U) |
| 4906 | #define TIM_SR_CC1IF_Pos (1U) |
4906 | #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ |
| 4907 | #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */ |
4907 | #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ |
| 4908 | #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */ |
4908 | #define TIM_SR_CC2IF_Pos (2U) |
| 4909 | #define TIM_SR_CC2IF_Pos (2U) |
4909 | #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ |
| 4910 | #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */ |
4910 | #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ |
| 4911 | #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */ |
4911 | #define TIM_SR_CC3IF_Pos (3U) |
| 4912 | #define TIM_SR_CC3IF_Pos (3U) |
4912 | #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ |
| 4913 | #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */ |
4913 | #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ |
| 4914 | #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */ |
4914 | #define TIM_SR_CC4IF_Pos (4U) |
| 4915 | #define TIM_SR_CC4IF_Pos (4U) |
4915 | #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ |
| 4916 | #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */ |
4916 | #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ |
| 4917 | #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */ |
4917 | #define TIM_SR_COMIF_Pos (5U) |
| 4918 | #define TIM_SR_COMIF_Pos (5U) |
4918 | #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ |
| 4919 | #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */ |
4919 | #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ |
| 4920 | #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */ |
4920 | #define TIM_SR_TIF_Pos (6U) |
| 4921 | #define TIM_SR_TIF_Pos (6U) |
4921 | #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ |
| 4922 | #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */ |
4922 | #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ |
| 4923 | #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */ |
4923 | #define TIM_SR_BIF_Pos (7U) |
| 4924 | #define TIM_SR_BIF_Pos (7U) |
4924 | #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ |
| 4925 | #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */ |
4925 | #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ |
| 4926 | #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */ |
4926 | #define TIM_SR_CC1OF_Pos (9U) |
| 4927 | #define TIM_SR_CC1OF_Pos (9U) |
4927 | #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ |
| 4928 | #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */ |
4928 | #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ |
| 4929 | #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */ |
4929 | #define TIM_SR_CC2OF_Pos (10U) |
| 4930 | #define TIM_SR_CC2OF_Pos (10U) |
4930 | #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ |
| 4931 | #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */ |
4931 | #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ |
| 4932 | #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */ |
4932 | #define TIM_SR_CC3OF_Pos (11U) |
| 4933 | #define TIM_SR_CC3OF_Pos (11U) |
4933 | #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ |
| 4934 | #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */ |
4934 | #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ |
| 4935 | #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */ |
4935 | #define TIM_SR_CC4OF_Pos (12U) |
| 4936 | #define TIM_SR_CC4OF_Pos (12U) |
4936 | #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ |
| 4937 | #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */ |
4937 | #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ |
| 4938 | #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */ |
4938 | |
| 4939 | 4939 | /******************* Bit definition for TIM_EGR register *******************/ |
|
| 4940 | /******************* Bit definition for TIM_EGR register *******************/ |
4940 | #define TIM_EGR_UG_Pos (0U) |
| 4941 | #define TIM_EGR_UG_Pos (0U) |
4941 | #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ |
| 4942 | #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */ |
4942 | #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ |
| 4943 | #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */ |
4943 | #define TIM_EGR_CC1G_Pos (1U) |
| 4944 | #define TIM_EGR_CC1G_Pos (1U) |
4944 | #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ |
| 4945 | #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */ |
4945 | #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ |
| 4946 | #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */ |
4946 | #define TIM_EGR_CC2G_Pos (2U) |
| 4947 | #define TIM_EGR_CC2G_Pos (2U) |
4947 | #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ |
| 4948 | #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */ |
4948 | #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ |
| 4949 | #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */ |
4949 | #define TIM_EGR_CC3G_Pos (3U) |
| 4950 | #define TIM_EGR_CC3G_Pos (3U) |
4950 | #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ |
| 4951 | #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */ |
4951 | #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ |
| 4952 | #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */ |
4952 | #define TIM_EGR_CC4G_Pos (4U) |
| 4953 | #define TIM_EGR_CC4G_Pos (4U) |
4953 | #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ |
| 4954 | #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */ |
4954 | #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ |
| 4955 | #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */ |
4955 | #define TIM_EGR_COMG_Pos (5U) |
| 4956 | #define TIM_EGR_COMG_Pos (5U) |
4956 | #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ |
| 4957 | #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */ |
4957 | #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ |
| 4958 | #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */ |
4958 | #define TIM_EGR_TG_Pos (6U) |
| 4959 | #define TIM_EGR_TG_Pos (6U) |
4959 | #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ |
| 4960 | #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */ |
4960 | #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ |
| 4961 | #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */ |
4961 | #define TIM_EGR_BG_Pos (7U) |
| 4962 | #define TIM_EGR_BG_Pos (7U) |
4962 | #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ |
| 4963 | #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */ |
4963 | #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ |
| 4964 | #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */ |
4964 | |
| 4965 | 4965 | /****************** Bit definition for TIM_CCMR1 register ******************/ |
|
| 4966 | /****************** Bit definition for TIM_CCMR1 register ******************/ |
4966 | #define TIM_CCMR1_CC1S_Pos (0U) |
| 4967 | #define TIM_CCMR1_CC1S_Pos (0U) |
4967 | #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ |
| 4968 | #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */ |
4968 | #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
| 4969 | #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */ |
4969 | #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ |
| 4970 | #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */ |
4970 | #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ |
| 4971 | #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */ |
4971 | |
| 4972 | 4972 | #define TIM_CCMR1_OC1FE_Pos (2U) |
|
| 4973 | #define TIM_CCMR1_OC1FE_Pos (2U) |
4973 | #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ |
| 4974 | #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */ |
4974 | #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ |
| 4975 | #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */ |
4975 | #define TIM_CCMR1_OC1PE_Pos (3U) |
| 4976 | #define TIM_CCMR1_OC1PE_Pos (3U) |
4976 | #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ |
| 4977 | #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */ |
4977 | #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ |
| 4978 | #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */ |
4978 | |
| 4979 | 4979 | #define TIM_CCMR1_OC1M_Pos (4U) |
|
| 4980 | #define TIM_CCMR1_OC1M_Pos (4U) |
4980 | #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ |
| 4981 | #define TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */ |
4981 | #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
| 4982 | #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */ |
4982 | #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ |
| 4983 | #define TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */ |
4983 | #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ |
| 4984 | #define TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */ |
4984 | #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ |
| 4985 | #define TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */ |
4985 | |
| 4986 | 4986 | #define TIM_CCMR1_OC1CE_Pos (7U) |
|
| 4987 | #define TIM_CCMR1_OC1CE_Pos (7U) |
4987 | #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ |
| 4988 | #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */ |
4988 | #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ |
| 4989 | #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */ |
4989 | |
| 4990 | 4990 | #define TIM_CCMR1_CC2S_Pos (8U) |
|
| 4991 | #define TIM_CCMR1_CC2S_Pos (8U) |
4991 | #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ |
| 4992 | #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */ |
4992 | #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
| 4993 | #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */ |
4993 | #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ |
| 4994 | #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */ |
4994 | #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ |
| 4995 | #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */ |
4995 | |
| 4996 | 4996 | #define TIM_CCMR1_OC2FE_Pos (10U) |
|
| 4997 | #define TIM_CCMR1_OC2FE_Pos (10U) |
4997 | #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ |
| 4998 | #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */ |
4998 | #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ |
| 4999 | #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */ |
4999 | #define TIM_CCMR1_OC2PE_Pos (11U) |
| 5000 | #define TIM_CCMR1_OC2PE_Pos (11U) |
5000 | #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ |
| 5001 | #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */ |
5001 | #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ |
| 5002 | #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */ |
5002 | |
| 5003 | 5003 | #define TIM_CCMR1_OC2M_Pos (12U) |
|
| 5004 | #define TIM_CCMR1_OC2M_Pos (12U) |
5004 | #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ |
| 5005 | #define TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */ |
5005 | #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
| 5006 | #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */ |
5006 | #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ |
| 5007 | #define TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */ |
5007 | #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ |
| 5008 | #define TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */ |
5008 | #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ |
| 5009 | #define TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */ |
5009 | |
| 5010 | 5010 | #define TIM_CCMR1_OC2CE_Pos (15U) |
|
| 5011 | #define TIM_CCMR1_OC2CE_Pos (15U) |
5011 | #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ |
| 5012 | #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */ |
5012 | #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ |
| 5013 | #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */ |
5013 | |
| 5014 | 5014 | /*---------------------------------------------------------------------------*/ |
|
| 5015 | /*---------------------------------------------------------------------------*/ |
5015 | |
| 5016 | 5016 | #define TIM_CCMR1_IC1PSC_Pos (2U) |
|
| 5017 | #define TIM_CCMR1_IC1PSC_Pos (2U) |
5017 | #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ |
| 5018 | #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */ |
5018 | #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
| 5019 | #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ |
5019 | #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ |
| 5020 | #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */ |
5020 | #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ |
| 5021 | #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */ |
5021 | |
| 5022 | 5022 | #define TIM_CCMR1_IC1F_Pos (4U) |
|
| 5023 | #define TIM_CCMR1_IC1F_Pos (4U) |
5023 | #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ |
| 5024 | #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */ |
5024 | #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
| 5025 | #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */ |
5025 | #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ |
| 5026 | #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */ |
5026 | #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ |
| 5027 | #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */ |
5027 | #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ |
| 5028 | #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */ |
5028 | #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ |
| 5029 | #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */ |
5029 | |
| 5030 | 5030 | #define TIM_CCMR1_IC2PSC_Pos (10U) |
|
| 5031 | #define TIM_CCMR1_IC2PSC_Pos (10U) |
5031 | #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ |
| 5032 | #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */ |
5032 | #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
| 5033 | #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ |
5033 | #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ |
| 5034 | #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */ |
5034 | #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ |
| 5035 | #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */ |
5035 | |
| 5036 | 5036 | #define TIM_CCMR1_IC2F_Pos (12U) |
|
| 5037 | #define TIM_CCMR1_IC2F_Pos (12U) |
5037 | #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ |
| 5038 | #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */ |
5038 | #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
| 5039 | #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */ |
5039 | #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ |
| 5040 | #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */ |
5040 | #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ |
| 5041 | #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */ |
5041 | #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ |
| 5042 | #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */ |
5042 | #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ |
| 5043 | #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */ |
5043 | |
| 5044 | 5044 | /****************** Bit definition for TIM_CCMR2 register ******************/ |
|
| 5045 | /****************** Bit definition for TIM_CCMR2 register ******************/ |
5045 | #define TIM_CCMR2_CC3S_Pos (0U) |
| 5046 | #define TIM_CCMR2_CC3S_Pos (0U) |
5046 | #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ |
| 5047 | #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */ |
5047 | #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
| 5048 | #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */ |
5048 | #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ |
| 5049 | #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */ |
5049 | #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ |
| 5050 | #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */ |
5050 | |
| 5051 | 5051 | #define TIM_CCMR2_OC3FE_Pos (2U) |
|
| 5052 | #define TIM_CCMR2_OC3FE_Pos (2U) |
5052 | #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ |
| 5053 | #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */ |
5053 | #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ |
| 5054 | #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */ |
5054 | #define TIM_CCMR2_OC3PE_Pos (3U) |
| 5055 | #define TIM_CCMR2_OC3PE_Pos (3U) |
5055 | #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ |
| 5056 | #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */ |
5056 | #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ |
| 5057 | #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */ |
5057 | |
| 5058 | 5058 | #define TIM_CCMR2_OC3M_Pos (4U) |
|
| 5059 | #define TIM_CCMR2_OC3M_Pos (4U) |
5059 | #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ |
| 5060 | #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */ |
5060 | #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
| 5061 | #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */ |
5061 | #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ |
| 5062 | #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */ |
5062 | #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ |
| 5063 | #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */ |
5063 | #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ |
| 5064 | #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */ |
5064 | |
| 5065 | 5065 | #define TIM_CCMR2_OC3CE_Pos (7U) |
|
| 5066 | #define TIM_CCMR2_OC3CE_Pos (7U) |
5066 | #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ |
| 5067 | #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */ |
5067 | #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ |
| 5068 | #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */ |
5068 | |
| 5069 | 5069 | #define TIM_CCMR2_CC4S_Pos (8U) |
|
| 5070 | #define TIM_CCMR2_CC4S_Pos (8U) |
5070 | #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ |
| 5071 | #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */ |
5071 | #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
| 5072 | #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */ |
5072 | #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ |
| 5073 | #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */ |
5073 | #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ |
| 5074 | #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */ |
5074 | |
| 5075 | 5075 | #define TIM_CCMR2_OC4FE_Pos (10U) |
|
| 5076 | #define TIM_CCMR2_OC4FE_Pos (10U) |
5076 | #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ |
| 5077 | #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */ |
5077 | #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ |
| 5078 | #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */ |
5078 | #define TIM_CCMR2_OC4PE_Pos (11U) |
| 5079 | #define TIM_CCMR2_OC4PE_Pos (11U) |
5079 | #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ |
| 5080 | #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */ |
5080 | #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ |
| 5081 | #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */ |
5081 | |
| 5082 | 5082 | #define TIM_CCMR2_OC4M_Pos (12U) |
|
| 5083 | #define TIM_CCMR2_OC4M_Pos (12U) |
5083 | #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ |
| 5084 | #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */ |
5084 | #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
| 5085 | #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */ |
5085 | #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ |
| 5086 | #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */ |
5086 | #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ |
| 5087 | #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */ |
5087 | #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ |
| 5088 | #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */ |
5088 | |
| 5089 | 5089 | #define TIM_CCMR2_OC4CE_Pos (15U) |
|
| 5090 | #define TIM_CCMR2_OC4CE_Pos (15U) |
5090 | #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ |
| 5091 | #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */ |
5091 | #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ |
| 5092 | #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */ |
5092 | |
| 5093 | 5093 | /*---------------------------------------------------------------------------*/ |
|
| 5094 | /*---------------------------------------------------------------------------*/ |
5094 | |
| 5095 | 5095 | #define TIM_CCMR2_IC3PSC_Pos (2U) |
|
| 5096 | #define TIM_CCMR2_IC3PSC_Pos (2U) |
5096 | #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ |
| 5097 | #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */ |
5097 | #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
| 5098 | #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ |
5098 | #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ |
| 5099 | #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */ |
5099 | #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ |
| 5100 | #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */ |
5100 | |
| 5101 | 5101 | #define TIM_CCMR2_IC3F_Pos (4U) |
|
| 5102 | #define TIM_CCMR2_IC3F_Pos (4U) |
5102 | #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ |
| 5103 | #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */ |
5103 | #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
| 5104 | #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */ |
5104 | #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ |
| 5105 | #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */ |
5105 | #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ |
| 5106 | #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */ |
5106 | #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ |
| 5107 | #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */ |
5107 | #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ |
| 5108 | #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */ |
5108 | |
| 5109 | 5109 | #define TIM_CCMR2_IC4PSC_Pos (10U) |
|
| 5110 | #define TIM_CCMR2_IC4PSC_Pos (10U) |
5110 | #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ |
| 5111 | #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */ |
5111 | #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
| 5112 | #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ |
5112 | #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ |
| 5113 | #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */ |
5113 | #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ |
| 5114 | #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */ |
5114 | |
| 5115 | 5115 | #define TIM_CCMR2_IC4F_Pos (12U) |
|
| 5116 | #define TIM_CCMR2_IC4F_Pos (12U) |
5116 | #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ |
| 5117 | #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */ |
5117 | #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
| 5118 | #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */ |
5118 | #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ |
| 5119 | #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */ |
5119 | #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ |
| 5120 | #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */ |
5120 | #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ |
| 5121 | #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */ |
5121 | #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ |
| 5122 | #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */ |
5122 | |
| 5123 | 5123 | /******************* Bit definition for TIM_CCER register ******************/ |
|
| 5124 | /******************* Bit definition for TIM_CCER register ******************/ |
5124 | #define TIM_CCER_CC1E_Pos (0U) |
| 5125 | #define TIM_CCER_CC1E_Pos (0U) |
5125 | #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ |
| 5126 | #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */ |
5126 | #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ |
| 5127 | #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */ |
5127 | #define TIM_CCER_CC1P_Pos (1U) |
| 5128 | #define TIM_CCER_CC1P_Pos (1U) |
5128 | #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ |
| 5129 | #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */ |
5129 | #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ |
| 5130 | #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */ |
5130 | #define TIM_CCER_CC1NE_Pos (2U) |
| 5131 | #define TIM_CCER_CC1NE_Pos (2U) |
5131 | #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ |
| 5132 | #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */ |
5132 | #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ |
| 5133 | #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */ |
5133 | #define TIM_CCER_CC1NP_Pos (3U) |
| 5134 | #define TIM_CCER_CC1NP_Pos (3U) |
5134 | #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ |
| 5135 | #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */ |
5135 | #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ |
| 5136 | #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */ |
5136 | #define TIM_CCER_CC2E_Pos (4U) |
| 5137 | #define TIM_CCER_CC2E_Pos (4U) |
5137 | #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ |
| 5138 | #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */ |
5138 | #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ |
| 5139 | #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */ |
5139 | #define TIM_CCER_CC2P_Pos (5U) |
| 5140 | #define TIM_CCER_CC2P_Pos (5U) |
5140 | #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ |
| 5141 | #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */ |
5141 | #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ |
| 5142 | #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */ |
5142 | #define TIM_CCER_CC2NE_Pos (6U) |
| 5143 | #define TIM_CCER_CC2NE_Pos (6U) |
5143 | #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ |
| 5144 | #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */ |
5144 | #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ |
| 5145 | #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */ |
5145 | #define TIM_CCER_CC2NP_Pos (7U) |
| 5146 | #define TIM_CCER_CC2NP_Pos (7U) |
5146 | #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ |
| 5147 | #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */ |
5147 | #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ |
| 5148 | #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */ |
5148 | #define TIM_CCER_CC3E_Pos (8U) |
| 5149 | #define TIM_CCER_CC3E_Pos (8U) |
5149 | #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ |
| 5150 | #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */ |
5150 | #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ |
| 5151 | #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */ |
5151 | #define TIM_CCER_CC3P_Pos (9U) |
| 5152 | #define TIM_CCER_CC3P_Pos (9U) |
5152 | #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ |
| 5153 | #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */ |
5153 | #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ |
| 5154 | #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */ |
5154 | #define TIM_CCER_CC3NE_Pos (10U) |
| 5155 | #define TIM_CCER_CC3NE_Pos (10U) |
5155 | #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ |
| 5156 | #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */ |
5156 | #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ |
| 5157 | #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */ |
5157 | #define TIM_CCER_CC3NP_Pos (11U) |
| 5158 | #define TIM_CCER_CC3NP_Pos (11U) |
5158 | #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ |
| 5159 | #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */ |
5159 | #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ |
| 5160 | #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */ |
5160 | #define TIM_CCER_CC4E_Pos (12U) |
| 5161 | #define TIM_CCER_CC4E_Pos (12U) |
5161 | #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ |
| 5162 | #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */ |
5162 | #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ |
| 5163 | #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */ |
5163 | #define TIM_CCER_CC4P_Pos (13U) |
| 5164 | #define TIM_CCER_CC4P_Pos (13U) |
5164 | #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ |
| 5165 | #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */ |
5165 | #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ |
| 5166 | #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */ |
5166 | |
| 5167 | 5167 | /******************* Bit definition for TIM_CNT register *******************/ |
|
| 5168 | /******************* Bit definition for TIM_CNT register *******************/ |
5168 | #define TIM_CNT_CNT_Pos (0U) |
| 5169 | #define TIM_CNT_CNT_Pos (0U) |
5169 | #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ |
| 5170 | #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */ |
5170 | #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ |
| 5171 | #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */ |
5171 | |
| 5172 | 5172 | /******************* Bit definition for TIM_PSC register *******************/ |
|
| 5173 | /******************* Bit definition for TIM_PSC register *******************/ |
5173 | #define TIM_PSC_PSC_Pos (0U) |
| 5174 | #define TIM_PSC_PSC_Pos (0U) |
5174 | #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ |
| 5175 | #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */ |
5175 | #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ |
| 5176 | #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */ |
5176 | |
| 5177 | 5177 | /******************* Bit definition for TIM_ARR register *******************/ |
|
| 5178 | /******************* Bit definition for TIM_ARR register *******************/ |
5178 | #define TIM_ARR_ARR_Pos (0U) |
| 5179 | #define TIM_ARR_ARR_Pos (0U) |
5179 | #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ |
| 5180 | #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */ |
5180 | #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ |
| 5181 | #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */ |
5181 | |
| 5182 | 5182 | /******************* Bit definition for TIM_RCR register *******************/ |
|
| 5183 | /******************* Bit definition for TIM_RCR register *******************/ |
5183 | #define TIM_RCR_REP_Pos (0U) |
| 5184 | #define TIM_RCR_REP_Pos (0U) |
5184 | #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */ |
| 5185 | #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */ |
5185 | #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ |
| 5186 | #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */ |
5186 | |
| 5187 | 5187 | /******************* Bit definition for TIM_CCR1 register ******************/ |
|
| 5188 | /******************* Bit definition for TIM_CCR1 register ******************/ |
5188 | #define TIM_CCR1_CCR1_Pos (0U) |
| 5189 | #define TIM_CCR1_CCR1_Pos (0U) |
5189 | #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ |
| 5190 | #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */ |
5190 | #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ |
| 5191 | #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */ |
5191 | |
| 5192 | 5192 | /******************* Bit definition for TIM_CCR2 register ******************/ |
|
| 5193 | /******************* Bit definition for TIM_CCR2 register ******************/ |
5193 | #define TIM_CCR2_CCR2_Pos (0U) |
| 5194 | #define TIM_CCR2_CCR2_Pos (0U) |
5194 | #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ |
| 5195 | #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */ |
5195 | #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ |
| 5196 | #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */ |
5196 | |
| 5197 | 5197 | /******************* Bit definition for TIM_CCR3 register ******************/ |
|
| 5198 | /******************* Bit definition for TIM_CCR3 register ******************/ |
5198 | #define TIM_CCR3_CCR3_Pos (0U) |
| 5199 | #define TIM_CCR3_CCR3_Pos (0U) |
5199 | #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ |
| 5200 | #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */ |
5200 | #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ |
| 5201 | #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */ |
5201 | |
| 5202 | 5202 | /******************* Bit definition for TIM_CCR4 register ******************/ |
|
| 5203 | /******************* Bit definition for TIM_CCR4 register ******************/ |
5203 | #define TIM_CCR4_CCR4_Pos (0U) |
| 5204 | #define TIM_CCR4_CCR4_Pos (0U) |
5204 | #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ |
| 5205 | #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */ |
5205 | #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ |
| 5206 | #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */ |
5206 | |
| 5207 | 5207 | /******************* Bit definition for TIM_BDTR register ******************/ |
|
| 5208 | /******************* Bit definition for TIM_BDTR register ******************/ |
5208 | #define TIM_BDTR_DTG_Pos (0U) |
| 5209 | #define TIM_BDTR_DTG_Pos (0U) |
5209 | #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ |
| 5210 | #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */ |
5210 | #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
| 5211 | #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */ |
5211 | #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ |
| 5212 | #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */ |
5212 | #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ |
| 5213 | #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */ |
5213 | #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ |
| 5214 | #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */ |
5214 | #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ |
| 5215 | #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */ |
5215 | #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ |
| 5216 | #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */ |
5216 | #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ |
| 5217 | #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */ |
5217 | #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ |
| 5218 | #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */ |
5218 | #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ |
| 5219 | #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */ |
5219 | |
| 5220 | 5220 | #define TIM_BDTR_LOCK_Pos (8U) |
|
| 5221 | #define TIM_BDTR_LOCK_Pos (8U) |
5221 | #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ |
| 5222 | #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */ |
5222 | #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ |
| 5223 | #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */ |
5223 | #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ |
| 5224 | #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */ |
5224 | #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ |
| 5225 | #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */ |
5225 | |
| 5226 | 5226 | #define TIM_BDTR_OSSI_Pos (10U) |
|
| 5227 | #define TIM_BDTR_OSSI_Pos (10U) |
5227 | #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ |
| 5228 | #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */ |
5228 | #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ |
| 5229 | #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */ |
5229 | #define TIM_BDTR_OSSR_Pos (11U) |
| 5230 | #define TIM_BDTR_OSSR_Pos (11U) |
5230 | #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ |
| 5231 | #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */ |
5231 | #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ |
| 5232 | #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */ |
5232 | #define TIM_BDTR_BKE_Pos (12U) |
| 5233 | #define TIM_BDTR_BKE_Pos (12U) |
5233 | #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ |
| 5234 | #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */ |
5234 | #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ |
| 5235 | #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */ |
5235 | #define TIM_BDTR_BKP_Pos (13U) |
| 5236 | #define TIM_BDTR_BKP_Pos (13U) |
5236 | #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ |
| 5237 | #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */ |
5237 | #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ |
| 5238 | #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */ |
5238 | #define TIM_BDTR_AOE_Pos (14U) |
| 5239 | #define TIM_BDTR_AOE_Pos (14U) |
5239 | #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ |
| 5240 | #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */ |
5240 | #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ |
| 5241 | #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */ |
5241 | #define TIM_BDTR_MOE_Pos (15U) |
| 5242 | #define TIM_BDTR_MOE_Pos (15U) |
5242 | #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ |
| 5243 | #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */ |
5243 | #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ |
| 5244 | #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */ |
5244 | |
| 5245 | 5245 | /******************* Bit definition for TIM_DCR register *******************/ |
|
| 5246 | /******************* Bit definition for TIM_DCR register *******************/ |
5246 | #define TIM_DCR_DBA_Pos (0U) |
| 5247 | #define TIM_DCR_DBA_Pos (0U) |
5247 | #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ |
| 5248 | #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */ |
5248 | #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ |
| 5249 | #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */ |
5249 | #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ |
| 5250 | #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */ |
5250 | #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ |
| 5251 | #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */ |
5251 | #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ |
| 5252 | #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */ |
5252 | #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ |
| 5253 | #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */ |
5253 | #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ |
| 5254 | #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */ |
5254 | |
| 5255 | 5255 | #define TIM_DCR_DBL_Pos (8U) |
|
| 5256 | #define TIM_DCR_DBL_Pos (8U) |
5256 | #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ |
| 5257 | #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */ |
5257 | #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ |
| 5258 | #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */ |
5258 | #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ |
| 5259 | #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */ |
5259 | #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ |
| 5260 | #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */ |
5260 | #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ |
| 5261 | #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */ |
5261 | #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ |
| 5262 | #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */ |
5262 | #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ |
| 5263 | #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */ |
5263 | |
| 5264 | 5264 | /******************* Bit definition for TIM_DMAR register ******************/ |
|
| 5265 | /******************* Bit definition for TIM_DMAR register ******************/ |
5265 | #define TIM_DMAR_DMAB_Pos (0U) |
| 5266 | #define TIM_DMAR_DMAB_Pos (0U) |
5266 | #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ |
| 5267 | #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */ |
5267 | #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ |
| 5268 | #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */ |
5268 | |
| 5269 | 5269 | /******************************************************************************/ |
|
| 5270 | /******************************************************************************/ |
5270 | /* */ |
| 5271 | /* */ |
5271 | /* Real-Time Clock */ |
| 5272 | /* Real-Time Clock */ |
5272 | /* */ |
| 5273 | /* */ |
5273 | /******************************************************************************/ |
| 5274 | /******************************************************************************/ |
5274 | |
| 5275 | 5275 | /******************* Bit definition for RTC_CRH register ********************/ |
|
| 5276 | /******************* Bit definition for RTC_CRH register ********************/ |
5276 | #define RTC_CRH_SECIE_Pos (0U) |
| 5277 | #define RTC_CRH_SECIE_Pos (0U) |
5277 | #define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */ |
| 5278 | #define RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos) /*!< 0x00000001 */ |
5278 | #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */ |
| 5279 | #define RTC_CRH_SECIE RTC_CRH_SECIE_Msk /*!< Second Interrupt Enable */ |
5279 | #define RTC_CRH_ALRIE_Pos (1U) |
| 5280 | #define RTC_CRH_ALRIE_Pos (1U) |
5280 | #define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */ |
| 5281 | #define RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos) /*!< 0x00000002 */ |
5281 | #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */ |
| 5282 | #define RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk /*!< Alarm Interrupt Enable */ |
5282 | #define RTC_CRH_OWIE_Pos (2U) |
| 5283 | #define RTC_CRH_OWIE_Pos (2U) |
5283 | #define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */ |
| 5284 | #define RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos) /*!< 0x00000004 */ |
5284 | #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */ |
| 5285 | #define RTC_CRH_OWIE RTC_CRH_OWIE_Msk /*!< OverfloW Interrupt Enable */ |
5285 | |
| 5286 | 5286 | /******************* Bit definition for RTC_CRL register ********************/ |
|
| 5287 | /******************* Bit definition for RTC_CRL register ********************/ |
5287 | #define RTC_CRL_SECF_Pos (0U) |
| 5288 | #define RTC_CRL_SECF_Pos (0U) |
5288 | #define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos) /*!< 0x00000001 */ |
| 5289 | #define RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos) /*!< 0x00000001 */ |
5289 | #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */ |
| 5290 | #define RTC_CRL_SECF RTC_CRL_SECF_Msk /*!< Second Flag */ |
5290 | #define RTC_CRL_ALRF_Pos (1U) |
| 5291 | #define RTC_CRL_ALRF_Pos (1U) |
5291 | #define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */ |
| 5292 | #define RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos) /*!< 0x00000002 */ |
5292 | #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */ |
| 5293 | #define RTC_CRL_ALRF RTC_CRL_ALRF_Msk /*!< Alarm Flag */ |
5293 | #define RTC_CRL_OWF_Pos (2U) |
| 5294 | #define RTC_CRL_OWF_Pos (2U) |
5294 | #define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos) /*!< 0x00000004 */ |
| 5295 | #define RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos) /*!< 0x00000004 */ |
5295 | #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */ |
| 5296 | #define RTC_CRL_OWF RTC_CRL_OWF_Msk /*!< OverfloW Flag */ |
5296 | #define RTC_CRL_RSF_Pos (3U) |
| 5297 | #define RTC_CRL_RSF_Pos (3U) |
5297 | #define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos) /*!< 0x00000008 */ |
| 5298 | #define RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos) /*!< 0x00000008 */ |
5298 | #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */ |
| 5299 | #define RTC_CRL_RSF RTC_CRL_RSF_Msk /*!< Registers Synchronized Flag */ |
5299 | #define RTC_CRL_CNF_Pos (4U) |
| 5300 | #define RTC_CRL_CNF_Pos (4U) |
5300 | #define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos) /*!< 0x00000010 */ |
| 5301 | #define RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos) /*!< 0x00000010 */ |
5301 | #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */ |
| 5302 | #define RTC_CRL_CNF RTC_CRL_CNF_Msk /*!< Configuration Flag */ |
5302 | #define RTC_CRL_RTOFF_Pos (5U) |
| 5303 | #define RTC_CRL_RTOFF_Pos (5U) |
5303 | #define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */ |
| 5304 | #define RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos) /*!< 0x00000020 */ |
5304 | #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */ |
| 5305 | #define RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk /*!< RTC operation OFF */ |
5305 | |
| 5306 | 5306 | /******************* Bit definition for RTC_PRLH register *******************/ |
|
| 5307 | /******************* Bit definition for RTC_PRLH register *******************/ |
5307 | #define RTC_PRLH_PRL_Pos (0U) |
| 5308 | #define RTC_PRLH_PRL_Pos (0U) |
5308 | #define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */ |
| 5309 | #define RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos) /*!< 0x0000000F */ |
5309 | #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */ |
| 5310 | #define RTC_PRLH_PRL RTC_PRLH_PRL_Msk /*!< RTC Prescaler Reload Value High */ |
5310 | |
| 5311 | 5311 | /******************* Bit definition for RTC_PRLL register *******************/ |
|
| 5312 | /******************* Bit definition for RTC_PRLL register *******************/ |
5312 | #define RTC_PRLL_PRL_Pos (0U) |
| 5313 | #define RTC_PRLL_PRL_Pos (0U) |
5313 | #define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */ |
| 5314 | #define RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos) /*!< 0x0000FFFF */ |
5314 | #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */ |
| 5315 | #define RTC_PRLL_PRL RTC_PRLL_PRL_Msk /*!< RTC Prescaler Reload Value Low */ |
5315 | |
| 5316 | 5316 | /******************* Bit definition for RTC_DIVH register *******************/ |
|
| 5317 | /******************* Bit definition for RTC_DIVH register *******************/ |
5317 | #define RTC_DIVH_RTC_DIV_Pos (0U) |
| 5318 | #define RTC_DIVH_RTC_DIV_Pos (0U) |
5318 | #define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */ |
| 5319 | #define RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos) /*!< 0x0000000F */ |
5319 | #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */ |
| 5320 | #define RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk /*!< RTC Clock Divider High */ |
5320 | |
| 5321 | 5321 | /******************* Bit definition for RTC_DIVL register *******************/ |
|
| 5322 | /******************* Bit definition for RTC_DIVL register *******************/ |
5322 | #define RTC_DIVL_RTC_DIV_Pos (0U) |
| 5323 | #define RTC_DIVL_RTC_DIV_Pos (0U) |
5323 | #define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */ |
| 5324 | #define RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos) /*!< 0x0000FFFF */ |
5324 | #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */ |
| 5325 | #define RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk /*!< RTC Clock Divider Low */ |
5325 | |
| 5326 | 5326 | /******************* Bit definition for RTC_CNTH register *******************/ |
|
| 5327 | /******************* Bit definition for RTC_CNTH register *******************/ |
5327 | #define RTC_CNTH_RTC_CNT_Pos (0U) |
| 5328 | #define RTC_CNTH_RTC_CNT_Pos (0U) |
5328 | #define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */ |
| 5329 | #define RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos) /*!< 0x0000FFFF */ |
5329 | #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */ |
| 5330 | #define RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk /*!< RTC Counter High */ |
5330 | |
| 5331 | 5331 | /******************* Bit definition for RTC_CNTL register *******************/ |
|
| 5332 | /******************* Bit definition for RTC_CNTL register *******************/ |
5332 | #define RTC_CNTL_RTC_CNT_Pos (0U) |
| 5333 | #define RTC_CNTL_RTC_CNT_Pos (0U) |
5333 | #define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */ |
| 5334 | #define RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos) /*!< 0x0000FFFF */ |
5334 | #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */ |
| 5335 | #define RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk /*!< RTC Counter Low */ |
5335 | |
| 5336 | 5336 | /******************* Bit definition for RTC_ALRH register *******************/ |
|
| 5337 | /******************* Bit definition for RTC_ALRH register *******************/ |
5337 | #define RTC_ALRH_RTC_ALR_Pos (0U) |
| 5338 | #define RTC_ALRH_RTC_ALR_Pos (0U) |
5338 | #define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */ |
| 5339 | #define RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos) /*!< 0x0000FFFF */ |
5339 | #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */ |
| 5340 | #define RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk /*!< RTC Alarm High */ |
5340 | |
| 5341 | 5341 | /******************* Bit definition for RTC_ALRL register *******************/ |
|
| 5342 | /******************* Bit definition for RTC_ALRL register *******************/ |
5342 | #define RTC_ALRL_RTC_ALR_Pos (0U) |
| 5343 | #define RTC_ALRL_RTC_ALR_Pos (0U) |
5343 | #define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */ |
| 5344 | #define RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos) /*!< 0x0000FFFF */ |
5344 | #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */ |
| 5345 | #define RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk /*!< RTC Alarm Low */ |
5345 | |
| 5346 | 5346 | /******************************************************************************/ |
|
| 5347 | /******************************************************************************/ |
5347 | /* */ |
| 5348 | /* */ |
5348 | /* Independent WATCHDOG (IWDG) */ |
| 5349 | /* Independent WATCHDOG (IWDG) */ |
5349 | /* */ |
| 5350 | /* */ |
5350 | /******************************************************************************/ |
| 5351 | /******************************************************************************/ |
5351 | |
| 5352 | 5352 | /******************* Bit definition for IWDG_KR register ********************/ |
|
| 5353 | /******************* Bit definition for IWDG_KR register ********************/ |
5353 | #define IWDG_KR_KEY_Pos (0U) |
| 5354 | #define IWDG_KR_KEY_Pos (0U) |
5354 | #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ |
| 5355 | #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ |
5355 | #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ |
| 5356 | #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */ |
5356 | |
| 5357 | 5357 | /******************* Bit definition for IWDG_PR register ********************/ |
|
| 5358 | /******************* Bit definition for IWDG_PR register ********************/ |
5358 | #define IWDG_PR_PR_Pos (0U) |
| 5359 | #define IWDG_PR_PR_Pos (0U) |
5359 | #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ |
| 5360 | #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */ |
5360 | #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ |
| 5361 | #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */ |
5361 | #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ |
| 5362 | #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */ |
5362 | #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ |
| 5363 | #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */ |
5363 | #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ |
| 5364 | #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */ |
5364 | |
| 5365 | 5365 | /******************* Bit definition for IWDG_RLR register *******************/ |
|
| 5366 | /******************* Bit definition for IWDG_RLR register *******************/ |
5366 | #define IWDG_RLR_RL_Pos (0U) |
| 5367 | #define IWDG_RLR_RL_Pos (0U) |
5367 | #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ |
| 5368 | #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */ |
5368 | #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ |
| 5369 | #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */ |
5369 | |
| 5370 | 5370 | /******************* Bit definition for IWDG_SR register ********************/ |
|
| 5371 | /******************* Bit definition for IWDG_SR register ********************/ |
5371 | #define IWDG_SR_PVU_Pos (0U) |
| 5372 | #define IWDG_SR_PVU_Pos (0U) |
5372 | #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ |
| 5373 | #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */ |
5373 | #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ |
| 5374 | #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */ |
5374 | #define IWDG_SR_RVU_Pos (1U) |
| 5375 | #define IWDG_SR_RVU_Pos (1U) |
5375 | #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ |
| 5376 | #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */ |
5376 | #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ |
| 5377 | #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */ |
5377 | |
| 5378 | 5378 | /******************************************************************************/ |
|
| 5379 | /******************************************************************************/ |
5379 | /* */ |
| 5380 | /* */ |
5380 | /* Window WATCHDOG (WWDG) */ |
| 5381 | /* Window WATCHDOG (WWDG) */ |
5381 | /* */ |
| 5382 | /* */ |
5382 | /******************************************************************************/ |
| 5383 | /******************************************************************************/ |
5383 | |
| 5384 | 5384 | /******************* Bit definition for WWDG_CR register ********************/ |
|
| 5385 | /******************* Bit definition for WWDG_CR register ********************/ |
5385 | #define WWDG_CR_T_Pos (0U) |
| 5386 | #define WWDG_CR_T_Pos (0U) |
5386 | #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ |
| 5387 | #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */ |
5387 | #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
| 5388 | #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */ |
5388 | #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ |
| 5389 | #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */ |
5389 | #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ |
| 5390 | #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */ |
5390 | #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ |
| 5391 | #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */ |
5391 | #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ |
| 5392 | #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */ |
5392 | #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ |
| 5393 | #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */ |
5393 | #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ |
| 5394 | #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */ |
5394 | #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ |
| 5395 | #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */ |
5395 | |
| 5396 | 5396 | /* Legacy defines */ |
|
| 5397 | /* Legacy defines */ |
5397 | #define WWDG_CR_T0 WWDG_CR_T_0 |
| 5398 | #define WWDG_CR_T0 WWDG_CR_T_0 |
5398 | #define WWDG_CR_T1 WWDG_CR_T_1 |
| 5399 | #define WWDG_CR_T1 WWDG_CR_T_1 |
5399 | #define WWDG_CR_T2 WWDG_CR_T_2 |
| 5400 | #define WWDG_CR_T2 WWDG_CR_T_2 |
5400 | #define WWDG_CR_T3 WWDG_CR_T_3 |
| 5401 | #define WWDG_CR_T3 WWDG_CR_T_3 |
5401 | #define WWDG_CR_T4 WWDG_CR_T_4 |
| 5402 | #define WWDG_CR_T4 WWDG_CR_T_4 |
5402 | #define WWDG_CR_T5 WWDG_CR_T_5 |
| 5403 | #define WWDG_CR_T5 WWDG_CR_T_5 |
5403 | #define WWDG_CR_T6 WWDG_CR_T_6 |
| 5404 | #define WWDG_CR_T6 WWDG_CR_T_6 |
5404 | |
| 5405 | 5405 | #define WWDG_CR_WDGA_Pos (7U) |
|
| 5406 | #define WWDG_CR_WDGA_Pos (7U) |
5406 | #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ |
| 5407 | #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */ |
5407 | #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ |
| 5408 | #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */ |
5408 | |
| 5409 | 5409 | /******************* Bit definition for WWDG_CFR register *******************/ |
|
| 5410 | /******************* Bit definition for WWDG_CFR register *******************/ |
5410 | #define WWDG_CFR_W_Pos (0U) |
| 5411 | #define WWDG_CFR_W_Pos (0U) |
5411 | #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ |
| 5412 | #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */ |
5412 | #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ |
| 5413 | #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */ |
5413 | #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ |
| 5414 | #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */ |
5414 | #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ |
| 5415 | #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */ |
5415 | #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ |
| 5416 | #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */ |
5416 | #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ |
| 5417 | #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */ |
5417 | #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ |
| 5418 | #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */ |
5418 | #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ |
| 5419 | #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */ |
5419 | #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ |
| 5420 | #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */ |
5420 | |
| 5421 | 5421 | /* Legacy defines */ |
|
| 5422 | /* Legacy defines */ |
5422 | #define WWDG_CFR_W0 WWDG_CFR_W_0 |
| 5423 | #define WWDG_CFR_W0 WWDG_CFR_W_0 |
5423 | #define WWDG_CFR_W1 WWDG_CFR_W_1 |
| 5424 | #define WWDG_CFR_W1 WWDG_CFR_W_1 |
5424 | #define WWDG_CFR_W2 WWDG_CFR_W_2 |
| 5425 | #define WWDG_CFR_W2 WWDG_CFR_W_2 |
5425 | #define WWDG_CFR_W3 WWDG_CFR_W_3 |
| 5426 | #define WWDG_CFR_W3 WWDG_CFR_W_3 |
5426 | #define WWDG_CFR_W4 WWDG_CFR_W_4 |
| 5427 | #define WWDG_CFR_W4 WWDG_CFR_W_4 |
5427 | #define WWDG_CFR_W5 WWDG_CFR_W_5 |
| 5428 | #define WWDG_CFR_W5 WWDG_CFR_W_5 |
5428 | #define WWDG_CFR_W6 WWDG_CFR_W_6 |
| 5429 | #define WWDG_CFR_W6 WWDG_CFR_W_6 |
5429 | |
| 5430 | 5430 | #define WWDG_CFR_WDGTB_Pos (7U) |
|
| 5431 | #define WWDG_CFR_WDGTB_Pos (7U) |
5431 | #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ |
| 5432 | #define WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */ |
5432 | #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ |
| 5433 | #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */ |
5433 | #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ |
| 5434 | #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */ |
5434 | #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ |
| 5435 | #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */ |
5435 | |
| 5436 | 5436 | /* Legacy defines */ |
|
| 5437 | /* Legacy defines */ |
5437 | #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 |
| 5438 | #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 |
5438 | #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 |
| 5439 | #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 |
5439 | |
| 5440 | 5440 | #define WWDG_CFR_EWI_Pos (9U) |
|
| 5441 | #define WWDG_CFR_EWI_Pos (9U) |
5441 | #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ |
| 5442 | #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */ |
5442 | #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ |
| 5443 | #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */ |
5443 | |
| 5444 | 5444 | /******************* Bit definition for WWDG_SR register ********************/ |
|
| 5445 | /******************* Bit definition for WWDG_SR register ********************/ |
5445 | #define WWDG_SR_EWIF_Pos (0U) |
| 5446 | #define WWDG_SR_EWIF_Pos (0U) |
5446 | #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ |
| 5447 | #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */ |
5447 | #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ |
| 5448 | #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */ |
5448 | |
| 5449 | 5449 | ||
| 5450 | 5450 | /******************************************************************************/ |
|
| 5451 | /******************************************************************************/ |
5451 | /* */ |
| 5452 | /* */ |
5452 | /* Controller Area Network */ |
| 5453 | /* Controller Area Network */ |
5453 | /* */ |
| 5454 | /* */ |
5454 | /******************************************************************************/ |
| 5455 | /******************************************************************************/ |
5455 | |
| 5456 | 5456 | /*!< CAN control and status registers */ |
|
| 5457 | /*!< CAN control and status registers */ |
5457 | /******************* Bit definition for CAN_MCR register ********************/ |
| 5458 | /******************* Bit definition for CAN_MCR register ********************/ |
5458 | #define CAN_MCR_INRQ_Pos (0U) |
| 5459 | #define CAN_MCR_INRQ_Pos (0U) |
5459 | #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ |
| 5460 | #define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */ |
5460 | #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */ |
| 5461 | #define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!< Initialization Request */ |
5461 | #define CAN_MCR_SLEEP_Pos (1U) |
| 5462 | #define CAN_MCR_SLEEP_Pos (1U) |
5462 | #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ |
| 5463 | #define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */ |
5463 | #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */ |
| 5464 | #define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!< Sleep Mode Request */ |
5464 | #define CAN_MCR_TXFP_Pos (2U) |
| 5465 | #define CAN_MCR_TXFP_Pos (2U) |
5465 | #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ |
| 5466 | #define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */ |
5466 | #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */ |
| 5467 | #define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!< Transmit FIFO Priority */ |
5467 | #define CAN_MCR_RFLM_Pos (3U) |
| 5468 | #define CAN_MCR_RFLM_Pos (3U) |
5468 | #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ |
| 5469 | #define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */ |
5469 | #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */ |
| 5470 | #define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!< Receive FIFO Locked Mode */ |
5470 | #define CAN_MCR_NART_Pos (4U) |
| 5471 | #define CAN_MCR_NART_Pos (4U) |
5471 | #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */ |
| 5472 | #define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */ |
5472 | #define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */ |
| 5473 | #define CAN_MCR_NART CAN_MCR_NART_Msk /*!< No Automatic Retransmission */ |
5473 | #define CAN_MCR_AWUM_Pos (5U) |
| 5474 | #define CAN_MCR_AWUM_Pos (5U) |
5474 | #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ |
| 5475 | #define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */ |
5475 | #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */ |
| 5476 | #define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!< Automatic Wakeup Mode */ |
5476 | #define CAN_MCR_ABOM_Pos (6U) |
| 5477 | #define CAN_MCR_ABOM_Pos (6U) |
5477 | #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ |
| 5478 | #define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */ |
5478 | #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */ |
| 5479 | #define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!< Automatic Bus-Off Management */ |
5479 | #define CAN_MCR_TTCM_Pos (7U) |
| 5480 | #define CAN_MCR_TTCM_Pos (7U) |
5480 | #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ |
| 5481 | #define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */ |
5481 | #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */ |
| 5482 | #define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!< Time Triggered Communication Mode */ |
5482 | #define CAN_MCR_RESET_Pos (15U) |
| 5483 | #define CAN_MCR_RESET_Pos (15U) |
5483 | #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ |
| 5484 | #define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */ |
5484 | #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */ |
| 5485 | #define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< CAN software master reset */ |
5485 | #define CAN_MCR_DBF_Pos (16U) |
| 5486 | #define CAN_MCR_DBF_Pos (16U) |
5486 | #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos) /*!< 0x00010000 */ |
| 5487 | #define CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos) /*!< 0x00010000 */ |
5487 | #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */ |
| 5488 | #define CAN_MCR_DBF CAN_MCR_DBF_Msk /*!< CAN Debug freeze */ |
5488 | |
| 5489 | 5489 | /******************* Bit definition for CAN_MSR register ********************/ |
|
| 5490 | /******************* Bit definition for CAN_MSR register ********************/ |
5490 | #define CAN_MSR_INAK_Pos (0U) |
| 5491 | #define CAN_MSR_INAK_Pos (0U) |
5491 | #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ |
| 5492 | #define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */ |
5492 | #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */ |
| 5493 | #define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!< Initialization Acknowledge */ |
5493 | #define CAN_MSR_SLAK_Pos (1U) |
| 5494 | #define CAN_MSR_SLAK_Pos (1U) |
5494 | #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ |
| 5495 | #define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */ |
5495 | #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */ |
| 5496 | #define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!< Sleep Acknowledge */ |
5496 | #define CAN_MSR_ERRI_Pos (2U) |
| 5497 | #define CAN_MSR_ERRI_Pos (2U) |
5497 | #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ |
| 5498 | #define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */ |
5498 | #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */ |
| 5499 | #define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!< Error Interrupt */ |
5499 | #define CAN_MSR_WKUI_Pos (3U) |
| 5500 | #define CAN_MSR_WKUI_Pos (3U) |
5500 | #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ |
| 5501 | #define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */ |
5501 | #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */ |
| 5502 | #define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!< Wakeup Interrupt */ |
5502 | #define CAN_MSR_SLAKI_Pos (4U) |
| 5503 | #define CAN_MSR_SLAKI_Pos (4U) |
5503 | #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ |
| 5504 | #define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */ |
5504 | #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */ |
| 5505 | #define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!< Sleep Acknowledge Interrupt */ |
5505 | #define CAN_MSR_TXM_Pos (8U) |
| 5506 | #define CAN_MSR_TXM_Pos (8U) |
5506 | #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ |
| 5507 | #define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */ |
5507 | #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */ |
| 5508 | #define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!< Transmit Mode */ |
5508 | #define CAN_MSR_RXM_Pos (9U) |
| 5509 | #define CAN_MSR_RXM_Pos (9U) |
5509 | #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ |
| 5510 | #define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */ |
5510 | #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */ |
| 5511 | #define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!< Receive Mode */ |
5511 | #define CAN_MSR_SAMP_Pos (10U) |
| 5512 | #define CAN_MSR_SAMP_Pos (10U) |
5512 | #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ |
| 5513 | #define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */ |
5513 | #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */ |
| 5514 | #define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!< Last Sample Point */ |
5514 | #define CAN_MSR_RX_Pos (11U) |
| 5515 | #define CAN_MSR_RX_Pos (11U) |
5515 | #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */ |
| 5516 | #define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */ |
5516 | #define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */ |
| 5517 | #define CAN_MSR_RX CAN_MSR_RX_Msk /*!< CAN Rx Signal */ |
5517 | |
| 5518 | 5518 | /******************* Bit definition for CAN_TSR register ********************/ |
|
| 5519 | /******************* Bit definition for CAN_TSR register ********************/ |
5519 | #define CAN_TSR_RQCP0_Pos (0U) |
| 5520 | #define CAN_TSR_RQCP0_Pos (0U) |
5520 | #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ |
| 5521 | #define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */ |
5521 | #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */ |
| 5522 | #define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!< Request Completed Mailbox0 */ |
5522 | #define CAN_TSR_TXOK0_Pos (1U) |
| 5523 | #define CAN_TSR_TXOK0_Pos (1U) |
5523 | #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ |
| 5524 | #define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */ |
5524 | #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */ |
| 5525 | #define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!< Transmission OK of Mailbox0 */ |
5525 | #define CAN_TSR_ALST0_Pos (2U) |
| 5526 | #define CAN_TSR_ALST0_Pos (2U) |
5526 | #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ |
| 5527 | #define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */ |
5527 | #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */ |
| 5528 | #define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!< Arbitration Lost for Mailbox0 */ |
5528 | #define CAN_TSR_TERR0_Pos (3U) |
| 5529 | #define CAN_TSR_TERR0_Pos (3U) |
5529 | #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ |
| 5530 | #define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */ |
5530 | #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */ |
| 5531 | #define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!< Transmission Error of Mailbox0 */ |
5531 | #define CAN_TSR_ABRQ0_Pos (7U) |
| 5532 | #define CAN_TSR_ABRQ0_Pos (7U) |
5532 | #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ |
| 5533 | #define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */ |
5533 | #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */ |
| 5534 | #define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!< Abort Request for Mailbox0 */ |
5534 | #define CAN_TSR_RQCP1_Pos (8U) |
| 5535 | #define CAN_TSR_RQCP1_Pos (8U) |
5535 | #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ |
| 5536 | #define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */ |
5536 | #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */ |
| 5537 | #define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!< Request Completed Mailbox1 */ |
5537 | #define CAN_TSR_TXOK1_Pos (9U) |
| 5538 | #define CAN_TSR_TXOK1_Pos (9U) |
5538 | #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ |
| 5539 | #define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */ |
5539 | #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */ |
| 5540 | #define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!< Transmission OK of Mailbox1 */ |
5540 | #define CAN_TSR_ALST1_Pos (10U) |
| 5541 | #define CAN_TSR_ALST1_Pos (10U) |
5541 | #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ |
| 5542 | #define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */ |
5542 | #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */ |
| 5543 | #define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!< Arbitration Lost for Mailbox1 */ |
5543 | #define CAN_TSR_TERR1_Pos (11U) |
| 5544 | #define CAN_TSR_TERR1_Pos (11U) |
5544 | #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ |
| 5545 | #define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */ |
5545 | #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */ |
| 5546 | #define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!< Transmission Error of Mailbox1 */ |
5546 | #define CAN_TSR_ABRQ1_Pos (15U) |
| 5547 | #define CAN_TSR_ABRQ1_Pos (15U) |
5547 | #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ |
| 5548 | #define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */ |
5548 | #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */ |
| 5549 | #define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!< Abort Request for Mailbox 1 */ |
5549 | #define CAN_TSR_RQCP2_Pos (16U) |
| 5550 | #define CAN_TSR_RQCP2_Pos (16U) |
5550 | #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ |
| 5551 | #define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */ |
5551 | #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */ |
| 5552 | #define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!< Request Completed Mailbox2 */ |
5552 | #define CAN_TSR_TXOK2_Pos (17U) |
| 5553 | #define CAN_TSR_TXOK2_Pos (17U) |
5553 | #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ |
| 5554 | #define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */ |
5554 | #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */ |
| 5555 | #define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!< Transmission OK of Mailbox 2 */ |
5555 | #define CAN_TSR_ALST2_Pos (18U) |
| 5556 | #define CAN_TSR_ALST2_Pos (18U) |
5556 | #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ |
| 5557 | #define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */ |
5557 | #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */ |
| 5558 | #define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!< Arbitration Lost for mailbox 2 */ |
5558 | #define CAN_TSR_TERR2_Pos (19U) |
| 5559 | #define CAN_TSR_TERR2_Pos (19U) |
5559 | #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ |
| 5560 | #define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */ |
5560 | #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */ |
| 5561 | #define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!< Transmission Error of Mailbox 2 */ |
5561 | #define CAN_TSR_ABRQ2_Pos (23U) |
| 5562 | #define CAN_TSR_ABRQ2_Pos (23U) |
5562 | #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ |
| 5563 | #define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */ |
5563 | #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */ |
| 5564 | #define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!< Abort Request for Mailbox 2 */ |
5564 | #define CAN_TSR_CODE_Pos (24U) |
| 5565 | #define CAN_TSR_CODE_Pos (24U) |
5565 | #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ |
| 5566 | #define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */ |
5566 | #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */ |
| 5567 | #define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!< Mailbox Code */ |
5567 | |
| 5568 | 5568 | #define CAN_TSR_TME_Pos (26U) |
|
| 5569 | #define CAN_TSR_TME_Pos (26U) |
5569 | #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ |
| 5570 | #define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */ |
5570 | #define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */ |
| 5571 | #define CAN_TSR_TME CAN_TSR_TME_Msk /*!< TME[2:0] bits */ |
5571 | #define CAN_TSR_TME0_Pos (26U) |
| 5572 | #define CAN_TSR_TME0_Pos (26U) |
5572 | #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ |
| 5573 | #define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */ |
5573 | #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */ |
| 5574 | #define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!< Transmit Mailbox 0 Empty */ |
5574 | #define CAN_TSR_TME1_Pos (27U) |
| 5575 | #define CAN_TSR_TME1_Pos (27U) |
5575 | #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ |
| 5576 | #define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */ |
5576 | #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */ |
| 5577 | #define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!< Transmit Mailbox 1 Empty */ |
5577 | #define CAN_TSR_TME2_Pos (28U) |
| 5578 | #define CAN_TSR_TME2_Pos (28U) |
5578 | #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ |
| 5579 | #define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */ |
5579 | #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */ |
| 5580 | #define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!< Transmit Mailbox 2 Empty */ |
5580 | |
| 5581 | 5581 | #define CAN_TSR_LOW_Pos (29U) |
|
| 5582 | #define CAN_TSR_LOW_Pos (29U) |
5582 | #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ |
| 5583 | #define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */ |
5583 | #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */ |
| 5584 | #define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!< LOW[2:0] bits */ |
5584 | #define CAN_TSR_LOW0_Pos (29U) |
| 5585 | #define CAN_TSR_LOW0_Pos (29U) |
5585 | #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ |
| 5586 | #define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */ |
5586 | #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */ |
| 5587 | #define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!< Lowest Priority Flag for Mailbox 0 */ |
5587 | #define CAN_TSR_LOW1_Pos (30U) |
| 5588 | #define CAN_TSR_LOW1_Pos (30U) |
5588 | #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ |
| 5589 | #define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */ |
5589 | #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */ |
| 5590 | #define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!< Lowest Priority Flag for Mailbox 1 */ |
5590 | #define CAN_TSR_LOW2_Pos (31U) |
| 5591 | #define CAN_TSR_LOW2_Pos (31U) |
5591 | #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ |
| 5592 | #define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */ |
5592 | #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */ |
| 5593 | #define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!< Lowest Priority Flag for Mailbox 2 */ |
5593 | |
| 5594 | 5594 | /******************* Bit definition for CAN_RF0R register *******************/ |
|
| 5595 | /******************* Bit definition for CAN_RF0R register *******************/ |
5595 | #define CAN_RF0R_FMP0_Pos (0U) |
| 5596 | #define CAN_RF0R_FMP0_Pos (0U) |
5596 | #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ |
| 5597 | #define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */ |
5597 | #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */ |
| 5598 | #define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!< FIFO 0 Message Pending */ |
5598 | #define CAN_RF0R_FULL0_Pos (3U) |
| 5599 | #define CAN_RF0R_FULL0_Pos (3U) |
5599 | #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ |
| 5600 | #define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */ |
5600 | #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */ |
| 5601 | #define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!< FIFO 0 Full */ |
5601 | #define CAN_RF0R_FOVR0_Pos (4U) |
| 5602 | #define CAN_RF0R_FOVR0_Pos (4U) |
5602 | #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ |
| 5603 | #define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */ |
5603 | #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */ |
| 5604 | #define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!< FIFO 0 Overrun */ |
5604 | #define CAN_RF0R_RFOM0_Pos (5U) |
| 5605 | #define CAN_RF0R_RFOM0_Pos (5U) |
5605 | #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ |
| 5606 | #define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */ |
5606 | #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */ |
| 5607 | #define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!< Release FIFO 0 Output Mailbox */ |
5607 | |
| 5608 | 5608 | /******************* Bit definition for CAN_RF1R register *******************/ |
|
| 5609 | /******************* Bit definition for CAN_RF1R register *******************/ |
5609 | #define CAN_RF1R_FMP1_Pos (0U) |
| 5610 | #define CAN_RF1R_FMP1_Pos (0U) |
5610 | #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ |
| 5611 | #define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */ |
5611 | #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */ |
| 5612 | #define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!< FIFO 1 Message Pending */ |
5612 | #define CAN_RF1R_FULL1_Pos (3U) |
| 5613 | #define CAN_RF1R_FULL1_Pos (3U) |
5613 | #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ |
| 5614 | #define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */ |
5614 | #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */ |
| 5615 | #define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!< FIFO 1 Full */ |
5615 | #define CAN_RF1R_FOVR1_Pos (4U) |
| 5616 | #define CAN_RF1R_FOVR1_Pos (4U) |
5616 | #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ |
| 5617 | #define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */ |
5617 | #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */ |
| 5618 | #define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!< FIFO 1 Overrun */ |
5618 | #define CAN_RF1R_RFOM1_Pos (5U) |
| 5619 | #define CAN_RF1R_RFOM1_Pos (5U) |
5619 | #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ |
| 5620 | #define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */ |
5620 | #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */ |
| 5621 | #define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!< Release FIFO 1 Output Mailbox */ |
5621 | |
| 5622 | 5622 | /******************** Bit definition for CAN_IER register *******************/ |
|
| 5623 | /******************** Bit definition for CAN_IER register *******************/ |
5623 | #define CAN_IER_TMEIE_Pos (0U) |
| 5624 | #define CAN_IER_TMEIE_Pos (0U) |
5624 | #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ |
| 5625 | #define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */ |
5625 | #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */ |
| 5626 | #define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!< Transmit Mailbox Empty Interrupt Enable */ |
5626 | #define CAN_IER_FMPIE0_Pos (1U) |
| 5627 | #define CAN_IER_FMPIE0_Pos (1U) |
5627 | #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ |
| 5628 | #define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */ |
5628 | #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */ |
| 5629 | #define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!< FIFO Message Pending Interrupt Enable */ |
5629 | #define CAN_IER_FFIE0_Pos (2U) |
| 5630 | #define CAN_IER_FFIE0_Pos (2U) |
5630 | #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ |
| 5631 | #define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */ |
5631 | #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */ |
| 5632 | #define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!< FIFO Full Interrupt Enable */ |
5632 | #define CAN_IER_FOVIE0_Pos (3U) |
| 5633 | #define CAN_IER_FOVIE0_Pos (3U) |
5633 | #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ |
| 5634 | #define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */ |
5634 | #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */ |
| 5635 | #define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!< FIFO Overrun Interrupt Enable */ |
5635 | #define CAN_IER_FMPIE1_Pos (4U) |
| 5636 | #define CAN_IER_FMPIE1_Pos (4U) |
5636 | #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ |
| 5637 | #define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */ |
5637 | #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */ |
| 5638 | #define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!< FIFO Message Pending Interrupt Enable */ |
5638 | #define CAN_IER_FFIE1_Pos (5U) |
| 5639 | #define CAN_IER_FFIE1_Pos (5U) |
5639 | #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ |
| 5640 | #define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */ |
5640 | #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */ |
| 5641 | #define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!< FIFO Full Interrupt Enable */ |
5641 | #define CAN_IER_FOVIE1_Pos (6U) |
| 5642 | #define CAN_IER_FOVIE1_Pos (6U) |
5642 | #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ |
| 5643 | #define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */ |
5643 | #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */ |
| 5644 | #define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!< FIFO Overrun Interrupt Enable */ |
5644 | #define CAN_IER_EWGIE_Pos (8U) |
| 5645 | #define CAN_IER_EWGIE_Pos (8U) |
5645 | #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ |
| 5646 | #define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */ |
5646 | #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */ |
| 5647 | #define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!< Error Warning Interrupt Enable */ |
5647 | #define CAN_IER_EPVIE_Pos (9U) |
| 5648 | #define CAN_IER_EPVIE_Pos (9U) |
5648 | #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ |
| 5649 | #define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */ |
5649 | #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */ |
| 5650 | #define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!< Error Passive Interrupt Enable */ |
5650 | #define CAN_IER_BOFIE_Pos (10U) |
| 5651 | #define CAN_IER_BOFIE_Pos (10U) |
5651 | #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ |
| 5652 | #define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */ |
5652 | #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */ |
| 5653 | #define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!< Bus-Off Interrupt Enable */ |
5653 | #define CAN_IER_LECIE_Pos (11U) |
| 5654 | #define CAN_IER_LECIE_Pos (11U) |
5654 | #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ |
| 5655 | #define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */ |
5655 | #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */ |
| 5656 | #define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!< Last Error Code Interrupt Enable */ |
5656 | #define CAN_IER_ERRIE_Pos (15U) |
| 5657 | #define CAN_IER_ERRIE_Pos (15U) |
5657 | #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ |
| 5658 | #define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */ |
5658 | #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */ |
| 5659 | #define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!< Error Interrupt Enable */ |
5659 | #define CAN_IER_WKUIE_Pos (16U) |
| 5660 | #define CAN_IER_WKUIE_Pos (16U) |
5660 | #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ |
| 5661 | #define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */ |
5661 | #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */ |
| 5662 | #define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!< Wakeup Interrupt Enable */ |
5662 | #define CAN_IER_SLKIE_Pos (17U) |
| 5663 | #define CAN_IER_SLKIE_Pos (17U) |
5663 | #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ |
| 5664 | #define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */ |
5664 | #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */ |
| 5665 | #define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!< Sleep Interrupt Enable */ |
5665 | |
| 5666 | 5666 | /******************** Bit definition for CAN_ESR register *******************/ |
|
| 5667 | /******************** Bit definition for CAN_ESR register *******************/ |
5667 | #define CAN_ESR_EWGF_Pos (0U) |
| 5668 | #define CAN_ESR_EWGF_Pos (0U) |
5668 | #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ |
| 5669 | #define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */ |
5669 | #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */ |
| 5670 | #define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!< Error Warning Flag */ |
5670 | #define CAN_ESR_EPVF_Pos (1U) |
| 5671 | #define CAN_ESR_EPVF_Pos (1U) |
5671 | #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ |
| 5672 | #define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */ |
5672 | #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */ |
| 5673 | #define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!< Error Passive Flag */ |
5673 | #define CAN_ESR_BOFF_Pos (2U) |
| 5674 | #define CAN_ESR_BOFF_Pos (2U) |
5674 | #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ |
| 5675 | #define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */ |
5675 | #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */ |
| 5676 | #define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!< Bus-Off Flag */ |
5676 | |
| 5677 | 5677 | #define CAN_ESR_LEC_Pos (4U) |
|
| 5678 | #define CAN_ESR_LEC_Pos (4U) |
5678 | #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ |
| 5679 | #define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */ |
5679 | #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */ |
| 5680 | #define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!< LEC[2:0] bits (Last Error Code) */ |
5680 | #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ |
| 5681 | #define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */ |
5681 | #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ |
| 5682 | #define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */ |
5682 | #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ |
| 5683 | #define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */ |
5683 | |
| 5684 | 5684 | #define CAN_ESR_TEC_Pos (16U) |
|
| 5685 | #define CAN_ESR_TEC_Pos (16U) |
5685 | #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ |
| 5686 | #define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */ |
5686 | #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */ |
| 5687 | #define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!< Least significant byte of the 9-bit Transmit Error Counter */ |
5687 | #define CAN_ESR_REC_Pos (24U) |
| 5688 | #define CAN_ESR_REC_Pos (24U) |
5688 | #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ |
| 5689 | #define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */ |
5689 | #define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */ |
| 5690 | #define CAN_ESR_REC CAN_ESR_REC_Msk /*!< Receive Error Counter */ |
5690 | |
| 5691 | 5691 | /******************* Bit definition for CAN_BTR register ********************/ |
|
| 5692 | /******************* Bit definition for CAN_BTR register ********************/ |
5692 | #define CAN_BTR_BRP_Pos (0U) |
| 5693 | #define CAN_BTR_BRP_Pos (0U) |
5693 | #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ |
| 5694 | #define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */ |
5694 | #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ |
| 5695 | #define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */ |
5695 | #define CAN_BTR_TS1_Pos (16U) |
| 5696 | #define CAN_BTR_TS1_Pos (16U) |
5696 | #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ |
| 5697 | #define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */ |
5697 | #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ |
| 5698 | #define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */ |
5698 | #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ |
| 5699 | #define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */ |
5699 | #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ |
| 5700 | #define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */ |
5700 | #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ |
| 5701 | #define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */ |
5701 | #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ |
| 5702 | #define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */ |
5702 | #define CAN_BTR_TS2_Pos (20U) |
| 5703 | #define CAN_BTR_TS2_Pos (20U) |
5703 | #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ |
| 5704 | #define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */ |
5704 | #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ |
| 5705 | #define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */ |
5705 | #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ |
| 5706 | #define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */ |
5706 | #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ |
| 5707 | #define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */ |
5707 | #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ |
| 5708 | #define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */ |
5708 | #define CAN_BTR_SJW_Pos (24U) |
| 5709 | #define CAN_BTR_SJW_Pos (24U) |
5709 | #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ |
| 5710 | #define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */ |
5710 | #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ |
| 5711 | #define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */ |
5711 | #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ |
| 5712 | #define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */ |
5712 | #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ |
| 5713 | #define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */ |
5713 | #define CAN_BTR_LBKM_Pos (30U) |
| 5714 | #define CAN_BTR_LBKM_Pos (30U) |
5714 | #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ |
| 5715 | #define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */ |
5715 | #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ |
| 5716 | #define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */ |
5716 | #define CAN_BTR_SILM_Pos (31U) |
| 5717 | #define CAN_BTR_SILM_Pos (31U) |
5717 | #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ |
| 5718 | #define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */ |
5718 | #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ |
| 5719 | #define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */ |
5719 | |
| 5720 | 5720 | /*!< Mailbox registers */ |
|
| 5721 | /*!< Mailbox registers */ |
5721 | /****************** Bit definition for CAN_TI0R register ********************/ |
| 5722 | /****************** Bit definition for CAN_TI0R register ********************/ |
5722 | #define CAN_TI0R_TXRQ_Pos (0U) |
| 5723 | #define CAN_TI0R_TXRQ_Pos (0U) |
5723 | #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ |
| 5724 | #define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */ |
5724 | #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */ |
| 5725 | #define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!< Transmit Mailbox Request */ |
5725 | #define CAN_TI0R_RTR_Pos (1U) |
| 5726 | #define CAN_TI0R_RTR_Pos (1U) |
5726 | #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ |
| 5727 | #define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */ |
5727 | #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */ |
| 5728 | #define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!< Remote Transmission Request */ |
5728 | #define CAN_TI0R_IDE_Pos (2U) |
| 5729 | #define CAN_TI0R_IDE_Pos (2U) |
5729 | #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ |
| 5730 | #define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */ |
5730 | #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */ |
| 5731 | #define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!< Identifier Extension */ |
5731 | #define CAN_TI0R_EXID_Pos (3U) |
| 5732 | #define CAN_TI0R_EXID_Pos (3U) |
5732 | #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| 5733 | #define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
5733 | #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */ |
| 5734 | #define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!< Extended Identifier */ |
5734 | #define CAN_TI0R_STID_Pos (21U) |
| 5735 | #define CAN_TI0R_STID_Pos (21U) |
5735 | #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ |
| 5736 | #define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */ |
5736 | #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
| 5737 | #define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
5737 | |
| 5738 | 5738 | /****************** Bit definition for CAN_TDT0R register *******************/ |
|
| 5739 | /****************** Bit definition for CAN_TDT0R register *******************/ |
5739 | #define CAN_TDT0R_DLC_Pos (0U) |
| 5740 | #define CAN_TDT0R_DLC_Pos (0U) |
5740 | #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ |
| 5741 | #define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */ |
5741 | #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */ |
| 5742 | #define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!< Data Length Code */ |
5742 | #define CAN_TDT0R_TGT_Pos (8U) |
| 5743 | #define CAN_TDT0R_TGT_Pos (8U) |
5743 | #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ |
| 5744 | #define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */ |
5744 | #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */ |
| 5745 | #define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!< Transmit Global Time */ |
5745 | #define CAN_TDT0R_TIME_Pos (16U) |
| 5746 | #define CAN_TDT0R_TIME_Pos (16U) |
5746 | #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| 5747 | #define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
5747 | #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */ |
| 5748 | #define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!< Message Time Stamp */ |
5748 | |
| 5749 | 5749 | /****************** Bit definition for CAN_TDL0R register *******************/ |
|
| 5750 | /****************** Bit definition for CAN_TDL0R register *******************/ |
5750 | #define CAN_TDL0R_DATA0_Pos (0U) |
| 5751 | #define CAN_TDL0R_DATA0_Pos (0U) |
5751 | #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| 5752 | #define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */ |
5752 | #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */ |
| 5753 | #define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!< Data byte 0 */ |
5753 | #define CAN_TDL0R_DATA1_Pos (8U) |
| 5754 | #define CAN_TDL0R_DATA1_Pos (8U) |
5754 | #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| 5755 | #define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
5755 | #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */ |
| 5756 | #define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!< Data byte 1 */ |
5756 | #define CAN_TDL0R_DATA2_Pos (16U) |
| 5757 | #define CAN_TDL0R_DATA2_Pos (16U) |
5757 | #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| 5758 | #define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
5758 | #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */ |
| 5759 | #define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!< Data byte 2 */ |
5759 | #define CAN_TDL0R_DATA3_Pos (24U) |
| 5760 | #define CAN_TDL0R_DATA3_Pos (24U) |
5760 | #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| 5761 | #define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
5761 | #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */ |
| 5762 | #define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!< Data byte 3 */ |
5762 | |
| 5763 | 5763 | /****************** Bit definition for CAN_TDH0R register *******************/ |
|
| 5764 | /****************** Bit definition for CAN_TDH0R register *******************/ |
5764 | #define CAN_TDH0R_DATA4_Pos (0U) |
| 5765 | #define CAN_TDH0R_DATA4_Pos (0U) |
5765 | #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| 5766 | #define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */ |
5766 | #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */ |
| 5767 | #define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!< Data byte 4 */ |
5767 | #define CAN_TDH0R_DATA5_Pos (8U) |
| 5768 | #define CAN_TDH0R_DATA5_Pos (8U) |
5768 | #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| 5769 | #define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
5769 | #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */ |
| 5770 | #define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!< Data byte 5 */ |
5770 | #define CAN_TDH0R_DATA6_Pos (16U) |
| 5771 | #define CAN_TDH0R_DATA6_Pos (16U) |
5771 | #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| 5772 | #define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
5772 | #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */ |
| 5773 | #define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!< Data byte 6 */ |
5773 | #define CAN_TDH0R_DATA7_Pos (24U) |
| 5774 | #define CAN_TDH0R_DATA7_Pos (24U) |
5774 | #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| 5775 | #define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
5775 | #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */ |
| 5776 | #define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!< Data byte 7 */ |
5776 | |
| 5777 | 5777 | /******************* Bit definition for CAN_TI1R register *******************/ |
|
| 5778 | /******************* Bit definition for CAN_TI1R register *******************/ |
5778 | #define CAN_TI1R_TXRQ_Pos (0U) |
| 5779 | #define CAN_TI1R_TXRQ_Pos (0U) |
5779 | #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ |
| 5780 | #define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */ |
5780 | #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */ |
| 5781 | #define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!< Transmit Mailbox Request */ |
5781 | #define CAN_TI1R_RTR_Pos (1U) |
| 5782 | #define CAN_TI1R_RTR_Pos (1U) |
5782 | #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ |
| 5783 | #define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */ |
5783 | #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */ |
| 5784 | #define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!< Remote Transmission Request */ |
5784 | #define CAN_TI1R_IDE_Pos (2U) |
| 5785 | #define CAN_TI1R_IDE_Pos (2U) |
5785 | #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ |
| 5786 | #define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */ |
5786 | #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */ |
| 5787 | #define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!< Identifier Extension */ |
5787 | #define CAN_TI1R_EXID_Pos (3U) |
| 5788 | #define CAN_TI1R_EXID_Pos (3U) |
5788 | #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| 5789 | #define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
5789 | #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */ |
| 5790 | #define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!< Extended Identifier */ |
5790 | #define CAN_TI1R_STID_Pos (21U) |
| 5791 | #define CAN_TI1R_STID_Pos (21U) |
5791 | #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ |
| 5792 | #define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */ |
5792 | #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
| 5793 | #define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
5793 | |
| 5794 | 5794 | /******************* Bit definition for CAN_TDT1R register ******************/ |
|
| 5795 | /******************* Bit definition for CAN_TDT1R register ******************/ |
5795 | #define CAN_TDT1R_DLC_Pos (0U) |
| 5796 | #define CAN_TDT1R_DLC_Pos (0U) |
5796 | #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ |
| 5797 | #define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */ |
5797 | #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */ |
| 5798 | #define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!< Data Length Code */ |
5798 | #define CAN_TDT1R_TGT_Pos (8U) |
| 5799 | #define CAN_TDT1R_TGT_Pos (8U) |
5799 | #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ |
| 5800 | #define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */ |
5800 | #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */ |
| 5801 | #define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!< Transmit Global Time */ |
5801 | #define CAN_TDT1R_TIME_Pos (16U) |
| 5802 | #define CAN_TDT1R_TIME_Pos (16U) |
5802 | #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| 5803 | #define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
5803 | #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */ |
| 5804 | #define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!< Message Time Stamp */ |
5804 | |
| 5805 | 5805 | /******************* Bit definition for CAN_TDL1R register ******************/ |
|
| 5806 | /******************* Bit definition for CAN_TDL1R register ******************/ |
5806 | #define CAN_TDL1R_DATA0_Pos (0U) |
| 5807 | #define CAN_TDL1R_DATA0_Pos (0U) |
5807 | #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| 5808 | #define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */ |
5808 | #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */ |
| 5809 | #define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!< Data byte 0 */ |
5809 | #define CAN_TDL1R_DATA1_Pos (8U) |
| 5810 | #define CAN_TDL1R_DATA1_Pos (8U) |
5810 | #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| 5811 | #define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
5811 | #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */ |
| 5812 | #define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!< Data byte 1 */ |
5812 | #define CAN_TDL1R_DATA2_Pos (16U) |
| 5813 | #define CAN_TDL1R_DATA2_Pos (16U) |
5813 | #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| 5814 | #define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
5814 | #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */ |
| 5815 | #define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!< Data byte 2 */ |
5815 | #define CAN_TDL1R_DATA3_Pos (24U) |
| 5816 | #define CAN_TDL1R_DATA3_Pos (24U) |
5816 | #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| 5817 | #define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
5817 | #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */ |
| 5818 | #define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!< Data byte 3 */ |
5818 | |
| 5819 | 5819 | /******************* Bit definition for CAN_TDH1R register ******************/ |
|
| 5820 | /******************* Bit definition for CAN_TDH1R register ******************/ |
5820 | #define CAN_TDH1R_DATA4_Pos (0U) |
| 5821 | #define CAN_TDH1R_DATA4_Pos (0U) |
5821 | #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| 5822 | #define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */ |
5822 | #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */ |
| 5823 | #define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!< Data byte 4 */ |
5823 | #define CAN_TDH1R_DATA5_Pos (8U) |
| 5824 | #define CAN_TDH1R_DATA5_Pos (8U) |
5824 | #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| 5825 | #define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
5825 | #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */ |
| 5826 | #define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!< Data byte 5 */ |
5826 | #define CAN_TDH1R_DATA6_Pos (16U) |
| 5827 | #define CAN_TDH1R_DATA6_Pos (16U) |
5827 | #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| 5828 | #define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
5828 | #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */ |
| 5829 | #define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!< Data byte 6 */ |
5829 | #define CAN_TDH1R_DATA7_Pos (24U) |
| 5830 | #define CAN_TDH1R_DATA7_Pos (24U) |
5830 | #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| 5831 | #define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
5831 | #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */ |
| 5832 | #define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!< Data byte 7 */ |
5832 | |
| 5833 | 5833 | /******************* Bit definition for CAN_TI2R register *******************/ |
|
| 5834 | /******************* Bit definition for CAN_TI2R register *******************/ |
5834 | #define CAN_TI2R_TXRQ_Pos (0U) |
| 5835 | #define CAN_TI2R_TXRQ_Pos (0U) |
5835 | #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ |
| 5836 | #define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */ |
5836 | #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */ |
| 5837 | #define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!< Transmit Mailbox Request */ |
5837 | #define CAN_TI2R_RTR_Pos (1U) |
| 5838 | #define CAN_TI2R_RTR_Pos (1U) |
5838 | #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ |
| 5839 | #define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */ |
5839 | #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */ |
| 5840 | #define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!< Remote Transmission Request */ |
5840 | #define CAN_TI2R_IDE_Pos (2U) |
| 5841 | #define CAN_TI2R_IDE_Pos (2U) |
5841 | #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ |
| 5842 | #define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */ |
5842 | #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */ |
| 5843 | #define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!< Identifier Extension */ |
5843 | #define CAN_TI2R_EXID_Pos (3U) |
| 5844 | #define CAN_TI2R_EXID_Pos (3U) |
5844 | #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ |
| 5845 | #define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */ |
5845 | #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */ |
| 5846 | #define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!< Extended identifier */ |
5846 | #define CAN_TI2R_STID_Pos (21U) |
| 5847 | #define CAN_TI2R_STID_Pos (21U) |
5847 | #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ |
| 5848 | #define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */ |
5848 | #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
| 5849 | #define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
5849 | |
| 5850 | 5850 | /******************* Bit definition for CAN_TDT2R register ******************/ |
|
| 5851 | /******************* Bit definition for CAN_TDT2R register ******************/ |
5851 | #define CAN_TDT2R_DLC_Pos (0U) |
| 5852 | #define CAN_TDT2R_DLC_Pos (0U) |
5852 | #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ |
| 5853 | #define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */ |
5853 | #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */ |
| 5854 | #define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!< Data Length Code */ |
5854 | #define CAN_TDT2R_TGT_Pos (8U) |
| 5855 | #define CAN_TDT2R_TGT_Pos (8U) |
5855 | #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ |
| 5856 | #define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */ |
5856 | #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */ |
| 5857 | #define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!< Transmit Global Time */ |
5857 | #define CAN_TDT2R_TIME_Pos (16U) |
| 5858 | #define CAN_TDT2R_TIME_Pos (16U) |
5858 | #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ |
| 5859 | #define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */ |
5859 | #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */ |
| 5860 | #define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!< Message Time Stamp */ |
5860 | |
| 5861 | 5861 | /******************* Bit definition for CAN_TDL2R register ******************/ |
|
| 5862 | /******************* Bit definition for CAN_TDL2R register ******************/ |
5862 | #define CAN_TDL2R_DATA0_Pos (0U) |
| 5863 | #define CAN_TDL2R_DATA0_Pos (0U) |
5863 | #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ |
| 5864 | #define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */ |
5864 | #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */ |
| 5865 | #define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!< Data byte 0 */ |
5865 | #define CAN_TDL2R_DATA1_Pos (8U) |
| 5866 | #define CAN_TDL2R_DATA1_Pos (8U) |
5866 | #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ |
| 5867 | #define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */ |
5867 | #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */ |
| 5868 | #define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!< Data byte 1 */ |
5868 | #define CAN_TDL2R_DATA2_Pos (16U) |
| 5869 | #define CAN_TDL2R_DATA2_Pos (16U) |
5869 | #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ |
| 5870 | #define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */ |
5870 | #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */ |
| 5871 | #define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!< Data byte 2 */ |
5871 | #define CAN_TDL2R_DATA3_Pos (24U) |
| 5872 | #define CAN_TDL2R_DATA3_Pos (24U) |
5872 | #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ |
| 5873 | #define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */ |
5873 | #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */ |
| 5874 | #define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!< Data byte 3 */ |
5874 | |
| 5875 | 5875 | /******************* Bit definition for CAN_TDH2R register ******************/ |
|
| 5876 | /******************* Bit definition for CAN_TDH2R register ******************/ |
5876 | #define CAN_TDH2R_DATA4_Pos (0U) |
| 5877 | #define CAN_TDH2R_DATA4_Pos (0U) |
5877 | #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ |
| 5878 | #define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */ |
5878 | #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */ |
| 5879 | #define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!< Data byte 4 */ |
5879 | #define CAN_TDH2R_DATA5_Pos (8U) |
| 5880 | #define CAN_TDH2R_DATA5_Pos (8U) |
5880 | #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ |
| 5881 | #define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */ |
5881 | #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */ |
| 5882 | #define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!< Data byte 5 */ |
5882 | #define CAN_TDH2R_DATA6_Pos (16U) |
| 5883 | #define CAN_TDH2R_DATA6_Pos (16U) |
5883 | #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ |
| 5884 | #define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */ |
5884 | #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */ |
| 5885 | #define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!< Data byte 6 */ |
5885 | #define CAN_TDH2R_DATA7_Pos (24U) |
| 5886 | #define CAN_TDH2R_DATA7_Pos (24U) |
5886 | #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ |
| 5887 | #define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */ |
5887 | #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */ |
| 5888 | #define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!< Data byte 7 */ |
5888 | |
| 5889 | 5889 | /******************* Bit definition for CAN_RI0R register *******************/ |
|
| 5890 | /******************* Bit definition for CAN_RI0R register *******************/ |
5890 | #define CAN_RI0R_RTR_Pos (1U) |
| 5891 | #define CAN_RI0R_RTR_Pos (1U) |
5891 | #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ |
| 5892 | #define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */ |
5892 | #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */ |
| 5893 | #define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!< Remote Transmission Request */ |
5893 | #define CAN_RI0R_IDE_Pos (2U) |
| 5894 | #define CAN_RI0R_IDE_Pos (2U) |
5894 | #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ |
| 5895 | #define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */ |
5895 | #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */ |
| 5896 | #define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!< Identifier Extension */ |
5896 | #define CAN_RI0R_EXID_Pos (3U) |
| 5897 | #define CAN_RI0R_EXID_Pos (3U) |
5897 | #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
| 5898 | #define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */ |
5898 | #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */ |
| 5899 | #define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!< Extended Identifier */ |
5899 | #define CAN_RI0R_STID_Pos (21U) |
| 5900 | #define CAN_RI0R_STID_Pos (21U) |
5900 | #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ |
| 5901 | #define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */ |
5901 | #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
| 5902 | #define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
5902 | |
| 5903 | 5903 | /******************* Bit definition for CAN_RDT0R register ******************/ |
|
| 5904 | /******************* Bit definition for CAN_RDT0R register ******************/ |
5904 | #define CAN_RDT0R_DLC_Pos (0U) |
| 5905 | #define CAN_RDT0R_DLC_Pos (0U) |
5905 | #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ |
| 5906 | #define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */ |
5906 | #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */ |
| 5907 | #define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!< Data Length Code */ |
5907 | #define CAN_RDT0R_FMI_Pos (8U) |
| 5908 | #define CAN_RDT0R_FMI_Pos (8U) |
5908 | #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ |
| 5909 | #define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */ |
5909 | #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */ |
| 5910 | #define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!< Filter Match Index */ |
5910 | #define CAN_RDT0R_TIME_Pos (16U) |
| 5911 | #define CAN_RDT0R_TIME_Pos (16U) |
5911 | #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
| 5912 | #define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */ |
5912 | #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */ |
| 5913 | #define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!< Message Time Stamp */ |
5913 | |
| 5914 | 5914 | /******************* Bit definition for CAN_RDL0R register ******************/ |
|
| 5915 | /******************* Bit definition for CAN_RDL0R register ******************/ |
5915 | #define CAN_RDL0R_DATA0_Pos (0U) |
| 5916 | #define CAN_RDL0R_DATA0_Pos (0U) |
5916 | #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ |
| 5917 | #define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */ |
5917 | #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */ |
| 5918 | #define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!< Data byte 0 */ |
5918 | #define CAN_RDL0R_DATA1_Pos (8U) |
| 5919 | #define CAN_RDL0R_DATA1_Pos (8U) |
5919 | #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
| 5920 | #define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */ |
5920 | #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */ |
| 5921 | #define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!< Data byte 1 */ |
5921 | #define CAN_RDL0R_DATA2_Pos (16U) |
| 5922 | #define CAN_RDL0R_DATA2_Pos (16U) |
5922 | #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
| 5923 | #define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */ |
5923 | #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */ |
| 5924 | #define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!< Data byte 2 */ |
5924 | #define CAN_RDL0R_DATA3_Pos (24U) |
| 5925 | #define CAN_RDL0R_DATA3_Pos (24U) |
5925 | #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
| 5926 | #define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */ |
5926 | #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */ |
| 5927 | #define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!< Data byte 3 */ |
5927 | |
| 5928 | 5928 | /******************* Bit definition for CAN_RDH0R register ******************/ |
|
| 5929 | /******************* Bit definition for CAN_RDH0R register ******************/ |
5929 | #define CAN_RDH0R_DATA4_Pos (0U) |
| 5930 | #define CAN_RDH0R_DATA4_Pos (0U) |
5930 | #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ |
| 5931 | #define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */ |
5931 | #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */ |
| 5932 | #define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!< Data byte 4 */ |
5932 | #define CAN_RDH0R_DATA5_Pos (8U) |
| 5933 | #define CAN_RDH0R_DATA5_Pos (8U) |
5933 | #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
| 5934 | #define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */ |
5934 | #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */ |
| 5935 | #define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!< Data byte 5 */ |
5935 | #define CAN_RDH0R_DATA6_Pos (16U) |
| 5936 | #define CAN_RDH0R_DATA6_Pos (16U) |
5936 | #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
| 5937 | #define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */ |
5937 | #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */ |
| 5938 | #define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!< Data byte 6 */ |
5938 | #define CAN_RDH0R_DATA7_Pos (24U) |
| 5939 | #define CAN_RDH0R_DATA7_Pos (24U) |
5939 | #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
| 5940 | #define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */ |
5940 | #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */ |
| 5941 | #define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!< Data byte 7 */ |
5941 | |
| 5942 | 5942 | /******************* Bit definition for CAN_RI1R register *******************/ |
|
| 5943 | /******************* Bit definition for CAN_RI1R register *******************/ |
5943 | #define CAN_RI1R_RTR_Pos (1U) |
| 5944 | #define CAN_RI1R_RTR_Pos (1U) |
5944 | #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ |
| 5945 | #define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */ |
5945 | #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */ |
| 5946 | #define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!< Remote Transmission Request */ |
5946 | #define CAN_RI1R_IDE_Pos (2U) |
| 5947 | #define CAN_RI1R_IDE_Pos (2U) |
5947 | #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ |
| 5948 | #define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */ |
5948 | #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */ |
| 5949 | #define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!< Identifier Extension */ |
5949 | #define CAN_RI1R_EXID_Pos (3U) |
| 5950 | #define CAN_RI1R_EXID_Pos (3U) |
5950 | #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
| 5951 | #define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */ |
5951 | #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */ |
| 5952 | #define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!< Extended identifier */ |
5952 | #define CAN_RI1R_STID_Pos (21U) |
| 5953 | #define CAN_RI1R_STID_Pos (21U) |
5953 | #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ |
| 5954 | #define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */ |
5954 | #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
| 5955 | #define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!< Standard Identifier or Extended Identifier */ |
5955 | |
| 5956 | 5956 | /******************* Bit definition for CAN_RDT1R register ******************/ |
|
| 5957 | /******************* Bit definition for CAN_RDT1R register ******************/ |
5957 | #define CAN_RDT1R_DLC_Pos (0U) |
| 5958 | #define CAN_RDT1R_DLC_Pos (0U) |
5958 | #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ |
| 5959 | #define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */ |
5959 | #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */ |
| 5960 | #define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!< Data Length Code */ |
5960 | #define CAN_RDT1R_FMI_Pos (8U) |
| 5961 | #define CAN_RDT1R_FMI_Pos (8U) |
5961 | #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ |
| 5962 | #define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */ |
5962 | #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */ |
| 5963 | #define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!< Filter Match Index */ |
5963 | #define CAN_RDT1R_TIME_Pos (16U) |
| 5964 | #define CAN_RDT1R_TIME_Pos (16U) |
5964 | #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
| 5965 | #define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */ |
5965 | #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */ |
| 5966 | #define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!< Message Time Stamp */ |
5966 | |
| 5967 | 5967 | /******************* Bit definition for CAN_RDL1R register ******************/ |
|
| 5968 | /******************* Bit definition for CAN_RDL1R register ******************/ |
5968 | #define CAN_RDL1R_DATA0_Pos (0U) |
| 5969 | #define CAN_RDL1R_DATA0_Pos (0U) |
5969 | #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ |
| 5970 | #define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */ |
5970 | #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */ |
| 5971 | #define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!< Data byte 0 */ |
5971 | #define CAN_RDL1R_DATA1_Pos (8U) |
| 5972 | #define CAN_RDL1R_DATA1_Pos (8U) |
5972 | #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
| 5973 | #define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */ |
5973 | #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */ |
| 5974 | #define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!< Data byte 1 */ |
5974 | #define CAN_RDL1R_DATA2_Pos (16U) |
| 5975 | #define CAN_RDL1R_DATA2_Pos (16U) |
5975 | #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
| 5976 | #define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */ |
5976 | #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */ |
| 5977 | #define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!< Data byte 2 */ |
5977 | #define CAN_RDL1R_DATA3_Pos (24U) |
| 5978 | #define CAN_RDL1R_DATA3_Pos (24U) |
5978 | #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
| 5979 | #define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */ |
5979 | #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */ |
| 5980 | #define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!< Data byte 3 */ |
5980 | |
| 5981 | 5981 | /******************* Bit definition for CAN_RDH1R register ******************/ |
|
| 5982 | /******************* Bit definition for CAN_RDH1R register ******************/ |
5982 | #define CAN_RDH1R_DATA4_Pos (0U) |
| 5983 | #define CAN_RDH1R_DATA4_Pos (0U) |
5983 | #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ |
| 5984 | #define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */ |
5984 | #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */ |
| 5985 | #define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!< Data byte 4 */ |
5985 | #define CAN_RDH1R_DATA5_Pos (8U) |
| 5986 | #define CAN_RDH1R_DATA5_Pos (8U) |
5986 | #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
| 5987 | #define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */ |
5987 | #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */ |
| 5988 | #define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!< Data byte 5 */ |
5988 | #define CAN_RDH1R_DATA6_Pos (16U) |
| 5989 | #define CAN_RDH1R_DATA6_Pos (16U) |
5989 | #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
| 5990 | #define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */ |
5990 | #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */ |
| 5991 | #define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!< Data byte 6 */ |
5991 | #define CAN_RDH1R_DATA7_Pos (24U) |
| 5992 | #define CAN_RDH1R_DATA7_Pos (24U) |
5992 | #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
| 5993 | #define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */ |
5993 | #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */ |
| 5994 | #define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!< Data byte 7 */ |
5994 | |
| 5995 | 5995 | /*!< CAN filter registers */ |
|
| 5996 | /*!< CAN filter registers */ |
5996 | /******************* Bit definition for CAN_FMR register ********************/ |
| 5997 | /******************* Bit definition for CAN_FMR register ********************/ |
5997 | #define CAN_FMR_FINIT_Pos (0U) |
| 5998 | #define CAN_FMR_FINIT_Pos (0U) |
5998 | #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ |
| 5999 | #define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */ |
5999 | #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */ |
| 6000 | #define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!< Filter Init Mode */ |
6000 | #define CAN_FMR_CAN2SB_Pos (8U) |
| 6001 | #define CAN_FMR_CAN2SB_Pos (8U) |
6001 | #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */ |
| 6002 | #define CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos) /*!< 0x00003F00 */ |
6002 | #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */ |
| 6003 | #define CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk /*!< CAN2 start bank */ |
6003 | |
| 6004 | 6004 | /******************* Bit definition for CAN_FM1R register *******************/ |
|
| 6005 | /******************* Bit definition for CAN_FM1R register *******************/ |
6005 | #define CAN_FM1R_FBM_Pos (0U) |
| 6006 | #define CAN_FM1R_FBM_Pos (0U) |
6006 | #define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */ |
| 6007 | #define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */ |
6007 | #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */ |
| 6008 | #define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!< Filter Mode */ |
6008 | #define CAN_FM1R_FBM0_Pos (0U) |
| 6009 | #define CAN_FM1R_FBM0_Pos (0U) |
6009 | #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ |
| 6010 | #define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */ |
6010 | #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */ |
| 6011 | #define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!< Filter Init Mode for filter 0 */ |
6011 | #define CAN_FM1R_FBM1_Pos (1U) |
| 6012 | #define CAN_FM1R_FBM1_Pos (1U) |
6012 | #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ |
| 6013 | #define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */ |
6013 | #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */ |
| 6014 | #define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!< Filter Init Mode for filter 1 */ |
6014 | #define CAN_FM1R_FBM2_Pos (2U) |
| 6015 | #define CAN_FM1R_FBM2_Pos (2U) |
6015 | #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ |
| 6016 | #define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */ |
6016 | #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */ |
| 6017 | #define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!< Filter Init Mode for filter 2 */ |
6017 | #define CAN_FM1R_FBM3_Pos (3U) |
| 6018 | #define CAN_FM1R_FBM3_Pos (3U) |
6018 | #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ |
| 6019 | #define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */ |
6019 | #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */ |
| 6020 | #define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!< Filter Init Mode for filter 3 */ |
6020 | #define CAN_FM1R_FBM4_Pos (4U) |
| 6021 | #define CAN_FM1R_FBM4_Pos (4U) |
6021 | #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ |
| 6022 | #define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */ |
6022 | #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */ |
| 6023 | #define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!< Filter Init Mode for filter 4 */ |
6023 | #define CAN_FM1R_FBM5_Pos (5U) |
| 6024 | #define CAN_FM1R_FBM5_Pos (5U) |
6024 | #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ |
| 6025 | #define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */ |
6025 | #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */ |
| 6026 | #define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!< Filter Init Mode for filter 5 */ |
6026 | #define CAN_FM1R_FBM6_Pos (6U) |
| 6027 | #define CAN_FM1R_FBM6_Pos (6U) |
6027 | #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ |
| 6028 | #define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */ |
6028 | #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */ |
| 6029 | #define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!< Filter Init Mode for filter 6 */ |
6029 | #define CAN_FM1R_FBM7_Pos (7U) |
| 6030 | #define CAN_FM1R_FBM7_Pos (7U) |
6030 | #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ |
| 6031 | #define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */ |
6031 | #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */ |
| 6032 | #define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!< Filter Init Mode for filter 7 */ |
6032 | #define CAN_FM1R_FBM8_Pos (8U) |
| 6033 | #define CAN_FM1R_FBM8_Pos (8U) |
6033 | #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ |
| 6034 | #define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */ |
6034 | #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */ |
| 6035 | #define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!< Filter Init Mode for filter 8 */ |
6035 | #define CAN_FM1R_FBM9_Pos (9U) |
| 6036 | #define CAN_FM1R_FBM9_Pos (9U) |
6036 | #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ |
| 6037 | #define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */ |
6037 | #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */ |
| 6038 | #define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!< Filter Init Mode for filter 9 */ |
6038 | #define CAN_FM1R_FBM10_Pos (10U) |
| 6039 | #define CAN_FM1R_FBM10_Pos (10U) |
6039 | #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ |
| 6040 | #define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */ |
6040 | #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */ |
| 6041 | #define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!< Filter Init Mode for filter 10 */ |
6041 | #define CAN_FM1R_FBM11_Pos (11U) |
| 6042 | #define CAN_FM1R_FBM11_Pos (11U) |
6042 | #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ |
| 6043 | #define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */ |
6043 | #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */ |
| 6044 | #define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!< Filter Init Mode for filter 11 */ |
6044 | #define CAN_FM1R_FBM12_Pos (12U) |
| 6045 | #define CAN_FM1R_FBM12_Pos (12U) |
6045 | #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ |
| 6046 | #define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */ |
6046 | #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */ |
| 6047 | #define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!< Filter Init Mode for filter 12 */ |
6047 | #define CAN_FM1R_FBM13_Pos (13U) |
| 6048 | #define CAN_FM1R_FBM13_Pos (13U) |
6048 | #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ |
| 6049 | #define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */ |
6049 | #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */ |
| 6050 | #define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!< Filter Init Mode for filter 13 */ |
6050 | #define CAN_FM1R_FBM14_Pos (14U) |
| 6051 | #define CAN_FM1R_FBM14_Pos (14U) |
6051 | #define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */ |
| 6052 | #define CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos) /*!< 0x00004000 */ |
6052 | #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!< Filter Init Mode for filter 14 */ |
| 6053 | #define CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk /*!< Filter Init Mode for filter 14 */ |
6053 | #define CAN_FM1R_FBM15_Pos (15U) |
| 6054 | #define CAN_FM1R_FBM15_Pos (15U) |
6054 | #define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */ |
| 6055 | #define CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos) /*!< 0x00008000 */ |
6055 | #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!< Filter Init Mode for filter 15 */ |
| 6056 | #define CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk /*!< Filter Init Mode for filter 15 */ |
6056 | #define CAN_FM1R_FBM16_Pos (16U) |
| 6057 | #define CAN_FM1R_FBM16_Pos (16U) |
6057 | #define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */ |
| 6058 | #define CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos) /*!< 0x00010000 */ |
6058 | #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!< Filter Init Mode for filter 16 */ |
| 6059 | #define CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk /*!< Filter Init Mode for filter 16 */ |
6059 | #define CAN_FM1R_FBM17_Pos (17U) |
| 6060 | #define CAN_FM1R_FBM17_Pos (17U) |
6060 | #define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */ |
| 6061 | #define CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos) /*!< 0x00020000 */ |
6061 | #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!< Filter Init Mode for filter 17 */ |
| 6062 | #define CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk /*!< Filter Init Mode for filter 17 */ |
6062 | #define CAN_FM1R_FBM18_Pos (18U) |
| 6063 | #define CAN_FM1R_FBM18_Pos (18U) |
6063 | #define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */ |
| 6064 | #define CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos) /*!< 0x00040000 */ |
6064 | #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!< Filter Init Mode for filter 18 */ |
| 6065 | #define CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk /*!< Filter Init Mode for filter 18 */ |
6065 | #define CAN_FM1R_FBM19_Pos (19U) |
| 6066 | #define CAN_FM1R_FBM19_Pos (19U) |
6066 | #define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */ |
| 6067 | #define CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos) /*!< 0x00080000 */ |
6067 | #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!< Filter Init Mode for filter 19 */ |
| 6068 | #define CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk /*!< Filter Init Mode for filter 19 */ |
6068 | #define CAN_FM1R_FBM20_Pos (20U) |
| 6069 | #define CAN_FM1R_FBM20_Pos (20U) |
6069 | #define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */ |
| 6070 | #define CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos) /*!< 0x00100000 */ |
6070 | #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!< Filter Init Mode for filter 20 */ |
| 6071 | #define CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk /*!< Filter Init Mode for filter 20 */ |
6071 | #define CAN_FM1R_FBM21_Pos (21U) |
| 6072 | #define CAN_FM1R_FBM21_Pos (21U) |
6072 | #define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */ |
| 6073 | #define CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos) /*!< 0x00200000 */ |
6073 | #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!< Filter Init Mode for filter 21 */ |
| 6074 | #define CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk /*!< Filter Init Mode for filter 21 */ |
6074 | #define CAN_FM1R_FBM22_Pos (22U) |
| 6075 | #define CAN_FM1R_FBM22_Pos (22U) |
6075 | #define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */ |
| 6076 | #define CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos) /*!< 0x00400000 */ |
6076 | #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!< Filter Init Mode for filter 22 */ |
| 6077 | #define CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk /*!< Filter Init Mode for filter 22 */ |
6077 | #define CAN_FM1R_FBM23_Pos (23U) |
| 6078 | #define CAN_FM1R_FBM23_Pos (23U) |
6078 | #define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */ |
| 6079 | #define CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos) /*!< 0x00800000 */ |
6079 | #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!< Filter Init Mode for filter 23 */ |
| 6080 | #define CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk /*!< Filter Init Mode for filter 23 */ |
6080 | #define CAN_FM1R_FBM24_Pos (24U) |
| 6081 | #define CAN_FM1R_FBM24_Pos (24U) |
6081 | #define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */ |
| 6082 | #define CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos) /*!< 0x01000000 */ |
6082 | #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!< Filter Init Mode for filter 24 */ |
| 6083 | #define CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk /*!< Filter Init Mode for filter 24 */ |
6083 | #define CAN_FM1R_FBM25_Pos (25U) |
| 6084 | #define CAN_FM1R_FBM25_Pos (25U) |
6084 | #define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */ |
| 6085 | #define CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos) /*!< 0x02000000 */ |
6085 | #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!< Filter Init Mode for filter 25 */ |
| 6086 | #define CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk /*!< Filter Init Mode for filter 25 */ |
6086 | #define CAN_FM1R_FBM26_Pos (26U) |
| 6087 | #define CAN_FM1R_FBM26_Pos (26U) |
6087 | #define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */ |
| 6088 | #define CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos) /*!< 0x04000000 */ |
6088 | #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!< Filter Init Mode for filter 26 */ |
| 6089 | #define CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk /*!< Filter Init Mode for filter 26 */ |
6089 | #define CAN_FM1R_FBM27_Pos (27U) |
| 6090 | #define CAN_FM1R_FBM27_Pos (27U) |
6090 | #define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */ |
| 6091 | #define CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos) /*!< 0x08000000 */ |
6091 | #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!< Filter Init Mode for filter 27 */ |
| 6092 | #define CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk /*!< Filter Init Mode for filter 27 */ |
6092 | |
| 6093 | 6093 | /******************* Bit definition for CAN_FS1R register *******************/ |
|
| 6094 | /******************* Bit definition for CAN_FS1R register *******************/ |
6094 | #define CAN_FS1R_FSC_Pos (0U) |
| 6095 | #define CAN_FS1R_FSC_Pos (0U) |
6095 | #define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */ |
| 6096 | #define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */ |
6096 | #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */ |
| 6097 | #define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!< Filter Scale Configuration */ |
6097 | #define CAN_FS1R_FSC0_Pos (0U) |
| 6098 | #define CAN_FS1R_FSC0_Pos (0U) |
6098 | #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ |
| 6099 | #define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */ |
6099 | #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */ |
| 6100 | #define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!< Filter Scale Configuration for filter 0 */ |
6100 | #define CAN_FS1R_FSC1_Pos (1U) |
| 6101 | #define CAN_FS1R_FSC1_Pos (1U) |
6101 | #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ |
| 6102 | #define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */ |
6102 | #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */ |
| 6103 | #define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!< Filter Scale Configuration for filter 1 */ |
6103 | #define CAN_FS1R_FSC2_Pos (2U) |
| 6104 | #define CAN_FS1R_FSC2_Pos (2U) |
6104 | #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ |
| 6105 | #define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */ |
6105 | #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */ |
| 6106 | #define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!< Filter Scale Configuration for filter 2 */ |
6106 | #define CAN_FS1R_FSC3_Pos (3U) |
| 6107 | #define CAN_FS1R_FSC3_Pos (3U) |
6107 | #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ |
| 6108 | #define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */ |
6108 | #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */ |
| 6109 | #define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!< Filter Scale Configuration for filter 3 */ |
6109 | #define CAN_FS1R_FSC4_Pos (4U) |
| 6110 | #define CAN_FS1R_FSC4_Pos (4U) |
6110 | #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ |
| 6111 | #define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */ |
6111 | #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */ |
| 6112 | #define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!< Filter Scale Configuration for filter 4 */ |
6112 | #define CAN_FS1R_FSC5_Pos (5U) |
| 6113 | #define CAN_FS1R_FSC5_Pos (5U) |
6113 | #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ |
| 6114 | #define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */ |
6114 | #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */ |
| 6115 | #define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!< Filter Scale Configuration for filter 5 */ |
6115 | #define CAN_FS1R_FSC6_Pos (6U) |
| 6116 | #define CAN_FS1R_FSC6_Pos (6U) |
6116 | #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ |
| 6117 | #define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */ |
6117 | #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */ |
| 6118 | #define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!< Filter Scale Configuration for filter 6 */ |
6118 | #define CAN_FS1R_FSC7_Pos (7U) |
| 6119 | #define CAN_FS1R_FSC7_Pos (7U) |
6119 | #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ |
| 6120 | #define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */ |
6120 | #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */ |
| 6121 | #define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!< Filter Scale Configuration for filter 7 */ |
6121 | #define CAN_FS1R_FSC8_Pos (8U) |
| 6122 | #define CAN_FS1R_FSC8_Pos (8U) |
6122 | #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ |
| 6123 | #define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */ |
6123 | #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */ |
| 6124 | #define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!< Filter Scale Configuration for filter 8 */ |
6124 | #define CAN_FS1R_FSC9_Pos (9U) |
| 6125 | #define CAN_FS1R_FSC9_Pos (9U) |
6125 | #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ |
| 6126 | #define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */ |
6126 | #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */ |
| 6127 | #define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!< Filter Scale Configuration for filter 9 */ |
6127 | #define CAN_FS1R_FSC10_Pos (10U) |
| 6128 | #define CAN_FS1R_FSC10_Pos (10U) |
6128 | #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ |
| 6129 | #define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */ |
6129 | #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */ |
| 6130 | #define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!< Filter Scale Configuration for filter 10 */ |
6130 | #define CAN_FS1R_FSC11_Pos (11U) |
| 6131 | #define CAN_FS1R_FSC11_Pos (11U) |
6131 | #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ |
| 6132 | #define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */ |
6132 | #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */ |
| 6133 | #define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!< Filter Scale Configuration for filter 11 */ |
6133 | #define CAN_FS1R_FSC12_Pos (12U) |
| 6134 | #define CAN_FS1R_FSC12_Pos (12U) |
6134 | #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ |
| 6135 | #define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */ |
6135 | #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */ |
| 6136 | #define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!< Filter Scale Configuration for filter 12 */ |
6136 | #define CAN_FS1R_FSC13_Pos (13U) |
| 6137 | #define CAN_FS1R_FSC13_Pos (13U) |
6137 | #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ |
| 6138 | #define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */ |
6138 | #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */ |
| 6139 | #define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!< Filter Scale Configuration for filter 13 */ |
6139 | #define CAN_FS1R_FSC14_Pos (14U) |
| 6140 | #define CAN_FS1R_FSC14_Pos (14U) |
6140 | #define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */ |
| 6141 | #define CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos) /*!< 0x00004000 */ |
6141 | #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!< Filter Scale Configuration for filter 14 */ |
| 6142 | #define CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk /*!< Filter Scale Configuration for filter 14 */ |
6142 | #define CAN_FS1R_FSC15_Pos (15U) |
| 6143 | #define CAN_FS1R_FSC15_Pos (15U) |
6143 | #define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */ |
| 6144 | #define CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos) /*!< 0x00008000 */ |
6144 | #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!< Filter Scale Configuration for filter 15 */ |
| 6145 | #define CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk /*!< Filter Scale Configuration for filter 15 */ |
6145 | #define CAN_FS1R_FSC16_Pos (16U) |
| 6146 | #define CAN_FS1R_FSC16_Pos (16U) |
6146 | #define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */ |
| 6147 | #define CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos) /*!< 0x00010000 */ |
6147 | #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!< Filter Scale Configuration for filter 16 */ |
| 6148 | #define CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk /*!< Filter Scale Configuration for filter 16 */ |
6148 | #define CAN_FS1R_FSC17_Pos (17U) |
| 6149 | #define CAN_FS1R_FSC17_Pos (17U) |
6149 | #define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */ |
| 6150 | #define CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos) /*!< 0x00020000 */ |
6150 | #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!< Filter Scale Configuration for filter 17 */ |
| 6151 | #define CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk /*!< Filter Scale Configuration for filter 17 */ |
6151 | #define CAN_FS1R_FSC18_Pos (18U) |
| 6152 | #define CAN_FS1R_FSC18_Pos (18U) |
6152 | #define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */ |
| 6153 | #define CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos) /*!< 0x00040000 */ |
6153 | #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!< Filter Scale Configuration for filter 18 */ |
| 6154 | #define CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk /*!< Filter Scale Configuration for filter 18 */ |
6154 | #define CAN_FS1R_FSC19_Pos (19U) |
| 6155 | #define CAN_FS1R_FSC19_Pos (19U) |
6155 | #define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */ |
| 6156 | #define CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos) /*!< 0x00080000 */ |
6156 | #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!< Filter Scale Configuration for filter 19 */ |
| 6157 | #define CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk /*!< Filter Scale Configuration for filter 19 */ |
6157 | #define CAN_FS1R_FSC20_Pos (20U) |
| 6158 | #define CAN_FS1R_FSC20_Pos (20U) |
6158 | #define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */ |
| 6159 | #define CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos) /*!< 0x00100000 */ |
6159 | #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!< Filter Scale Configuration for filter 20 */ |
| 6160 | #define CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk /*!< Filter Scale Configuration for filter 20 */ |
6160 | #define CAN_FS1R_FSC21_Pos (21U) |
| 6161 | #define CAN_FS1R_FSC21_Pos (21U) |
6161 | #define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */ |
| 6162 | #define CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos) /*!< 0x00200000 */ |
6162 | #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!< Filter Scale Configuration for filter 21 */ |
| 6163 | #define CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk /*!< Filter Scale Configuration for filter 21 */ |
6163 | #define CAN_FS1R_FSC22_Pos (22U) |
| 6164 | #define CAN_FS1R_FSC22_Pos (22U) |
6164 | #define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */ |
| 6165 | #define CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos) /*!< 0x00400000 */ |
6165 | #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!< Filter Scale Configuration for filter 22 */ |
| 6166 | #define CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk /*!< Filter Scale Configuration for filter 22 */ |
6166 | #define CAN_FS1R_FSC23_Pos (23U) |
| 6167 | #define CAN_FS1R_FSC23_Pos (23U) |
6167 | #define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */ |
| 6168 | #define CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos) /*!< 0x00800000 */ |
6168 | #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!< Filter Scale Configuration for filter 23 */ |
| 6169 | #define CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk /*!< Filter Scale Configuration for filter 23 */ |
6169 | #define CAN_FS1R_FSC24_Pos (24U) |
| 6170 | #define CAN_FS1R_FSC24_Pos (24U) |
6170 | #define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */ |
| 6171 | #define CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos) /*!< 0x01000000 */ |
6171 | #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!< Filter Scale Configuration for filter 24 */ |
| 6172 | #define CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk /*!< Filter Scale Configuration for filter 24 */ |
6172 | #define CAN_FS1R_FSC25_Pos (25U) |
| 6173 | #define CAN_FS1R_FSC25_Pos (25U) |
6173 | #define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */ |
| 6174 | #define CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos) /*!< 0x02000000 */ |
6174 | #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!< Filter Scale Configuration for filter 25 */ |
| 6175 | #define CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk /*!< Filter Scale Configuration for filter 25 */ |
6175 | #define CAN_FS1R_FSC26_Pos (26U) |
| 6176 | #define CAN_FS1R_FSC26_Pos (26U) |
6176 | #define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */ |
| 6177 | #define CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos) /*!< 0x04000000 */ |
6177 | #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!< Filter Scale Configuration for filter 26 */ |
| 6178 | #define CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk /*!< Filter Scale Configuration for filter 26 */ |
6178 | #define CAN_FS1R_FSC27_Pos (27U) |
| 6179 | #define CAN_FS1R_FSC27_Pos (27U) |
6179 | #define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */ |
| 6180 | #define CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos) /*!< 0x08000000 */ |
6180 | #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!< Filter Scale Configuration for filter 27 */ |
| 6181 | #define CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk /*!< Filter Scale Configuration for filter 27 */ |
6181 | |
| 6182 | 6182 | /****************** Bit definition for CAN_FFA1R register *******************/ |
|
| 6183 | /****************** Bit definition for CAN_FFA1R register *******************/ |
6183 | #define CAN_FFA1R_FFA_Pos (0U) |
| 6184 | #define CAN_FFA1R_FFA_Pos (0U) |
6184 | #define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */ |
| 6185 | #define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */ |
6185 | #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */ |
| 6186 | #define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!< Filter FIFO Assignment */ |
6186 | #define CAN_FFA1R_FFA0_Pos (0U) |
| 6187 | #define CAN_FFA1R_FFA0_Pos (0U) |
6187 | #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ |
| 6188 | #define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */ |
6188 | #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */ |
| 6189 | #define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!< Filter FIFO Assignment for filter 0 */ |
6189 | #define CAN_FFA1R_FFA1_Pos (1U) |
| 6190 | #define CAN_FFA1R_FFA1_Pos (1U) |
6190 | #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ |
| 6191 | #define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */ |
6191 | #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */ |
| 6192 | #define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!< Filter FIFO Assignment for filter 1 */ |
6192 | #define CAN_FFA1R_FFA2_Pos (2U) |
| 6193 | #define CAN_FFA1R_FFA2_Pos (2U) |
6193 | #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ |
| 6194 | #define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */ |
6194 | #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */ |
| 6195 | #define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!< Filter FIFO Assignment for filter 2 */ |
6195 | #define CAN_FFA1R_FFA3_Pos (3U) |
| 6196 | #define CAN_FFA1R_FFA3_Pos (3U) |
6196 | #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ |
| 6197 | #define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */ |
6197 | #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */ |
| 6198 | #define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!< Filter FIFO Assignment for filter 3 */ |
6198 | #define CAN_FFA1R_FFA4_Pos (4U) |
| 6199 | #define CAN_FFA1R_FFA4_Pos (4U) |
6199 | #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ |
| 6200 | #define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */ |
6200 | #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */ |
| 6201 | #define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!< Filter FIFO Assignment for filter 4 */ |
6201 | #define CAN_FFA1R_FFA5_Pos (5U) |
| 6202 | #define CAN_FFA1R_FFA5_Pos (5U) |
6202 | #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ |
| 6203 | #define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */ |
6203 | #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */ |
| 6204 | #define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!< Filter FIFO Assignment for filter 5 */ |
6204 | #define CAN_FFA1R_FFA6_Pos (6U) |
| 6205 | #define CAN_FFA1R_FFA6_Pos (6U) |
6205 | #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ |
| 6206 | #define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */ |
6206 | #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */ |
| 6207 | #define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!< Filter FIFO Assignment for filter 6 */ |
6207 | #define CAN_FFA1R_FFA7_Pos (7U) |
| 6208 | #define CAN_FFA1R_FFA7_Pos (7U) |
6208 | #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ |
| 6209 | #define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */ |
6209 | #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */ |
| 6210 | #define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!< Filter FIFO Assignment for filter 7 */ |
6210 | #define CAN_FFA1R_FFA8_Pos (8U) |
| 6211 | #define CAN_FFA1R_FFA8_Pos (8U) |
6211 | #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ |
| 6212 | #define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */ |
6212 | #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */ |
| 6213 | #define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!< Filter FIFO Assignment for filter 8 */ |
6213 | #define CAN_FFA1R_FFA9_Pos (9U) |
| 6214 | #define CAN_FFA1R_FFA9_Pos (9U) |
6214 | #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ |
| 6215 | #define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */ |
6215 | #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */ |
| 6216 | #define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!< Filter FIFO Assignment for filter 9 */ |
6216 | #define CAN_FFA1R_FFA10_Pos (10U) |
| 6217 | #define CAN_FFA1R_FFA10_Pos (10U) |
6217 | #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ |
| 6218 | #define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */ |
6218 | #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */ |
| 6219 | #define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!< Filter FIFO Assignment for filter 10 */ |
6219 | #define CAN_FFA1R_FFA11_Pos (11U) |
| 6220 | #define CAN_FFA1R_FFA11_Pos (11U) |
6220 | #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ |
| 6221 | #define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */ |
6221 | #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */ |
| 6222 | #define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!< Filter FIFO Assignment for filter 11 */ |
6222 | #define CAN_FFA1R_FFA12_Pos (12U) |
| 6223 | #define CAN_FFA1R_FFA12_Pos (12U) |
6223 | #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ |
| 6224 | #define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */ |
6224 | #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */ |
| 6225 | #define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!< Filter FIFO Assignment for filter 12 */ |
6225 | #define CAN_FFA1R_FFA13_Pos (13U) |
| 6226 | #define CAN_FFA1R_FFA13_Pos (13U) |
6226 | #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ |
| 6227 | #define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */ |
6227 | #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */ |
| 6228 | #define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!< Filter FIFO Assignment for filter 13 */ |
6228 | #define CAN_FFA1_FFA14_Pos (14U) |
| 6229 | #define CAN_FFA1_FFA14_Pos (14U) |
6229 | #define CAN_FFA1_FFA14_Msk (0x1UL << CAN_FFA1_FFA14_Pos) /*!< 0x00004000 */ |
| 6230 | #define CAN_FFA1_FFA14_Msk (0x1UL << CAN_FFA1_FFA14_Pos) /*!< 0x00004000 */ |
6230 | #define CAN_FFA1_FFA14 CAN_FFA1_FFA14_Msk /*!< Filter FIFO Assignment for filter 14 */ |
| 6231 | #define CAN_FFA1_FFA14 CAN_FFA1_FFA14_Msk /*!< Filter FIFO Assignment for filter 14 */ |
6231 | #define CAN_FFA1_FFA15_Pos (15U) |
| 6232 | #define CAN_FFA1_FFA15_Pos (15U) |
6232 | #define CAN_FFA1_FFA15_Msk (0x1UL << CAN_FFA1_FFA15_Pos) /*!< 0x00008000 */ |
| 6233 | #define CAN_FFA1_FFA15_Msk (0x1UL << CAN_FFA1_FFA15_Pos) /*!< 0x00008000 */ |
6233 | #define CAN_FFA1_FFA15 CAN_FFA1_FFA15_Msk /*!< Filter FIFO Assignment for filter 15 */ |
| 6234 | #define CAN_FFA1_FFA15 CAN_FFA1_FFA15_Msk /*!< Filter FIFO Assignment for filter 15 */ |
6234 | #define CAN_FFA1_FFA16_Pos (16U) |
| 6235 | #define CAN_FFA1_FFA16_Pos (16U) |
6235 | #define CAN_FFA1_FFA16_Msk (0x1UL << CAN_FFA1_FFA16_Pos) /*!< 0x00010000 */ |
| 6236 | #define CAN_FFA1_FFA16_Msk (0x1UL << CAN_FFA1_FFA16_Pos) /*!< 0x00010000 */ |
6236 | #define CAN_FFA1_FFA16 CAN_FFA1_FFA16_Msk /*!< Filter FIFO Assignment for filter 16 */ |
| 6237 | #define CAN_FFA1_FFA16 CAN_FFA1_FFA16_Msk /*!< Filter FIFO Assignment for filter 16 */ |
6237 | #define CAN_FFA1_FFA17_Pos (17U) |
| 6238 | #define CAN_FFA1_FFA17_Pos (17U) |
6238 | #define CAN_FFA1_FFA17_Msk (0x1UL << CAN_FFA1_FFA17_Pos) /*!< 0x00020000 */ |
| 6239 | #define CAN_FFA1_FFA17_Msk (0x1UL << CAN_FFA1_FFA17_Pos) /*!< 0x00020000 */ |
6239 | #define CAN_FFA1_FFA17 CAN_FFA1_FFA17_Msk /*!< Filter FIFO Assignment for filter 17 */ |
| 6240 | #define CAN_FFA1_FFA17 CAN_FFA1_FFA17_Msk /*!< Filter FIFO Assignment for filter 17 */ |
6240 | #define CAN_FFA1_FFA18_Pos (18U) |
| 6241 | #define CAN_FFA1_FFA18_Pos (18U) |
6241 | #define CAN_FFA1_FFA18_Msk (0x1UL << CAN_FFA1_FFA18_Pos) /*!< 0x00040000 */ |
| 6242 | #define CAN_FFA1_FFA18_Msk (0x1UL << CAN_FFA1_FFA18_Pos) /*!< 0x00040000 */ |
6242 | #define CAN_FFA1_FFA18 CAN_FFA1_FFA18_Msk /*!< Filter FIFO Assignment for filter 18 */ |
| 6243 | #define CAN_FFA1_FFA18 CAN_FFA1_FFA18_Msk /*!< Filter FIFO Assignment for filter 18 */ |
6243 | #define CAN_FFA1_FFA19_Pos (19U) |
| 6244 | #define CAN_FFA1_FFA19_Pos (19U) |
6244 | #define CAN_FFA1_FFA19_Msk (0x1UL << CAN_FFA1_FFA19_Pos) /*!< 0x00080000 */ |
| 6245 | #define CAN_FFA1_FFA19_Msk (0x1UL << CAN_FFA1_FFA19_Pos) /*!< 0x00080000 */ |
6245 | #define CAN_FFA1_FFA19 CAN_FFA1_FFA19_Msk /*!< Filter FIFO Assignment for filter 19 */ |
| 6246 | #define CAN_FFA1_FFA19 CAN_FFA1_FFA19_Msk /*!< Filter FIFO Assignment for filter 19 */ |
6246 | #define CAN_FFA1_FFA20_Pos (20U) |
| 6247 | #define CAN_FFA1_FFA20_Pos (20U) |
6247 | #define CAN_FFA1_FFA20_Msk (0x1UL << CAN_FFA1_FFA20_Pos) /*!< 0x00100000 */ |
| 6248 | #define CAN_FFA1_FFA20_Msk (0x1UL << CAN_FFA1_FFA20_Pos) /*!< 0x00100000 */ |
6248 | #define CAN_FFA1_FFA20 CAN_FFA1_FFA20_Msk /*!< Filter FIFO Assignment for filter 20 */ |
| 6249 | #define CAN_FFA1_FFA20 CAN_FFA1_FFA20_Msk /*!< Filter FIFO Assignment for filter 20 */ |
6249 | #define CAN_FFA1_FFA21_Pos (21U) |
| 6250 | #define CAN_FFA1_FFA21_Pos (21U) |
6250 | #define CAN_FFA1_FFA21_Msk (0x1UL << CAN_FFA1_FFA21_Pos) /*!< 0x00200000 */ |
| 6251 | #define CAN_FFA1_FFA21_Msk (0x1UL << CAN_FFA1_FFA21_Pos) /*!< 0x00200000 */ |
6251 | #define CAN_FFA1_FFA21 CAN_FFA1_FFA21_Msk /*!< Filter FIFO Assignment for filter 21 */ |
| 6252 | #define CAN_FFA1_FFA21 CAN_FFA1_FFA21_Msk /*!< Filter FIFO Assignment for filter 21 */ |
6252 | #define CAN_FFA1_FFA22_Pos (22U) |
| 6253 | #define CAN_FFA1_FFA22_Pos (22U) |
6253 | #define CAN_FFA1_FFA22_Msk (0x1UL << CAN_FFA1_FFA22_Pos) /*!< 0x00400000 */ |
| 6254 | #define CAN_FFA1_FFA22_Msk (0x1UL << CAN_FFA1_FFA22_Pos) /*!< 0x00400000 */ |
6254 | #define CAN_FFA1_FFA22 CAN_FFA1_FFA22_Msk /*!< Filter FIFO Assignment for filter 22 */ |
| 6255 | #define CAN_FFA1_FFA22 CAN_FFA1_FFA22_Msk /*!< Filter FIFO Assignment for filter 22 */ |
6255 | #define CAN_FFA1_FFA23_Pos (23U) |
| 6256 | #define CAN_FFA1_FFA23_Pos (23U) |
6256 | #define CAN_FFA1_FFA23_Msk (0x1UL << CAN_FFA1_FFA23_Pos) /*!< 0x00800000 */ |
| 6257 | #define CAN_FFA1_FFA23_Msk (0x1UL << CAN_FFA1_FFA23_Pos) /*!< 0x00800000 */ |
6257 | #define CAN_FFA1_FFA23 CAN_FFA1_FFA23_Msk /*!< Filter FIFO Assignment for filter 23 */ |
| 6258 | #define CAN_FFA1_FFA23 CAN_FFA1_FFA23_Msk /*!< Filter FIFO Assignment for filter 23 */ |
6258 | #define CAN_FFA1_FFA24_Pos (24U) |
| 6259 | #define CAN_FFA1_FFA24_Pos (24U) |
6259 | #define CAN_FFA1_FFA24_Msk (0x1UL << CAN_FFA1_FFA24_Pos) /*!< 0x01000000 */ |
| 6260 | #define CAN_FFA1_FFA24_Msk (0x1UL << CAN_FFA1_FFA24_Pos) /*!< 0x01000000 */ |
6260 | #define CAN_FFA1_FFA24 CAN_FFA1_FFA24_Msk /*!< Filter FIFO Assignment for filter 24 */ |
| 6261 | #define CAN_FFA1_FFA24 CAN_FFA1_FFA24_Msk /*!< Filter FIFO Assignment for filter 24 */ |
6261 | #define CAN_FFA1_FFA25_Pos (25U) |
| 6262 | #define CAN_FFA1_FFA25_Pos (25U) |
6262 | #define CAN_FFA1_FFA25_Msk (0x1UL << CAN_FFA1_FFA25_Pos) /*!< 0x02000000 */ |
| 6263 | #define CAN_FFA1_FFA25_Msk (0x1UL << CAN_FFA1_FFA25_Pos) /*!< 0x02000000 */ |
6263 | #define CAN_FFA1_FFA25 CAN_FFA1_FFA25_Msk /*!< Filter FIFO Assignment for filter 25 */ |
| 6264 | #define CAN_FFA1_FFA25 CAN_FFA1_FFA25_Msk /*!< Filter FIFO Assignment for filter 25 */ |
6264 | #define CAN_FFA1_FFA26_Pos (26U) |
| 6265 | #define CAN_FFA1_FFA26_Pos (26U) |
6265 | #define CAN_FFA1_FFA26_Msk (0x1UL << CAN_FFA1_FFA26_Pos) /*!< 0x04000000 */ |
| 6266 | #define CAN_FFA1_FFA26_Msk (0x1UL << CAN_FFA1_FFA26_Pos) /*!< 0x04000000 */ |
6266 | #define CAN_FFA1_FFA26 CAN_FFA1_FFA26_Msk /*!< Filter FIFO Assignment for filter 26 */ |
| 6267 | #define CAN_FFA1_FFA26 CAN_FFA1_FFA26_Msk /*!< Filter FIFO Assignment for filter 26 */ |
6267 | #define CAN_FFA1_FFA27_Pos (27U) |
| 6268 | #define CAN_FFA1_FFA27_Pos (27U) |
6268 | #define CAN_FFA1_FFA27_Msk (0x1UL << CAN_FFA1_FFA27_Pos) /*!< 0x08000000 */ |
| 6269 | #define CAN_FFA1_FFA27_Msk (0x1UL << CAN_FFA1_FFA27_Pos) /*!< 0x08000000 */ |
6269 | #define CAN_FFA1_FFA27 CAN_FFA1_FFA27_Msk /*!< Filter FIFO Assignment for filter 27 */ |
| 6270 | #define CAN_FFA1_FFA27 CAN_FFA1_FFA27_Msk /*!< Filter FIFO Assignment for filter 27 */ |
6270 | |
| 6271 | 6271 | /******************* Bit definition for CAN_FA1R register *******************/ |
|
| 6272 | /******************* Bit definition for CAN_FA1R register *******************/ |
6272 | #define CAN_FA1R_FACT_Pos (0U) |
| 6273 | #define CAN_FA1R_FACT_Pos (0U) |
6273 | #define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */ |
| 6274 | #define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */ |
6274 | #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */ |
| 6275 | #define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!< Filter Active */ |
6275 | #define CAN_FA1R_FACT0_Pos (0U) |
| 6276 | #define CAN_FA1R_FACT0_Pos (0U) |
6276 | #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ |
| 6277 | #define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */ |
6277 | #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */ |
| 6278 | #define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!< Filter 0 Active */ |
6278 | #define CAN_FA1R_FACT1_Pos (1U) |
| 6279 | #define CAN_FA1R_FACT1_Pos (1U) |
6279 | #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ |
| 6280 | #define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */ |
6280 | #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */ |
| 6281 | #define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!< Filter 1 Active */ |
6281 | #define CAN_FA1R_FACT2_Pos (2U) |
| 6282 | #define CAN_FA1R_FACT2_Pos (2U) |
6282 | #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ |
| 6283 | #define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */ |
6283 | #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */ |
| 6284 | #define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!< Filter 2 Active */ |
6284 | #define CAN_FA1R_FACT3_Pos (3U) |
| 6285 | #define CAN_FA1R_FACT3_Pos (3U) |
6285 | #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ |
| 6286 | #define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */ |
6286 | #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */ |
| 6287 | #define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!< Filter 3 Active */ |
6287 | #define CAN_FA1R_FACT4_Pos (4U) |
| 6288 | #define CAN_FA1R_FACT4_Pos (4U) |
6288 | #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ |
| 6289 | #define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */ |
6289 | #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */ |
| 6290 | #define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!< Filter 4 Active */ |
6290 | #define CAN_FA1R_FACT5_Pos (5U) |
| 6291 | #define CAN_FA1R_FACT5_Pos (5U) |
6291 | #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ |
| 6292 | #define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */ |
6292 | #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */ |
| 6293 | #define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!< Filter 5 Active */ |
6293 | #define CAN_FA1R_FACT6_Pos (6U) |
| 6294 | #define CAN_FA1R_FACT6_Pos (6U) |
6294 | #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ |
| 6295 | #define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */ |
6295 | #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */ |
| 6296 | #define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!< Filter 6 Active */ |
6296 | #define CAN_FA1R_FACT7_Pos (7U) |
| 6297 | #define CAN_FA1R_FACT7_Pos (7U) |
6297 | #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ |
| 6298 | #define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */ |
6298 | #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */ |
| 6299 | #define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!< Filter 7 Active */ |
6299 | #define CAN_FA1R_FACT8_Pos (8U) |
| 6300 | #define CAN_FA1R_FACT8_Pos (8U) |
6300 | #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ |
| 6301 | #define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */ |
6301 | #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */ |
| 6302 | #define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!< Filter 8 Active */ |
6302 | #define CAN_FA1R_FACT9_Pos (9U) |
| 6303 | #define CAN_FA1R_FACT9_Pos (9U) |
6303 | #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ |
| 6304 | #define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */ |
6304 | #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */ |
| 6305 | #define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!< Filter 9 Active */ |
6305 | #define CAN_FA1R_FACT10_Pos (10U) |
| 6306 | #define CAN_FA1R_FACT10_Pos (10U) |
6306 | #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ |
| 6307 | #define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */ |
6307 | #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */ |
| 6308 | #define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!< Filter 10 Active */ |
6308 | #define CAN_FA1R_FACT11_Pos (11U) |
| 6309 | #define CAN_FA1R_FACT11_Pos (11U) |
6309 | #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ |
| 6310 | #define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */ |
6310 | #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */ |
| 6311 | #define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!< Filter 11 Active */ |
6311 | #define CAN_FA1R_FACT12_Pos (12U) |
| 6312 | #define CAN_FA1R_FACT12_Pos (12U) |
6312 | #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ |
| 6313 | #define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */ |
6313 | #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */ |
| 6314 | #define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!< Filter 12 Active */ |
6314 | #define CAN_FA1R_FACT13_Pos (13U) |
| 6315 | #define CAN_FA1R_FACT13_Pos (13U) |
6315 | #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ |
| 6316 | #define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */ |
6316 | #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */ |
| 6317 | #define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!< Filter 13 Active */ |
6317 | #define CAN_FA1R_FACT14_Pos (14U) |
| 6318 | #define CAN_FA1R_FACT14_Pos (14U) |
6318 | #define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */ |
| 6319 | #define CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos) /*!< 0x00004000 */ |
6319 | #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!< Filter 14 Active */ |
| 6320 | #define CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk /*!< Filter 14 Active */ |
6320 | #define CAN_FA1R_FACT15_Pos (15U) |
| 6321 | #define CAN_FA1R_FACT15_Pos (15U) |
6321 | #define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */ |
| 6322 | #define CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos) /*!< 0x00008000 */ |
6322 | #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!< Filter 15 Active */ |
| 6323 | #define CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk /*!< Filter 15 Active */ |
6323 | #define CAN_FA1R_FACT16_Pos (16U) |
| 6324 | #define CAN_FA1R_FACT16_Pos (16U) |
6324 | #define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */ |
| 6325 | #define CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos) /*!< 0x00010000 */ |
6325 | #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!< Filter 16 Active */ |
| 6326 | #define CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk /*!< Filter 16 Active */ |
6326 | #define CAN_FA1R_FACT17_Pos (17U) |
| 6327 | #define CAN_FA1R_FACT17_Pos (17U) |
6327 | #define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */ |
| 6328 | #define CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos) /*!< 0x00020000 */ |
6328 | #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!< Filter 17 Active */ |
| 6329 | #define CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk /*!< Filter 17 Active */ |
6329 | #define CAN_FA1R_FACT18_Pos (18U) |
| 6330 | #define CAN_FA1R_FACT18_Pos (18U) |
6330 | #define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */ |
| 6331 | #define CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos) /*!< 0x00040000 */ |
6331 | #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!< Filter 18 Active */ |
| 6332 | #define CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk /*!< Filter 18 Active */ |
6332 | #define CAN_FA1R_FACT19_Pos (19U) |
| 6333 | #define CAN_FA1R_FACT19_Pos (19U) |
6333 | #define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */ |
| 6334 | #define CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos) /*!< 0x00080000 */ |
6334 | #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!< Filter 19 Active */ |
| 6335 | #define CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk /*!< Filter 19 Active */ |
6335 | #define CAN_FA1R_FACT20_Pos (20U) |
| 6336 | #define CAN_FA1R_FACT20_Pos (20U) |
6336 | #define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */ |
| 6337 | #define CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos) /*!< 0x00100000 */ |
6337 | #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!< Filter 20 Active */ |
| 6338 | #define CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk /*!< Filter 20 Active */ |
6338 | #define CAN_FA1R_FACT21_Pos (21U) |
| 6339 | #define CAN_FA1R_FACT21_Pos (21U) |
6339 | #define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */ |
| 6340 | #define CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos) /*!< 0x00200000 */ |
6340 | #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!< Filter 21 Active */ |
| 6341 | #define CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk /*!< Filter 21 Active */ |
6341 | #define CAN_FA1R_FACT22_Pos (22U) |
| 6342 | #define CAN_FA1R_FACT22_Pos (22U) |
6342 | #define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */ |
| 6343 | #define CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos) /*!< 0x00400000 */ |
6343 | #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!< Filter 22 Active */ |
| 6344 | #define CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk /*!< Filter 22 Active */ |
6344 | #define CAN_FA1R_FACT23_Pos (23U) |
| 6345 | #define CAN_FA1R_FACT23_Pos (23U) |
6345 | #define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */ |
| 6346 | #define CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos) /*!< 0x00800000 */ |
6346 | #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!< Filter 23 Active */ |
| 6347 | #define CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk /*!< Filter 23 Active */ |
6347 | #define CAN_FA1R_FACT24_Pos (24U) |
| 6348 | #define CAN_FA1R_FACT24_Pos (24U) |
6348 | #define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */ |
| 6349 | #define CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos) /*!< 0x01000000 */ |
6349 | #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!< Filter 24 Active */ |
| 6350 | #define CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk /*!< Filter 24 Active */ |
6350 | #define CAN_FA1R_FACT25_Pos (25U) |
| 6351 | #define CAN_FA1R_FACT25_Pos (25U) |
6351 | #define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */ |
| 6352 | #define CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos) /*!< 0x02000000 */ |
6352 | #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!< Filter 25 Active */ |
| 6353 | #define CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk /*!< Filter 25 Active */ |
6353 | #define CAN_FA1R_FACT26_Pos (26U) |
| 6354 | #define CAN_FA1R_FACT26_Pos (26U) |
6354 | #define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */ |
| 6355 | #define CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos) /*!< 0x04000000 */ |
6355 | #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!< Filter 26 Active */ |
| 6356 | #define CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk /*!< Filter 26 Active */ |
6356 | #define CAN_FA1R_FACT27_Pos (27U) |
| 6357 | #define CAN_FA1R_FACT27_Pos (27U) |
6357 | #define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */ |
| 6358 | #define CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos) /*!< 0x08000000 */ |
6358 | #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!< Filter 27 Active */ |
| 6359 | #define CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk /*!< Filter 27 Active */ |
6359 | |
| 6360 | 6360 | /******************* Bit definition for CAN_F0R1 register *******************/ |
|
| 6361 | /******************* Bit definition for CAN_F0R1 register *******************/ |
6361 | #define CAN_F0R1_FB0_Pos (0U) |
| 6362 | #define CAN_F0R1_FB0_Pos (0U) |
6362 | #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ |
| 6363 | #define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */ |
6363 | #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */ |
| 6364 | #define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!< Filter bit 0 */ |
6364 | #define CAN_F0R1_FB1_Pos (1U) |
| 6365 | #define CAN_F0R1_FB1_Pos (1U) |
6365 | #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ |
| 6366 | #define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */ |
6366 | #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */ |
| 6367 | #define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!< Filter bit 1 */ |
6367 | #define CAN_F0R1_FB2_Pos (2U) |
| 6368 | #define CAN_F0R1_FB2_Pos (2U) |
6368 | #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ |
| 6369 | #define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */ |
6369 | #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */ |
| 6370 | #define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!< Filter bit 2 */ |
6370 | #define CAN_F0R1_FB3_Pos (3U) |
| 6371 | #define CAN_F0R1_FB3_Pos (3U) |
6371 | #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ |
| 6372 | #define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */ |
6372 | #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */ |
| 6373 | #define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!< Filter bit 3 */ |
6373 | #define CAN_F0R1_FB4_Pos (4U) |
| 6374 | #define CAN_F0R1_FB4_Pos (4U) |
6374 | #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ |
| 6375 | #define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */ |
6375 | #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */ |
| 6376 | #define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!< Filter bit 4 */ |
6376 | #define CAN_F0R1_FB5_Pos (5U) |
| 6377 | #define CAN_F0R1_FB5_Pos (5U) |
6377 | #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ |
| 6378 | #define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */ |
6378 | #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */ |
| 6379 | #define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!< Filter bit 5 */ |
6379 | #define CAN_F0R1_FB6_Pos (6U) |
| 6380 | #define CAN_F0R1_FB6_Pos (6U) |
6380 | #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ |
| 6381 | #define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */ |
6381 | #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */ |
| 6382 | #define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!< Filter bit 6 */ |
6382 | #define CAN_F0R1_FB7_Pos (7U) |
| 6383 | #define CAN_F0R1_FB7_Pos (7U) |
6383 | #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ |
| 6384 | #define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */ |
6384 | #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */ |
| 6385 | #define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!< Filter bit 7 */ |
6385 | #define CAN_F0R1_FB8_Pos (8U) |
| 6386 | #define CAN_F0R1_FB8_Pos (8U) |
6386 | #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ |
| 6387 | #define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */ |
6387 | #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */ |
| 6388 | #define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!< Filter bit 8 */ |
6388 | #define CAN_F0R1_FB9_Pos (9U) |
| 6389 | #define CAN_F0R1_FB9_Pos (9U) |
6389 | #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ |
| 6390 | #define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */ |
6390 | #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */ |
| 6391 | #define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!< Filter bit 9 */ |
6391 | #define CAN_F0R1_FB10_Pos (10U) |
| 6392 | #define CAN_F0R1_FB10_Pos (10U) |
6392 | #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ |
| 6393 | #define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */ |
6393 | #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */ |
| 6394 | #define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!< Filter bit 10 */ |
6394 | #define CAN_F0R1_FB11_Pos (11U) |
| 6395 | #define CAN_F0R1_FB11_Pos (11U) |
6395 | #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ |
| 6396 | #define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */ |
6396 | #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */ |
| 6397 | #define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!< Filter bit 11 */ |
6397 | #define CAN_F0R1_FB12_Pos (12U) |
| 6398 | #define CAN_F0R1_FB12_Pos (12U) |
6398 | #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ |
| 6399 | #define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */ |
6399 | #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */ |
| 6400 | #define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!< Filter bit 12 */ |
6400 | #define CAN_F0R1_FB13_Pos (13U) |
| 6401 | #define CAN_F0R1_FB13_Pos (13U) |
6401 | #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ |
| 6402 | #define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */ |
6402 | #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */ |
| 6403 | #define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!< Filter bit 13 */ |
6403 | #define CAN_F0R1_FB14_Pos (14U) |
| 6404 | #define CAN_F0R1_FB14_Pos (14U) |
6404 | #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ |
| 6405 | #define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */ |
6405 | #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */ |
| 6406 | #define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!< Filter bit 14 */ |
6406 | #define CAN_F0R1_FB15_Pos (15U) |
| 6407 | #define CAN_F0R1_FB15_Pos (15U) |
6407 | #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ |
| 6408 | #define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */ |
6408 | #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */ |
| 6409 | #define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!< Filter bit 15 */ |
6409 | #define CAN_F0R1_FB16_Pos (16U) |
| 6410 | #define CAN_F0R1_FB16_Pos (16U) |
6410 | #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ |
| 6411 | #define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */ |
6411 | #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */ |
| 6412 | #define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!< Filter bit 16 */ |
6412 | #define CAN_F0R1_FB17_Pos (17U) |
| 6413 | #define CAN_F0R1_FB17_Pos (17U) |
6413 | #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ |
| 6414 | #define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */ |
6414 | #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */ |
| 6415 | #define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!< Filter bit 17 */ |
6415 | #define CAN_F0R1_FB18_Pos (18U) |
| 6416 | #define CAN_F0R1_FB18_Pos (18U) |
6416 | #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ |
| 6417 | #define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */ |
6417 | #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */ |
| 6418 | #define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!< Filter bit 18 */ |
6418 | #define CAN_F0R1_FB19_Pos (19U) |
| 6419 | #define CAN_F0R1_FB19_Pos (19U) |
6419 | #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ |
| 6420 | #define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */ |
6420 | #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */ |
| 6421 | #define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!< Filter bit 19 */ |
6421 | #define CAN_F0R1_FB20_Pos (20U) |
| 6422 | #define CAN_F0R1_FB20_Pos (20U) |
6422 | #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ |
| 6423 | #define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */ |
6423 | #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */ |
| 6424 | #define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!< Filter bit 20 */ |
6424 | #define CAN_F0R1_FB21_Pos (21U) |
| 6425 | #define CAN_F0R1_FB21_Pos (21U) |
6425 | #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ |
| 6426 | #define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */ |
6426 | #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */ |
| 6427 | #define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!< Filter bit 21 */ |
6427 | #define CAN_F0R1_FB22_Pos (22U) |
| 6428 | #define CAN_F0R1_FB22_Pos (22U) |
6428 | #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ |
| 6429 | #define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */ |
6429 | #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */ |
| 6430 | #define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!< Filter bit 22 */ |
6430 | #define CAN_F0R1_FB23_Pos (23U) |
| 6431 | #define CAN_F0R1_FB23_Pos (23U) |
6431 | #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ |
| 6432 | #define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */ |
6432 | #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */ |
| 6433 | #define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!< Filter bit 23 */ |
6433 | #define CAN_F0R1_FB24_Pos (24U) |
| 6434 | #define CAN_F0R1_FB24_Pos (24U) |
6434 | #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ |
| 6435 | #define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */ |
6435 | #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */ |
| 6436 | #define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!< Filter bit 24 */ |
6436 | #define CAN_F0R1_FB25_Pos (25U) |
| 6437 | #define CAN_F0R1_FB25_Pos (25U) |
6437 | #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ |
| 6438 | #define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */ |
6438 | #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */ |
| 6439 | #define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!< Filter bit 25 */ |
6439 | #define CAN_F0R1_FB26_Pos (26U) |
| 6440 | #define CAN_F0R1_FB26_Pos (26U) |
6440 | #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ |
| 6441 | #define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */ |
6441 | #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */ |
| 6442 | #define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!< Filter bit 26 */ |
6442 | #define CAN_F0R1_FB27_Pos (27U) |
| 6443 | #define CAN_F0R1_FB27_Pos (27U) |
6443 | #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ |
| 6444 | #define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */ |
6444 | #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */ |
| 6445 | #define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!< Filter bit 27 */ |
6445 | #define CAN_F0R1_FB28_Pos (28U) |
| 6446 | #define CAN_F0R1_FB28_Pos (28U) |
6446 | #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ |
| 6447 | #define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */ |
6447 | #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */ |
| 6448 | #define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!< Filter bit 28 */ |
6448 | #define CAN_F0R1_FB29_Pos (29U) |
| 6449 | #define CAN_F0R1_FB29_Pos (29U) |
6449 | #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ |
| 6450 | #define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */ |
6450 | #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */ |
| 6451 | #define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!< Filter bit 29 */ |
6451 | #define CAN_F0R1_FB30_Pos (30U) |
| 6452 | #define CAN_F0R1_FB30_Pos (30U) |
6452 | #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ |
| 6453 | #define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */ |
6453 | #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */ |
| 6454 | #define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!< Filter bit 30 */ |
6454 | #define CAN_F0R1_FB31_Pos (31U) |
| 6455 | #define CAN_F0R1_FB31_Pos (31U) |
6455 | #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ |
| 6456 | #define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */ |
6456 | #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */ |
| 6457 | #define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!< Filter bit 31 */ |
6457 | |
| 6458 | 6458 | /******************* Bit definition for CAN_F1R1 register *******************/ |
|
| 6459 | /******************* Bit definition for CAN_F1R1 register *******************/ |
6459 | #define CAN_F1R1_FB0_Pos (0U) |
| 6460 | #define CAN_F1R1_FB0_Pos (0U) |
6460 | #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ |
| 6461 | #define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */ |
6461 | #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */ |
| 6462 | #define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!< Filter bit 0 */ |
6462 | #define CAN_F1R1_FB1_Pos (1U) |
| 6463 | #define CAN_F1R1_FB1_Pos (1U) |
6463 | #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ |
| 6464 | #define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */ |
6464 | #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */ |
| 6465 | #define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!< Filter bit 1 */ |
6465 | #define CAN_F1R1_FB2_Pos (2U) |
| 6466 | #define CAN_F1R1_FB2_Pos (2U) |
6466 | #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ |
| 6467 | #define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */ |
6467 | #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */ |
| 6468 | #define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!< Filter bit 2 */ |
6468 | #define CAN_F1R1_FB3_Pos (3U) |
| 6469 | #define CAN_F1R1_FB3_Pos (3U) |
6469 | #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ |
| 6470 | #define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */ |
6470 | #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */ |
| 6471 | #define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!< Filter bit 3 */ |
6471 | #define CAN_F1R1_FB4_Pos (4U) |
| 6472 | #define CAN_F1R1_FB4_Pos (4U) |
6472 | #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ |
| 6473 | #define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */ |
6473 | #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */ |
| 6474 | #define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!< Filter bit 4 */ |
6474 | #define CAN_F1R1_FB5_Pos (5U) |
| 6475 | #define CAN_F1R1_FB5_Pos (5U) |
6475 | #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ |
| 6476 | #define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */ |
6476 | #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */ |
| 6477 | #define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!< Filter bit 5 */ |
6477 | #define CAN_F1R1_FB6_Pos (6U) |
| 6478 | #define CAN_F1R1_FB6_Pos (6U) |
6478 | #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ |
| 6479 | #define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */ |
6479 | #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */ |
| 6480 | #define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!< Filter bit 6 */ |
6480 | #define CAN_F1R1_FB7_Pos (7U) |
| 6481 | #define CAN_F1R1_FB7_Pos (7U) |
6481 | #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ |
| 6482 | #define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */ |
6482 | #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */ |
| 6483 | #define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!< Filter bit 7 */ |
6483 | #define CAN_F1R1_FB8_Pos (8U) |
| 6484 | #define CAN_F1R1_FB8_Pos (8U) |
6484 | #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ |
| 6485 | #define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */ |
6485 | #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */ |
| 6486 | #define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!< Filter bit 8 */ |
6486 | #define CAN_F1R1_FB9_Pos (9U) |
| 6487 | #define CAN_F1R1_FB9_Pos (9U) |
6487 | #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ |
| 6488 | #define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */ |
6488 | #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */ |
| 6489 | #define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!< Filter bit 9 */ |
6489 | #define CAN_F1R1_FB10_Pos (10U) |
| 6490 | #define CAN_F1R1_FB10_Pos (10U) |
6490 | #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ |
| 6491 | #define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */ |
6491 | #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */ |
| 6492 | #define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!< Filter bit 10 */ |
6492 | #define CAN_F1R1_FB11_Pos (11U) |
| 6493 | #define CAN_F1R1_FB11_Pos (11U) |
6493 | #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ |
| 6494 | #define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */ |
6494 | #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */ |
| 6495 | #define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!< Filter bit 11 */ |
6495 | #define CAN_F1R1_FB12_Pos (12U) |
| 6496 | #define CAN_F1R1_FB12_Pos (12U) |
6496 | #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ |
| 6497 | #define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */ |
6497 | #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */ |
| 6498 | #define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!< Filter bit 12 */ |
6498 | #define CAN_F1R1_FB13_Pos (13U) |
| 6499 | #define CAN_F1R1_FB13_Pos (13U) |
6499 | #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ |
| 6500 | #define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */ |
6500 | #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */ |
| 6501 | #define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!< Filter bit 13 */ |
6501 | #define CAN_F1R1_FB14_Pos (14U) |
| 6502 | #define CAN_F1R1_FB14_Pos (14U) |
6502 | #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ |
| 6503 | #define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */ |
6503 | #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */ |
| 6504 | #define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!< Filter bit 14 */ |
6504 | #define CAN_F1R1_FB15_Pos (15U) |
| 6505 | #define CAN_F1R1_FB15_Pos (15U) |
6505 | #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ |
| 6506 | #define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */ |
6506 | #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */ |
| 6507 | #define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!< Filter bit 15 */ |
6507 | #define CAN_F1R1_FB16_Pos (16U) |
| 6508 | #define CAN_F1R1_FB16_Pos (16U) |
6508 | #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ |
| 6509 | #define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */ |
6509 | #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */ |
| 6510 | #define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!< Filter bit 16 */ |
6510 | #define CAN_F1R1_FB17_Pos (17U) |
| 6511 | #define CAN_F1R1_FB17_Pos (17U) |
6511 | #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ |
| 6512 | #define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */ |
6512 | #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */ |
| 6513 | #define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!< Filter bit 17 */ |
6513 | #define CAN_F1R1_FB18_Pos (18U) |
| 6514 | #define CAN_F1R1_FB18_Pos (18U) |
6514 | #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ |
| 6515 | #define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */ |
6515 | #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */ |
| 6516 | #define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!< Filter bit 18 */ |
6516 | #define CAN_F1R1_FB19_Pos (19U) |
| 6517 | #define CAN_F1R1_FB19_Pos (19U) |
6517 | #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ |
| 6518 | #define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */ |
6518 | #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */ |
| 6519 | #define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!< Filter bit 19 */ |
6519 | #define CAN_F1R1_FB20_Pos (20U) |
| 6520 | #define CAN_F1R1_FB20_Pos (20U) |
6520 | #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ |
| 6521 | #define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */ |
6521 | #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */ |
| 6522 | #define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!< Filter bit 20 */ |
6522 | #define CAN_F1R1_FB21_Pos (21U) |
| 6523 | #define CAN_F1R1_FB21_Pos (21U) |
6523 | #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ |
| 6524 | #define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */ |
6524 | #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */ |
| 6525 | #define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!< Filter bit 21 */ |
6525 | #define CAN_F1R1_FB22_Pos (22U) |
| 6526 | #define CAN_F1R1_FB22_Pos (22U) |
6526 | #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ |
| 6527 | #define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */ |
6527 | #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */ |
| 6528 | #define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!< Filter bit 22 */ |
6528 | #define CAN_F1R1_FB23_Pos (23U) |
| 6529 | #define CAN_F1R1_FB23_Pos (23U) |
6529 | #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ |
| 6530 | #define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */ |
6530 | #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */ |
| 6531 | #define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!< Filter bit 23 */ |
6531 | #define CAN_F1R1_FB24_Pos (24U) |
| 6532 | #define CAN_F1R1_FB24_Pos (24U) |
6532 | #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ |
| 6533 | #define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */ |
6533 | #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */ |
| 6534 | #define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!< Filter bit 24 */ |
6534 | #define CAN_F1R1_FB25_Pos (25U) |
| 6535 | #define CAN_F1R1_FB25_Pos (25U) |
6535 | #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ |
| 6536 | #define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */ |
6536 | #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */ |
| 6537 | #define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!< Filter bit 25 */ |
6537 | #define CAN_F1R1_FB26_Pos (26U) |
| 6538 | #define CAN_F1R1_FB26_Pos (26U) |
6538 | #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ |
| 6539 | #define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */ |
6539 | #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */ |
| 6540 | #define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!< Filter bit 26 */ |
6540 | #define CAN_F1R1_FB27_Pos (27U) |
| 6541 | #define CAN_F1R1_FB27_Pos (27U) |
6541 | #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ |
| 6542 | #define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */ |
6542 | #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */ |
| 6543 | #define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!< Filter bit 27 */ |
6543 | #define CAN_F1R1_FB28_Pos (28U) |
| 6544 | #define CAN_F1R1_FB28_Pos (28U) |
6544 | #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ |
| 6545 | #define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */ |
6545 | #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */ |
| 6546 | #define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!< Filter bit 28 */ |
6546 | #define CAN_F1R1_FB29_Pos (29U) |
| 6547 | #define CAN_F1R1_FB29_Pos (29U) |
6547 | #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ |
| 6548 | #define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */ |
6548 | #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */ |
| 6549 | #define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!< Filter bit 29 */ |
6549 | #define CAN_F1R1_FB30_Pos (30U) |
| 6550 | #define CAN_F1R1_FB30_Pos (30U) |
6550 | #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ |
| 6551 | #define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */ |
6551 | #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */ |
| 6552 | #define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!< Filter bit 30 */ |
6552 | #define CAN_F1R1_FB31_Pos (31U) |
| 6553 | #define CAN_F1R1_FB31_Pos (31U) |
6553 | #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ |
| 6554 | #define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */ |
6554 | #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */ |
| 6555 | #define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!< Filter bit 31 */ |
6555 | |
| 6556 | 6556 | /******************* Bit definition for CAN_F2R1 register *******************/ |
|
| 6557 | /******************* Bit definition for CAN_F2R1 register *******************/ |
6557 | #define CAN_F2R1_FB0_Pos (0U) |
| 6558 | #define CAN_F2R1_FB0_Pos (0U) |
6558 | #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ |
| 6559 | #define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */ |
6559 | #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */ |
| 6560 | #define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!< Filter bit 0 */ |
6560 | #define CAN_F2R1_FB1_Pos (1U) |
| 6561 | #define CAN_F2R1_FB1_Pos (1U) |
6561 | #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ |
| 6562 | #define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */ |
6562 | #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */ |
| 6563 | #define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!< Filter bit 1 */ |
6563 | #define CAN_F2R1_FB2_Pos (2U) |
| 6564 | #define CAN_F2R1_FB2_Pos (2U) |
6564 | #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ |
| 6565 | #define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */ |
6565 | #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */ |
| 6566 | #define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!< Filter bit 2 */ |
6566 | #define CAN_F2R1_FB3_Pos (3U) |
| 6567 | #define CAN_F2R1_FB3_Pos (3U) |
6567 | #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ |
| 6568 | #define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */ |
6568 | #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */ |
| 6569 | #define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!< Filter bit 3 */ |
6569 | #define CAN_F2R1_FB4_Pos (4U) |
| 6570 | #define CAN_F2R1_FB4_Pos (4U) |
6570 | #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ |
| 6571 | #define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */ |
6571 | #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */ |
| 6572 | #define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!< Filter bit 4 */ |
6572 | #define CAN_F2R1_FB5_Pos (5U) |
| 6573 | #define CAN_F2R1_FB5_Pos (5U) |
6573 | #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ |
| 6574 | #define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */ |
6574 | #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */ |
| 6575 | #define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!< Filter bit 5 */ |
6575 | #define CAN_F2R1_FB6_Pos (6U) |
| 6576 | #define CAN_F2R1_FB6_Pos (6U) |
6576 | #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ |
| 6577 | #define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */ |
6577 | #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */ |
| 6578 | #define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!< Filter bit 6 */ |
6578 | #define CAN_F2R1_FB7_Pos (7U) |
| 6579 | #define CAN_F2R1_FB7_Pos (7U) |
6579 | #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ |
| 6580 | #define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */ |
6580 | #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */ |
| 6581 | #define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!< Filter bit 7 */ |
6581 | #define CAN_F2R1_FB8_Pos (8U) |
| 6582 | #define CAN_F2R1_FB8_Pos (8U) |
6582 | #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ |
| 6583 | #define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */ |
6583 | #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */ |
| 6584 | #define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!< Filter bit 8 */ |
6584 | #define CAN_F2R1_FB9_Pos (9U) |
| 6585 | #define CAN_F2R1_FB9_Pos (9U) |
6585 | #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ |
| 6586 | #define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */ |
6586 | #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */ |
| 6587 | #define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!< Filter bit 9 */ |
6587 | #define CAN_F2R1_FB10_Pos (10U) |
| 6588 | #define CAN_F2R1_FB10_Pos (10U) |
6588 | #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ |
| 6589 | #define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */ |
6589 | #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */ |
| 6590 | #define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!< Filter bit 10 */ |
6590 | #define CAN_F2R1_FB11_Pos (11U) |
| 6591 | #define CAN_F2R1_FB11_Pos (11U) |
6591 | #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ |
| 6592 | #define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */ |
6592 | #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */ |
| 6593 | #define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!< Filter bit 11 */ |
6593 | #define CAN_F2R1_FB12_Pos (12U) |
| 6594 | #define CAN_F2R1_FB12_Pos (12U) |
6594 | #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ |
| 6595 | #define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */ |
6595 | #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */ |
| 6596 | #define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!< Filter bit 12 */ |
6596 | #define CAN_F2R1_FB13_Pos (13U) |
| 6597 | #define CAN_F2R1_FB13_Pos (13U) |
6597 | #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ |
| 6598 | #define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */ |
6598 | #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */ |
| 6599 | #define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!< Filter bit 13 */ |
6599 | #define CAN_F2R1_FB14_Pos (14U) |
| 6600 | #define CAN_F2R1_FB14_Pos (14U) |
6600 | #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ |
| 6601 | #define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */ |
6601 | #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */ |
| 6602 | #define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!< Filter bit 14 */ |
6602 | #define CAN_F2R1_FB15_Pos (15U) |
| 6603 | #define CAN_F2R1_FB15_Pos (15U) |
6603 | #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ |
| 6604 | #define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */ |
6604 | #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */ |
| 6605 | #define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!< Filter bit 15 */ |
6605 | #define CAN_F2R1_FB16_Pos (16U) |
| 6606 | #define CAN_F2R1_FB16_Pos (16U) |
6606 | #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ |
| 6607 | #define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */ |
6607 | #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */ |
| 6608 | #define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!< Filter bit 16 */ |
6608 | #define CAN_F2R1_FB17_Pos (17U) |
| 6609 | #define CAN_F2R1_FB17_Pos (17U) |
6609 | #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ |
| 6610 | #define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */ |
6610 | #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */ |
| 6611 | #define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!< Filter bit 17 */ |
6611 | #define CAN_F2R1_FB18_Pos (18U) |
| 6612 | #define CAN_F2R1_FB18_Pos (18U) |
6612 | #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ |
| 6613 | #define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */ |
6613 | #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */ |
| 6614 | #define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!< Filter bit 18 */ |
6614 | #define CAN_F2R1_FB19_Pos (19U) |
| 6615 | #define CAN_F2R1_FB19_Pos (19U) |
6615 | #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ |
| 6616 | #define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */ |
6616 | #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */ |
| 6617 | #define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!< Filter bit 19 */ |
6617 | #define CAN_F2R1_FB20_Pos (20U) |
| 6618 | #define CAN_F2R1_FB20_Pos (20U) |
6618 | #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ |
| 6619 | #define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */ |
6619 | #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */ |
| 6620 | #define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!< Filter bit 20 */ |
6620 | #define CAN_F2R1_FB21_Pos (21U) |
| 6621 | #define CAN_F2R1_FB21_Pos (21U) |
6621 | #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ |
| 6622 | #define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */ |
6622 | #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */ |
| 6623 | #define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!< Filter bit 21 */ |
6623 | #define CAN_F2R1_FB22_Pos (22U) |
| 6624 | #define CAN_F2R1_FB22_Pos (22U) |
6624 | #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ |
| 6625 | #define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */ |
6625 | #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */ |
| 6626 | #define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!< Filter bit 22 */ |
6626 | #define CAN_F2R1_FB23_Pos (23U) |
| 6627 | #define CAN_F2R1_FB23_Pos (23U) |
6627 | #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ |
| 6628 | #define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */ |
6628 | #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */ |
| 6629 | #define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!< Filter bit 23 */ |
6629 | #define CAN_F2R1_FB24_Pos (24U) |
| 6630 | #define CAN_F2R1_FB24_Pos (24U) |
6630 | #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ |
| 6631 | #define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */ |
6631 | #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */ |
| 6632 | #define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!< Filter bit 24 */ |
6632 | #define CAN_F2R1_FB25_Pos (25U) |
| 6633 | #define CAN_F2R1_FB25_Pos (25U) |
6633 | #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ |
| 6634 | #define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */ |
6634 | #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */ |
| 6635 | #define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!< Filter bit 25 */ |
6635 | #define CAN_F2R1_FB26_Pos (26U) |
| 6636 | #define CAN_F2R1_FB26_Pos (26U) |
6636 | #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ |
| 6637 | #define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */ |
6637 | #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */ |
| 6638 | #define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!< Filter bit 26 */ |
6638 | #define CAN_F2R1_FB27_Pos (27U) |
| 6639 | #define CAN_F2R1_FB27_Pos (27U) |
6639 | #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ |
| 6640 | #define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */ |
6640 | #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */ |
| 6641 | #define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!< Filter bit 27 */ |
6641 | #define CAN_F2R1_FB28_Pos (28U) |
| 6642 | #define CAN_F2R1_FB28_Pos (28U) |
6642 | #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ |
| 6643 | #define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */ |
6643 | #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */ |
| 6644 | #define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!< Filter bit 28 */ |
6644 | #define CAN_F2R1_FB29_Pos (29U) |
| 6645 | #define CAN_F2R1_FB29_Pos (29U) |
6645 | #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ |
| 6646 | #define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */ |
6646 | #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */ |
| 6647 | #define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!< Filter bit 29 */ |
6647 | #define CAN_F2R1_FB30_Pos (30U) |
| 6648 | #define CAN_F2R1_FB30_Pos (30U) |
6648 | #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ |
| 6649 | #define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */ |
6649 | #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */ |
| 6650 | #define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!< Filter bit 30 */ |
6650 | #define CAN_F2R1_FB31_Pos (31U) |
| 6651 | #define CAN_F2R1_FB31_Pos (31U) |
6651 | #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ |
| 6652 | #define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */ |
6652 | #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */ |
| 6653 | #define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!< Filter bit 31 */ |
6653 | |
| 6654 | 6654 | /******************* Bit definition for CAN_F3R1 register *******************/ |
|
| 6655 | /******************* Bit definition for CAN_F3R1 register *******************/ |
6655 | #define CAN_F3R1_FB0_Pos (0U) |
| 6656 | #define CAN_F3R1_FB0_Pos (0U) |
6656 | #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ |
| 6657 | #define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */ |
6657 | #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */ |
| 6658 | #define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!< Filter bit 0 */ |
6658 | #define CAN_F3R1_FB1_Pos (1U) |
| 6659 | #define CAN_F3R1_FB1_Pos (1U) |
6659 | #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ |
| 6660 | #define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */ |
6660 | #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */ |
| 6661 | #define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!< Filter bit 1 */ |
6661 | #define CAN_F3R1_FB2_Pos (2U) |
| 6662 | #define CAN_F3R1_FB2_Pos (2U) |
6662 | #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ |
| 6663 | #define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */ |
6663 | #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */ |
| 6664 | #define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!< Filter bit 2 */ |
6664 | #define CAN_F3R1_FB3_Pos (3U) |
| 6665 | #define CAN_F3R1_FB3_Pos (3U) |
6665 | #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ |
| 6666 | #define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */ |
6666 | #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */ |
| 6667 | #define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!< Filter bit 3 */ |
6667 | #define CAN_F3R1_FB4_Pos (4U) |
| 6668 | #define CAN_F3R1_FB4_Pos (4U) |
6668 | #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ |
| 6669 | #define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */ |
6669 | #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */ |
| 6670 | #define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!< Filter bit 4 */ |
6670 | #define CAN_F3R1_FB5_Pos (5U) |
| 6671 | #define CAN_F3R1_FB5_Pos (5U) |
6671 | #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ |
| 6672 | #define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */ |
6672 | #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */ |
| 6673 | #define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!< Filter bit 5 */ |
6673 | #define CAN_F3R1_FB6_Pos (6U) |
| 6674 | #define CAN_F3R1_FB6_Pos (6U) |
6674 | #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ |
| 6675 | #define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */ |
6675 | #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */ |
| 6676 | #define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!< Filter bit 6 */ |
6676 | #define CAN_F3R1_FB7_Pos (7U) |
| 6677 | #define CAN_F3R1_FB7_Pos (7U) |
6677 | #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ |
| 6678 | #define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */ |
6678 | #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */ |
| 6679 | #define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!< Filter bit 7 */ |
6679 | #define CAN_F3R1_FB8_Pos (8U) |
| 6680 | #define CAN_F3R1_FB8_Pos (8U) |
6680 | #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ |
| 6681 | #define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */ |
6681 | #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */ |
| 6682 | #define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!< Filter bit 8 */ |
6682 | #define CAN_F3R1_FB9_Pos (9U) |
| 6683 | #define CAN_F3R1_FB9_Pos (9U) |
6683 | #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ |
| 6684 | #define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */ |
6684 | #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */ |
| 6685 | #define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!< Filter bit 9 */ |
6685 | #define CAN_F3R1_FB10_Pos (10U) |
| 6686 | #define CAN_F3R1_FB10_Pos (10U) |
6686 | #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ |
| 6687 | #define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */ |
6687 | #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */ |
| 6688 | #define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!< Filter bit 10 */ |
6688 | #define CAN_F3R1_FB11_Pos (11U) |
| 6689 | #define CAN_F3R1_FB11_Pos (11U) |
6689 | #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ |
| 6690 | #define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */ |
6690 | #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */ |
| 6691 | #define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!< Filter bit 11 */ |
6691 | #define CAN_F3R1_FB12_Pos (12U) |
| 6692 | #define CAN_F3R1_FB12_Pos (12U) |
6692 | #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ |
| 6693 | #define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */ |
6693 | #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */ |
| 6694 | #define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!< Filter bit 12 */ |
6694 | #define CAN_F3R1_FB13_Pos (13U) |
| 6695 | #define CAN_F3R1_FB13_Pos (13U) |
6695 | #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ |
| 6696 | #define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */ |
6696 | #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */ |
| 6697 | #define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!< Filter bit 13 */ |
6697 | #define CAN_F3R1_FB14_Pos (14U) |
| 6698 | #define CAN_F3R1_FB14_Pos (14U) |
6698 | #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ |
| 6699 | #define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */ |
6699 | #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */ |
| 6700 | #define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!< Filter bit 14 */ |
6700 | #define CAN_F3R1_FB15_Pos (15U) |
| 6701 | #define CAN_F3R1_FB15_Pos (15U) |
6701 | #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ |
| 6702 | #define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */ |
6702 | #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */ |
| 6703 | #define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!< Filter bit 15 */ |
6703 | #define CAN_F3R1_FB16_Pos (16U) |
| 6704 | #define CAN_F3R1_FB16_Pos (16U) |
6704 | #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ |
| 6705 | #define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */ |
6705 | #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */ |
| 6706 | #define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!< Filter bit 16 */ |
6706 | #define CAN_F3R1_FB17_Pos (17U) |
| 6707 | #define CAN_F3R1_FB17_Pos (17U) |
6707 | #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ |
| 6708 | #define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */ |
6708 | #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */ |
| 6709 | #define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!< Filter bit 17 */ |
6709 | #define CAN_F3R1_FB18_Pos (18U) |
| 6710 | #define CAN_F3R1_FB18_Pos (18U) |
6710 | #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ |
| 6711 | #define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */ |
6711 | #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */ |
| 6712 | #define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!< Filter bit 18 */ |
6712 | #define CAN_F3R1_FB19_Pos (19U) |
| 6713 | #define CAN_F3R1_FB19_Pos (19U) |
6713 | #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ |
| 6714 | #define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */ |
6714 | #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */ |
| 6715 | #define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!< Filter bit 19 */ |
6715 | #define CAN_F3R1_FB20_Pos (20U) |
| 6716 | #define CAN_F3R1_FB20_Pos (20U) |
6716 | #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ |
| 6717 | #define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */ |
6717 | #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */ |
| 6718 | #define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!< Filter bit 20 */ |
6718 | #define CAN_F3R1_FB21_Pos (21U) |
| 6719 | #define CAN_F3R1_FB21_Pos (21U) |
6719 | #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ |
| 6720 | #define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */ |
6720 | #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */ |
| 6721 | #define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!< Filter bit 21 */ |
6721 | #define CAN_F3R1_FB22_Pos (22U) |
| 6722 | #define CAN_F3R1_FB22_Pos (22U) |
6722 | #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ |
| 6723 | #define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */ |
6723 | #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */ |
| 6724 | #define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!< Filter bit 22 */ |
6724 | #define CAN_F3R1_FB23_Pos (23U) |
| 6725 | #define CAN_F3R1_FB23_Pos (23U) |
6725 | #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ |
| 6726 | #define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */ |
6726 | #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */ |
| 6727 | #define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!< Filter bit 23 */ |
6727 | #define CAN_F3R1_FB24_Pos (24U) |
| 6728 | #define CAN_F3R1_FB24_Pos (24U) |
6728 | #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ |
| 6729 | #define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */ |
6729 | #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */ |
| 6730 | #define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!< Filter bit 24 */ |
6730 | #define CAN_F3R1_FB25_Pos (25U) |
| 6731 | #define CAN_F3R1_FB25_Pos (25U) |
6731 | #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ |
| 6732 | #define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */ |
6732 | #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */ |
| 6733 | #define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!< Filter bit 25 */ |
6733 | #define CAN_F3R1_FB26_Pos (26U) |
| 6734 | #define CAN_F3R1_FB26_Pos (26U) |
6734 | #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ |
| 6735 | #define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */ |
6735 | #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */ |
| 6736 | #define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!< Filter bit 26 */ |
6736 | #define CAN_F3R1_FB27_Pos (27U) |
| 6737 | #define CAN_F3R1_FB27_Pos (27U) |
6737 | #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ |
| 6738 | #define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */ |
6738 | #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */ |
| 6739 | #define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!< Filter bit 27 */ |
6739 | #define CAN_F3R1_FB28_Pos (28U) |
| 6740 | #define CAN_F3R1_FB28_Pos (28U) |
6740 | #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ |
| 6741 | #define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */ |
6741 | #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */ |
| 6742 | #define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!< Filter bit 28 */ |
6742 | #define CAN_F3R1_FB29_Pos (29U) |
| 6743 | #define CAN_F3R1_FB29_Pos (29U) |
6743 | #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ |
| 6744 | #define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */ |
6744 | #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */ |
| 6745 | #define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!< Filter bit 29 */ |
6745 | #define CAN_F3R1_FB30_Pos (30U) |
| 6746 | #define CAN_F3R1_FB30_Pos (30U) |
6746 | #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ |
| 6747 | #define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */ |
6747 | #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */ |
| 6748 | #define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!< Filter bit 30 */ |
6748 | #define CAN_F3R1_FB31_Pos (31U) |
| 6749 | #define CAN_F3R1_FB31_Pos (31U) |
6749 | #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ |
| 6750 | #define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */ |
6750 | #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */ |
| 6751 | #define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!< Filter bit 31 */ |
6751 | |
| 6752 | 6752 | /******************* Bit definition for CAN_F4R1 register *******************/ |
|
| 6753 | /******************* Bit definition for CAN_F4R1 register *******************/ |
6753 | #define CAN_F4R1_FB0_Pos (0U) |
| 6754 | #define CAN_F4R1_FB0_Pos (0U) |
6754 | #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ |
| 6755 | #define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */ |
6755 | #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */ |
| 6756 | #define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!< Filter bit 0 */ |
6756 | #define CAN_F4R1_FB1_Pos (1U) |
| 6757 | #define CAN_F4R1_FB1_Pos (1U) |
6757 | #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ |
| 6758 | #define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */ |
6758 | #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */ |
| 6759 | #define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!< Filter bit 1 */ |
6759 | #define CAN_F4R1_FB2_Pos (2U) |
| 6760 | #define CAN_F4R1_FB2_Pos (2U) |
6760 | #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ |
| 6761 | #define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */ |
6761 | #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */ |
| 6762 | #define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!< Filter bit 2 */ |
6762 | #define CAN_F4R1_FB3_Pos (3U) |
| 6763 | #define CAN_F4R1_FB3_Pos (3U) |
6763 | #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ |
| 6764 | #define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */ |
6764 | #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */ |
| 6765 | #define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!< Filter bit 3 */ |
6765 | #define CAN_F4R1_FB4_Pos (4U) |
| 6766 | #define CAN_F4R1_FB4_Pos (4U) |
6766 | #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ |
| 6767 | #define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */ |
6767 | #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */ |
| 6768 | #define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!< Filter bit 4 */ |
6768 | #define CAN_F4R1_FB5_Pos (5U) |
| 6769 | #define CAN_F4R1_FB5_Pos (5U) |
6769 | #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ |
| 6770 | #define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */ |
6770 | #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */ |
| 6771 | #define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!< Filter bit 5 */ |
6771 | #define CAN_F4R1_FB6_Pos (6U) |
| 6772 | #define CAN_F4R1_FB6_Pos (6U) |
6772 | #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ |
| 6773 | #define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */ |
6773 | #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */ |
| 6774 | #define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!< Filter bit 6 */ |
6774 | #define CAN_F4R1_FB7_Pos (7U) |
| 6775 | #define CAN_F4R1_FB7_Pos (7U) |
6775 | #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ |
| 6776 | #define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */ |
6776 | #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */ |
| 6777 | #define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!< Filter bit 7 */ |
6777 | #define CAN_F4R1_FB8_Pos (8U) |
| 6778 | #define CAN_F4R1_FB8_Pos (8U) |
6778 | #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ |
| 6779 | #define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */ |
6779 | #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */ |
| 6780 | #define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!< Filter bit 8 */ |
6780 | #define CAN_F4R1_FB9_Pos (9U) |
| 6781 | #define CAN_F4R1_FB9_Pos (9U) |
6781 | #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ |
| 6782 | #define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */ |
6782 | #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */ |
| 6783 | #define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!< Filter bit 9 */ |
6783 | #define CAN_F4R1_FB10_Pos (10U) |
| 6784 | #define CAN_F4R1_FB10_Pos (10U) |
6784 | #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ |
| 6785 | #define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */ |
6785 | #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */ |
| 6786 | #define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!< Filter bit 10 */ |
6786 | #define CAN_F4R1_FB11_Pos (11U) |
| 6787 | #define CAN_F4R1_FB11_Pos (11U) |
6787 | #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ |
| 6788 | #define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */ |
6788 | #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */ |
| 6789 | #define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!< Filter bit 11 */ |
6789 | #define CAN_F4R1_FB12_Pos (12U) |
| 6790 | #define CAN_F4R1_FB12_Pos (12U) |
6790 | #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ |
| 6791 | #define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */ |
6791 | #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */ |
| 6792 | #define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!< Filter bit 12 */ |
6792 | #define CAN_F4R1_FB13_Pos (13U) |
| 6793 | #define CAN_F4R1_FB13_Pos (13U) |
6793 | #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ |
| 6794 | #define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */ |
6794 | #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */ |
| 6795 | #define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!< Filter bit 13 */ |
6795 | #define CAN_F4R1_FB14_Pos (14U) |
| 6796 | #define CAN_F4R1_FB14_Pos (14U) |
6796 | #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ |
| 6797 | #define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */ |
6797 | #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */ |
| 6798 | #define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!< Filter bit 14 */ |
6798 | #define CAN_F4R1_FB15_Pos (15U) |
| 6799 | #define CAN_F4R1_FB15_Pos (15U) |
6799 | #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ |
| 6800 | #define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */ |
6800 | #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */ |
| 6801 | #define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!< Filter bit 15 */ |
6801 | #define CAN_F4R1_FB16_Pos (16U) |
| 6802 | #define CAN_F4R1_FB16_Pos (16U) |
6802 | #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ |
| 6803 | #define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */ |
6803 | #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */ |
| 6804 | #define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!< Filter bit 16 */ |
6804 | #define CAN_F4R1_FB17_Pos (17U) |
| 6805 | #define CAN_F4R1_FB17_Pos (17U) |
6805 | #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ |
| 6806 | #define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */ |
6806 | #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */ |
| 6807 | #define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!< Filter bit 17 */ |
6807 | #define CAN_F4R1_FB18_Pos (18U) |
| 6808 | #define CAN_F4R1_FB18_Pos (18U) |
6808 | #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ |
| 6809 | #define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */ |
6809 | #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */ |
| 6810 | #define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!< Filter bit 18 */ |
6810 | #define CAN_F4R1_FB19_Pos (19U) |
| 6811 | #define CAN_F4R1_FB19_Pos (19U) |
6811 | #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ |
| 6812 | #define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */ |
6812 | #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */ |
| 6813 | #define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!< Filter bit 19 */ |
6813 | #define CAN_F4R1_FB20_Pos (20U) |
| 6814 | #define CAN_F4R1_FB20_Pos (20U) |
6814 | #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ |
| 6815 | #define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */ |
6815 | #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */ |
| 6816 | #define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!< Filter bit 20 */ |
6816 | #define CAN_F4R1_FB21_Pos (21U) |
| 6817 | #define CAN_F4R1_FB21_Pos (21U) |
6817 | #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ |
| 6818 | #define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */ |
6818 | #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */ |
| 6819 | #define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!< Filter bit 21 */ |
6819 | #define CAN_F4R1_FB22_Pos (22U) |
| 6820 | #define CAN_F4R1_FB22_Pos (22U) |
6820 | #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ |
| 6821 | #define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */ |
6821 | #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */ |
| 6822 | #define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!< Filter bit 22 */ |
6822 | #define CAN_F4R1_FB23_Pos (23U) |
| 6823 | #define CAN_F4R1_FB23_Pos (23U) |
6823 | #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ |
| 6824 | #define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */ |
6824 | #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */ |
| 6825 | #define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!< Filter bit 23 */ |
6825 | #define CAN_F4R1_FB24_Pos (24U) |
| 6826 | #define CAN_F4R1_FB24_Pos (24U) |
6826 | #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ |
| 6827 | #define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */ |
6827 | #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */ |
| 6828 | #define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!< Filter bit 24 */ |
6828 | #define CAN_F4R1_FB25_Pos (25U) |
| 6829 | #define CAN_F4R1_FB25_Pos (25U) |
6829 | #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ |
| 6830 | #define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */ |
6830 | #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */ |
| 6831 | #define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!< Filter bit 25 */ |
6831 | #define CAN_F4R1_FB26_Pos (26U) |
| 6832 | #define CAN_F4R1_FB26_Pos (26U) |
6832 | #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ |
| 6833 | #define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */ |
6833 | #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */ |
| 6834 | #define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!< Filter bit 26 */ |
6834 | #define CAN_F4R1_FB27_Pos (27U) |
| 6835 | #define CAN_F4R1_FB27_Pos (27U) |
6835 | #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ |
| 6836 | #define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */ |
6836 | #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */ |
| 6837 | #define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!< Filter bit 27 */ |
6837 | #define CAN_F4R1_FB28_Pos (28U) |
| 6838 | #define CAN_F4R1_FB28_Pos (28U) |
6838 | #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ |
| 6839 | #define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */ |
6839 | #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */ |
| 6840 | #define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!< Filter bit 28 */ |
6840 | #define CAN_F4R1_FB29_Pos (29U) |
| 6841 | #define CAN_F4R1_FB29_Pos (29U) |
6841 | #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ |
| 6842 | #define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */ |
6842 | #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */ |
| 6843 | #define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!< Filter bit 29 */ |
6843 | #define CAN_F4R1_FB30_Pos (30U) |
| 6844 | #define CAN_F4R1_FB30_Pos (30U) |
6844 | #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ |
| 6845 | #define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */ |
6845 | #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */ |
| 6846 | #define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!< Filter bit 30 */ |
6846 | #define CAN_F4R1_FB31_Pos (31U) |
| 6847 | #define CAN_F4R1_FB31_Pos (31U) |
6847 | #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ |
| 6848 | #define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */ |
6848 | #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */ |
| 6849 | #define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!< Filter bit 31 */ |
6849 | |
| 6850 | 6850 | /******************* Bit definition for CAN_F5R1 register *******************/ |
|
| 6851 | /******************* Bit definition for CAN_F5R1 register *******************/ |
6851 | #define CAN_F5R1_FB0_Pos (0U) |
| 6852 | #define CAN_F5R1_FB0_Pos (0U) |
6852 | #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ |
| 6853 | #define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */ |
6853 | #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */ |
| 6854 | #define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!< Filter bit 0 */ |
6854 | #define CAN_F5R1_FB1_Pos (1U) |
| 6855 | #define CAN_F5R1_FB1_Pos (1U) |
6855 | #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ |
| 6856 | #define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */ |
6856 | #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */ |
| 6857 | #define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!< Filter bit 1 */ |
6857 | #define CAN_F5R1_FB2_Pos (2U) |
| 6858 | #define CAN_F5R1_FB2_Pos (2U) |
6858 | #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ |
| 6859 | #define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */ |
6859 | #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */ |
| 6860 | #define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!< Filter bit 2 */ |
6860 | #define CAN_F5R1_FB3_Pos (3U) |
| 6861 | #define CAN_F5R1_FB3_Pos (3U) |
6861 | #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ |
| 6862 | #define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */ |
6862 | #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */ |
| 6863 | #define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!< Filter bit 3 */ |
6863 | #define CAN_F5R1_FB4_Pos (4U) |
| 6864 | #define CAN_F5R1_FB4_Pos (4U) |
6864 | #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ |
| 6865 | #define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */ |
6865 | #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */ |
| 6866 | #define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!< Filter bit 4 */ |
6866 | #define CAN_F5R1_FB5_Pos (5U) |
| 6867 | #define CAN_F5R1_FB5_Pos (5U) |
6867 | #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ |
| 6868 | #define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */ |
6868 | #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */ |
| 6869 | #define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!< Filter bit 5 */ |
6869 | #define CAN_F5R1_FB6_Pos (6U) |
| 6870 | #define CAN_F5R1_FB6_Pos (6U) |
6870 | #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ |
| 6871 | #define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */ |
6871 | #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */ |
| 6872 | #define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!< Filter bit 6 */ |
6872 | #define CAN_F5R1_FB7_Pos (7U) |
| 6873 | #define CAN_F5R1_FB7_Pos (7U) |
6873 | #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ |
| 6874 | #define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */ |
6874 | #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */ |
| 6875 | #define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!< Filter bit 7 */ |
6875 | #define CAN_F5R1_FB8_Pos (8U) |
| 6876 | #define CAN_F5R1_FB8_Pos (8U) |
6876 | #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ |
| 6877 | #define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */ |
6877 | #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */ |
| 6878 | #define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!< Filter bit 8 */ |
6878 | #define CAN_F5R1_FB9_Pos (9U) |
| 6879 | #define CAN_F5R1_FB9_Pos (9U) |
6879 | #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ |
| 6880 | #define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */ |
6880 | #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */ |
| 6881 | #define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!< Filter bit 9 */ |
6881 | #define CAN_F5R1_FB10_Pos (10U) |
| 6882 | #define CAN_F5R1_FB10_Pos (10U) |
6882 | #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ |
| 6883 | #define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */ |
6883 | #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */ |
| 6884 | #define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!< Filter bit 10 */ |
6884 | #define CAN_F5R1_FB11_Pos (11U) |
| 6885 | #define CAN_F5R1_FB11_Pos (11U) |
6885 | #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ |
| 6886 | #define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */ |
6886 | #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */ |
| 6887 | #define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!< Filter bit 11 */ |
6887 | #define CAN_F5R1_FB12_Pos (12U) |
| 6888 | #define CAN_F5R1_FB12_Pos (12U) |
6888 | #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ |
| 6889 | #define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */ |
6889 | #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */ |
| 6890 | #define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!< Filter bit 12 */ |
6890 | #define CAN_F5R1_FB13_Pos (13U) |
| 6891 | #define CAN_F5R1_FB13_Pos (13U) |
6891 | #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ |
| 6892 | #define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */ |
6892 | #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */ |
| 6893 | #define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!< Filter bit 13 */ |
6893 | #define CAN_F5R1_FB14_Pos (14U) |
| 6894 | #define CAN_F5R1_FB14_Pos (14U) |
6894 | #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ |
| 6895 | #define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */ |
6895 | #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */ |
| 6896 | #define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!< Filter bit 14 */ |
6896 | #define CAN_F5R1_FB15_Pos (15U) |
| 6897 | #define CAN_F5R1_FB15_Pos (15U) |
6897 | #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ |
| 6898 | #define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */ |
6898 | #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */ |
| 6899 | #define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!< Filter bit 15 */ |
6899 | #define CAN_F5R1_FB16_Pos (16U) |
| 6900 | #define CAN_F5R1_FB16_Pos (16U) |
6900 | #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ |
| 6901 | #define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */ |
6901 | #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */ |
| 6902 | #define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!< Filter bit 16 */ |
6902 | #define CAN_F5R1_FB17_Pos (17U) |
| 6903 | #define CAN_F5R1_FB17_Pos (17U) |
6903 | #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ |
| 6904 | #define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */ |
6904 | #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */ |
| 6905 | #define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!< Filter bit 17 */ |
6905 | #define CAN_F5R1_FB18_Pos (18U) |
| 6906 | #define CAN_F5R1_FB18_Pos (18U) |
6906 | #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ |
| 6907 | #define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */ |
6907 | #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */ |
| 6908 | #define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!< Filter bit 18 */ |
6908 | #define CAN_F5R1_FB19_Pos (19U) |
| 6909 | #define CAN_F5R1_FB19_Pos (19U) |
6909 | #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ |
| 6910 | #define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */ |
6910 | #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */ |
| 6911 | #define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!< Filter bit 19 */ |
6911 | #define CAN_F5R1_FB20_Pos (20U) |
| 6912 | #define CAN_F5R1_FB20_Pos (20U) |
6912 | #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ |
| 6913 | #define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */ |
6913 | #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */ |
| 6914 | #define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!< Filter bit 20 */ |
6914 | #define CAN_F5R1_FB21_Pos (21U) |
| 6915 | #define CAN_F5R1_FB21_Pos (21U) |
6915 | #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ |
| 6916 | #define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */ |
6916 | #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */ |
| 6917 | #define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!< Filter bit 21 */ |
6917 | #define CAN_F5R1_FB22_Pos (22U) |
| 6918 | #define CAN_F5R1_FB22_Pos (22U) |
6918 | #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ |
| 6919 | #define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */ |
6919 | #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */ |
| 6920 | #define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!< Filter bit 22 */ |
6920 | #define CAN_F5R1_FB23_Pos (23U) |
| 6921 | #define CAN_F5R1_FB23_Pos (23U) |
6921 | #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ |
| 6922 | #define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */ |
6922 | #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */ |
| 6923 | #define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!< Filter bit 23 */ |
6923 | #define CAN_F5R1_FB24_Pos (24U) |
| 6924 | #define CAN_F5R1_FB24_Pos (24U) |
6924 | #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ |
| 6925 | #define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */ |
6925 | #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */ |
| 6926 | #define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!< Filter bit 24 */ |
6926 | #define CAN_F5R1_FB25_Pos (25U) |
| 6927 | #define CAN_F5R1_FB25_Pos (25U) |
6927 | #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ |
| 6928 | #define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */ |
6928 | #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */ |
| 6929 | #define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!< Filter bit 25 */ |
6929 | #define CAN_F5R1_FB26_Pos (26U) |
| 6930 | #define CAN_F5R1_FB26_Pos (26U) |
6930 | #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ |
| 6931 | #define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */ |
6931 | #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */ |
| 6932 | #define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!< Filter bit 26 */ |
6932 | #define CAN_F5R1_FB27_Pos (27U) |
| 6933 | #define CAN_F5R1_FB27_Pos (27U) |
6933 | #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ |
| 6934 | #define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */ |
6934 | #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */ |
| 6935 | #define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!< Filter bit 27 */ |
6935 | #define CAN_F5R1_FB28_Pos (28U) |
| 6936 | #define CAN_F5R1_FB28_Pos (28U) |
6936 | #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ |
| 6937 | #define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */ |
6937 | #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */ |
| 6938 | #define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!< Filter bit 28 */ |
6938 | #define CAN_F5R1_FB29_Pos (29U) |
| 6939 | #define CAN_F5R1_FB29_Pos (29U) |
6939 | #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ |
| 6940 | #define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */ |
6940 | #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */ |
| 6941 | #define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!< Filter bit 29 */ |
6941 | #define CAN_F5R1_FB30_Pos (30U) |
| 6942 | #define CAN_F5R1_FB30_Pos (30U) |
6942 | #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ |
| 6943 | #define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */ |
6943 | #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */ |
| 6944 | #define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!< Filter bit 30 */ |
6944 | #define CAN_F5R1_FB31_Pos (31U) |
| 6945 | #define CAN_F5R1_FB31_Pos (31U) |
6945 | #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ |
| 6946 | #define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */ |
6946 | #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */ |
| 6947 | #define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!< Filter bit 31 */ |
6947 | |
| 6948 | 6948 | /******************* Bit definition for CAN_F6R1 register *******************/ |
|
| 6949 | /******************* Bit definition for CAN_F6R1 register *******************/ |
6949 | #define CAN_F6R1_FB0_Pos (0U) |
| 6950 | #define CAN_F6R1_FB0_Pos (0U) |
6950 | #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ |
| 6951 | #define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */ |
6951 | #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */ |
| 6952 | #define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!< Filter bit 0 */ |
6952 | #define CAN_F6R1_FB1_Pos (1U) |
| 6953 | #define CAN_F6R1_FB1_Pos (1U) |
6953 | #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ |
| 6954 | #define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */ |
6954 | #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */ |
| 6955 | #define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!< Filter bit 1 */ |
6955 | #define CAN_F6R1_FB2_Pos (2U) |
| 6956 | #define CAN_F6R1_FB2_Pos (2U) |
6956 | #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ |
| 6957 | #define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */ |
6957 | #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */ |
| 6958 | #define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!< Filter bit 2 */ |
6958 | #define CAN_F6R1_FB3_Pos (3U) |
| 6959 | #define CAN_F6R1_FB3_Pos (3U) |
6959 | #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ |
| 6960 | #define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */ |
6960 | #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */ |
| 6961 | #define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!< Filter bit 3 */ |
6961 | #define CAN_F6R1_FB4_Pos (4U) |
| 6962 | #define CAN_F6R1_FB4_Pos (4U) |
6962 | #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ |
| 6963 | #define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */ |
6963 | #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */ |
| 6964 | #define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!< Filter bit 4 */ |
6964 | #define CAN_F6R1_FB5_Pos (5U) |
| 6965 | #define CAN_F6R1_FB5_Pos (5U) |
6965 | #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ |
| 6966 | #define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */ |
6966 | #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */ |
| 6967 | #define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!< Filter bit 5 */ |
6967 | #define CAN_F6R1_FB6_Pos (6U) |
| 6968 | #define CAN_F6R1_FB6_Pos (6U) |
6968 | #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ |
| 6969 | #define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */ |
6969 | #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */ |
| 6970 | #define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!< Filter bit 6 */ |
6970 | #define CAN_F6R1_FB7_Pos (7U) |
| 6971 | #define CAN_F6R1_FB7_Pos (7U) |
6971 | #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ |
| 6972 | #define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */ |
6972 | #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */ |
| 6973 | #define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!< Filter bit 7 */ |
6973 | #define CAN_F6R1_FB8_Pos (8U) |
| 6974 | #define CAN_F6R1_FB8_Pos (8U) |
6974 | #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ |
| 6975 | #define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */ |
6975 | #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */ |
| 6976 | #define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!< Filter bit 8 */ |
6976 | #define CAN_F6R1_FB9_Pos (9U) |
| 6977 | #define CAN_F6R1_FB9_Pos (9U) |
6977 | #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ |
| 6978 | #define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */ |
6978 | #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */ |
| 6979 | #define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!< Filter bit 9 */ |
6979 | #define CAN_F6R1_FB10_Pos (10U) |
| 6980 | #define CAN_F6R1_FB10_Pos (10U) |
6980 | #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ |
| 6981 | #define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */ |
6981 | #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */ |
| 6982 | #define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!< Filter bit 10 */ |
6982 | #define CAN_F6R1_FB11_Pos (11U) |
| 6983 | #define CAN_F6R1_FB11_Pos (11U) |
6983 | #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ |
| 6984 | #define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */ |
6984 | #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */ |
| 6985 | #define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!< Filter bit 11 */ |
6985 | #define CAN_F6R1_FB12_Pos (12U) |
| 6986 | #define CAN_F6R1_FB12_Pos (12U) |
6986 | #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ |
| 6987 | #define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */ |
6987 | #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */ |
| 6988 | #define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!< Filter bit 12 */ |
6988 | #define CAN_F6R1_FB13_Pos (13U) |
| 6989 | #define CAN_F6R1_FB13_Pos (13U) |
6989 | #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ |
| 6990 | #define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */ |
6990 | #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */ |
| 6991 | #define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!< Filter bit 13 */ |
6991 | #define CAN_F6R1_FB14_Pos (14U) |
| 6992 | #define CAN_F6R1_FB14_Pos (14U) |
6992 | #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ |
| 6993 | #define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */ |
6993 | #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */ |
| 6994 | #define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!< Filter bit 14 */ |
6994 | #define CAN_F6R1_FB15_Pos (15U) |
| 6995 | #define CAN_F6R1_FB15_Pos (15U) |
6995 | #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ |
| 6996 | #define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */ |
6996 | #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */ |
| 6997 | #define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!< Filter bit 15 */ |
6997 | #define CAN_F6R1_FB16_Pos (16U) |
| 6998 | #define CAN_F6R1_FB16_Pos (16U) |
6998 | #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ |
| 6999 | #define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */ |
6999 | #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */ |
| 7000 | #define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!< Filter bit 16 */ |
7000 | #define CAN_F6R1_FB17_Pos (17U) |
| 7001 | #define CAN_F6R1_FB17_Pos (17U) |
7001 | #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ |
| 7002 | #define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */ |
7002 | #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */ |
| 7003 | #define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!< Filter bit 17 */ |
7003 | #define CAN_F6R1_FB18_Pos (18U) |
| 7004 | #define CAN_F6R1_FB18_Pos (18U) |
7004 | #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ |
| 7005 | #define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */ |
7005 | #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */ |
| 7006 | #define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!< Filter bit 18 */ |
7006 | #define CAN_F6R1_FB19_Pos (19U) |
| 7007 | #define CAN_F6R1_FB19_Pos (19U) |
7007 | #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ |
| 7008 | #define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */ |
7008 | #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */ |
| 7009 | #define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!< Filter bit 19 */ |
7009 | #define CAN_F6R1_FB20_Pos (20U) |
| 7010 | #define CAN_F6R1_FB20_Pos (20U) |
7010 | #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ |
| 7011 | #define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */ |
7011 | #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */ |
| 7012 | #define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!< Filter bit 20 */ |
7012 | #define CAN_F6R1_FB21_Pos (21U) |
| 7013 | #define CAN_F6R1_FB21_Pos (21U) |
7013 | #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ |
| 7014 | #define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */ |
7014 | #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */ |
| 7015 | #define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!< Filter bit 21 */ |
7015 | #define CAN_F6R1_FB22_Pos (22U) |
| 7016 | #define CAN_F6R1_FB22_Pos (22U) |
7016 | #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ |
| 7017 | #define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */ |
7017 | #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */ |
| 7018 | #define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!< Filter bit 22 */ |
7018 | #define CAN_F6R1_FB23_Pos (23U) |
| 7019 | #define CAN_F6R1_FB23_Pos (23U) |
7019 | #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ |
| 7020 | #define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */ |
7020 | #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */ |
| 7021 | #define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!< Filter bit 23 */ |
7021 | #define CAN_F6R1_FB24_Pos (24U) |
| 7022 | #define CAN_F6R1_FB24_Pos (24U) |
7022 | #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ |
| 7023 | #define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */ |
7023 | #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */ |
| 7024 | #define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!< Filter bit 24 */ |
7024 | #define CAN_F6R1_FB25_Pos (25U) |
| 7025 | #define CAN_F6R1_FB25_Pos (25U) |
7025 | #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ |
| 7026 | #define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */ |
7026 | #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */ |
| 7027 | #define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!< Filter bit 25 */ |
7027 | #define CAN_F6R1_FB26_Pos (26U) |
| 7028 | #define CAN_F6R1_FB26_Pos (26U) |
7028 | #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ |
| 7029 | #define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */ |
7029 | #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */ |
| 7030 | #define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!< Filter bit 26 */ |
7030 | #define CAN_F6R1_FB27_Pos (27U) |
| 7031 | #define CAN_F6R1_FB27_Pos (27U) |
7031 | #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ |
| 7032 | #define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */ |
7032 | #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */ |
| 7033 | #define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!< Filter bit 27 */ |
7033 | #define CAN_F6R1_FB28_Pos (28U) |
| 7034 | #define CAN_F6R1_FB28_Pos (28U) |
7034 | #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ |
| 7035 | #define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */ |
7035 | #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */ |
| 7036 | #define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!< Filter bit 28 */ |
7036 | #define CAN_F6R1_FB29_Pos (29U) |
| 7037 | #define CAN_F6R1_FB29_Pos (29U) |
7037 | #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ |
| 7038 | #define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */ |
7038 | #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */ |
| 7039 | #define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!< Filter bit 29 */ |
7039 | #define CAN_F6R1_FB30_Pos (30U) |
| 7040 | #define CAN_F6R1_FB30_Pos (30U) |
7040 | #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ |
| 7041 | #define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */ |
7041 | #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */ |
| 7042 | #define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!< Filter bit 30 */ |
7042 | #define CAN_F6R1_FB31_Pos (31U) |
| 7043 | #define CAN_F6R1_FB31_Pos (31U) |
7043 | #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ |
| 7044 | #define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */ |
7044 | #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */ |
| 7045 | #define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!< Filter bit 31 */ |
7045 | |
| 7046 | 7046 | /******************* Bit definition for CAN_F7R1 register *******************/ |
|
| 7047 | /******************* Bit definition for CAN_F7R1 register *******************/ |
7047 | #define CAN_F7R1_FB0_Pos (0U) |
| 7048 | #define CAN_F7R1_FB0_Pos (0U) |
7048 | #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ |
| 7049 | #define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */ |
7049 | #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */ |
| 7050 | #define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!< Filter bit 0 */ |
7050 | #define CAN_F7R1_FB1_Pos (1U) |
| 7051 | #define CAN_F7R1_FB1_Pos (1U) |
7051 | #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ |
| 7052 | #define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */ |
7052 | #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */ |
| 7053 | #define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!< Filter bit 1 */ |
7053 | #define CAN_F7R1_FB2_Pos (2U) |
| 7054 | #define CAN_F7R1_FB2_Pos (2U) |
7054 | #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ |
| 7055 | #define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */ |
7055 | #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */ |
| 7056 | #define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!< Filter bit 2 */ |
7056 | #define CAN_F7R1_FB3_Pos (3U) |
| 7057 | #define CAN_F7R1_FB3_Pos (3U) |
7057 | #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ |
| 7058 | #define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */ |
7058 | #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */ |
| 7059 | #define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!< Filter bit 3 */ |
7059 | #define CAN_F7R1_FB4_Pos (4U) |
| 7060 | #define CAN_F7R1_FB4_Pos (4U) |
7060 | #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ |
| 7061 | #define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */ |
7061 | #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */ |
| 7062 | #define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!< Filter bit 4 */ |
7062 | #define CAN_F7R1_FB5_Pos (5U) |
| 7063 | #define CAN_F7R1_FB5_Pos (5U) |
7063 | #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ |
| 7064 | #define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */ |
7064 | #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */ |
| 7065 | #define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!< Filter bit 5 */ |
7065 | #define CAN_F7R1_FB6_Pos (6U) |
| 7066 | #define CAN_F7R1_FB6_Pos (6U) |
7066 | #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ |
| 7067 | #define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */ |
7067 | #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */ |
| 7068 | #define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!< Filter bit 6 */ |
7068 | #define CAN_F7R1_FB7_Pos (7U) |
| 7069 | #define CAN_F7R1_FB7_Pos (7U) |
7069 | #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ |
| 7070 | #define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */ |
7070 | #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */ |
| 7071 | #define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!< Filter bit 7 */ |
7071 | #define CAN_F7R1_FB8_Pos (8U) |
| 7072 | #define CAN_F7R1_FB8_Pos (8U) |
7072 | #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ |
| 7073 | #define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */ |
7073 | #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */ |
| 7074 | #define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!< Filter bit 8 */ |
7074 | #define CAN_F7R1_FB9_Pos (9U) |
| 7075 | #define CAN_F7R1_FB9_Pos (9U) |
7075 | #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ |
| 7076 | #define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */ |
7076 | #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */ |
| 7077 | #define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!< Filter bit 9 */ |
7077 | #define CAN_F7R1_FB10_Pos (10U) |
| 7078 | #define CAN_F7R1_FB10_Pos (10U) |
7078 | #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ |
| 7079 | #define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */ |
7079 | #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */ |
| 7080 | #define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!< Filter bit 10 */ |
7080 | #define CAN_F7R1_FB11_Pos (11U) |
| 7081 | #define CAN_F7R1_FB11_Pos (11U) |
7081 | #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ |
| 7082 | #define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */ |
7082 | #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */ |
| 7083 | #define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!< Filter bit 11 */ |
7083 | #define CAN_F7R1_FB12_Pos (12U) |
| 7084 | #define CAN_F7R1_FB12_Pos (12U) |
7084 | #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ |
| 7085 | #define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */ |
7085 | #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */ |
| 7086 | #define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!< Filter bit 12 */ |
7086 | #define CAN_F7R1_FB13_Pos (13U) |
| 7087 | #define CAN_F7R1_FB13_Pos (13U) |
7087 | #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ |
| 7088 | #define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */ |
7088 | #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */ |
| 7089 | #define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!< Filter bit 13 */ |
7089 | #define CAN_F7R1_FB14_Pos (14U) |
| 7090 | #define CAN_F7R1_FB14_Pos (14U) |
7090 | #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ |
| 7091 | #define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */ |
7091 | #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */ |
| 7092 | #define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!< Filter bit 14 */ |
7092 | #define CAN_F7R1_FB15_Pos (15U) |
| 7093 | #define CAN_F7R1_FB15_Pos (15U) |
7093 | #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ |
| 7094 | #define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */ |
7094 | #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */ |
| 7095 | #define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!< Filter bit 15 */ |
7095 | #define CAN_F7R1_FB16_Pos (16U) |
| 7096 | #define CAN_F7R1_FB16_Pos (16U) |
7096 | #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ |
| 7097 | #define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */ |
7097 | #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */ |
| 7098 | #define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!< Filter bit 16 */ |
7098 | #define CAN_F7R1_FB17_Pos (17U) |
| 7099 | #define CAN_F7R1_FB17_Pos (17U) |
7099 | #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ |
| 7100 | #define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */ |
7100 | #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */ |
| 7101 | #define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!< Filter bit 17 */ |
7101 | #define CAN_F7R1_FB18_Pos (18U) |
| 7102 | #define CAN_F7R1_FB18_Pos (18U) |
7102 | #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ |
| 7103 | #define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */ |
7103 | #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */ |
| 7104 | #define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!< Filter bit 18 */ |
7104 | #define CAN_F7R1_FB19_Pos (19U) |
| 7105 | #define CAN_F7R1_FB19_Pos (19U) |
7105 | #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ |
| 7106 | #define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */ |
7106 | #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */ |
| 7107 | #define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!< Filter bit 19 */ |
7107 | #define CAN_F7R1_FB20_Pos (20U) |
| 7108 | #define CAN_F7R1_FB20_Pos (20U) |
7108 | #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ |
| 7109 | #define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */ |
7109 | #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */ |
| 7110 | #define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!< Filter bit 20 */ |
7110 | #define CAN_F7R1_FB21_Pos (21U) |
| 7111 | #define CAN_F7R1_FB21_Pos (21U) |
7111 | #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ |
| 7112 | #define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */ |
7112 | #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */ |
| 7113 | #define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!< Filter bit 21 */ |
7113 | #define CAN_F7R1_FB22_Pos (22U) |
| 7114 | #define CAN_F7R1_FB22_Pos (22U) |
7114 | #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ |
| 7115 | #define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */ |
7115 | #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */ |
| 7116 | #define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!< Filter bit 22 */ |
7116 | #define CAN_F7R1_FB23_Pos (23U) |
| 7117 | #define CAN_F7R1_FB23_Pos (23U) |
7117 | #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ |
| 7118 | #define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */ |
7118 | #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */ |
| 7119 | #define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!< Filter bit 23 */ |
7119 | #define CAN_F7R1_FB24_Pos (24U) |
| 7120 | #define CAN_F7R1_FB24_Pos (24U) |
7120 | #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ |
| 7121 | #define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */ |
7121 | #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */ |
| 7122 | #define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!< Filter bit 24 */ |
7122 | #define CAN_F7R1_FB25_Pos (25U) |
| 7123 | #define CAN_F7R1_FB25_Pos (25U) |
7123 | #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ |
| 7124 | #define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */ |
7124 | #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */ |
| 7125 | #define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!< Filter bit 25 */ |
7125 | #define CAN_F7R1_FB26_Pos (26U) |
| 7126 | #define CAN_F7R1_FB26_Pos (26U) |
7126 | #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ |
| 7127 | #define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */ |
7127 | #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */ |
| 7128 | #define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!< Filter bit 26 */ |
7128 | #define CAN_F7R1_FB27_Pos (27U) |
| 7129 | #define CAN_F7R1_FB27_Pos (27U) |
7129 | #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ |
| 7130 | #define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */ |
7130 | #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */ |
| 7131 | #define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!< Filter bit 27 */ |
7131 | #define CAN_F7R1_FB28_Pos (28U) |
| 7132 | #define CAN_F7R1_FB28_Pos (28U) |
7132 | #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ |
| 7133 | #define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */ |
7133 | #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */ |
| 7134 | #define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!< Filter bit 28 */ |
7134 | #define CAN_F7R1_FB29_Pos (29U) |
| 7135 | #define CAN_F7R1_FB29_Pos (29U) |
7135 | #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ |
| 7136 | #define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */ |
7136 | #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */ |
| 7137 | #define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!< Filter bit 29 */ |
7137 | #define CAN_F7R1_FB30_Pos (30U) |
| 7138 | #define CAN_F7R1_FB30_Pos (30U) |
7138 | #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ |
| 7139 | #define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */ |
7139 | #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */ |
| 7140 | #define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!< Filter bit 30 */ |
7140 | #define CAN_F7R1_FB31_Pos (31U) |
| 7141 | #define CAN_F7R1_FB31_Pos (31U) |
7141 | #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ |
| 7142 | #define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */ |
7142 | #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */ |
| 7143 | #define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!< Filter bit 31 */ |
7143 | |
| 7144 | 7144 | /******************* Bit definition for CAN_F8R1 register *******************/ |
|
| 7145 | /******************* Bit definition for CAN_F8R1 register *******************/ |
7145 | #define CAN_F8R1_FB0_Pos (0U) |
| 7146 | #define CAN_F8R1_FB0_Pos (0U) |
7146 | #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ |
| 7147 | #define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */ |
7147 | #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */ |
| 7148 | #define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!< Filter bit 0 */ |
7148 | #define CAN_F8R1_FB1_Pos (1U) |
| 7149 | #define CAN_F8R1_FB1_Pos (1U) |
7149 | #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ |
| 7150 | #define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */ |
7150 | #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */ |
| 7151 | #define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!< Filter bit 1 */ |
7151 | #define CAN_F8R1_FB2_Pos (2U) |
| 7152 | #define CAN_F8R1_FB2_Pos (2U) |
7152 | #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ |
| 7153 | #define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */ |
7153 | #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */ |
| 7154 | #define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!< Filter bit 2 */ |
7154 | #define CAN_F8R1_FB3_Pos (3U) |
| 7155 | #define CAN_F8R1_FB3_Pos (3U) |
7155 | #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ |
| 7156 | #define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */ |
7156 | #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */ |
| 7157 | #define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!< Filter bit 3 */ |
7157 | #define CAN_F8R1_FB4_Pos (4U) |
| 7158 | #define CAN_F8R1_FB4_Pos (4U) |
7158 | #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ |
| 7159 | #define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */ |
7159 | #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */ |
| 7160 | #define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!< Filter bit 4 */ |
7160 | #define CAN_F8R1_FB5_Pos (5U) |
| 7161 | #define CAN_F8R1_FB5_Pos (5U) |
7161 | #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ |
| 7162 | #define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */ |
7162 | #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */ |
| 7163 | #define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!< Filter bit 5 */ |
7163 | #define CAN_F8R1_FB6_Pos (6U) |
| 7164 | #define CAN_F8R1_FB6_Pos (6U) |
7164 | #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ |
| 7165 | #define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */ |
7165 | #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */ |
| 7166 | #define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!< Filter bit 6 */ |
7166 | #define CAN_F8R1_FB7_Pos (7U) |
| 7167 | #define CAN_F8R1_FB7_Pos (7U) |
7167 | #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ |
| 7168 | #define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */ |
7168 | #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */ |
| 7169 | #define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!< Filter bit 7 */ |
7169 | #define CAN_F8R1_FB8_Pos (8U) |
| 7170 | #define CAN_F8R1_FB8_Pos (8U) |
7170 | #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ |
| 7171 | #define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */ |
7171 | #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */ |
| 7172 | #define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!< Filter bit 8 */ |
7172 | #define CAN_F8R1_FB9_Pos (9U) |
| 7173 | #define CAN_F8R1_FB9_Pos (9U) |
7173 | #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ |
| 7174 | #define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */ |
7174 | #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */ |
| 7175 | #define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!< Filter bit 9 */ |
7175 | #define CAN_F8R1_FB10_Pos (10U) |
| 7176 | #define CAN_F8R1_FB10_Pos (10U) |
7176 | #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ |
| 7177 | #define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */ |
7177 | #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */ |
| 7178 | #define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!< Filter bit 10 */ |
7178 | #define CAN_F8R1_FB11_Pos (11U) |
| 7179 | #define CAN_F8R1_FB11_Pos (11U) |
7179 | #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ |
| 7180 | #define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */ |
7180 | #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */ |
| 7181 | #define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!< Filter bit 11 */ |
7181 | #define CAN_F8R1_FB12_Pos (12U) |
| 7182 | #define CAN_F8R1_FB12_Pos (12U) |
7182 | #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ |
| 7183 | #define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */ |
7183 | #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */ |
| 7184 | #define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!< Filter bit 12 */ |
7184 | #define CAN_F8R1_FB13_Pos (13U) |
| 7185 | #define CAN_F8R1_FB13_Pos (13U) |
7185 | #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ |
| 7186 | #define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */ |
7186 | #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */ |
| 7187 | #define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!< Filter bit 13 */ |
7187 | #define CAN_F8R1_FB14_Pos (14U) |
| 7188 | #define CAN_F8R1_FB14_Pos (14U) |
7188 | #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ |
| 7189 | #define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */ |
7189 | #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */ |
| 7190 | #define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!< Filter bit 14 */ |
7190 | #define CAN_F8R1_FB15_Pos (15U) |
| 7191 | #define CAN_F8R1_FB15_Pos (15U) |
7191 | #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ |
| 7192 | #define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */ |
7192 | #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */ |
| 7193 | #define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!< Filter bit 15 */ |
7193 | #define CAN_F8R1_FB16_Pos (16U) |
| 7194 | #define CAN_F8R1_FB16_Pos (16U) |
7194 | #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ |
| 7195 | #define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */ |
7195 | #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */ |
| 7196 | #define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!< Filter bit 16 */ |
7196 | #define CAN_F8R1_FB17_Pos (17U) |
| 7197 | #define CAN_F8R1_FB17_Pos (17U) |
7197 | #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ |
| 7198 | #define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */ |
7198 | #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */ |
| 7199 | #define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!< Filter bit 17 */ |
7199 | #define CAN_F8R1_FB18_Pos (18U) |
| 7200 | #define CAN_F8R1_FB18_Pos (18U) |
7200 | #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ |
| 7201 | #define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */ |
7201 | #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */ |
| 7202 | #define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!< Filter bit 18 */ |
7202 | #define CAN_F8R1_FB19_Pos (19U) |
| 7203 | #define CAN_F8R1_FB19_Pos (19U) |
7203 | #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ |
| 7204 | #define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */ |
7204 | #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */ |
| 7205 | #define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!< Filter bit 19 */ |
7205 | #define CAN_F8R1_FB20_Pos (20U) |
| 7206 | #define CAN_F8R1_FB20_Pos (20U) |
7206 | #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ |
| 7207 | #define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */ |
7207 | #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */ |
| 7208 | #define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!< Filter bit 20 */ |
7208 | #define CAN_F8R1_FB21_Pos (21U) |
| 7209 | #define CAN_F8R1_FB21_Pos (21U) |
7209 | #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ |
| 7210 | #define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */ |
7210 | #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */ |
| 7211 | #define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!< Filter bit 21 */ |
7211 | #define CAN_F8R1_FB22_Pos (22U) |
| 7212 | #define CAN_F8R1_FB22_Pos (22U) |
7212 | #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ |
| 7213 | #define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */ |
7213 | #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */ |
| 7214 | #define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!< Filter bit 22 */ |
7214 | #define CAN_F8R1_FB23_Pos (23U) |
| 7215 | #define CAN_F8R1_FB23_Pos (23U) |
7215 | #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ |
| 7216 | #define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */ |
7216 | #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */ |
| 7217 | #define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!< Filter bit 23 */ |
7217 | #define CAN_F8R1_FB24_Pos (24U) |
| 7218 | #define CAN_F8R1_FB24_Pos (24U) |
7218 | #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ |
| 7219 | #define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */ |
7219 | #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */ |
| 7220 | #define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!< Filter bit 24 */ |
7220 | #define CAN_F8R1_FB25_Pos (25U) |
| 7221 | #define CAN_F8R1_FB25_Pos (25U) |
7221 | #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ |
| 7222 | #define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */ |
7222 | #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */ |
| 7223 | #define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!< Filter bit 25 */ |
7223 | #define CAN_F8R1_FB26_Pos (26U) |
| 7224 | #define CAN_F8R1_FB26_Pos (26U) |
7224 | #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ |
| 7225 | #define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */ |
7225 | #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */ |
| 7226 | #define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!< Filter bit 26 */ |
7226 | #define CAN_F8R1_FB27_Pos (27U) |
| 7227 | #define CAN_F8R1_FB27_Pos (27U) |
7227 | #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ |
| 7228 | #define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */ |
7228 | #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */ |
| 7229 | #define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!< Filter bit 27 */ |
7229 | #define CAN_F8R1_FB28_Pos (28U) |
| 7230 | #define CAN_F8R1_FB28_Pos (28U) |
7230 | #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ |
| 7231 | #define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */ |
7231 | #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */ |
| 7232 | #define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!< Filter bit 28 */ |
7232 | #define CAN_F8R1_FB29_Pos (29U) |
| 7233 | #define CAN_F8R1_FB29_Pos (29U) |
7233 | #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ |
| 7234 | #define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */ |
7234 | #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */ |
| 7235 | #define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!< Filter bit 29 */ |
7235 | #define CAN_F8R1_FB30_Pos (30U) |
| 7236 | #define CAN_F8R1_FB30_Pos (30U) |
7236 | #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ |
| 7237 | #define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */ |
7237 | #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */ |
| 7238 | #define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!< Filter bit 30 */ |
7238 | #define CAN_F8R1_FB31_Pos (31U) |
| 7239 | #define CAN_F8R1_FB31_Pos (31U) |
7239 | #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ |
| 7240 | #define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */ |
7240 | #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */ |
| 7241 | #define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!< Filter bit 31 */ |
7241 | |
| 7242 | 7242 | /******************* Bit definition for CAN_F9R1 register *******************/ |
|
| 7243 | /******************* Bit definition for CAN_F9R1 register *******************/ |
7243 | #define CAN_F9R1_FB0_Pos (0U) |
| 7244 | #define CAN_F9R1_FB0_Pos (0U) |
7244 | #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ |
| 7245 | #define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */ |
7245 | #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */ |
| 7246 | #define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!< Filter bit 0 */ |
7246 | #define CAN_F9R1_FB1_Pos (1U) |
| 7247 | #define CAN_F9R1_FB1_Pos (1U) |
7247 | #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ |
| 7248 | #define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */ |
7248 | #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */ |
| 7249 | #define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!< Filter bit 1 */ |
7249 | #define CAN_F9R1_FB2_Pos (2U) |
| 7250 | #define CAN_F9R1_FB2_Pos (2U) |
7250 | #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ |
| 7251 | #define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */ |
7251 | #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */ |
| 7252 | #define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!< Filter bit 2 */ |
7252 | #define CAN_F9R1_FB3_Pos (3U) |
| 7253 | #define CAN_F9R1_FB3_Pos (3U) |
7253 | #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ |
| 7254 | #define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */ |
7254 | #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */ |
| 7255 | #define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!< Filter bit 3 */ |
7255 | #define CAN_F9R1_FB4_Pos (4U) |
| 7256 | #define CAN_F9R1_FB4_Pos (4U) |
7256 | #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ |
| 7257 | #define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */ |
7257 | #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */ |
| 7258 | #define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!< Filter bit 4 */ |
7258 | #define CAN_F9R1_FB5_Pos (5U) |
| 7259 | #define CAN_F9R1_FB5_Pos (5U) |
7259 | #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ |
| 7260 | #define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */ |
7260 | #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */ |
| 7261 | #define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!< Filter bit 5 */ |
7261 | #define CAN_F9R1_FB6_Pos (6U) |
| 7262 | #define CAN_F9R1_FB6_Pos (6U) |
7262 | #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ |
| 7263 | #define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */ |
7263 | #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */ |
| 7264 | #define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!< Filter bit 6 */ |
7264 | #define CAN_F9R1_FB7_Pos (7U) |
| 7265 | #define CAN_F9R1_FB7_Pos (7U) |
7265 | #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ |
| 7266 | #define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */ |
7266 | #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */ |
| 7267 | #define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!< Filter bit 7 */ |
7267 | #define CAN_F9R1_FB8_Pos (8U) |
| 7268 | #define CAN_F9R1_FB8_Pos (8U) |
7268 | #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ |
| 7269 | #define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */ |
7269 | #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */ |
| 7270 | #define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!< Filter bit 8 */ |
7270 | #define CAN_F9R1_FB9_Pos (9U) |
| 7271 | #define CAN_F9R1_FB9_Pos (9U) |
7271 | #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ |
| 7272 | #define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */ |
7272 | #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */ |
| 7273 | #define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!< Filter bit 9 */ |
7273 | #define CAN_F9R1_FB10_Pos (10U) |
| 7274 | #define CAN_F9R1_FB10_Pos (10U) |
7274 | #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ |
| 7275 | #define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */ |
7275 | #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */ |
| 7276 | #define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!< Filter bit 10 */ |
7276 | #define CAN_F9R1_FB11_Pos (11U) |
| 7277 | #define CAN_F9R1_FB11_Pos (11U) |
7277 | #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ |
| 7278 | #define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */ |
7278 | #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */ |
| 7279 | #define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!< Filter bit 11 */ |
7279 | #define CAN_F9R1_FB12_Pos (12U) |
| 7280 | #define CAN_F9R1_FB12_Pos (12U) |
7280 | #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ |
| 7281 | #define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */ |
7281 | #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */ |
| 7282 | #define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!< Filter bit 12 */ |
7282 | #define CAN_F9R1_FB13_Pos (13U) |
| 7283 | #define CAN_F9R1_FB13_Pos (13U) |
7283 | #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ |
| 7284 | #define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */ |
7284 | #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */ |
| 7285 | #define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!< Filter bit 13 */ |
7285 | #define CAN_F9R1_FB14_Pos (14U) |
| 7286 | #define CAN_F9R1_FB14_Pos (14U) |
7286 | #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ |
| 7287 | #define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */ |
7287 | #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */ |
| 7288 | #define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!< Filter bit 14 */ |
7288 | #define CAN_F9R1_FB15_Pos (15U) |
| 7289 | #define CAN_F9R1_FB15_Pos (15U) |
7289 | #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ |
| 7290 | #define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */ |
7290 | #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */ |
| 7291 | #define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!< Filter bit 15 */ |
7291 | #define CAN_F9R1_FB16_Pos (16U) |
| 7292 | #define CAN_F9R1_FB16_Pos (16U) |
7292 | #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ |
| 7293 | #define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */ |
7293 | #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */ |
| 7294 | #define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!< Filter bit 16 */ |
7294 | #define CAN_F9R1_FB17_Pos (17U) |
| 7295 | #define CAN_F9R1_FB17_Pos (17U) |
7295 | #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ |
| 7296 | #define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */ |
7296 | #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */ |
| 7297 | #define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!< Filter bit 17 */ |
7297 | #define CAN_F9R1_FB18_Pos (18U) |
| 7298 | #define CAN_F9R1_FB18_Pos (18U) |
7298 | #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ |
| 7299 | #define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */ |
7299 | #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */ |
| 7300 | #define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!< Filter bit 18 */ |
7300 | #define CAN_F9R1_FB19_Pos (19U) |
| 7301 | #define CAN_F9R1_FB19_Pos (19U) |
7301 | #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ |
| 7302 | #define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */ |
7302 | #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */ |
| 7303 | #define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!< Filter bit 19 */ |
7303 | #define CAN_F9R1_FB20_Pos (20U) |
| 7304 | #define CAN_F9R1_FB20_Pos (20U) |
7304 | #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ |
| 7305 | #define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */ |
7305 | #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */ |
| 7306 | #define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!< Filter bit 20 */ |
7306 | #define CAN_F9R1_FB21_Pos (21U) |
| 7307 | #define CAN_F9R1_FB21_Pos (21U) |
7307 | #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ |
| 7308 | #define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */ |
7308 | #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */ |
| 7309 | #define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!< Filter bit 21 */ |
7309 | #define CAN_F9R1_FB22_Pos (22U) |
| 7310 | #define CAN_F9R1_FB22_Pos (22U) |
7310 | #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ |
| 7311 | #define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */ |
7311 | #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */ |
| 7312 | #define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!< Filter bit 22 */ |
7312 | #define CAN_F9R1_FB23_Pos (23U) |
| 7313 | #define CAN_F9R1_FB23_Pos (23U) |
7313 | #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ |
| 7314 | #define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */ |
7314 | #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */ |
| 7315 | #define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!< Filter bit 23 */ |
7315 | #define CAN_F9R1_FB24_Pos (24U) |
| 7316 | #define CAN_F9R1_FB24_Pos (24U) |
7316 | #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ |
| 7317 | #define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */ |
7317 | #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */ |
| 7318 | #define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!< Filter bit 24 */ |
7318 | #define CAN_F9R1_FB25_Pos (25U) |
| 7319 | #define CAN_F9R1_FB25_Pos (25U) |
7319 | #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ |
| 7320 | #define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */ |
7320 | #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */ |
| 7321 | #define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!< Filter bit 25 */ |
7321 | #define CAN_F9R1_FB26_Pos (26U) |
| 7322 | #define CAN_F9R1_FB26_Pos (26U) |
7322 | #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ |
| 7323 | #define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */ |
7323 | #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */ |
| 7324 | #define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!< Filter bit 26 */ |
7324 | #define CAN_F9R1_FB27_Pos (27U) |
| 7325 | #define CAN_F9R1_FB27_Pos (27U) |
7325 | #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ |
| 7326 | #define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */ |
7326 | #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */ |
| 7327 | #define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!< Filter bit 27 */ |
7327 | #define CAN_F9R1_FB28_Pos (28U) |
| 7328 | #define CAN_F9R1_FB28_Pos (28U) |
7328 | #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ |
| 7329 | #define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */ |
7329 | #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */ |
| 7330 | #define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!< Filter bit 28 */ |
7330 | #define CAN_F9R1_FB29_Pos (29U) |
| 7331 | #define CAN_F9R1_FB29_Pos (29U) |
7331 | #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ |
| 7332 | #define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */ |
7332 | #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */ |
| 7333 | #define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!< Filter bit 29 */ |
7333 | #define CAN_F9R1_FB30_Pos (30U) |
| 7334 | #define CAN_F9R1_FB30_Pos (30U) |
7334 | #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ |
| 7335 | #define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */ |
7335 | #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */ |
| 7336 | #define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!< Filter bit 30 */ |
7336 | #define CAN_F9R1_FB31_Pos (31U) |
| 7337 | #define CAN_F9R1_FB31_Pos (31U) |
7337 | #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ |
| 7338 | #define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */ |
7338 | #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */ |
| 7339 | #define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!< Filter bit 31 */ |
7339 | |
| 7340 | 7340 | /******************* Bit definition for CAN_F10R1 register ******************/ |
|
| 7341 | /******************* Bit definition for CAN_F10R1 register ******************/ |
7341 | #define CAN_F10R1_FB0_Pos (0U) |
| 7342 | #define CAN_F10R1_FB0_Pos (0U) |
7342 | #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ |
| 7343 | #define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */ |
7343 | #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */ |
| 7344 | #define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!< Filter bit 0 */ |
7344 | #define CAN_F10R1_FB1_Pos (1U) |
| 7345 | #define CAN_F10R1_FB1_Pos (1U) |
7345 | #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ |
| 7346 | #define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */ |
7346 | #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */ |
| 7347 | #define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!< Filter bit 1 */ |
7347 | #define CAN_F10R1_FB2_Pos (2U) |
| 7348 | #define CAN_F10R1_FB2_Pos (2U) |
7348 | #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ |
| 7349 | #define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */ |
7349 | #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */ |
| 7350 | #define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!< Filter bit 2 */ |
7350 | #define CAN_F10R1_FB3_Pos (3U) |
| 7351 | #define CAN_F10R1_FB3_Pos (3U) |
7351 | #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ |
| 7352 | #define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */ |
7352 | #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */ |
| 7353 | #define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!< Filter bit 3 */ |
7353 | #define CAN_F10R1_FB4_Pos (4U) |
| 7354 | #define CAN_F10R1_FB4_Pos (4U) |
7354 | #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ |
| 7355 | #define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */ |
7355 | #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */ |
| 7356 | #define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!< Filter bit 4 */ |
7356 | #define CAN_F10R1_FB5_Pos (5U) |
| 7357 | #define CAN_F10R1_FB5_Pos (5U) |
7357 | #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ |
| 7358 | #define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */ |
7358 | #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */ |
| 7359 | #define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!< Filter bit 5 */ |
7359 | #define CAN_F10R1_FB6_Pos (6U) |
| 7360 | #define CAN_F10R1_FB6_Pos (6U) |
7360 | #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ |
| 7361 | #define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */ |
7361 | #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */ |
| 7362 | #define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!< Filter bit 6 */ |
7362 | #define CAN_F10R1_FB7_Pos (7U) |
| 7363 | #define CAN_F10R1_FB7_Pos (7U) |
7363 | #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ |
| 7364 | #define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */ |
7364 | #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */ |
| 7365 | #define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!< Filter bit 7 */ |
7365 | #define CAN_F10R1_FB8_Pos (8U) |
| 7366 | #define CAN_F10R1_FB8_Pos (8U) |
7366 | #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ |
| 7367 | #define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */ |
7367 | #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */ |
| 7368 | #define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!< Filter bit 8 */ |
7368 | #define CAN_F10R1_FB9_Pos (9U) |
| 7369 | #define CAN_F10R1_FB9_Pos (9U) |
7369 | #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ |
| 7370 | #define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */ |
7370 | #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */ |
| 7371 | #define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!< Filter bit 9 */ |
7371 | #define CAN_F10R1_FB10_Pos (10U) |
| 7372 | #define CAN_F10R1_FB10_Pos (10U) |
7372 | #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ |
| 7373 | #define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */ |
7373 | #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */ |
| 7374 | #define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!< Filter bit 10 */ |
7374 | #define CAN_F10R1_FB11_Pos (11U) |
| 7375 | #define CAN_F10R1_FB11_Pos (11U) |
7375 | #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ |
| 7376 | #define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */ |
7376 | #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */ |
| 7377 | #define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!< Filter bit 11 */ |
7377 | #define CAN_F10R1_FB12_Pos (12U) |
| 7378 | #define CAN_F10R1_FB12_Pos (12U) |
7378 | #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ |
| 7379 | #define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */ |
7379 | #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */ |
| 7380 | #define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!< Filter bit 12 */ |
7380 | #define CAN_F10R1_FB13_Pos (13U) |
| 7381 | #define CAN_F10R1_FB13_Pos (13U) |
7381 | #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ |
| 7382 | #define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */ |
7382 | #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */ |
| 7383 | #define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!< Filter bit 13 */ |
7383 | #define CAN_F10R1_FB14_Pos (14U) |
| 7384 | #define CAN_F10R1_FB14_Pos (14U) |
7384 | #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ |
| 7385 | #define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */ |
7385 | #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */ |
| 7386 | #define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!< Filter bit 14 */ |
7386 | #define CAN_F10R1_FB15_Pos (15U) |
| 7387 | #define CAN_F10R1_FB15_Pos (15U) |
7387 | #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ |
| 7388 | #define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */ |
7388 | #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */ |
| 7389 | #define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!< Filter bit 15 */ |
7389 | #define CAN_F10R1_FB16_Pos (16U) |
| 7390 | #define CAN_F10R1_FB16_Pos (16U) |
7390 | #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ |
| 7391 | #define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */ |
7391 | #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */ |
| 7392 | #define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!< Filter bit 16 */ |
7392 | #define CAN_F10R1_FB17_Pos (17U) |
| 7393 | #define CAN_F10R1_FB17_Pos (17U) |
7393 | #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ |
| 7394 | #define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */ |
7394 | #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */ |
| 7395 | #define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!< Filter bit 17 */ |
7395 | #define CAN_F10R1_FB18_Pos (18U) |
| 7396 | #define CAN_F10R1_FB18_Pos (18U) |
7396 | #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ |
| 7397 | #define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */ |
7397 | #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */ |
| 7398 | #define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!< Filter bit 18 */ |
7398 | #define CAN_F10R1_FB19_Pos (19U) |
| 7399 | #define CAN_F10R1_FB19_Pos (19U) |
7399 | #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ |
| 7400 | #define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */ |
7400 | #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */ |
| 7401 | #define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!< Filter bit 19 */ |
7401 | #define CAN_F10R1_FB20_Pos (20U) |
| 7402 | #define CAN_F10R1_FB20_Pos (20U) |
7402 | #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ |
| 7403 | #define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */ |
7403 | #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */ |
| 7404 | #define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!< Filter bit 20 */ |
7404 | #define CAN_F10R1_FB21_Pos (21U) |
| 7405 | #define CAN_F10R1_FB21_Pos (21U) |
7405 | #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ |
| 7406 | #define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */ |
7406 | #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */ |
| 7407 | #define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!< Filter bit 21 */ |
7407 | #define CAN_F10R1_FB22_Pos (22U) |
| 7408 | #define CAN_F10R1_FB22_Pos (22U) |
7408 | #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ |
| 7409 | #define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */ |
7409 | #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */ |
| 7410 | #define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!< Filter bit 22 */ |
7410 | #define CAN_F10R1_FB23_Pos (23U) |
| 7411 | #define CAN_F10R1_FB23_Pos (23U) |
7411 | #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ |
| 7412 | #define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */ |
7412 | #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */ |
| 7413 | #define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!< Filter bit 23 */ |
7413 | #define CAN_F10R1_FB24_Pos (24U) |
| 7414 | #define CAN_F10R1_FB24_Pos (24U) |
7414 | #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ |
| 7415 | #define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */ |
7415 | #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */ |
| 7416 | #define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!< Filter bit 24 */ |
7416 | #define CAN_F10R1_FB25_Pos (25U) |
| 7417 | #define CAN_F10R1_FB25_Pos (25U) |
7417 | #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ |
| 7418 | #define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */ |
7418 | #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */ |
| 7419 | #define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!< Filter bit 25 */ |
7419 | #define CAN_F10R1_FB26_Pos (26U) |
| 7420 | #define CAN_F10R1_FB26_Pos (26U) |
7420 | #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ |
| 7421 | #define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */ |
7421 | #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */ |
| 7422 | #define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!< Filter bit 26 */ |
7422 | #define CAN_F10R1_FB27_Pos (27U) |
| 7423 | #define CAN_F10R1_FB27_Pos (27U) |
7423 | #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ |
| 7424 | #define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */ |
7424 | #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */ |
| 7425 | #define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!< Filter bit 27 */ |
7425 | #define CAN_F10R1_FB28_Pos (28U) |
| 7426 | #define CAN_F10R1_FB28_Pos (28U) |
7426 | #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ |
| 7427 | #define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */ |
7427 | #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */ |
| 7428 | #define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!< Filter bit 28 */ |
7428 | #define CAN_F10R1_FB29_Pos (29U) |
| 7429 | #define CAN_F10R1_FB29_Pos (29U) |
7429 | #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ |
| 7430 | #define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */ |
7430 | #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */ |
| 7431 | #define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!< Filter bit 29 */ |
7431 | #define CAN_F10R1_FB30_Pos (30U) |
| 7432 | #define CAN_F10R1_FB30_Pos (30U) |
7432 | #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ |
| 7433 | #define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */ |
7433 | #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */ |
| 7434 | #define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!< Filter bit 30 */ |
7434 | #define CAN_F10R1_FB31_Pos (31U) |
| 7435 | #define CAN_F10R1_FB31_Pos (31U) |
7435 | #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ |
| 7436 | #define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */ |
7436 | #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */ |
| 7437 | #define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!< Filter bit 31 */ |
7437 | |
| 7438 | 7438 | /******************* Bit definition for CAN_F11R1 register ******************/ |
|
| 7439 | /******************* Bit definition for CAN_F11R1 register ******************/ |
7439 | #define CAN_F11R1_FB0_Pos (0U) |
| 7440 | #define CAN_F11R1_FB0_Pos (0U) |
7440 | #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ |
| 7441 | #define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */ |
7441 | #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */ |
| 7442 | #define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!< Filter bit 0 */ |
7442 | #define CAN_F11R1_FB1_Pos (1U) |
| 7443 | #define CAN_F11R1_FB1_Pos (1U) |
7443 | #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ |
| 7444 | #define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */ |
7444 | #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */ |
| 7445 | #define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!< Filter bit 1 */ |
7445 | #define CAN_F11R1_FB2_Pos (2U) |
| 7446 | #define CAN_F11R1_FB2_Pos (2U) |
7446 | #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ |
| 7447 | #define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */ |
7447 | #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */ |
| 7448 | #define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!< Filter bit 2 */ |
7448 | #define CAN_F11R1_FB3_Pos (3U) |
| 7449 | #define CAN_F11R1_FB3_Pos (3U) |
7449 | #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ |
| 7450 | #define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */ |
7450 | #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */ |
| 7451 | #define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!< Filter bit 3 */ |
7451 | #define CAN_F11R1_FB4_Pos (4U) |
| 7452 | #define CAN_F11R1_FB4_Pos (4U) |
7452 | #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ |
| 7453 | #define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */ |
7453 | #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */ |
| 7454 | #define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!< Filter bit 4 */ |
7454 | #define CAN_F11R1_FB5_Pos (5U) |
| 7455 | #define CAN_F11R1_FB5_Pos (5U) |
7455 | #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ |
| 7456 | #define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */ |
7456 | #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */ |
| 7457 | #define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!< Filter bit 5 */ |
7457 | #define CAN_F11R1_FB6_Pos (6U) |
| 7458 | #define CAN_F11R1_FB6_Pos (6U) |
7458 | #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ |
| 7459 | #define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */ |
7459 | #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */ |
| 7460 | #define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!< Filter bit 6 */ |
7460 | #define CAN_F11R1_FB7_Pos (7U) |
| 7461 | #define CAN_F11R1_FB7_Pos (7U) |
7461 | #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ |
| 7462 | #define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */ |
7462 | #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */ |
| 7463 | #define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!< Filter bit 7 */ |
7463 | #define CAN_F11R1_FB8_Pos (8U) |
| 7464 | #define CAN_F11R1_FB8_Pos (8U) |
7464 | #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ |
| 7465 | #define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */ |
7465 | #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */ |
| 7466 | #define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!< Filter bit 8 */ |
7466 | #define CAN_F11R1_FB9_Pos (9U) |
| 7467 | #define CAN_F11R1_FB9_Pos (9U) |
7467 | #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ |
| 7468 | #define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */ |
7468 | #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */ |
| 7469 | #define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!< Filter bit 9 */ |
7469 | #define CAN_F11R1_FB10_Pos (10U) |
| 7470 | #define CAN_F11R1_FB10_Pos (10U) |
7470 | #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ |
| 7471 | #define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */ |
7471 | #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */ |
| 7472 | #define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!< Filter bit 10 */ |
7472 | #define CAN_F11R1_FB11_Pos (11U) |
| 7473 | #define CAN_F11R1_FB11_Pos (11U) |
7473 | #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ |
| 7474 | #define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */ |
7474 | #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */ |
| 7475 | #define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!< Filter bit 11 */ |
7475 | #define CAN_F11R1_FB12_Pos (12U) |
| 7476 | #define CAN_F11R1_FB12_Pos (12U) |
7476 | #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ |
| 7477 | #define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */ |
7477 | #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */ |
| 7478 | #define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!< Filter bit 12 */ |
7478 | #define CAN_F11R1_FB13_Pos (13U) |
| 7479 | #define CAN_F11R1_FB13_Pos (13U) |
7479 | #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ |
| 7480 | #define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */ |
7480 | #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */ |
| 7481 | #define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!< Filter bit 13 */ |
7481 | #define CAN_F11R1_FB14_Pos (14U) |
| 7482 | #define CAN_F11R1_FB14_Pos (14U) |
7482 | #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ |
| 7483 | #define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */ |
7483 | #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */ |
| 7484 | #define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!< Filter bit 14 */ |
7484 | #define CAN_F11R1_FB15_Pos (15U) |
| 7485 | #define CAN_F11R1_FB15_Pos (15U) |
7485 | #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ |
| 7486 | #define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */ |
7486 | #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */ |
| 7487 | #define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!< Filter bit 15 */ |
7487 | #define CAN_F11R1_FB16_Pos (16U) |
| 7488 | #define CAN_F11R1_FB16_Pos (16U) |
7488 | #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ |
| 7489 | #define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */ |
7489 | #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */ |
| 7490 | #define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!< Filter bit 16 */ |
7490 | #define CAN_F11R1_FB17_Pos (17U) |
| 7491 | #define CAN_F11R1_FB17_Pos (17U) |
7491 | #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ |
| 7492 | #define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */ |
7492 | #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */ |
| 7493 | #define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!< Filter bit 17 */ |
7493 | #define CAN_F11R1_FB18_Pos (18U) |
| 7494 | #define CAN_F11R1_FB18_Pos (18U) |
7494 | #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ |
| 7495 | #define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */ |
7495 | #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */ |
| 7496 | #define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!< Filter bit 18 */ |
7496 | #define CAN_F11R1_FB19_Pos (19U) |
| 7497 | #define CAN_F11R1_FB19_Pos (19U) |
7497 | #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ |
| 7498 | #define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */ |
7498 | #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */ |
| 7499 | #define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!< Filter bit 19 */ |
7499 | #define CAN_F11R1_FB20_Pos (20U) |
| 7500 | #define CAN_F11R1_FB20_Pos (20U) |
7500 | #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ |
| 7501 | #define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */ |
7501 | #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */ |
| 7502 | #define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!< Filter bit 20 */ |
7502 | #define CAN_F11R1_FB21_Pos (21U) |
| 7503 | #define CAN_F11R1_FB21_Pos (21U) |
7503 | #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ |
| 7504 | #define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */ |
7504 | #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */ |
| 7505 | #define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!< Filter bit 21 */ |
7505 | #define CAN_F11R1_FB22_Pos (22U) |
| 7506 | #define CAN_F11R1_FB22_Pos (22U) |
7506 | #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ |
| 7507 | #define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */ |
7507 | #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */ |
| 7508 | #define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!< Filter bit 22 */ |
7508 | #define CAN_F11R1_FB23_Pos (23U) |
| 7509 | #define CAN_F11R1_FB23_Pos (23U) |
7509 | #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ |
| 7510 | #define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */ |
7510 | #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */ |
| 7511 | #define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!< Filter bit 23 */ |
7511 | #define CAN_F11R1_FB24_Pos (24U) |
| 7512 | #define CAN_F11R1_FB24_Pos (24U) |
7512 | #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ |
| 7513 | #define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */ |
7513 | #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */ |
| 7514 | #define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!< Filter bit 24 */ |
7514 | #define CAN_F11R1_FB25_Pos (25U) |
| 7515 | #define CAN_F11R1_FB25_Pos (25U) |
7515 | #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ |
| 7516 | #define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */ |
7516 | #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */ |
| 7517 | #define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!< Filter bit 25 */ |
7517 | #define CAN_F11R1_FB26_Pos (26U) |
| 7518 | #define CAN_F11R1_FB26_Pos (26U) |
7518 | #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ |
| 7519 | #define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */ |
7519 | #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */ |
| 7520 | #define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!< Filter bit 26 */ |
7520 | #define CAN_F11R1_FB27_Pos (27U) |
| 7521 | #define CAN_F11R1_FB27_Pos (27U) |
7521 | #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ |
| 7522 | #define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */ |
7522 | #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */ |
| 7523 | #define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!< Filter bit 27 */ |
7523 | #define CAN_F11R1_FB28_Pos (28U) |
| 7524 | #define CAN_F11R1_FB28_Pos (28U) |
7524 | #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ |
| 7525 | #define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */ |
7525 | #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */ |
| 7526 | #define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!< Filter bit 28 */ |
7526 | #define CAN_F11R1_FB29_Pos (29U) |
| 7527 | #define CAN_F11R1_FB29_Pos (29U) |
7527 | #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ |
| 7528 | #define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */ |
7528 | #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */ |
| 7529 | #define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!< Filter bit 29 */ |
7529 | #define CAN_F11R1_FB30_Pos (30U) |
| 7530 | #define CAN_F11R1_FB30_Pos (30U) |
7530 | #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ |
| 7531 | #define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */ |
7531 | #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */ |
| 7532 | #define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!< Filter bit 30 */ |
7532 | #define CAN_F11R1_FB31_Pos (31U) |
| 7533 | #define CAN_F11R1_FB31_Pos (31U) |
7533 | #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ |
| 7534 | #define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */ |
7534 | #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */ |
| 7535 | #define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!< Filter bit 31 */ |
7535 | |
| 7536 | 7536 | /******************* Bit definition for CAN_F12R1 register ******************/ |
|
| 7537 | /******************* Bit definition for CAN_F12R1 register ******************/ |
7537 | #define CAN_F12R1_FB0_Pos (0U) |
| 7538 | #define CAN_F12R1_FB0_Pos (0U) |
7538 | #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ |
| 7539 | #define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */ |
7539 | #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */ |
| 7540 | #define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!< Filter bit 0 */ |
7540 | #define CAN_F12R1_FB1_Pos (1U) |
| 7541 | #define CAN_F12R1_FB1_Pos (1U) |
7541 | #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ |
| 7542 | #define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */ |
7542 | #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */ |
| 7543 | #define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!< Filter bit 1 */ |
7543 | #define CAN_F12R1_FB2_Pos (2U) |
| 7544 | #define CAN_F12R1_FB2_Pos (2U) |
7544 | #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ |
| 7545 | #define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */ |
7545 | #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */ |
| 7546 | #define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!< Filter bit 2 */ |
7546 | #define CAN_F12R1_FB3_Pos (3U) |
| 7547 | #define CAN_F12R1_FB3_Pos (3U) |
7547 | #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ |
| 7548 | #define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */ |
7548 | #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */ |
| 7549 | #define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!< Filter bit 3 */ |
7549 | #define CAN_F12R1_FB4_Pos (4U) |
| 7550 | #define CAN_F12R1_FB4_Pos (4U) |
7550 | #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ |
| 7551 | #define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */ |
7551 | #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */ |
| 7552 | #define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!< Filter bit 4 */ |
7552 | #define CAN_F12R1_FB5_Pos (5U) |
| 7553 | #define CAN_F12R1_FB5_Pos (5U) |
7553 | #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ |
| 7554 | #define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */ |
7554 | #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */ |
| 7555 | #define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!< Filter bit 5 */ |
7555 | #define CAN_F12R1_FB6_Pos (6U) |
| 7556 | #define CAN_F12R1_FB6_Pos (6U) |
7556 | #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ |
| 7557 | #define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */ |
7557 | #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */ |
| 7558 | #define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!< Filter bit 6 */ |
7558 | #define CAN_F12R1_FB7_Pos (7U) |
| 7559 | #define CAN_F12R1_FB7_Pos (7U) |
7559 | #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ |
| 7560 | #define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */ |
7560 | #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */ |
| 7561 | #define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!< Filter bit 7 */ |
7561 | #define CAN_F12R1_FB8_Pos (8U) |
| 7562 | #define CAN_F12R1_FB8_Pos (8U) |
7562 | #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ |
| 7563 | #define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */ |
7563 | #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */ |
| 7564 | #define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!< Filter bit 8 */ |
7564 | #define CAN_F12R1_FB9_Pos (9U) |
| 7565 | #define CAN_F12R1_FB9_Pos (9U) |
7565 | #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ |
| 7566 | #define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */ |
7566 | #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */ |
| 7567 | #define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!< Filter bit 9 */ |
7567 | #define CAN_F12R1_FB10_Pos (10U) |
| 7568 | #define CAN_F12R1_FB10_Pos (10U) |
7568 | #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ |
| 7569 | #define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */ |
7569 | #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */ |
| 7570 | #define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!< Filter bit 10 */ |
7570 | #define CAN_F12R1_FB11_Pos (11U) |
| 7571 | #define CAN_F12R1_FB11_Pos (11U) |
7571 | #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ |
| 7572 | #define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */ |
7572 | #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */ |
| 7573 | #define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!< Filter bit 11 */ |
7573 | #define CAN_F12R1_FB12_Pos (12U) |
| 7574 | #define CAN_F12R1_FB12_Pos (12U) |
7574 | #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ |
| 7575 | #define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */ |
7575 | #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */ |
| 7576 | #define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!< Filter bit 12 */ |
7576 | #define CAN_F12R1_FB13_Pos (13U) |
| 7577 | #define CAN_F12R1_FB13_Pos (13U) |
7577 | #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ |
| 7578 | #define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */ |
7578 | #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */ |
| 7579 | #define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!< Filter bit 13 */ |
7579 | #define CAN_F12R1_FB14_Pos (14U) |
| 7580 | #define CAN_F12R1_FB14_Pos (14U) |
7580 | #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ |
| 7581 | #define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */ |
7581 | #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */ |
| 7582 | #define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!< Filter bit 14 */ |
7582 | #define CAN_F12R1_FB15_Pos (15U) |
| 7583 | #define CAN_F12R1_FB15_Pos (15U) |
7583 | #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ |
| 7584 | #define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */ |
7584 | #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */ |
| 7585 | #define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!< Filter bit 15 */ |
7585 | #define CAN_F12R1_FB16_Pos (16U) |
| 7586 | #define CAN_F12R1_FB16_Pos (16U) |
7586 | #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ |
| 7587 | #define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */ |
7587 | #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */ |
| 7588 | #define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!< Filter bit 16 */ |
7588 | #define CAN_F12R1_FB17_Pos (17U) |
| 7589 | #define CAN_F12R1_FB17_Pos (17U) |
7589 | #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ |
| 7590 | #define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */ |
7590 | #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */ |
| 7591 | #define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!< Filter bit 17 */ |
7591 | #define CAN_F12R1_FB18_Pos (18U) |
| 7592 | #define CAN_F12R1_FB18_Pos (18U) |
7592 | #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ |
| 7593 | #define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */ |
7593 | #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */ |
| 7594 | #define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!< Filter bit 18 */ |
7594 | #define CAN_F12R1_FB19_Pos (19U) |
| 7595 | #define CAN_F12R1_FB19_Pos (19U) |
7595 | #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ |
| 7596 | #define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */ |
7596 | #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */ |
| 7597 | #define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!< Filter bit 19 */ |
7597 | #define CAN_F12R1_FB20_Pos (20U) |
| 7598 | #define CAN_F12R1_FB20_Pos (20U) |
7598 | #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ |
| 7599 | #define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */ |
7599 | #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */ |
| 7600 | #define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!< Filter bit 20 */ |
7600 | #define CAN_F12R1_FB21_Pos (21U) |
| 7601 | #define CAN_F12R1_FB21_Pos (21U) |
7601 | #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ |
| 7602 | #define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */ |
7602 | #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */ |
| 7603 | #define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!< Filter bit 21 */ |
7603 | #define CAN_F12R1_FB22_Pos (22U) |
| 7604 | #define CAN_F12R1_FB22_Pos (22U) |
7604 | #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ |
| 7605 | #define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */ |
7605 | #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */ |
| 7606 | #define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!< Filter bit 22 */ |
7606 | #define CAN_F12R1_FB23_Pos (23U) |
| 7607 | #define CAN_F12R1_FB23_Pos (23U) |
7607 | #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ |
| 7608 | #define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */ |
7608 | #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */ |
| 7609 | #define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!< Filter bit 23 */ |
7609 | #define CAN_F12R1_FB24_Pos (24U) |
| 7610 | #define CAN_F12R1_FB24_Pos (24U) |
7610 | #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ |
| 7611 | #define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */ |
7611 | #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */ |
| 7612 | #define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!< Filter bit 24 */ |
7612 | #define CAN_F12R1_FB25_Pos (25U) |
| 7613 | #define CAN_F12R1_FB25_Pos (25U) |
7613 | #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ |
| 7614 | #define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */ |
7614 | #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */ |
| 7615 | #define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!< Filter bit 25 */ |
7615 | #define CAN_F12R1_FB26_Pos (26U) |
| 7616 | #define CAN_F12R1_FB26_Pos (26U) |
7616 | #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ |
| 7617 | #define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */ |
7617 | #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */ |
| 7618 | #define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!< Filter bit 26 */ |
7618 | #define CAN_F12R1_FB27_Pos (27U) |
| 7619 | #define CAN_F12R1_FB27_Pos (27U) |
7619 | #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ |
| 7620 | #define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */ |
7620 | #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */ |
| 7621 | #define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!< Filter bit 27 */ |
7621 | #define CAN_F12R1_FB28_Pos (28U) |
| 7622 | #define CAN_F12R1_FB28_Pos (28U) |
7622 | #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ |
| 7623 | #define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */ |
7623 | #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */ |
| 7624 | #define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!< Filter bit 28 */ |
7624 | #define CAN_F12R1_FB29_Pos (29U) |
| 7625 | #define CAN_F12R1_FB29_Pos (29U) |
7625 | #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ |
| 7626 | #define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */ |
7626 | #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */ |
| 7627 | #define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!< Filter bit 29 */ |
7627 | #define CAN_F12R1_FB30_Pos (30U) |
| 7628 | #define CAN_F12R1_FB30_Pos (30U) |
7628 | #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ |
| 7629 | #define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */ |
7629 | #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */ |
| 7630 | #define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!< Filter bit 30 */ |
7630 | #define CAN_F12R1_FB31_Pos (31U) |
| 7631 | #define CAN_F12R1_FB31_Pos (31U) |
7631 | #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ |
| 7632 | #define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */ |
7632 | #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */ |
| 7633 | #define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!< Filter bit 31 */ |
7633 | |
| 7634 | 7634 | /******************* Bit definition for CAN_F13R1 register ******************/ |
|
| 7635 | /******************* Bit definition for CAN_F13R1 register ******************/ |
7635 | #define CAN_F13R1_FB0_Pos (0U) |
| 7636 | #define CAN_F13R1_FB0_Pos (0U) |
7636 | #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ |
| 7637 | #define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */ |
7637 | #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */ |
| 7638 | #define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!< Filter bit 0 */ |
7638 | #define CAN_F13R1_FB1_Pos (1U) |
| 7639 | #define CAN_F13R1_FB1_Pos (1U) |
7639 | #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ |
| 7640 | #define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */ |
7640 | #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */ |
| 7641 | #define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!< Filter bit 1 */ |
7641 | #define CAN_F13R1_FB2_Pos (2U) |
| 7642 | #define CAN_F13R1_FB2_Pos (2U) |
7642 | #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ |
| 7643 | #define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */ |
7643 | #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */ |
| 7644 | #define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!< Filter bit 2 */ |
7644 | #define CAN_F13R1_FB3_Pos (3U) |
| 7645 | #define CAN_F13R1_FB3_Pos (3U) |
7645 | #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ |
| 7646 | #define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */ |
7646 | #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */ |
| 7647 | #define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!< Filter bit 3 */ |
7647 | #define CAN_F13R1_FB4_Pos (4U) |
| 7648 | #define CAN_F13R1_FB4_Pos (4U) |
7648 | #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ |
| 7649 | #define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */ |
7649 | #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */ |
| 7650 | #define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!< Filter bit 4 */ |
7650 | #define CAN_F13R1_FB5_Pos (5U) |
| 7651 | #define CAN_F13R1_FB5_Pos (5U) |
7651 | #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ |
| 7652 | #define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */ |
7652 | #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */ |
| 7653 | #define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!< Filter bit 5 */ |
7653 | #define CAN_F13R1_FB6_Pos (6U) |
| 7654 | #define CAN_F13R1_FB6_Pos (6U) |
7654 | #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ |
| 7655 | #define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */ |
7655 | #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */ |
| 7656 | #define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!< Filter bit 6 */ |
7656 | #define CAN_F13R1_FB7_Pos (7U) |
| 7657 | #define CAN_F13R1_FB7_Pos (7U) |
7657 | #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ |
| 7658 | #define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */ |
7658 | #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */ |
| 7659 | #define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!< Filter bit 7 */ |
7659 | #define CAN_F13R1_FB8_Pos (8U) |
| 7660 | #define CAN_F13R1_FB8_Pos (8U) |
7660 | #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ |
| 7661 | #define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */ |
7661 | #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */ |
| 7662 | #define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!< Filter bit 8 */ |
7662 | #define CAN_F13R1_FB9_Pos (9U) |
| 7663 | #define CAN_F13R1_FB9_Pos (9U) |
7663 | #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ |
| 7664 | #define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */ |
7664 | #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */ |
| 7665 | #define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!< Filter bit 9 */ |
7665 | #define CAN_F13R1_FB10_Pos (10U) |
| 7666 | #define CAN_F13R1_FB10_Pos (10U) |
7666 | #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ |
| 7667 | #define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */ |
7667 | #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */ |
| 7668 | #define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!< Filter bit 10 */ |
7668 | #define CAN_F13R1_FB11_Pos (11U) |
| 7669 | #define CAN_F13R1_FB11_Pos (11U) |
7669 | #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ |
| 7670 | #define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */ |
7670 | #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */ |
| 7671 | #define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!< Filter bit 11 */ |
7671 | #define CAN_F13R1_FB12_Pos (12U) |
| 7672 | #define CAN_F13R1_FB12_Pos (12U) |
7672 | #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ |
| 7673 | #define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */ |
7673 | #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */ |
| 7674 | #define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!< Filter bit 12 */ |
7674 | #define CAN_F13R1_FB13_Pos (13U) |
| 7675 | #define CAN_F13R1_FB13_Pos (13U) |
7675 | #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ |
| 7676 | #define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */ |
7676 | #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */ |
| 7677 | #define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!< Filter bit 13 */ |
7677 | #define CAN_F13R1_FB14_Pos (14U) |
| 7678 | #define CAN_F13R1_FB14_Pos (14U) |
7678 | #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ |
| 7679 | #define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */ |
7679 | #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */ |
| 7680 | #define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!< Filter bit 14 */ |
7680 | #define CAN_F13R1_FB15_Pos (15U) |
| 7681 | #define CAN_F13R1_FB15_Pos (15U) |
7681 | #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ |
| 7682 | #define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */ |
7682 | #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */ |
| 7683 | #define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!< Filter bit 15 */ |
7683 | #define CAN_F13R1_FB16_Pos (16U) |
| 7684 | #define CAN_F13R1_FB16_Pos (16U) |
7684 | #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ |
| 7685 | #define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */ |
7685 | #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */ |
| 7686 | #define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!< Filter bit 16 */ |
7686 | #define CAN_F13R1_FB17_Pos (17U) |
| 7687 | #define CAN_F13R1_FB17_Pos (17U) |
7687 | #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ |
| 7688 | #define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */ |
7688 | #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */ |
| 7689 | #define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!< Filter bit 17 */ |
7689 | #define CAN_F13R1_FB18_Pos (18U) |
| 7690 | #define CAN_F13R1_FB18_Pos (18U) |
7690 | #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ |
| 7691 | #define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */ |
7691 | #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */ |
| 7692 | #define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!< Filter bit 18 */ |
7692 | #define CAN_F13R1_FB19_Pos (19U) |
| 7693 | #define CAN_F13R1_FB19_Pos (19U) |
7693 | #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ |
| 7694 | #define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */ |
7694 | #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */ |
| 7695 | #define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!< Filter bit 19 */ |
7695 | #define CAN_F13R1_FB20_Pos (20U) |
| 7696 | #define CAN_F13R1_FB20_Pos (20U) |
7696 | #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ |
| 7697 | #define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */ |
7697 | #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */ |
| 7698 | #define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!< Filter bit 20 */ |
7698 | #define CAN_F13R1_FB21_Pos (21U) |
| 7699 | #define CAN_F13R1_FB21_Pos (21U) |
7699 | #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ |
| 7700 | #define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */ |
7700 | #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */ |
| 7701 | #define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!< Filter bit 21 */ |
7701 | #define CAN_F13R1_FB22_Pos (22U) |
| 7702 | #define CAN_F13R1_FB22_Pos (22U) |
7702 | #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ |
| 7703 | #define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */ |
7703 | #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */ |
| 7704 | #define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!< Filter bit 22 */ |
7704 | #define CAN_F13R1_FB23_Pos (23U) |
| 7705 | #define CAN_F13R1_FB23_Pos (23U) |
7705 | #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ |
| 7706 | #define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */ |
7706 | #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */ |
| 7707 | #define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!< Filter bit 23 */ |
7707 | #define CAN_F13R1_FB24_Pos (24U) |
| 7708 | #define CAN_F13R1_FB24_Pos (24U) |
7708 | #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ |
| 7709 | #define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */ |
7709 | #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */ |
| 7710 | #define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!< Filter bit 24 */ |
7710 | #define CAN_F13R1_FB25_Pos (25U) |
| 7711 | #define CAN_F13R1_FB25_Pos (25U) |
7711 | #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ |
| 7712 | #define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */ |
7712 | #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */ |
| 7713 | #define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!< Filter bit 25 */ |
7713 | #define CAN_F13R1_FB26_Pos (26U) |
| 7714 | #define CAN_F13R1_FB26_Pos (26U) |
7714 | #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ |
| 7715 | #define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */ |
7715 | #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */ |
| 7716 | #define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!< Filter bit 26 */ |
7716 | #define CAN_F13R1_FB27_Pos (27U) |
| 7717 | #define CAN_F13R1_FB27_Pos (27U) |
7717 | #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ |
| 7718 | #define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */ |
7718 | #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */ |
| 7719 | #define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!< Filter bit 27 */ |
7719 | #define CAN_F13R1_FB28_Pos (28U) |
| 7720 | #define CAN_F13R1_FB28_Pos (28U) |
7720 | #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ |
| 7721 | #define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */ |
7721 | #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */ |
| 7722 | #define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!< Filter bit 28 */ |
7722 | #define CAN_F13R1_FB29_Pos (29U) |
| 7723 | #define CAN_F13R1_FB29_Pos (29U) |
7723 | #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ |
| 7724 | #define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */ |
7724 | #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */ |
| 7725 | #define CAN_F13R1_FB29 CAN_F13R1_FB29_Msk /*!< Filter bit 29 */ |
7725 | #define CAN_F13R1_FB30_Pos (30U) |
| 7726 | #define CAN_F13R1_FB30_Pos (30U) |
7726 | #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ |
| 7727 | #define CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos) /*!< 0x40000000 */ |
7727 | #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */ |
| 7728 | #define CAN_F13R1_FB30 CAN_F13R1_FB30_Msk /*!< Filter bit 30 */ |
7728 | #define CAN_F13R1_FB31_Pos (31U) |
| 7729 | #define CAN_F13R1_FB31_Pos (31U) |
7729 | #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ |
| 7730 | #define CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos) /*!< 0x80000000 */ |
7730 | #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */ |
| 7731 | #define CAN_F13R1_FB31 CAN_F13R1_FB31_Msk /*!< Filter bit 31 */ |
7731 | |
| 7732 | 7732 | /******************* Bit definition for CAN_F14R1 register ******************/ |
|
| 7733 | /******************* Bit definition for CAN_F14R1 register ******************/ |
7733 | #define CAN_F14R1_FB0_Pos (0U) |
| 7734 | #define CAN_F14R1_FB0_Pos (0U) |
7734 | #define CAN_F14R1_FB0_Msk (0x1UL << CAN_F14R1_FB0_Pos) /*!< 0x00000001 */ |
| 7735 | #define CAN_F14R1_FB0_Msk (0x1UL << CAN_F14R1_FB0_Pos) /*!< 0x00000001 */ |
7735 | #define CAN_F14R1_FB0 CAN_F14R1_FB0_Msk /*!< Filter bit 0 */ |
| 7736 | #define CAN_F14R1_FB0 CAN_F14R1_FB0_Msk /*!< Filter bit 0 */ |
7736 | #define CAN_F14R1_FB1_Pos (1U) |
| 7737 | #define CAN_F14R1_FB1_Pos (1U) |
7737 | #define CAN_F14R1_FB1_Msk (0x1UL << CAN_F14R1_FB1_Pos) /*!< 0x00000002 */ |
| 7738 | #define CAN_F14R1_FB1_Msk (0x1UL << CAN_F14R1_FB1_Pos) /*!< 0x00000002 */ |
7738 | #define CAN_F14R1_FB1 CAN_F14R1_FB1_Msk /*!< Filter bit 1 */ |
| 7739 | #define CAN_F14R1_FB1 CAN_F14R1_FB1_Msk /*!< Filter bit 1 */ |
7739 | #define CAN_F14R1_FB2_Pos (2U) |
| 7740 | #define CAN_F14R1_FB2_Pos (2U) |
7740 | #define CAN_F14R1_FB2_Msk (0x1UL << CAN_F14R1_FB2_Pos) /*!< 0x00000004 */ |
| 7741 | #define CAN_F14R1_FB2_Msk (0x1UL << CAN_F14R1_FB2_Pos) /*!< 0x00000004 */ |
7741 | #define CAN_F14R1_FB2 CAN_F14R1_FB2_Msk /*!< Filter bit 2 */ |
| 7742 | #define CAN_F14R1_FB2 CAN_F14R1_FB2_Msk /*!< Filter bit 2 */ |
7742 | #define CAN_F14R1_FB3_Pos (3U) |
| 7743 | #define CAN_F14R1_FB3_Pos (3U) |
7743 | #define CAN_F14R1_FB3_Msk (0x1UL << CAN_F14R1_FB3_Pos) /*!< 0x00000008 */ |
| 7744 | #define CAN_F14R1_FB3_Msk (0x1UL << CAN_F14R1_FB3_Pos) /*!< 0x00000008 */ |
7744 | #define CAN_F14R1_FB3 CAN_F14R1_FB3_Msk /*!< Filter bit 3 */ |
| 7745 | #define CAN_F14R1_FB3 CAN_F14R1_FB3_Msk /*!< Filter bit 3 */ |
7745 | #define CAN_F14R1_FB4_Pos (4U) |
| 7746 | #define CAN_F14R1_FB4_Pos (4U) |
7746 | #define CAN_F14R1_FB4_Msk (0x1UL << CAN_F14R1_FB4_Pos) /*!< 0x00000010 */ |
| 7747 | #define CAN_F14R1_FB4_Msk (0x1UL << CAN_F14R1_FB4_Pos) /*!< 0x00000010 */ |
7747 | #define CAN_F14R1_FB4 CAN_F14R1_FB4_Msk /*!< Filter bit 4 */ |
| 7748 | #define CAN_F14R1_FB4 CAN_F14R1_FB4_Msk /*!< Filter bit 4 */ |
7748 | #define CAN_F14R1_FB5_Pos (5U) |
| 7749 | #define CAN_F14R1_FB5_Pos (5U) |
7749 | #define CAN_F14R1_FB5_Msk (0x1UL << CAN_F14R1_FB5_Pos) /*!< 0x00000020 */ |
| 7750 | #define CAN_F14R1_FB5_Msk (0x1UL << CAN_F14R1_FB5_Pos) /*!< 0x00000020 */ |
7750 | #define CAN_F14R1_FB5 CAN_F14R1_FB5_Msk /*!< Filter bit 5 */ |
| 7751 | #define CAN_F14R1_FB5 CAN_F14R1_FB5_Msk /*!< Filter bit 5 */ |
7751 | #define CAN_F14R1_FB6_Pos (6U) |
| 7752 | #define CAN_F14R1_FB6_Pos (6U) |
7752 | #define CAN_F14R1_FB6_Msk (0x1UL << CAN_F14R1_FB6_Pos) /*!< 0x00000040 */ |
| 7753 | #define CAN_F14R1_FB6_Msk (0x1UL << CAN_F14R1_FB6_Pos) /*!< 0x00000040 */ |
7753 | #define CAN_F14R1_FB6 CAN_F14R1_FB6_Msk /*!< Filter bit 6 */ |
| 7754 | #define CAN_F14R1_FB6 CAN_F14R1_FB6_Msk /*!< Filter bit 6 */ |
7754 | #define CAN_F14R1_FB7_Pos (7U) |
| 7755 | #define CAN_F14R1_FB7_Pos (7U) |
7755 | #define CAN_F14R1_FB7_Msk (0x1UL << CAN_F14R1_FB7_Pos) /*!< 0x00000080 */ |
| 7756 | #define CAN_F14R1_FB7_Msk (0x1UL << CAN_F14R1_FB7_Pos) /*!< 0x00000080 */ |
7756 | #define CAN_F14R1_FB7 CAN_F14R1_FB7_Msk /*!< Filter bit 7 */ |
| 7757 | #define CAN_F14R1_FB7 CAN_F14R1_FB7_Msk /*!< Filter bit 7 */ |
7757 | #define CAN_F14R1_FB8_Pos (8U) |
| 7758 | #define CAN_F14R1_FB8_Pos (8U) |
7758 | #define CAN_F14R1_FB8_Msk (0x1UL << CAN_F14R1_FB8_Pos) /*!< 0x00000100 */ |
| 7759 | #define CAN_F14R1_FB8_Msk (0x1UL << CAN_F14R1_FB8_Pos) /*!< 0x00000100 */ |
7759 | #define CAN_F14R1_FB8 CAN_F14R1_FB8_Msk /*!< Filter bit 8 */ |
| 7760 | #define CAN_F14R1_FB8 CAN_F14R1_FB8_Msk /*!< Filter bit 8 */ |
7760 | #define CAN_F14R1_FB9_Pos (9U) |
| 7761 | #define CAN_F14R1_FB9_Pos (9U) |
7761 | #define CAN_F14R1_FB9_Msk (0x1UL << CAN_F14R1_FB9_Pos) /*!< 0x00000200 */ |
| 7762 | #define CAN_F14R1_FB9_Msk (0x1UL << CAN_F14R1_FB9_Pos) /*!< 0x00000200 */ |
7762 | #define CAN_F14R1_FB9 CAN_F14R1_FB9_Msk /*!< Filter bit 9 */ |
| 7763 | #define CAN_F14R1_FB9 CAN_F14R1_FB9_Msk /*!< Filter bit 9 */ |
7763 | #define CAN_F14R1_FB10_Pos (10U) |
| 7764 | #define CAN_F14R1_FB10_Pos (10U) |
7764 | #define CAN_F14R1_FB10_Msk (0x1UL << CAN_F14R1_FB10_Pos) /*!< 0x00000400 */ |
| 7765 | #define CAN_F14R1_FB10_Msk (0x1UL << CAN_F14R1_FB10_Pos) /*!< 0x00000400 */ |
7765 | #define CAN_F14R1_FB10 CAN_F14R1_FB10_Msk /*!< Filter bit 10 */ |
| 7766 | #define CAN_F14R1_FB10 CAN_F14R1_FB10_Msk /*!< Filter bit 10 */ |
7766 | #define CAN_F14R1_FB11_Pos (11U) |
| 7767 | #define CAN_F14R1_FB11_Pos (11U) |
7767 | #define CAN_F14R1_FB11_Msk (0x1UL << CAN_F14R1_FB11_Pos) /*!< 0x00000800 */ |
| 7768 | #define CAN_F14R1_FB11_Msk (0x1UL << CAN_F14R1_FB11_Pos) /*!< 0x00000800 */ |
7768 | #define CAN_F14R1_FB11 CAN_F14R1_FB11_Msk /*!< Filter bit 11 */ |
| 7769 | #define CAN_F14R1_FB11 CAN_F14R1_FB11_Msk /*!< Filter bit 11 */ |
7769 | #define CAN_F14R1_FB12_Pos (12U) |
| 7770 | #define CAN_F14R1_FB12_Pos (12U) |
7770 | #define CAN_F14R1_FB12_Msk (0x1UL << CAN_F14R1_FB12_Pos) /*!< 0x00001000 */ |
| 7771 | #define CAN_F14R1_FB12_Msk (0x1UL << CAN_F14R1_FB12_Pos) /*!< 0x00001000 */ |
7771 | #define CAN_F14R1_FB12 CAN_F14R1_FB12_Msk /*!< Filter bit 12 */ |
| 7772 | #define CAN_F14R1_FB12 CAN_F14R1_FB12_Msk /*!< Filter bit 12 */ |
7772 | #define CAN_F14R1_FB13_Pos (13U) |
| 7773 | #define CAN_F14R1_FB13_Pos (13U) |
7773 | #define CAN_F14R1_FB13_Msk (0x1UL << CAN_F14R1_FB13_Pos) /*!< 0x00002000 */ |
| 7774 | #define CAN_F14R1_FB13_Msk (0x1UL << CAN_F14R1_FB13_Pos) /*!< 0x00002000 */ |
7774 | #define CAN_F14R1_FB13 CAN_F14R1_FB13_Msk /*!< Filter bit 13 */ |
| 7775 | #define CAN_F14R1_FB13 CAN_F14R1_FB13_Msk /*!< Filter bit 13 */ |
7775 | #define CAN_F14R1_FB14_Pos (14U) |
| 7776 | #define CAN_F14R1_FB14_Pos (14U) |
7776 | #define CAN_F14R1_FB14_Msk (0x1UL << CAN_F14R1_FB14_Pos) /*!< 0x00004000 */ |
| 7777 | #define CAN_F14R1_FB14_Msk (0x1UL << CAN_F14R1_FB14_Pos) /*!< 0x00004000 */ |
7777 | #define CAN_F14R1_FB14 CAN_F14R1_FB14_Msk /*!< Filter bit 14 */ |
| 7778 | #define CAN_F14R1_FB14 CAN_F14R1_FB14_Msk /*!< Filter bit 14 */ |
7778 | #define CAN_F14R1_FB15_Pos (15U) |
| 7779 | #define CAN_F14R1_FB15_Pos (15U) |
7779 | #define CAN_F14R1_FB15_Msk (0x1UL << CAN_F14R1_FB15_Pos) /*!< 0x00008000 */ |
| 7780 | #define CAN_F14R1_FB15_Msk (0x1UL << CAN_F14R1_FB15_Pos) /*!< 0x00008000 */ |
7780 | #define CAN_F14R1_FB15 CAN_F14R1_FB15_Msk /*!< Filter bit 15 */ |
| 7781 | #define CAN_F14R1_FB15 CAN_F14R1_FB15_Msk /*!< Filter bit 15 */ |
7781 | #define CAN_F14R1_FB16_Pos (16U) |
| 7782 | #define CAN_F14R1_FB16_Pos (16U) |
7782 | #define CAN_F14R1_FB16_Msk (0x1UL << CAN_F14R1_FB16_Pos) /*!< 0x00010000 */ |
| 7783 | #define CAN_F14R1_FB16_Msk (0x1UL << CAN_F14R1_FB16_Pos) /*!< 0x00010000 */ |
7783 | #define CAN_F14R1_FB16 CAN_F14R1_FB16_Msk /*!< Filter bit 16 */ |
| 7784 | #define CAN_F14R1_FB16 CAN_F14R1_FB16_Msk /*!< Filter bit 16 */ |
7784 | #define CAN_F14R1_FB17_Pos (17U) |
| 7785 | #define CAN_F14R1_FB17_Pos (17U) |
7785 | #define CAN_F14R1_FB17_Msk (0x1UL << CAN_F14R1_FB17_Pos) /*!< 0x00020000 */ |
| 7786 | #define CAN_F14R1_FB17_Msk (0x1UL << CAN_F14R1_FB17_Pos) /*!< 0x00020000 */ |
7786 | #define CAN_F14R1_FB17 CAN_F14R1_FB17_Msk /*!< Filter bit 17 */ |
| 7787 | #define CAN_F14R1_FB17 CAN_F14R1_FB17_Msk /*!< Filter bit 17 */ |
7787 | #define CAN_F14R1_FB18_Pos (18U) |
| 7788 | #define CAN_F14R1_FB18_Pos (18U) |
7788 | #define CAN_F14R1_FB18_Msk (0x1UL << CAN_F14R1_FB18_Pos) /*!< 0x00040000 */ |
| 7789 | #define CAN_F14R1_FB18_Msk (0x1UL << CAN_F14R1_FB18_Pos) /*!< 0x00040000 */ |
7789 | #define CAN_F14R1_FB18 CAN_F14R1_FB18_Msk /*!< Filter bit 18 */ |
| 7790 | #define CAN_F14R1_FB18 CAN_F14R1_FB18_Msk /*!< Filter bit 18 */ |
7790 | #define CAN_F14R1_FB19_Pos (19U) |
| 7791 | #define CAN_F14R1_FB19_Pos (19U) |
7791 | #define CAN_F14R1_FB19_Msk (0x1UL << CAN_F14R1_FB19_Pos) /*!< 0x00080000 */ |
| 7792 | #define CAN_F14R1_FB19_Msk (0x1UL << CAN_F14R1_FB19_Pos) /*!< 0x00080000 */ |
7792 | #define CAN_F14R1_FB19 CAN_F14R1_FB19_Msk /*!< Filter bit 19 */ |
| 7793 | #define CAN_F14R1_FB19 CAN_F14R1_FB19_Msk /*!< Filter bit 19 */ |
7793 | #define CAN_F14R1_FB20_Pos (20U) |
| 7794 | #define CAN_F14R1_FB20_Pos (20U) |
7794 | #define CAN_F14R1_FB20_Msk (0x1UL << CAN_F14R1_FB20_Pos) /*!< 0x00100000 */ |
| 7795 | #define CAN_F14R1_FB20_Msk (0x1UL << CAN_F14R1_FB20_Pos) /*!< 0x00100000 */ |
7795 | #define CAN_F14R1_FB20 CAN_F14R1_FB20_Msk /*!< Filter bit 20 */ |
| 7796 | #define CAN_F14R1_FB20 CAN_F14R1_FB20_Msk /*!< Filter bit 20 */ |
7796 | #define CAN_F14R1_FB21_Pos (21U) |
| 7797 | #define CAN_F14R1_FB21_Pos (21U) |
7797 | #define CAN_F14R1_FB21_Msk (0x1UL << CAN_F14R1_FB21_Pos) /*!< 0x00200000 */ |
| 7798 | #define CAN_F14R1_FB21_Msk (0x1UL << CAN_F14R1_FB21_Pos) /*!< 0x00200000 */ |
7798 | #define CAN_F14R1_FB21 CAN_F14R1_FB21_Msk /*!< Filter bit 21 */ |
| 7799 | #define CAN_F14R1_FB21 CAN_F14R1_FB21_Msk /*!< Filter bit 21 */ |
7799 | #define CAN_F14R1_FB22_Pos (22U) |
| 7800 | #define CAN_F14R1_FB22_Pos (22U) |
7800 | #define CAN_F14R1_FB22_Msk (0x1UL << CAN_F14R1_FB22_Pos) /*!< 0x00400000 */ |
| 7801 | #define CAN_F14R1_FB22_Msk (0x1UL << CAN_F14R1_FB22_Pos) /*!< 0x00400000 */ |
7801 | #define CAN_F14R1_FB22 CAN_F14R1_FB22_Msk /*!< Filter bit 22 */ |
| 7802 | #define CAN_F14R1_FB22 CAN_F14R1_FB22_Msk /*!< Filter bit 22 */ |
7802 | #define CAN_F14R1_FB23_Pos (23U) |
| 7803 | #define CAN_F14R1_FB23_Pos (23U) |
7803 | #define CAN_F14R1_FB23_Msk (0x1UL << CAN_F14R1_FB23_Pos) /*!< 0x00800000 */ |
| 7804 | #define CAN_F14R1_FB23_Msk (0x1UL << CAN_F14R1_FB23_Pos) /*!< 0x00800000 */ |
7804 | #define CAN_F14R1_FB23 CAN_F14R1_FB23_Msk /*!< Filter bit 23 */ |
| 7805 | #define CAN_F14R1_FB23 CAN_F14R1_FB23_Msk /*!< Filter bit 23 */ |
7805 | #define CAN_F14R1_FB24_Pos (24U) |
| 7806 | #define CAN_F14R1_FB24_Pos (24U) |
7806 | #define CAN_F14R1_FB24_Msk (0x1UL << CAN_F14R1_FB24_Pos) /*!< 0x01000000 */ |
| 7807 | #define CAN_F14R1_FB24_Msk (0x1UL << CAN_F14R1_FB24_Pos) /*!< 0x01000000 */ |
7807 | #define CAN_F14R1_FB24 CAN_F14R1_FB24_Msk /*!< Filter bit 24 */ |
| 7808 | #define CAN_F14R1_FB24 CAN_F14R1_FB24_Msk /*!< Filter bit 24 */ |
7808 | #define CAN_F14R1_FB25_Pos (25U) |
| 7809 | #define CAN_F14R1_FB25_Pos (25U) |
7809 | #define CAN_F14R1_FB25_Msk (0x1UL << CAN_F14R1_FB25_Pos) /*!< 0x02000000 */ |
| 7810 | #define CAN_F14R1_FB25_Msk (0x1UL << CAN_F14R1_FB25_Pos) /*!< 0x02000000 */ |
7810 | #define CAN_F14R1_FB25 CAN_F14R1_FB25_Msk /*!< Filter bit 25 */ |
| 7811 | #define CAN_F14R1_FB25 CAN_F14R1_FB25_Msk /*!< Filter bit 25 */ |
7811 | #define CAN_F14R1_FB26_Pos (26U) |
| 7812 | #define CAN_F14R1_FB26_Pos (26U) |
7812 | #define CAN_F14R1_FB26_Msk (0x1UL << CAN_F14R1_FB26_Pos) /*!< 0x04000000 */ |
| 7813 | #define CAN_F14R1_FB26_Msk (0x1UL << CAN_F14R1_FB26_Pos) /*!< 0x04000000 */ |
7813 | #define CAN_F14R1_FB26 CAN_F14R1_FB26_Msk /*!< Filter bit 26 */ |
| 7814 | #define CAN_F14R1_FB26 CAN_F14R1_FB26_Msk /*!< Filter bit 26 */ |
7814 | #define CAN_F14R1_FB27_Pos (27U) |
| 7815 | #define CAN_F14R1_FB27_Pos (27U) |
7815 | #define CAN_F14R1_FB27_Msk (0x1UL << CAN_F14R1_FB27_Pos) /*!< 0x08000000 */ |
| 7816 | #define CAN_F14R1_FB27_Msk (0x1UL << CAN_F14R1_FB27_Pos) /*!< 0x08000000 */ |
7816 | #define CAN_F14R1_FB27 CAN_F14R1_FB27_Msk /*!< Filter bit 27 */ |
| 7817 | #define CAN_F14R1_FB27 CAN_F14R1_FB27_Msk /*!< Filter bit 27 */ |
7817 | #define CAN_F14R1_FB28_Pos (28U) |
| 7818 | #define CAN_F14R1_FB28_Pos (28U) |
7818 | #define CAN_F14R1_FB28_Msk (0x1UL << CAN_F14R1_FB28_Pos) /*!< 0x10000000 */ |
| 7819 | #define CAN_F14R1_FB28_Msk (0x1UL << CAN_F14R1_FB28_Pos) /*!< 0x10000000 */ |
7819 | #define CAN_F14R1_FB28 CAN_F14R1_FB28_Msk /*!< Filter bit 28 */ |
| 7820 | #define CAN_F14R1_FB28 CAN_F14R1_FB28_Msk /*!< Filter bit 28 */ |
7820 | #define CAN_F14R1_FB29_Pos (29U) |
| 7821 | #define CAN_F14R1_FB29_Pos (29U) |
7821 | #define CAN_F14R1_FB29_Msk (0x1UL << CAN_F14R1_FB29_Pos) /*!< 0x20000000 */ |
| 7822 | #define CAN_F14R1_FB29_Msk (0x1UL << CAN_F14R1_FB29_Pos) /*!< 0x20000000 */ |
7822 | #define CAN_F14R1_FB29 CAN_F14R1_FB29_Msk /*!< Filter bit 29 */ |
| 7823 | #define CAN_F14R1_FB29 CAN_F14R1_FB29_Msk /*!< Filter bit 29 */ |
7823 | #define CAN_F14R1_FB30_Pos (30U) |
| 7824 | #define CAN_F14R1_FB30_Pos (30U) |
7824 | #define CAN_F14R1_FB30_Msk (0x1UL << CAN_F14R1_FB30_Pos) /*!< 0x40000000 */ |
| 7825 | #define CAN_F14R1_FB30_Msk (0x1UL << CAN_F14R1_FB30_Pos) /*!< 0x40000000 */ |
7825 | #define CAN_F14R1_FB30 CAN_F14R1_FB30_Msk /*!< Filter bit 30 */ |
| 7826 | #define CAN_F14R1_FB30 CAN_F14R1_FB30_Msk /*!< Filter bit 30 */ |
7826 | #define CAN_F14R1_FB31_Pos (31U) |
| 7827 | #define CAN_F14R1_FB31_Pos (31U) |
7827 | #define CAN_F14R1_FB31_Msk (0x1UL << CAN_F14R1_FB31_Pos) /*!< 0x80000000 */ |
| 7828 | #define CAN_F14R1_FB31_Msk (0x1UL << CAN_F14R1_FB31_Pos) /*!< 0x80000000 */ |
7828 | #define CAN_F14R1_FB31 CAN_F14R1_FB31_Msk /*!< Filter bit 31 */ |
| 7829 | #define CAN_F14R1_FB31 CAN_F14R1_FB31_Msk /*!< Filter bit 31 */ |
7829 | |
| 7830 | 7830 | /******************* Bit definition for CAN_F15R1 register ******************/ |
|
| 7831 | /******************* Bit definition for CAN_F15R1 register ******************/ |
7831 | #define CAN_F15R1_FB0_Pos (0U) |
| 7832 | #define CAN_F15R1_FB0_Pos (0U) |
7832 | #define CAN_F15R1_FB0_Msk (0x1UL << CAN_F15R1_FB0_Pos) /*!< 0x00000001 */ |
| 7833 | #define CAN_F15R1_FB0_Msk (0x1UL << CAN_F15R1_FB0_Pos) /*!< 0x00000001 */ |
7833 | #define CAN_F15R1_FB0 CAN_F15R1_FB0_Msk /*!< Filter bit 0 */ |
| 7834 | #define CAN_F15R1_FB0 CAN_F15R1_FB0_Msk /*!< Filter bit 0 */ |
7834 | #define CAN_F15R1_FB1_Pos (1U) |
| 7835 | #define CAN_F15R1_FB1_Pos (1U) |
7835 | #define CAN_F15R1_FB1_Msk (0x1UL << CAN_F15R1_FB1_Pos) /*!< 0x00000002 */ |
| 7836 | #define CAN_F15R1_FB1_Msk (0x1UL << CAN_F15R1_FB1_Pos) /*!< 0x00000002 */ |
7836 | #define CAN_F15R1_FB1 CAN_F15R1_FB1_Msk /*!< Filter bit 1 */ |
| 7837 | #define CAN_F15R1_FB1 CAN_F15R1_FB1_Msk /*!< Filter bit 1 */ |
7837 | #define CAN_F15R1_FB2_Pos (2U) |
| 7838 | #define CAN_F15R1_FB2_Pos (2U) |
7838 | #define CAN_F15R1_FB2_Msk (0x1UL << CAN_F15R1_FB2_Pos) /*!< 0x00000004 */ |
| 7839 | #define CAN_F15R1_FB2_Msk (0x1UL << CAN_F15R1_FB2_Pos) /*!< 0x00000004 */ |
7839 | #define CAN_F15R1_FB2 CAN_F15R1_FB2_Msk /*!< Filter bit 2 */ |
| 7840 | #define CAN_F15R1_FB2 CAN_F15R1_FB2_Msk /*!< Filter bit 2 */ |
7840 | #define CAN_F15R1_FB3_Pos (3U) |
| 7841 | #define CAN_F15R1_FB3_Pos (3U) |
7841 | #define CAN_F15R1_FB3_Msk (0x1UL << CAN_F15R1_FB3_Pos) /*!< 0x00000008 */ |
| 7842 | #define CAN_F15R1_FB3_Msk (0x1UL << CAN_F15R1_FB3_Pos) /*!< 0x00000008 */ |
7842 | #define CAN_F15R1_FB3 CAN_F15R1_FB3_Msk /*!< Filter bit 3 */ |
| 7843 | #define CAN_F15R1_FB3 CAN_F15R1_FB3_Msk /*!< Filter bit 3 */ |
7843 | #define CAN_F15R1_FB4_Pos (4U) |
| 7844 | #define CAN_F15R1_FB4_Pos (4U) |
7844 | #define CAN_F15R1_FB4_Msk (0x1UL << CAN_F15R1_FB4_Pos) /*!< 0x00000010 */ |
| 7845 | #define CAN_F15R1_FB4_Msk (0x1UL << CAN_F15R1_FB4_Pos) /*!< 0x00000010 */ |
7845 | #define CAN_F15R1_FB4 CAN_F15R1_FB4_Msk /*!< Filter bit 4 */ |
| 7846 | #define CAN_F15R1_FB4 CAN_F15R1_FB4_Msk /*!< Filter bit 4 */ |
7846 | #define CAN_F15R1_FB5_Pos (5U) |
| 7847 | #define CAN_F15R1_FB5_Pos (5U) |
7847 | #define CAN_F15R1_FB5_Msk (0x1UL << CAN_F15R1_FB5_Pos) /*!< 0x00000020 */ |
| 7848 | #define CAN_F15R1_FB5_Msk (0x1UL << CAN_F15R1_FB5_Pos) /*!< 0x00000020 */ |
7848 | #define CAN_F15R1_FB5 CAN_F15R1_FB5_Msk /*!< Filter bit 5 */ |
| 7849 | #define CAN_F15R1_FB5 CAN_F15R1_FB5_Msk /*!< Filter bit 5 */ |
7849 | #define CAN_F15R1_FB6_Pos (6U) |
| 7850 | #define CAN_F15R1_FB6_Pos (6U) |
7850 | #define CAN_F15R1_FB6_Msk (0x1UL << CAN_F15R1_FB6_Pos) /*!< 0x00000040 */ |
| 7851 | #define CAN_F15R1_FB6_Msk (0x1UL << CAN_F15R1_FB6_Pos) /*!< 0x00000040 */ |
7851 | #define CAN_F15R1_FB6 CAN_F15R1_FB6_Msk /*!< Filter bit 6 */ |
| 7852 | #define CAN_F15R1_FB6 CAN_F15R1_FB6_Msk /*!< Filter bit 6 */ |
7852 | #define CAN_F15R1_FB7_Pos (7U) |
| 7853 | #define CAN_F15R1_FB7_Pos (7U) |
7853 | #define CAN_F15R1_FB7_Msk (0x1UL << CAN_F15R1_FB7_Pos) /*!< 0x00000080 */ |
| 7854 | #define CAN_F15R1_FB7_Msk (0x1UL << CAN_F15R1_FB7_Pos) /*!< 0x00000080 */ |
7854 | #define CAN_F15R1_FB7 CAN_F15R1_FB7_Msk /*!< Filter bit 7 */ |
| 7855 | #define CAN_F15R1_FB7 CAN_F15R1_FB7_Msk /*!< Filter bit 7 */ |
7855 | #define CAN_F15R1_FB8_Pos (8U) |
| 7856 | #define CAN_F15R1_FB8_Pos (8U) |
7856 | #define CAN_F15R1_FB8_Msk (0x1UL << CAN_F15R1_FB8_Pos) /*!< 0x00000100 */ |
| 7857 | #define CAN_F15R1_FB8_Msk (0x1UL << CAN_F15R1_FB8_Pos) /*!< 0x00000100 */ |
7857 | #define CAN_F15R1_FB8 CAN_F15R1_FB8_Msk /*!< Filter bit 8 */ |
| 7858 | #define CAN_F15R1_FB8 CAN_F15R1_FB8_Msk /*!< Filter bit 8 */ |
7858 | #define CAN_F15R1_FB9_Pos (9U) |
| 7859 | #define CAN_F15R1_FB9_Pos (9U) |
7859 | #define CAN_F15R1_FB9_Msk (0x1UL << CAN_F15R1_FB9_Pos) /*!< 0x00000200 */ |
| 7860 | #define CAN_F15R1_FB9_Msk (0x1UL << CAN_F15R1_FB9_Pos) /*!< 0x00000200 */ |
7860 | #define CAN_F15R1_FB9 CAN_F15R1_FB9_Msk /*!< Filter bit 9 */ |
| 7861 | #define CAN_F15R1_FB9 CAN_F15R1_FB9_Msk /*!< Filter bit 9 */ |
7861 | #define CAN_F15R1_FB10_Pos (10U) |
| 7862 | #define CAN_F15R1_FB10_Pos (10U) |
7862 | #define CAN_F15R1_FB10_Msk (0x1UL << CAN_F15R1_FB10_Pos) /*!< 0x00000400 */ |
| 7863 | #define CAN_F15R1_FB10_Msk (0x1UL << CAN_F15R1_FB10_Pos) /*!< 0x00000400 */ |
7863 | #define CAN_F15R1_FB10 CAN_F15R1_FB10_Msk /*!< Filter bit 10 */ |
| 7864 | #define CAN_F15R1_FB10 CAN_F15R1_FB10_Msk /*!< Filter bit 10 */ |
7864 | #define CAN_F15R1_FB11_Pos (11U) |
| 7865 | #define CAN_F15R1_FB11_Pos (11U) |
7865 | #define CAN_F15R1_FB11_Msk (0x1UL << CAN_F15R1_FB11_Pos) /*!< 0x00000800 */ |
| 7866 | #define CAN_F15R1_FB11_Msk (0x1UL << CAN_F15R1_FB11_Pos) /*!< 0x00000800 */ |
7866 | #define CAN_F15R1_FB11 CAN_F15R1_FB11_Msk /*!< Filter bit 11 */ |
| 7867 | #define CAN_F15R1_FB11 CAN_F15R1_FB11_Msk /*!< Filter bit 11 */ |
7867 | #define CAN_F15R1_FB12_Pos (12U) |
| 7868 | #define CAN_F15R1_FB12_Pos (12U) |
7868 | #define CAN_F15R1_FB12_Msk (0x1UL << CAN_F15R1_FB12_Pos) /*!< 0x00001000 */ |
| 7869 | #define CAN_F15R1_FB12_Msk (0x1UL << CAN_F15R1_FB12_Pos) /*!< 0x00001000 */ |
7869 | #define CAN_F15R1_FB12 CAN_F15R1_FB12_Msk /*!< Filter bit 12 */ |
| 7870 | #define CAN_F15R1_FB12 CAN_F15R1_FB12_Msk /*!< Filter bit 12 */ |
7870 | #define CAN_F15R1_FB13_Pos (13U) |
| 7871 | #define CAN_F15R1_FB13_Pos (13U) |
7871 | #define CAN_F15R1_FB13_Msk (0x1UL << CAN_F15R1_FB13_Pos) /*!< 0x00002000 */ |
| 7872 | #define CAN_F15R1_FB13_Msk (0x1UL << CAN_F15R1_FB13_Pos) /*!< 0x00002000 */ |
7872 | #define CAN_F15R1_FB13 CAN_F15R1_FB13_Msk /*!< Filter bit 13 */ |
| 7873 | #define CAN_F15R1_FB13 CAN_F15R1_FB13_Msk /*!< Filter bit 13 */ |
7873 | #define CAN_F15R1_FB14_Pos (14U) |
| 7874 | #define CAN_F15R1_FB14_Pos (14U) |
7874 | #define CAN_F15R1_FB14_Msk (0x1UL << CAN_F15R1_FB14_Pos) /*!< 0x00004000 */ |
| 7875 | #define CAN_F15R1_FB14_Msk (0x1UL << CAN_F15R1_FB14_Pos) /*!< 0x00004000 */ |
7875 | #define CAN_F15R1_FB14 CAN_F15R1_FB14_Msk /*!< Filter bit 14 */ |
| 7876 | #define CAN_F15R1_FB14 CAN_F15R1_FB14_Msk /*!< Filter bit 14 */ |
7876 | #define CAN_F15R1_FB15_Pos (15U) |
| 7877 | #define CAN_F15R1_FB15_Pos (15U) |
7877 | #define CAN_F15R1_FB15_Msk (0x1UL << CAN_F15R1_FB15_Pos) /*!< 0x00008000 */ |
| 7878 | #define CAN_F15R1_FB15_Msk (0x1UL << CAN_F15R1_FB15_Pos) /*!< 0x00008000 */ |
7878 | #define CAN_F15R1_FB15 CAN_F15R1_FB15_Msk /*!< Filter bit 15 */ |
| 7879 | #define CAN_F15R1_FB15 CAN_F15R1_FB15_Msk /*!< Filter bit 15 */ |
7879 | #define CAN_F15R1_FB16_Pos (16U) |
| 7880 | #define CAN_F15R1_FB16_Pos (16U) |
7880 | #define CAN_F15R1_FB16_Msk (0x1UL << CAN_F15R1_FB16_Pos) /*!< 0x00010000 */ |
| 7881 | #define CAN_F15R1_FB16_Msk (0x1UL << CAN_F15R1_FB16_Pos) /*!< 0x00010000 */ |
7881 | #define CAN_F15R1_FB16 CAN_F15R1_FB16_Msk /*!< Filter bit 16 */ |
| 7882 | #define CAN_F15R1_FB16 CAN_F15R1_FB16_Msk /*!< Filter bit 16 */ |
7882 | #define CAN_F15R1_FB17_Pos (17U) |
| 7883 | #define CAN_F15R1_FB17_Pos (17U) |
7883 | #define CAN_F15R1_FB17_Msk (0x1UL << CAN_F15R1_FB17_Pos) /*!< 0x00020000 */ |
| 7884 | #define CAN_F15R1_FB17_Msk (0x1UL << CAN_F15R1_FB17_Pos) /*!< 0x00020000 */ |
7884 | #define CAN_F15R1_FB17 CAN_F15R1_FB17_Msk /*!< Filter bit 17 */ |
| 7885 | #define CAN_F15R1_FB17 CAN_F15R1_FB17_Msk /*!< Filter bit 17 */ |
7885 | #define CAN_F15R1_FB18_Pos (18U) |
| 7886 | #define CAN_F15R1_FB18_Pos (18U) |
7886 | #define CAN_F15R1_FB18_Msk (0x1UL << CAN_F15R1_FB18_Pos) /*!< 0x00040000 */ |
| 7887 | #define CAN_F15R1_FB18_Msk (0x1UL << CAN_F15R1_FB18_Pos) /*!< 0x00040000 */ |
7887 | #define CAN_F15R1_FB18 CAN_F15R1_FB18_Msk /*!< Filter bit 18 */ |
| 7888 | #define CAN_F15R1_FB18 CAN_F15R1_FB18_Msk /*!< Filter bit 18 */ |
7888 | #define CAN_F15R1_FB19_Pos (19U) |
| 7889 | #define CAN_F15R1_FB19_Pos (19U) |
7889 | #define CAN_F15R1_FB19_Msk (0x1UL << CAN_F15R1_FB19_Pos) /*!< 0x00080000 */ |
| 7890 | #define CAN_F15R1_FB19_Msk (0x1UL << CAN_F15R1_FB19_Pos) /*!< 0x00080000 */ |
7890 | #define CAN_F15R1_FB19 CAN_F15R1_FB19_Msk /*!< Filter bit 19 */ |
| 7891 | #define CAN_F15R1_FB19 CAN_F15R1_FB19_Msk /*!< Filter bit 19 */ |
7891 | #define CAN_F15R1_FB20_Pos (20U) |
| 7892 | #define CAN_F15R1_FB20_Pos (20U) |
7892 | #define CAN_F15R1_FB20_Msk (0x1UL << CAN_F15R1_FB20_Pos) /*!< 0x00100000 */ |
| 7893 | #define CAN_F15R1_FB20_Msk (0x1UL << CAN_F15R1_FB20_Pos) /*!< 0x00100000 */ |
7893 | #define CAN_F15R1_FB20 CAN_F15R1_FB20_Msk /*!< Filter bit 20 */ |
| 7894 | #define CAN_F15R1_FB20 CAN_F15R1_FB20_Msk /*!< Filter bit 20 */ |
7894 | #define CAN_F15R1_FB21_Pos (21U) |
| 7895 | #define CAN_F15R1_FB21_Pos (21U) |
7895 | #define CAN_F15R1_FB21_Msk (0x1UL << CAN_F15R1_FB21_Pos) /*!< 0x00200000 */ |
| 7896 | #define CAN_F15R1_FB21_Msk (0x1UL << CAN_F15R1_FB21_Pos) /*!< 0x00200000 */ |
7896 | #define CAN_F15R1_FB21 CAN_F15R1_FB21_Msk /*!< Filter bit 21 */ |
| 7897 | #define CAN_F15R1_FB21 CAN_F15R1_FB21_Msk /*!< Filter bit 21 */ |
7897 | #define CAN_F15R1_FB22_Pos (22U) |
| 7898 | #define CAN_F15R1_FB22_Pos (22U) |
7898 | #define CAN_F15R1_FB22_Msk (0x1UL << CAN_F15R1_FB22_Pos) /*!< 0x00400000 */ |
| 7899 | #define CAN_F15R1_FB22_Msk (0x1UL << CAN_F15R1_FB22_Pos) /*!< 0x00400000 */ |
7899 | #define CAN_F15R1_FB22 CAN_F15R1_FB22_Msk /*!< Filter bit 22 */ |
| 7900 | #define CAN_F15R1_FB22 CAN_F15R1_FB22_Msk /*!< Filter bit 22 */ |
7900 | #define CAN_F15R1_FB23_Pos (23U) |
| 7901 | #define CAN_F15R1_FB23_Pos (23U) |
7901 | #define CAN_F15R1_FB23_Msk (0x1UL << CAN_F15R1_FB23_Pos) /*!< 0x00800000 */ |
| 7902 | #define CAN_F15R1_FB23_Msk (0x1UL << CAN_F15R1_FB23_Pos) /*!< 0x00800000 */ |
7902 | #define CAN_F15R1_FB23 CAN_F15R1_FB23_Msk /*!< Filter bit 23 */ |
| 7903 | #define CAN_F15R1_FB23 CAN_F15R1_FB23_Msk /*!< Filter bit 23 */ |
7903 | #define CAN_F15R1_FB24_Pos (24U) |
| 7904 | #define CAN_F15R1_FB24_Pos (24U) |
7904 | #define CAN_F15R1_FB24_Msk (0x1UL << CAN_F15R1_FB24_Pos) /*!< 0x01000000 */ |
| 7905 | #define CAN_F15R1_FB24_Msk (0x1UL << CAN_F15R1_FB24_Pos) /*!< 0x01000000 */ |
7905 | #define CAN_F15R1_FB24 CAN_F15R1_FB24_Msk /*!< Filter bit 24 */ |
| 7906 | #define CAN_F15R1_FB24 CAN_F15R1_FB24_Msk /*!< Filter bit 24 */ |
7906 | #define CAN_F15R1_FB25_Pos (25U) |
| 7907 | #define CAN_F15R1_FB25_Pos (25U) |
7907 | #define CAN_F15R1_FB25_Msk (0x1UL << CAN_F15R1_FB25_Pos) /*!< 0x02000000 */ |
| 7908 | #define CAN_F15R1_FB25_Msk (0x1UL << CAN_F15R1_FB25_Pos) /*!< 0x02000000 */ |
7908 | #define CAN_F15R1_FB25 CAN_F15R1_FB25_Msk /*!< Filter bit 25 */ |
| 7909 | #define CAN_F15R1_FB25 CAN_F15R1_FB25_Msk /*!< Filter bit 25 */ |
7909 | #define CAN_F15R1_FB26_Pos (26U) |
| 7910 | #define CAN_F15R1_FB26_Pos (26U) |
7910 | #define CAN_F15R1_FB26_Msk (0x1UL << CAN_F15R1_FB26_Pos) /*!< 0x04000000 */ |
| 7911 | #define CAN_F15R1_FB26_Msk (0x1UL << CAN_F15R1_FB26_Pos) /*!< 0x04000000 */ |
7911 | #define CAN_F15R1_FB26 CAN_F15R1_FB26_Msk /*!< Filter bit 26 */ |
| 7912 | #define CAN_F15R1_FB26 CAN_F15R1_FB26_Msk /*!< Filter bit 26 */ |
7912 | #define CAN_F15R1_FB27_Pos (27U) |
| 7913 | #define CAN_F15R1_FB27_Pos (27U) |
7913 | #define CAN_F15R1_FB27_Msk (0x1UL << CAN_F15R1_FB27_Pos) /*!< 0x08000000 */ |
| 7914 | #define CAN_F15R1_FB27_Msk (0x1UL << CAN_F15R1_FB27_Pos) /*!< 0x08000000 */ |
7914 | #define CAN_F15R1_FB27 CAN_F15R1_FB27_Msk /*!< Filter bit 27 */ |
| 7915 | #define CAN_F15R1_FB27 CAN_F15R1_FB27_Msk /*!< Filter bit 27 */ |
7915 | #define CAN_F15R1_FB28_Pos (28U) |
| 7916 | #define CAN_F15R1_FB28_Pos (28U) |
7916 | #define CAN_F15R1_FB28_Msk (0x1UL << CAN_F15R1_FB28_Pos) /*!< 0x10000000 */ |
| 7917 | #define CAN_F15R1_FB28_Msk (0x1UL << CAN_F15R1_FB28_Pos) /*!< 0x10000000 */ |
7917 | #define CAN_F15R1_FB28 CAN_F15R1_FB28_Msk /*!< Filter bit 28 */ |
| 7918 | #define CAN_F15R1_FB28 CAN_F15R1_FB28_Msk /*!< Filter bit 28 */ |
7918 | #define CAN_F15R1_FB29_Pos (29U) |
| 7919 | #define CAN_F15R1_FB29_Pos (29U) |
7919 | #define CAN_F15R1_FB29_Msk (0x1UL << CAN_F15R1_FB29_Pos) /*!< 0x20000000 */ |
| 7920 | #define CAN_F15R1_FB29_Msk (0x1UL << CAN_F15R1_FB29_Pos) /*!< 0x20000000 */ |
7920 | #define CAN_F15R1_FB29 CAN_F15R1_FB29_Msk /*!< Filter bit 29 */ |
| 7921 | #define CAN_F15R1_FB29 CAN_F15R1_FB29_Msk /*!< Filter bit 29 */ |
7921 | #define CAN_F15R1_FB30_Pos (30U) |
| 7922 | #define CAN_F15R1_FB30_Pos (30U) |
7922 | #define CAN_F15R1_FB30_Msk (0x1UL << CAN_F15R1_FB30_Pos) /*!< 0x40000000 */ |
| 7923 | #define CAN_F15R1_FB30_Msk (0x1UL << CAN_F15R1_FB30_Pos) /*!< 0x40000000 */ |
7923 | #define CAN_F15R1_FB30 CAN_F15R1_FB30_Msk /*!< Filter bit 30 */ |
| 7924 | #define CAN_F15R1_FB30 CAN_F15R1_FB30_Msk /*!< Filter bit 30 */ |
7924 | #define CAN_F15R1_FB31_Pos (31U) |
| 7925 | #define CAN_F15R1_FB31_Pos (31U) |
7925 | #define CAN_F15R1_FB31_Msk (0x1UL << CAN_F15R1_FB31_Pos) /*!< 0x80000000 */ |
| 7926 | #define CAN_F15R1_FB31_Msk (0x1UL << CAN_F15R1_FB31_Pos) /*!< 0x80000000 */ |
7926 | #define CAN_F15R1_FB31 CAN_F15R1_FB31_Msk /*!< Filter bit 31 */ |
| 7927 | #define CAN_F15R1_FB31 CAN_F15R1_FB31_Msk /*!< Filter bit 31 */ |
7927 | |
| 7928 | 7928 | /******************* Bit definition for CAN_F16R1 register ******************/ |
|
| 7929 | /******************* Bit definition for CAN_F16R1 register ******************/ |
7929 | #define CAN_F16R1_FB0_Pos (0U) |
| 7930 | #define CAN_F16R1_FB0_Pos (0U) |
7930 | #define CAN_F16R1_FB0_Msk (0x1UL << CAN_F16R1_FB0_Pos) /*!< 0x00000001 */ |
| 7931 | #define CAN_F16R1_FB0_Msk (0x1UL << CAN_F16R1_FB0_Pos) /*!< 0x00000001 */ |
7931 | #define CAN_F16R1_FB0 CAN_F16R1_FB0_Msk /*!< Filter bit 0 */ |
| 7932 | #define CAN_F16R1_FB0 CAN_F16R1_FB0_Msk /*!< Filter bit 0 */ |
7932 | #define CAN_F16R1_FB1_Pos (1U) |
| 7933 | #define CAN_F16R1_FB1_Pos (1U) |
7933 | #define CAN_F16R1_FB1_Msk (0x1UL << CAN_F16R1_FB1_Pos) /*!< 0x00000002 */ |
| 7934 | #define CAN_F16R1_FB1_Msk (0x1UL << CAN_F16R1_FB1_Pos) /*!< 0x00000002 */ |
7934 | #define CAN_F16R1_FB1 CAN_F16R1_FB1_Msk /*!< Filter bit 1 */ |
| 7935 | #define CAN_F16R1_FB1 CAN_F16R1_FB1_Msk /*!< Filter bit 1 */ |
7935 | #define CAN_F16R1_FB2_Pos (2U) |
| 7936 | #define CAN_F16R1_FB2_Pos (2U) |
7936 | #define CAN_F16R1_FB2_Msk (0x1UL << CAN_F16R1_FB2_Pos) /*!< 0x00000004 */ |
| 7937 | #define CAN_F16R1_FB2_Msk (0x1UL << CAN_F16R1_FB2_Pos) /*!< 0x00000004 */ |
7937 | #define CAN_F16R1_FB2 CAN_F16R1_FB2_Msk /*!< Filter bit 2 */ |
| 7938 | #define CAN_F16R1_FB2 CAN_F16R1_FB2_Msk /*!< Filter bit 2 */ |
7938 | #define CAN_F16R1_FB3_Pos (3U) |
| 7939 | #define CAN_F16R1_FB3_Pos (3U) |
7939 | #define CAN_F16R1_FB3_Msk (0x1UL << CAN_F16R1_FB3_Pos) /*!< 0x00000008 */ |
| 7940 | #define CAN_F16R1_FB3_Msk (0x1UL << CAN_F16R1_FB3_Pos) /*!< 0x00000008 */ |
7940 | #define CAN_F16R1_FB3 CAN_F16R1_FB3_Msk /*!< Filter bit 3 */ |
| 7941 | #define CAN_F16R1_FB3 CAN_F16R1_FB3_Msk /*!< Filter bit 3 */ |
7941 | #define CAN_F16R1_FB4_Pos (4U) |
| 7942 | #define CAN_F16R1_FB4_Pos (4U) |
7942 | #define CAN_F16R1_FB4_Msk (0x1UL << CAN_F16R1_FB4_Pos) /*!< 0x00000010 */ |
| 7943 | #define CAN_F16R1_FB4_Msk (0x1UL << CAN_F16R1_FB4_Pos) /*!< 0x00000010 */ |
7943 | #define CAN_F16R1_FB4 CAN_F16R1_FB4_Msk /*!< Filter bit 4 */ |
| 7944 | #define CAN_F16R1_FB4 CAN_F16R1_FB4_Msk /*!< Filter bit 4 */ |
7944 | #define CAN_F16R1_FB5_Pos (5U) |
| 7945 | #define CAN_F16R1_FB5_Pos (5U) |
7945 | #define CAN_F16R1_FB5_Msk (0x1UL << CAN_F16R1_FB5_Pos) /*!< 0x00000020 */ |
| 7946 | #define CAN_F16R1_FB5_Msk (0x1UL << CAN_F16R1_FB5_Pos) /*!< 0x00000020 */ |
7946 | #define CAN_F16R1_FB5 CAN_F16R1_FB5_Msk /*!< Filter bit 5 */ |
| 7947 | #define CAN_F16R1_FB5 CAN_F16R1_FB5_Msk /*!< Filter bit 5 */ |
7947 | #define CAN_F16R1_FB6_Pos (6U) |
| 7948 | #define CAN_F16R1_FB6_Pos (6U) |
7948 | #define CAN_F16R1_FB6_Msk (0x1UL << CAN_F16R1_FB6_Pos) /*!< 0x00000040 */ |
| 7949 | #define CAN_F16R1_FB6_Msk (0x1UL << CAN_F16R1_FB6_Pos) /*!< 0x00000040 */ |
7949 | #define CAN_F16R1_FB6 CAN_F16R1_FB6_Msk /*!< Filter bit 6 */ |
| 7950 | #define CAN_F16R1_FB6 CAN_F16R1_FB6_Msk /*!< Filter bit 6 */ |
7950 | #define CAN_F16R1_FB7_Pos (7U) |
| 7951 | #define CAN_F16R1_FB7_Pos (7U) |
7951 | #define CAN_F16R1_FB7_Msk (0x1UL << CAN_F16R1_FB7_Pos) /*!< 0x00000080 */ |
| 7952 | #define CAN_F16R1_FB7_Msk (0x1UL << CAN_F16R1_FB7_Pos) /*!< 0x00000080 */ |
7952 | #define CAN_F16R1_FB7 CAN_F16R1_FB7_Msk /*!< Filter bit 7 */ |
| 7953 | #define CAN_F16R1_FB7 CAN_F16R1_FB7_Msk /*!< Filter bit 7 */ |
7953 | #define CAN_F16R1_FB8_Pos (8U) |
| 7954 | #define CAN_F16R1_FB8_Pos (8U) |
7954 | #define CAN_F16R1_FB8_Msk (0x1UL << CAN_F16R1_FB8_Pos) /*!< 0x00000100 */ |
| 7955 | #define CAN_F16R1_FB8_Msk (0x1UL << CAN_F16R1_FB8_Pos) /*!< 0x00000100 */ |
7955 | #define CAN_F16R1_FB8 CAN_F16R1_FB8_Msk /*!< Filter bit 8 */ |
| 7956 | #define CAN_F16R1_FB8 CAN_F16R1_FB8_Msk /*!< Filter bit 8 */ |
7956 | #define CAN_F16R1_FB9_Pos (9U) |
| 7957 | #define CAN_F16R1_FB9_Pos (9U) |
7957 | #define CAN_F16R1_FB9_Msk (0x1UL << CAN_F16R1_FB9_Pos) /*!< 0x00000200 */ |
| 7958 | #define CAN_F16R1_FB9_Msk (0x1UL << CAN_F16R1_FB9_Pos) /*!< 0x00000200 */ |
7958 | #define CAN_F16R1_FB9 CAN_F16R1_FB9_Msk /*!< Filter bit 9 */ |
| 7959 | #define CAN_F16R1_FB9 CAN_F16R1_FB9_Msk /*!< Filter bit 9 */ |
7959 | #define CAN_F16R1_FB10_Pos (10U) |
| 7960 | #define CAN_F16R1_FB10_Pos (10U) |
7960 | #define CAN_F16R1_FB10_Msk (0x1UL << CAN_F16R1_FB10_Pos) /*!< 0x00000400 */ |
| 7961 | #define CAN_F16R1_FB10_Msk (0x1UL << CAN_F16R1_FB10_Pos) /*!< 0x00000400 */ |
7961 | #define CAN_F16R1_FB10 CAN_F16R1_FB10_Msk /*!< Filter bit 10 */ |
| 7962 | #define CAN_F16R1_FB10 CAN_F16R1_FB10_Msk /*!< Filter bit 10 */ |
7962 | #define CAN_F16R1_FB11_Pos (11U) |
| 7963 | #define CAN_F16R1_FB11_Pos (11U) |
7963 | #define CAN_F16R1_FB11_Msk (0x1UL << CAN_F16R1_FB11_Pos) /*!< 0x00000800 */ |
| 7964 | #define CAN_F16R1_FB11_Msk (0x1UL << CAN_F16R1_FB11_Pos) /*!< 0x00000800 */ |
7964 | #define CAN_F16R1_FB11 CAN_F16R1_FB11_Msk /*!< Filter bit 11 */ |
| 7965 | #define CAN_F16R1_FB11 CAN_F16R1_FB11_Msk /*!< Filter bit 11 */ |
7965 | #define CAN_F16R1_FB12_Pos (12U) |
| 7966 | #define CAN_F16R1_FB12_Pos (12U) |
7966 | #define CAN_F16R1_FB12_Msk (0x1UL << CAN_F16R1_FB12_Pos) /*!< 0x00001000 */ |
| 7967 | #define CAN_F16R1_FB12_Msk (0x1UL << CAN_F16R1_FB12_Pos) /*!< 0x00001000 */ |
7967 | #define CAN_F16R1_FB12 CAN_F16R1_FB12_Msk /*!< Filter bit 12 */ |
| 7968 | #define CAN_F16R1_FB12 CAN_F16R1_FB12_Msk /*!< Filter bit 12 */ |
7968 | #define CAN_F16R1_FB13_Pos (13U) |
| 7969 | #define CAN_F16R1_FB13_Pos (13U) |
7969 | #define CAN_F16R1_FB13_Msk (0x1UL << CAN_F16R1_FB13_Pos) /*!< 0x00002000 */ |
| 7970 | #define CAN_F16R1_FB13_Msk (0x1UL << CAN_F16R1_FB13_Pos) /*!< 0x00002000 */ |
7970 | #define CAN_F16R1_FB13 CAN_F16R1_FB13_Msk /*!< Filter bit 13 */ |
| 7971 | #define CAN_F16R1_FB13 CAN_F16R1_FB13_Msk /*!< Filter bit 13 */ |
7971 | #define CAN_F16R1_FB14_Pos (14U) |
| 7972 | #define CAN_F16R1_FB14_Pos (14U) |
7972 | #define CAN_F16R1_FB14_Msk (0x1UL << CAN_F16R1_FB14_Pos) /*!< 0x00004000 */ |
| 7973 | #define CAN_F16R1_FB14_Msk (0x1UL << CAN_F16R1_FB14_Pos) /*!< 0x00004000 */ |
7973 | #define CAN_F16R1_FB14 CAN_F16R1_FB14_Msk /*!< Filter bit 14 */ |
| 7974 | #define CAN_F16R1_FB14 CAN_F16R1_FB14_Msk /*!< Filter bit 14 */ |
7974 | #define CAN_F16R1_FB15_Pos (15U) |
| 7975 | #define CAN_F16R1_FB15_Pos (15U) |
7975 | #define CAN_F16R1_FB15_Msk (0x1UL << CAN_F16R1_FB15_Pos) /*!< 0x00008000 */ |
| 7976 | #define CAN_F16R1_FB15_Msk (0x1UL << CAN_F16R1_FB15_Pos) /*!< 0x00008000 */ |
7976 | #define CAN_F16R1_FB15 CAN_F16R1_FB15_Msk /*!< Filter bit 15 */ |
| 7977 | #define CAN_F16R1_FB15 CAN_F16R1_FB15_Msk /*!< Filter bit 15 */ |
7977 | #define CAN_F16R1_FB16_Pos (16U) |
| 7978 | #define CAN_F16R1_FB16_Pos (16U) |
7978 | #define CAN_F16R1_FB16_Msk (0x1UL << CAN_F16R1_FB16_Pos) /*!< 0x00010000 */ |
| 7979 | #define CAN_F16R1_FB16_Msk (0x1UL << CAN_F16R1_FB16_Pos) /*!< 0x00010000 */ |
7979 | #define CAN_F16R1_FB16 CAN_F16R1_FB16_Msk /*!< Filter bit 16 */ |
| 7980 | #define CAN_F16R1_FB16 CAN_F16R1_FB16_Msk /*!< Filter bit 16 */ |
7980 | #define CAN_F16R1_FB17_Pos (17U) |
| 7981 | #define CAN_F16R1_FB17_Pos (17U) |
7981 | #define CAN_F16R1_FB17_Msk (0x1UL << CAN_F16R1_FB17_Pos) /*!< 0x00020000 */ |
| 7982 | #define CAN_F16R1_FB17_Msk (0x1UL << CAN_F16R1_FB17_Pos) /*!< 0x00020000 */ |
7982 | #define CAN_F16R1_FB17 CAN_F16R1_FB17_Msk /*!< Filter bit 17 */ |
| 7983 | #define CAN_F16R1_FB17 CAN_F16R1_FB17_Msk /*!< Filter bit 17 */ |
7983 | #define CAN_F16R1_FB18_Pos (18U) |
| 7984 | #define CAN_F16R1_FB18_Pos (18U) |
7984 | #define CAN_F16R1_FB18_Msk (0x1UL << CAN_F16R1_FB18_Pos) /*!< 0x00040000 */ |
| 7985 | #define CAN_F16R1_FB18_Msk (0x1UL << CAN_F16R1_FB18_Pos) /*!< 0x00040000 */ |
7985 | #define CAN_F16R1_FB18 CAN_F16R1_FB18_Msk /*!< Filter bit 18 */ |
| 7986 | #define CAN_F16R1_FB18 CAN_F16R1_FB18_Msk /*!< Filter bit 18 */ |
7986 | #define CAN_F16R1_FB19_Pos (19U) |
| 7987 | #define CAN_F16R1_FB19_Pos (19U) |
7987 | #define CAN_F16R1_FB19_Msk (0x1UL << CAN_F16R1_FB19_Pos) /*!< 0x00080000 */ |
| 7988 | #define CAN_F16R1_FB19_Msk (0x1UL << CAN_F16R1_FB19_Pos) /*!< 0x00080000 */ |
7988 | #define CAN_F16R1_FB19 CAN_F16R1_FB19_Msk /*!< Filter bit 19 */ |
| 7989 | #define CAN_F16R1_FB19 CAN_F16R1_FB19_Msk /*!< Filter bit 19 */ |
7989 | #define CAN_F16R1_FB20_Pos (20U) |
| 7990 | #define CAN_F16R1_FB20_Pos (20U) |
7990 | #define CAN_F16R1_FB20_Msk (0x1UL << CAN_F16R1_FB20_Pos) /*!< 0x00100000 */ |
| 7991 | #define CAN_F16R1_FB20_Msk (0x1UL << CAN_F16R1_FB20_Pos) /*!< 0x00100000 */ |
7991 | #define CAN_F16R1_FB20 CAN_F16R1_FB20_Msk /*!< Filter bit 20 */ |
| 7992 | #define CAN_F16R1_FB20 CAN_F16R1_FB20_Msk /*!< Filter bit 20 */ |
7992 | #define CAN_F16R1_FB21_Pos (21U) |
| 7993 | #define CAN_F16R1_FB21_Pos (21U) |
7993 | #define CAN_F16R1_FB21_Msk (0x1UL << CAN_F16R1_FB21_Pos) /*!< 0x00200000 */ |
| 7994 | #define CAN_F16R1_FB21_Msk (0x1UL << CAN_F16R1_FB21_Pos) /*!< 0x00200000 */ |
7994 | #define CAN_F16R1_FB21 CAN_F16R1_FB21_Msk /*!< Filter bit 21 */ |
| 7995 | #define CAN_F16R1_FB21 CAN_F16R1_FB21_Msk /*!< Filter bit 21 */ |
7995 | #define CAN_F16R1_FB22_Pos (22U) |
| 7996 | #define CAN_F16R1_FB22_Pos (22U) |
7996 | #define CAN_F16R1_FB22_Msk (0x1UL << CAN_F16R1_FB22_Pos) /*!< 0x00400000 */ |
| 7997 | #define CAN_F16R1_FB22_Msk (0x1UL << CAN_F16R1_FB22_Pos) /*!< 0x00400000 */ |
7997 | #define CAN_F16R1_FB22 CAN_F16R1_FB22_Msk /*!< Filter bit 22 */ |
| 7998 | #define CAN_F16R1_FB22 CAN_F16R1_FB22_Msk /*!< Filter bit 22 */ |
7998 | #define CAN_F16R1_FB23_Pos (23U) |
| 7999 | #define CAN_F16R1_FB23_Pos (23U) |
7999 | #define CAN_F16R1_FB23_Msk (0x1UL << CAN_F16R1_FB23_Pos) /*!< 0x00800000 */ |
| 8000 | #define CAN_F16R1_FB23_Msk (0x1UL << CAN_F16R1_FB23_Pos) /*!< 0x00800000 */ |
8000 | #define CAN_F16R1_FB23 CAN_F16R1_FB23_Msk /*!< Filter bit 23 */ |
| 8001 | #define CAN_F16R1_FB23 CAN_F16R1_FB23_Msk /*!< Filter bit 23 */ |
8001 | #define CAN_F16R1_FB24_Pos (24U) |
| 8002 | #define CAN_F16R1_FB24_Pos (24U) |
8002 | #define CAN_F16R1_FB24_Msk (0x1UL << CAN_F16R1_FB24_Pos) /*!< 0x01000000 */ |
| 8003 | #define CAN_F16R1_FB24_Msk (0x1UL << CAN_F16R1_FB24_Pos) /*!< 0x01000000 */ |
8003 | #define CAN_F16R1_FB24 CAN_F16R1_FB24_Msk /*!< Filter bit 24 */ |
| 8004 | #define CAN_F16R1_FB24 CAN_F16R1_FB24_Msk /*!< Filter bit 24 */ |
8004 | #define CAN_F16R1_FB25_Pos (25U) |
| 8005 | #define CAN_F16R1_FB25_Pos (25U) |
8005 | #define CAN_F16R1_FB25_Msk (0x1UL << CAN_F16R1_FB25_Pos) /*!< 0x02000000 */ |
| 8006 | #define CAN_F16R1_FB25_Msk (0x1UL << CAN_F16R1_FB25_Pos) /*!< 0x02000000 */ |
8006 | #define CAN_F16R1_FB25 CAN_F16R1_FB25_Msk /*!< Filter bit 25 */ |
| 8007 | #define CAN_F16R1_FB25 CAN_F16R1_FB25_Msk /*!< Filter bit 25 */ |
8007 | #define CAN_F16R1_FB26_Pos (26U) |
| 8008 | #define CAN_F16R1_FB26_Pos (26U) |
8008 | #define CAN_F16R1_FB26_Msk (0x1UL << CAN_F16R1_FB26_Pos) /*!< 0x04000000 */ |
| 8009 | #define CAN_F16R1_FB26_Msk (0x1UL << CAN_F16R1_FB26_Pos) /*!< 0x04000000 */ |
8009 | #define CAN_F16R1_FB26 CAN_F16R1_FB26_Msk /*!< Filter bit 26 */ |
| 8010 | #define CAN_F16R1_FB26 CAN_F16R1_FB26_Msk /*!< Filter bit 26 */ |
8010 | #define CAN_F16R1_FB27_Pos (27U) |
| 8011 | #define CAN_F16R1_FB27_Pos (27U) |
8011 | #define CAN_F16R1_FB27_Msk (0x1UL << CAN_F16R1_FB27_Pos) /*!< 0x08000000 */ |
| 8012 | #define CAN_F16R1_FB27_Msk (0x1UL << CAN_F16R1_FB27_Pos) /*!< 0x08000000 */ |
8012 | #define CAN_F16R1_FB27 CAN_F16R1_FB27_Msk /*!< Filter bit 27 */ |
| 8013 | #define CAN_F16R1_FB27 CAN_F16R1_FB27_Msk /*!< Filter bit 27 */ |
8013 | #define CAN_F16R1_FB28_Pos (28U) |
| 8014 | #define CAN_F16R1_FB28_Pos (28U) |
8014 | #define CAN_F16R1_FB28_Msk (0x1UL << CAN_F16R1_FB28_Pos) /*!< 0x10000000 */ |
| 8015 | #define CAN_F16R1_FB28_Msk (0x1UL << CAN_F16R1_FB28_Pos) /*!< 0x10000000 */ |
8015 | #define CAN_F16R1_FB28 CAN_F16R1_FB28_Msk /*!< Filter bit 28 */ |
| 8016 | #define CAN_F16R1_FB28 CAN_F16R1_FB28_Msk /*!< Filter bit 28 */ |
8016 | #define CAN_F16R1_FB29_Pos (29U) |
| 8017 | #define CAN_F16R1_FB29_Pos (29U) |
8017 | #define CAN_F16R1_FB29_Msk (0x1UL << CAN_F16R1_FB29_Pos) /*!< 0x20000000 */ |
| 8018 | #define CAN_F16R1_FB29_Msk (0x1UL << CAN_F16R1_FB29_Pos) /*!< 0x20000000 */ |
8018 | #define CAN_F16R1_FB29 CAN_F16R1_FB29_Msk /*!< Filter bit 29 */ |
| 8019 | #define CAN_F16R1_FB29 CAN_F16R1_FB29_Msk /*!< Filter bit 29 */ |
8019 | #define CAN_F16R1_FB30_Pos (30U) |
| 8020 | #define CAN_F16R1_FB30_Pos (30U) |
8020 | #define CAN_F16R1_FB30_Msk (0x1UL << CAN_F16R1_FB30_Pos) /*!< 0x40000000 */ |
| 8021 | #define CAN_F16R1_FB30_Msk (0x1UL << CAN_F16R1_FB30_Pos) /*!< 0x40000000 */ |
8021 | #define CAN_F16R1_FB30 CAN_F16R1_FB30_Msk /*!< Filter bit 30 */ |
| 8022 | #define CAN_F16R1_FB30 CAN_F16R1_FB30_Msk /*!< Filter bit 30 */ |
8022 | #define CAN_F16R1_FB31_Pos (31U) |
| 8023 | #define CAN_F16R1_FB31_Pos (31U) |
8023 | #define CAN_F16R1_FB31_Msk (0x1UL << CAN_F16R1_FB31_Pos) /*!< 0x80000000 */ |
| 8024 | #define CAN_F16R1_FB31_Msk (0x1UL << CAN_F16R1_FB31_Pos) /*!< 0x80000000 */ |
8024 | #define CAN_F16R1_FB31 CAN_F16R1_FB31_Msk /*!< Filter bit 31 */ |
| 8025 | #define CAN_F16R1_FB31 CAN_F16R1_FB31_Msk /*!< Filter bit 31 */ |
8025 | |
| 8026 | 8026 | /******************* Bit definition for CAN_F17R1 register ******************/ |
|
| 8027 | /******************* Bit definition for CAN_F17R1 register ******************/ |
8027 | #define CAN_F17R1_FB0_Pos (0U) |
| 8028 | #define CAN_F17R1_FB0_Pos (0U) |
8028 | #define CAN_F17R1_FB0_Msk (0x1UL << CAN_F17R1_FB0_Pos) /*!< 0x00000001 */ |
| 8029 | #define CAN_F17R1_FB0_Msk (0x1UL << CAN_F17R1_FB0_Pos) /*!< 0x00000001 */ |
8029 | #define CAN_F17R1_FB0 CAN_F17R1_FB0_Msk /*!< Filter bit 0 */ |
| 8030 | #define CAN_F17R1_FB0 CAN_F17R1_FB0_Msk /*!< Filter bit 0 */ |
8030 | #define CAN_F17R1_FB1_Pos (1U) |
| 8031 | #define CAN_F17R1_FB1_Pos (1U) |
8031 | #define CAN_F17R1_FB1_Msk (0x1UL << CAN_F17R1_FB1_Pos) /*!< 0x00000002 */ |
| 8032 | #define CAN_F17R1_FB1_Msk (0x1UL << CAN_F17R1_FB1_Pos) /*!< 0x00000002 */ |
8032 | #define CAN_F17R1_FB1 CAN_F17R1_FB1_Msk /*!< Filter bit 1 */ |
| 8033 | #define CAN_F17R1_FB1 CAN_F17R1_FB1_Msk /*!< Filter bit 1 */ |
8033 | #define CAN_F17R1_FB2_Pos (2U) |
| 8034 | #define CAN_F17R1_FB2_Pos (2U) |
8034 | #define CAN_F17R1_FB2_Msk (0x1UL << CAN_F17R1_FB2_Pos) /*!< 0x00000004 */ |
| 8035 | #define CAN_F17R1_FB2_Msk (0x1UL << CAN_F17R1_FB2_Pos) /*!< 0x00000004 */ |
8035 | #define CAN_F17R1_FB2 CAN_F17R1_FB2_Msk /*!< Filter bit 2 */ |
| 8036 | #define CAN_F17R1_FB2 CAN_F17R1_FB2_Msk /*!< Filter bit 2 */ |
8036 | #define CAN_F17R1_FB3_Pos (3U) |
| 8037 | #define CAN_F17R1_FB3_Pos (3U) |
8037 | #define CAN_F17R1_FB3_Msk (0x1UL << CAN_F17R1_FB3_Pos) /*!< 0x00000008 */ |
| 8038 | #define CAN_F17R1_FB3_Msk (0x1UL << CAN_F17R1_FB3_Pos) /*!< 0x00000008 */ |
8038 | #define CAN_F17R1_FB3 CAN_F17R1_FB3_Msk /*!< Filter bit 3 */ |
| 8039 | #define CAN_F17R1_FB3 CAN_F17R1_FB3_Msk /*!< Filter bit 3 */ |
8039 | #define CAN_F17R1_FB4_Pos (4U) |
| 8040 | #define CAN_F17R1_FB4_Pos (4U) |
8040 | #define CAN_F17R1_FB4_Msk (0x1UL << CAN_F17R1_FB4_Pos) /*!< 0x00000010 */ |
| 8041 | #define CAN_F17R1_FB4_Msk (0x1UL << CAN_F17R1_FB4_Pos) /*!< 0x00000010 */ |
8041 | #define CAN_F17R1_FB4 CAN_F17R1_FB4_Msk /*!< Filter bit 4 */ |
| 8042 | #define CAN_F17R1_FB4 CAN_F17R1_FB4_Msk /*!< Filter bit 4 */ |
8042 | #define CAN_F17R1_FB5_Pos (5U) |
| 8043 | #define CAN_F17R1_FB5_Pos (5U) |
8043 | #define CAN_F17R1_FB5_Msk (0x1UL << CAN_F17R1_FB5_Pos) /*!< 0x00000020 */ |
| 8044 | #define CAN_F17R1_FB5_Msk (0x1UL << CAN_F17R1_FB5_Pos) /*!< 0x00000020 */ |
8044 | #define CAN_F17R1_FB5 CAN_F17R1_FB5_Msk /*!< Filter bit 5 */ |
| 8045 | #define CAN_F17R1_FB5 CAN_F17R1_FB5_Msk /*!< Filter bit 5 */ |
8045 | #define CAN_F17R1_FB6_Pos (6U) |
| 8046 | #define CAN_F17R1_FB6_Pos (6U) |
8046 | #define CAN_F17R1_FB6_Msk (0x1UL << CAN_F17R1_FB6_Pos) /*!< 0x00000040 */ |
| 8047 | #define CAN_F17R1_FB6_Msk (0x1UL << CAN_F17R1_FB6_Pos) /*!< 0x00000040 */ |
8047 | #define CAN_F17R1_FB6 CAN_F17R1_FB6_Msk /*!< Filter bit 6 */ |
| 8048 | #define CAN_F17R1_FB6 CAN_F17R1_FB6_Msk /*!< Filter bit 6 */ |
8048 | #define CAN_F17R1_FB7_Pos (7U) |
| 8049 | #define CAN_F17R1_FB7_Pos (7U) |
8049 | #define CAN_F17R1_FB7_Msk (0x1UL << CAN_F17R1_FB7_Pos) /*!< 0x00000080 */ |
| 8050 | #define CAN_F17R1_FB7_Msk (0x1UL << CAN_F17R1_FB7_Pos) /*!< 0x00000080 */ |
8050 | #define CAN_F17R1_FB7 CAN_F17R1_FB7_Msk /*!< Filter bit 7 */ |
| 8051 | #define CAN_F17R1_FB7 CAN_F17R1_FB7_Msk /*!< Filter bit 7 */ |
8051 | #define CAN_F17R1_FB8_Pos (8U) |
| 8052 | #define CAN_F17R1_FB8_Pos (8U) |
8052 | #define CAN_F17R1_FB8_Msk (0x1UL << CAN_F17R1_FB8_Pos) /*!< 0x00000100 */ |
| 8053 | #define CAN_F17R1_FB8_Msk (0x1UL << CAN_F17R1_FB8_Pos) /*!< 0x00000100 */ |
8053 | #define CAN_F17R1_FB8 CAN_F17R1_FB8_Msk /*!< Filter bit 8 */ |
| 8054 | #define CAN_F17R1_FB8 CAN_F17R1_FB8_Msk /*!< Filter bit 8 */ |
8054 | #define CAN_F17R1_FB9_Pos (9U) |
| 8055 | #define CAN_F17R1_FB9_Pos (9U) |
8055 | #define CAN_F17R1_FB9_Msk (0x1UL << CAN_F17R1_FB9_Pos) /*!< 0x00000200 */ |
| 8056 | #define CAN_F17R1_FB9_Msk (0x1UL << CAN_F17R1_FB9_Pos) /*!< 0x00000200 */ |
8056 | #define CAN_F17R1_FB9 CAN_F17R1_FB9_Msk /*!< Filter bit 9 */ |
| 8057 | #define CAN_F17R1_FB9 CAN_F17R1_FB9_Msk /*!< Filter bit 9 */ |
8057 | #define CAN_F17R1_FB10_Pos (10U) |
| 8058 | #define CAN_F17R1_FB10_Pos (10U) |
8058 | #define CAN_F17R1_FB10_Msk (0x1UL << CAN_F17R1_FB10_Pos) /*!< 0x00000400 */ |
| 8059 | #define CAN_F17R1_FB10_Msk (0x1UL << CAN_F17R1_FB10_Pos) /*!< 0x00000400 */ |
8059 | #define CAN_F17R1_FB10 CAN_F17R1_FB10_Msk /*!< Filter bit 10 */ |
| 8060 | #define CAN_F17R1_FB10 CAN_F17R1_FB10_Msk /*!< Filter bit 10 */ |
8060 | #define CAN_F17R1_FB11_Pos (11U) |
| 8061 | #define CAN_F17R1_FB11_Pos (11U) |
8061 | #define CAN_F17R1_FB11_Msk (0x1UL << CAN_F17R1_FB11_Pos) /*!< 0x00000800 */ |
| 8062 | #define CAN_F17R1_FB11_Msk (0x1UL << CAN_F17R1_FB11_Pos) /*!< 0x00000800 */ |
8062 | #define CAN_F17R1_FB11 CAN_F17R1_FB11_Msk /*!< Filter bit 11 */ |
| 8063 | #define CAN_F17R1_FB11 CAN_F17R1_FB11_Msk /*!< Filter bit 11 */ |
8063 | #define CAN_F17R1_FB12_Pos (12U) |
| 8064 | #define CAN_F17R1_FB12_Pos (12U) |
8064 | #define CAN_F17R1_FB12_Msk (0x1UL << CAN_F17R1_FB12_Pos) /*!< 0x00001000 */ |
| 8065 | #define CAN_F17R1_FB12_Msk (0x1UL << CAN_F17R1_FB12_Pos) /*!< 0x00001000 */ |
8065 | #define CAN_F17R1_FB12 CAN_F17R1_FB12_Msk /*!< Filter bit 12 */ |
| 8066 | #define CAN_F17R1_FB12 CAN_F17R1_FB12_Msk /*!< Filter bit 12 */ |
8066 | #define CAN_F17R1_FB13_Pos (13U) |
| 8067 | #define CAN_F17R1_FB13_Pos (13U) |
8067 | #define CAN_F17R1_FB13_Msk (0x1UL << CAN_F17R1_FB13_Pos) /*!< 0x00002000 */ |
| 8068 | #define CAN_F17R1_FB13_Msk (0x1UL << CAN_F17R1_FB13_Pos) /*!< 0x00002000 */ |
8068 | #define CAN_F17R1_FB13 CAN_F17R1_FB13_Msk /*!< Filter bit 13 */ |
| 8069 | #define CAN_F17R1_FB13 CAN_F17R1_FB13_Msk /*!< Filter bit 13 */ |
8069 | #define CAN_F17R1_FB14_Pos (14U) |
| 8070 | #define CAN_F17R1_FB14_Pos (14U) |
8070 | #define CAN_F17R1_FB14_Msk (0x1UL << CAN_F17R1_FB14_Pos) /*!< 0x00004000 */ |
| 8071 | #define CAN_F17R1_FB14_Msk (0x1UL << CAN_F17R1_FB14_Pos) /*!< 0x00004000 */ |
8071 | #define CAN_F17R1_FB14 CAN_F17R1_FB14_Msk /*!< Filter bit 14 */ |
| 8072 | #define CAN_F17R1_FB14 CAN_F17R1_FB14_Msk /*!< Filter bit 14 */ |
8072 | #define CAN_F17R1_FB15_Pos (15U) |
| 8073 | #define CAN_F17R1_FB15_Pos (15U) |
8073 | #define CAN_F17R1_FB15_Msk (0x1UL << CAN_F17R1_FB15_Pos) /*!< 0x00008000 */ |
| 8074 | #define CAN_F17R1_FB15_Msk (0x1UL << CAN_F17R1_FB15_Pos) /*!< 0x00008000 */ |
8074 | #define CAN_F17R1_FB15 CAN_F17R1_FB15_Msk /*!< Filter bit 15 */ |
| 8075 | #define CAN_F17R1_FB15 CAN_F17R1_FB15_Msk /*!< Filter bit 15 */ |
8075 | #define CAN_F17R1_FB16_Pos (16U) |
| 8076 | #define CAN_F17R1_FB16_Pos (16U) |
8076 | #define CAN_F17R1_FB16_Msk (0x1UL << CAN_F17R1_FB16_Pos) /*!< 0x00010000 */ |
| 8077 | #define CAN_F17R1_FB16_Msk (0x1UL << CAN_F17R1_FB16_Pos) /*!< 0x00010000 */ |
8077 | #define CAN_F17R1_FB16 CAN_F17R1_FB16_Msk /*!< Filter bit 16 */ |
| 8078 | #define CAN_F17R1_FB16 CAN_F17R1_FB16_Msk /*!< Filter bit 16 */ |
8078 | #define CAN_F17R1_FB17_Pos (17U) |
| 8079 | #define CAN_F17R1_FB17_Pos (17U) |
8079 | #define CAN_F17R1_FB17_Msk (0x1UL << CAN_F17R1_FB17_Pos) /*!< 0x00020000 */ |
| 8080 | #define CAN_F17R1_FB17_Msk (0x1UL << CAN_F17R1_FB17_Pos) /*!< 0x00020000 */ |
8080 | #define CAN_F17R1_FB17 CAN_F17R1_FB17_Msk /*!< Filter bit 17 */ |
| 8081 | #define CAN_F17R1_FB17 CAN_F17R1_FB17_Msk /*!< Filter bit 17 */ |
8081 | #define CAN_F17R1_FB18_Pos (18U) |
| 8082 | #define CAN_F17R1_FB18_Pos (18U) |
8082 | #define CAN_F17R1_FB18_Msk (0x1UL << CAN_F17R1_FB18_Pos) /*!< 0x00040000 */ |
| 8083 | #define CAN_F17R1_FB18_Msk (0x1UL << CAN_F17R1_FB18_Pos) /*!< 0x00040000 */ |
8083 | #define CAN_F17R1_FB18 CAN_F17R1_FB18_Msk /*!< Filter bit 18 */ |
| 8084 | #define CAN_F17R1_FB18 CAN_F17R1_FB18_Msk /*!< Filter bit 18 */ |
8084 | #define CAN_F17R1_FB19_Pos (19U) |
| 8085 | #define CAN_F17R1_FB19_Pos (19U) |
8085 | #define CAN_F17R1_FB19_Msk (0x1UL << CAN_F17R1_FB19_Pos) /*!< 0x00080000 */ |
| 8086 | #define CAN_F17R1_FB19_Msk (0x1UL << CAN_F17R1_FB19_Pos) /*!< 0x00080000 */ |
8086 | #define CAN_F17R1_FB19 CAN_F17R1_FB19_Msk /*!< Filter bit 19 */ |
| 8087 | #define CAN_F17R1_FB19 CAN_F17R1_FB19_Msk /*!< Filter bit 19 */ |
8087 | #define CAN_F17R1_FB20_Pos (20U) |
| 8088 | #define CAN_F17R1_FB20_Pos (20U) |
8088 | #define CAN_F17R1_FB20_Msk (0x1UL << CAN_F17R1_FB20_Pos) /*!< 0x00100000 */ |
| 8089 | #define CAN_F17R1_FB20_Msk (0x1UL << CAN_F17R1_FB20_Pos) /*!< 0x00100000 */ |
8089 | #define CAN_F17R1_FB20 CAN_F17R1_FB20_Msk /*!< Filter bit 20 */ |
| 8090 | #define CAN_F17R1_FB20 CAN_F17R1_FB20_Msk /*!< Filter bit 20 */ |
8090 | #define CAN_F17R1_FB21_Pos (21U) |
| 8091 | #define CAN_F17R1_FB21_Pos (21U) |
8091 | #define CAN_F17R1_FB21_Msk (0x1UL << CAN_F17R1_FB21_Pos) /*!< 0x00200000 */ |
| 8092 | #define CAN_F17R1_FB21_Msk (0x1UL << CAN_F17R1_FB21_Pos) /*!< 0x00200000 */ |
8092 | #define CAN_F17R1_FB21 CAN_F17R1_FB21_Msk /*!< Filter bit 21 */ |
| 8093 | #define CAN_F17R1_FB21 CAN_F17R1_FB21_Msk /*!< Filter bit 21 */ |
8093 | #define CAN_F17R1_FB22_Pos (22U) |
| 8094 | #define CAN_F17R1_FB22_Pos (22U) |
8094 | #define CAN_F17R1_FB22_Msk (0x1UL << CAN_F17R1_FB22_Pos) /*!< 0x00400000 */ |
| 8095 | #define CAN_F17R1_FB22_Msk (0x1UL << CAN_F17R1_FB22_Pos) /*!< 0x00400000 */ |
8095 | #define CAN_F17R1_FB22 CAN_F17R1_FB22_Msk /*!< Filter bit 22 */ |
| 8096 | #define CAN_F17R1_FB22 CAN_F17R1_FB22_Msk /*!< Filter bit 22 */ |
8096 | #define CAN_F17R1_FB23_Pos (23U) |
| 8097 | #define CAN_F17R1_FB23_Pos (23U) |
8097 | #define CAN_F17R1_FB23_Msk (0x1UL << CAN_F17R1_FB23_Pos) /*!< 0x00800000 */ |
| 8098 | #define CAN_F17R1_FB23_Msk (0x1UL << CAN_F17R1_FB23_Pos) /*!< 0x00800000 */ |
8098 | #define CAN_F17R1_FB23 CAN_F17R1_FB23_Msk /*!< Filter bit 23 */ |
| 8099 | #define CAN_F17R1_FB23 CAN_F17R1_FB23_Msk /*!< Filter bit 23 */ |
8099 | #define CAN_F17R1_FB24_Pos (24U) |
| 8100 | #define CAN_F17R1_FB24_Pos (24U) |
8100 | #define CAN_F17R1_FB24_Msk (0x1UL << CAN_F17R1_FB24_Pos) /*!< 0x01000000 */ |
| 8101 | #define CAN_F17R1_FB24_Msk (0x1UL << CAN_F17R1_FB24_Pos) /*!< 0x01000000 */ |
8101 | #define CAN_F17R1_FB24 CAN_F17R1_FB24_Msk /*!< Filter bit 24 */ |
| 8102 | #define CAN_F17R1_FB24 CAN_F17R1_FB24_Msk /*!< Filter bit 24 */ |
8102 | #define CAN_F17R1_FB25_Pos (25U) |
| 8103 | #define CAN_F17R1_FB25_Pos (25U) |
8103 | #define CAN_F17R1_FB25_Msk (0x1UL << CAN_F17R1_FB25_Pos) /*!< 0x02000000 */ |
| 8104 | #define CAN_F17R1_FB25_Msk (0x1UL << CAN_F17R1_FB25_Pos) /*!< 0x02000000 */ |
8104 | #define CAN_F17R1_FB25 CAN_F17R1_FB25_Msk /*!< Filter bit 25 */ |
| 8105 | #define CAN_F17R1_FB25 CAN_F17R1_FB25_Msk /*!< Filter bit 25 */ |
8105 | #define CAN_F17R1_FB26_Pos (26U) |
| 8106 | #define CAN_F17R1_FB26_Pos (26U) |
8106 | #define CAN_F17R1_FB26_Msk (0x1UL << CAN_F17R1_FB26_Pos) /*!< 0x04000000 */ |
| 8107 | #define CAN_F17R1_FB26_Msk (0x1UL << CAN_F17R1_FB26_Pos) /*!< 0x04000000 */ |
8107 | #define CAN_F17R1_FB26 CAN_F17R1_FB26_Msk /*!< Filter bit 26 */ |
| 8108 | #define CAN_F17R1_FB26 CAN_F17R1_FB26_Msk /*!< Filter bit 26 */ |
8108 | #define CAN_F17R1_FB27_Pos (27U) |
| 8109 | #define CAN_F17R1_FB27_Pos (27U) |
8109 | #define CAN_F17R1_FB27_Msk (0x1UL << CAN_F17R1_FB27_Pos) /*!< 0x08000000 */ |
| 8110 | #define CAN_F17R1_FB27_Msk (0x1UL << CAN_F17R1_FB27_Pos) /*!< 0x08000000 */ |
8110 | #define CAN_F17R1_FB27 CAN_F17R1_FB27_Msk /*!< Filter bit 27 */ |
| 8111 | #define CAN_F17R1_FB27 CAN_F17R1_FB27_Msk /*!< Filter bit 27 */ |
8111 | #define CAN_F17R1_FB28_Pos (28U) |
| 8112 | #define CAN_F17R1_FB28_Pos (28U) |
8112 | #define CAN_F17R1_FB28_Msk (0x1UL << CAN_F17R1_FB28_Pos) /*!< 0x10000000 */ |
| 8113 | #define CAN_F17R1_FB28_Msk (0x1UL << CAN_F17R1_FB28_Pos) /*!< 0x10000000 */ |
8113 | #define CAN_F17R1_FB28 CAN_F17R1_FB28_Msk /*!< Filter bit 28 */ |
| 8114 | #define CAN_F17R1_FB28 CAN_F17R1_FB28_Msk /*!< Filter bit 28 */ |
8114 | #define CAN_F17R1_FB29_Pos (29U) |
| 8115 | #define CAN_F17R1_FB29_Pos (29U) |
8115 | #define CAN_F17R1_FB29_Msk (0x1UL << CAN_F17R1_FB29_Pos) /*!< 0x20000000 */ |
| 8116 | #define CAN_F17R1_FB29_Msk (0x1UL << CAN_F17R1_FB29_Pos) /*!< 0x20000000 */ |
8116 | #define CAN_F17R1_FB29 CAN_F17R1_FB29_Msk /*!< Filter bit 29 */ |
| 8117 | #define CAN_F17R1_FB29 CAN_F17R1_FB29_Msk /*!< Filter bit 29 */ |
8117 | #define CAN_F17R1_FB30_Pos (30U) |
| 8118 | #define CAN_F17R1_FB30_Pos (30U) |
8118 | #define CAN_F17R1_FB30_Msk (0x1UL << CAN_F17R1_FB30_Pos) /*!< 0x40000000 */ |
| 8119 | #define CAN_F17R1_FB30_Msk (0x1UL << CAN_F17R1_FB30_Pos) /*!< 0x40000000 */ |
8119 | #define CAN_F17R1_FB30 CAN_F17R1_FB30_Msk /*!< Filter bit 30 */ |
| 8120 | #define CAN_F17R1_FB30 CAN_F17R1_FB30_Msk /*!< Filter bit 30 */ |
8120 | #define CAN_F17R1_FB31_Pos (31U) |
| 8121 | #define CAN_F17R1_FB31_Pos (31U) |
8121 | #define CAN_F17R1_FB31_Msk (0x1UL << CAN_F17R1_FB31_Pos) /*!< 0x80000000 */ |
| 8122 | #define CAN_F17R1_FB31_Msk (0x1UL << CAN_F17R1_FB31_Pos) /*!< 0x80000000 */ |
8122 | #define CAN_F17R1_FB31 CAN_F17R1_FB31_Msk /*!< Filter bit 31 */ |
| 8123 | #define CAN_F17R1_FB31 CAN_F17R1_FB31_Msk /*!< Filter bit 31 */ |
8123 | |
| 8124 | 8124 | /******************* Bit definition for CAN_F18R1 register ******************/ |
|
| 8125 | /******************* Bit definition for CAN_F18R1 register ******************/ |
8125 | #define CAN_F18R1_FB0_Pos (0U) |
| 8126 | #define CAN_F18R1_FB0_Pos (0U) |
8126 | #define CAN_F18R1_FB0_Msk (0x1UL << CAN_F18R1_FB0_Pos) /*!< 0x00000001 */ |
| 8127 | #define CAN_F18R1_FB0_Msk (0x1UL << CAN_F18R1_FB0_Pos) /*!< 0x00000001 */ |
8127 | #define CAN_F18R1_FB0 CAN_F18R1_FB0_Msk /*!< Filter bit 0 */ |
| 8128 | #define CAN_F18R1_FB0 CAN_F18R1_FB0_Msk /*!< Filter bit 0 */ |
8128 | #define CAN_F18R1_FB1_Pos (1U) |
| 8129 | #define CAN_F18R1_FB1_Pos (1U) |
8129 | #define CAN_F18R1_FB1_Msk (0x1UL << CAN_F18R1_FB1_Pos) /*!< 0x00000002 */ |
| 8130 | #define CAN_F18R1_FB1_Msk (0x1UL << CAN_F18R1_FB1_Pos) /*!< 0x00000002 */ |
8130 | #define CAN_F18R1_FB1 CAN_F18R1_FB1_Msk /*!< Filter bit 1 */ |
| 8131 | #define CAN_F18R1_FB1 CAN_F18R1_FB1_Msk /*!< Filter bit 1 */ |
8131 | #define CAN_F18R1_FB2_Pos (2U) |
| 8132 | #define CAN_F18R1_FB2_Pos (2U) |
8132 | #define CAN_F18R1_FB2_Msk (0x1UL << CAN_F18R1_FB2_Pos) /*!< 0x00000004 */ |
| 8133 | #define CAN_F18R1_FB2_Msk (0x1UL << CAN_F18R1_FB2_Pos) /*!< 0x00000004 */ |
8133 | #define CAN_F18R1_FB2 CAN_F18R1_FB2_Msk /*!< Filter bit 2 */ |
| 8134 | #define CAN_F18R1_FB2 CAN_F18R1_FB2_Msk /*!< Filter bit 2 */ |
8134 | #define CAN_F18R1_FB3_Pos (3U) |
| 8135 | #define CAN_F18R1_FB3_Pos (3U) |
8135 | #define CAN_F18R1_FB3_Msk (0x1UL << CAN_F18R1_FB3_Pos) /*!< 0x00000008 */ |
| 8136 | #define CAN_F18R1_FB3_Msk (0x1UL << CAN_F18R1_FB3_Pos) /*!< 0x00000008 */ |
8136 | #define CAN_F18R1_FB3 CAN_F18R1_FB3_Msk /*!< Filter bit 3 */ |
| 8137 | #define CAN_F18R1_FB3 CAN_F18R1_FB3_Msk /*!< Filter bit 3 */ |
8137 | #define CAN_F18R1_FB4_Pos (4U) |
| 8138 | #define CAN_F18R1_FB4_Pos (4U) |
8138 | #define CAN_F18R1_FB4_Msk (0x1UL << CAN_F18R1_FB4_Pos) /*!< 0x00000010 */ |
| 8139 | #define CAN_F18R1_FB4_Msk (0x1UL << CAN_F18R1_FB4_Pos) /*!< 0x00000010 */ |
8139 | #define CAN_F18R1_FB4 CAN_F18R1_FB4_Msk /*!< Filter bit 4 */ |
| 8140 | #define CAN_F18R1_FB4 CAN_F18R1_FB4_Msk /*!< Filter bit 4 */ |
8140 | #define CAN_F18R1_FB5_Pos (5U) |
| 8141 | #define CAN_F18R1_FB5_Pos (5U) |
8141 | #define CAN_F18R1_FB5_Msk (0x1UL << CAN_F18R1_FB5_Pos) /*!< 0x00000020 */ |
| 8142 | #define CAN_F18R1_FB5_Msk (0x1UL << CAN_F18R1_FB5_Pos) /*!< 0x00000020 */ |
8142 | #define CAN_F18R1_FB5 CAN_F18R1_FB5_Msk /*!< Filter bit 5 */ |
| 8143 | #define CAN_F18R1_FB5 CAN_F18R1_FB5_Msk /*!< Filter bit 5 */ |
8143 | #define CAN_F18R1_FB6_Pos (6U) |
| 8144 | #define CAN_F18R1_FB6_Pos (6U) |
8144 | #define CAN_F18R1_FB6_Msk (0x1UL << CAN_F18R1_FB6_Pos) /*!< 0x00000040 */ |
| 8145 | #define CAN_F18R1_FB6_Msk (0x1UL << CAN_F18R1_FB6_Pos) /*!< 0x00000040 */ |
8145 | #define CAN_F18R1_FB6 CAN_F18R1_FB6_Msk /*!< Filter bit 6 */ |
| 8146 | #define CAN_F18R1_FB6 CAN_F18R1_FB6_Msk /*!< Filter bit 6 */ |
8146 | #define CAN_F18R1_FB7_Pos (7U) |
| 8147 | #define CAN_F18R1_FB7_Pos (7U) |
8147 | #define CAN_F18R1_FB7_Msk (0x1UL << CAN_F18R1_FB7_Pos) /*!< 0x00000080 */ |
| 8148 | #define CAN_F18R1_FB7_Msk (0x1UL << CAN_F18R1_FB7_Pos) /*!< 0x00000080 */ |
8148 | #define CAN_F18R1_FB7 CAN_F18R1_FB7_Msk /*!< Filter bit 7 */ |
| 8149 | #define CAN_F18R1_FB7 CAN_F18R1_FB7_Msk /*!< Filter bit 7 */ |
8149 | #define CAN_F18R1_FB8_Pos (8U) |
| 8150 | #define CAN_F18R1_FB8_Pos (8U) |
8150 | #define CAN_F18R1_FB8_Msk (0x1UL << CAN_F18R1_FB8_Pos) /*!< 0x00000100 */ |
| 8151 | #define CAN_F18R1_FB8_Msk (0x1UL << CAN_F18R1_FB8_Pos) /*!< 0x00000100 */ |
8151 | #define CAN_F18R1_FB8 CAN_F18R1_FB8_Msk /*!< Filter bit 8 */ |
| 8152 | #define CAN_F18R1_FB8 CAN_F18R1_FB8_Msk /*!< Filter bit 8 */ |
8152 | #define CAN_F18R1_FB9_Pos (9U) |
| 8153 | #define CAN_F18R1_FB9_Pos (9U) |
8153 | #define CAN_F18R1_FB9_Msk (0x1UL << CAN_F18R1_FB9_Pos) /*!< 0x00000200 */ |
| 8154 | #define CAN_F18R1_FB9_Msk (0x1UL << CAN_F18R1_FB9_Pos) /*!< 0x00000200 */ |
8154 | #define CAN_F18R1_FB9 CAN_F18R1_FB9_Msk /*!< Filter bit 9 */ |
| 8155 | #define CAN_F18R1_FB9 CAN_F18R1_FB9_Msk /*!< Filter bit 9 */ |
8155 | #define CAN_F18R1_FB10_Pos (10U) |
| 8156 | #define CAN_F18R1_FB10_Pos (10U) |
8156 | #define CAN_F18R1_FB10_Msk (0x1UL << CAN_F18R1_FB10_Pos) /*!< 0x00000400 */ |
| 8157 | #define CAN_F18R1_FB10_Msk (0x1UL << CAN_F18R1_FB10_Pos) /*!< 0x00000400 */ |
8157 | #define CAN_F18R1_FB10 CAN_F18R1_FB10_Msk /*!< Filter bit 10 */ |
| 8158 | #define CAN_F18R1_FB10 CAN_F18R1_FB10_Msk /*!< Filter bit 10 */ |
8158 | #define CAN_F18R1_FB11_Pos (11U) |
| 8159 | #define CAN_F18R1_FB11_Pos (11U) |
8159 | #define CAN_F18R1_FB11_Msk (0x1UL << CAN_F18R1_FB11_Pos) /*!< 0x00000800 */ |
| 8160 | #define CAN_F18R1_FB11_Msk (0x1UL << CAN_F18R1_FB11_Pos) /*!< 0x00000800 */ |
8160 | #define CAN_F18R1_FB11 CAN_F18R1_FB11_Msk /*!< Filter bit 11 */ |
| 8161 | #define CAN_F18R1_FB11 CAN_F18R1_FB11_Msk /*!< Filter bit 11 */ |
8161 | #define CAN_F18R1_FB12_Pos (12U) |
| 8162 | #define CAN_F18R1_FB12_Pos (12U) |
8162 | #define CAN_F18R1_FB12_Msk (0x1UL << CAN_F18R1_FB12_Pos) /*!< 0x00001000 */ |
| 8163 | #define CAN_F18R1_FB12_Msk (0x1UL << CAN_F18R1_FB12_Pos) /*!< 0x00001000 */ |
8163 | #define CAN_F18R1_FB12 CAN_F18R1_FB12_Msk /*!< Filter bit 12 */ |
| 8164 | #define CAN_F18R1_FB12 CAN_F18R1_FB12_Msk /*!< Filter bit 12 */ |
8164 | #define CAN_F18R1_FB13_Pos (13U) |
| 8165 | #define CAN_F18R1_FB13_Pos (13U) |
8165 | #define CAN_F18R1_FB13_Msk (0x1UL << CAN_F18R1_FB13_Pos) /*!< 0x00002000 */ |
| 8166 | #define CAN_F18R1_FB13_Msk (0x1UL << CAN_F18R1_FB13_Pos) /*!< 0x00002000 */ |
8166 | #define CAN_F18R1_FB13 CAN_F18R1_FB13_Msk /*!< Filter bit 13 */ |
| 8167 | #define CAN_F18R1_FB13 CAN_F18R1_FB13_Msk /*!< Filter bit 13 */ |
8167 | #define CAN_F18R1_FB14_Pos (14U) |
| 8168 | #define CAN_F18R1_FB14_Pos (14U) |
8168 | #define CAN_F18R1_FB14_Msk (0x1UL << CAN_F18R1_FB14_Pos) /*!< 0x00004000 */ |
| 8169 | #define CAN_F18R1_FB14_Msk (0x1UL << CAN_F18R1_FB14_Pos) /*!< 0x00004000 */ |
8169 | #define CAN_F18R1_FB14 CAN_F18R1_FB14_Msk /*!< Filter bit 14 */ |
| 8170 | #define CAN_F18R1_FB14 CAN_F18R1_FB14_Msk /*!< Filter bit 14 */ |
8170 | #define CAN_F18R1_FB15_Pos (15U) |
| 8171 | #define CAN_F18R1_FB15_Pos (15U) |
8171 | #define CAN_F18R1_FB15_Msk (0x1UL << CAN_F18R1_FB15_Pos) /*!< 0x00008000 */ |
| 8172 | #define CAN_F18R1_FB15_Msk (0x1UL << CAN_F18R1_FB15_Pos) /*!< 0x00008000 */ |
8172 | #define CAN_F18R1_FB15 CAN_F18R1_FB15_Msk /*!< Filter bit 15 */ |
| 8173 | #define CAN_F18R1_FB15 CAN_F18R1_FB15_Msk /*!< Filter bit 15 */ |
8173 | #define CAN_F18R1_FB16_Pos (16U) |
| 8174 | #define CAN_F18R1_FB16_Pos (16U) |
8174 | #define CAN_F18R1_FB16_Msk (0x1UL << CAN_F18R1_FB16_Pos) /*!< 0x00010000 */ |
| 8175 | #define CAN_F18R1_FB16_Msk (0x1UL << CAN_F18R1_FB16_Pos) /*!< 0x00010000 */ |
8175 | #define CAN_F18R1_FB16 CAN_F18R1_FB16_Msk /*!< Filter bit 16 */ |
| 8176 | #define CAN_F18R1_FB16 CAN_F18R1_FB16_Msk /*!< Filter bit 16 */ |
8176 | #define CAN_F18R1_FB17_Pos (17U) |
| 8177 | #define CAN_F18R1_FB17_Pos (17U) |
8177 | #define CAN_F18R1_FB17_Msk (0x1UL << CAN_F18R1_FB17_Pos) /*!< 0x00020000 */ |
| 8178 | #define CAN_F18R1_FB17_Msk (0x1UL << CAN_F18R1_FB17_Pos) /*!< 0x00020000 */ |
8178 | #define CAN_F18R1_FB17 CAN_F18R1_FB17_Msk /*!< Filter bit 17 */ |
| 8179 | #define CAN_F18R1_FB17 CAN_F18R1_FB17_Msk /*!< Filter bit 17 */ |
8179 | #define CAN_F18R1_FB18_Pos (18U) |
| 8180 | #define CAN_F18R1_FB18_Pos (18U) |
8180 | #define CAN_F18R1_FB18_Msk (0x1UL << CAN_F18R1_FB18_Pos) /*!< 0x00040000 */ |
| 8181 | #define CAN_F18R1_FB18_Msk (0x1UL << CAN_F18R1_FB18_Pos) /*!< 0x00040000 */ |
8181 | #define CAN_F18R1_FB18 CAN_F18R1_FB18_Msk /*!< Filter bit 18 */ |
| 8182 | #define CAN_F18R1_FB18 CAN_F18R1_FB18_Msk /*!< Filter bit 18 */ |
8182 | #define CAN_F18R1_FB19_Pos (19U) |
| 8183 | #define CAN_F18R1_FB19_Pos (19U) |
8183 | #define CAN_F18R1_FB19_Msk (0x1UL << CAN_F18R1_FB19_Pos) /*!< 0x00080000 */ |
| 8184 | #define CAN_F18R1_FB19_Msk (0x1UL << CAN_F18R1_FB19_Pos) /*!< 0x00080000 */ |
8184 | #define CAN_F18R1_FB19 CAN_F18R1_FB19_Msk /*!< Filter bit 19 */ |
| 8185 | #define CAN_F18R1_FB19 CAN_F18R1_FB19_Msk /*!< Filter bit 19 */ |
8185 | #define CAN_F18R1_FB20_Pos (20U) |
| 8186 | #define CAN_F18R1_FB20_Pos (20U) |
8186 | #define CAN_F18R1_FB20_Msk (0x1UL << CAN_F18R1_FB20_Pos) /*!< 0x00100000 */ |
| 8187 | #define CAN_F18R1_FB20_Msk (0x1UL << CAN_F18R1_FB20_Pos) /*!< 0x00100000 */ |
8187 | #define CAN_F18R1_FB20 CAN_F18R1_FB20_Msk /*!< Filter bit 20 */ |
| 8188 | #define CAN_F18R1_FB20 CAN_F18R1_FB20_Msk /*!< Filter bit 20 */ |
8188 | #define CAN_F18R1_FB21_Pos (21U) |
| 8189 | #define CAN_F18R1_FB21_Pos (21U) |
8189 | #define CAN_F18R1_FB21_Msk (0x1UL << CAN_F18R1_FB21_Pos) /*!< 0x00200000 */ |
| 8190 | #define CAN_F18R1_FB21_Msk (0x1UL << CAN_F18R1_FB21_Pos) /*!< 0x00200000 */ |
8190 | #define CAN_F18R1_FB21 CAN_F18R1_FB21_Msk /*!< Filter bit 21 */ |
| 8191 | #define CAN_F18R1_FB21 CAN_F18R1_FB21_Msk /*!< Filter bit 21 */ |
8191 | #define CAN_F18R1_FB22_Pos (22U) |
| 8192 | #define CAN_F18R1_FB22_Pos (22U) |
8192 | #define CAN_F18R1_FB22_Msk (0x1UL << CAN_F18R1_FB22_Pos) /*!< 0x00400000 */ |
| 8193 | #define CAN_F18R1_FB22_Msk (0x1UL << CAN_F18R1_FB22_Pos) /*!< 0x00400000 */ |
8193 | #define CAN_F18R1_FB22 CAN_F18R1_FB22_Msk /*!< Filter bit 22 */ |
| 8194 | #define CAN_F18R1_FB22 CAN_F18R1_FB22_Msk /*!< Filter bit 22 */ |
8194 | #define CAN_F18R1_FB23_Pos (23U) |
| 8195 | #define CAN_F18R1_FB23_Pos (23U) |
8195 | #define CAN_F18R1_FB23_Msk (0x1UL << CAN_F18R1_FB23_Pos) /*!< 0x00800000 */ |
| 8196 | #define CAN_F18R1_FB23_Msk (0x1UL << CAN_F18R1_FB23_Pos) /*!< 0x00800000 */ |
8196 | #define CAN_F18R1_FB23 CAN_F18R1_FB23_Msk /*!< Filter bit 23 */ |
| 8197 | #define CAN_F18R1_FB23 CAN_F18R1_FB23_Msk /*!< Filter bit 23 */ |
8197 | #define CAN_F18R1_FB24_Pos (24U) |
| 8198 | #define CAN_F18R1_FB24_Pos (24U) |
8198 | #define CAN_F18R1_FB24_Msk (0x1UL << CAN_F18R1_FB24_Pos) /*!< 0x01000000 */ |
| 8199 | #define CAN_F18R1_FB24_Msk (0x1UL << CAN_F18R1_FB24_Pos) /*!< 0x01000000 */ |
8199 | #define CAN_F18R1_FB24 CAN_F18R1_FB24_Msk /*!< Filter bit 24 */ |
| 8200 | #define CAN_F18R1_FB24 CAN_F18R1_FB24_Msk /*!< Filter bit 24 */ |
8200 | #define CAN_F18R1_FB25_Pos (25U) |
| 8201 | #define CAN_F18R1_FB25_Pos (25U) |
8201 | #define CAN_F18R1_FB25_Msk (0x1UL << CAN_F18R1_FB25_Pos) /*!< 0x02000000 */ |
| 8202 | #define CAN_F18R1_FB25_Msk (0x1UL << CAN_F18R1_FB25_Pos) /*!< 0x02000000 */ |
8202 | #define CAN_F18R1_FB25 CAN_F18R1_FB25_Msk /*!< Filter bit 25 */ |
| 8203 | #define CAN_F18R1_FB25 CAN_F18R1_FB25_Msk /*!< Filter bit 25 */ |
8203 | #define CAN_F18R1_FB26_Pos (26U) |
| 8204 | #define CAN_F18R1_FB26_Pos (26U) |
8204 | #define CAN_F18R1_FB26_Msk (0x1UL << CAN_F18R1_FB26_Pos) /*!< 0x04000000 */ |
| 8205 | #define CAN_F18R1_FB26_Msk (0x1UL << CAN_F18R1_FB26_Pos) /*!< 0x04000000 */ |
8205 | #define CAN_F18R1_FB26 CAN_F18R1_FB26_Msk /*!< Filter bit 26 */ |
| 8206 | #define CAN_F18R1_FB26 CAN_F18R1_FB26_Msk /*!< Filter bit 26 */ |
8206 | #define CAN_F18R1_FB27_Pos (27U) |
| 8207 | #define CAN_F18R1_FB27_Pos (27U) |
8207 | #define CAN_F18R1_FB27_Msk (0x1UL << CAN_F18R1_FB27_Pos) /*!< 0x08000000 */ |
| 8208 | #define CAN_F18R1_FB27_Msk (0x1UL << CAN_F18R1_FB27_Pos) /*!< 0x08000000 */ |
8208 | #define CAN_F18R1_FB27 CAN_F18R1_FB27_Msk /*!< Filter bit 27 */ |
| 8209 | #define CAN_F18R1_FB27 CAN_F18R1_FB27_Msk /*!< Filter bit 27 */ |
8209 | #define CAN_F18R1_FB28_Pos (28U) |
| 8210 | #define CAN_F18R1_FB28_Pos (28U) |
8210 | #define CAN_F18R1_FB28_Msk (0x1UL << CAN_F18R1_FB28_Pos) /*!< 0x10000000 */ |
| 8211 | #define CAN_F18R1_FB28_Msk (0x1UL << CAN_F18R1_FB28_Pos) /*!< 0x10000000 */ |
8211 | #define CAN_F18R1_FB28 CAN_F18R1_FB28_Msk /*!< Filter bit 28 */ |
| 8212 | #define CAN_F18R1_FB28 CAN_F18R1_FB28_Msk /*!< Filter bit 28 */ |
8212 | #define CAN_F18R1_FB29_Pos (29U) |
| 8213 | #define CAN_F18R1_FB29_Pos (29U) |
8213 | #define CAN_F18R1_FB29_Msk (0x1UL << CAN_F18R1_FB29_Pos) /*!< 0x20000000 */ |
| 8214 | #define CAN_F18R1_FB29_Msk (0x1UL << CAN_F18R1_FB29_Pos) /*!< 0x20000000 */ |
8214 | #define CAN_F18R1_FB29 CAN_F18R1_FB29_Msk /*!< Filter bit 29 */ |
| 8215 | #define CAN_F18R1_FB29 CAN_F18R1_FB29_Msk /*!< Filter bit 29 */ |
8215 | #define CAN_F18R1_FB30_Pos (30U) |
| 8216 | #define CAN_F18R1_FB30_Pos (30U) |
8216 | #define CAN_F18R1_FB30_Msk (0x1UL << CAN_F18R1_FB30_Pos) /*!< 0x40000000 */ |
| 8217 | #define CAN_F18R1_FB30_Msk (0x1UL << CAN_F18R1_FB30_Pos) /*!< 0x40000000 */ |
8217 | #define CAN_F18R1_FB30 CAN_F18R1_FB30_Msk /*!< Filter bit 30 */ |
| 8218 | #define CAN_F18R1_FB30 CAN_F18R1_FB30_Msk /*!< Filter bit 30 */ |
8218 | #define CAN_F18R1_FB31_Pos (31U) |
| 8219 | #define CAN_F18R1_FB31_Pos (31U) |
8219 | #define CAN_F18R1_FB31_Msk (0x1UL << CAN_F18R1_FB31_Pos) /*!< 0x80000000 */ |
| 8220 | #define CAN_F18R1_FB31_Msk (0x1UL << CAN_F18R1_FB31_Pos) /*!< 0x80000000 */ |
8220 | #define CAN_F18R1_FB31 CAN_F18R1_FB31_Msk /*!< Filter bit 31 */ |
| 8221 | #define CAN_F18R1_FB31 CAN_F18R1_FB31_Msk /*!< Filter bit 31 */ |
8221 | |
| 8222 | 8222 | /******************* Bit definition for CAN_F19R1 register ******************/ |
|
| 8223 | /******************* Bit definition for CAN_F19R1 register ******************/ |
8223 | #define CAN_F19R1_FB0_Pos (0U) |
| 8224 | #define CAN_F19R1_FB0_Pos (0U) |
8224 | #define CAN_F19R1_FB0_Msk (0x1UL << CAN_F19R1_FB0_Pos) /*!< 0x00000001 */ |
| 8225 | #define CAN_F19R1_FB0_Msk (0x1UL << CAN_F19R1_FB0_Pos) /*!< 0x00000001 */ |
8225 | #define CAN_F19R1_FB0 CAN_F19R1_FB0_Msk /*!< Filter bit 0 */ |
| 8226 | #define CAN_F19R1_FB0 CAN_F19R1_FB0_Msk /*!< Filter bit 0 */ |
8226 | #define CAN_F19R1_FB1_Pos (1U) |
| 8227 | #define CAN_F19R1_FB1_Pos (1U) |
8227 | #define CAN_F19R1_FB1_Msk (0x1UL << CAN_F19R1_FB1_Pos) /*!< 0x00000002 */ |
| 8228 | #define CAN_F19R1_FB1_Msk (0x1UL << CAN_F19R1_FB1_Pos) /*!< 0x00000002 */ |
8228 | #define CAN_F19R1_FB1 CAN_F19R1_FB1_Msk /*!< Filter bit 1 */ |
| 8229 | #define CAN_F19R1_FB1 CAN_F19R1_FB1_Msk /*!< Filter bit 1 */ |
8229 | #define CAN_F19R1_FB2_Pos (2U) |
| 8230 | #define CAN_F19R1_FB2_Pos (2U) |
8230 | #define CAN_F19R1_FB2_Msk (0x1UL << CAN_F19R1_FB2_Pos) /*!< 0x00000004 */ |
| 8231 | #define CAN_F19R1_FB2_Msk (0x1UL << CAN_F19R1_FB2_Pos) /*!< 0x00000004 */ |
8231 | #define CAN_F19R1_FB2 CAN_F19R1_FB2_Msk /*!< Filter bit 2 */ |
| 8232 | #define CAN_F19R1_FB2 CAN_F19R1_FB2_Msk /*!< Filter bit 2 */ |
8232 | #define CAN_F19R1_FB3_Pos (3U) |
| 8233 | #define CAN_F19R1_FB3_Pos (3U) |
8233 | #define CAN_F19R1_FB3_Msk (0x1UL << CAN_F19R1_FB3_Pos) /*!< 0x00000008 */ |
| 8234 | #define CAN_F19R1_FB3_Msk (0x1UL << CAN_F19R1_FB3_Pos) /*!< 0x00000008 */ |
8234 | #define CAN_F19R1_FB3 CAN_F19R1_FB3_Msk /*!< Filter bit 3 */ |
| 8235 | #define CAN_F19R1_FB3 CAN_F19R1_FB3_Msk /*!< Filter bit 3 */ |
8235 | #define CAN_F19R1_FB4_Pos (4U) |
| 8236 | #define CAN_F19R1_FB4_Pos (4U) |
8236 | #define CAN_F19R1_FB4_Msk (0x1UL << CAN_F19R1_FB4_Pos) /*!< 0x00000010 */ |
| 8237 | #define CAN_F19R1_FB4_Msk (0x1UL << CAN_F19R1_FB4_Pos) /*!< 0x00000010 */ |
8237 | #define CAN_F19R1_FB4 CAN_F19R1_FB4_Msk /*!< Filter bit 4 */ |
| 8238 | #define CAN_F19R1_FB4 CAN_F19R1_FB4_Msk /*!< Filter bit 4 */ |
8238 | #define CAN_F19R1_FB5_Pos (5U) |
| 8239 | #define CAN_F19R1_FB5_Pos (5U) |
8239 | #define CAN_F19R1_FB5_Msk (0x1UL << CAN_F19R1_FB5_Pos) /*!< 0x00000020 */ |
| 8240 | #define CAN_F19R1_FB5_Msk (0x1UL << CAN_F19R1_FB5_Pos) /*!< 0x00000020 */ |
8240 | #define CAN_F19R1_FB5 CAN_F19R1_FB5_Msk /*!< Filter bit 5 */ |
| 8241 | #define CAN_F19R1_FB5 CAN_F19R1_FB5_Msk /*!< Filter bit 5 */ |
8241 | #define CAN_F19R1_FB6_Pos (6U) |
| 8242 | #define CAN_F19R1_FB6_Pos (6U) |
8242 | #define CAN_F19R1_FB6_Msk (0x1UL << CAN_F19R1_FB6_Pos) /*!< 0x00000040 */ |
| 8243 | #define CAN_F19R1_FB6_Msk (0x1UL << CAN_F19R1_FB6_Pos) /*!< 0x00000040 */ |
8243 | #define CAN_F19R1_FB6 CAN_F19R1_FB6_Msk /*!< Filter bit 6 */ |
| 8244 | #define CAN_F19R1_FB6 CAN_F19R1_FB6_Msk /*!< Filter bit 6 */ |
8244 | #define CAN_F19R1_FB7_Pos (7U) |
| 8245 | #define CAN_F19R1_FB7_Pos (7U) |
8245 | #define CAN_F19R1_FB7_Msk (0x1UL << CAN_F19R1_FB7_Pos) /*!< 0x00000080 */ |
| 8246 | #define CAN_F19R1_FB7_Msk (0x1UL << CAN_F19R1_FB7_Pos) /*!< 0x00000080 */ |
8246 | #define CAN_F19R1_FB7 CAN_F19R1_FB7_Msk /*!< Filter bit 7 */ |
| 8247 | #define CAN_F19R1_FB7 CAN_F19R1_FB7_Msk /*!< Filter bit 7 */ |
8247 | #define CAN_F19R1_FB8_Pos (8U) |
| 8248 | #define CAN_F19R1_FB8_Pos (8U) |
8248 | #define CAN_F19R1_FB8_Msk (0x1UL << CAN_F19R1_FB8_Pos) /*!< 0x00000100 */ |
| 8249 | #define CAN_F19R1_FB8_Msk (0x1UL << CAN_F19R1_FB8_Pos) /*!< 0x00000100 */ |
8249 | #define CAN_F19R1_FB8 CAN_F19R1_FB8_Msk /*!< Filter bit 8 */ |
| 8250 | #define CAN_F19R1_FB8 CAN_F19R1_FB8_Msk /*!< Filter bit 8 */ |
8250 | #define CAN_F19R1_FB9_Pos (9U) |
| 8251 | #define CAN_F19R1_FB9_Pos (9U) |
8251 | #define CAN_F19R1_FB9_Msk (0x1UL << CAN_F19R1_FB9_Pos) /*!< 0x00000200 */ |
| 8252 | #define CAN_F19R1_FB9_Msk (0x1UL << CAN_F19R1_FB9_Pos) /*!< 0x00000200 */ |
8252 | #define CAN_F19R1_FB9 CAN_F19R1_FB9_Msk /*!< Filter bit 9 */ |
| 8253 | #define CAN_F19R1_FB9 CAN_F19R1_FB9_Msk /*!< Filter bit 9 */ |
8253 | #define CAN_F19R1_FB10_Pos (10U) |
| 8254 | #define CAN_F19R1_FB10_Pos (10U) |
8254 | #define CAN_F19R1_FB10_Msk (0x1UL << CAN_F19R1_FB10_Pos) /*!< 0x00000400 */ |
| 8255 | #define CAN_F19R1_FB10_Msk (0x1UL << CAN_F19R1_FB10_Pos) /*!< 0x00000400 */ |
8255 | #define CAN_F19R1_FB10 CAN_F19R1_FB10_Msk /*!< Filter bit 10 */ |
| 8256 | #define CAN_F19R1_FB10 CAN_F19R1_FB10_Msk /*!< Filter bit 10 */ |
8256 | #define CAN_F19R1_FB11_Pos (11U) |
| 8257 | #define CAN_F19R1_FB11_Pos (11U) |
8257 | #define CAN_F19R1_FB11_Msk (0x1UL << CAN_F19R1_FB11_Pos) /*!< 0x00000800 */ |
| 8258 | #define CAN_F19R1_FB11_Msk (0x1UL << CAN_F19R1_FB11_Pos) /*!< 0x00000800 */ |
8258 | #define CAN_F19R1_FB11 CAN_F19R1_FB11_Msk /*!< Filter bit 11 */ |
| 8259 | #define CAN_F19R1_FB11 CAN_F19R1_FB11_Msk /*!< Filter bit 11 */ |
8259 | #define CAN_F19R1_FB12_Pos (12U) |
| 8260 | #define CAN_F19R1_FB12_Pos (12U) |
8260 | #define CAN_F19R1_FB12_Msk (0x1UL << CAN_F19R1_FB12_Pos) /*!< 0x00001000 */ |
| 8261 | #define CAN_F19R1_FB12_Msk (0x1UL << CAN_F19R1_FB12_Pos) /*!< 0x00001000 */ |
8261 | #define CAN_F19R1_FB12 CAN_F19R1_FB12_Msk /*!< Filter bit 12 */ |
| 8262 | #define CAN_F19R1_FB12 CAN_F19R1_FB12_Msk /*!< Filter bit 12 */ |
8262 | #define CAN_F19R1_FB13_Pos (13U) |
| 8263 | #define CAN_F19R1_FB13_Pos (13U) |
8263 | #define CAN_F19R1_FB13_Msk (0x1UL << CAN_F19R1_FB13_Pos) /*!< 0x00002000 */ |
| 8264 | #define CAN_F19R1_FB13_Msk (0x1UL << CAN_F19R1_FB13_Pos) /*!< 0x00002000 */ |
8264 | #define CAN_F19R1_FB13 CAN_F19R1_FB13_Msk /*!< Filter bit 13 */ |
| 8265 | #define CAN_F19R1_FB13 CAN_F19R1_FB13_Msk /*!< Filter bit 13 */ |
8265 | #define CAN_F19R1_FB14_Pos (14U) |
| 8266 | #define CAN_F19R1_FB14_Pos (14U) |
8266 | #define CAN_F19R1_FB14_Msk (0x1UL << CAN_F19R1_FB14_Pos) /*!< 0x00004000 */ |
| 8267 | #define CAN_F19R1_FB14_Msk (0x1UL << CAN_F19R1_FB14_Pos) /*!< 0x00004000 */ |
8267 | #define CAN_F19R1_FB14 CAN_F19R1_FB14_Msk /*!< Filter bit 14 */ |
| 8268 | #define CAN_F19R1_FB14 CAN_F19R1_FB14_Msk /*!< Filter bit 14 */ |
8268 | #define CAN_F19R1_FB15_Pos (15U) |
| 8269 | #define CAN_F19R1_FB15_Pos (15U) |
8269 | #define CAN_F19R1_FB15_Msk (0x1UL << CAN_F19R1_FB15_Pos) /*!< 0x00008000 */ |
| 8270 | #define CAN_F19R1_FB15_Msk (0x1UL << CAN_F19R1_FB15_Pos) /*!< 0x00008000 */ |
8270 | #define CAN_F19R1_FB15 CAN_F19R1_FB15_Msk /*!< Filter bit 15 */ |
| 8271 | #define CAN_F19R1_FB15 CAN_F19R1_FB15_Msk /*!< Filter bit 15 */ |
8271 | #define CAN_F19R1_FB16_Pos (16U) |
| 8272 | #define CAN_F19R1_FB16_Pos (16U) |
8272 | #define CAN_F19R1_FB16_Msk (0x1UL << CAN_F19R1_FB16_Pos) /*!< 0x00010000 */ |
| 8273 | #define CAN_F19R1_FB16_Msk (0x1UL << CAN_F19R1_FB16_Pos) /*!< 0x00010000 */ |
8273 | #define CAN_F19R1_FB16 CAN_F19R1_FB16_Msk /*!< Filter bit 16 */ |
| 8274 | #define CAN_F19R1_FB16 CAN_F19R1_FB16_Msk /*!< Filter bit 16 */ |
8274 | #define CAN_F19R1_FB17_Pos (17U) |
| 8275 | #define CAN_F19R1_FB17_Pos (17U) |
8275 | #define CAN_F19R1_FB17_Msk (0x1UL << CAN_F19R1_FB17_Pos) /*!< 0x00020000 */ |
| 8276 | #define CAN_F19R1_FB17_Msk (0x1UL << CAN_F19R1_FB17_Pos) /*!< 0x00020000 */ |
8276 | #define CAN_F19R1_FB17 CAN_F19R1_FB17_Msk /*!< Filter bit 17 */ |
| 8277 | #define CAN_F19R1_FB17 CAN_F19R1_FB17_Msk /*!< Filter bit 17 */ |
8277 | #define CAN_F19R1_FB18_Pos (18U) |
| 8278 | #define CAN_F19R1_FB18_Pos (18U) |
8278 | #define CAN_F19R1_FB18_Msk (0x1UL << CAN_F19R1_FB18_Pos) /*!< 0x00040000 */ |
| 8279 | #define CAN_F19R1_FB18_Msk (0x1UL << CAN_F19R1_FB18_Pos) /*!< 0x00040000 */ |
8279 | #define CAN_F19R1_FB18 CAN_F19R1_FB18_Msk /*!< Filter bit 18 */ |
| 8280 | #define CAN_F19R1_FB18 CAN_F19R1_FB18_Msk /*!< Filter bit 18 */ |
8280 | #define CAN_F19R1_FB19_Pos (19U) |
| 8281 | #define CAN_F19R1_FB19_Pos (19U) |
8281 | #define CAN_F19R1_FB19_Msk (0x1UL << CAN_F19R1_FB19_Pos) /*!< 0x00080000 */ |
| 8282 | #define CAN_F19R1_FB19_Msk (0x1UL << CAN_F19R1_FB19_Pos) /*!< 0x00080000 */ |
8282 | #define CAN_F19R1_FB19 CAN_F19R1_FB19_Msk /*!< Filter bit 19 */ |
| 8283 | #define CAN_F19R1_FB19 CAN_F19R1_FB19_Msk /*!< Filter bit 19 */ |
8283 | #define CAN_F19R1_FB20_Pos (20U) |
| 8284 | #define CAN_F19R1_FB20_Pos (20U) |
8284 | #define CAN_F19R1_FB20_Msk (0x1UL << CAN_F19R1_FB20_Pos) /*!< 0x00100000 */ |
| 8285 | #define CAN_F19R1_FB20_Msk (0x1UL << CAN_F19R1_FB20_Pos) /*!< 0x00100000 */ |
8285 | #define CAN_F19R1_FB20 CAN_F19R1_FB20_Msk /*!< Filter bit 20 */ |
| 8286 | #define CAN_F19R1_FB20 CAN_F19R1_FB20_Msk /*!< Filter bit 20 */ |
8286 | #define CAN_F19R1_FB21_Pos (21U) |
| 8287 | #define CAN_F19R1_FB21_Pos (21U) |
8287 | #define CAN_F19R1_FB21_Msk (0x1UL << CAN_F19R1_FB21_Pos) /*!< 0x00200000 */ |
| 8288 | #define CAN_F19R1_FB21_Msk (0x1UL << CAN_F19R1_FB21_Pos) /*!< 0x00200000 */ |
8288 | #define CAN_F19R1_FB21 CAN_F19R1_FB21_Msk /*!< Filter bit 21 */ |
| 8289 | #define CAN_F19R1_FB21 CAN_F19R1_FB21_Msk /*!< Filter bit 21 */ |
8289 | #define CAN_F19R1_FB22_Pos (22U) |
| 8290 | #define CAN_F19R1_FB22_Pos (22U) |
8290 | #define CAN_F19R1_FB22_Msk (0x1UL << CAN_F19R1_FB22_Pos) /*!< 0x00400000 */ |
| 8291 | #define CAN_F19R1_FB22_Msk (0x1UL << CAN_F19R1_FB22_Pos) /*!< 0x00400000 */ |
8291 | #define CAN_F19R1_FB22 CAN_F19R1_FB22_Msk /*!< Filter bit 22 */ |
| 8292 | #define CAN_F19R1_FB22 CAN_F19R1_FB22_Msk /*!< Filter bit 22 */ |
8292 | #define CAN_F19R1_FB23_Pos (23U) |
| 8293 | #define CAN_F19R1_FB23_Pos (23U) |
8293 | #define CAN_F19R1_FB23_Msk (0x1UL << CAN_F19R1_FB23_Pos) /*!< 0x00800000 */ |
| 8294 | #define CAN_F19R1_FB23_Msk (0x1UL << CAN_F19R1_FB23_Pos) /*!< 0x00800000 */ |
8294 | #define CAN_F19R1_FB23 CAN_F19R1_FB23_Msk /*!< Filter bit 23 */ |
| 8295 | #define CAN_F19R1_FB23 CAN_F19R1_FB23_Msk /*!< Filter bit 23 */ |
8295 | #define CAN_F19R1_FB24_Pos (24U) |
| 8296 | #define CAN_F19R1_FB24_Pos (24U) |
8296 | #define CAN_F19R1_FB24_Msk (0x1UL << CAN_F19R1_FB24_Pos) /*!< 0x01000000 */ |
| 8297 | #define CAN_F19R1_FB24_Msk (0x1UL << CAN_F19R1_FB24_Pos) /*!< 0x01000000 */ |
8297 | #define CAN_F19R1_FB24 CAN_F19R1_FB24_Msk /*!< Filter bit 24 */ |
| 8298 | #define CAN_F19R1_FB24 CAN_F19R1_FB24_Msk /*!< Filter bit 24 */ |
8298 | #define CAN_F19R1_FB25_Pos (25U) |
| 8299 | #define CAN_F19R1_FB25_Pos (25U) |
8299 | #define CAN_F19R1_FB25_Msk (0x1UL << CAN_F19R1_FB25_Pos) /*!< 0x02000000 */ |
| 8300 | #define CAN_F19R1_FB25_Msk (0x1UL << CAN_F19R1_FB25_Pos) /*!< 0x02000000 */ |
8300 | #define CAN_F19R1_FB25 CAN_F19R1_FB25_Msk /*!< Filter bit 25 */ |
| 8301 | #define CAN_F19R1_FB25 CAN_F19R1_FB25_Msk /*!< Filter bit 25 */ |
8301 | #define CAN_F19R1_FB26_Pos (26U) |
| 8302 | #define CAN_F19R1_FB26_Pos (26U) |
8302 | #define CAN_F19R1_FB26_Msk (0x1UL << CAN_F19R1_FB26_Pos) /*!< 0x04000000 */ |
| 8303 | #define CAN_F19R1_FB26_Msk (0x1UL << CAN_F19R1_FB26_Pos) /*!< 0x04000000 */ |
8303 | #define CAN_F19R1_FB26 CAN_F19R1_FB26_Msk /*!< Filter bit 26 */ |
| 8304 | #define CAN_F19R1_FB26 CAN_F19R1_FB26_Msk /*!< Filter bit 26 */ |
8304 | #define CAN_F19R1_FB27_Pos (27U) |
| 8305 | #define CAN_F19R1_FB27_Pos (27U) |
8305 | #define CAN_F19R1_FB27_Msk (0x1UL << CAN_F19R1_FB27_Pos) /*!< 0x08000000 */ |
| 8306 | #define CAN_F19R1_FB27_Msk (0x1UL << CAN_F19R1_FB27_Pos) /*!< 0x08000000 */ |
8306 | #define CAN_F19R1_FB27 CAN_F19R1_FB27_Msk /*!< Filter bit 27 */ |
| 8307 | #define CAN_F19R1_FB27 CAN_F19R1_FB27_Msk /*!< Filter bit 27 */ |
8307 | #define CAN_F19R1_FB28_Pos (28U) |
| 8308 | #define CAN_F19R1_FB28_Pos (28U) |
8308 | #define CAN_F19R1_FB28_Msk (0x1UL << CAN_F19R1_FB28_Pos) /*!< 0x10000000 */ |
| 8309 | #define CAN_F19R1_FB28_Msk (0x1UL << CAN_F19R1_FB28_Pos) /*!< 0x10000000 */ |
8309 | #define CAN_F19R1_FB28 CAN_F19R1_FB28_Msk /*!< Filter bit 28 */ |
| 8310 | #define CAN_F19R1_FB28 CAN_F19R1_FB28_Msk /*!< Filter bit 28 */ |
8310 | #define CAN_F19R1_FB29_Pos (29U) |
| 8311 | #define CAN_F19R1_FB29_Pos (29U) |
8311 | #define CAN_F19R1_FB29_Msk (0x1UL << CAN_F19R1_FB29_Pos) /*!< 0x20000000 */ |
| 8312 | #define CAN_F19R1_FB29_Msk (0x1UL << CAN_F19R1_FB29_Pos) /*!< 0x20000000 */ |
8312 | #define CAN_F19R1_FB29 CAN_F19R1_FB29_Msk /*!< Filter bit 29 */ |
| 8313 | #define CAN_F19R1_FB29 CAN_F19R1_FB29_Msk /*!< Filter bit 29 */ |
8313 | #define CAN_F19R1_FB30_Pos (30U) |
| 8314 | #define CAN_F19R1_FB30_Pos (30U) |
8314 | #define CAN_F19R1_FB30_Msk (0x1UL << CAN_F19R1_FB30_Pos) /*!< 0x40000000 */ |
| 8315 | #define CAN_F19R1_FB30_Msk (0x1UL << CAN_F19R1_FB30_Pos) /*!< 0x40000000 */ |
8315 | #define CAN_F19R1_FB30 CAN_F19R1_FB30_Msk /*!< Filter bit 30 */ |
| 8316 | #define CAN_F19R1_FB30 CAN_F19R1_FB30_Msk /*!< Filter bit 30 */ |
8316 | #define CAN_F19R1_FB31_Pos (31U) |
| 8317 | #define CAN_F19R1_FB31_Pos (31U) |
8317 | #define CAN_F19R1_FB31_Msk (0x1UL << CAN_F19R1_FB31_Pos) /*!< 0x80000000 */ |
| 8318 | #define CAN_F19R1_FB31_Msk (0x1UL << CAN_F19R1_FB31_Pos) /*!< 0x80000000 */ |
8318 | #define CAN_F19R1_FB31 CAN_F19R1_FB31_Msk /*!< Filter bit 31 */ |
| 8319 | #define CAN_F19R1_FB31 CAN_F19R1_FB31_Msk /*!< Filter bit 31 */ |
8319 | |
| 8320 | 8320 | /******************* Bit definition for CAN_F20R1 register ******************/ |
|
| 8321 | /******************* Bit definition for CAN_F20R1 register ******************/ |
8321 | #define CAN_F20R1_FB0_Pos (0U) |
| 8322 | #define CAN_F20R1_FB0_Pos (0U) |
8322 | #define CAN_F20R1_FB0_Msk (0x1UL << CAN_F20R1_FB0_Pos) /*!< 0x00000001 */ |
| 8323 | #define CAN_F20R1_FB0_Msk (0x1UL << CAN_F20R1_FB0_Pos) /*!< 0x00000001 */ |
8323 | #define CAN_F20R1_FB0 CAN_F20R1_FB0_Msk /*!< Filter bit 0 */ |
| 8324 | #define CAN_F20R1_FB0 CAN_F20R1_FB0_Msk /*!< Filter bit 0 */ |
8324 | #define CAN_F20R1_FB1_Pos (1U) |
| 8325 | #define CAN_F20R1_FB1_Pos (1U) |
8325 | #define CAN_F20R1_FB1_Msk (0x1UL << CAN_F20R1_FB1_Pos) /*!< 0x00000002 */ |
| 8326 | #define CAN_F20R1_FB1_Msk (0x1UL << CAN_F20R1_FB1_Pos) /*!< 0x00000002 */ |
8326 | #define CAN_F20R1_FB1 CAN_F20R1_FB1_Msk /*!< Filter bit 1 */ |
| 8327 | #define CAN_F20R1_FB1 CAN_F20R1_FB1_Msk /*!< Filter bit 1 */ |
8327 | #define CAN_F20R1_FB2_Pos (2U) |
| 8328 | #define CAN_F20R1_FB2_Pos (2U) |
8328 | #define CAN_F20R1_FB2_Msk (0x1UL << CAN_F20R1_FB2_Pos) /*!< 0x00000004 */ |
| 8329 | #define CAN_F20R1_FB2_Msk (0x1UL << CAN_F20R1_FB2_Pos) /*!< 0x00000004 */ |
8329 | #define CAN_F20R1_FB2 CAN_F20R1_FB2_Msk /*!< Filter bit 2 */ |
| 8330 | #define CAN_F20R1_FB2 CAN_F20R1_FB2_Msk /*!< Filter bit 2 */ |
8330 | #define CAN_F20R1_FB3_Pos (3U) |
| 8331 | #define CAN_F20R1_FB3_Pos (3U) |
8331 | #define CAN_F20R1_FB3_Msk (0x1UL << CAN_F20R1_FB3_Pos) /*!< 0x00000008 */ |
| 8332 | #define CAN_F20R1_FB3_Msk (0x1UL << CAN_F20R1_FB3_Pos) /*!< 0x00000008 */ |
8332 | #define CAN_F20R1_FB3 CAN_F20R1_FB3_Msk /*!< Filter bit 3 */ |
| 8333 | #define CAN_F20R1_FB3 CAN_F20R1_FB3_Msk /*!< Filter bit 3 */ |
8333 | #define CAN_F20R1_FB4_Pos (4U) |
| 8334 | #define CAN_F20R1_FB4_Pos (4U) |
8334 | #define CAN_F20R1_FB4_Msk (0x1UL << CAN_F20R1_FB4_Pos) /*!< 0x00000010 */ |
| 8335 | #define CAN_F20R1_FB4_Msk (0x1UL << CAN_F20R1_FB4_Pos) /*!< 0x00000010 */ |
8335 | #define CAN_F20R1_FB4 CAN_F20R1_FB4_Msk /*!< Filter bit 4 */ |
| 8336 | #define CAN_F20R1_FB4 CAN_F20R1_FB4_Msk /*!< Filter bit 4 */ |
8336 | #define CAN_F20R1_FB5_Pos (5U) |
| 8337 | #define CAN_F20R1_FB5_Pos (5U) |
8337 | #define CAN_F20R1_FB5_Msk (0x1UL << CAN_F20R1_FB5_Pos) /*!< 0x00000020 */ |
| 8338 | #define CAN_F20R1_FB5_Msk (0x1UL << CAN_F20R1_FB5_Pos) /*!< 0x00000020 */ |
8338 | #define CAN_F20R1_FB5 CAN_F20R1_FB5_Msk /*!< Filter bit 5 */ |
| 8339 | #define CAN_F20R1_FB5 CAN_F20R1_FB5_Msk /*!< Filter bit 5 */ |
8339 | #define CAN_F20R1_FB6_Pos (6U) |
| 8340 | #define CAN_F20R1_FB6_Pos (6U) |
8340 | #define CAN_F20R1_FB6_Msk (0x1UL << CAN_F20R1_FB6_Pos) /*!< 0x00000040 */ |
| 8341 | #define CAN_F20R1_FB6_Msk (0x1UL << CAN_F20R1_FB6_Pos) /*!< 0x00000040 */ |
8341 | #define CAN_F20R1_FB6 CAN_F20R1_FB6_Msk /*!< Filter bit 6 */ |
| 8342 | #define CAN_F20R1_FB6 CAN_F20R1_FB6_Msk /*!< Filter bit 6 */ |
8342 | #define CAN_F20R1_FB7_Pos (7U) |
| 8343 | #define CAN_F20R1_FB7_Pos (7U) |
8343 | #define CAN_F20R1_FB7_Msk (0x1UL << CAN_F20R1_FB7_Pos) /*!< 0x00000080 */ |
| 8344 | #define CAN_F20R1_FB7_Msk (0x1UL << CAN_F20R1_FB7_Pos) /*!< 0x00000080 */ |
8344 | #define CAN_F20R1_FB7 CAN_F20R1_FB7_Msk /*!< Filter bit 7 */ |
| 8345 | #define CAN_F20R1_FB7 CAN_F20R1_FB7_Msk /*!< Filter bit 7 */ |
8345 | #define CAN_F20R1_FB8_Pos (8U) |
| 8346 | #define CAN_F20R1_FB8_Pos (8U) |
8346 | #define CAN_F20R1_FB8_Msk (0x1UL << CAN_F20R1_FB8_Pos) /*!< 0x00000100 */ |
| 8347 | #define CAN_F20R1_FB8_Msk (0x1UL << CAN_F20R1_FB8_Pos) /*!< 0x00000100 */ |
8347 | #define CAN_F20R1_FB8 CAN_F20R1_FB8_Msk /*!< Filter bit 8 */ |
| 8348 | #define CAN_F20R1_FB8 CAN_F20R1_FB8_Msk /*!< Filter bit 8 */ |
8348 | #define CAN_F20R1_FB9_Pos (9U) |
| 8349 | #define CAN_F20R1_FB9_Pos (9U) |
8349 | #define CAN_F20R1_FB9_Msk (0x1UL << CAN_F20R1_FB9_Pos) /*!< 0x00000200 */ |
| 8350 | #define CAN_F20R1_FB9_Msk (0x1UL << CAN_F20R1_FB9_Pos) /*!< 0x00000200 */ |
8350 | #define CAN_F20R1_FB9 CAN_F20R1_FB9_Msk /*!< Filter bit 9 */ |
| 8351 | #define CAN_F20R1_FB9 CAN_F20R1_FB9_Msk /*!< Filter bit 9 */ |
8351 | #define CAN_F20R1_FB10_Pos (10U) |
| 8352 | #define CAN_F20R1_FB10_Pos (10U) |
8352 | #define CAN_F20R1_FB10_Msk (0x1UL << CAN_F20R1_FB10_Pos) /*!< 0x00000400 */ |
| 8353 | #define CAN_F20R1_FB10_Msk (0x1UL << CAN_F20R1_FB10_Pos) /*!< 0x00000400 */ |
8353 | #define CAN_F20R1_FB10 CAN_F20R1_FB10_Msk /*!< Filter bit 10 */ |
| 8354 | #define CAN_F20R1_FB10 CAN_F20R1_FB10_Msk /*!< Filter bit 10 */ |
8354 | #define CAN_F20R1_FB11_Pos (11U) |
| 8355 | #define CAN_F20R1_FB11_Pos (11U) |
8355 | #define CAN_F20R1_FB11_Msk (0x1UL << CAN_F20R1_FB11_Pos) /*!< 0x00000800 */ |
| 8356 | #define CAN_F20R1_FB11_Msk (0x1UL << CAN_F20R1_FB11_Pos) /*!< 0x00000800 */ |
8356 | #define CAN_F20R1_FB11 CAN_F20R1_FB11_Msk /*!< Filter bit 11 */ |
| 8357 | #define CAN_F20R1_FB11 CAN_F20R1_FB11_Msk /*!< Filter bit 11 */ |
8357 | #define CAN_F20R1_FB12_Pos (12U) |
| 8358 | #define CAN_F20R1_FB12_Pos (12U) |
8358 | #define CAN_F20R1_FB12_Msk (0x1UL << CAN_F20R1_FB12_Pos) /*!< 0x00001000 */ |
| 8359 | #define CAN_F20R1_FB12_Msk (0x1UL << CAN_F20R1_FB12_Pos) /*!< 0x00001000 */ |
8359 | #define CAN_F20R1_FB12 CAN_F20R1_FB12_Msk /*!< Filter bit 12 */ |
| 8360 | #define CAN_F20R1_FB12 CAN_F20R1_FB12_Msk /*!< Filter bit 12 */ |
8360 | #define CAN_F20R1_FB13_Pos (13U) |
| 8361 | #define CAN_F20R1_FB13_Pos (13U) |
8361 | #define CAN_F20R1_FB13_Msk (0x1UL << CAN_F20R1_FB13_Pos) /*!< 0x00002000 */ |
| 8362 | #define CAN_F20R1_FB13_Msk (0x1UL << CAN_F20R1_FB13_Pos) /*!< 0x00002000 */ |
8362 | #define CAN_F20R1_FB13 CAN_F20R1_FB13_Msk /*!< Filter bit 13 */ |
| 8363 | #define CAN_F20R1_FB13 CAN_F20R1_FB13_Msk /*!< Filter bit 13 */ |
8363 | #define CAN_F20R1_FB14_Pos (14U) |
| 8364 | #define CAN_F20R1_FB14_Pos (14U) |
8364 | #define CAN_F20R1_FB14_Msk (0x1UL << CAN_F20R1_FB14_Pos) /*!< 0x00004000 */ |
| 8365 | #define CAN_F20R1_FB14_Msk (0x1UL << CAN_F20R1_FB14_Pos) /*!< 0x00004000 */ |
8365 | #define CAN_F20R1_FB14 CAN_F20R1_FB14_Msk /*!< Filter bit 14 */ |
| 8366 | #define CAN_F20R1_FB14 CAN_F20R1_FB14_Msk /*!< Filter bit 14 */ |
8366 | #define CAN_F20R1_FB15_Pos (15U) |
| 8367 | #define CAN_F20R1_FB15_Pos (15U) |
8367 | #define CAN_F20R1_FB15_Msk (0x1UL << CAN_F20R1_FB15_Pos) /*!< 0x00008000 */ |
| 8368 | #define CAN_F20R1_FB15_Msk (0x1UL << CAN_F20R1_FB15_Pos) /*!< 0x00008000 */ |
8368 | #define CAN_F20R1_FB15 CAN_F20R1_FB15_Msk /*!< Filter bit 15 */ |
| 8369 | #define CAN_F20R1_FB15 CAN_F20R1_FB15_Msk /*!< Filter bit 15 */ |
8369 | #define CAN_F20R1_FB16_Pos (16U) |
| 8370 | #define CAN_F20R1_FB16_Pos (16U) |
8370 | #define CAN_F20R1_FB16_Msk (0x1UL << CAN_F20R1_FB16_Pos) /*!< 0x00010000 */ |
| 8371 | #define CAN_F20R1_FB16_Msk (0x1UL << CAN_F20R1_FB16_Pos) /*!< 0x00010000 */ |
8371 | #define CAN_F20R1_FB16 CAN_F20R1_FB16_Msk /*!< Filter bit 16 */ |
| 8372 | #define CAN_F20R1_FB16 CAN_F20R1_FB16_Msk /*!< Filter bit 16 */ |
8372 | #define CAN_F20R1_FB17_Pos (17U) |
| 8373 | #define CAN_F20R1_FB17_Pos (17U) |
8373 | #define CAN_F20R1_FB17_Msk (0x1UL << CAN_F20R1_FB17_Pos) /*!< 0x00020000 */ |
| 8374 | #define CAN_F20R1_FB17_Msk (0x1UL << CAN_F20R1_FB17_Pos) /*!< 0x00020000 */ |
8374 | #define CAN_F20R1_FB17 CAN_F20R1_FB17_Msk /*!< Filter bit 17 */ |
| 8375 | #define CAN_F20R1_FB17 CAN_F20R1_FB17_Msk /*!< Filter bit 17 */ |
8375 | #define CAN_F20R1_FB18_Pos (18U) |
| 8376 | #define CAN_F20R1_FB18_Pos (18U) |
8376 | #define CAN_F20R1_FB18_Msk (0x1UL << CAN_F20R1_FB18_Pos) /*!< 0x00040000 */ |
| 8377 | #define CAN_F20R1_FB18_Msk (0x1UL << CAN_F20R1_FB18_Pos) /*!< 0x00040000 */ |
8377 | #define CAN_F20R1_FB18 CAN_F20R1_FB18_Msk /*!< Filter bit 18 */ |
| 8378 | #define CAN_F20R1_FB18 CAN_F20R1_FB18_Msk /*!< Filter bit 18 */ |
8378 | #define CAN_F20R1_FB19_Pos (19U) |
| 8379 | #define CAN_F20R1_FB19_Pos (19U) |
8379 | #define CAN_F20R1_FB19_Msk (0x1UL << CAN_F20R1_FB19_Pos) /*!< 0x00080000 */ |
| 8380 | #define CAN_F20R1_FB19_Msk (0x1UL << CAN_F20R1_FB19_Pos) /*!< 0x00080000 */ |
8380 | #define CAN_F20R1_FB19 CAN_F20R1_FB19_Msk /*!< Filter bit 19 */ |
| 8381 | #define CAN_F20R1_FB19 CAN_F20R1_FB19_Msk /*!< Filter bit 19 */ |
8381 | #define CAN_F20R1_FB20_Pos (20U) |
| 8382 | #define CAN_F20R1_FB20_Pos (20U) |
8382 | #define CAN_F20R1_FB20_Msk (0x1UL << CAN_F20R1_FB20_Pos) /*!< 0x00100000 */ |
| 8383 | #define CAN_F20R1_FB20_Msk (0x1UL << CAN_F20R1_FB20_Pos) /*!< 0x00100000 */ |
8383 | #define CAN_F20R1_FB20 CAN_F20R1_FB20_Msk /*!< Filter bit 20 */ |
| 8384 | #define CAN_F20R1_FB20 CAN_F20R1_FB20_Msk /*!< Filter bit 20 */ |
8384 | #define CAN_F20R1_FB21_Pos (21U) |
| 8385 | #define CAN_F20R1_FB21_Pos (21U) |
8385 | #define CAN_F20R1_FB21_Msk (0x1UL << CAN_F20R1_FB21_Pos) /*!< 0x00200000 */ |
| 8386 | #define CAN_F20R1_FB21_Msk (0x1UL << CAN_F20R1_FB21_Pos) /*!< 0x00200000 */ |
8386 | #define CAN_F20R1_FB21 CAN_F20R1_FB21_Msk /*!< Filter bit 21 */ |
| 8387 | #define CAN_F20R1_FB21 CAN_F20R1_FB21_Msk /*!< Filter bit 21 */ |
8387 | #define CAN_F20R1_FB22_Pos (22U) |
| 8388 | #define CAN_F20R1_FB22_Pos (22U) |
8388 | #define CAN_F20R1_FB22_Msk (0x1UL << CAN_F20R1_FB22_Pos) /*!< 0x00400000 */ |
| 8389 | #define CAN_F20R1_FB22_Msk (0x1UL << CAN_F20R1_FB22_Pos) /*!< 0x00400000 */ |
8389 | #define CAN_F20R1_FB22 CAN_F20R1_FB22_Msk /*!< Filter bit 22 */ |
| 8390 | #define CAN_F20R1_FB22 CAN_F20R1_FB22_Msk /*!< Filter bit 22 */ |
8390 | #define CAN_F20R1_FB23_Pos (23U) |
| 8391 | #define CAN_F20R1_FB23_Pos (23U) |
8391 | #define CAN_F20R1_FB23_Msk (0x1UL << CAN_F20R1_FB23_Pos) /*!< 0x00800000 */ |
| 8392 | #define CAN_F20R1_FB23_Msk (0x1UL << CAN_F20R1_FB23_Pos) /*!< 0x00800000 */ |
8392 | #define CAN_F20R1_FB23 CAN_F20R1_FB23_Msk /*!< Filter bit 23 */ |
| 8393 | #define CAN_F20R1_FB23 CAN_F20R1_FB23_Msk /*!< Filter bit 23 */ |
8393 | #define CAN_F20R1_FB24_Pos (24U) |
| 8394 | #define CAN_F20R1_FB24_Pos (24U) |
8394 | #define CAN_F20R1_FB24_Msk (0x1UL << CAN_F20R1_FB24_Pos) /*!< 0x01000000 */ |
| 8395 | #define CAN_F20R1_FB24_Msk (0x1UL << CAN_F20R1_FB24_Pos) /*!< 0x01000000 */ |
8395 | #define CAN_F20R1_FB24 CAN_F20R1_FB24_Msk /*!< Filter bit 24 */ |
| 8396 | #define CAN_F20R1_FB24 CAN_F20R1_FB24_Msk /*!< Filter bit 24 */ |
8396 | #define CAN_F20R1_FB25_Pos (25U) |
| 8397 | #define CAN_F20R1_FB25_Pos (25U) |
8397 | #define CAN_F20R1_FB25_Msk (0x1UL << CAN_F20R1_FB25_Pos) /*!< 0x02000000 */ |
| 8398 | #define CAN_F20R1_FB25_Msk (0x1UL << CAN_F20R1_FB25_Pos) /*!< 0x02000000 */ |
8398 | #define CAN_F20R1_FB25 CAN_F20R1_FB25_Msk /*!< Filter bit 25 */ |
| 8399 | #define CAN_F20R1_FB25 CAN_F20R1_FB25_Msk /*!< Filter bit 25 */ |
8399 | #define CAN_F20R1_FB26_Pos (26U) |
| 8400 | #define CAN_F20R1_FB26_Pos (26U) |
8400 | #define CAN_F20R1_FB26_Msk (0x1UL << CAN_F20R1_FB26_Pos) /*!< 0x04000000 */ |
| 8401 | #define CAN_F20R1_FB26_Msk (0x1UL << CAN_F20R1_FB26_Pos) /*!< 0x04000000 */ |
8401 | #define CAN_F20R1_FB26 CAN_F20R1_FB26_Msk /*!< Filter bit 26 */ |
| 8402 | #define CAN_F20R1_FB26 CAN_F20R1_FB26_Msk /*!< Filter bit 26 */ |
8402 | #define CAN_F20R1_FB27_Pos (27U) |
| 8403 | #define CAN_F20R1_FB27_Pos (27U) |
8403 | #define CAN_F20R1_FB27_Msk (0x1UL << CAN_F20R1_FB27_Pos) /*!< 0x08000000 */ |
| 8404 | #define CAN_F20R1_FB27_Msk (0x1UL << CAN_F20R1_FB27_Pos) /*!< 0x08000000 */ |
8404 | #define CAN_F20R1_FB27 CAN_F20R1_FB27_Msk /*!< Filter bit 27 */ |
| 8405 | #define CAN_F20R1_FB27 CAN_F20R1_FB27_Msk /*!< Filter bit 27 */ |
8405 | #define CAN_F20R1_FB28_Pos (28U) |
| 8406 | #define CAN_F20R1_FB28_Pos (28U) |
8406 | #define CAN_F20R1_FB28_Msk (0x1UL << CAN_F20R1_FB28_Pos) /*!< 0x10000000 */ |
| 8407 | #define CAN_F20R1_FB28_Msk (0x1UL << CAN_F20R1_FB28_Pos) /*!< 0x10000000 */ |
8407 | #define CAN_F20R1_FB28 CAN_F20R1_FB28_Msk /*!< Filter bit 28 */ |
| 8408 | #define CAN_F20R1_FB28 CAN_F20R1_FB28_Msk /*!< Filter bit 28 */ |
8408 | #define CAN_F20R1_FB29_Pos (29U) |
| 8409 | #define CAN_F20R1_FB29_Pos (29U) |
8409 | #define CAN_F20R1_FB29_Msk (0x1UL << CAN_F20R1_FB29_Pos) /*!< 0x20000000 */ |
| 8410 | #define CAN_F20R1_FB29_Msk (0x1UL << CAN_F20R1_FB29_Pos) /*!< 0x20000000 */ |
8410 | #define CAN_F20R1_FB29 CAN_F20R1_FB29_Msk /*!< Filter bit 29 */ |
| 8411 | #define CAN_F20R1_FB29 CAN_F20R1_FB29_Msk /*!< Filter bit 29 */ |
8411 | #define CAN_F20R1_FB30_Pos (30U) |
| 8412 | #define CAN_F20R1_FB30_Pos (30U) |
8412 | #define CAN_F20R1_FB30_Msk (0x1UL << CAN_F20R1_FB30_Pos) /*!< 0x40000000 */ |
| 8413 | #define CAN_F20R1_FB30_Msk (0x1UL << CAN_F20R1_FB30_Pos) /*!< 0x40000000 */ |
8413 | #define CAN_F20R1_FB30 CAN_F20R1_FB30_Msk /*!< Filter bit 30 */ |
| 8414 | #define CAN_F20R1_FB30 CAN_F20R1_FB30_Msk /*!< Filter bit 30 */ |
8414 | #define CAN_F20R1_FB31_Pos (31U) |
| 8415 | #define CAN_F20R1_FB31_Pos (31U) |
8415 | #define CAN_F20R1_FB31_Msk (0x1UL << CAN_F20R1_FB31_Pos) /*!< 0x80000000 */ |
| 8416 | #define CAN_F20R1_FB31_Msk (0x1UL << CAN_F20R1_FB31_Pos) /*!< 0x80000000 */ |
8416 | #define CAN_F20R1_FB31 CAN_F20R1_FB31_Msk /*!< Filter bit 31 */ |
| 8417 | #define CAN_F20R1_FB31 CAN_F20R1_FB31_Msk /*!< Filter bit 31 */ |
8417 | |
| 8418 | 8418 | /******************* Bit definition for CAN_F21R1 register ******************/ |
|
| 8419 | /******************* Bit definition for CAN_F21R1 register ******************/ |
8419 | #define CAN_F21R1_FB0_Pos (0U) |
| 8420 | #define CAN_F21R1_FB0_Pos (0U) |
8420 | #define CAN_F21R1_FB0_Msk (0x1UL << CAN_F21R1_FB0_Pos) /*!< 0x00000001 */ |
| 8421 | #define CAN_F21R1_FB0_Msk (0x1UL << CAN_F21R1_FB0_Pos) /*!< 0x00000001 */ |
8421 | #define CAN_F21R1_FB0 CAN_F21R1_FB0_Msk /*!< Filter bit 0 */ |
| 8422 | #define CAN_F21R1_FB0 CAN_F21R1_FB0_Msk /*!< Filter bit 0 */ |
8422 | #define CAN_F21R1_FB1_Pos (1U) |
| 8423 | #define CAN_F21R1_FB1_Pos (1U) |
8423 | #define CAN_F21R1_FB1_Msk (0x1UL << CAN_F21R1_FB1_Pos) /*!< 0x00000002 */ |
| 8424 | #define CAN_F21R1_FB1_Msk (0x1UL << CAN_F21R1_FB1_Pos) /*!< 0x00000002 */ |
8424 | #define CAN_F21R1_FB1 CAN_F21R1_FB1_Msk /*!< Filter bit 1 */ |
| 8425 | #define CAN_F21R1_FB1 CAN_F21R1_FB1_Msk /*!< Filter bit 1 */ |
8425 | #define CAN_F21R1_FB2_Pos (2U) |
| 8426 | #define CAN_F21R1_FB2_Pos (2U) |
8426 | #define CAN_F21R1_FB2_Msk (0x1UL << CAN_F21R1_FB2_Pos) /*!< 0x00000004 */ |
| 8427 | #define CAN_F21R1_FB2_Msk (0x1UL << CAN_F21R1_FB2_Pos) /*!< 0x00000004 */ |
8427 | #define CAN_F21R1_FB2 CAN_F21R1_FB2_Msk /*!< Filter bit 2 */ |
| 8428 | #define CAN_F21R1_FB2 CAN_F21R1_FB2_Msk /*!< Filter bit 2 */ |
8428 | #define CAN_F21R1_FB3_Pos (3U) |
| 8429 | #define CAN_F21R1_FB3_Pos (3U) |
8429 | #define CAN_F21R1_FB3_Msk (0x1UL << CAN_F21R1_FB3_Pos) /*!< 0x00000008 */ |
| 8430 | #define CAN_F21R1_FB3_Msk (0x1UL << CAN_F21R1_FB3_Pos) /*!< 0x00000008 */ |
8430 | #define CAN_F21R1_FB3 CAN_F21R1_FB3_Msk /*!< Filter bit 3 */ |
| 8431 | #define CAN_F21R1_FB3 CAN_F21R1_FB3_Msk /*!< Filter bit 3 */ |
8431 | #define CAN_F21R1_FB4_Pos (4U) |
| 8432 | #define CAN_F21R1_FB4_Pos (4U) |
8432 | #define CAN_F21R1_FB4_Msk (0x1UL << CAN_F21R1_FB4_Pos) /*!< 0x00000010 */ |
| 8433 | #define CAN_F21R1_FB4_Msk (0x1UL << CAN_F21R1_FB4_Pos) /*!< 0x00000010 */ |
8433 | #define CAN_F21R1_FB4 CAN_F21R1_FB4_Msk /*!< Filter bit 4 */ |
| 8434 | #define CAN_F21R1_FB4 CAN_F21R1_FB4_Msk /*!< Filter bit 4 */ |
8434 | #define CAN_F21R1_FB5_Pos (5U) |
| 8435 | #define CAN_F21R1_FB5_Pos (5U) |
8435 | #define CAN_F21R1_FB5_Msk (0x1UL << CAN_F21R1_FB5_Pos) /*!< 0x00000020 */ |
| 8436 | #define CAN_F21R1_FB5_Msk (0x1UL << CAN_F21R1_FB5_Pos) /*!< 0x00000020 */ |
8436 | #define CAN_F21R1_FB5 CAN_F21R1_FB5_Msk /*!< Filter bit 5 */ |
| 8437 | #define CAN_F21R1_FB5 CAN_F21R1_FB5_Msk /*!< Filter bit 5 */ |
8437 | #define CAN_F21R1_FB6_Pos (6U) |
| 8438 | #define CAN_F21R1_FB6_Pos (6U) |
8438 | #define CAN_F21R1_FB6_Msk (0x1UL << CAN_F21R1_FB6_Pos) /*!< 0x00000040 */ |
| 8439 | #define CAN_F21R1_FB6_Msk (0x1UL << CAN_F21R1_FB6_Pos) /*!< 0x00000040 */ |
8439 | #define CAN_F21R1_FB6 CAN_F21R1_FB6_Msk /*!< Filter bit 6 */ |
| 8440 | #define CAN_F21R1_FB6 CAN_F21R1_FB6_Msk /*!< Filter bit 6 */ |
8440 | #define CAN_F21R1_FB7_Pos (7U) |
| 8441 | #define CAN_F21R1_FB7_Pos (7U) |
8441 | #define CAN_F21R1_FB7_Msk (0x1UL << CAN_F21R1_FB7_Pos) /*!< 0x00000080 */ |
| 8442 | #define CAN_F21R1_FB7_Msk (0x1UL << CAN_F21R1_FB7_Pos) /*!< 0x00000080 */ |
8442 | #define CAN_F21R1_FB7 CAN_F21R1_FB7_Msk /*!< Filter bit 7 */ |
| 8443 | #define CAN_F21R1_FB7 CAN_F21R1_FB7_Msk /*!< Filter bit 7 */ |
8443 | #define CAN_F21R1_FB8_Pos (8U) |
| 8444 | #define CAN_F21R1_FB8_Pos (8U) |
8444 | #define CAN_F21R1_FB8_Msk (0x1UL << CAN_F21R1_FB8_Pos) /*!< 0x00000100 */ |
| 8445 | #define CAN_F21R1_FB8_Msk (0x1UL << CAN_F21R1_FB8_Pos) /*!< 0x00000100 */ |
8445 | #define CAN_F21R1_FB8 CAN_F21R1_FB8_Msk /*!< Filter bit 8 */ |
| 8446 | #define CAN_F21R1_FB8 CAN_F21R1_FB8_Msk /*!< Filter bit 8 */ |
8446 | #define CAN_F21R1_FB9_Pos (9U) |
| 8447 | #define CAN_F21R1_FB9_Pos (9U) |
8447 | #define CAN_F21R1_FB9_Msk (0x1UL << CAN_F21R1_FB9_Pos) /*!< 0x00000200 */ |
| 8448 | #define CAN_F21R1_FB9_Msk (0x1UL << CAN_F21R1_FB9_Pos) /*!< 0x00000200 */ |
8448 | #define CAN_F21R1_FB9 CAN_F21R1_FB9_Msk /*!< Filter bit 9 */ |
| 8449 | #define CAN_F21R1_FB9 CAN_F21R1_FB9_Msk /*!< Filter bit 9 */ |
8449 | #define CAN_F21R1_FB10_Pos (10U) |
| 8450 | #define CAN_F21R1_FB10_Pos (10U) |
8450 | #define CAN_F21R1_FB10_Msk (0x1UL << CAN_F21R1_FB10_Pos) /*!< 0x00000400 */ |
| 8451 | #define CAN_F21R1_FB10_Msk (0x1UL << CAN_F21R1_FB10_Pos) /*!< 0x00000400 */ |
8451 | #define CAN_F21R1_FB10 CAN_F21R1_FB10_Msk /*!< Filter bit 10 */ |
| 8452 | #define CAN_F21R1_FB10 CAN_F21R1_FB10_Msk /*!< Filter bit 10 */ |
8452 | #define CAN_F21R1_FB11_Pos (11U) |
| 8453 | #define CAN_F21R1_FB11_Pos (11U) |
8453 | #define CAN_F21R1_FB11_Msk (0x1UL << CAN_F21R1_FB11_Pos) /*!< 0x00000800 */ |
| 8454 | #define CAN_F21R1_FB11_Msk (0x1UL << CAN_F21R1_FB11_Pos) /*!< 0x00000800 */ |
8454 | #define CAN_F21R1_FB11 CAN_F21R1_FB11_Msk /*!< Filter bit 11 */ |
| 8455 | #define CAN_F21R1_FB11 CAN_F21R1_FB11_Msk /*!< Filter bit 11 */ |
8455 | #define CAN_F21R1_FB12_Pos (12U) |
| 8456 | #define CAN_F21R1_FB12_Pos (12U) |
8456 | #define CAN_F21R1_FB12_Msk (0x1UL << CAN_F21R1_FB12_Pos) /*!< 0x00001000 */ |
| 8457 | #define CAN_F21R1_FB12_Msk (0x1UL << CAN_F21R1_FB12_Pos) /*!< 0x00001000 */ |
8457 | #define CAN_F21R1_FB12 CAN_F21R1_FB12_Msk /*!< Filter bit 12 */ |
| 8458 | #define CAN_F21R1_FB12 CAN_F21R1_FB12_Msk /*!< Filter bit 12 */ |
8458 | #define CAN_F21R1_FB13_Pos (13U) |
| 8459 | #define CAN_F21R1_FB13_Pos (13U) |
8459 | #define CAN_F21R1_FB13_Msk (0x1UL << CAN_F21R1_FB13_Pos) /*!< 0x00002000 */ |
| 8460 | #define CAN_F21R1_FB13_Msk (0x1UL << CAN_F21R1_FB13_Pos) /*!< 0x00002000 */ |
8460 | #define CAN_F21R1_FB13 CAN_F21R1_FB13_Msk /*!< Filter bit 13 */ |
| 8461 | #define CAN_F21R1_FB13 CAN_F21R1_FB13_Msk /*!< Filter bit 13 */ |
8461 | #define CAN_F21R1_FB14_Pos (14U) |
| 8462 | #define CAN_F21R1_FB14_Pos (14U) |
8462 | #define CAN_F21R1_FB14_Msk (0x1UL << CAN_F21R1_FB14_Pos) /*!< 0x00004000 */ |
| 8463 | #define CAN_F21R1_FB14_Msk (0x1UL << CAN_F21R1_FB14_Pos) /*!< 0x00004000 */ |
8463 | #define CAN_F21R1_FB14 CAN_F21R1_FB14_Msk /*!< Filter bit 14 */ |
| 8464 | #define CAN_F21R1_FB14 CAN_F21R1_FB14_Msk /*!< Filter bit 14 */ |
8464 | #define CAN_F21R1_FB15_Pos (15U) |
| 8465 | #define CAN_F21R1_FB15_Pos (15U) |
8465 | #define CAN_F21R1_FB15_Msk (0x1UL << CAN_F21R1_FB15_Pos) /*!< 0x00008000 */ |
| 8466 | #define CAN_F21R1_FB15_Msk (0x1UL << CAN_F21R1_FB15_Pos) /*!< 0x00008000 */ |
8466 | #define CAN_F21R1_FB15 CAN_F21R1_FB15_Msk /*!< Filter bit 15 */ |
| 8467 | #define CAN_F21R1_FB15 CAN_F21R1_FB15_Msk /*!< Filter bit 15 */ |
8467 | #define CAN_F21R1_FB16_Pos (16U) |
| 8468 | #define CAN_F21R1_FB16_Pos (16U) |
8468 | #define CAN_F21R1_FB16_Msk (0x1UL << CAN_F21R1_FB16_Pos) /*!< 0x00010000 */ |
| 8469 | #define CAN_F21R1_FB16_Msk (0x1UL << CAN_F21R1_FB16_Pos) /*!< 0x00010000 */ |
8469 | #define CAN_F21R1_FB16 CAN_F21R1_FB16_Msk /*!< Filter bit 16 */ |
| 8470 | #define CAN_F21R1_FB16 CAN_F21R1_FB16_Msk /*!< Filter bit 16 */ |
8470 | #define CAN_F21R1_FB17_Pos (17U) |
| 8471 | #define CAN_F21R1_FB17_Pos (17U) |
8471 | #define CAN_F21R1_FB17_Msk (0x1UL << CAN_F21R1_FB17_Pos) /*!< 0x00020000 */ |
| 8472 | #define CAN_F21R1_FB17_Msk (0x1UL << CAN_F21R1_FB17_Pos) /*!< 0x00020000 */ |
8472 | #define CAN_F21R1_FB17 CAN_F21R1_FB17_Msk /*!< Filter bit 17 */ |
| 8473 | #define CAN_F21R1_FB17 CAN_F21R1_FB17_Msk /*!< Filter bit 17 */ |
8473 | #define CAN_F21R1_FB18_Pos (18U) |
| 8474 | #define CAN_F21R1_FB18_Pos (18U) |
8474 | #define CAN_F21R1_FB18_Msk (0x1UL << CAN_F21R1_FB18_Pos) /*!< 0x00040000 */ |
| 8475 | #define CAN_F21R1_FB18_Msk (0x1UL << CAN_F21R1_FB18_Pos) /*!< 0x00040000 */ |
8475 | #define CAN_F21R1_FB18 CAN_F21R1_FB18_Msk /*!< Filter bit 18 */ |
| 8476 | #define CAN_F21R1_FB18 CAN_F21R1_FB18_Msk /*!< Filter bit 18 */ |
8476 | #define CAN_F21R1_FB19_Pos (19U) |
| 8477 | #define CAN_F21R1_FB19_Pos (19U) |
8477 | #define CAN_F21R1_FB19_Msk (0x1UL << CAN_F21R1_FB19_Pos) /*!< 0x00080000 */ |
| 8478 | #define CAN_F21R1_FB19_Msk (0x1UL << CAN_F21R1_FB19_Pos) /*!< 0x00080000 */ |
8478 | #define CAN_F21R1_FB19 CAN_F21R1_FB19_Msk /*!< Filter bit 19 */ |
| 8479 | #define CAN_F21R1_FB19 CAN_F21R1_FB19_Msk /*!< Filter bit 19 */ |
8479 | #define CAN_F21R1_FB20_Pos (20U) |
| 8480 | #define CAN_F21R1_FB20_Pos (20U) |
8480 | #define CAN_F21R1_FB20_Msk (0x1UL << CAN_F21R1_FB20_Pos) /*!< 0x00100000 */ |
| 8481 | #define CAN_F21R1_FB20_Msk (0x1UL << CAN_F21R1_FB20_Pos) /*!< 0x00100000 */ |
8481 | #define CAN_F21R1_FB20 CAN_F21R1_FB20_Msk /*!< Filter bit 20 */ |
| 8482 | #define CAN_F21R1_FB20 CAN_F21R1_FB20_Msk /*!< Filter bit 20 */ |
8482 | #define CAN_F21R1_FB21_Pos (21U) |
| 8483 | #define CAN_F21R1_FB21_Pos (21U) |
8483 | #define CAN_F21R1_FB21_Msk (0x1UL << CAN_F21R1_FB21_Pos) /*!< 0x00200000 */ |
| 8484 | #define CAN_F21R1_FB21_Msk (0x1UL << CAN_F21R1_FB21_Pos) /*!< 0x00200000 */ |
8484 | #define CAN_F21R1_FB21 CAN_F21R1_FB21_Msk /*!< Filter bit 21 */ |
| 8485 | #define CAN_F21R1_FB21 CAN_F21R1_FB21_Msk /*!< Filter bit 21 */ |
8485 | #define CAN_F21R1_FB22_Pos (22U) |
| 8486 | #define CAN_F21R1_FB22_Pos (22U) |
8486 | #define CAN_F21R1_FB22_Msk (0x1UL << CAN_F21R1_FB22_Pos) /*!< 0x00400000 */ |
| 8487 | #define CAN_F21R1_FB22_Msk (0x1UL << CAN_F21R1_FB22_Pos) /*!< 0x00400000 */ |
8487 | #define CAN_F21R1_FB22 CAN_F21R1_FB22_Msk /*!< Filter bit 22 */ |
| 8488 | #define CAN_F21R1_FB22 CAN_F21R1_FB22_Msk /*!< Filter bit 22 */ |
8488 | #define CAN_F21R1_FB23_Pos (23U) |
| 8489 | #define CAN_F21R1_FB23_Pos (23U) |
8489 | #define CAN_F21R1_FB23_Msk (0x1UL << CAN_F21R1_FB23_Pos) /*!< 0x00800000 */ |
| 8490 | #define CAN_F21R1_FB23_Msk (0x1UL << CAN_F21R1_FB23_Pos) /*!< 0x00800000 */ |
8490 | #define CAN_F21R1_FB23 CAN_F21R1_FB23_Msk /*!< Filter bit 23 */ |
| 8491 | #define CAN_F21R1_FB23 CAN_F21R1_FB23_Msk /*!< Filter bit 23 */ |
8491 | #define CAN_F21R1_FB24_Pos (24U) |
| 8492 | #define CAN_F21R1_FB24_Pos (24U) |
8492 | #define CAN_F21R1_FB24_Msk (0x1UL << CAN_F21R1_FB24_Pos) /*!< 0x01000000 */ |
| 8493 | #define CAN_F21R1_FB24_Msk (0x1UL << CAN_F21R1_FB24_Pos) /*!< 0x01000000 */ |
8493 | #define CAN_F21R1_FB24 CAN_F21R1_FB24_Msk /*!< Filter bit 24 */ |
| 8494 | #define CAN_F21R1_FB24 CAN_F21R1_FB24_Msk /*!< Filter bit 24 */ |
8494 | #define CAN_F21R1_FB25_Pos (25U) |
| 8495 | #define CAN_F21R1_FB25_Pos (25U) |
8495 | #define CAN_F21R1_FB25_Msk (0x1UL << CAN_F21R1_FB25_Pos) /*!< 0x02000000 */ |
| 8496 | #define CAN_F21R1_FB25_Msk (0x1UL << CAN_F21R1_FB25_Pos) /*!< 0x02000000 */ |
8496 | #define CAN_F21R1_FB25 CAN_F21R1_FB25_Msk /*!< Filter bit 25 */ |
| 8497 | #define CAN_F21R1_FB25 CAN_F21R1_FB25_Msk /*!< Filter bit 25 */ |
8497 | #define CAN_F21R1_FB26_Pos (26U) |
| 8498 | #define CAN_F21R1_FB26_Pos (26U) |
8498 | #define CAN_F21R1_FB26_Msk (0x1UL << CAN_F21R1_FB26_Pos) /*!< 0x04000000 */ |
| 8499 | #define CAN_F21R1_FB26_Msk (0x1UL << CAN_F21R1_FB26_Pos) /*!< 0x04000000 */ |
8499 | #define CAN_F21R1_FB26 CAN_F21R1_FB26_Msk /*!< Filter bit 26 */ |
| 8500 | #define CAN_F21R1_FB26 CAN_F21R1_FB26_Msk /*!< Filter bit 26 */ |
8500 | #define CAN_F21R1_FB27_Pos (27U) |
| 8501 | #define CAN_F21R1_FB27_Pos (27U) |
8501 | #define CAN_F21R1_FB27_Msk (0x1UL << CAN_F21R1_FB27_Pos) /*!< 0x08000000 */ |
| 8502 | #define CAN_F21R1_FB27_Msk (0x1UL << CAN_F21R1_FB27_Pos) /*!< 0x08000000 */ |
8502 | #define CAN_F21R1_FB27 CAN_F21R1_FB27_Msk /*!< Filter bit 27 */ |
| 8503 | #define CAN_F21R1_FB27 CAN_F21R1_FB27_Msk /*!< Filter bit 27 */ |
8503 | #define CAN_F21R1_FB28_Pos (28U) |
| 8504 | #define CAN_F21R1_FB28_Pos (28U) |
8504 | #define CAN_F21R1_FB28_Msk (0x1UL << CAN_F21R1_FB28_Pos) /*!< 0x10000000 */ |
| 8505 | #define CAN_F21R1_FB28_Msk (0x1UL << CAN_F21R1_FB28_Pos) /*!< 0x10000000 */ |
8505 | #define CAN_F21R1_FB28 CAN_F21R1_FB28_Msk /*!< Filter bit 28 */ |
| 8506 | #define CAN_F21R1_FB28 CAN_F21R1_FB28_Msk /*!< Filter bit 28 */ |
8506 | #define CAN_F21R1_FB29_Pos (29U) |
| 8507 | #define CAN_F21R1_FB29_Pos (29U) |
8507 | #define CAN_F21R1_FB29_Msk (0x1UL << CAN_F21R1_FB29_Pos) /*!< 0x20000000 */ |
| 8508 | #define CAN_F21R1_FB29_Msk (0x1UL << CAN_F21R1_FB29_Pos) /*!< 0x20000000 */ |
8508 | #define CAN_F21R1_FB29 CAN_F21R1_FB29_Msk /*!< Filter bit 29 */ |
| 8509 | #define CAN_F21R1_FB29 CAN_F21R1_FB29_Msk /*!< Filter bit 29 */ |
8509 | #define CAN_F21R1_FB30_Pos (30U) |
| 8510 | #define CAN_F21R1_FB30_Pos (30U) |
8510 | #define CAN_F21R1_FB30_Msk (0x1UL << CAN_F21R1_FB30_Pos) /*!< 0x40000000 */ |
| 8511 | #define CAN_F21R1_FB30_Msk (0x1UL << CAN_F21R1_FB30_Pos) /*!< 0x40000000 */ |
8511 | #define CAN_F21R1_FB30 CAN_F21R1_FB30_Msk /*!< Filter bit 30 */ |
| 8512 | #define CAN_F21R1_FB30 CAN_F21R1_FB30_Msk /*!< Filter bit 30 */ |
8512 | #define CAN_F21R1_FB31_Pos (31U) |
| 8513 | #define CAN_F21R1_FB31_Pos (31U) |
8513 | #define CAN_F21R1_FB31_Msk (0x1UL << CAN_F21R1_FB31_Pos) /*!< 0x80000000 */ |
| 8514 | #define CAN_F21R1_FB31_Msk (0x1UL << CAN_F21R1_FB31_Pos) /*!< 0x80000000 */ |
8514 | #define CAN_F21R1_FB31 CAN_F21R1_FB31_Msk /*!< Filter bit 31 */ |
| 8515 | #define CAN_F21R1_FB31 CAN_F21R1_FB31_Msk /*!< Filter bit 31 */ |
8515 | |
| 8516 | 8516 | /******************* Bit definition for CAN_F22R1 register ******************/ |
|
| 8517 | /******************* Bit definition for CAN_F22R1 register ******************/ |
8517 | #define CAN_F22R1_FB0_Pos (0U) |
| 8518 | #define CAN_F22R1_FB0_Pos (0U) |
8518 | #define CAN_F22R1_FB0_Msk (0x1UL << CAN_F22R1_FB0_Pos) /*!< 0x00000001 */ |
| 8519 | #define CAN_F22R1_FB0_Msk (0x1UL << CAN_F22R1_FB0_Pos) /*!< 0x00000001 */ |
8519 | #define CAN_F22R1_FB0 CAN_F22R1_FB0_Msk /*!< Filter bit 0 */ |
| 8520 | #define CAN_F22R1_FB0 CAN_F22R1_FB0_Msk /*!< Filter bit 0 */ |
8520 | #define CAN_F22R1_FB1_Pos (1U) |
| 8521 | #define CAN_F22R1_FB1_Pos (1U) |
8521 | #define CAN_F22R1_FB1_Msk (0x1UL << CAN_F22R1_FB1_Pos) /*!< 0x00000002 */ |
| 8522 | #define CAN_F22R1_FB1_Msk (0x1UL << CAN_F22R1_FB1_Pos) /*!< 0x00000002 */ |
8522 | #define CAN_F22R1_FB1 CAN_F22R1_FB1_Msk /*!< Filter bit 1 */ |
| 8523 | #define CAN_F22R1_FB1 CAN_F22R1_FB1_Msk /*!< Filter bit 1 */ |
8523 | #define CAN_F22R1_FB2_Pos (2U) |
| 8524 | #define CAN_F22R1_FB2_Pos (2U) |
8524 | #define CAN_F22R1_FB2_Msk (0x1UL << CAN_F22R1_FB2_Pos) /*!< 0x00000004 */ |
| 8525 | #define CAN_F22R1_FB2_Msk (0x1UL << CAN_F22R1_FB2_Pos) /*!< 0x00000004 */ |
8525 | #define CAN_F22R1_FB2 CAN_F22R1_FB2_Msk /*!< Filter bit 2 */ |
| 8526 | #define CAN_F22R1_FB2 CAN_F22R1_FB2_Msk /*!< Filter bit 2 */ |
8526 | #define CAN_F22R1_FB3_Pos (3U) |
| 8527 | #define CAN_F22R1_FB3_Pos (3U) |
8527 | #define CAN_F22R1_FB3_Msk (0x1UL << CAN_F22R1_FB3_Pos) /*!< 0x00000008 */ |
| 8528 | #define CAN_F22R1_FB3_Msk (0x1UL << CAN_F22R1_FB3_Pos) /*!< 0x00000008 */ |
8528 | #define CAN_F22R1_FB3 CAN_F22R1_FB3_Msk /*!< Filter bit 3 */ |
| 8529 | #define CAN_F22R1_FB3 CAN_F22R1_FB3_Msk /*!< Filter bit 3 */ |
8529 | #define CAN_F22R1_FB4_Pos (4U) |
| 8530 | #define CAN_F22R1_FB4_Pos (4U) |
8530 | #define CAN_F22R1_FB4_Msk (0x1UL << CAN_F22R1_FB4_Pos) /*!< 0x00000010 */ |
| 8531 | #define CAN_F22R1_FB4_Msk (0x1UL << CAN_F22R1_FB4_Pos) /*!< 0x00000010 */ |
8531 | #define CAN_F22R1_FB4 CAN_F22R1_FB4_Msk /*!< Filter bit 4 */ |
| 8532 | #define CAN_F22R1_FB4 CAN_F22R1_FB4_Msk /*!< Filter bit 4 */ |
8532 | #define CAN_F22R1_FB5_Pos (5U) |
| 8533 | #define CAN_F22R1_FB5_Pos (5U) |
8533 | #define CAN_F22R1_FB5_Msk (0x1UL << CAN_F22R1_FB5_Pos) /*!< 0x00000020 */ |
| 8534 | #define CAN_F22R1_FB5_Msk (0x1UL << CAN_F22R1_FB5_Pos) /*!< 0x00000020 */ |
8534 | #define CAN_F22R1_FB5 CAN_F22R1_FB5_Msk /*!< Filter bit 5 */ |
| 8535 | #define CAN_F22R1_FB5 CAN_F22R1_FB5_Msk /*!< Filter bit 5 */ |
8535 | #define CAN_F22R1_FB6_Pos (6U) |
| 8536 | #define CAN_F22R1_FB6_Pos (6U) |
8536 | #define CAN_F22R1_FB6_Msk (0x1UL << CAN_F22R1_FB6_Pos) /*!< 0x00000040 */ |
| 8537 | #define CAN_F22R1_FB6_Msk (0x1UL << CAN_F22R1_FB6_Pos) /*!< 0x00000040 */ |
8537 | #define CAN_F22R1_FB6 CAN_F22R1_FB6_Msk /*!< Filter bit 6 */ |
| 8538 | #define CAN_F22R1_FB6 CAN_F22R1_FB6_Msk /*!< Filter bit 6 */ |
8538 | #define CAN_F22R1_FB7_Pos (7U) |
| 8539 | #define CAN_F22R1_FB7_Pos (7U) |
8539 | #define CAN_F22R1_FB7_Msk (0x1UL << CAN_F22R1_FB7_Pos) /*!< 0x00000080 */ |
| 8540 | #define CAN_F22R1_FB7_Msk (0x1UL << CAN_F22R1_FB7_Pos) /*!< 0x00000080 */ |
8540 | #define CAN_F22R1_FB7 CAN_F22R1_FB7_Msk /*!< Filter bit 7 */ |
| 8541 | #define CAN_F22R1_FB7 CAN_F22R1_FB7_Msk /*!< Filter bit 7 */ |
8541 | #define CAN_F22R1_FB8_Pos (8U) |
| 8542 | #define CAN_F22R1_FB8_Pos (8U) |
8542 | #define CAN_F22R1_FB8_Msk (0x1UL << CAN_F22R1_FB8_Pos) /*!< 0x00000100 */ |
| 8543 | #define CAN_F22R1_FB8_Msk (0x1UL << CAN_F22R1_FB8_Pos) /*!< 0x00000100 */ |
8543 | #define CAN_F22R1_FB8 CAN_F22R1_FB8_Msk /*!< Filter bit 8 */ |
| 8544 | #define CAN_F22R1_FB8 CAN_F22R1_FB8_Msk /*!< Filter bit 8 */ |
8544 | #define CAN_F22R1_FB9_Pos (9U) |
| 8545 | #define CAN_F22R1_FB9_Pos (9U) |
8545 | #define CAN_F22R1_FB9_Msk (0x1UL << CAN_F22R1_FB9_Pos) /*!< 0x00000200 */ |
| 8546 | #define CAN_F22R1_FB9_Msk (0x1UL << CAN_F22R1_FB9_Pos) /*!< 0x00000200 */ |
8546 | #define CAN_F22R1_FB9 CAN_F22R1_FB9_Msk /*!< Filter bit 9 */ |
| 8547 | #define CAN_F22R1_FB9 CAN_F22R1_FB9_Msk /*!< Filter bit 9 */ |
8547 | #define CAN_F22R1_FB10_Pos (10U) |
| 8548 | #define CAN_F22R1_FB10_Pos (10U) |
8548 | #define CAN_F22R1_FB10_Msk (0x1UL << CAN_F22R1_FB10_Pos) /*!< 0x00000400 */ |
| 8549 | #define CAN_F22R1_FB10_Msk (0x1UL << CAN_F22R1_FB10_Pos) /*!< 0x00000400 */ |
8549 | #define CAN_F22R1_FB10 CAN_F22R1_FB10_Msk /*!< Filter bit 10 */ |
| 8550 | #define CAN_F22R1_FB10 CAN_F22R1_FB10_Msk /*!< Filter bit 10 */ |
8550 | #define CAN_F22R1_FB11_Pos (11U) |
| 8551 | #define CAN_F22R1_FB11_Pos (11U) |
8551 | #define CAN_F22R1_FB11_Msk (0x1UL << CAN_F22R1_FB11_Pos) /*!< 0x00000800 */ |
| 8552 | #define CAN_F22R1_FB11_Msk (0x1UL << CAN_F22R1_FB11_Pos) /*!< 0x00000800 */ |
8552 | #define CAN_F22R1_FB11 CAN_F22R1_FB11_Msk /*!< Filter bit 11 */ |
| 8553 | #define CAN_F22R1_FB11 CAN_F22R1_FB11_Msk /*!< Filter bit 11 */ |
8553 | #define CAN_F22R1_FB12_Pos (12U) |
| 8554 | #define CAN_F22R1_FB12_Pos (12U) |
8554 | #define CAN_F22R1_FB12_Msk (0x1UL << CAN_F22R1_FB12_Pos) /*!< 0x00001000 */ |
| 8555 | #define CAN_F22R1_FB12_Msk (0x1UL << CAN_F22R1_FB12_Pos) /*!< 0x00001000 */ |
8555 | #define CAN_F22R1_FB12 CAN_F22R1_FB12_Msk /*!< Filter bit 12 */ |
| 8556 | #define CAN_F22R1_FB12 CAN_F22R1_FB12_Msk /*!< Filter bit 12 */ |
8556 | #define CAN_F22R1_FB13_Pos (13U) |
| 8557 | #define CAN_F22R1_FB13_Pos (13U) |
8557 | #define CAN_F22R1_FB13_Msk (0x1UL << CAN_F22R1_FB13_Pos) /*!< 0x00002000 */ |
| 8558 | #define CAN_F22R1_FB13_Msk (0x1UL << CAN_F22R1_FB13_Pos) /*!< 0x00002000 */ |
8558 | #define CAN_F22R1_FB13 CAN_F22R1_FB13_Msk /*!< Filter bit 13 */ |
| 8559 | #define CAN_F22R1_FB13 CAN_F22R1_FB13_Msk /*!< Filter bit 13 */ |
8559 | #define CAN_F22R1_FB14_Pos (14U) |
| 8560 | #define CAN_F22R1_FB14_Pos (14U) |
8560 | #define CAN_F22R1_FB14_Msk (0x1UL << CAN_F22R1_FB14_Pos) /*!< 0x00004000 */ |
| 8561 | #define CAN_F22R1_FB14_Msk (0x1UL << CAN_F22R1_FB14_Pos) /*!< 0x00004000 */ |
8561 | #define CAN_F22R1_FB14 CAN_F22R1_FB14_Msk /*!< Filter bit 14 */ |
| 8562 | #define CAN_F22R1_FB14 CAN_F22R1_FB14_Msk /*!< Filter bit 14 */ |
8562 | #define CAN_F22R1_FB15_Pos (15U) |
| 8563 | #define CAN_F22R1_FB15_Pos (15U) |
8563 | #define CAN_F22R1_FB15_Msk (0x1UL << CAN_F22R1_FB15_Pos) /*!< 0x00008000 */ |
| 8564 | #define CAN_F22R1_FB15_Msk (0x1UL << CAN_F22R1_FB15_Pos) /*!< 0x00008000 */ |
8564 | #define CAN_F22R1_FB15 CAN_F22R1_FB15_Msk /*!< Filter bit 15 */ |
| 8565 | #define CAN_F22R1_FB15 CAN_F22R1_FB15_Msk /*!< Filter bit 15 */ |
8565 | #define CAN_F22R1_FB16_Pos (16U) |
| 8566 | #define CAN_F22R1_FB16_Pos (16U) |
8566 | #define CAN_F22R1_FB16_Msk (0x1UL << CAN_F22R1_FB16_Pos) /*!< 0x00010000 */ |
| 8567 | #define CAN_F22R1_FB16_Msk (0x1UL << CAN_F22R1_FB16_Pos) /*!< 0x00010000 */ |
8567 | #define CAN_F22R1_FB16 CAN_F22R1_FB16_Msk /*!< Filter bit 16 */ |
| 8568 | #define CAN_F22R1_FB16 CAN_F22R1_FB16_Msk /*!< Filter bit 16 */ |
8568 | #define CAN_F22R1_FB17_Pos (17U) |
| 8569 | #define CAN_F22R1_FB17_Pos (17U) |
8569 | #define CAN_F22R1_FB17_Msk (0x1UL << CAN_F22R1_FB17_Pos) /*!< 0x00020000 */ |
| 8570 | #define CAN_F22R1_FB17_Msk (0x1UL << CAN_F22R1_FB17_Pos) /*!< 0x00020000 */ |
8570 | #define CAN_F22R1_FB17 CAN_F22R1_FB17_Msk /*!< Filter bit 17 */ |
| 8571 | #define CAN_F22R1_FB17 CAN_F22R1_FB17_Msk /*!< Filter bit 17 */ |
8571 | #define CAN_F22R1_FB18_Pos (18U) |
| 8572 | #define CAN_F22R1_FB18_Pos (18U) |
8572 | #define CAN_F22R1_FB18_Msk (0x1UL << CAN_F22R1_FB18_Pos) /*!< 0x00040000 */ |
| 8573 | #define CAN_F22R1_FB18_Msk (0x1UL << CAN_F22R1_FB18_Pos) /*!< 0x00040000 */ |
8573 | #define CAN_F22R1_FB18 CAN_F22R1_FB18_Msk /*!< Filter bit 18 */ |
| 8574 | #define CAN_F22R1_FB18 CAN_F22R1_FB18_Msk /*!< Filter bit 18 */ |
8574 | #define CAN_F22R1_FB19_Pos (19U) |
| 8575 | #define CAN_F22R1_FB19_Pos (19U) |
8575 | #define CAN_F22R1_FB19_Msk (0x1UL << CAN_F22R1_FB19_Pos) /*!< 0x00080000 */ |
| 8576 | #define CAN_F22R1_FB19_Msk (0x1UL << CAN_F22R1_FB19_Pos) /*!< 0x00080000 */ |
8576 | #define CAN_F22R1_FB19 CAN_F22R1_FB19_Msk /*!< Filter bit 19 */ |
| 8577 | #define CAN_F22R1_FB19 CAN_F22R1_FB19_Msk /*!< Filter bit 19 */ |
8577 | #define CAN_F22R1_FB20_Pos (20U) |
| 8578 | #define CAN_F22R1_FB20_Pos (20U) |
8578 | #define CAN_F22R1_FB20_Msk (0x1UL << CAN_F22R1_FB20_Pos) /*!< 0x00100000 */ |
| 8579 | #define CAN_F22R1_FB20_Msk (0x1UL << CAN_F22R1_FB20_Pos) /*!< 0x00100000 */ |
8579 | #define CAN_F22R1_FB20 CAN_F22R1_FB20_Msk /*!< Filter bit 20 */ |
| 8580 | #define CAN_F22R1_FB20 CAN_F22R1_FB20_Msk /*!< Filter bit 20 */ |
8580 | #define CAN_F22R1_FB21_Pos (21U) |
| 8581 | #define CAN_F22R1_FB21_Pos (21U) |
8581 | #define CAN_F22R1_FB21_Msk (0x1UL << CAN_F22R1_FB21_Pos) /*!< 0x00200000 */ |
| 8582 | #define CAN_F22R1_FB21_Msk (0x1UL << CAN_F22R1_FB21_Pos) /*!< 0x00200000 */ |
8582 | #define CAN_F22R1_FB21 CAN_F22R1_FB21_Msk /*!< Filter bit 21 */ |
| 8583 | #define CAN_F22R1_FB21 CAN_F22R1_FB21_Msk /*!< Filter bit 21 */ |
8583 | #define CAN_F22R1_FB22_Pos (22U) |
| 8584 | #define CAN_F22R1_FB22_Pos (22U) |
8584 | #define CAN_F22R1_FB22_Msk (0x1UL << CAN_F22R1_FB22_Pos) /*!< 0x00400000 */ |
| 8585 | #define CAN_F22R1_FB22_Msk (0x1UL << CAN_F22R1_FB22_Pos) /*!< 0x00400000 */ |
8585 | #define CAN_F22R1_FB22 CAN_F22R1_FB22_Msk /*!< Filter bit 22 */ |
| 8586 | #define CAN_F22R1_FB22 CAN_F22R1_FB22_Msk /*!< Filter bit 22 */ |
8586 | #define CAN_F22R1_FB23_Pos (23U) |
| 8587 | #define CAN_F22R1_FB23_Pos (23U) |
8587 | #define CAN_F22R1_FB23_Msk (0x1UL << CAN_F22R1_FB23_Pos) /*!< 0x00800000 */ |
| 8588 | #define CAN_F22R1_FB23_Msk (0x1UL << CAN_F22R1_FB23_Pos) /*!< 0x00800000 */ |
8588 | #define CAN_F22R1_FB23 CAN_F22R1_FB23_Msk /*!< Filter bit 23 */ |
| 8589 | #define CAN_F22R1_FB23 CAN_F22R1_FB23_Msk /*!< Filter bit 23 */ |
8589 | #define CAN_F22R1_FB24_Pos (24U) |
| 8590 | #define CAN_F22R1_FB24_Pos (24U) |
8590 | #define CAN_F22R1_FB24_Msk (0x1UL << CAN_F22R1_FB24_Pos) /*!< 0x01000000 */ |
| 8591 | #define CAN_F22R1_FB24_Msk (0x1UL << CAN_F22R1_FB24_Pos) /*!< 0x01000000 */ |
8591 | #define CAN_F22R1_FB24 CAN_F22R1_FB24_Msk /*!< Filter bit 24 */ |
| 8592 | #define CAN_F22R1_FB24 CAN_F22R1_FB24_Msk /*!< Filter bit 24 */ |
8592 | #define CAN_F22R1_FB25_Pos (25U) |
| 8593 | #define CAN_F22R1_FB25_Pos (25U) |
8593 | #define CAN_F22R1_FB25_Msk (0x1UL << CAN_F22R1_FB25_Pos) /*!< 0x02000000 */ |
| 8594 | #define CAN_F22R1_FB25_Msk (0x1UL << CAN_F22R1_FB25_Pos) /*!< 0x02000000 */ |
8594 | #define CAN_F22R1_FB25 CAN_F22R1_FB25_Msk /*!< Filter bit 25 */ |
| 8595 | #define CAN_F22R1_FB25 CAN_F22R1_FB25_Msk /*!< Filter bit 25 */ |
8595 | #define CAN_F22R1_FB26_Pos (26U) |
| 8596 | #define CAN_F22R1_FB26_Pos (26U) |
8596 | #define CAN_F22R1_FB26_Msk (0x1UL << CAN_F22R1_FB26_Pos) /*!< 0x04000000 */ |
| 8597 | #define CAN_F22R1_FB26_Msk (0x1UL << CAN_F22R1_FB26_Pos) /*!< 0x04000000 */ |
8597 | #define CAN_F22R1_FB26 CAN_F22R1_FB26_Msk /*!< Filter bit 26 */ |
| 8598 | #define CAN_F22R1_FB26 CAN_F22R1_FB26_Msk /*!< Filter bit 26 */ |
8598 | #define CAN_F22R1_FB27_Pos (27U) |
| 8599 | #define CAN_F22R1_FB27_Pos (27U) |
8599 | #define CAN_F22R1_FB27_Msk (0x1UL << CAN_F22R1_FB27_Pos) /*!< 0x08000000 */ |
| 8600 | #define CAN_F22R1_FB27_Msk (0x1UL << CAN_F22R1_FB27_Pos) /*!< 0x08000000 */ |
8600 | #define CAN_F22R1_FB27 CAN_F22R1_FB27_Msk /*!< Filter bit 27 */ |
| 8601 | #define CAN_F22R1_FB27 CAN_F22R1_FB27_Msk /*!< Filter bit 27 */ |
8601 | #define CAN_F22R1_FB28_Pos (28U) |
| 8602 | #define CAN_F22R1_FB28_Pos (28U) |
8602 | #define CAN_F22R1_FB28_Msk (0x1UL << CAN_F22R1_FB28_Pos) /*!< 0x10000000 */ |
| 8603 | #define CAN_F22R1_FB28_Msk (0x1UL << CAN_F22R1_FB28_Pos) /*!< 0x10000000 */ |
8603 | #define CAN_F22R1_FB28 CAN_F22R1_FB28_Msk /*!< Filter bit 28 */ |
| 8604 | #define CAN_F22R1_FB28 CAN_F22R1_FB28_Msk /*!< Filter bit 28 */ |
8604 | #define CAN_F22R1_FB29_Pos (29U) |
| 8605 | #define CAN_F22R1_FB29_Pos (29U) |
8605 | #define CAN_F22R1_FB29_Msk (0x1UL << CAN_F22R1_FB29_Pos) /*!< 0x20000000 */ |
| 8606 | #define CAN_F22R1_FB29_Msk (0x1UL << CAN_F22R1_FB29_Pos) /*!< 0x20000000 */ |
8606 | #define CAN_F22R1_FB29 CAN_F22R1_FB29_Msk /*!< Filter bit 29 */ |
| 8607 | #define CAN_F22R1_FB29 CAN_F22R1_FB29_Msk /*!< Filter bit 29 */ |
8607 | #define CAN_F22R1_FB30_Pos (30U) |
| 8608 | #define CAN_F22R1_FB30_Pos (30U) |
8608 | #define CAN_F22R1_FB30_Msk (0x1UL << CAN_F22R1_FB30_Pos) /*!< 0x40000000 */ |
| 8609 | #define CAN_F22R1_FB30_Msk (0x1UL << CAN_F22R1_FB30_Pos) /*!< 0x40000000 */ |
8609 | #define CAN_F22R1_FB30 CAN_F22R1_FB30_Msk /*!< Filter bit 30 */ |
| 8610 | #define CAN_F22R1_FB30 CAN_F22R1_FB30_Msk /*!< Filter bit 30 */ |
8610 | #define CAN_F22R1_FB31_Pos (31U) |
| 8611 | #define CAN_F22R1_FB31_Pos (31U) |
8611 | #define CAN_F22R1_FB31_Msk (0x1UL << CAN_F22R1_FB31_Pos) /*!< 0x80000000 */ |
| 8612 | #define CAN_F22R1_FB31_Msk (0x1UL << CAN_F22R1_FB31_Pos) /*!< 0x80000000 */ |
8612 | #define CAN_F22R1_FB31 CAN_F22R1_FB31_Msk /*!< Filter bit 31 */ |
| 8613 | #define CAN_F22R1_FB31 CAN_F22R1_FB31_Msk /*!< Filter bit 31 */ |
8613 | |
| 8614 | 8614 | /******************* Bit definition for CAN_F23R1 register ******************/ |
|
| 8615 | /******************* Bit definition for CAN_F23R1 register ******************/ |
8615 | #define CAN_F23R1_FB0_Pos (0U) |
| 8616 | #define CAN_F23R1_FB0_Pos (0U) |
8616 | #define CAN_F23R1_FB0_Msk (0x1UL << CAN_F23R1_FB0_Pos) /*!< 0x00000001 */ |
| 8617 | #define CAN_F23R1_FB0_Msk (0x1UL << CAN_F23R1_FB0_Pos) /*!< 0x00000001 */ |
8617 | #define CAN_F23R1_FB0 CAN_F23R1_FB0_Msk /*!< Filter bit 0 */ |
| 8618 | #define CAN_F23R1_FB0 CAN_F23R1_FB0_Msk /*!< Filter bit 0 */ |
8618 | #define CAN_F23R1_FB1_Pos (1U) |
| 8619 | #define CAN_F23R1_FB1_Pos (1U) |
8619 | #define CAN_F23R1_FB1_Msk (0x1UL << CAN_F23R1_FB1_Pos) /*!< 0x00000002 */ |
| 8620 | #define CAN_F23R1_FB1_Msk (0x1UL << CAN_F23R1_FB1_Pos) /*!< 0x00000002 */ |
8620 | #define CAN_F23R1_FB1 CAN_F23R1_FB1_Msk /*!< Filter bit 1 */ |
| 8621 | #define CAN_F23R1_FB1 CAN_F23R1_FB1_Msk /*!< Filter bit 1 */ |
8621 | #define CAN_F23R1_FB2_Pos (2U) |
| 8622 | #define CAN_F23R1_FB2_Pos (2U) |
8622 | #define CAN_F23R1_FB2_Msk (0x1UL << CAN_F23R1_FB2_Pos) /*!< 0x00000004 */ |
| 8623 | #define CAN_F23R1_FB2_Msk (0x1UL << CAN_F23R1_FB2_Pos) /*!< 0x00000004 */ |
8623 | #define CAN_F23R1_FB2 CAN_F23R1_FB2_Msk /*!< Filter bit 2 */ |
| 8624 | #define CAN_F23R1_FB2 CAN_F23R1_FB2_Msk /*!< Filter bit 2 */ |
8624 | #define CAN_F23R1_FB3_Pos (3U) |
| 8625 | #define CAN_F23R1_FB3_Pos (3U) |
8625 | #define CAN_F23R1_FB3_Msk (0x1UL << CAN_F23R1_FB3_Pos) /*!< 0x00000008 */ |
| 8626 | #define CAN_F23R1_FB3_Msk (0x1UL << CAN_F23R1_FB3_Pos) /*!< 0x00000008 */ |
8626 | #define CAN_F23R1_FB3 CAN_F23R1_FB3_Msk /*!< Filter bit 3 */ |
| 8627 | #define CAN_F23R1_FB3 CAN_F23R1_FB3_Msk /*!< Filter bit 3 */ |
8627 | #define CAN_F23R1_FB4_Pos (4U) |
| 8628 | #define CAN_F23R1_FB4_Pos (4U) |
8628 | #define CAN_F23R1_FB4_Msk (0x1UL << CAN_F23R1_FB4_Pos) /*!< 0x00000010 */ |
| 8629 | #define CAN_F23R1_FB4_Msk (0x1UL << CAN_F23R1_FB4_Pos) /*!< 0x00000010 */ |
8629 | #define CAN_F23R1_FB4 CAN_F23R1_FB4_Msk /*!< Filter bit 4 */ |
| 8630 | #define CAN_F23R1_FB4 CAN_F23R1_FB4_Msk /*!< Filter bit 4 */ |
8630 | #define CAN_F23R1_FB5_Pos (5U) |
| 8631 | #define CAN_F23R1_FB5_Pos (5U) |
8631 | #define CAN_F23R1_FB5_Msk (0x1UL << CAN_F23R1_FB5_Pos) /*!< 0x00000020 */ |
| 8632 | #define CAN_F23R1_FB5_Msk (0x1UL << CAN_F23R1_FB5_Pos) /*!< 0x00000020 */ |
8632 | #define CAN_F23R1_FB5 CAN_F23R1_FB5_Msk /*!< Filter bit 5 */ |
| 8633 | #define CAN_F23R1_FB5 CAN_F23R1_FB5_Msk /*!< Filter bit 5 */ |
8633 | #define CAN_F23R1_FB6_Pos (6U) |
| 8634 | #define CAN_F23R1_FB6_Pos (6U) |
8634 | #define CAN_F23R1_FB6_Msk (0x1UL << CAN_F23R1_FB6_Pos) /*!< 0x00000040 */ |
| 8635 | #define CAN_F23R1_FB6_Msk (0x1UL << CAN_F23R1_FB6_Pos) /*!< 0x00000040 */ |
8635 | #define CAN_F23R1_FB6 CAN_F23R1_FB6_Msk /*!< Filter bit 6 */ |
| 8636 | #define CAN_F23R1_FB6 CAN_F23R1_FB6_Msk /*!< Filter bit 6 */ |
8636 | #define CAN_F23R1_FB7_Pos (7U) |
| 8637 | #define CAN_F23R1_FB7_Pos (7U) |
8637 | #define CAN_F23R1_FB7_Msk (0x1UL << CAN_F23R1_FB7_Pos) /*!< 0x00000080 */ |
| 8638 | #define CAN_F23R1_FB7_Msk (0x1UL << CAN_F23R1_FB7_Pos) /*!< 0x00000080 */ |
8638 | #define CAN_F23R1_FB7 CAN_F23R1_FB7_Msk /*!< Filter bit 7 */ |
| 8639 | #define CAN_F23R1_FB7 CAN_F23R1_FB7_Msk /*!< Filter bit 7 */ |
8639 | #define CAN_F23R1_FB8_Pos (8U) |
| 8640 | #define CAN_F23R1_FB8_Pos (8U) |
8640 | #define CAN_F23R1_FB8_Msk (0x1UL << CAN_F23R1_FB8_Pos) /*!< 0x00000100 */ |
| 8641 | #define CAN_F23R1_FB8_Msk (0x1UL << CAN_F23R1_FB8_Pos) /*!< 0x00000100 */ |
8641 | #define CAN_F23R1_FB8 CAN_F23R1_FB8_Msk /*!< Filter bit 8 */ |
| 8642 | #define CAN_F23R1_FB8 CAN_F23R1_FB8_Msk /*!< Filter bit 8 */ |
8642 | #define CAN_F23R1_FB9_Pos (9U) |
| 8643 | #define CAN_F23R1_FB9_Pos (9U) |
8643 | #define CAN_F23R1_FB9_Msk (0x1UL << CAN_F23R1_FB9_Pos) /*!< 0x00000200 */ |
| 8644 | #define CAN_F23R1_FB9_Msk (0x1UL << CAN_F23R1_FB9_Pos) /*!< 0x00000200 */ |
8644 | #define CAN_F23R1_FB9 CAN_F23R1_FB9_Msk /*!< Filter bit 9 */ |
| 8645 | #define CAN_F23R1_FB9 CAN_F23R1_FB9_Msk /*!< Filter bit 9 */ |
8645 | #define CAN_F23R1_FB10_Pos (10U) |
| 8646 | #define CAN_F23R1_FB10_Pos (10U) |
8646 | #define CAN_F23R1_FB10_Msk (0x1UL << CAN_F23R1_FB10_Pos) /*!< 0x00000400 */ |
| 8647 | #define CAN_F23R1_FB10_Msk (0x1UL << CAN_F23R1_FB10_Pos) /*!< 0x00000400 */ |
8647 | #define CAN_F23R1_FB10 CAN_F23R1_FB10_Msk /*!< Filter bit 10 */ |
| 8648 | #define CAN_F23R1_FB10 CAN_F23R1_FB10_Msk /*!< Filter bit 10 */ |
8648 | #define CAN_F23R1_FB11_Pos (11U) |
| 8649 | #define CAN_F23R1_FB11_Pos (11U) |
8649 | #define CAN_F23R1_FB11_Msk (0x1UL << CAN_F23R1_FB11_Pos) /*!< 0x00000800 */ |
| 8650 | #define CAN_F23R1_FB11_Msk (0x1UL << CAN_F23R1_FB11_Pos) /*!< 0x00000800 */ |
8650 | #define CAN_F23R1_FB11 CAN_F23R1_FB11_Msk /*!< Filter bit 11 */ |
| 8651 | #define CAN_F23R1_FB11 CAN_F23R1_FB11_Msk /*!< Filter bit 11 */ |
8651 | #define CAN_F23R1_FB12_Pos (12U) |
| 8652 | #define CAN_F23R1_FB12_Pos (12U) |
8652 | #define CAN_F23R1_FB12_Msk (0x1UL << CAN_F23R1_FB12_Pos) /*!< 0x00001000 */ |
| 8653 | #define CAN_F23R1_FB12_Msk (0x1UL << CAN_F23R1_FB12_Pos) /*!< 0x00001000 */ |
8653 | #define CAN_F23R1_FB12 CAN_F23R1_FB12_Msk /*!< Filter bit 12 */ |
| 8654 | #define CAN_F23R1_FB12 CAN_F23R1_FB12_Msk /*!< Filter bit 12 */ |
8654 | #define CAN_F23R1_FB13_Pos (13U) |
| 8655 | #define CAN_F23R1_FB13_Pos (13U) |
8655 | #define CAN_F23R1_FB13_Msk (0x1UL << CAN_F23R1_FB13_Pos) /*!< 0x00002000 */ |
| 8656 | #define CAN_F23R1_FB13_Msk (0x1UL << CAN_F23R1_FB13_Pos) /*!< 0x00002000 */ |
8656 | #define CAN_F23R1_FB13 CAN_F23R1_FB13_Msk /*!< Filter bit 13 */ |
| 8657 | #define CAN_F23R1_FB13 CAN_F23R1_FB13_Msk /*!< Filter bit 13 */ |
8657 | #define CAN_F23R1_FB14_Pos (14U) |
| 8658 | #define CAN_F23R1_FB14_Pos (14U) |
8658 | #define CAN_F23R1_FB14_Msk (0x1UL << CAN_F23R1_FB14_Pos) /*!< 0x00004000 */ |
| 8659 | #define CAN_F23R1_FB14_Msk (0x1UL << CAN_F23R1_FB14_Pos) /*!< 0x00004000 */ |
8659 | #define CAN_F23R1_FB14 CAN_F23R1_FB14_Msk /*!< Filter bit 14 */ |
| 8660 | #define CAN_F23R1_FB14 CAN_F23R1_FB14_Msk /*!< Filter bit 14 */ |
8660 | #define CAN_F23R1_FB15_Pos (15U) |
| 8661 | #define CAN_F23R1_FB15_Pos (15U) |
8661 | #define CAN_F23R1_FB15_Msk (0x1UL << CAN_F23R1_FB15_Pos) /*!< 0x00008000 */ |
| 8662 | #define CAN_F23R1_FB15_Msk (0x1UL << CAN_F23R1_FB15_Pos) /*!< 0x00008000 */ |
8662 | #define CAN_F23R1_FB15 CAN_F23R1_FB15_Msk /*!< Filter bit 15 */ |
| 8663 | #define CAN_F23R1_FB15 CAN_F23R1_FB15_Msk /*!< Filter bit 15 */ |
8663 | #define CAN_F23R1_FB16_Pos (16U) |
| 8664 | #define CAN_F23R1_FB16_Pos (16U) |
8664 | #define CAN_F23R1_FB16_Msk (0x1UL << CAN_F23R1_FB16_Pos) /*!< 0x00010000 */ |
| 8665 | #define CAN_F23R1_FB16_Msk (0x1UL << CAN_F23R1_FB16_Pos) /*!< 0x00010000 */ |
8665 | #define CAN_F23R1_FB16 CAN_F23R1_FB16_Msk /*!< Filter bit 16 */ |
| 8666 | #define CAN_F23R1_FB16 CAN_F23R1_FB16_Msk /*!< Filter bit 16 */ |
8666 | #define CAN_F23R1_FB17_Pos (17U) |
| 8667 | #define CAN_F23R1_FB17_Pos (17U) |
8667 | #define CAN_F23R1_FB17_Msk (0x1UL << CAN_F23R1_FB17_Pos) /*!< 0x00020000 */ |
| 8668 | #define CAN_F23R1_FB17_Msk (0x1UL << CAN_F23R1_FB17_Pos) /*!< 0x00020000 */ |
8668 | #define CAN_F23R1_FB17 CAN_F23R1_FB17_Msk /*!< Filter bit 17 */ |
| 8669 | #define CAN_F23R1_FB17 CAN_F23R1_FB17_Msk /*!< Filter bit 17 */ |
8669 | #define CAN_F23R1_FB18_Pos (18U) |
| 8670 | #define CAN_F23R1_FB18_Pos (18U) |
8670 | #define CAN_F23R1_FB18_Msk (0x1UL << CAN_F23R1_FB18_Pos) /*!< 0x00040000 */ |
| 8671 | #define CAN_F23R1_FB18_Msk (0x1UL << CAN_F23R1_FB18_Pos) /*!< 0x00040000 */ |
8671 | #define CAN_F23R1_FB18 CAN_F23R1_FB18_Msk /*!< Filter bit 18 */ |
| 8672 | #define CAN_F23R1_FB18 CAN_F23R1_FB18_Msk /*!< Filter bit 18 */ |
8672 | #define CAN_F23R1_FB19_Pos (19U) |
| 8673 | #define CAN_F23R1_FB19_Pos (19U) |
8673 | #define CAN_F23R1_FB19_Msk (0x1UL << CAN_F23R1_FB19_Pos) /*!< 0x00080000 */ |
| 8674 | #define CAN_F23R1_FB19_Msk (0x1UL << CAN_F23R1_FB19_Pos) /*!< 0x00080000 */ |
8674 | #define CAN_F23R1_FB19 CAN_F23R1_FB19_Msk /*!< Filter bit 19 */ |
| 8675 | #define CAN_F23R1_FB19 CAN_F23R1_FB19_Msk /*!< Filter bit 19 */ |
8675 | #define CAN_F23R1_FB20_Pos (20U) |
| 8676 | #define CAN_F23R1_FB20_Pos (20U) |
8676 | #define CAN_F23R1_FB20_Msk (0x1UL << CAN_F23R1_FB20_Pos) /*!< 0x00100000 */ |
| 8677 | #define CAN_F23R1_FB20_Msk (0x1UL << CAN_F23R1_FB20_Pos) /*!< 0x00100000 */ |
8677 | #define CAN_F23R1_FB20 CAN_F23R1_FB20_Msk /*!< Filter bit 20 */ |
| 8678 | #define CAN_F23R1_FB20 CAN_F23R1_FB20_Msk /*!< Filter bit 20 */ |
8678 | #define CAN_F23R1_FB21_Pos (21U) |
| 8679 | #define CAN_F23R1_FB21_Pos (21U) |
8679 | #define CAN_F23R1_FB21_Msk (0x1UL << CAN_F23R1_FB21_Pos) /*!< 0x00200000 */ |
| 8680 | #define CAN_F23R1_FB21_Msk (0x1UL << CAN_F23R1_FB21_Pos) /*!< 0x00200000 */ |
8680 | #define CAN_F23R1_FB21 CAN_F23R1_FB21_Msk /*!< Filter bit 21 */ |
| 8681 | #define CAN_F23R1_FB21 CAN_F23R1_FB21_Msk /*!< Filter bit 21 */ |
8681 | #define CAN_F23R1_FB22_Pos (22U) |
| 8682 | #define CAN_F23R1_FB22_Pos (22U) |
8682 | #define CAN_F23R1_FB22_Msk (0x1UL << CAN_F23R1_FB22_Pos) /*!< 0x00400000 */ |
| 8683 | #define CAN_F23R1_FB22_Msk (0x1UL << CAN_F23R1_FB22_Pos) /*!< 0x00400000 */ |
8683 | #define CAN_F23R1_FB22 CAN_F23R1_FB22_Msk /*!< Filter bit 22 */ |
| 8684 | #define CAN_F23R1_FB22 CAN_F23R1_FB22_Msk /*!< Filter bit 22 */ |
8684 | #define CAN_F23R1_FB23_Pos (23U) |
| 8685 | #define CAN_F23R1_FB23_Pos (23U) |
8685 | #define CAN_F23R1_FB23_Msk (0x1UL << CAN_F23R1_FB23_Pos) /*!< 0x00800000 */ |
| 8686 | #define CAN_F23R1_FB23_Msk (0x1UL << CAN_F23R1_FB23_Pos) /*!< 0x00800000 */ |
8686 | #define CAN_F23R1_FB23 CAN_F23R1_FB23_Msk /*!< Filter bit 23 */ |
| 8687 | #define CAN_F23R1_FB23 CAN_F23R1_FB23_Msk /*!< Filter bit 23 */ |
8687 | #define CAN_F23R1_FB24_Pos (24U) |
| 8688 | #define CAN_F23R1_FB24_Pos (24U) |
8688 | #define CAN_F23R1_FB24_Msk (0x1UL << CAN_F23R1_FB24_Pos) /*!< 0x01000000 */ |
| 8689 | #define CAN_F23R1_FB24_Msk (0x1UL << CAN_F23R1_FB24_Pos) /*!< 0x01000000 */ |
8689 | #define CAN_F23R1_FB24 CAN_F23R1_FB24_Msk /*!< Filter bit 24 */ |
| 8690 | #define CAN_F23R1_FB24 CAN_F23R1_FB24_Msk /*!< Filter bit 24 */ |
8690 | #define CAN_F23R1_FB25_Pos (25U) |
| 8691 | #define CAN_F23R1_FB25_Pos (25U) |
8691 | #define CAN_F23R1_FB25_Msk (0x1UL << CAN_F23R1_FB25_Pos) /*!< 0x02000000 */ |
| 8692 | #define CAN_F23R1_FB25_Msk (0x1UL << CAN_F23R1_FB25_Pos) /*!< 0x02000000 */ |
8692 | #define CAN_F23R1_FB25 CAN_F23R1_FB25_Msk /*!< Filter bit 25 */ |
| 8693 | #define CAN_F23R1_FB25 CAN_F23R1_FB25_Msk /*!< Filter bit 25 */ |
8693 | #define CAN_F23R1_FB26_Pos (26U) |
| 8694 | #define CAN_F23R1_FB26_Pos (26U) |
8694 | #define CAN_F23R1_FB26_Msk (0x1UL << CAN_F23R1_FB26_Pos) /*!< 0x04000000 */ |
| 8695 | #define CAN_F23R1_FB26_Msk (0x1UL << CAN_F23R1_FB26_Pos) /*!< 0x04000000 */ |
8695 | #define CAN_F23R1_FB26 CAN_F23R1_FB26_Msk /*!< Filter bit 26 */ |
| 8696 | #define CAN_F23R1_FB26 CAN_F23R1_FB26_Msk /*!< Filter bit 26 */ |
8696 | #define CAN_F23R1_FB27_Pos (27U) |
| 8697 | #define CAN_F23R1_FB27_Pos (27U) |
8697 | #define CAN_F23R1_FB27_Msk (0x1UL << CAN_F23R1_FB27_Pos) /*!< 0x08000000 */ |
| 8698 | #define CAN_F23R1_FB27_Msk (0x1UL << CAN_F23R1_FB27_Pos) /*!< 0x08000000 */ |
8698 | #define CAN_F23R1_FB27 CAN_F23R1_FB27_Msk /*!< Filter bit 27 */ |
| 8699 | #define CAN_F23R1_FB27 CAN_F23R1_FB27_Msk /*!< Filter bit 27 */ |
8699 | #define CAN_F23R1_FB28_Pos (28U) |
| 8700 | #define CAN_F23R1_FB28_Pos (28U) |
8700 | #define CAN_F23R1_FB28_Msk (0x1UL << CAN_F23R1_FB28_Pos) /*!< 0x10000000 */ |
| 8701 | #define CAN_F23R1_FB28_Msk (0x1UL << CAN_F23R1_FB28_Pos) /*!< 0x10000000 */ |
8701 | #define CAN_F23R1_FB28 CAN_F23R1_FB28_Msk /*!< Filter bit 28 */ |
| 8702 | #define CAN_F23R1_FB28 CAN_F23R1_FB28_Msk /*!< Filter bit 28 */ |
8702 | #define CAN_F23R1_FB29_Pos (29U) |
| 8703 | #define CAN_F23R1_FB29_Pos (29U) |
8703 | #define CAN_F23R1_FB29_Msk (0x1UL << CAN_F23R1_FB29_Pos) /*!< 0x20000000 */ |
| 8704 | #define CAN_F23R1_FB29_Msk (0x1UL << CAN_F23R1_FB29_Pos) /*!< 0x20000000 */ |
8704 | #define CAN_F23R1_FB29 CAN_F23R1_FB29_Msk /*!< Filter bit 29 */ |
| 8705 | #define CAN_F23R1_FB29 CAN_F23R1_FB29_Msk /*!< Filter bit 29 */ |
8705 | #define CAN_F23R1_FB30_Pos (30U) |
| 8706 | #define CAN_F23R1_FB30_Pos (30U) |
8706 | #define CAN_F23R1_FB30_Msk (0x1UL << CAN_F23R1_FB30_Pos) /*!< 0x40000000 */ |
| 8707 | #define CAN_F23R1_FB30_Msk (0x1UL << CAN_F23R1_FB30_Pos) /*!< 0x40000000 */ |
8707 | #define CAN_F23R1_FB30 CAN_F23R1_FB30_Msk /*!< Filter bit 30 */ |
| 8708 | #define CAN_F23R1_FB30 CAN_F23R1_FB30_Msk /*!< Filter bit 30 */ |
8708 | #define CAN_F23R1_FB31_Pos (31U) |
| 8709 | #define CAN_F23R1_FB31_Pos (31U) |
8709 | #define CAN_F23R1_FB31_Msk (0x1UL << CAN_F23R1_FB31_Pos) /*!< 0x80000000 */ |
| 8710 | #define CAN_F23R1_FB31_Msk (0x1UL << CAN_F23R1_FB31_Pos) /*!< 0x80000000 */ |
8710 | #define CAN_F23R1_FB31 CAN_F23R1_FB31_Msk /*!< Filter bit 31 */ |
| 8711 | #define CAN_F23R1_FB31 CAN_F23R1_FB31_Msk /*!< Filter bit 31 */ |
8711 | |
| 8712 | 8712 | /******************* Bit definition for CAN_F24R1 register ******************/ |
|
| 8713 | /******************* Bit definition for CAN_F24R1 register ******************/ |
8713 | #define CAN_F24R1_FB0_Pos (0U) |
| 8714 | #define CAN_F24R1_FB0_Pos (0U) |
8714 | #define CAN_F24R1_FB0_Msk (0x1UL << CAN_F24R1_FB0_Pos) /*!< 0x00000001 */ |
| 8715 | #define CAN_F24R1_FB0_Msk (0x1UL << CAN_F24R1_FB0_Pos) /*!< 0x00000001 */ |
8715 | #define CAN_F24R1_FB0 CAN_F24R1_FB0_Msk /*!< Filter bit 0 */ |
| 8716 | #define CAN_F24R1_FB0 CAN_F24R1_FB0_Msk /*!< Filter bit 0 */ |
8716 | #define CAN_F24R1_FB1_Pos (1U) |
| 8717 | #define CAN_F24R1_FB1_Pos (1U) |
8717 | #define CAN_F24R1_FB1_Msk (0x1UL << CAN_F24R1_FB1_Pos) /*!< 0x00000002 */ |
| 8718 | #define CAN_F24R1_FB1_Msk (0x1UL << CAN_F24R1_FB1_Pos) /*!< 0x00000002 */ |
8718 | #define CAN_F24R1_FB1 CAN_F24R1_FB1_Msk /*!< Filter bit 1 */ |
| 8719 | #define CAN_F24R1_FB1 CAN_F24R1_FB1_Msk /*!< Filter bit 1 */ |
8719 | #define CAN_F24R1_FB2_Pos (2U) |
| 8720 | #define CAN_F24R1_FB2_Pos (2U) |
8720 | #define CAN_F24R1_FB2_Msk (0x1UL << CAN_F24R1_FB2_Pos) /*!< 0x00000004 */ |
| 8721 | #define CAN_F24R1_FB2_Msk (0x1UL << CAN_F24R1_FB2_Pos) /*!< 0x00000004 */ |
8721 | #define CAN_F24R1_FB2 CAN_F24R1_FB2_Msk /*!< Filter bit 2 */ |
| 8722 | #define CAN_F24R1_FB2 CAN_F24R1_FB2_Msk /*!< Filter bit 2 */ |
8722 | #define CAN_F24R1_FB3_Pos (3U) |
| 8723 | #define CAN_F24R1_FB3_Pos (3U) |
8723 | #define CAN_F24R1_FB3_Msk (0x1UL << CAN_F24R1_FB3_Pos) /*!< 0x00000008 */ |
| 8724 | #define CAN_F24R1_FB3_Msk (0x1UL << CAN_F24R1_FB3_Pos) /*!< 0x00000008 */ |
8724 | #define CAN_F24R1_FB3 CAN_F24R1_FB3_Msk /*!< Filter bit 3 */ |
| 8725 | #define CAN_F24R1_FB3 CAN_F24R1_FB3_Msk /*!< Filter bit 3 */ |
8725 | #define CAN_F24R1_FB4_Pos (4U) |
| 8726 | #define CAN_F24R1_FB4_Pos (4U) |
8726 | #define CAN_F24R1_FB4_Msk (0x1UL << CAN_F24R1_FB4_Pos) /*!< 0x00000010 */ |
| 8727 | #define CAN_F24R1_FB4_Msk (0x1UL << CAN_F24R1_FB4_Pos) /*!< 0x00000010 */ |
8727 | #define CAN_F24R1_FB4 CAN_F24R1_FB4_Msk /*!< Filter bit 4 */ |
| 8728 | #define CAN_F24R1_FB4 CAN_F24R1_FB4_Msk /*!< Filter bit 4 */ |
8728 | #define CAN_F24R1_FB5_Pos (5U) |
| 8729 | #define CAN_F24R1_FB5_Pos (5U) |
8729 | #define CAN_F24R1_FB5_Msk (0x1UL << CAN_F24R1_FB5_Pos) /*!< 0x00000020 */ |
| 8730 | #define CAN_F24R1_FB5_Msk (0x1UL << CAN_F24R1_FB5_Pos) /*!< 0x00000020 */ |
8730 | #define CAN_F24R1_FB5 CAN_F24R1_FB5_Msk /*!< Filter bit 5 */ |
| 8731 | #define CAN_F24R1_FB5 CAN_F24R1_FB5_Msk /*!< Filter bit 5 */ |
8731 | #define CAN_F24R1_FB6_Pos (6U) |
| 8732 | #define CAN_F24R1_FB6_Pos (6U) |
8732 | #define CAN_F24R1_FB6_Msk (0x1UL << CAN_F24R1_FB6_Pos) /*!< 0x00000040 */ |
| 8733 | #define CAN_F24R1_FB6_Msk (0x1UL << CAN_F24R1_FB6_Pos) /*!< 0x00000040 */ |
8733 | #define CAN_F24R1_FB6 CAN_F24R1_FB6_Msk /*!< Filter bit 6 */ |
| 8734 | #define CAN_F24R1_FB6 CAN_F24R1_FB6_Msk /*!< Filter bit 6 */ |
8734 | #define CAN_F24R1_FB7_Pos (7U) |
| 8735 | #define CAN_F24R1_FB7_Pos (7U) |
8735 | #define CAN_F24R1_FB7_Msk (0x1UL << CAN_F24R1_FB7_Pos) /*!< 0x00000080 */ |
| 8736 | #define CAN_F24R1_FB7_Msk (0x1UL << CAN_F24R1_FB7_Pos) /*!< 0x00000080 */ |
8736 | #define CAN_F24R1_FB7 CAN_F24R1_FB7_Msk /*!< Filter bit 7 */ |
| 8737 | #define CAN_F24R1_FB7 CAN_F24R1_FB7_Msk /*!< Filter bit 7 */ |
8737 | #define CAN_F24R1_FB8_Pos (8U) |
| 8738 | #define CAN_F24R1_FB8_Pos (8U) |
8738 | #define CAN_F24R1_FB8_Msk (0x1UL << CAN_F24R1_FB8_Pos) /*!< 0x00000100 */ |
| 8739 | #define CAN_F24R1_FB8_Msk (0x1UL << CAN_F24R1_FB8_Pos) /*!< 0x00000100 */ |
8739 | #define CAN_F24R1_FB8 CAN_F24R1_FB8_Msk /*!< Filter bit 8 */ |
| 8740 | #define CAN_F24R1_FB8 CAN_F24R1_FB8_Msk /*!< Filter bit 8 */ |
8740 | #define CAN_F24R1_FB9_Pos (9U) |
| 8741 | #define CAN_F24R1_FB9_Pos (9U) |
8741 | #define CAN_F24R1_FB9_Msk (0x1UL << CAN_F24R1_FB9_Pos) /*!< 0x00000200 */ |
| 8742 | #define CAN_F24R1_FB9_Msk (0x1UL << CAN_F24R1_FB9_Pos) /*!< 0x00000200 */ |
8742 | #define CAN_F24R1_FB9 CAN_F24R1_FB9_Msk /*!< Filter bit 9 */ |
| 8743 | #define CAN_F24R1_FB9 CAN_F24R1_FB9_Msk /*!< Filter bit 9 */ |
8743 | #define CAN_F24R1_FB10_Pos (10U) |
| 8744 | #define CAN_F24R1_FB10_Pos (10U) |
8744 | #define CAN_F24R1_FB10_Msk (0x1UL << CAN_F24R1_FB10_Pos) /*!< 0x00000400 */ |
| 8745 | #define CAN_F24R1_FB10_Msk (0x1UL << CAN_F24R1_FB10_Pos) /*!< 0x00000400 */ |
8745 | #define CAN_F24R1_FB10 CAN_F24R1_FB10_Msk /*!< Filter bit 10 */ |
| 8746 | #define CAN_F24R1_FB10 CAN_F24R1_FB10_Msk /*!< Filter bit 10 */ |
8746 | #define CAN_F24R1_FB11_Pos (11U) |
| 8747 | #define CAN_F24R1_FB11_Pos (11U) |
8747 | #define CAN_F24R1_FB11_Msk (0x1UL << CAN_F24R1_FB11_Pos) /*!< 0x00000800 */ |
| 8748 | #define CAN_F24R1_FB11_Msk (0x1UL << CAN_F24R1_FB11_Pos) /*!< 0x00000800 */ |
8748 | #define CAN_F24R1_FB11 CAN_F24R1_FB11_Msk /*!< Filter bit 11 */ |
| 8749 | #define CAN_F24R1_FB11 CAN_F24R1_FB11_Msk /*!< Filter bit 11 */ |
8749 | #define CAN_F24R1_FB12_Pos (12U) |
| 8750 | #define CAN_F24R1_FB12_Pos (12U) |
8750 | #define CAN_F24R1_FB12_Msk (0x1UL << CAN_F24R1_FB12_Pos) /*!< 0x00001000 */ |
| 8751 | #define CAN_F24R1_FB12_Msk (0x1UL << CAN_F24R1_FB12_Pos) /*!< 0x00001000 */ |
8751 | #define CAN_F24R1_FB12 CAN_F24R1_FB12_Msk /*!< Filter bit 12 */ |
| 8752 | #define CAN_F24R1_FB12 CAN_F24R1_FB12_Msk /*!< Filter bit 12 */ |
8752 | #define CAN_F24R1_FB13_Pos (13U) |
| 8753 | #define CAN_F24R1_FB13_Pos (13U) |
8753 | #define CAN_F24R1_FB13_Msk (0x1UL << CAN_F24R1_FB13_Pos) /*!< 0x00002000 */ |
| 8754 | #define CAN_F24R1_FB13_Msk (0x1UL << CAN_F24R1_FB13_Pos) /*!< 0x00002000 */ |
8754 | #define CAN_F24R1_FB13 CAN_F24R1_FB13_Msk /*!< Filter bit 13 */ |
| 8755 | #define CAN_F24R1_FB13 CAN_F24R1_FB13_Msk /*!< Filter bit 13 */ |
8755 | #define CAN_F24R1_FB14_Pos (14U) |
| 8756 | #define CAN_F24R1_FB14_Pos (14U) |
8756 | #define CAN_F24R1_FB14_Msk (0x1UL << CAN_F24R1_FB14_Pos) /*!< 0x00004000 */ |
| 8757 | #define CAN_F24R1_FB14_Msk (0x1UL << CAN_F24R1_FB14_Pos) /*!< 0x00004000 */ |
8757 | #define CAN_F24R1_FB14 CAN_F24R1_FB14_Msk /*!< Filter bit 14 */ |
| 8758 | #define CAN_F24R1_FB14 CAN_F24R1_FB14_Msk /*!< Filter bit 14 */ |
8758 | #define CAN_F24R1_FB15_Pos (15U) |
| 8759 | #define CAN_F24R1_FB15_Pos (15U) |
8759 | #define CAN_F24R1_FB15_Msk (0x1UL << CAN_F24R1_FB15_Pos) /*!< 0x00008000 */ |
| 8760 | #define CAN_F24R1_FB15_Msk (0x1UL << CAN_F24R1_FB15_Pos) /*!< 0x00008000 */ |
8760 | #define CAN_F24R1_FB15 CAN_F24R1_FB15_Msk /*!< Filter bit 15 */ |
| 8761 | #define CAN_F24R1_FB15 CAN_F24R1_FB15_Msk /*!< Filter bit 15 */ |
8761 | #define CAN_F24R1_FB16_Pos (16U) |
| 8762 | #define CAN_F24R1_FB16_Pos (16U) |
8762 | #define CAN_F24R1_FB16_Msk (0x1UL << CAN_F24R1_FB16_Pos) /*!< 0x00010000 */ |
| 8763 | #define CAN_F24R1_FB16_Msk (0x1UL << CAN_F24R1_FB16_Pos) /*!< 0x00010000 */ |
8763 | #define CAN_F24R1_FB16 CAN_F24R1_FB16_Msk /*!< Filter bit 16 */ |
| 8764 | #define CAN_F24R1_FB16 CAN_F24R1_FB16_Msk /*!< Filter bit 16 */ |
8764 | #define CAN_F24R1_FB17_Pos (17U) |
| 8765 | #define CAN_F24R1_FB17_Pos (17U) |
8765 | #define CAN_F24R1_FB17_Msk (0x1UL << CAN_F24R1_FB17_Pos) /*!< 0x00020000 */ |
| 8766 | #define CAN_F24R1_FB17_Msk (0x1UL << CAN_F24R1_FB17_Pos) /*!< 0x00020000 */ |
8766 | #define CAN_F24R1_FB17 CAN_F24R1_FB17_Msk /*!< Filter bit 17 */ |
| 8767 | #define CAN_F24R1_FB17 CAN_F24R1_FB17_Msk /*!< Filter bit 17 */ |
8767 | #define CAN_F24R1_FB18_Pos (18U) |
| 8768 | #define CAN_F24R1_FB18_Pos (18U) |
8768 | #define CAN_F24R1_FB18_Msk (0x1UL << CAN_F24R1_FB18_Pos) /*!< 0x00040000 */ |
| 8769 | #define CAN_F24R1_FB18_Msk (0x1UL << CAN_F24R1_FB18_Pos) /*!< 0x00040000 */ |
8769 | #define CAN_F24R1_FB18 CAN_F24R1_FB18_Msk /*!< Filter bit 18 */ |
| 8770 | #define CAN_F24R1_FB18 CAN_F24R1_FB18_Msk /*!< Filter bit 18 */ |
8770 | #define CAN_F24R1_FB19_Pos (19U) |
| 8771 | #define CAN_F24R1_FB19_Pos (19U) |
8771 | #define CAN_F24R1_FB19_Msk (0x1UL << CAN_F24R1_FB19_Pos) /*!< 0x00080000 */ |
| 8772 | #define CAN_F24R1_FB19_Msk (0x1UL << CAN_F24R1_FB19_Pos) /*!< 0x00080000 */ |
8772 | #define CAN_F24R1_FB19 CAN_F24R1_FB19_Msk /*!< Filter bit 19 */ |
| 8773 | #define CAN_F24R1_FB19 CAN_F24R1_FB19_Msk /*!< Filter bit 19 */ |
8773 | #define CAN_F24R1_FB20_Pos (20U) |
| 8774 | #define CAN_F24R1_FB20_Pos (20U) |
8774 | #define CAN_F24R1_FB20_Msk (0x1UL << CAN_F24R1_FB20_Pos) /*!< 0x00100000 */ |
| 8775 | #define CAN_F24R1_FB20_Msk (0x1UL << CAN_F24R1_FB20_Pos) /*!< 0x00100000 */ |
8775 | #define CAN_F24R1_FB20 CAN_F24R1_FB20_Msk /*!< Filter bit 20 */ |
| 8776 | #define CAN_F24R1_FB20 CAN_F24R1_FB20_Msk /*!< Filter bit 20 */ |
8776 | #define CAN_F24R1_FB21_Pos (21U) |
| 8777 | #define CAN_F24R1_FB21_Pos (21U) |
8777 | #define CAN_F24R1_FB21_Msk (0x1UL << CAN_F24R1_FB21_Pos) /*!< 0x00200000 */ |
| 8778 | #define CAN_F24R1_FB21_Msk (0x1UL << CAN_F24R1_FB21_Pos) /*!< 0x00200000 */ |
8778 | #define CAN_F24R1_FB21 CAN_F24R1_FB21_Msk /*!< Filter bit 21 */ |
| 8779 | #define CAN_F24R1_FB21 CAN_F24R1_FB21_Msk /*!< Filter bit 21 */ |
8779 | #define CAN_F24R1_FB22_Pos (22U) |
| 8780 | #define CAN_F24R1_FB22_Pos (22U) |
8780 | #define CAN_F24R1_FB22_Msk (0x1UL << CAN_F24R1_FB22_Pos) /*!< 0x00400000 */ |
| 8781 | #define CAN_F24R1_FB22_Msk (0x1UL << CAN_F24R1_FB22_Pos) /*!< 0x00400000 */ |
8781 | #define CAN_F24R1_FB22 CAN_F24R1_FB22_Msk /*!< Filter bit 22 */ |
| 8782 | #define CAN_F24R1_FB22 CAN_F24R1_FB22_Msk /*!< Filter bit 22 */ |
8782 | #define CAN_F24R1_FB23_Pos (23U) |
| 8783 | #define CAN_F24R1_FB23_Pos (23U) |
8783 | #define CAN_F24R1_FB23_Msk (0x1UL << CAN_F24R1_FB23_Pos) /*!< 0x00800000 */ |
| 8784 | #define CAN_F24R1_FB23_Msk (0x1UL << CAN_F24R1_FB23_Pos) /*!< 0x00800000 */ |
8784 | #define CAN_F24R1_FB23 CAN_F24R1_FB23_Msk /*!< Filter bit 23 */ |
| 8785 | #define CAN_F24R1_FB23 CAN_F24R1_FB23_Msk /*!< Filter bit 23 */ |
8785 | #define CAN_F24R1_FB24_Pos (24U) |
| 8786 | #define CAN_F24R1_FB24_Pos (24U) |
8786 | #define CAN_F24R1_FB24_Msk (0x1UL << CAN_F24R1_FB24_Pos) /*!< 0x01000000 */ |
| 8787 | #define CAN_F24R1_FB24_Msk (0x1UL << CAN_F24R1_FB24_Pos) /*!< 0x01000000 */ |
8787 | #define CAN_F24R1_FB24 CAN_F24R1_FB24_Msk /*!< Filter bit 24 */ |
| 8788 | #define CAN_F24R1_FB24 CAN_F24R1_FB24_Msk /*!< Filter bit 24 */ |
8788 | #define CAN_F24R1_FB25_Pos (25U) |
| 8789 | #define CAN_F24R1_FB25_Pos (25U) |
8789 | #define CAN_F24R1_FB25_Msk (0x1UL << CAN_F24R1_FB25_Pos) /*!< 0x02000000 */ |
| 8790 | #define CAN_F24R1_FB25_Msk (0x1UL << CAN_F24R1_FB25_Pos) /*!< 0x02000000 */ |
8790 | #define CAN_F24R1_FB25 CAN_F24R1_FB25_Msk /*!< Filter bit 25 */ |
| 8791 | #define CAN_F24R1_FB25 CAN_F24R1_FB25_Msk /*!< Filter bit 25 */ |
8791 | #define CAN_F24R1_FB26_Pos (26U) |
| 8792 | #define CAN_F24R1_FB26_Pos (26U) |
8792 | #define CAN_F24R1_FB26_Msk (0x1UL << CAN_F24R1_FB26_Pos) /*!< 0x04000000 */ |
| 8793 | #define CAN_F24R1_FB26_Msk (0x1UL << CAN_F24R1_FB26_Pos) /*!< 0x04000000 */ |
8793 | #define CAN_F24R1_FB26 CAN_F24R1_FB26_Msk /*!< Filter bit 26 */ |
| 8794 | #define CAN_F24R1_FB26 CAN_F24R1_FB26_Msk /*!< Filter bit 26 */ |
8794 | #define CAN_F24R1_FB27_Pos (27U) |
| 8795 | #define CAN_F24R1_FB27_Pos (27U) |
8795 | #define CAN_F24R1_FB27_Msk (0x1UL << CAN_F24R1_FB27_Pos) /*!< 0x08000000 */ |
| 8796 | #define CAN_F24R1_FB27_Msk (0x1UL << CAN_F24R1_FB27_Pos) /*!< 0x08000000 */ |
8796 | #define CAN_F24R1_FB27 CAN_F24R1_FB27_Msk /*!< Filter bit 27 */ |
| 8797 | #define CAN_F24R1_FB27 CAN_F24R1_FB27_Msk /*!< Filter bit 27 */ |
8797 | #define CAN_F24R1_FB28_Pos (28U) |
| 8798 | #define CAN_F24R1_FB28_Pos (28U) |
8798 | #define CAN_F24R1_FB28_Msk (0x1UL << CAN_F24R1_FB28_Pos) /*!< 0x10000000 */ |
| 8799 | #define CAN_F24R1_FB28_Msk (0x1UL << CAN_F24R1_FB28_Pos) /*!< 0x10000000 */ |
8799 | #define CAN_F24R1_FB28 CAN_F24R1_FB28_Msk /*!< Filter bit 28 */ |
| 8800 | #define CAN_F24R1_FB28 CAN_F24R1_FB28_Msk /*!< Filter bit 28 */ |
8800 | #define CAN_F24R1_FB29_Pos (29U) |
| 8801 | #define CAN_F24R1_FB29_Pos (29U) |
8801 | #define CAN_F24R1_FB29_Msk (0x1UL << CAN_F24R1_FB29_Pos) /*!< 0x20000000 */ |
| 8802 | #define CAN_F24R1_FB29_Msk (0x1UL << CAN_F24R1_FB29_Pos) /*!< 0x20000000 */ |
8802 | #define CAN_F24R1_FB29 CAN_F24R1_FB29_Msk /*!< Filter bit 29 */ |
| 8803 | #define CAN_F24R1_FB29 CAN_F24R1_FB29_Msk /*!< Filter bit 29 */ |
8803 | #define CAN_F24R1_FB30_Pos (30U) |
| 8804 | #define CAN_F24R1_FB30_Pos (30U) |
8804 | #define CAN_F24R1_FB30_Msk (0x1UL << CAN_F24R1_FB30_Pos) /*!< 0x40000000 */ |
| 8805 | #define CAN_F24R1_FB30_Msk (0x1UL << CAN_F24R1_FB30_Pos) /*!< 0x40000000 */ |
8805 | #define CAN_F24R1_FB30 CAN_F24R1_FB30_Msk /*!< Filter bit 30 */ |
| 8806 | #define CAN_F24R1_FB30 CAN_F24R1_FB30_Msk /*!< Filter bit 30 */ |
8806 | #define CAN_F24R1_FB31_Pos (31U) |
| 8807 | #define CAN_F24R1_FB31_Pos (31U) |
8807 | #define CAN_F24R1_FB31_Msk (0x1UL << CAN_F24R1_FB31_Pos) /*!< 0x80000000 */ |
| 8808 | #define CAN_F24R1_FB31_Msk (0x1UL << CAN_F24R1_FB31_Pos) /*!< 0x80000000 */ |
8808 | #define CAN_F24R1_FB31 CAN_F24R1_FB31_Msk /*!< Filter bit 31 */ |
| 8809 | #define CAN_F24R1_FB31 CAN_F24R1_FB31_Msk /*!< Filter bit 31 */ |
8809 | |
| 8810 | 8810 | /******************* Bit definition for CAN_F25R1 register ******************/ |
|
| 8811 | /******************* Bit definition for CAN_F25R1 register ******************/ |
8811 | #define CAN_F25R1_FB0_Pos (0U) |
| 8812 | #define CAN_F25R1_FB0_Pos (0U) |
8812 | #define CAN_F25R1_FB0_Msk (0x1UL << CAN_F25R1_FB0_Pos) /*!< 0x00000001 */ |
| 8813 | #define CAN_F25R1_FB0_Msk (0x1UL << CAN_F25R1_FB0_Pos) /*!< 0x00000001 */ |
8813 | #define CAN_F25R1_FB0 CAN_F25R1_FB0_Msk /*!< Filter bit 0 */ |
| 8814 | #define CAN_F25R1_FB0 CAN_F25R1_FB0_Msk /*!< Filter bit 0 */ |
8814 | #define CAN_F25R1_FB1_Pos (1U) |
| 8815 | #define CAN_F25R1_FB1_Pos (1U) |
8815 | #define CAN_F25R1_FB1_Msk (0x1UL << CAN_F25R1_FB1_Pos) /*!< 0x00000002 */ |
| 8816 | #define CAN_F25R1_FB1_Msk (0x1UL << CAN_F25R1_FB1_Pos) /*!< 0x00000002 */ |
8816 | #define CAN_F25R1_FB1 CAN_F25R1_FB1_Msk /*!< Filter bit 1 */ |
| 8817 | #define CAN_F25R1_FB1 CAN_F25R1_FB1_Msk /*!< Filter bit 1 */ |
8817 | #define CAN_F25R1_FB2_Pos (2U) |
| 8818 | #define CAN_F25R1_FB2_Pos (2U) |
8818 | #define CAN_F25R1_FB2_Msk (0x1UL << CAN_F25R1_FB2_Pos) /*!< 0x00000004 */ |
| 8819 | #define CAN_F25R1_FB2_Msk (0x1UL << CAN_F25R1_FB2_Pos) /*!< 0x00000004 */ |
8819 | #define CAN_F25R1_FB2 CAN_F25R1_FB2_Msk /*!< Filter bit 2 */ |
| 8820 | #define CAN_F25R1_FB2 CAN_F25R1_FB2_Msk /*!< Filter bit 2 */ |
8820 | #define CAN_F25R1_FB3_Pos (3U) |
| 8821 | #define CAN_F25R1_FB3_Pos (3U) |
8821 | #define CAN_F25R1_FB3_Msk (0x1UL << CAN_F25R1_FB3_Pos) /*!< 0x00000008 */ |
| 8822 | #define CAN_F25R1_FB3_Msk (0x1UL << CAN_F25R1_FB3_Pos) /*!< 0x00000008 */ |
8822 | #define CAN_F25R1_FB3 CAN_F25R1_FB3_Msk /*!< Filter bit 3 */ |
| 8823 | #define CAN_F25R1_FB3 CAN_F25R1_FB3_Msk /*!< Filter bit 3 */ |
8823 | #define CAN_F25R1_FB4_Pos (4U) |
| 8824 | #define CAN_F25R1_FB4_Pos (4U) |
8824 | #define CAN_F25R1_FB4_Msk (0x1UL << CAN_F25R1_FB4_Pos) /*!< 0x00000010 */ |
| 8825 | #define CAN_F25R1_FB4_Msk (0x1UL << CAN_F25R1_FB4_Pos) /*!< 0x00000010 */ |
8825 | #define CAN_F25R1_FB4 CAN_F25R1_FB4_Msk /*!< Filter bit 4 */ |
| 8826 | #define CAN_F25R1_FB4 CAN_F25R1_FB4_Msk /*!< Filter bit 4 */ |
8826 | #define CAN_F25R1_FB5_Pos (5U) |
| 8827 | #define CAN_F25R1_FB5_Pos (5U) |
8827 | #define CAN_F25R1_FB5_Msk (0x1UL << CAN_F25R1_FB5_Pos) /*!< 0x00000020 */ |
| 8828 | #define CAN_F25R1_FB5_Msk (0x1UL << CAN_F25R1_FB5_Pos) /*!< 0x00000020 */ |
8828 | #define CAN_F25R1_FB5 CAN_F25R1_FB5_Msk /*!< Filter bit 5 */ |
| 8829 | #define CAN_F25R1_FB5 CAN_F25R1_FB5_Msk /*!< Filter bit 5 */ |
8829 | #define CAN_F25R1_FB6_Pos (6U) |
| 8830 | #define CAN_F25R1_FB6_Pos (6U) |
8830 | #define CAN_F25R1_FB6_Msk (0x1UL << CAN_F25R1_FB6_Pos) /*!< 0x00000040 */ |
| 8831 | #define CAN_F25R1_FB6_Msk (0x1UL << CAN_F25R1_FB6_Pos) /*!< 0x00000040 */ |
8831 | #define CAN_F25R1_FB6 CAN_F25R1_FB6_Msk /*!< Filter bit 6 */ |
| 8832 | #define CAN_F25R1_FB6 CAN_F25R1_FB6_Msk /*!< Filter bit 6 */ |
8832 | #define CAN_F25R1_FB7_Pos (7U) |
| 8833 | #define CAN_F25R1_FB7_Pos (7U) |
8833 | #define CAN_F25R1_FB7_Msk (0x1UL << CAN_F25R1_FB7_Pos) /*!< 0x00000080 */ |
| 8834 | #define CAN_F25R1_FB7_Msk (0x1UL << CAN_F25R1_FB7_Pos) /*!< 0x00000080 */ |
8834 | #define CAN_F25R1_FB7 CAN_F25R1_FB7_Msk /*!< Filter bit 7 */ |
| 8835 | #define CAN_F25R1_FB7 CAN_F25R1_FB7_Msk /*!< Filter bit 7 */ |
8835 | #define CAN_F25R1_FB8_Pos (8U) |
| 8836 | #define CAN_F25R1_FB8_Pos (8U) |
8836 | #define CAN_F25R1_FB8_Msk (0x1UL << CAN_F25R1_FB8_Pos) /*!< 0x00000100 */ |
| 8837 | #define CAN_F25R1_FB8_Msk (0x1UL << CAN_F25R1_FB8_Pos) /*!< 0x00000100 */ |
8837 | #define CAN_F25R1_FB8 CAN_F25R1_FB8_Msk /*!< Filter bit 8 */ |
| 8838 | #define CAN_F25R1_FB8 CAN_F25R1_FB8_Msk /*!< Filter bit 8 */ |
8838 | #define CAN_F25R1_FB9_Pos (9U) |
| 8839 | #define CAN_F25R1_FB9_Pos (9U) |
8839 | #define CAN_F25R1_FB9_Msk (0x1UL << CAN_F25R1_FB9_Pos) /*!< 0x00000200 */ |
| 8840 | #define CAN_F25R1_FB9_Msk (0x1UL << CAN_F25R1_FB9_Pos) /*!< 0x00000200 */ |
8840 | #define CAN_F25R1_FB9 CAN_F25R1_FB9_Msk /*!< Filter bit 9 */ |
| 8841 | #define CAN_F25R1_FB9 CAN_F25R1_FB9_Msk /*!< Filter bit 9 */ |
8841 | #define CAN_F25R1_FB10_Pos (10U) |
| 8842 | #define CAN_F25R1_FB10_Pos (10U) |
8842 | #define CAN_F25R1_FB10_Msk (0x1UL << CAN_F25R1_FB10_Pos) /*!< 0x00000400 */ |
| 8843 | #define CAN_F25R1_FB10_Msk (0x1UL << CAN_F25R1_FB10_Pos) /*!< 0x00000400 */ |
8843 | #define CAN_F25R1_FB10 CAN_F25R1_FB10_Msk /*!< Filter bit 10 */ |
| 8844 | #define CAN_F25R1_FB10 CAN_F25R1_FB10_Msk /*!< Filter bit 10 */ |
8844 | #define CAN_F25R1_FB11_Pos (11U) |
| 8845 | #define CAN_F25R1_FB11_Pos (11U) |
8845 | #define CAN_F25R1_FB11_Msk (0x1UL << CAN_F25R1_FB11_Pos) /*!< 0x00000800 */ |
| 8846 | #define CAN_F25R1_FB11_Msk (0x1UL << CAN_F25R1_FB11_Pos) /*!< 0x00000800 */ |
8846 | #define CAN_F25R1_FB11 CAN_F25R1_FB11_Msk /*!< Filter bit 11 */ |
| 8847 | #define CAN_F25R1_FB11 CAN_F25R1_FB11_Msk /*!< Filter bit 11 */ |
8847 | #define CAN_F25R1_FB12_Pos (12U) |
| 8848 | #define CAN_F25R1_FB12_Pos (12U) |
8848 | #define CAN_F25R1_FB12_Msk (0x1UL << CAN_F25R1_FB12_Pos) /*!< 0x00001000 */ |
| 8849 | #define CAN_F25R1_FB12_Msk (0x1UL << CAN_F25R1_FB12_Pos) /*!< 0x00001000 */ |
8849 | #define CAN_F25R1_FB12 CAN_F25R1_FB12_Msk /*!< Filter bit 12 */ |
| 8850 | #define CAN_F25R1_FB12 CAN_F25R1_FB12_Msk /*!< Filter bit 12 */ |
8850 | #define CAN_F25R1_FB13_Pos (13U) |
| 8851 | #define CAN_F25R1_FB13_Pos (13U) |
8851 | #define CAN_F25R1_FB13_Msk (0x1UL << CAN_F25R1_FB13_Pos) /*!< 0x00002000 */ |
| 8852 | #define CAN_F25R1_FB13_Msk (0x1UL << CAN_F25R1_FB13_Pos) /*!< 0x00002000 */ |
8852 | #define CAN_F25R1_FB13 CAN_F25R1_FB13_Msk /*!< Filter bit 13 */ |
| 8853 | #define CAN_F25R1_FB13 CAN_F25R1_FB13_Msk /*!< Filter bit 13 */ |
8853 | #define CAN_F25R1_FB14_Pos (14U) |
| 8854 | #define CAN_F25R1_FB14_Pos (14U) |
8854 | #define CAN_F25R1_FB14_Msk (0x1UL << CAN_F25R1_FB14_Pos) /*!< 0x00004000 */ |
| 8855 | #define CAN_F25R1_FB14_Msk (0x1UL << CAN_F25R1_FB14_Pos) /*!< 0x00004000 */ |
8855 | #define CAN_F25R1_FB14 CAN_F25R1_FB14_Msk /*!< Filter bit 14 */ |
| 8856 | #define CAN_F25R1_FB14 CAN_F25R1_FB14_Msk /*!< Filter bit 14 */ |
8856 | #define CAN_F25R1_FB15_Pos (15U) |
| 8857 | #define CAN_F25R1_FB15_Pos (15U) |
8857 | #define CAN_F25R1_FB15_Msk (0x1UL << CAN_F25R1_FB15_Pos) /*!< 0x00008000 */ |
| 8858 | #define CAN_F25R1_FB15_Msk (0x1UL << CAN_F25R1_FB15_Pos) /*!< 0x00008000 */ |
8858 | #define CAN_F25R1_FB15 CAN_F25R1_FB15_Msk /*!< Filter bit 15 */ |
| 8859 | #define CAN_F25R1_FB15 CAN_F25R1_FB15_Msk /*!< Filter bit 15 */ |
8859 | #define CAN_F25R1_FB16_Pos (16U) |
| 8860 | #define CAN_F25R1_FB16_Pos (16U) |
8860 | #define CAN_F25R1_FB16_Msk (0x1UL << CAN_F25R1_FB16_Pos) /*!< 0x00010000 */ |
| 8861 | #define CAN_F25R1_FB16_Msk (0x1UL << CAN_F25R1_FB16_Pos) /*!< 0x00010000 */ |
8861 | #define CAN_F25R1_FB16 CAN_F25R1_FB16_Msk /*!< Filter bit 16 */ |
| 8862 | #define CAN_F25R1_FB16 CAN_F25R1_FB16_Msk /*!< Filter bit 16 */ |
8862 | #define CAN_F25R1_FB17_Pos (17U) |
| 8863 | #define CAN_F25R1_FB17_Pos (17U) |
8863 | #define CAN_F25R1_FB17_Msk (0x1UL << CAN_F25R1_FB17_Pos) /*!< 0x00020000 */ |
| 8864 | #define CAN_F25R1_FB17_Msk (0x1UL << CAN_F25R1_FB17_Pos) /*!< 0x00020000 */ |
8864 | #define CAN_F25R1_FB17 CAN_F25R1_FB17_Msk /*!< Filter bit 17 */ |
| 8865 | #define CAN_F25R1_FB17 CAN_F25R1_FB17_Msk /*!< Filter bit 17 */ |
8865 | #define CAN_F25R1_FB18_Pos (18U) |
| 8866 | #define CAN_F25R1_FB18_Pos (18U) |
8866 | #define CAN_F25R1_FB18_Msk (0x1UL << CAN_F25R1_FB18_Pos) /*!< 0x00040000 */ |
| 8867 | #define CAN_F25R1_FB18_Msk (0x1UL << CAN_F25R1_FB18_Pos) /*!< 0x00040000 */ |
8867 | #define CAN_F25R1_FB18 CAN_F25R1_FB18_Msk /*!< Filter bit 18 */ |
| 8868 | #define CAN_F25R1_FB18 CAN_F25R1_FB18_Msk /*!< Filter bit 18 */ |
8868 | #define CAN_F25R1_FB19_Pos (19U) |
| 8869 | #define CAN_F25R1_FB19_Pos (19U) |
8869 | #define CAN_F25R1_FB19_Msk (0x1UL << CAN_F25R1_FB19_Pos) /*!< 0x00080000 */ |
| 8870 | #define CAN_F25R1_FB19_Msk (0x1UL << CAN_F25R1_FB19_Pos) /*!< 0x00080000 */ |
8870 | #define CAN_F25R1_FB19 CAN_F25R1_FB19_Msk /*!< Filter bit 19 */ |
| 8871 | #define CAN_F25R1_FB19 CAN_F25R1_FB19_Msk /*!< Filter bit 19 */ |
8871 | #define CAN_F25R1_FB20_Pos (20U) |
| 8872 | #define CAN_F25R1_FB20_Pos (20U) |
8872 | #define CAN_F25R1_FB20_Msk (0x1UL << CAN_F25R1_FB20_Pos) /*!< 0x00100000 */ |
| 8873 | #define CAN_F25R1_FB20_Msk (0x1UL << CAN_F25R1_FB20_Pos) /*!< 0x00100000 */ |
8873 | #define CAN_F25R1_FB20 CAN_F25R1_FB20_Msk /*!< Filter bit 20 */ |
| 8874 | #define CAN_F25R1_FB20 CAN_F25R1_FB20_Msk /*!< Filter bit 20 */ |
8874 | #define CAN_F25R1_FB21_Pos (21U) |
| 8875 | #define CAN_F25R1_FB21_Pos (21U) |
8875 | #define CAN_F25R1_FB21_Msk (0x1UL << CAN_F25R1_FB21_Pos) /*!< 0x00200000 */ |
| 8876 | #define CAN_F25R1_FB21_Msk (0x1UL << CAN_F25R1_FB21_Pos) /*!< 0x00200000 */ |
8876 | #define CAN_F25R1_FB21 CAN_F25R1_FB21_Msk /*!< Filter bit 21 */ |
| 8877 | #define CAN_F25R1_FB21 CAN_F25R1_FB21_Msk /*!< Filter bit 21 */ |
8877 | #define CAN_F25R1_FB22_Pos (22U) |
| 8878 | #define CAN_F25R1_FB22_Pos (22U) |
8878 | #define CAN_F25R1_FB22_Msk (0x1UL << CAN_F25R1_FB22_Pos) /*!< 0x00400000 */ |
| 8879 | #define CAN_F25R1_FB22_Msk (0x1UL << CAN_F25R1_FB22_Pos) /*!< 0x00400000 */ |
8879 | #define CAN_F25R1_FB22 CAN_F25R1_FB22_Msk /*!< Filter bit 22 */ |
| 8880 | #define CAN_F25R1_FB22 CAN_F25R1_FB22_Msk /*!< Filter bit 22 */ |
8880 | #define CAN_F25R1_FB23_Pos (23U) |
| 8881 | #define CAN_F25R1_FB23_Pos (23U) |
8881 | #define CAN_F25R1_FB23_Msk (0x1UL << CAN_F25R1_FB23_Pos) /*!< 0x00800000 */ |
| 8882 | #define CAN_F25R1_FB23_Msk (0x1UL << CAN_F25R1_FB23_Pos) /*!< 0x00800000 */ |
8882 | #define CAN_F25R1_FB23 CAN_F25R1_FB23_Msk /*!< Filter bit 23 */ |
| 8883 | #define CAN_F25R1_FB23 CAN_F25R1_FB23_Msk /*!< Filter bit 23 */ |
8883 | #define CAN_F25R1_FB24_Pos (24U) |
| 8884 | #define CAN_F25R1_FB24_Pos (24U) |
8884 | #define CAN_F25R1_FB24_Msk (0x1UL << CAN_F25R1_FB24_Pos) /*!< 0x01000000 */ |
| 8885 | #define CAN_F25R1_FB24_Msk (0x1UL << CAN_F25R1_FB24_Pos) /*!< 0x01000000 */ |
8885 | #define CAN_F25R1_FB24 CAN_F25R1_FB24_Msk /*!< Filter bit 24 */ |
| 8886 | #define CAN_F25R1_FB24 CAN_F25R1_FB24_Msk /*!< Filter bit 24 */ |
8886 | #define CAN_F25R1_FB25_Pos (25U) |
| 8887 | #define CAN_F25R1_FB25_Pos (25U) |
8887 | #define CAN_F25R1_FB25_Msk (0x1UL << CAN_F25R1_FB25_Pos) /*!< 0x02000000 */ |
| 8888 | #define CAN_F25R1_FB25_Msk (0x1UL << CAN_F25R1_FB25_Pos) /*!< 0x02000000 */ |
8888 | #define CAN_F25R1_FB25 CAN_F25R1_FB25_Msk /*!< Filter bit 25 */ |
| 8889 | #define CAN_F25R1_FB25 CAN_F25R1_FB25_Msk /*!< Filter bit 25 */ |
8889 | #define CAN_F25R1_FB26_Pos (26U) |
| 8890 | #define CAN_F25R1_FB26_Pos (26U) |
8890 | #define CAN_F25R1_FB26_Msk (0x1UL << CAN_F25R1_FB26_Pos) /*!< 0x04000000 */ |
| 8891 | #define CAN_F25R1_FB26_Msk (0x1UL << CAN_F25R1_FB26_Pos) /*!< 0x04000000 */ |
8891 | #define CAN_F25R1_FB26 CAN_F25R1_FB26_Msk /*!< Filter bit 26 */ |
| 8892 | #define CAN_F25R1_FB26 CAN_F25R1_FB26_Msk /*!< Filter bit 26 */ |
8892 | #define CAN_F25R1_FB27_Pos (27U) |
| 8893 | #define CAN_F25R1_FB27_Pos (27U) |
8893 | #define CAN_F25R1_FB27_Msk (0x1UL << CAN_F25R1_FB27_Pos) /*!< 0x08000000 */ |
| 8894 | #define CAN_F25R1_FB27_Msk (0x1UL << CAN_F25R1_FB27_Pos) /*!< 0x08000000 */ |
8894 | #define CAN_F25R1_FB27 CAN_F25R1_FB27_Msk /*!< Filter bit 27 */ |
| 8895 | #define CAN_F25R1_FB27 CAN_F25R1_FB27_Msk /*!< Filter bit 27 */ |
8895 | #define CAN_F25R1_FB28_Pos (28U) |
| 8896 | #define CAN_F25R1_FB28_Pos (28U) |
8896 | #define CAN_F25R1_FB28_Msk (0x1UL << CAN_F25R1_FB28_Pos) /*!< 0x10000000 */ |
| 8897 | #define CAN_F25R1_FB28_Msk (0x1UL << CAN_F25R1_FB28_Pos) /*!< 0x10000000 */ |
8897 | #define CAN_F25R1_FB28 CAN_F25R1_FB28_Msk /*!< Filter bit 28 */ |
| 8898 | #define CAN_F25R1_FB28 CAN_F25R1_FB28_Msk /*!< Filter bit 28 */ |
8898 | #define CAN_F25R1_FB29_Pos (29U) |
| 8899 | #define CAN_F25R1_FB29_Pos (29U) |
8899 | #define CAN_F25R1_FB29_Msk (0x1UL << CAN_F25R1_FB29_Pos) /*!< 0x20000000 */ |
| 8900 | #define CAN_F25R1_FB29_Msk (0x1UL << CAN_F25R1_FB29_Pos) /*!< 0x20000000 */ |
8900 | #define CAN_F25R1_FB29 CAN_F25R1_FB29_Msk /*!< Filter bit 29 */ |
| 8901 | #define CAN_F25R1_FB29 CAN_F25R1_FB29_Msk /*!< Filter bit 29 */ |
8901 | #define CAN_F25R1_FB30_Pos (30U) |
| 8902 | #define CAN_F25R1_FB30_Pos (30U) |
8902 | #define CAN_F25R1_FB30_Msk (0x1UL << CAN_F25R1_FB30_Pos) /*!< 0x40000000 */ |
| 8903 | #define CAN_F25R1_FB30_Msk (0x1UL << CAN_F25R1_FB30_Pos) /*!< 0x40000000 */ |
8903 | #define CAN_F25R1_FB30 CAN_F25R1_FB30_Msk /*!< Filter bit 30 */ |
| 8904 | #define CAN_F25R1_FB30 CAN_F25R1_FB30_Msk /*!< Filter bit 30 */ |
8904 | #define CAN_F25R1_FB31_Pos (31U) |
| 8905 | #define CAN_F25R1_FB31_Pos (31U) |
8905 | #define CAN_F25R1_FB31_Msk (0x1UL << CAN_F25R1_FB31_Pos) /*!< 0x80000000 */ |
| 8906 | #define CAN_F25R1_FB31_Msk (0x1UL << CAN_F25R1_FB31_Pos) /*!< 0x80000000 */ |
8906 | #define CAN_F25R1_FB31 CAN_F25R1_FB31_Msk /*!< Filter bit 31 */ |
| 8907 | #define CAN_F25R1_FB31 CAN_F25R1_FB31_Msk /*!< Filter bit 31 */ |
8907 | |
| 8908 | 8908 | /******************* Bit definition for CAN_F26R1 register ******************/ |
|
| 8909 | /******************* Bit definition for CAN_F26R1 register ******************/ |
8909 | #define CAN_F26R1_FB0_Pos (0U) |
| 8910 | #define CAN_F26R1_FB0_Pos (0U) |
8910 | #define CAN_F26R1_FB0_Msk (0x1UL << CAN_F26R1_FB0_Pos) /*!< 0x00000001 */ |
| 8911 | #define CAN_F26R1_FB0_Msk (0x1UL << CAN_F26R1_FB0_Pos) /*!< 0x00000001 */ |
8911 | #define CAN_F26R1_FB0 CAN_F26R1_FB0_Msk /*!< Filter bit 0 */ |
| 8912 | #define CAN_F26R1_FB0 CAN_F26R1_FB0_Msk /*!< Filter bit 0 */ |
8912 | #define CAN_F26R1_FB1_Pos (1U) |
| 8913 | #define CAN_F26R1_FB1_Pos (1U) |
8913 | #define CAN_F26R1_FB1_Msk (0x1UL << CAN_F26R1_FB1_Pos) /*!< 0x00000002 */ |
| 8914 | #define CAN_F26R1_FB1_Msk (0x1UL << CAN_F26R1_FB1_Pos) /*!< 0x00000002 */ |
8914 | #define CAN_F26R1_FB1 CAN_F26R1_FB1_Msk /*!< Filter bit 1 */ |
| 8915 | #define CAN_F26R1_FB1 CAN_F26R1_FB1_Msk /*!< Filter bit 1 */ |
8915 | #define CAN_F26R1_FB2_Pos (2U) |
| 8916 | #define CAN_F26R1_FB2_Pos (2U) |
8916 | #define CAN_F26R1_FB2_Msk (0x1UL << CAN_F26R1_FB2_Pos) /*!< 0x00000004 */ |
| 8917 | #define CAN_F26R1_FB2_Msk (0x1UL << CAN_F26R1_FB2_Pos) /*!< 0x00000004 */ |
8917 | #define CAN_F26R1_FB2 CAN_F26R1_FB2_Msk /*!< Filter bit 2 */ |
| 8918 | #define CAN_F26R1_FB2 CAN_F26R1_FB2_Msk /*!< Filter bit 2 */ |
8918 | #define CAN_F26R1_FB3_Pos (3U) |
| 8919 | #define CAN_F26R1_FB3_Pos (3U) |
8919 | #define CAN_F26R1_FB3_Msk (0x1UL << CAN_F26R1_FB3_Pos) /*!< 0x00000008 */ |
| 8920 | #define CAN_F26R1_FB3_Msk (0x1UL << CAN_F26R1_FB3_Pos) /*!< 0x00000008 */ |
8920 | #define CAN_F26R1_FB3 CAN_F26R1_FB3_Msk /*!< Filter bit 3 */ |
| 8921 | #define CAN_F26R1_FB3 CAN_F26R1_FB3_Msk /*!< Filter bit 3 */ |
8921 | #define CAN_F26R1_FB4_Pos (4U) |
| 8922 | #define CAN_F26R1_FB4_Pos (4U) |
8922 | #define CAN_F26R1_FB4_Msk (0x1UL << CAN_F26R1_FB4_Pos) /*!< 0x00000010 */ |
| 8923 | #define CAN_F26R1_FB4_Msk (0x1UL << CAN_F26R1_FB4_Pos) /*!< 0x00000010 */ |
8923 | #define CAN_F26R1_FB4 CAN_F26R1_FB4_Msk /*!< Filter bit 4 */ |
| 8924 | #define CAN_F26R1_FB4 CAN_F26R1_FB4_Msk /*!< Filter bit 4 */ |
8924 | #define CAN_F26R1_FB5_Pos (5U) |
| 8925 | #define CAN_F26R1_FB5_Pos (5U) |
8925 | #define CAN_F26R1_FB5_Msk (0x1UL << CAN_F26R1_FB5_Pos) /*!< 0x00000020 */ |
| 8926 | #define CAN_F26R1_FB5_Msk (0x1UL << CAN_F26R1_FB5_Pos) /*!< 0x00000020 */ |
8926 | #define CAN_F26R1_FB5 CAN_F26R1_FB5_Msk /*!< Filter bit 5 */ |
| 8927 | #define CAN_F26R1_FB5 CAN_F26R1_FB5_Msk /*!< Filter bit 5 */ |
8927 | #define CAN_F26R1_FB6_Pos (6U) |
| 8928 | #define CAN_F26R1_FB6_Pos (6U) |
8928 | #define CAN_F26R1_FB6_Msk (0x1UL << CAN_F26R1_FB6_Pos) /*!< 0x00000040 */ |
| 8929 | #define CAN_F26R1_FB6_Msk (0x1UL << CAN_F26R1_FB6_Pos) /*!< 0x00000040 */ |
8929 | #define CAN_F26R1_FB6 CAN_F26R1_FB6_Msk /*!< Filter bit 6 */ |
| 8930 | #define CAN_F26R1_FB6 CAN_F26R1_FB6_Msk /*!< Filter bit 6 */ |
8930 | #define CAN_F26R1_FB7_Pos (7U) |
| 8931 | #define CAN_F26R1_FB7_Pos (7U) |
8931 | #define CAN_F26R1_FB7_Msk (0x1UL << CAN_F26R1_FB7_Pos) /*!< 0x00000080 */ |
| 8932 | #define CAN_F26R1_FB7_Msk (0x1UL << CAN_F26R1_FB7_Pos) /*!< 0x00000080 */ |
8932 | #define CAN_F26R1_FB7 CAN_F26R1_FB7_Msk /*!< Filter bit 7 */ |
| 8933 | #define CAN_F26R1_FB7 CAN_F26R1_FB7_Msk /*!< Filter bit 7 */ |
8933 | #define CAN_F26R1_FB8_Pos (8U) |
| 8934 | #define CAN_F26R1_FB8_Pos (8U) |
8934 | #define CAN_F26R1_FB8_Msk (0x1UL << CAN_F26R1_FB8_Pos) /*!< 0x00000100 */ |
| 8935 | #define CAN_F26R1_FB8_Msk (0x1UL << CAN_F26R1_FB8_Pos) /*!< 0x00000100 */ |
8935 | #define CAN_F26R1_FB8 CAN_F26R1_FB8_Msk /*!< Filter bit 8 */ |
| 8936 | #define CAN_F26R1_FB8 CAN_F26R1_FB8_Msk /*!< Filter bit 8 */ |
8936 | #define CAN_F26R1_FB9_Pos (9U) |
| 8937 | #define CAN_F26R1_FB9_Pos (9U) |
8937 | #define CAN_F26R1_FB9_Msk (0x1UL << CAN_F26R1_FB9_Pos) /*!< 0x00000200 */ |
| 8938 | #define CAN_F26R1_FB9_Msk (0x1UL << CAN_F26R1_FB9_Pos) /*!< 0x00000200 */ |
8938 | #define CAN_F26R1_FB9 CAN_F26R1_FB9_Msk /*!< Filter bit 9 */ |
| 8939 | #define CAN_F26R1_FB9 CAN_F26R1_FB9_Msk /*!< Filter bit 9 */ |
8939 | #define CAN_F26R1_FB10_Pos (10U) |
| 8940 | #define CAN_F26R1_FB10_Pos (10U) |
8940 | #define CAN_F26R1_FB10_Msk (0x1UL << CAN_F26R1_FB10_Pos) /*!< 0x00000400 */ |
| 8941 | #define CAN_F26R1_FB10_Msk (0x1UL << CAN_F26R1_FB10_Pos) /*!< 0x00000400 */ |
8941 | #define CAN_F26R1_FB10 CAN_F26R1_FB10_Msk /*!< Filter bit 10 */ |
| 8942 | #define CAN_F26R1_FB10 CAN_F26R1_FB10_Msk /*!< Filter bit 10 */ |
8942 | #define CAN_F26R1_FB11_Pos (11U) |
| 8943 | #define CAN_F26R1_FB11_Pos (11U) |
8943 | #define CAN_F26R1_FB11_Msk (0x1UL << CAN_F26R1_FB11_Pos) /*!< 0x00000800 */ |
| 8944 | #define CAN_F26R1_FB11_Msk (0x1UL << CAN_F26R1_FB11_Pos) /*!< 0x00000800 */ |
8944 | #define CAN_F26R1_FB11 CAN_F26R1_FB11_Msk /*!< Filter bit 11 */ |
| 8945 | #define CAN_F26R1_FB11 CAN_F26R1_FB11_Msk /*!< Filter bit 11 */ |
8945 | #define CAN_F26R1_FB12_Pos (12U) |
| 8946 | #define CAN_F26R1_FB12_Pos (12U) |
8946 | #define CAN_F26R1_FB12_Msk (0x1UL << CAN_F26R1_FB12_Pos) /*!< 0x00001000 */ |
| 8947 | #define CAN_F26R1_FB12_Msk (0x1UL << CAN_F26R1_FB12_Pos) /*!< 0x00001000 */ |
8947 | #define CAN_F26R1_FB12 CAN_F26R1_FB12_Msk /*!< Filter bit 12 */ |
| 8948 | #define CAN_F26R1_FB12 CAN_F26R1_FB12_Msk /*!< Filter bit 12 */ |
8948 | #define CAN_F26R1_FB13_Pos (13U) |
| 8949 | #define CAN_F26R1_FB13_Pos (13U) |
8949 | #define CAN_F26R1_FB13_Msk (0x1UL << CAN_F26R1_FB13_Pos) /*!< 0x00002000 */ |
| 8950 | #define CAN_F26R1_FB13_Msk (0x1UL << CAN_F26R1_FB13_Pos) /*!< 0x00002000 */ |
8950 | #define CAN_F26R1_FB13 CAN_F26R1_FB13_Msk /*!< Filter bit 13 */ |
| 8951 | #define CAN_F26R1_FB13 CAN_F26R1_FB13_Msk /*!< Filter bit 13 */ |
8951 | #define CAN_F26R1_FB14_Pos (14U) |
| 8952 | #define CAN_F26R1_FB14_Pos (14U) |
8952 | #define CAN_F26R1_FB14_Msk (0x1UL << CAN_F26R1_FB14_Pos) /*!< 0x00004000 */ |
| 8953 | #define CAN_F26R1_FB14_Msk (0x1UL << CAN_F26R1_FB14_Pos) /*!< 0x00004000 */ |
8953 | #define CAN_F26R1_FB14 CAN_F26R1_FB14_Msk /*!< Filter bit 14 */ |
| 8954 | #define CAN_F26R1_FB14 CAN_F26R1_FB14_Msk /*!< Filter bit 14 */ |
8954 | #define CAN_F26R1_FB15_Pos (15U) |
| 8955 | #define CAN_F26R1_FB15_Pos (15U) |
8955 | #define CAN_F26R1_FB15_Msk (0x1UL << CAN_F26R1_FB15_Pos) /*!< 0x00008000 */ |
| 8956 | #define CAN_F26R1_FB15_Msk (0x1UL << CAN_F26R1_FB15_Pos) /*!< 0x00008000 */ |
8956 | #define CAN_F26R1_FB15 CAN_F26R1_FB15_Msk /*!< Filter bit 15 */ |
| 8957 | #define CAN_F26R1_FB15 CAN_F26R1_FB15_Msk /*!< Filter bit 15 */ |
8957 | #define CAN_F26R1_FB16_Pos (16U) |
| 8958 | #define CAN_F26R1_FB16_Pos (16U) |
8958 | #define CAN_F26R1_FB16_Msk (0x1UL << CAN_F26R1_FB16_Pos) /*!< 0x00010000 */ |
| 8959 | #define CAN_F26R1_FB16_Msk (0x1UL << CAN_F26R1_FB16_Pos) /*!< 0x00010000 */ |
8959 | #define CAN_F26R1_FB16 CAN_F26R1_FB16_Msk /*!< Filter bit 16 */ |
| 8960 | #define CAN_F26R1_FB16 CAN_F26R1_FB16_Msk /*!< Filter bit 16 */ |
8960 | #define CAN_F26R1_FB17_Pos (17U) |
| 8961 | #define CAN_F26R1_FB17_Pos (17U) |
8961 | #define CAN_F26R1_FB17_Msk (0x1UL << CAN_F26R1_FB17_Pos) /*!< 0x00020000 */ |
| 8962 | #define CAN_F26R1_FB17_Msk (0x1UL << CAN_F26R1_FB17_Pos) /*!< 0x00020000 */ |
8962 | #define CAN_F26R1_FB17 CAN_F26R1_FB17_Msk /*!< Filter bit 17 */ |
| 8963 | #define CAN_F26R1_FB17 CAN_F26R1_FB17_Msk /*!< Filter bit 17 */ |
8963 | #define CAN_F26R1_FB18_Pos (18U) |
| 8964 | #define CAN_F26R1_FB18_Pos (18U) |
8964 | #define CAN_F26R1_FB18_Msk (0x1UL << CAN_F26R1_FB18_Pos) /*!< 0x00040000 */ |
| 8965 | #define CAN_F26R1_FB18_Msk (0x1UL << CAN_F26R1_FB18_Pos) /*!< 0x00040000 */ |
8965 | #define CAN_F26R1_FB18 CAN_F26R1_FB18_Msk /*!< Filter bit 18 */ |
| 8966 | #define CAN_F26R1_FB18 CAN_F26R1_FB18_Msk /*!< Filter bit 18 */ |
8966 | #define CAN_F26R1_FB19_Pos (19U) |
| 8967 | #define CAN_F26R1_FB19_Pos (19U) |
8967 | #define CAN_F26R1_FB19_Msk (0x1UL << CAN_F26R1_FB19_Pos) /*!< 0x00080000 */ |
| 8968 | #define CAN_F26R1_FB19_Msk (0x1UL << CAN_F26R1_FB19_Pos) /*!< 0x00080000 */ |
8968 | #define CAN_F26R1_FB19 CAN_F26R1_FB19_Msk /*!< Filter bit 19 */ |
| 8969 | #define CAN_F26R1_FB19 CAN_F26R1_FB19_Msk /*!< Filter bit 19 */ |
8969 | #define CAN_F26R1_FB20_Pos (20U) |
| 8970 | #define CAN_F26R1_FB20_Pos (20U) |
8970 | #define CAN_F26R1_FB20_Msk (0x1UL << CAN_F26R1_FB20_Pos) /*!< 0x00100000 */ |
| 8971 | #define CAN_F26R1_FB20_Msk (0x1UL << CAN_F26R1_FB20_Pos) /*!< 0x00100000 */ |
8971 | #define CAN_F26R1_FB20 CAN_F26R1_FB20_Msk /*!< Filter bit 20 */ |
| 8972 | #define CAN_F26R1_FB20 CAN_F26R1_FB20_Msk /*!< Filter bit 20 */ |
8972 | #define CAN_F26R1_FB21_Pos (21U) |
| 8973 | #define CAN_F26R1_FB21_Pos (21U) |
8973 | #define CAN_F26R1_FB21_Msk (0x1UL << CAN_F26R1_FB21_Pos) /*!< 0x00200000 */ |
| 8974 | #define CAN_F26R1_FB21_Msk (0x1UL << CAN_F26R1_FB21_Pos) /*!< 0x00200000 */ |
8974 | #define CAN_F26R1_FB21 CAN_F26R1_FB21_Msk /*!< Filter bit 21 */ |
| 8975 | #define CAN_F26R1_FB21 CAN_F26R1_FB21_Msk /*!< Filter bit 21 */ |
8975 | #define CAN_F26R1_FB22_Pos (22U) |
| 8976 | #define CAN_F26R1_FB22_Pos (22U) |
8976 | #define CAN_F26R1_FB22_Msk (0x1UL << CAN_F26R1_FB22_Pos) /*!< 0x00400000 */ |
| 8977 | #define CAN_F26R1_FB22_Msk (0x1UL << CAN_F26R1_FB22_Pos) /*!< 0x00400000 */ |
8977 | #define CAN_F26R1_FB22 CAN_F26R1_FB22_Msk /*!< Filter bit 22 */ |
| 8978 | #define CAN_F26R1_FB22 CAN_F26R1_FB22_Msk /*!< Filter bit 22 */ |
8978 | #define CAN_F26R1_FB23_Pos (23U) |
| 8979 | #define CAN_F26R1_FB23_Pos (23U) |
8979 | #define CAN_F26R1_FB23_Msk (0x1UL << CAN_F26R1_FB23_Pos) /*!< 0x00800000 */ |
| 8980 | #define CAN_F26R1_FB23_Msk (0x1UL << CAN_F26R1_FB23_Pos) /*!< 0x00800000 */ |
8980 | #define CAN_F26R1_FB23 CAN_F26R1_FB23_Msk /*!< Filter bit 23 */ |
| 8981 | #define CAN_F26R1_FB23 CAN_F26R1_FB23_Msk /*!< Filter bit 23 */ |
8981 | #define CAN_F26R1_FB24_Pos (24U) |
| 8982 | #define CAN_F26R1_FB24_Pos (24U) |
8982 | #define CAN_F26R1_FB24_Msk (0x1UL << CAN_F26R1_FB24_Pos) /*!< 0x01000000 */ |
| 8983 | #define CAN_F26R1_FB24_Msk (0x1UL << CAN_F26R1_FB24_Pos) /*!< 0x01000000 */ |
8983 | #define CAN_F26R1_FB24 CAN_F26R1_FB24_Msk /*!< Filter bit 24 */ |
| 8984 | #define CAN_F26R1_FB24 CAN_F26R1_FB24_Msk /*!< Filter bit 24 */ |
8984 | #define CAN_F26R1_FB25_Pos (25U) |
| 8985 | #define CAN_F26R1_FB25_Pos (25U) |
8985 | #define CAN_F26R1_FB25_Msk (0x1UL << CAN_F26R1_FB25_Pos) /*!< 0x02000000 */ |
| 8986 | #define CAN_F26R1_FB25_Msk (0x1UL << CAN_F26R1_FB25_Pos) /*!< 0x02000000 */ |
8986 | #define CAN_F26R1_FB25 CAN_F26R1_FB25_Msk /*!< Filter bit 25 */ |
| 8987 | #define CAN_F26R1_FB25 CAN_F26R1_FB25_Msk /*!< Filter bit 25 */ |
8987 | #define CAN_F26R1_FB26_Pos (26U) |
| 8988 | #define CAN_F26R1_FB26_Pos (26U) |
8988 | #define CAN_F26R1_FB26_Msk (0x1UL << CAN_F26R1_FB26_Pos) /*!< 0x04000000 */ |
| 8989 | #define CAN_F26R1_FB26_Msk (0x1UL << CAN_F26R1_FB26_Pos) /*!< 0x04000000 */ |
8989 | #define CAN_F26R1_FB26 CAN_F26R1_FB26_Msk /*!< Filter bit 26 */ |
| 8990 | #define CAN_F26R1_FB26 CAN_F26R1_FB26_Msk /*!< Filter bit 26 */ |
8990 | #define CAN_F26R1_FB27_Pos (27U) |
| 8991 | #define CAN_F26R1_FB27_Pos (27U) |
8991 | #define CAN_F26R1_FB27_Msk (0x1UL << CAN_F26R1_FB27_Pos) /*!< 0x08000000 */ |
| 8992 | #define CAN_F26R1_FB27_Msk (0x1UL << CAN_F26R1_FB27_Pos) /*!< 0x08000000 */ |
8992 | #define CAN_F26R1_FB27 CAN_F26R1_FB27_Msk /*!< Filter bit 27 */ |
| 8993 | #define CAN_F26R1_FB27 CAN_F26R1_FB27_Msk /*!< Filter bit 27 */ |
8993 | #define CAN_F26R1_FB28_Pos (28U) |
| 8994 | #define CAN_F26R1_FB28_Pos (28U) |
8994 | #define CAN_F26R1_FB28_Msk (0x1UL << CAN_F26R1_FB28_Pos) /*!< 0x10000000 */ |
| 8995 | #define CAN_F26R1_FB28_Msk (0x1UL << CAN_F26R1_FB28_Pos) /*!< 0x10000000 */ |
8995 | #define CAN_F26R1_FB28 CAN_F26R1_FB28_Msk /*!< Filter bit 28 */ |
| 8996 | #define CAN_F26R1_FB28 CAN_F26R1_FB28_Msk /*!< Filter bit 28 */ |
8996 | #define CAN_F26R1_FB29_Pos (29U) |
| 8997 | #define CAN_F26R1_FB29_Pos (29U) |
8997 | #define CAN_F26R1_FB29_Msk (0x1UL << CAN_F26R1_FB29_Pos) /*!< 0x20000000 */ |
| 8998 | #define CAN_F26R1_FB29_Msk (0x1UL << CAN_F26R1_FB29_Pos) /*!< 0x20000000 */ |
8998 | #define CAN_F26R1_FB29 CAN_F26R1_FB29_Msk /*!< Filter bit 29 */ |
| 8999 | #define CAN_F26R1_FB29 CAN_F26R1_FB29_Msk /*!< Filter bit 29 */ |
8999 | #define CAN_F26R1_FB30_Pos (30U) |
| 9000 | #define CAN_F26R1_FB30_Pos (30U) |
9000 | #define CAN_F26R1_FB30_Msk (0x1UL << CAN_F26R1_FB30_Pos) /*!< 0x40000000 */ |
| 9001 | #define CAN_F26R1_FB30_Msk (0x1UL << CAN_F26R1_FB30_Pos) /*!< 0x40000000 */ |
9001 | #define CAN_F26R1_FB30 CAN_F26R1_FB30_Msk /*!< Filter bit 30 */ |
| 9002 | #define CAN_F26R1_FB30 CAN_F26R1_FB30_Msk /*!< Filter bit 30 */ |
9002 | #define CAN_F26R1_FB31_Pos (31U) |
| 9003 | #define CAN_F26R1_FB31_Pos (31U) |
9003 | #define CAN_F26R1_FB31_Msk (0x1UL << CAN_F26R1_FB31_Pos) /*!< 0x80000000 */ |
| 9004 | #define CAN_F26R1_FB31_Msk (0x1UL << CAN_F26R1_FB31_Pos) /*!< 0x80000000 */ |
9004 | #define CAN_F26R1_FB31 CAN_F26R1_FB31_Msk /*!< Filter bit 31 */ |
| 9005 | #define CAN_F26R1_FB31 CAN_F26R1_FB31_Msk /*!< Filter bit 31 */ |
9005 | |
| 9006 | 9006 | /******************* Bit definition for CAN_F27R1 register ******************/ |
|
| 9007 | /******************* Bit definition for CAN_F27R1 register ******************/ |
9007 | #define CAN_F27R1_FB0_Pos (0U) |
| 9008 | #define CAN_F27R1_FB0_Pos (0U) |
9008 | #define CAN_F27R1_FB0_Msk (0x1UL << CAN_F27R1_FB0_Pos) /*!< 0x00000001 */ |
| 9009 | #define CAN_F27R1_FB0_Msk (0x1UL << CAN_F27R1_FB0_Pos) /*!< 0x00000001 */ |
9009 | #define CAN_F27R1_FB0 CAN_F27R1_FB0_Msk /*!< Filter bit 0 */ |
| 9010 | #define CAN_F27R1_FB0 CAN_F27R1_FB0_Msk /*!< Filter bit 0 */ |
9010 | #define CAN_F27R1_FB1_Pos (1U) |
| 9011 | #define CAN_F27R1_FB1_Pos (1U) |
9011 | #define CAN_F27R1_FB1_Msk (0x1UL << CAN_F27R1_FB1_Pos) /*!< 0x00000002 */ |
| 9012 | #define CAN_F27R1_FB1_Msk (0x1UL << CAN_F27R1_FB1_Pos) /*!< 0x00000002 */ |
9012 | #define CAN_F27R1_FB1 CAN_F27R1_FB1_Msk /*!< Filter bit 1 */ |
| 9013 | #define CAN_F27R1_FB1 CAN_F27R1_FB1_Msk /*!< Filter bit 1 */ |
9013 | #define CAN_F27R1_FB2_Pos (2U) |
| 9014 | #define CAN_F27R1_FB2_Pos (2U) |
9014 | #define CAN_F27R1_FB2_Msk (0x1UL << CAN_F27R1_FB2_Pos) /*!< 0x00000004 */ |
| 9015 | #define CAN_F27R1_FB2_Msk (0x1UL << CAN_F27R1_FB2_Pos) /*!< 0x00000004 */ |
9015 | #define CAN_F27R1_FB2 CAN_F27R1_FB2_Msk /*!< Filter bit 2 */ |
| 9016 | #define CAN_F27R1_FB2 CAN_F27R1_FB2_Msk /*!< Filter bit 2 */ |
9016 | #define CAN_F27R1_FB3_Pos (3U) |
| 9017 | #define CAN_F27R1_FB3_Pos (3U) |
9017 | #define CAN_F27R1_FB3_Msk (0x1UL << CAN_F27R1_FB3_Pos) /*!< 0x00000008 */ |
| 9018 | #define CAN_F27R1_FB3_Msk (0x1UL << CAN_F27R1_FB3_Pos) /*!< 0x00000008 */ |
9018 | #define CAN_F27R1_FB3 CAN_F27R1_FB3_Msk /*!< Filter bit 3 */ |
| 9019 | #define CAN_F27R1_FB3 CAN_F27R1_FB3_Msk /*!< Filter bit 3 */ |
9019 | #define CAN_F27R1_FB4_Pos (4U) |
| 9020 | #define CAN_F27R1_FB4_Pos (4U) |
9020 | #define CAN_F27R1_FB4_Msk (0x1UL << CAN_F27R1_FB4_Pos) /*!< 0x00000010 */ |
| 9021 | #define CAN_F27R1_FB4_Msk (0x1UL << CAN_F27R1_FB4_Pos) /*!< 0x00000010 */ |
9021 | #define CAN_F27R1_FB4 CAN_F27R1_FB4_Msk /*!< Filter bit 4 */ |
| 9022 | #define CAN_F27R1_FB4 CAN_F27R1_FB4_Msk /*!< Filter bit 4 */ |
9022 | #define CAN_F27R1_FB5_Pos (5U) |
| 9023 | #define CAN_F27R1_FB5_Pos (5U) |
9023 | #define CAN_F27R1_FB5_Msk (0x1UL << CAN_F27R1_FB5_Pos) /*!< 0x00000020 */ |
| 9024 | #define CAN_F27R1_FB5_Msk (0x1UL << CAN_F27R1_FB5_Pos) /*!< 0x00000020 */ |
9024 | #define CAN_F27R1_FB5 CAN_F27R1_FB5_Msk /*!< Filter bit 5 */ |
| 9025 | #define CAN_F27R1_FB5 CAN_F27R1_FB5_Msk /*!< Filter bit 5 */ |
9025 | #define CAN_F27R1_FB6_Pos (6U) |
| 9026 | #define CAN_F27R1_FB6_Pos (6U) |
9026 | #define CAN_F27R1_FB6_Msk (0x1UL << CAN_F27R1_FB6_Pos) /*!< 0x00000040 */ |
| 9027 | #define CAN_F27R1_FB6_Msk (0x1UL << CAN_F27R1_FB6_Pos) /*!< 0x00000040 */ |
9027 | #define CAN_F27R1_FB6 CAN_F27R1_FB6_Msk /*!< Filter bit 6 */ |
| 9028 | #define CAN_F27R1_FB6 CAN_F27R1_FB6_Msk /*!< Filter bit 6 */ |
9028 | #define CAN_F27R1_FB7_Pos (7U) |
| 9029 | #define CAN_F27R1_FB7_Pos (7U) |
9029 | #define CAN_F27R1_FB7_Msk (0x1UL << CAN_F27R1_FB7_Pos) /*!< 0x00000080 */ |
| 9030 | #define CAN_F27R1_FB7_Msk (0x1UL << CAN_F27R1_FB7_Pos) /*!< 0x00000080 */ |
9030 | #define CAN_F27R1_FB7 CAN_F27R1_FB7_Msk /*!< Filter bit 7 */ |
| 9031 | #define CAN_F27R1_FB7 CAN_F27R1_FB7_Msk /*!< Filter bit 7 */ |
9031 | #define CAN_F27R1_FB8_Pos (8U) |
| 9032 | #define CAN_F27R1_FB8_Pos (8U) |
9032 | #define CAN_F27R1_FB8_Msk (0x1UL << CAN_F27R1_FB8_Pos) /*!< 0x00000100 */ |
| 9033 | #define CAN_F27R1_FB8_Msk (0x1UL << CAN_F27R1_FB8_Pos) /*!< 0x00000100 */ |
9033 | #define CAN_F27R1_FB8 CAN_F27R1_FB8_Msk /*!< Filter bit 8 */ |
| 9034 | #define CAN_F27R1_FB8 CAN_F27R1_FB8_Msk /*!< Filter bit 8 */ |
9034 | #define CAN_F27R1_FB9_Pos (9U) |
| 9035 | #define CAN_F27R1_FB9_Pos (9U) |
9035 | #define CAN_F27R1_FB9_Msk (0x1UL << CAN_F27R1_FB9_Pos) /*!< 0x00000200 */ |
| 9036 | #define CAN_F27R1_FB9_Msk (0x1UL << CAN_F27R1_FB9_Pos) /*!< 0x00000200 */ |
9036 | #define CAN_F27R1_FB9 CAN_F27R1_FB9_Msk /*!< Filter bit 9 */ |
| 9037 | #define CAN_F27R1_FB9 CAN_F27R1_FB9_Msk /*!< Filter bit 9 */ |
9037 | #define CAN_F27R1_FB10_Pos (10U) |
| 9038 | #define CAN_F27R1_FB10_Pos (10U) |
9038 | #define CAN_F27R1_FB10_Msk (0x1UL << CAN_F27R1_FB10_Pos) /*!< 0x00000400 */ |
| 9039 | #define CAN_F27R1_FB10_Msk (0x1UL << CAN_F27R1_FB10_Pos) /*!< 0x00000400 */ |
9039 | #define CAN_F27R1_FB10 CAN_F27R1_FB10_Msk /*!< Filter bit 10 */ |
| 9040 | #define CAN_F27R1_FB10 CAN_F27R1_FB10_Msk /*!< Filter bit 10 */ |
9040 | #define CAN_F27R1_FB11_Pos (11U) |
| 9041 | #define CAN_F27R1_FB11_Pos (11U) |
9041 | #define CAN_F27R1_FB11_Msk (0x1UL << CAN_F27R1_FB11_Pos) /*!< 0x00000800 */ |
| 9042 | #define CAN_F27R1_FB11_Msk (0x1UL << CAN_F27R1_FB11_Pos) /*!< 0x00000800 */ |
9042 | #define CAN_F27R1_FB11 CAN_F27R1_FB11_Msk /*!< Filter bit 11 */ |
| 9043 | #define CAN_F27R1_FB11 CAN_F27R1_FB11_Msk /*!< Filter bit 11 */ |
9043 | #define CAN_F27R1_FB12_Pos (12U) |
| 9044 | #define CAN_F27R1_FB12_Pos (12U) |
9044 | #define CAN_F27R1_FB12_Msk (0x1UL << CAN_F27R1_FB12_Pos) /*!< 0x00001000 */ |
| 9045 | #define CAN_F27R1_FB12_Msk (0x1UL << CAN_F27R1_FB12_Pos) /*!< 0x00001000 */ |
9045 | #define CAN_F27R1_FB12 CAN_F27R1_FB12_Msk /*!< Filter bit 12 */ |
| 9046 | #define CAN_F27R1_FB12 CAN_F27R1_FB12_Msk /*!< Filter bit 12 */ |
9046 | #define CAN_F27R1_FB13_Pos (13U) |
| 9047 | #define CAN_F27R1_FB13_Pos (13U) |
9047 | #define CAN_F27R1_FB13_Msk (0x1UL << CAN_F27R1_FB13_Pos) /*!< 0x00002000 */ |
| 9048 | #define CAN_F27R1_FB13_Msk (0x1UL << CAN_F27R1_FB13_Pos) /*!< 0x00002000 */ |
9048 | #define CAN_F27R1_FB13 CAN_F27R1_FB13_Msk /*!< Filter bit 13 */ |
| 9049 | #define CAN_F27R1_FB13 CAN_F27R1_FB13_Msk /*!< Filter bit 13 */ |
9049 | #define CAN_F27R1_FB14_Pos (14U) |
| 9050 | #define CAN_F27R1_FB14_Pos (14U) |
9050 | #define CAN_F27R1_FB14_Msk (0x1UL << CAN_F27R1_FB14_Pos) /*!< 0x00004000 */ |
| 9051 | #define CAN_F27R1_FB14_Msk (0x1UL << CAN_F27R1_FB14_Pos) /*!< 0x00004000 */ |
9051 | #define CAN_F27R1_FB14 CAN_F27R1_FB14_Msk /*!< Filter bit 14 */ |
| 9052 | #define CAN_F27R1_FB14 CAN_F27R1_FB14_Msk /*!< Filter bit 14 */ |
9052 | #define CAN_F27R1_FB15_Pos (15U) |
| 9053 | #define CAN_F27R1_FB15_Pos (15U) |
9053 | #define CAN_F27R1_FB15_Msk (0x1UL << CAN_F27R1_FB15_Pos) /*!< 0x00008000 */ |
| 9054 | #define CAN_F27R1_FB15_Msk (0x1UL << CAN_F27R1_FB15_Pos) /*!< 0x00008000 */ |
9054 | #define CAN_F27R1_FB15 CAN_F27R1_FB15_Msk /*!< Filter bit 15 */ |
| 9055 | #define CAN_F27R1_FB15 CAN_F27R1_FB15_Msk /*!< Filter bit 15 */ |
9055 | #define CAN_F27R1_FB16_Pos (16U) |
| 9056 | #define CAN_F27R1_FB16_Pos (16U) |
9056 | #define CAN_F27R1_FB16_Msk (0x1UL << CAN_F27R1_FB16_Pos) /*!< 0x00010000 */ |
| 9057 | #define CAN_F27R1_FB16_Msk (0x1UL << CAN_F27R1_FB16_Pos) /*!< 0x00010000 */ |
9057 | #define CAN_F27R1_FB16 CAN_F27R1_FB16_Msk /*!< Filter bit 16 */ |
| 9058 | #define CAN_F27R1_FB16 CAN_F27R1_FB16_Msk /*!< Filter bit 16 */ |
9058 | #define CAN_F27R1_FB17_Pos (17U) |
| 9059 | #define CAN_F27R1_FB17_Pos (17U) |
9059 | #define CAN_F27R1_FB17_Msk (0x1UL << CAN_F27R1_FB17_Pos) /*!< 0x00020000 */ |
| 9060 | #define CAN_F27R1_FB17_Msk (0x1UL << CAN_F27R1_FB17_Pos) /*!< 0x00020000 */ |
9060 | #define CAN_F27R1_FB17 CAN_F27R1_FB17_Msk /*!< Filter bit 17 */ |
| 9061 | #define CAN_F27R1_FB17 CAN_F27R1_FB17_Msk /*!< Filter bit 17 */ |
9061 | #define CAN_F27R1_FB18_Pos (18U) |
| 9062 | #define CAN_F27R1_FB18_Pos (18U) |
9062 | #define CAN_F27R1_FB18_Msk (0x1UL << CAN_F27R1_FB18_Pos) /*!< 0x00040000 */ |
| 9063 | #define CAN_F27R1_FB18_Msk (0x1UL << CAN_F27R1_FB18_Pos) /*!< 0x00040000 */ |
9063 | #define CAN_F27R1_FB18 CAN_F27R1_FB18_Msk /*!< Filter bit 18 */ |
| 9064 | #define CAN_F27R1_FB18 CAN_F27R1_FB18_Msk /*!< Filter bit 18 */ |
9064 | #define CAN_F27R1_FB19_Pos (19U) |
| 9065 | #define CAN_F27R1_FB19_Pos (19U) |
9065 | #define CAN_F27R1_FB19_Msk (0x1UL << CAN_F27R1_FB19_Pos) /*!< 0x00080000 */ |
| 9066 | #define CAN_F27R1_FB19_Msk (0x1UL << CAN_F27R1_FB19_Pos) /*!< 0x00080000 */ |
9066 | #define CAN_F27R1_FB19 CAN_F27R1_FB19_Msk /*!< Filter bit 19 */ |
| 9067 | #define CAN_F27R1_FB19 CAN_F27R1_FB19_Msk /*!< Filter bit 19 */ |
9067 | #define CAN_F27R1_FB20_Pos (20U) |
| 9068 | #define CAN_F27R1_FB20_Pos (20U) |
9068 | #define CAN_F27R1_FB20_Msk (0x1UL << CAN_F27R1_FB20_Pos) /*!< 0x00100000 */ |
| 9069 | #define CAN_F27R1_FB20_Msk (0x1UL << CAN_F27R1_FB20_Pos) /*!< 0x00100000 */ |
9069 | #define CAN_F27R1_FB20 CAN_F27R1_FB20_Msk /*!< Filter bit 20 */ |
| 9070 | #define CAN_F27R1_FB20 CAN_F27R1_FB20_Msk /*!< Filter bit 20 */ |
9070 | #define CAN_F27R1_FB21_Pos (21U) |
| 9071 | #define CAN_F27R1_FB21_Pos (21U) |
9071 | #define CAN_F27R1_FB21_Msk (0x1UL << CAN_F27R1_FB21_Pos) /*!< 0x00200000 */ |
| 9072 | #define CAN_F27R1_FB21_Msk (0x1UL << CAN_F27R1_FB21_Pos) /*!< 0x00200000 */ |
9072 | #define CAN_F27R1_FB21 CAN_F27R1_FB21_Msk /*!< Filter bit 21 */ |
| 9073 | #define CAN_F27R1_FB21 CAN_F27R1_FB21_Msk /*!< Filter bit 21 */ |
9073 | #define CAN_F27R1_FB22_Pos (22U) |
| 9074 | #define CAN_F27R1_FB22_Pos (22U) |
9074 | #define CAN_F27R1_FB22_Msk (0x1UL << CAN_F27R1_FB22_Pos) /*!< 0x00400000 */ |
| 9075 | #define CAN_F27R1_FB22_Msk (0x1UL << CAN_F27R1_FB22_Pos) /*!< 0x00400000 */ |
9075 | #define CAN_F27R1_FB22 CAN_F27R1_FB22_Msk /*!< Filter bit 22 */ |
| 9076 | #define CAN_F27R1_FB22 CAN_F27R1_FB22_Msk /*!< Filter bit 22 */ |
9076 | #define CAN_F27R1_FB23_Pos (23U) |
| 9077 | #define CAN_F27R1_FB23_Pos (23U) |
9077 | #define CAN_F27R1_FB23_Msk (0x1UL << CAN_F27R1_FB23_Pos) /*!< 0x00800000 */ |
| 9078 | #define CAN_F27R1_FB23_Msk (0x1UL << CAN_F27R1_FB23_Pos) /*!< 0x00800000 */ |
9078 | #define CAN_F27R1_FB23 CAN_F27R1_FB23_Msk /*!< Filter bit 23 */ |
| 9079 | #define CAN_F27R1_FB23 CAN_F27R1_FB23_Msk /*!< Filter bit 23 */ |
9079 | #define CAN_F27R1_FB24_Pos (24U) |
| 9080 | #define CAN_F27R1_FB24_Pos (24U) |
9080 | #define CAN_F27R1_FB24_Msk (0x1UL << CAN_F27R1_FB24_Pos) /*!< 0x01000000 */ |
| 9081 | #define CAN_F27R1_FB24_Msk (0x1UL << CAN_F27R1_FB24_Pos) /*!< 0x01000000 */ |
9081 | #define CAN_F27R1_FB24 CAN_F27R1_FB24_Msk /*!< Filter bit 24 */ |
| 9082 | #define CAN_F27R1_FB24 CAN_F27R1_FB24_Msk /*!< Filter bit 24 */ |
9082 | #define CAN_F27R1_FB25_Pos (25U) |
| 9083 | #define CAN_F27R1_FB25_Pos (25U) |
9083 | #define CAN_F27R1_FB25_Msk (0x1UL << CAN_F27R1_FB25_Pos) /*!< 0x02000000 */ |
| 9084 | #define CAN_F27R1_FB25_Msk (0x1UL << CAN_F27R1_FB25_Pos) /*!< 0x02000000 */ |
9084 | #define CAN_F27R1_FB25 CAN_F27R1_FB25_Msk /*!< Filter bit 25 */ |
| 9085 | #define CAN_F27R1_FB25 CAN_F27R1_FB25_Msk /*!< Filter bit 25 */ |
9085 | #define CAN_F27R1_FB26_Pos (26U) |
| 9086 | #define CAN_F27R1_FB26_Pos (26U) |
9086 | #define CAN_F27R1_FB26_Msk (0x1UL << CAN_F27R1_FB26_Pos) /*!< 0x04000000 */ |
| 9087 | #define CAN_F27R1_FB26_Msk (0x1UL << CAN_F27R1_FB26_Pos) /*!< 0x04000000 */ |
9087 | #define CAN_F27R1_FB26 CAN_F27R1_FB26_Msk /*!< Filter bit 26 */ |
| 9088 | #define CAN_F27R1_FB26 CAN_F27R1_FB26_Msk /*!< Filter bit 26 */ |
9088 | #define CAN_F27R1_FB27_Pos (27U) |
| 9089 | #define CAN_F27R1_FB27_Pos (27U) |
9089 | #define CAN_F27R1_FB27_Msk (0x1UL << CAN_F27R1_FB27_Pos) /*!< 0x08000000 */ |
| 9090 | #define CAN_F27R1_FB27_Msk (0x1UL << CAN_F27R1_FB27_Pos) /*!< 0x08000000 */ |
9090 | #define CAN_F27R1_FB27 CAN_F27R1_FB27_Msk /*!< Filter bit 27 */ |
| 9091 | #define CAN_F27R1_FB27 CAN_F27R1_FB27_Msk /*!< Filter bit 27 */ |
9091 | #define CAN_F27R1_FB28_Pos (28U) |
| 9092 | #define CAN_F27R1_FB28_Pos (28U) |
9092 | #define CAN_F27R1_FB28_Msk (0x1UL << CAN_F27R1_FB28_Pos) /*!< 0x10000000 */ |
| 9093 | #define CAN_F27R1_FB28_Msk (0x1UL << CAN_F27R1_FB28_Pos) /*!< 0x10000000 */ |
9093 | #define CAN_F27R1_FB28 CAN_F27R1_FB28_Msk /*!< Filter bit 28 */ |
| 9094 | #define CAN_F27R1_FB28 CAN_F27R1_FB28_Msk /*!< Filter bit 28 */ |
9094 | #define CAN_F27R1_FB29_Pos (29U) |
| 9095 | #define CAN_F27R1_FB29_Pos (29U) |
9095 | #define CAN_F27R1_FB29_Msk (0x1UL << CAN_F27R1_FB29_Pos) /*!< 0x20000000 */ |
| 9096 | #define CAN_F27R1_FB29_Msk (0x1UL << CAN_F27R1_FB29_Pos) /*!< 0x20000000 */ |
9096 | #define CAN_F27R1_FB29 CAN_F27R1_FB29_Msk /*!< Filter bit 29 */ |
| 9097 | #define CAN_F27R1_FB29 CAN_F27R1_FB29_Msk /*!< Filter bit 29 */ |
9097 | #define CAN_F27R1_FB30_Pos (30U) |
| 9098 | #define CAN_F27R1_FB30_Pos (30U) |
9098 | #define CAN_F27R1_FB30_Msk (0x1UL << CAN_F27R1_FB30_Pos) /*!< 0x40000000 */ |
| 9099 | #define CAN_F27R1_FB30_Msk (0x1UL << CAN_F27R1_FB30_Pos) /*!< 0x40000000 */ |
9099 | #define CAN_F27R1_FB30 CAN_F27R1_FB30_Msk /*!< Filter bit 30 */ |
| 9100 | #define CAN_F27R1_FB30 CAN_F27R1_FB30_Msk /*!< Filter bit 30 */ |
9100 | #define CAN_F27R1_FB31_Pos (31U) |
| 9101 | #define CAN_F27R1_FB31_Pos (31U) |
9101 | #define CAN_F27R1_FB31_Msk (0x1UL << CAN_F27R1_FB31_Pos) /*!< 0x80000000 */ |
| 9102 | #define CAN_F27R1_FB31_Msk (0x1UL << CAN_F27R1_FB31_Pos) /*!< 0x80000000 */ |
9102 | #define CAN_F27R1_FB31 CAN_F27R1_FB31_Msk /*!< Filter bit 31 */ |
| 9103 | #define CAN_F27R1_FB31 CAN_F27R1_FB31_Msk /*!< Filter bit 31 */ |
9103 | |
| 9104 | 9104 | /******************* Bit definition for CAN_F0R2 register *******************/ |
|
| 9105 | /******************* Bit definition for CAN_F0R2 register *******************/ |
9105 | #define CAN_F0R2_FB0_Pos (0U) |
| 9106 | #define CAN_F0R2_FB0_Pos (0U) |
9106 | #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ |
| 9107 | #define CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos) /*!< 0x00000001 */ |
9107 | #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */ |
| 9108 | #define CAN_F0R2_FB0 CAN_F0R2_FB0_Msk /*!< Filter bit 0 */ |
9108 | #define CAN_F0R2_FB1_Pos (1U) |
| 9109 | #define CAN_F0R2_FB1_Pos (1U) |
9109 | #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ |
| 9110 | #define CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos) /*!< 0x00000002 */ |
9110 | #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */ |
| 9111 | #define CAN_F0R2_FB1 CAN_F0R2_FB1_Msk /*!< Filter bit 1 */ |
9111 | #define CAN_F0R2_FB2_Pos (2U) |
| 9112 | #define CAN_F0R2_FB2_Pos (2U) |
9112 | #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ |
| 9113 | #define CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos) /*!< 0x00000004 */ |
9113 | #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */ |
| 9114 | #define CAN_F0R2_FB2 CAN_F0R2_FB2_Msk /*!< Filter bit 2 */ |
9114 | #define CAN_F0R2_FB3_Pos (3U) |
| 9115 | #define CAN_F0R2_FB3_Pos (3U) |
9115 | #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ |
| 9116 | #define CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos) /*!< 0x00000008 */ |
9116 | #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */ |
| 9117 | #define CAN_F0R2_FB3 CAN_F0R2_FB3_Msk /*!< Filter bit 3 */ |
9117 | #define CAN_F0R2_FB4_Pos (4U) |
| 9118 | #define CAN_F0R2_FB4_Pos (4U) |
9118 | #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ |
| 9119 | #define CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos) /*!< 0x00000010 */ |
9119 | #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */ |
| 9120 | #define CAN_F0R2_FB4 CAN_F0R2_FB4_Msk /*!< Filter bit 4 */ |
9120 | #define CAN_F0R2_FB5_Pos (5U) |
| 9121 | #define CAN_F0R2_FB5_Pos (5U) |
9121 | #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ |
| 9122 | #define CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos) /*!< 0x00000020 */ |
9122 | #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */ |
| 9123 | #define CAN_F0R2_FB5 CAN_F0R2_FB5_Msk /*!< Filter bit 5 */ |
9123 | #define CAN_F0R2_FB6_Pos (6U) |
| 9124 | #define CAN_F0R2_FB6_Pos (6U) |
9124 | #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ |
| 9125 | #define CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos) /*!< 0x00000040 */ |
9125 | #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */ |
| 9126 | #define CAN_F0R2_FB6 CAN_F0R2_FB6_Msk /*!< Filter bit 6 */ |
9126 | #define CAN_F0R2_FB7_Pos (7U) |
| 9127 | #define CAN_F0R2_FB7_Pos (7U) |
9127 | #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ |
| 9128 | #define CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos) /*!< 0x00000080 */ |
9128 | #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */ |
| 9129 | #define CAN_F0R2_FB7 CAN_F0R2_FB7_Msk /*!< Filter bit 7 */ |
9129 | #define CAN_F0R2_FB8_Pos (8U) |
| 9130 | #define CAN_F0R2_FB8_Pos (8U) |
9130 | #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ |
| 9131 | #define CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos) /*!< 0x00000100 */ |
9131 | #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */ |
| 9132 | #define CAN_F0R2_FB8 CAN_F0R2_FB8_Msk /*!< Filter bit 8 */ |
9132 | #define CAN_F0R2_FB9_Pos (9U) |
| 9133 | #define CAN_F0R2_FB9_Pos (9U) |
9133 | #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ |
| 9134 | #define CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos) /*!< 0x00000200 */ |
9134 | #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */ |
| 9135 | #define CAN_F0R2_FB9 CAN_F0R2_FB9_Msk /*!< Filter bit 9 */ |
9135 | #define CAN_F0R2_FB10_Pos (10U) |
| 9136 | #define CAN_F0R2_FB10_Pos (10U) |
9136 | #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ |
| 9137 | #define CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos) /*!< 0x00000400 */ |
9137 | #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */ |
| 9138 | #define CAN_F0R2_FB10 CAN_F0R2_FB10_Msk /*!< Filter bit 10 */ |
9138 | #define CAN_F0R2_FB11_Pos (11U) |
| 9139 | #define CAN_F0R2_FB11_Pos (11U) |
9139 | #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ |
| 9140 | #define CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos) /*!< 0x00000800 */ |
9140 | #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */ |
| 9141 | #define CAN_F0R2_FB11 CAN_F0R2_FB11_Msk /*!< Filter bit 11 */ |
9141 | #define CAN_F0R2_FB12_Pos (12U) |
| 9142 | #define CAN_F0R2_FB12_Pos (12U) |
9142 | #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ |
| 9143 | #define CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos) /*!< 0x00001000 */ |
9143 | #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */ |
| 9144 | #define CAN_F0R2_FB12 CAN_F0R2_FB12_Msk /*!< Filter bit 12 */ |
9144 | #define CAN_F0R2_FB13_Pos (13U) |
| 9145 | #define CAN_F0R2_FB13_Pos (13U) |
9145 | #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ |
| 9146 | #define CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos) /*!< 0x00002000 */ |
9146 | #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */ |
| 9147 | #define CAN_F0R2_FB13 CAN_F0R2_FB13_Msk /*!< Filter bit 13 */ |
9147 | #define CAN_F0R2_FB14_Pos (14U) |
| 9148 | #define CAN_F0R2_FB14_Pos (14U) |
9148 | #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ |
| 9149 | #define CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos) /*!< 0x00004000 */ |
9149 | #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */ |
| 9150 | #define CAN_F0R2_FB14 CAN_F0R2_FB14_Msk /*!< Filter bit 14 */ |
9150 | #define CAN_F0R2_FB15_Pos (15U) |
| 9151 | #define CAN_F0R2_FB15_Pos (15U) |
9151 | #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ |
| 9152 | #define CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos) /*!< 0x00008000 */ |
9152 | #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */ |
| 9153 | #define CAN_F0R2_FB15 CAN_F0R2_FB15_Msk /*!< Filter bit 15 */ |
9153 | #define CAN_F0R2_FB16_Pos (16U) |
| 9154 | #define CAN_F0R2_FB16_Pos (16U) |
9154 | #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ |
| 9155 | #define CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos) /*!< 0x00010000 */ |
9155 | #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */ |
| 9156 | #define CAN_F0R2_FB16 CAN_F0R2_FB16_Msk /*!< Filter bit 16 */ |
9156 | #define CAN_F0R2_FB17_Pos (17U) |
| 9157 | #define CAN_F0R2_FB17_Pos (17U) |
9157 | #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ |
| 9158 | #define CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos) /*!< 0x00020000 */ |
9158 | #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */ |
| 9159 | #define CAN_F0R2_FB17 CAN_F0R2_FB17_Msk /*!< Filter bit 17 */ |
9159 | #define CAN_F0R2_FB18_Pos (18U) |
| 9160 | #define CAN_F0R2_FB18_Pos (18U) |
9160 | #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ |
| 9161 | #define CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos) /*!< 0x00040000 */ |
9161 | #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */ |
| 9162 | #define CAN_F0R2_FB18 CAN_F0R2_FB18_Msk /*!< Filter bit 18 */ |
9162 | #define CAN_F0R2_FB19_Pos (19U) |
| 9163 | #define CAN_F0R2_FB19_Pos (19U) |
9163 | #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ |
| 9164 | #define CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos) /*!< 0x00080000 */ |
9164 | #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */ |
| 9165 | #define CAN_F0R2_FB19 CAN_F0R2_FB19_Msk /*!< Filter bit 19 */ |
9165 | #define CAN_F0R2_FB20_Pos (20U) |
| 9166 | #define CAN_F0R2_FB20_Pos (20U) |
9166 | #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ |
| 9167 | #define CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos) /*!< 0x00100000 */ |
9167 | #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */ |
| 9168 | #define CAN_F0R2_FB20 CAN_F0R2_FB20_Msk /*!< Filter bit 20 */ |
9168 | #define CAN_F0R2_FB21_Pos (21U) |
| 9169 | #define CAN_F0R2_FB21_Pos (21U) |
9169 | #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ |
| 9170 | #define CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos) /*!< 0x00200000 */ |
9170 | #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */ |
| 9171 | #define CAN_F0R2_FB21 CAN_F0R2_FB21_Msk /*!< Filter bit 21 */ |
9171 | #define CAN_F0R2_FB22_Pos (22U) |
| 9172 | #define CAN_F0R2_FB22_Pos (22U) |
9172 | #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ |
| 9173 | #define CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos) /*!< 0x00400000 */ |
9173 | #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */ |
| 9174 | #define CAN_F0R2_FB22 CAN_F0R2_FB22_Msk /*!< Filter bit 22 */ |
9174 | #define CAN_F0R2_FB23_Pos (23U) |
| 9175 | #define CAN_F0R2_FB23_Pos (23U) |
9175 | #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ |
| 9176 | #define CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos) /*!< 0x00800000 */ |
9176 | #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */ |
| 9177 | #define CAN_F0R2_FB23 CAN_F0R2_FB23_Msk /*!< Filter bit 23 */ |
9177 | #define CAN_F0R2_FB24_Pos (24U) |
| 9178 | #define CAN_F0R2_FB24_Pos (24U) |
9178 | #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ |
| 9179 | #define CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos) /*!< 0x01000000 */ |
9179 | #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */ |
| 9180 | #define CAN_F0R2_FB24 CAN_F0R2_FB24_Msk /*!< Filter bit 24 */ |
9180 | #define CAN_F0R2_FB25_Pos (25U) |
| 9181 | #define CAN_F0R2_FB25_Pos (25U) |
9181 | #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ |
| 9182 | #define CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos) /*!< 0x02000000 */ |
9182 | #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */ |
| 9183 | #define CAN_F0R2_FB25 CAN_F0R2_FB25_Msk /*!< Filter bit 25 */ |
9183 | #define CAN_F0R2_FB26_Pos (26U) |
| 9184 | #define CAN_F0R2_FB26_Pos (26U) |
9184 | #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ |
| 9185 | #define CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos) /*!< 0x04000000 */ |
9185 | #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */ |
| 9186 | #define CAN_F0R2_FB26 CAN_F0R2_FB26_Msk /*!< Filter bit 26 */ |
9186 | #define CAN_F0R2_FB27_Pos (27U) |
| 9187 | #define CAN_F0R2_FB27_Pos (27U) |
9187 | #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ |
| 9188 | #define CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos) /*!< 0x08000000 */ |
9188 | #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */ |
| 9189 | #define CAN_F0R2_FB27 CAN_F0R2_FB27_Msk /*!< Filter bit 27 */ |
9189 | #define CAN_F0R2_FB28_Pos (28U) |
| 9190 | #define CAN_F0R2_FB28_Pos (28U) |
9190 | #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ |
| 9191 | #define CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos) /*!< 0x10000000 */ |
9191 | #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */ |
| 9192 | #define CAN_F0R2_FB28 CAN_F0R2_FB28_Msk /*!< Filter bit 28 */ |
9192 | #define CAN_F0R2_FB29_Pos (29U) |
| 9193 | #define CAN_F0R2_FB29_Pos (29U) |
9193 | #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ |
| 9194 | #define CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos) /*!< 0x20000000 */ |
9194 | #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */ |
| 9195 | #define CAN_F0R2_FB29 CAN_F0R2_FB29_Msk /*!< Filter bit 29 */ |
9195 | #define CAN_F0R2_FB30_Pos (30U) |
| 9196 | #define CAN_F0R2_FB30_Pos (30U) |
9196 | #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ |
| 9197 | #define CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos) /*!< 0x40000000 */ |
9197 | #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */ |
| 9198 | #define CAN_F0R2_FB30 CAN_F0R2_FB30_Msk /*!< Filter bit 30 */ |
9198 | #define CAN_F0R2_FB31_Pos (31U) |
| 9199 | #define CAN_F0R2_FB31_Pos (31U) |
9199 | #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ |
| 9200 | #define CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos) /*!< 0x80000000 */ |
9200 | #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */ |
| 9201 | #define CAN_F0R2_FB31 CAN_F0R2_FB31_Msk /*!< Filter bit 31 */ |
9201 | |
| 9202 | 9202 | /******************* Bit definition for CAN_F1R2 register *******************/ |
|
| 9203 | /******************* Bit definition for CAN_F1R2 register *******************/ |
9203 | #define CAN_F1R2_FB0_Pos (0U) |
| 9204 | #define CAN_F1R2_FB0_Pos (0U) |
9204 | #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ |
| 9205 | #define CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos) /*!< 0x00000001 */ |
9205 | #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */ |
| 9206 | #define CAN_F1R2_FB0 CAN_F1R2_FB0_Msk /*!< Filter bit 0 */ |
9206 | #define CAN_F1R2_FB1_Pos (1U) |
| 9207 | #define CAN_F1R2_FB1_Pos (1U) |
9207 | #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ |
| 9208 | #define CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos) /*!< 0x00000002 */ |
9208 | #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */ |
| 9209 | #define CAN_F1R2_FB1 CAN_F1R2_FB1_Msk /*!< Filter bit 1 */ |
9209 | #define CAN_F1R2_FB2_Pos (2U) |
| 9210 | #define CAN_F1R2_FB2_Pos (2U) |
9210 | #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ |
| 9211 | #define CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos) /*!< 0x00000004 */ |
9211 | #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */ |
| 9212 | #define CAN_F1R2_FB2 CAN_F1R2_FB2_Msk /*!< Filter bit 2 */ |
9212 | #define CAN_F1R2_FB3_Pos (3U) |
| 9213 | #define CAN_F1R2_FB3_Pos (3U) |
9213 | #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ |
| 9214 | #define CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos) /*!< 0x00000008 */ |
9214 | #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */ |
| 9215 | #define CAN_F1R2_FB3 CAN_F1R2_FB3_Msk /*!< Filter bit 3 */ |
9215 | #define CAN_F1R2_FB4_Pos (4U) |
| 9216 | #define CAN_F1R2_FB4_Pos (4U) |
9216 | #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ |
| 9217 | #define CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos) /*!< 0x00000010 */ |
9217 | #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */ |
| 9218 | #define CAN_F1R2_FB4 CAN_F1R2_FB4_Msk /*!< Filter bit 4 */ |
9218 | #define CAN_F1R2_FB5_Pos (5U) |
| 9219 | #define CAN_F1R2_FB5_Pos (5U) |
9219 | #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ |
| 9220 | #define CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos) /*!< 0x00000020 */ |
9220 | #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */ |
| 9221 | #define CAN_F1R2_FB5 CAN_F1R2_FB5_Msk /*!< Filter bit 5 */ |
9221 | #define CAN_F1R2_FB6_Pos (6U) |
| 9222 | #define CAN_F1R2_FB6_Pos (6U) |
9222 | #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ |
| 9223 | #define CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos) /*!< 0x00000040 */ |
9223 | #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */ |
| 9224 | #define CAN_F1R2_FB6 CAN_F1R2_FB6_Msk /*!< Filter bit 6 */ |
9224 | #define CAN_F1R2_FB7_Pos (7U) |
| 9225 | #define CAN_F1R2_FB7_Pos (7U) |
9225 | #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ |
| 9226 | #define CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos) /*!< 0x00000080 */ |
9226 | #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */ |
| 9227 | #define CAN_F1R2_FB7 CAN_F1R2_FB7_Msk /*!< Filter bit 7 */ |
9227 | #define CAN_F1R2_FB8_Pos (8U) |
| 9228 | #define CAN_F1R2_FB8_Pos (8U) |
9228 | #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ |
| 9229 | #define CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos) /*!< 0x00000100 */ |
9229 | #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */ |
| 9230 | #define CAN_F1R2_FB8 CAN_F1R2_FB8_Msk /*!< Filter bit 8 */ |
9230 | #define CAN_F1R2_FB9_Pos (9U) |
| 9231 | #define CAN_F1R2_FB9_Pos (9U) |
9231 | #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ |
| 9232 | #define CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos) /*!< 0x00000200 */ |
9232 | #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */ |
| 9233 | #define CAN_F1R2_FB9 CAN_F1R2_FB9_Msk /*!< Filter bit 9 */ |
9233 | #define CAN_F1R2_FB10_Pos (10U) |
| 9234 | #define CAN_F1R2_FB10_Pos (10U) |
9234 | #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ |
| 9235 | #define CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos) /*!< 0x00000400 */ |
9235 | #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */ |
| 9236 | #define CAN_F1R2_FB10 CAN_F1R2_FB10_Msk /*!< Filter bit 10 */ |
9236 | #define CAN_F1R2_FB11_Pos (11U) |
| 9237 | #define CAN_F1R2_FB11_Pos (11U) |
9237 | #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ |
| 9238 | #define CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos) /*!< 0x00000800 */ |
9238 | #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */ |
| 9239 | #define CAN_F1R2_FB11 CAN_F1R2_FB11_Msk /*!< Filter bit 11 */ |
9239 | #define CAN_F1R2_FB12_Pos (12U) |
| 9240 | #define CAN_F1R2_FB12_Pos (12U) |
9240 | #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ |
| 9241 | #define CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos) /*!< 0x00001000 */ |
9241 | #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */ |
| 9242 | #define CAN_F1R2_FB12 CAN_F1R2_FB12_Msk /*!< Filter bit 12 */ |
9242 | #define CAN_F1R2_FB13_Pos (13U) |
| 9243 | #define CAN_F1R2_FB13_Pos (13U) |
9243 | #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ |
| 9244 | #define CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos) /*!< 0x00002000 */ |
9244 | #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */ |
| 9245 | #define CAN_F1R2_FB13 CAN_F1R2_FB13_Msk /*!< Filter bit 13 */ |
9245 | #define CAN_F1R2_FB14_Pos (14U) |
| 9246 | #define CAN_F1R2_FB14_Pos (14U) |
9246 | #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ |
| 9247 | #define CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos) /*!< 0x00004000 */ |
9247 | #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */ |
| 9248 | #define CAN_F1R2_FB14 CAN_F1R2_FB14_Msk /*!< Filter bit 14 */ |
9248 | #define CAN_F1R2_FB15_Pos (15U) |
| 9249 | #define CAN_F1R2_FB15_Pos (15U) |
9249 | #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ |
| 9250 | #define CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos) /*!< 0x00008000 */ |
9250 | #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */ |
| 9251 | #define CAN_F1R2_FB15 CAN_F1R2_FB15_Msk /*!< Filter bit 15 */ |
9251 | #define CAN_F1R2_FB16_Pos (16U) |
| 9252 | #define CAN_F1R2_FB16_Pos (16U) |
9252 | #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ |
| 9253 | #define CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos) /*!< 0x00010000 */ |
9253 | #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */ |
| 9254 | #define CAN_F1R2_FB16 CAN_F1R2_FB16_Msk /*!< Filter bit 16 */ |
9254 | #define CAN_F1R2_FB17_Pos (17U) |
| 9255 | #define CAN_F1R2_FB17_Pos (17U) |
9255 | #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ |
| 9256 | #define CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos) /*!< 0x00020000 */ |
9256 | #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */ |
| 9257 | #define CAN_F1R2_FB17 CAN_F1R2_FB17_Msk /*!< Filter bit 17 */ |
9257 | #define CAN_F1R2_FB18_Pos (18U) |
| 9258 | #define CAN_F1R2_FB18_Pos (18U) |
9258 | #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ |
| 9259 | #define CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos) /*!< 0x00040000 */ |
9259 | #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */ |
| 9260 | #define CAN_F1R2_FB18 CAN_F1R2_FB18_Msk /*!< Filter bit 18 */ |
9260 | #define CAN_F1R2_FB19_Pos (19U) |
| 9261 | #define CAN_F1R2_FB19_Pos (19U) |
9261 | #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ |
| 9262 | #define CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos) /*!< 0x00080000 */ |
9262 | #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */ |
| 9263 | #define CAN_F1R2_FB19 CAN_F1R2_FB19_Msk /*!< Filter bit 19 */ |
9263 | #define CAN_F1R2_FB20_Pos (20U) |
| 9264 | #define CAN_F1R2_FB20_Pos (20U) |
9264 | #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ |
| 9265 | #define CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos) /*!< 0x00100000 */ |
9265 | #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */ |
| 9266 | #define CAN_F1R2_FB20 CAN_F1R2_FB20_Msk /*!< Filter bit 20 */ |
9266 | #define CAN_F1R2_FB21_Pos (21U) |
| 9267 | #define CAN_F1R2_FB21_Pos (21U) |
9267 | #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ |
| 9268 | #define CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos) /*!< 0x00200000 */ |
9268 | #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */ |
| 9269 | #define CAN_F1R2_FB21 CAN_F1R2_FB21_Msk /*!< Filter bit 21 */ |
9269 | #define CAN_F1R2_FB22_Pos (22U) |
| 9270 | #define CAN_F1R2_FB22_Pos (22U) |
9270 | #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ |
| 9271 | #define CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos) /*!< 0x00400000 */ |
9271 | #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */ |
| 9272 | #define CAN_F1R2_FB22 CAN_F1R2_FB22_Msk /*!< Filter bit 22 */ |
9272 | #define CAN_F1R2_FB23_Pos (23U) |
| 9273 | #define CAN_F1R2_FB23_Pos (23U) |
9273 | #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ |
| 9274 | #define CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos) /*!< 0x00800000 */ |
9274 | #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */ |
| 9275 | #define CAN_F1R2_FB23 CAN_F1R2_FB23_Msk /*!< Filter bit 23 */ |
9275 | #define CAN_F1R2_FB24_Pos (24U) |
| 9276 | #define CAN_F1R2_FB24_Pos (24U) |
9276 | #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ |
| 9277 | #define CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos) /*!< 0x01000000 */ |
9277 | #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */ |
| 9278 | #define CAN_F1R2_FB24 CAN_F1R2_FB24_Msk /*!< Filter bit 24 */ |
9278 | #define CAN_F1R2_FB25_Pos (25U) |
| 9279 | #define CAN_F1R2_FB25_Pos (25U) |
9279 | #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ |
| 9280 | #define CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos) /*!< 0x02000000 */ |
9280 | #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */ |
| 9281 | #define CAN_F1R2_FB25 CAN_F1R2_FB25_Msk /*!< Filter bit 25 */ |
9281 | #define CAN_F1R2_FB26_Pos (26U) |
| 9282 | #define CAN_F1R2_FB26_Pos (26U) |
9282 | #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ |
| 9283 | #define CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos) /*!< 0x04000000 */ |
9283 | #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */ |
| 9284 | #define CAN_F1R2_FB26 CAN_F1R2_FB26_Msk /*!< Filter bit 26 */ |
9284 | #define CAN_F1R2_FB27_Pos (27U) |
| 9285 | #define CAN_F1R2_FB27_Pos (27U) |
9285 | #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ |
| 9286 | #define CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos) /*!< 0x08000000 */ |
9286 | #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */ |
| 9287 | #define CAN_F1R2_FB27 CAN_F1R2_FB27_Msk /*!< Filter bit 27 */ |
9287 | #define CAN_F1R2_FB28_Pos (28U) |
| 9288 | #define CAN_F1R2_FB28_Pos (28U) |
9288 | #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ |
| 9289 | #define CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos) /*!< 0x10000000 */ |
9289 | #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */ |
| 9290 | #define CAN_F1R2_FB28 CAN_F1R2_FB28_Msk /*!< Filter bit 28 */ |
9290 | #define CAN_F1R2_FB29_Pos (29U) |
| 9291 | #define CAN_F1R2_FB29_Pos (29U) |
9291 | #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ |
| 9292 | #define CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos) /*!< 0x20000000 */ |
9292 | #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */ |
| 9293 | #define CAN_F1R2_FB29 CAN_F1R2_FB29_Msk /*!< Filter bit 29 */ |
9293 | #define CAN_F1R2_FB30_Pos (30U) |
| 9294 | #define CAN_F1R2_FB30_Pos (30U) |
9294 | #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ |
| 9295 | #define CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos) /*!< 0x40000000 */ |
9295 | #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */ |
| 9296 | #define CAN_F1R2_FB30 CAN_F1R2_FB30_Msk /*!< Filter bit 30 */ |
9296 | #define CAN_F1R2_FB31_Pos (31U) |
| 9297 | #define CAN_F1R2_FB31_Pos (31U) |
9297 | #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ |
| 9298 | #define CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos) /*!< 0x80000000 */ |
9298 | #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */ |
| 9299 | #define CAN_F1R2_FB31 CAN_F1R2_FB31_Msk /*!< Filter bit 31 */ |
9299 | |
| 9300 | 9300 | /******************* Bit definition for CAN_F2R2 register *******************/ |
|
| 9301 | /******************* Bit definition for CAN_F2R2 register *******************/ |
9301 | #define CAN_F2R2_FB0_Pos (0U) |
| 9302 | #define CAN_F2R2_FB0_Pos (0U) |
9302 | #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ |
| 9303 | #define CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos) /*!< 0x00000001 */ |
9303 | #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */ |
| 9304 | #define CAN_F2R2_FB0 CAN_F2R2_FB0_Msk /*!< Filter bit 0 */ |
9304 | #define CAN_F2R2_FB1_Pos (1U) |
| 9305 | #define CAN_F2R2_FB1_Pos (1U) |
9305 | #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ |
| 9306 | #define CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos) /*!< 0x00000002 */ |
9306 | #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */ |
| 9307 | #define CAN_F2R2_FB1 CAN_F2R2_FB1_Msk /*!< Filter bit 1 */ |
9307 | #define CAN_F2R2_FB2_Pos (2U) |
| 9308 | #define CAN_F2R2_FB2_Pos (2U) |
9308 | #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ |
| 9309 | #define CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos) /*!< 0x00000004 */ |
9309 | #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */ |
| 9310 | #define CAN_F2R2_FB2 CAN_F2R2_FB2_Msk /*!< Filter bit 2 */ |
9310 | #define CAN_F2R2_FB3_Pos (3U) |
| 9311 | #define CAN_F2R2_FB3_Pos (3U) |
9311 | #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ |
| 9312 | #define CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos) /*!< 0x00000008 */ |
9312 | #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */ |
| 9313 | #define CAN_F2R2_FB3 CAN_F2R2_FB3_Msk /*!< Filter bit 3 */ |
9313 | #define CAN_F2R2_FB4_Pos (4U) |
| 9314 | #define CAN_F2R2_FB4_Pos (4U) |
9314 | #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ |
| 9315 | #define CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos) /*!< 0x00000010 */ |
9315 | #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */ |
| 9316 | #define CAN_F2R2_FB4 CAN_F2R2_FB4_Msk /*!< Filter bit 4 */ |
9316 | #define CAN_F2R2_FB5_Pos (5U) |
| 9317 | #define CAN_F2R2_FB5_Pos (5U) |
9317 | #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ |
| 9318 | #define CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos) /*!< 0x00000020 */ |
9318 | #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */ |
| 9319 | #define CAN_F2R2_FB5 CAN_F2R2_FB5_Msk /*!< Filter bit 5 */ |
9319 | #define CAN_F2R2_FB6_Pos (6U) |
| 9320 | #define CAN_F2R2_FB6_Pos (6U) |
9320 | #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ |
| 9321 | #define CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos) /*!< 0x00000040 */ |
9321 | #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */ |
| 9322 | #define CAN_F2R2_FB6 CAN_F2R2_FB6_Msk /*!< Filter bit 6 */ |
9322 | #define CAN_F2R2_FB7_Pos (7U) |
| 9323 | #define CAN_F2R2_FB7_Pos (7U) |
9323 | #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ |
| 9324 | #define CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos) /*!< 0x00000080 */ |
9324 | #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */ |
| 9325 | #define CAN_F2R2_FB7 CAN_F2R2_FB7_Msk /*!< Filter bit 7 */ |
9325 | #define CAN_F2R2_FB8_Pos (8U) |
| 9326 | #define CAN_F2R2_FB8_Pos (8U) |
9326 | #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ |
| 9327 | #define CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos) /*!< 0x00000100 */ |
9327 | #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */ |
| 9328 | #define CAN_F2R2_FB8 CAN_F2R2_FB8_Msk /*!< Filter bit 8 */ |
9328 | #define CAN_F2R2_FB9_Pos (9U) |
| 9329 | #define CAN_F2R2_FB9_Pos (9U) |
9329 | #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ |
| 9330 | #define CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos) /*!< 0x00000200 */ |
9330 | #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */ |
| 9331 | #define CAN_F2R2_FB9 CAN_F2R2_FB9_Msk /*!< Filter bit 9 */ |
9331 | #define CAN_F2R2_FB10_Pos (10U) |
| 9332 | #define CAN_F2R2_FB10_Pos (10U) |
9332 | #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ |
| 9333 | #define CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos) /*!< 0x00000400 */ |
9333 | #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */ |
| 9334 | #define CAN_F2R2_FB10 CAN_F2R2_FB10_Msk /*!< Filter bit 10 */ |
9334 | #define CAN_F2R2_FB11_Pos (11U) |
| 9335 | #define CAN_F2R2_FB11_Pos (11U) |
9335 | #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ |
| 9336 | #define CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos) /*!< 0x00000800 */ |
9336 | #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */ |
| 9337 | #define CAN_F2R2_FB11 CAN_F2R2_FB11_Msk /*!< Filter bit 11 */ |
9337 | #define CAN_F2R2_FB12_Pos (12U) |
| 9338 | #define CAN_F2R2_FB12_Pos (12U) |
9338 | #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ |
| 9339 | #define CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos) /*!< 0x00001000 */ |
9339 | #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */ |
| 9340 | #define CAN_F2R2_FB12 CAN_F2R2_FB12_Msk /*!< Filter bit 12 */ |
9340 | #define CAN_F2R2_FB13_Pos (13U) |
| 9341 | #define CAN_F2R2_FB13_Pos (13U) |
9341 | #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ |
| 9342 | #define CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos) /*!< 0x00002000 */ |
9342 | #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */ |
| 9343 | #define CAN_F2R2_FB13 CAN_F2R2_FB13_Msk /*!< Filter bit 13 */ |
9343 | #define CAN_F2R2_FB14_Pos (14U) |
| 9344 | #define CAN_F2R2_FB14_Pos (14U) |
9344 | #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ |
| 9345 | #define CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos) /*!< 0x00004000 */ |
9345 | #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */ |
| 9346 | #define CAN_F2R2_FB14 CAN_F2R2_FB14_Msk /*!< Filter bit 14 */ |
9346 | #define CAN_F2R2_FB15_Pos (15U) |
| 9347 | #define CAN_F2R2_FB15_Pos (15U) |
9347 | #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ |
| 9348 | #define CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos) /*!< 0x00008000 */ |
9348 | #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */ |
| 9349 | #define CAN_F2R2_FB15 CAN_F2R2_FB15_Msk /*!< Filter bit 15 */ |
9349 | #define CAN_F2R2_FB16_Pos (16U) |
| 9350 | #define CAN_F2R2_FB16_Pos (16U) |
9350 | #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ |
| 9351 | #define CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos) /*!< 0x00010000 */ |
9351 | #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */ |
| 9352 | #define CAN_F2R2_FB16 CAN_F2R2_FB16_Msk /*!< Filter bit 16 */ |
9352 | #define CAN_F2R2_FB17_Pos (17U) |
| 9353 | #define CAN_F2R2_FB17_Pos (17U) |
9353 | #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ |
| 9354 | #define CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos) /*!< 0x00020000 */ |
9354 | #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */ |
| 9355 | #define CAN_F2R2_FB17 CAN_F2R2_FB17_Msk /*!< Filter bit 17 */ |
9355 | #define CAN_F2R2_FB18_Pos (18U) |
| 9356 | #define CAN_F2R2_FB18_Pos (18U) |
9356 | #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ |
| 9357 | #define CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos) /*!< 0x00040000 */ |
9357 | #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */ |
| 9358 | #define CAN_F2R2_FB18 CAN_F2R2_FB18_Msk /*!< Filter bit 18 */ |
9358 | #define CAN_F2R2_FB19_Pos (19U) |
| 9359 | #define CAN_F2R2_FB19_Pos (19U) |
9359 | #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ |
| 9360 | #define CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos) /*!< 0x00080000 */ |
9360 | #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */ |
| 9361 | #define CAN_F2R2_FB19 CAN_F2R2_FB19_Msk /*!< Filter bit 19 */ |
9361 | #define CAN_F2R2_FB20_Pos (20U) |
| 9362 | #define CAN_F2R2_FB20_Pos (20U) |
9362 | #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ |
| 9363 | #define CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos) /*!< 0x00100000 */ |
9363 | #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */ |
| 9364 | #define CAN_F2R2_FB20 CAN_F2R2_FB20_Msk /*!< Filter bit 20 */ |
9364 | #define CAN_F2R2_FB21_Pos (21U) |
| 9365 | #define CAN_F2R2_FB21_Pos (21U) |
9365 | #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ |
| 9366 | #define CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos) /*!< 0x00200000 */ |
9366 | #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */ |
| 9367 | #define CAN_F2R2_FB21 CAN_F2R2_FB21_Msk /*!< Filter bit 21 */ |
9367 | #define CAN_F2R2_FB22_Pos (22U) |
| 9368 | #define CAN_F2R2_FB22_Pos (22U) |
9368 | #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ |
| 9369 | #define CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos) /*!< 0x00400000 */ |
9369 | #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */ |
| 9370 | #define CAN_F2R2_FB22 CAN_F2R2_FB22_Msk /*!< Filter bit 22 */ |
9370 | #define CAN_F2R2_FB23_Pos (23U) |
| 9371 | #define CAN_F2R2_FB23_Pos (23U) |
9371 | #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ |
| 9372 | #define CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos) /*!< 0x00800000 */ |
9372 | #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */ |
| 9373 | #define CAN_F2R2_FB23 CAN_F2R2_FB23_Msk /*!< Filter bit 23 */ |
9373 | #define CAN_F2R2_FB24_Pos (24U) |
| 9374 | #define CAN_F2R2_FB24_Pos (24U) |
9374 | #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ |
| 9375 | #define CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos) /*!< 0x01000000 */ |
9375 | #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */ |
| 9376 | #define CAN_F2R2_FB24 CAN_F2R2_FB24_Msk /*!< Filter bit 24 */ |
9376 | #define CAN_F2R2_FB25_Pos (25U) |
| 9377 | #define CAN_F2R2_FB25_Pos (25U) |
9377 | #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ |
| 9378 | #define CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos) /*!< 0x02000000 */ |
9378 | #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */ |
| 9379 | #define CAN_F2R2_FB25 CAN_F2R2_FB25_Msk /*!< Filter bit 25 */ |
9379 | #define CAN_F2R2_FB26_Pos (26U) |
| 9380 | #define CAN_F2R2_FB26_Pos (26U) |
9380 | #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ |
| 9381 | #define CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos) /*!< 0x04000000 */ |
9381 | #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */ |
| 9382 | #define CAN_F2R2_FB26 CAN_F2R2_FB26_Msk /*!< Filter bit 26 */ |
9382 | #define CAN_F2R2_FB27_Pos (27U) |
| 9383 | #define CAN_F2R2_FB27_Pos (27U) |
9383 | #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ |
| 9384 | #define CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos) /*!< 0x08000000 */ |
9384 | #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */ |
| 9385 | #define CAN_F2R2_FB27 CAN_F2R2_FB27_Msk /*!< Filter bit 27 */ |
9385 | #define CAN_F2R2_FB28_Pos (28U) |
| 9386 | #define CAN_F2R2_FB28_Pos (28U) |
9386 | #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ |
| 9387 | #define CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos) /*!< 0x10000000 */ |
9387 | #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */ |
| 9388 | #define CAN_F2R2_FB28 CAN_F2R2_FB28_Msk /*!< Filter bit 28 */ |
9388 | #define CAN_F2R2_FB29_Pos (29U) |
| 9389 | #define CAN_F2R2_FB29_Pos (29U) |
9389 | #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ |
| 9390 | #define CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos) /*!< 0x20000000 */ |
9390 | #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */ |
| 9391 | #define CAN_F2R2_FB29 CAN_F2R2_FB29_Msk /*!< Filter bit 29 */ |
9391 | #define CAN_F2R2_FB30_Pos (30U) |
| 9392 | #define CAN_F2R2_FB30_Pos (30U) |
9392 | #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ |
| 9393 | #define CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos) /*!< 0x40000000 */ |
9393 | #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */ |
| 9394 | #define CAN_F2R2_FB30 CAN_F2R2_FB30_Msk /*!< Filter bit 30 */ |
9394 | #define CAN_F2R2_FB31_Pos (31U) |
| 9395 | #define CAN_F2R2_FB31_Pos (31U) |
9395 | #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ |
| 9396 | #define CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos) /*!< 0x80000000 */ |
9396 | #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */ |
| 9397 | #define CAN_F2R2_FB31 CAN_F2R2_FB31_Msk /*!< Filter bit 31 */ |
9397 | |
| 9398 | 9398 | /******************* Bit definition for CAN_F3R2 register *******************/ |
|
| 9399 | /******************* Bit definition for CAN_F3R2 register *******************/ |
9399 | #define CAN_F3R2_FB0_Pos (0U) |
| 9400 | #define CAN_F3R2_FB0_Pos (0U) |
9400 | #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ |
| 9401 | #define CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos) /*!< 0x00000001 */ |
9401 | #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */ |
| 9402 | #define CAN_F3R2_FB0 CAN_F3R2_FB0_Msk /*!< Filter bit 0 */ |
9402 | #define CAN_F3R2_FB1_Pos (1U) |
| 9403 | #define CAN_F3R2_FB1_Pos (1U) |
9403 | #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ |
| 9404 | #define CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos) /*!< 0x00000002 */ |
9404 | #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */ |
| 9405 | #define CAN_F3R2_FB1 CAN_F3R2_FB1_Msk /*!< Filter bit 1 */ |
9405 | #define CAN_F3R2_FB2_Pos (2U) |
| 9406 | #define CAN_F3R2_FB2_Pos (2U) |
9406 | #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ |
| 9407 | #define CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos) /*!< 0x00000004 */ |
9407 | #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */ |
| 9408 | #define CAN_F3R2_FB2 CAN_F3R2_FB2_Msk /*!< Filter bit 2 */ |
9408 | #define CAN_F3R2_FB3_Pos (3U) |
| 9409 | #define CAN_F3R2_FB3_Pos (3U) |
9409 | #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ |
| 9410 | #define CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos) /*!< 0x00000008 */ |
9410 | #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */ |
| 9411 | #define CAN_F3R2_FB3 CAN_F3R2_FB3_Msk /*!< Filter bit 3 */ |
9411 | #define CAN_F3R2_FB4_Pos (4U) |
| 9412 | #define CAN_F3R2_FB4_Pos (4U) |
9412 | #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ |
| 9413 | #define CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos) /*!< 0x00000010 */ |
9413 | #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */ |
| 9414 | #define CAN_F3R2_FB4 CAN_F3R2_FB4_Msk /*!< Filter bit 4 */ |
9414 | #define CAN_F3R2_FB5_Pos (5U) |
| 9415 | #define CAN_F3R2_FB5_Pos (5U) |
9415 | #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ |
| 9416 | #define CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos) /*!< 0x00000020 */ |
9416 | #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */ |
| 9417 | #define CAN_F3R2_FB5 CAN_F3R2_FB5_Msk /*!< Filter bit 5 */ |
9417 | #define CAN_F3R2_FB6_Pos (6U) |
| 9418 | #define CAN_F3R2_FB6_Pos (6U) |
9418 | #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ |
| 9419 | #define CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos) /*!< 0x00000040 */ |
9419 | #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */ |
| 9420 | #define CAN_F3R2_FB6 CAN_F3R2_FB6_Msk /*!< Filter bit 6 */ |
9420 | #define CAN_F3R2_FB7_Pos (7U) |
| 9421 | #define CAN_F3R2_FB7_Pos (7U) |
9421 | #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ |
| 9422 | #define CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos) /*!< 0x00000080 */ |
9422 | #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */ |
| 9423 | #define CAN_F3R2_FB7 CAN_F3R2_FB7_Msk /*!< Filter bit 7 */ |
9423 | #define CAN_F3R2_FB8_Pos (8U) |
| 9424 | #define CAN_F3R2_FB8_Pos (8U) |
9424 | #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ |
| 9425 | #define CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos) /*!< 0x00000100 */ |
9425 | #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */ |
| 9426 | #define CAN_F3R2_FB8 CAN_F3R2_FB8_Msk /*!< Filter bit 8 */ |
9426 | #define CAN_F3R2_FB9_Pos (9U) |
| 9427 | #define CAN_F3R2_FB9_Pos (9U) |
9427 | #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ |
| 9428 | #define CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos) /*!< 0x00000200 */ |
9428 | #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */ |
| 9429 | #define CAN_F3R2_FB9 CAN_F3R2_FB9_Msk /*!< Filter bit 9 */ |
9429 | #define CAN_F3R2_FB10_Pos (10U) |
| 9430 | #define CAN_F3R2_FB10_Pos (10U) |
9430 | #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ |
| 9431 | #define CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos) /*!< 0x00000400 */ |
9431 | #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */ |
| 9432 | #define CAN_F3R2_FB10 CAN_F3R2_FB10_Msk /*!< Filter bit 10 */ |
9432 | #define CAN_F3R2_FB11_Pos (11U) |
| 9433 | #define CAN_F3R2_FB11_Pos (11U) |
9433 | #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ |
| 9434 | #define CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos) /*!< 0x00000800 */ |
9434 | #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */ |
| 9435 | #define CAN_F3R2_FB11 CAN_F3R2_FB11_Msk /*!< Filter bit 11 */ |
9435 | #define CAN_F3R2_FB12_Pos (12U) |
| 9436 | #define CAN_F3R2_FB12_Pos (12U) |
9436 | #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ |
| 9437 | #define CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos) /*!< 0x00001000 */ |
9437 | #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */ |
| 9438 | #define CAN_F3R2_FB12 CAN_F3R2_FB12_Msk /*!< Filter bit 12 */ |
9438 | #define CAN_F3R2_FB13_Pos (13U) |
| 9439 | #define CAN_F3R2_FB13_Pos (13U) |
9439 | #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ |
| 9440 | #define CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos) /*!< 0x00002000 */ |
9440 | #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */ |
| 9441 | #define CAN_F3R2_FB13 CAN_F3R2_FB13_Msk /*!< Filter bit 13 */ |
9441 | #define CAN_F3R2_FB14_Pos (14U) |
| 9442 | #define CAN_F3R2_FB14_Pos (14U) |
9442 | #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ |
| 9443 | #define CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos) /*!< 0x00004000 */ |
9443 | #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */ |
| 9444 | #define CAN_F3R2_FB14 CAN_F3R2_FB14_Msk /*!< Filter bit 14 */ |
9444 | #define CAN_F3R2_FB15_Pos (15U) |
| 9445 | #define CAN_F3R2_FB15_Pos (15U) |
9445 | #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ |
| 9446 | #define CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos) /*!< 0x00008000 */ |
9446 | #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */ |
| 9447 | #define CAN_F3R2_FB15 CAN_F3R2_FB15_Msk /*!< Filter bit 15 */ |
9447 | #define CAN_F3R2_FB16_Pos (16U) |
| 9448 | #define CAN_F3R2_FB16_Pos (16U) |
9448 | #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ |
| 9449 | #define CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos) /*!< 0x00010000 */ |
9449 | #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */ |
| 9450 | #define CAN_F3R2_FB16 CAN_F3R2_FB16_Msk /*!< Filter bit 16 */ |
9450 | #define CAN_F3R2_FB17_Pos (17U) |
| 9451 | #define CAN_F3R2_FB17_Pos (17U) |
9451 | #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ |
| 9452 | #define CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos) /*!< 0x00020000 */ |
9452 | #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */ |
| 9453 | #define CAN_F3R2_FB17 CAN_F3R2_FB17_Msk /*!< Filter bit 17 */ |
9453 | #define CAN_F3R2_FB18_Pos (18U) |
| 9454 | #define CAN_F3R2_FB18_Pos (18U) |
9454 | #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ |
| 9455 | #define CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos) /*!< 0x00040000 */ |
9455 | #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */ |
| 9456 | #define CAN_F3R2_FB18 CAN_F3R2_FB18_Msk /*!< Filter bit 18 */ |
9456 | #define CAN_F3R2_FB19_Pos (19U) |
| 9457 | #define CAN_F3R2_FB19_Pos (19U) |
9457 | #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ |
| 9458 | #define CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos) /*!< 0x00080000 */ |
9458 | #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */ |
| 9459 | #define CAN_F3R2_FB19 CAN_F3R2_FB19_Msk /*!< Filter bit 19 */ |
9459 | #define CAN_F3R2_FB20_Pos (20U) |
| 9460 | #define CAN_F3R2_FB20_Pos (20U) |
9460 | #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ |
| 9461 | #define CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos) /*!< 0x00100000 */ |
9461 | #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */ |
| 9462 | #define CAN_F3R2_FB20 CAN_F3R2_FB20_Msk /*!< Filter bit 20 */ |
9462 | #define CAN_F3R2_FB21_Pos (21U) |
| 9463 | #define CAN_F3R2_FB21_Pos (21U) |
9463 | #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ |
| 9464 | #define CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos) /*!< 0x00200000 */ |
9464 | #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */ |
| 9465 | #define CAN_F3R2_FB21 CAN_F3R2_FB21_Msk /*!< Filter bit 21 */ |
9465 | #define CAN_F3R2_FB22_Pos (22U) |
| 9466 | #define CAN_F3R2_FB22_Pos (22U) |
9466 | #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ |
| 9467 | #define CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos) /*!< 0x00400000 */ |
9467 | #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */ |
| 9468 | #define CAN_F3R2_FB22 CAN_F3R2_FB22_Msk /*!< Filter bit 22 */ |
9468 | #define CAN_F3R2_FB23_Pos (23U) |
| 9469 | #define CAN_F3R2_FB23_Pos (23U) |
9469 | #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ |
| 9470 | #define CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos) /*!< 0x00800000 */ |
9470 | #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */ |
| 9471 | #define CAN_F3R2_FB23 CAN_F3R2_FB23_Msk /*!< Filter bit 23 */ |
9471 | #define CAN_F3R2_FB24_Pos (24U) |
| 9472 | #define CAN_F3R2_FB24_Pos (24U) |
9472 | #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ |
| 9473 | #define CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos) /*!< 0x01000000 */ |
9473 | #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */ |
| 9474 | #define CAN_F3R2_FB24 CAN_F3R2_FB24_Msk /*!< Filter bit 24 */ |
9474 | #define CAN_F3R2_FB25_Pos (25U) |
| 9475 | #define CAN_F3R2_FB25_Pos (25U) |
9475 | #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ |
| 9476 | #define CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos) /*!< 0x02000000 */ |
9476 | #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */ |
| 9477 | #define CAN_F3R2_FB25 CAN_F3R2_FB25_Msk /*!< Filter bit 25 */ |
9477 | #define CAN_F3R2_FB26_Pos (26U) |
| 9478 | #define CAN_F3R2_FB26_Pos (26U) |
9478 | #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ |
| 9479 | #define CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos) /*!< 0x04000000 */ |
9479 | #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */ |
| 9480 | #define CAN_F3R2_FB26 CAN_F3R2_FB26_Msk /*!< Filter bit 26 */ |
9480 | #define CAN_F3R2_FB27_Pos (27U) |
| 9481 | #define CAN_F3R2_FB27_Pos (27U) |
9481 | #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ |
| 9482 | #define CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos) /*!< 0x08000000 */ |
9482 | #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */ |
| 9483 | #define CAN_F3R2_FB27 CAN_F3R2_FB27_Msk /*!< Filter bit 27 */ |
9483 | #define CAN_F3R2_FB28_Pos (28U) |
| 9484 | #define CAN_F3R2_FB28_Pos (28U) |
9484 | #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ |
| 9485 | #define CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos) /*!< 0x10000000 */ |
9485 | #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */ |
| 9486 | #define CAN_F3R2_FB28 CAN_F3R2_FB28_Msk /*!< Filter bit 28 */ |
9486 | #define CAN_F3R2_FB29_Pos (29U) |
| 9487 | #define CAN_F3R2_FB29_Pos (29U) |
9487 | #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ |
| 9488 | #define CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos) /*!< 0x20000000 */ |
9488 | #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */ |
| 9489 | #define CAN_F3R2_FB29 CAN_F3R2_FB29_Msk /*!< Filter bit 29 */ |
9489 | #define CAN_F3R2_FB30_Pos (30U) |
| 9490 | #define CAN_F3R2_FB30_Pos (30U) |
9490 | #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ |
| 9491 | #define CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos) /*!< 0x40000000 */ |
9491 | #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */ |
| 9492 | #define CAN_F3R2_FB30 CAN_F3R2_FB30_Msk /*!< Filter bit 30 */ |
9492 | #define CAN_F3R2_FB31_Pos (31U) |
| 9493 | #define CAN_F3R2_FB31_Pos (31U) |
9493 | #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ |
| 9494 | #define CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos) /*!< 0x80000000 */ |
9494 | #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */ |
| 9495 | #define CAN_F3R2_FB31 CAN_F3R2_FB31_Msk /*!< Filter bit 31 */ |
9495 | |
| 9496 | 9496 | /******************* Bit definition for CAN_F4R2 register *******************/ |
|
| 9497 | /******************* Bit definition for CAN_F4R2 register *******************/ |
9497 | #define CAN_F4R2_FB0_Pos (0U) |
| 9498 | #define CAN_F4R2_FB0_Pos (0U) |
9498 | #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ |
| 9499 | #define CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos) /*!< 0x00000001 */ |
9499 | #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */ |
| 9500 | #define CAN_F4R2_FB0 CAN_F4R2_FB0_Msk /*!< Filter bit 0 */ |
9500 | #define CAN_F4R2_FB1_Pos (1U) |
| 9501 | #define CAN_F4R2_FB1_Pos (1U) |
9501 | #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ |
| 9502 | #define CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos) /*!< 0x00000002 */ |
9502 | #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */ |
| 9503 | #define CAN_F4R2_FB1 CAN_F4R2_FB1_Msk /*!< Filter bit 1 */ |
9503 | #define CAN_F4R2_FB2_Pos (2U) |
| 9504 | #define CAN_F4R2_FB2_Pos (2U) |
9504 | #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ |
| 9505 | #define CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos) /*!< 0x00000004 */ |
9505 | #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */ |
| 9506 | #define CAN_F4R2_FB2 CAN_F4R2_FB2_Msk /*!< Filter bit 2 */ |
9506 | #define CAN_F4R2_FB3_Pos (3U) |
| 9507 | #define CAN_F4R2_FB3_Pos (3U) |
9507 | #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ |
| 9508 | #define CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos) /*!< 0x00000008 */ |
9508 | #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */ |
| 9509 | #define CAN_F4R2_FB3 CAN_F4R2_FB3_Msk /*!< Filter bit 3 */ |
9509 | #define CAN_F4R2_FB4_Pos (4U) |
| 9510 | #define CAN_F4R2_FB4_Pos (4U) |
9510 | #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ |
| 9511 | #define CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos) /*!< 0x00000010 */ |
9511 | #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */ |
| 9512 | #define CAN_F4R2_FB4 CAN_F4R2_FB4_Msk /*!< Filter bit 4 */ |
9512 | #define CAN_F4R2_FB5_Pos (5U) |
| 9513 | #define CAN_F4R2_FB5_Pos (5U) |
9513 | #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ |
| 9514 | #define CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos) /*!< 0x00000020 */ |
9514 | #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */ |
| 9515 | #define CAN_F4R2_FB5 CAN_F4R2_FB5_Msk /*!< Filter bit 5 */ |
9515 | #define CAN_F4R2_FB6_Pos (6U) |
| 9516 | #define CAN_F4R2_FB6_Pos (6U) |
9516 | #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ |
| 9517 | #define CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos) /*!< 0x00000040 */ |
9517 | #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */ |
| 9518 | #define CAN_F4R2_FB6 CAN_F4R2_FB6_Msk /*!< Filter bit 6 */ |
9518 | #define CAN_F4R2_FB7_Pos (7U) |
| 9519 | #define CAN_F4R2_FB7_Pos (7U) |
9519 | #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ |
| 9520 | #define CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos) /*!< 0x00000080 */ |
9520 | #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */ |
| 9521 | #define CAN_F4R2_FB7 CAN_F4R2_FB7_Msk /*!< Filter bit 7 */ |
9521 | #define CAN_F4R2_FB8_Pos (8U) |
| 9522 | #define CAN_F4R2_FB8_Pos (8U) |
9522 | #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ |
| 9523 | #define CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos) /*!< 0x00000100 */ |
9523 | #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */ |
| 9524 | #define CAN_F4R2_FB8 CAN_F4R2_FB8_Msk /*!< Filter bit 8 */ |
9524 | #define CAN_F4R2_FB9_Pos (9U) |
| 9525 | #define CAN_F4R2_FB9_Pos (9U) |
9525 | #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ |
| 9526 | #define CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos) /*!< 0x00000200 */ |
9526 | #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */ |
| 9527 | #define CAN_F4R2_FB9 CAN_F4R2_FB9_Msk /*!< Filter bit 9 */ |
9527 | #define CAN_F4R2_FB10_Pos (10U) |
| 9528 | #define CAN_F4R2_FB10_Pos (10U) |
9528 | #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ |
| 9529 | #define CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos) /*!< 0x00000400 */ |
9529 | #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */ |
| 9530 | #define CAN_F4R2_FB10 CAN_F4R2_FB10_Msk /*!< Filter bit 10 */ |
9530 | #define CAN_F4R2_FB11_Pos (11U) |
| 9531 | #define CAN_F4R2_FB11_Pos (11U) |
9531 | #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ |
| 9532 | #define CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos) /*!< 0x00000800 */ |
9532 | #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */ |
| 9533 | #define CAN_F4R2_FB11 CAN_F4R2_FB11_Msk /*!< Filter bit 11 */ |
9533 | #define CAN_F4R2_FB12_Pos (12U) |
| 9534 | #define CAN_F4R2_FB12_Pos (12U) |
9534 | #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ |
| 9535 | #define CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos) /*!< 0x00001000 */ |
9535 | #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */ |
| 9536 | #define CAN_F4R2_FB12 CAN_F4R2_FB12_Msk /*!< Filter bit 12 */ |
9536 | #define CAN_F4R2_FB13_Pos (13U) |
| 9537 | #define CAN_F4R2_FB13_Pos (13U) |
9537 | #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ |
| 9538 | #define CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos) /*!< 0x00002000 */ |
9538 | #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */ |
| 9539 | #define CAN_F4R2_FB13 CAN_F4R2_FB13_Msk /*!< Filter bit 13 */ |
9539 | #define CAN_F4R2_FB14_Pos (14U) |
| 9540 | #define CAN_F4R2_FB14_Pos (14U) |
9540 | #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ |
| 9541 | #define CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos) /*!< 0x00004000 */ |
9541 | #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */ |
| 9542 | #define CAN_F4R2_FB14 CAN_F4R2_FB14_Msk /*!< Filter bit 14 */ |
9542 | #define CAN_F4R2_FB15_Pos (15U) |
| 9543 | #define CAN_F4R2_FB15_Pos (15U) |
9543 | #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ |
| 9544 | #define CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos) /*!< 0x00008000 */ |
9544 | #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */ |
| 9545 | #define CAN_F4R2_FB15 CAN_F4R2_FB15_Msk /*!< Filter bit 15 */ |
9545 | #define CAN_F4R2_FB16_Pos (16U) |
| 9546 | #define CAN_F4R2_FB16_Pos (16U) |
9546 | #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ |
| 9547 | #define CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos) /*!< 0x00010000 */ |
9547 | #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */ |
| 9548 | #define CAN_F4R2_FB16 CAN_F4R2_FB16_Msk /*!< Filter bit 16 */ |
9548 | #define CAN_F4R2_FB17_Pos (17U) |
| 9549 | #define CAN_F4R2_FB17_Pos (17U) |
9549 | #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ |
| 9550 | #define CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos) /*!< 0x00020000 */ |
9550 | #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */ |
| 9551 | #define CAN_F4R2_FB17 CAN_F4R2_FB17_Msk /*!< Filter bit 17 */ |
9551 | #define CAN_F4R2_FB18_Pos (18U) |
| 9552 | #define CAN_F4R2_FB18_Pos (18U) |
9552 | #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ |
| 9553 | #define CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos) /*!< 0x00040000 */ |
9553 | #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */ |
| 9554 | #define CAN_F4R2_FB18 CAN_F4R2_FB18_Msk /*!< Filter bit 18 */ |
9554 | #define CAN_F4R2_FB19_Pos (19U) |
| 9555 | #define CAN_F4R2_FB19_Pos (19U) |
9555 | #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ |
| 9556 | #define CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos) /*!< 0x00080000 */ |
9556 | #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */ |
| 9557 | #define CAN_F4R2_FB19 CAN_F4R2_FB19_Msk /*!< Filter bit 19 */ |
9557 | #define CAN_F4R2_FB20_Pos (20U) |
| 9558 | #define CAN_F4R2_FB20_Pos (20U) |
9558 | #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ |
| 9559 | #define CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos) /*!< 0x00100000 */ |
9559 | #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */ |
| 9560 | #define CAN_F4R2_FB20 CAN_F4R2_FB20_Msk /*!< Filter bit 20 */ |
9560 | #define CAN_F4R2_FB21_Pos (21U) |
| 9561 | #define CAN_F4R2_FB21_Pos (21U) |
9561 | #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ |
| 9562 | #define CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos) /*!< 0x00200000 */ |
9562 | #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */ |
| 9563 | #define CAN_F4R2_FB21 CAN_F4R2_FB21_Msk /*!< Filter bit 21 */ |
9563 | #define CAN_F4R2_FB22_Pos (22U) |
| 9564 | #define CAN_F4R2_FB22_Pos (22U) |
9564 | #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ |
| 9565 | #define CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos) /*!< 0x00400000 */ |
9565 | #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */ |
| 9566 | #define CAN_F4R2_FB22 CAN_F4R2_FB22_Msk /*!< Filter bit 22 */ |
9566 | #define CAN_F4R2_FB23_Pos (23U) |
| 9567 | #define CAN_F4R2_FB23_Pos (23U) |
9567 | #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ |
| 9568 | #define CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos) /*!< 0x00800000 */ |
9568 | #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */ |
| 9569 | #define CAN_F4R2_FB23 CAN_F4R2_FB23_Msk /*!< Filter bit 23 */ |
9569 | #define CAN_F4R2_FB24_Pos (24U) |
| 9570 | #define CAN_F4R2_FB24_Pos (24U) |
9570 | #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ |
| 9571 | #define CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos) /*!< 0x01000000 */ |
9571 | #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */ |
| 9572 | #define CAN_F4R2_FB24 CAN_F4R2_FB24_Msk /*!< Filter bit 24 */ |
9572 | #define CAN_F4R2_FB25_Pos (25U) |
| 9573 | #define CAN_F4R2_FB25_Pos (25U) |
9573 | #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ |
| 9574 | #define CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos) /*!< 0x02000000 */ |
9574 | #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */ |
| 9575 | #define CAN_F4R2_FB25 CAN_F4R2_FB25_Msk /*!< Filter bit 25 */ |
9575 | #define CAN_F4R2_FB26_Pos (26U) |
| 9576 | #define CAN_F4R2_FB26_Pos (26U) |
9576 | #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ |
| 9577 | #define CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos) /*!< 0x04000000 */ |
9577 | #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */ |
| 9578 | #define CAN_F4R2_FB26 CAN_F4R2_FB26_Msk /*!< Filter bit 26 */ |
9578 | #define CAN_F4R2_FB27_Pos (27U) |
| 9579 | #define CAN_F4R2_FB27_Pos (27U) |
9579 | #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ |
| 9580 | #define CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos) /*!< 0x08000000 */ |
9580 | #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */ |
| 9581 | #define CAN_F4R2_FB27 CAN_F4R2_FB27_Msk /*!< Filter bit 27 */ |
9581 | #define CAN_F4R2_FB28_Pos (28U) |
| 9582 | #define CAN_F4R2_FB28_Pos (28U) |
9582 | #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ |
| 9583 | #define CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos) /*!< 0x10000000 */ |
9583 | #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */ |
| 9584 | #define CAN_F4R2_FB28 CAN_F4R2_FB28_Msk /*!< Filter bit 28 */ |
9584 | #define CAN_F4R2_FB29_Pos (29U) |
| 9585 | #define CAN_F4R2_FB29_Pos (29U) |
9585 | #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ |
| 9586 | #define CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos) /*!< 0x20000000 */ |
9586 | #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */ |
| 9587 | #define CAN_F4R2_FB29 CAN_F4R2_FB29_Msk /*!< Filter bit 29 */ |
9587 | #define CAN_F4R2_FB30_Pos (30U) |
| 9588 | #define CAN_F4R2_FB30_Pos (30U) |
9588 | #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ |
| 9589 | #define CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos) /*!< 0x40000000 */ |
9589 | #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */ |
| 9590 | #define CAN_F4R2_FB30 CAN_F4R2_FB30_Msk /*!< Filter bit 30 */ |
9590 | #define CAN_F4R2_FB31_Pos (31U) |
| 9591 | #define CAN_F4R2_FB31_Pos (31U) |
9591 | #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ |
| 9592 | #define CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos) /*!< 0x80000000 */ |
9592 | #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */ |
| 9593 | #define CAN_F4R2_FB31 CAN_F4R2_FB31_Msk /*!< Filter bit 31 */ |
9593 | |
| 9594 | 9594 | /******************* Bit definition for CAN_F5R2 register *******************/ |
|
| 9595 | /******************* Bit definition for CAN_F5R2 register *******************/ |
9595 | #define CAN_F5R2_FB0_Pos (0U) |
| 9596 | #define CAN_F5R2_FB0_Pos (0U) |
9596 | #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ |
| 9597 | #define CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos) /*!< 0x00000001 */ |
9597 | #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */ |
| 9598 | #define CAN_F5R2_FB0 CAN_F5R2_FB0_Msk /*!< Filter bit 0 */ |
9598 | #define CAN_F5R2_FB1_Pos (1U) |
| 9599 | #define CAN_F5R2_FB1_Pos (1U) |
9599 | #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ |
| 9600 | #define CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos) /*!< 0x00000002 */ |
9600 | #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */ |
| 9601 | #define CAN_F5R2_FB1 CAN_F5R2_FB1_Msk /*!< Filter bit 1 */ |
9601 | #define CAN_F5R2_FB2_Pos (2U) |
| 9602 | #define CAN_F5R2_FB2_Pos (2U) |
9602 | #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ |
| 9603 | #define CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos) /*!< 0x00000004 */ |
9603 | #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */ |
| 9604 | #define CAN_F5R2_FB2 CAN_F5R2_FB2_Msk /*!< Filter bit 2 */ |
9604 | #define CAN_F5R2_FB3_Pos (3U) |
| 9605 | #define CAN_F5R2_FB3_Pos (3U) |
9605 | #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ |
| 9606 | #define CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos) /*!< 0x00000008 */ |
9606 | #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */ |
| 9607 | #define CAN_F5R2_FB3 CAN_F5R2_FB3_Msk /*!< Filter bit 3 */ |
9607 | #define CAN_F5R2_FB4_Pos (4U) |
| 9608 | #define CAN_F5R2_FB4_Pos (4U) |
9608 | #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ |
| 9609 | #define CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos) /*!< 0x00000010 */ |
9609 | #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */ |
| 9610 | #define CAN_F5R2_FB4 CAN_F5R2_FB4_Msk /*!< Filter bit 4 */ |
9610 | #define CAN_F5R2_FB5_Pos (5U) |
| 9611 | #define CAN_F5R2_FB5_Pos (5U) |
9611 | #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ |
| 9612 | #define CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos) /*!< 0x00000020 */ |
9612 | #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */ |
| 9613 | #define CAN_F5R2_FB5 CAN_F5R2_FB5_Msk /*!< Filter bit 5 */ |
9613 | #define CAN_F5R2_FB6_Pos (6U) |
| 9614 | #define CAN_F5R2_FB6_Pos (6U) |
9614 | #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ |
| 9615 | #define CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos) /*!< 0x00000040 */ |
9615 | #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */ |
| 9616 | #define CAN_F5R2_FB6 CAN_F5R2_FB6_Msk /*!< Filter bit 6 */ |
9616 | #define CAN_F5R2_FB7_Pos (7U) |
| 9617 | #define CAN_F5R2_FB7_Pos (7U) |
9617 | #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ |
| 9618 | #define CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos) /*!< 0x00000080 */ |
9618 | #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */ |
| 9619 | #define CAN_F5R2_FB7 CAN_F5R2_FB7_Msk /*!< Filter bit 7 */ |
9619 | #define CAN_F5R2_FB8_Pos (8U) |
| 9620 | #define CAN_F5R2_FB8_Pos (8U) |
9620 | #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ |
| 9621 | #define CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos) /*!< 0x00000100 */ |
9621 | #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */ |
| 9622 | #define CAN_F5R2_FB8 CAN_F5R2_FB8_Msk /*!< Filter bit 8 */ |
9622 | #define CAN_F5R2_FB9_Pos (9U) |
| 9623 | #define CAN_F5R2_FB9_Pos (9U) |
9623 | #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ |
| 9624 | #define CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos) /*!< 0x00000200 */ |
9624 | #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */ |
| 9625 | #define CAN_F5R2_FB9 CAN_F5R2_FB9_Msk /*!< Filter bit 9 */ |
9625 | #define CAN_F5R2_FB10_Pos (10U) |
| 9626 | #define CAN_F5R2_FB10_Pos (10U) |
9626 | #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ |
| 9627 | #define CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos) /*!< 0x00000400 */ |
9627 | #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */ |
| 9628 | #define CAN_F5R2_FB10 CAN_F5R2_FB10_Msk /*!< Filter bit 10 */ |
9628 | #define CAN_F5R2_FB11_Pos (11U) |
| 9629 | #define CAN_F5R2_FB11_Pos (11U) |
9629 | #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ |
| 9630 | #define CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos) /*!< 0x00000800 */ |
9630 | #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */ |
| 9631 | #define CAN_F5R2_FB11 CAN_F5R2_FB11_Msk /*!< Filter bit 11 */ |
9631 | #define CAN_F5R2_FB12_Pos (12U) |
| 9632 | #define CAN_F5R2_FB12_Pos (12U) |
9632 | #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ |
| 9633 | #define CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos) /*!< 0x00001000 */ |
9633 | #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */ |
| 9634 | #define CAN_F5R2_FB12 CAN_F5R2_FB12_Msk /*!< Filter bit 12 */ |
9634 | #define CAN_F5R2_FB13_Pos (13U) |
| 9635 | #define CAN_F5R2_FB13_Pos (13U) |
9635 | #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ |
| 9636 | #define CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos) /*!< 0x00002000 */ |
9636 | #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */ |
| 9637 | #define CAN_F5R2_FB13 CAN_F5R2_FB13_Msk /*!< Filter bit 13 */ |
9637 | #define CAN_F5R2_FB14_Pos (14U) |
| 9638 | #define CAN_F5R2_FB14_Pos (14U) |
9638 | #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ |
| 9639 | #define CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos) /*!< 0x00004000 */ |
9639 | #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */ |
| 9640 | #define CAN_F5R2_FB14 CAN_F5R2_FB14_Msk /*!< Filter bit 14 */ |
9640 | #define CAN_F5R2_FB15_Pos (15U) |
| 9641 | #define CAN_F5R2_FB15_Pos (15U) |
9641 | #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ |
| 9642 | #define CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos) /*!< 0x00008000 */ |
9642 | #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */ |
| 9643 | #define CAN_F5R2_FB15 CAN_F5R2_FB15_Msk /*!< Filter bit 15 */ |
9643 | #define CAN_F5R2_FB16_Pos (16U) |
| 9644 | #define CAN_F5R2_FB16_Pos (16U) |
9644 | #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ |
| 9645 | #define CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos) /*!< 0x00010000 */ |
9645 | #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */ |
| 9646 | #define CAN_F5R2_FB16 CAN_F5R2_FB16_Msk /*!< Filter bit 16 */ |
9646 | #define CAN_F5R2_FB17_Pos (17U) |
| 9647 | #define CAN_F5R2_FB17_Pos (17U) |
9647 | #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ |
| 9648 | #define CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos) /*!< 0x00020000 */ |
9648 | #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */ |
| 9649 | #define CAN_F5R2_FB17 CAN_F5R2_FB17_Msk /*!< Filter bit 17 */ |
9649 | #define CAN_F5R2_FB18_Pos (18U) |
| 9650 | #define CAN_F5R2_FB18_Pos (18U) |
9650 | #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ |
| 9651 | #define CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos) /*!< 0x00040000 */ |
9651 | #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */ |
| 9652 | #define CAN_F5R2_FB18 CAN_F5R2_FB18_Msk /*!< Filter bit 18 */ |
9652 | #define CAN_F5R2_FB19_Pos (19U) |
| 9653 | #define CAN_F5R2_FB19_Pos (19U) |
9653 | #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ |
| 9654 | #define CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos) /*!< 0x00080000 */ |
9654 | #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */ |
| 9655 | #define CAN_F5R2_FB19 CAN_F5R2_FB19_Msk /*!< Filter bit 19 */ |
9655 | #define CAN_F5R2_FB20_Pos (20U) |
| 9656 | #define CAN_F5R2_FB20_Pos (20U) |
9656 | #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ |
| 9657 | #define CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos) /*!< 0x00100000 */ |
9657 | #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */ |
| 9658 | #define CAN_F5R2_FB20 CAN_F5R2_FB20_Msk /*!< Filter bit 20 */ |
9658 | #define CAN_F5R2_FB21_Pos (21U) |
| 9659 | #define CAN_F5R2_FB21_Pos (21U) |
9659 | #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ |
| 9660 | #define CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos) /*!< 0x00200000 */ |
9660 | #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */ |
| 9661 | #define CAN_F5R2_FB21 CAN_F5R2_FB21_Msk /*!< Filter bit 21 */ |
9661 | #define CAN_F5R2_FB22_Pos (22U) |
| 9662 | #define CAN_F5R2_FB22_Pos (22U) |
9662 | #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ |
| 9663 | #define CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos) /*!< 0x00400000 */ |
9663 | #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */ |
| 9664 | #define CAN_F5R2_FB22 CAN_F5R2_FB22_Msk /*!< Filter bit 22 */ |
9664 | #define CAN_F5R2_FB23_Pos (23U) |
| 9665 | #define CAN_F5R2_FB23_Pos (23U) |
9665 | #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ |
| 9666 | #define CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos) /*!< 0x00800000 */ |
9666 | #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */ |
| 9667 | #define CAN_F5R2_FB23 CAN_F5R2_FB23_Msk /*!< Filter bit 23 */ |
9667 | #define CAN_F5R2_FB24_Pos (24U) |
| 9668 | #define CAN_F5R2_FB24_Pos (24U) |
9668 | #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ |
| 9669 | #define CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos) /*!< 0x01000000 */ |
9669 | #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */ |
| 9670 | #define CAN_F5R2_FB24 CAN_F5R2_FB24_Msk /*!< Filter bit 24 */ |
9670 | #define CAN_F5R2_FB25_Pos (25U) |
| 9671 | #define CAN_F5R2_FB25_Pos (25U) |
9671 | #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ |
| 9672 | #define CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos) /*!< 0x02000000 */ |
9672 | #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */ |
| 9673 | #define CAN_F5R2_FB25 CAN_F5R2_FB25_Msk /*!< Filter bit 25 */ |
9673 | #define CAN_F5R2_FB26_Pos (26U) |
| 9674 | #define CAN_F5R2_FB26_Pos (26U) |
9674 | #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ |
| 9675 | #define CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos) /*!< 0x04000000 */ |
9675 | #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */ |
| 9676 | #define CAN_F5R2_FB26 CAN_F5R2_FB26_Msk /*!< Filter bit 26 */ |
9676 | #define CAN_F5R2_FB27_Pos (27U) |
| 9677 | #define CAN_F5R2_FB27_Pos (27U) |
9677 | #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ |
| 9678 | #define CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos) /*!< 0x08000000 */ |
9678 | #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */ |
| 9679 | #define CAN_F5R2_FB27 CAN_F5R2_FB27_Msk /*!< Filter bit 27 */ |
9679 | #define CAN_F5R2_FB28_Pos (28U) |
| 9680 | #define CAN_F5R2_FB28_Pos (28U) |
9680 | #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ |
| 9681 | #define CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos) /*!< 0x10000000 */ |
9681 | #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */ |
| 9682 | #define CAN_F5R2_FB28 CAN_F5R2_FB28_Msk /*!< Filter bit 28 */ |
9682 | #define CAN_F5R2_FB29_Pos (29U) |
| 9683 | #define CAN_F5R2_FB29_Pos (29U) |
9683 | #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ |
| 9684 | #define CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos) /*!< 0x20000000 */ |
9684 | #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */ |
| 9685 | #define CAN_F5R2_FB29 CAN_F5R2_FB29_Msk /*!< Filter bit 29 */ |
9685 | #define CAN_F5R2_FB30_Pos (30U) |
| 9686 | #define CAN_F5R2_FB30_Pos (30U) |
9686 | #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ |
| 9687 | #define CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos) /*!< 0x40000000 */ |
9687 | #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */ |
| 9688 | #define CAN_F5R2_FB30 CAN_F5R2_FB30_Msk /*!< Filter bit 30 */ |
9688 | #define CAN_F5R2_FB31_Pos (31U) |
| 9689 | #define CAN_F5R2_FB31_Pos (31U) |
9689 | #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ |
| 9690 | #define CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos) /*!< 0x80000000 */ |
9690 | #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */ |
| 9691 | #define CAN_F5R2_FB31 CAN_F5R2_FB31_Msk /*!< Filter bit 31 */ |
9691 | |
| 9692 | 9692 | /******************* Bit definition for CAN_F6R2 register *******************/ |
|
| 9693 | /******************* Bit definition for CAN_F6R2 register *******************/ |
9693 | #define CAN_F6R2_FB0_Pos (0U) |
| 9694 | #define CAN_F6R2_FB0_Pos (0U) |
9694 | #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ |
| 9695 | #define CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos) /*!< 0x00000001 */ |
9695 | #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */ |
| 9696 | #define CAN_F6R2_FB0 CAN_F6R2_FB0_Msk /*!< Filter bit 0 */ |
9696 | #define CAN_F6R2_FB1_Pos (1U) |
| 9697 | #define CAN_F6R2_FB1_Pos (1U) |
9697 | #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ |
| 9698 | #define CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos) /*!< 0x00000002 */ |
9698 | #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */ |
| 9699 | #define CAN_F6R2_FB1 CAN_F6R2_FB1_Msk /*!< Filter bit 1 */ |
9699 | #define CAN_F6R2_FB2_Pos (2U) |
| 9700 | #define CAN_F6R2_FB2_Pos (2U) |
9700 | #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ |
| 9701 | #define CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos) /*!< 0x00000004 */ |
9701 | #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */ |
| 9702 | #define CAN_F6R2_FB2 CAN_F6R2_FB2_Msk /*!< Filter bit 2 */ |
9702 | #define CAN_F6R2_FB3_Pos (3U) |
| 9703 | #define CAN_F6R2_FB3_Pos (3U) |
9703 | #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ |
| 9704 | #define CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos) /*!< 0x00000008 */ |
9704 | #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */ |
| 9705 | #define CAN_F6R2_FB3 CAN_F6R2_FB3_Msk /*!< Filter bit 3 */ |
9705 | #define CAN_F6R2_FB4_Pos (4U) |
| 9706 | #define CAN_F6R2_FB4_Pos (4U) |
9706 | #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ |
| 9707 | #define CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos) /*!< 0x00000010 */ |
9707 | #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */ |
| 9708 | #define CAN_F6R2_FB4 CAN_F6R2_FB4_Msk /*!< Filter bit 4 */ |
9708 | #define CAN_F6R2_FB5_Pos (5U) |
| 9709 | #define CAN_F6R2_FB5_Pos (5U) |
9709 | #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ |
| 9710 | #define CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos) /*!< 0x00000020 */ |
9710 | #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */ |
| 9711 | #define CAN_F6R2_FB5 CAN_F6R2_FB5_Msk /*!< Filter bit 5 */ |
9711 | #define CAN_F6R2_FB6_Pos (6U) |
| 9712 | #define CAN_F6R2_FB6_Pos (6U) |
9712 | #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ |
| 9713 | #define CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos) /*!< 0x00000040 */ |
9713 | #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */ |
| 9714 | #define CAN_F6R2_FB6 CAN_F6R2_FB6_Msk /*!< Filter bit 6 */ |
9714 | #define CAN_F6R2_FB7_Pos (7U) |
| 9715 | #define CAN_F6R2_FB7_Pos (7U) |
9715 | #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ |
| 9716 | #define CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos) /*!< 0x00000080 */ |
9716 | #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */ |
| 9717 | #define CAN_F6R2_FB7 CAN_F6R2_FB7_Msk /*!< Filter bit 7 */ |
9717 | #define CAN_F6R2_FB8_Pos (8U) |
| 9718 | #define CAN_F6R2_FB8_Pos (8U) |
9718 | #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ |
| 9719 | #define CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos) /*!< 0x00000100 */ |
9719 | #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */ |
| 9720 | #define CAN_F6R2_FB8 CAN_F6R2_FB8_Msk /*!< Filter bit 8 */ |
9720 | #define CAN_F6R2_FB9_Pos (9U) |
| 9721 | #define CAN_F6R2_FB9_Pos (9U) |
9721 | #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ |
| 9722 | #define CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos) /*!< 0x00000200 */ |
9722 | #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */ |
| 9723 | #define CAN_F6R2_FB9 CAN_F6R2_FB9_Msk /*!< Filter bit 9 */ |
9723 | #define CAN_F6R2_FB10_Pos (10U) |
| 9724 | #define CAN_F6R2_FB10_Pos (10U) |
9724 | #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ |
| 9725 | #define CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos) /*!< 0x00000400 */ |
9725 | #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */ |
| 9726 | #define CAN_F6R2_FB10 CAN_F6R2_FB10_Msk /*!< Filter bit 10 */ |
9726 | #define CAN_F6R2_FB11_Pos (11U) |
| 9727 | #define CAN_F6R2_FB11_Pos (11U) |
9727 | #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ |
| 9728 | #define CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos) /*!< 0x00000800 */ |
9728 | #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */ |
| 9729 | #define CAN_F6R2_FB11 CAN_F6R2_FB11_Msk /*!< Filter bit 11 */ |
9729 | #define CAN_F6R2_FB12_Pos (12U) |
| 9730 | #define CAN_F6R2_FB12_Pos (12U) |
9730 | #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ |
| 9731 | #define CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos) /*!< 0x00001000 */ |
9731 | #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */ |
| 9732 | #define CAN_F6R2_FB12 CAN_F6R2_FB12_Msk /*!< Filter bit 12 */ |
9732 | #define CAN_F6R2_FB13_Pos (13U) |
| 9733 | #define CAN_F6R2_FB13_Pos (13U) |
9733 | #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ |
| 9734 | #define CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos) /*!< 0x00002000 */ |
9734 | #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */ |
| 9735 | #define CAN_F6R2_FB13 CAN_F6R2_FB13_Msk /*!< Filter bit 13 */ |
9735 | #define CAN_F6R2_FB14_Pos (14U) |
| 9736 | #define CAN_F6R2_FB14_Pos (14U) |
9736 | #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ |
| 9737 | #define CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos) /*!< 0x00004000 */ |
9737 | #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */ |
| 9738 | #define CAN_F6R2_FB14 CAN_F6R2_FB14_Msk /*!< Filter bit 14 */ |
9738 | #define CAN_F6R2_FB15_Pos (15U) |
| 9739 | #define CAN_F6R2_FB15_Pos (15U) |
9739 | #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ |
| 9740 | #define CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos) /*!< 0x00008000 */ |
9740 | #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */ |
| 9741 | #define CAN_F6R2_FB15 CAN_F6R2_FB15_Msk /*!< Filter bit 15 */ |
9741 | #define CAN_F6R2_FB16_Pos (16U) |
| 9742 | #define CAN_F6R2_FB16_Pos (16U) |
9742 | #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ |
| 9743 | #define CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos) /*!< 0x00010000 */ |
9743 | #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */ |
| 9744 | #define CAN_F6R2_FB16 CAN_F6R2_FB16_Msk /*!< Filter bit 16 */ |
9744 | #define CAN_F6R2_FB17_Pos (17U) |
| 9745 | #define CAN_F6R2_FB17_Pos (17U) |
9745 | #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ |
| 9746 | #define CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos) /*!< 0x00020000 */ |
9746 | #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */ |
| 9747 | #define CAN_F6R2_FB17 CAN_F6R2_FB17_Msk /*!< Filter bit 17 */ |
9747 | #define CAN_F6R2_FB18_Pos (18U) |
| 9748 | #define CAN_F6R2_FB18_Pos (18U) |
9748 | #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ |
| 9749 | #define CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos) /*!< 0x00040000 */ |
9749 | #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */ |
| 9750 | #define CAN_F6R2_FB18 CAN_F6R2_FB18_Msk /*!< Filter bit 18 */ |
9750 | #define CAN_F6R2_FB19_Pos (19U) |
| 9751 | #define CAN_F6R2_FB19_Pos (19U) |
9751 | #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ |
| 9752 | #define CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos) /*!< 0x00080000 */ |
9752 | #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */ |
| 9753 | #define CAN_F6R2_FB19 CAN_F6R2_FB19_Msk /*!< Filter bit 19 */ |
9753 | #define CAN_F6R2_FB20_Pos (20U) |
| 9754 | #define CAN_F6R2_FB20_Pos (20U) |
9754 | #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ |
| 9755 | #define CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos) /*!< 0x00100000 */ |
9755 | #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */ |
| 9756 | #define CAN_F6R2_FB20 CAN_F6R2_FB20_Msk /*!< Filter bit 20 */ |
9756 | #define CAN_F6R2_FB21_Pos (21U) |
| 9757 | #define CAN_F6R2_FB21_Pos (21U) |
9757 | #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ |
| 9758 | #define CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos) /*!< 0x00200000 */ |
9758 | #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */ |
| 9759 | #define CAN_F6R2_FB21 CAN_F6R2_FB21_Msk /*!< Filter bit 21 */ |
9759 | #define CAN_F6R2_FB22_Pos (22U) |
| 9760 | #define CAN_F6R2_FB22_Pos (22U) |
9760 | #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ |
| 9761 | #define CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos) /*!< 0x00400000 */ |
9761 | #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */ |
| 9762 | #define CAN_F6R2_FB22 CAN_F6R2_FB22_Msk /*!< Filter bit 22 */ |
9762 | #define CAN_F6R2_FB23_Pos (23U) |
| 9763 | #define CAN_F6R2_FB23_Pos (23U) |
9763 | #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ |
| 9764 | #define CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos) /*!< 0x00800000 */ |
9764 | #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */ |
| 9765 | #define CAN_F6R2_FB23 CAN_F6R2_FB23_Msk /*!< Filter bit 23 */ |
9765 | #define CAN_F6R2_FB24_Pos (24U) |
| 9766 | #define CAN_F6R2_FB24_Pos (24U) |
9766 | #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ |
| 9767 | #define CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos) /*!< 0x01000000 */ |
9767 | #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */ |
| 9768 | #define CAN_F6R2_FB24 CAN_F6R2_FB24_Msk /*!< Filter bit 24 */ |
9768 | #define CAN_F6R2_FB25_Pos (25U) |
| 9769 | #define CAN_F6R2_FB25_Pos (25U) |
9769 | #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ |
| 9770 | #define CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos) /*!< 0x02000000 */ |
9770 | #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */ |
| 9771 | #define CAN_F6R2_FB25 CAN_F6R2_FB25_Msk /*!< Filter bit 25 */ |
9771 | #define CAN_F6R2_FB26_Pos (26U) |
| 9772 | #define CAN_F6R2_FB26_Pos (26U) |
9772 | #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ |
| 9773 | #define CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos) /*!< 0x04000000 */ |
9773 | #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */ |
| 9774 | #define CAN_F6R2_FB26 CAN_F6R2_FB26_Msk /*!< Filter bit 26 */ |
9774 | #define CAN_F6R2_FB27_Pos (27U) |
| 9775 | #define CAN_F6R2_FB27_Pos (27U) |
9775 | #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ |
| 9776 | #define CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos) /*!< 0x08000000 */ |
9776 | #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */ |
| 9777 | #define CAN_F6R2_FB27 CAN_F6R2_FB27_Msk /*!< Filter bit 27 */ |
9777 | #define CAN_F6R2_FB28_Pos (28U) |
| 9778 | #define CAN_F6R2_FB28_Pos (28U) |
9778 | #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ |
| 9779 | #define CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos) /*!< 0x10000000 */ |
9779 | #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */ |
| 9780 | #define CAN_F6R2_FB28 CAN_F6R2_FB28_Msk /*!< Filter bit 28 */ |
9780 | #define CAN_F6R2_FB29_Pos (29U) |
| 9781 | #define CAN_F6R2_FB29_Pos (29U) |
9781 | #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ |
| 9782 | #define CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos) /*!< 0x20000000 */ |
9782 | #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */ |
| 9783 | #define CAN_F6R2_FB29 CAN_F6R2_FB29_Msk /*!< Filter bit 29 */ |
9783 | #define CAN_F6R2_FB30_Pos (30U) |
| 9784 | #define CAN_F6R2_FB30_Pos (30U) |
9784 | #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ |
| 9785 | #define CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos) /*!< 0x40000000 */ |
9785 | #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */ |
| 9786 | #define CAN_F6R2_FB30 CAN_F6R2_FB30_Msk /*!< Filter bit 30 */ |
9786 | #define CAN_F6R2_FB31_Pos (31U) |
| 9787 | #define CAN_F6R2_FB31_Pos (31U) |
9787 | #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ |
| 9788 | #define CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos) /*!< 0x80000000 */ |
9788 | #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */ |
| 9789 | #define CAN_F6R2_FB31 CAN_F6R2_FB31_Msk /*!< Filter bit 31 */ |
9789 | |
| 9790 | 9790 | /******************* Bit definition for CAN_F7R2 register *******************/ |
|
| 9791 | /******************* Bit definition for CAN_F7R2 register *******************/ |
9791 | #define CAN_F7R2_FB0_Pos (0U) |
| 9792 | #define CAN_F7R2_FB0_Pos (0U) |
9792 | #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ |
| 9793 | #define CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos) /*!< 0x00000001 */ |
9793 | #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */ |
| 9794 | #define CAN_F7R2_FB0 CAN_F7R2_FB0_Msk /*!< Filter bit 0 */ |
9794 | #define CAN_F7R2_FB1_Pos (1U) |
| 9795 | #define CAN_F7R2_FB1_Pos (1U) |
9795 | #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ |
| 9796 | #define CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos) /*!< 0x00000002 */ |
9796 | #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */ |
| 9797 | #define CAN_F7R2_FB1 CAN_F7R2_FB1_Msk /*!< Filter bit 1 */ |
9797 | #define CAN_F7R2_FB2_Pos (2U) |
| 9798 | #define CAN_F7R2_FB2_Pos (2U) |
9798 | #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ |
| 9799 | #define CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos) /*!< 0x00000004 */ |
9799 | #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */ |
| 9800 | #define CAN_F7R2_FB2 CAN_F7R2_FB2_Msk /*!< Filter bit 2 */ |
9800 | #define CAN_F7R2_FB3_Pos (3U) |
| 9801 | #define CAN_F7R2_FB3_Pos (3U) |
9801 | #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ |
| 9802 | #define CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos) /*!< 0x00000008 */ |
9802 | #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */ |
| 9803 | #define CAN_F7R2_FB3 CAN_F7R2_FB3_Msk /*!< Filter bit 3 */ |
9803 | #define CAN_F7R2_FB4_Pos (4U) |
| 9804 | #define CAN_F7R2_FB4_Pos (4U) |
9804 | #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ |
| 9805 | #define CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos) /*!< 0x00000010 */ |
9805 | #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */ |
| 9806 | #define CAN_F7R2_FB4 CAN_F7R2_FB4_Msk /*!< Filter bit 4 */ |
9806 | #define CAN_F7R2_FB5_Pos (5U) |
| 9807 | #define CAN_F7R2_FB5_Pos (5U) |
9807 | #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ |
| 9808 | #define CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos) /*!< 0x00000020 */ |
9808 | #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */ |
| 9809 | #define CAN_F7R2_FB5 CAN_F7R2_FB5_Msk /*!< Filter bit 5 */ |
9809 | #define CAN_F7R2_FB6_Pos (6U) |
| 9810 | #define CAN_F7R2_FB6_Pos (6U) |
9810 | #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ |
| 9811 | #define CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos) /*!< 0x00000040 */ |
9811 | #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */ |
| 9812 | #define CAN_F7R2_FB6 CAN_F7R2_FB6_Msk /*!< Filter bit 6 */ |
9812 | #define CAN_F7R2_FB7_Pos (7U) |
| 9813 | #define CAN_F7R2_FB7_Pos (7U) |
9813 | #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ |
| 9814 | #define CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos) /*!< 0x00000080 */ |
9814 | #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */ |
| 9815 | #define CAN_F7R2_FB7 CAN_F7R2_FB7_Msk /*!< Filter bit 7 */ |
9815 | #define CAN_F7R2_FB8_Pos (8U) |
| 9816 | #define CAN_F7R2_FB8_Pos (8U) |
9816 | #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ |
| 9817 | #define CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos) /*!< 0x00000100 */ |
9817 | #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */ |
| 9818 | #define CAN_F7R2_FB8 CAN_F7R2_FB8_Msk /*!< Filter bit 8 */ |
9818 | #define CAN_F7R2_FB9_Pos (9U) |
| 9819 | #define CAN_F7R2_FB9_Pos (9U) |
9819 | #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ |
| 9820 | #define CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos) /*!< 0x00000200 */ |
9820 | #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */ |
| 9821 | #define CAN_F7R2_FB9 CAN_F7R2_FB9_Msk /*!< Filter bit 9 */ |
9821 | #define CAN_F7R2_FB10_Pos (10U) |
| 9822 | #define CAN_F7R2_FB10_Pos (10U) |
9822 | #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ |
| 9823 | #define CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos) /*!< 0x00000400 */ |
9823 | #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */ |
| 9824 | #define CAN_F7R2_FB10 CAN_F7R2_FB10_Msk /*!< Filter bit 10 */ |
9824 | #define CAN_F7R2_FB11_Pos (11U) |
| 9825 | #define CAN_F7R2_FB11_Pos (11U) |
9825 | #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ |
| 9826 | #define CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos) /*!< 0x00000800 */ |
9826 | #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */ |
| 9827 | #define CAN_F7R2_FB11 CAN_F7R2_FB11_Msk /*!< Filter bit 11 */ |
9827 | #define CAN_F7R2_FB12_Pos (12U) |
| 9828 | #define CAN_F7R2_FB12_Pos (12U) |
9828 | #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ |
| 9829 | #define CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos) /*!< 0x00001000 */ |
9829 | #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */ |
| 9830 | #define CAN_F7R2_FB12 CAN_F7R2_FB12_Msk /*!< Filter bit 12 */ |
9830 | #define CAN_F7R2_FB13_Pos (13U) |
| 9831 | #define CAN_F7R2_FB13_Pos (13U) |
9831 | #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ |
| 9832 | #define CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos) /*!< 0x00002000 */ |
9832 | #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */ |
| 9833 | #define CAN_F7R2_FB13 CAN_F7R2_FB13_Msk /*!< Filter bit 13 */ |
9833 | #define CAN_F7R2_FB14_Pos (14U) |
| 9834 | #define CAN_F7R2_FB14_Pos (14U) |
9834 | #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ |
| 9835 | #define CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos) /*!< 0x00004000 */ |
9835 | #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */ |
| 9836 | #define CAN_F7R2_FB14 CAN_F7R2_FB14_Msk /*!< Filter bit 14 */ |
9836 | #define CAN_F7R2_FB15_Pos (15U) |
| 9837 | #define CAN_F7R2_FB15_Pos (15U) |
9837 | #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ |
| 9838 | #define CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos) /*!< 0x00008000 */ |
9838 | #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */ |
| 9839 | #define CAN_F7R2_FB15 CAN_F7R2_FB15_Msk /*!< Filter bit 15 */ |
9839 | #define CAN_F7R2_FB16_Pos (16U) |
| 9840 | #define CAN_F7R2_FB16_Pos (16U) |
9840 | #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ |
| 9841 | #define CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos) /*!< 0x00010000 */ |
9841 | #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */ |
| 9842 | #define CAN_F7R2_FB16 CAN_F7R2_FB16_Msk /*!< Filter bit 16 */ |
9842 | #define CAN_F7R2_FB17_Pos (17U) |
| 9843 | #define CAN_F7R2_FB17_Pos (17U) |
9843 | #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ |
| 9844 | #define CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos) /*!< 0x00020000 */ |
9844 | #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */ |
| 9845 | #define CAN_F7R2_FB17 CAN_F7R2_FB17_Msk /*!< Filter bit 17 */ |
9845 | #define CAN_F7R2_FB18_Pos (18U) |
| 9846 | #define CAN_F7R2_FB18_Pos (18U) |
9846 | #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ |
| 9847 | #define CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos) /*!< 0x00040000 */ |
9847 | #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */ |
| 9848 | #define CAN_F7R2_FB18 CAN_F7R2_FB18_Msk /*!< Filter bit 18 */ |
9848 | #define CAN_F7R2_FB19_Pos (19U) |
| 9849 | #define CAN_F7R2_FB19_Pos (19U) |
9849 | #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ |
| 9850 | #define CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos) /*!< 0x00080000 */ |
9850 | #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */ |
| 9851 | #define CAN_F7R2_FB19 CAN_F7R2_FB19_Msk /*!< Filter bit 19 */ |
9851 | #define CAN_F7R2_FB20_Pos (20U) |
| 9852 | #define CAN_F7R2_FB20_Pos (20U) |
9852 | #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ |
| 9853 | #define CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos) /*!< 0x00100000 */ |
9853 | #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */ |
| 9854 | #define CAN_F7R2_FB20 CAN_F7R2_FB20_Msk /*!< Filter bit 20 */ |
9854 | #define CAN_F7R2_FB21_Pos (21U) |
| 9855 | #define CAN_F7R2_FB21_Pos (21U) |
9855 | #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ |
| 9856 | #define CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos) /*!< 0x00200000 */ |
9856 | #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */ |
| 9857 | #define CAN_F7R2_FB21 CAN_F7R2_FB21_Msk /*!< Filter bit 21 */ |
9857 | #define CAN_F7R2_FB22_Pos (22U) |
| 9858 | #define CAN_F7R2_FB22_Pos (22U) |
9858 | #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ |
| 9859 | #define CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos) /*!< 0x00400000 */ |
9859 | #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */ |
| 9860 | #define CAN_F7R2_FB22 CAN_F7R2_FB22_Msk /*!< Filter bit 22 */ |
9860 | #define CAN_F7R2_FB23_Pos (23U) |
| 9861 | #define CAN_F7R2_FB23_Pos (23U) |
9861 | #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ |
| 9862 | #define CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos) /*!< 0x00800000 */ |
9862 | #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */ |
| 9863 | #define CAN_F7R2_FB23 CAN_F7R2_FB23_Msk /*!< Filter bit 23 */ |
9863 | #define CAN_F7R2_FB24_Pos (24U) |
| 9864 | #define CAN_F7R2_FB24_Pos (24U) |
9864 | #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ |
| 9865 | #define CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos) /*!< 0x01000000 */ |
9865 | #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */ |
| 9866 | #define CAN_F7R2_FB24 CAN_F7R2_FB24_Msk /*!< Filter bit 24 */ |
9866 | #define CAN_F7R2_FB25_Pos (25U) |
| 9867 | #define CAN_F7R2_FB25_Pos (25U) |
9867 | #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ |
| 9868 | #define CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos) /*!< 0x02000000 */ |
9868 | #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */ |
| 9869 | #define CAN_F7R2_FB25 CAN_F7R2_FB25_Msk /*!< Filter bit 25 */ |
9869 | #define CAN_F7R2_FB26_Pos (26U) |
| 9870 | #define CAN_F7R2_FB26_Pos (26U) |
9870 | #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ |
| 9871 | #define CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos) /*!< 0x04000000 */ |
9871 | #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */ |
| 9872 | #define CAN_F7R2_FB26 CAN_F7R2_FB26_Msk /*!< Filter bit 26 */ |
9872 | #define CAN_F7R2_FB27_Pos (27U) |
| 9873 | #define CAN_F7R2_FB27_Pos (27U) |
9873 | #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ |
| 9874 | #define CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos) /*!< 0x08000000 */ |
9874 | #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */ |
| 9875 | #define CAN_F7R2_FB27 CAN_F7R2_FB27_Msk /*!< Filter bit 27 */ |
9875 | #define CAN_F7R2_FB28_Pos (28U) |
| 9876 | #define CAN_F7R2_FB28_Pos (28U) |
9876 | #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ |
| 9877 | #define CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos) /*!< 0x10000000 */ |
9877 | #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */ |
| 9878 | #define CAN_F7R2_FB28 CAN_F7R2_FB28_Msk /*!< Filter bit 28 */ |
9878 | #define CAN_F7R2_FB29_Pos (29U) |
| 9879 | #define CAN_F7R2_FB29_Pos (29U) |
9879 | #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ |
| 9880 | #define CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos) /*!< 0x20000000 */ |
9880 | #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */ |
| 9881 | #define CAN_F7R2_FB29 CAN_F7R2_FB29_Msk /*!< Filter bit 29 */ |
9881 | #define CAN_F7R2_FB30_Pos (30U) |
| 9882 | #define CAN_F7R2_FB30_Pos (30U) |
9882 | #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ |
| 9883 | #define CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos) /*!< 0x40000000 */ |
9883 | #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */ |
| 9884 | #define CAN_F7R2_FB30 CAN_F7R2_FB30_Msk /*!< Filter bit 30 */ |
9884 | #define CAN_F7R2_FB31_Pos (31U) |
| 9885 | #define CAN_F7R2_FB31_Pos (31U) |
9885 | #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ |
| 9886 | #define CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos) /*!< 0x80000000 */ |
9886 | #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */ |
| 9887 | #define CAN_F7R2_FB31 CAN_F7R2_FB31_Msk /*!< Filter bit 31 */ |
9887 | |
| 9888 | 9888 | /******************* Bit definition for CAN_F8R2 register *******************/ |
|
| 9889 | /******************* Bit definition for CAN_F8R2 register *******************/ |
9889 | #define CAN_F8R2_FB0_Pos (0U) |
| 9890 | #define CAN_F8R2_FB0_Pos (0U) |
9890 | #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ |
| 9891 | #define CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos) /*!< 0x00000001 */ |
9891 | #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */ |
| 9892 | #define CAN_F8R2_FB0 CAN_F8R2_FB0_Msk /*!< Filter bit 0 */ |
9892 | #define CAN_F8R2_FB1_Pos (1U) |
| 9893 | #define CAN_F8R2_FB1_Pos (1U) |
9893 | #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ |
| 9894 | #define CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos) /*!< 0x00000002 */ |
9894 | #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */ |
| 9895 | #define CAN_F8R2_FB1 CAN_F8R2_FB1_Msk /*!< Filter bit 1 */ |
9895 | #define CAN_F8R2_FB2_Pos (2U) |
| 9896 | #define CAN_F8R2_FB2_Pos (2U) |
9896 | #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ |
| 9897 | #define CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos) /*!< 0x00000004 */ |
9897 | #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */ |
| 9898 | #define CAN_F8R2_FB2 CAN_F8R2_FB2_Msk /*!< Filter bit 2 */ |
9898 | #define CAN_F8R2_FB3_Pos (3U) |
| 9899 | #define CAN_F8R2_FB3_Pos (3U) |
9899 | #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ |
| 9900 | #define CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos) /*!< 0x00000008 */ |
9900 | #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */ |
| 9901 | #define CAN_F8R2_FB3 CAN_F8R2_FB3_Msk /*!< Filter bit 3 */ |
9901 | #define CAN_F8R2_FB4_Pos (4U) |
| 9902 | #define CAN_F8R2_FB4_Pos (4U) |
9902 | #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ |
| 9903 | #define CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos) /*!< 0x00000010 */ |
9903 | #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */ |
| 9904 | #define CAN_F8R2_FB4 CAN_F8R2_FB4_Msk /*!< Filter bit 4 */ |
9904 | #define CAN_F8R2_FB5_Pos (5U) |
| 9905 | #define CAN_F8R2_FB5_Pos (5U) |
9905 | #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ |
| 9906 | #define CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos) /*!< 0x00000020 */ |
9906 | #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */ |
| 9907 | #define CAN_F8R2_FB5 CAN_F8R2_FB5_Msk /*!< Filter bit 5 */ |
9907 | #define CAN_F8R2_FB6_Pos (6U) |
| 9908 | #define CAN_F8R2_FB6_Pos (6U) |
9908 | #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ |
| 9909 | #define CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos) /*!< 0x00000040 */ |
9909 | #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */ |
| 9910 | #define CAN_F8R2_FB6 CAN_F8R2_FB6_Msk /*!< Filter bit 6 */ |
9910 | #define CAN_F8R2_FB7_Pos (7U) |
| 9911 | #define CAN_F8R2_FB7_Pos (7U) |
9911 | #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ |
| 9912 | #define CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos) /*!< 0x00000080 */ |
9912 | #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */ |
| 9913 | #define CAN_F8R2_FB7 CAN_F8R2_FB7_Msk /*!< Filter bit 7 */ |
9913 | #define CAN_F8R2_FB8_Pos (8U) |
| 9914 | #define CAN_F8R2_FB8_Pos (8U) |
9914 | #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ |
| 9915 | #define CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos) /*!< 0x00000100 */ |
9915 | #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */ |
| 9916 | #define CAN_F8R2_FB8 CAN_F8R2_FB8_Msk /*!< Filter bit 8 */ |
9916 | #define CAN_F8R2_FB9_Pos (9U) |
| 9917 | #define CAN_F8R2_FB9_Pos (9U) |
9917 | #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ |
| 9918 | #define CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos) /*!< 0x00000200 */ |
9918 | #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */ |
| 9919 | #define CAN_F8R2_FB9 CAN_F8R2_FB9_Msk /*!< Filter bit 9 */ |
9919 | #define CAN_F8R2_FB10_Pos (10U) |
| 9920 | #define CAN_F8R2_FB10_Pos (10U) |
9920 | #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ |
| 9921 | #define CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos) /*!< 0x00000400 */ |
9921 | #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */ |
| 9922 | #define CAN_F8R2_FB10 CAN_F8R2_FB10_Msk /*!< Filter bit 10 */ |
9922 | #define CAN_F8R2_FB11_Pos (11U) |
| 9923 | #define CAN_F8R2_FB11_Pos (11U) |
9923 | #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ |
| 9924 | #define CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos) /*!< 0x00000800 */ |
9924 | #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */ |
| 9925 | #define CAN_F8R2_FB11 CAN_F8R2_FB11_Msk /*!< Filter bit 11 */ |
9925 | #define CAN_F8R2_FB12_Pos (12U) |
| 9926 | #define CAN_F8R2_FB12_Pos (12U) |
9926 | #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ |
| 9927 | #define CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos) /*!< 0x00001000 */ |
9927 | #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */ |
| 9928 | #define CAN_F8R2_FB12 CAN_F8R2_FB12_Msk /*!< Filter bit 12 */ |
9928 | #define CAN_F8R2_FB13_Pos (13U) |
| 9929 | #define CAN_F8R2_FB13_Pos (13U) |
9929 | #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ |
| 9930 | #define CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos) /*!< 0x00002000 */ |
9930 | #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */ |
| 9931 | #define CAN_F8R2_FB13 CAN_F8R2_FB13_Msk /*!< Filter bit 13 */ |
9931 | #define CAN_F8R2_FB14_Pos (14U) |
| 9932 | #define CAN_F8R2_FB14_Pos (14U) |
9932 | #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ |
| 9933 | #define CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos) /*!< 0x00004000 */ |
9933 | #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */ |
| 9934 | #define CAN_F8R2_FB14 CAN_F8R2_FB14_Msk /*!< Filter bit 14 */ |
9934 | #define CAN_F8R2_FB15_Pos (15U) |
| 9935 | #define CAN_F8R2_FB15_Pos (15U) |
9935 | #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ |
| 9936 | #define CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos) /*!< 0x00008000 */ |
9936 | #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */ |
| 9937 | #define CAN_F8R2_FB15 CAN_F8R2_FB15_Msk /*!< Filter bit 15 */ |
9937 | #define CAN_F8R2_FB16_Pos (16U) |
| 9938 | #define CAN_F8R2_FB16_Pos (16U) |
9938 | #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ |
| 9939 | #define CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos) /*!< 0x00010000 */ |
9939 | #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */ |
| 9940 | #define CAN_F8R2_FB16 CAN_F8R2_FB16_Msk /*!< Filter bit 16 */ |
9940 | #define CAN_F8R2_FB17_Pos (17U) |
| 9941 | #define CAN_F8R2_FB17_Pos (17U) |
9941 | #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ |
| 9942 | #define CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos) /*!< 0x00020000 */ |
9942 | #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */ |
| 9943 | #define CAN_F8R2_FB17 CAN_F8R2_FB17_Msk /*!< Filter bit 17 */ |
9943 | #define CAN_F8R2_FB18_Pos (18U) |
| 9944 | #define CAN_F8R2_FB18_Pos (18U) |
9944 | #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ |
| 9945 | #define CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos) /*!< 0x00040000 */ |
9945 | #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */ |
| 9946 | #define CAN_F8R2_FB18 CAN_F8R2_FB18_Msk /*!< Filter bit 18 */ |
9946 | #define CAN_F8R2_FB19_Pos (19U) |
| 9947 | #define CAN_F8R2_FB19_Pos (19U) |
9947 | #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ |
| 9948 | #define CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos) /*!< 0x00080000 */ |
9948 | #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */ |
| 9949 | #define CAN_F8R2_FB19 CAN_F8R2_FB19_Msk /*!< Filter bit 19 */ |
9949 | #define CAN_F8R2_FB20_Pos (20U) |
| 9950 | #define CAN_F8R2_FB20_Pos (20U) |
9950 | #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ |
| 9951 | #define CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos) /*!< 0x00100000 */ |
9951 | #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */ |
| 9952 | #define CAN_F8R2_FB20 CAN_F8R2_FB20_Msk /*!< Filter bit 20 */ |
9952 | #define CAN_F8R2_FB21_Pos (21U) |
| 9953 | #define CAN_F8R2_FB21_Pos (21U) |
9953 | #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ |
| 9954 | #define CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos) /*!< 0x00200000 */ |
9954 | #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */ |
| 9955 | #define CAN_F8R2_FB21 CAN_F8R2_FB21_Msk /*!< Filter bit 21 */ |
9955 | #define CAN_F8R2_FB22_Pos (22U) |
| 9956 | #define CAN_F8R2_FB22_Pos (22U) |
9956 | #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ |
| 9957 | #define CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos) /*!< 0x00400000 */ |
9957 | #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */ |
| 9958 | #define CAN_F8R2_FB22 CAN_F8R2_FB22_Msk /*!< Filter bit 22 */ |
9958 | #define CAN_F8R2_FB23_Pos (23U) |
| 9959 | #define CAN_F8R2_FB23_Pos (23U) |
9959 | #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ |
| 9960 | #define CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos) /*!< 0x00800000 */ |
9960 | #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */ |
| 9961 | #define CAN_F8R2_FB23 CAN_F8R2_FB23_Msk /*!< Filter bit 23 */ |
9961 | #define CAN_F8R2_FB24_Pos (24U) |
| 9962 | #define CAN_F8R2_FB24_Pos (24U) |
9962 | #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ |
| 9963 | #define CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos) /*!< 0x01000000 */ |
9963 | #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */ |
| 9964 | #define CAN_F8R2_FB24 CAN_F8R2_FB24_Msk /*!< Filter bit 24 */ |
9964 | #define CAN_F8R2_FB25_Pos (25U) |
| 9965 | #define CAN_F8R2_FB25_Pos (25U) |
9965 | #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ |
| 9966 | #define CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos) /*!< 0x02000000 */ |
9966 | #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */ |
| 9967 | #define CAN_F8R2_FB25 CAN_F8R2_FB25_Msk /*!< Filter bit 25 */ |
9967 | #define CAN_F8R2_FB26_Pos (26U) |
| 9968 | #define CAN_F8R2_FB26_Pos (26U) |
9968 | #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ |
| 9969 | #define CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos) /*!< 0x04000000 */ |
9969 | #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */ |
| 9970 | #define CAN_F8R2_FB26 CAN_F8R2_FB26_Msk /*!< Filter bit 26 */ |
9970 | #define CAN_F8R2_FB27_Pos (27U) |
| 9971 | #define CAN_F8R2_FB27_Pos (27U) |
9971 | #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ |
| 9972 | #define CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos) /*!< 0x08000000 */ |
9972 | #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */ |
| 9973 | #define CAN_F8R2_FB27 CAN_F8R2_FB27_Msk /*!< Filter bit 27 */ |
9973 | #define CAN_F8R2_FB28_Pos (28U) |
| 9974 | #define CAN_F8R2_FB28_Pos (28U) |
9974 | #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ |
| 9975 | #define CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos) /*!< 0x10000000 */ |
9975 | #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */ |
| 9976 | #define CAN_F8R2_FB28 CAN_F8R2_FB28_Msk /*!< Filter bit 28 */ |
9976 | #define CAN_F8R2_FB29_Pos (29U) |
| 9977 | #define CAN_F8R2_FB29_Pos (29U) |
9977 | #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ |
| 9978 | #define CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos) /*!< 0x20000000 */ |
9978 | #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */ |
| 9979 | #define CAN_F8R2_FB29 CAN_F8R2_FB29_Msk /*!< Filter bit 29 */ |
9979 | #define CAN_F8R2_FB30_Pos (30U) |
| 9980 | #define CAN_F8R2_FB30_Pos (30U) |
9980 | #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ |
| 9981 | #define CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos) /*!< 0x40000000 */ |
9981 | #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */ |
| 9982 | #define CAN_F8R2_FB30 CAN_F8R2_FB30_Msk /*!< Filter bit 30 */ |
9982 | #define CAN_F8R2_FB31_Pos (31U) |
| 9983 | #define CAN_F8R2_FB31_Pos (31U) |
9983 | #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ |
| 9984 | #define CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos) /*!< 0x80000000 */ |
9984 | #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */ |
| 9985 | #define CAN_F8R2_FB31 CAN_F8R2_FB31_Msk /*!< Filter bit 31 */ |
9985 | |
| 9986 | 9986 | /******************* Bit definition for CAN_F9R2 register *******************/ |
|
| 9987 | /******************* Bit definition for CAN_F9R2 register *******************/ |
9987 | #define CAN_F9R2_FB0_Pos (0U) |
| 9988 | #define CAN_F9R2_FB0_Pos (0U) |
9988 | #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ |
| 9989 | #define CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos) /*!< 0x00000001 */ |
9989 | #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */ |
| 9990 | #define CAN_F9R2_FB0 CAN_F9R2_FB0_Msk /*!< Filter bit 0 */ |
9990 | #define CAN_F9R2_FB1_Pos (1U) |
| 9991 | #define CAN_F9R2_FB1_Pos (1U) |
9991 | #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ |
| 9992 | #define CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos) /*!< 0x00000002 */ |
9992 | #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */ |
| 9993 | #define CAN_F9R2_FB1 CAN_F9R2_FB1_Msk /*!< Filter bit 1 */ |
9993 | #define CAN_F9R2_FB2_Pos (2U) |
| 9994 | #define CAN_F9R2_FB2_Pos (2U) |
9994 | #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ |
| 9995 | #define CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos) /*!< 0x00000004 */ |
9995 | #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */ |
| 9996 | #define CAN_F9R2_FB2 CAN_F9R2_FB2_Msk /*!< Filter bit 2 */ |
9996 | #define CAN_F9R2_FB3_Pos (3U) |
| 9997 | #define CAN_F9R2_FB3_Pos (3U) |
9997 | #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ |
| 9998 | #define CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos) /*!< 0x00000008 */ |
9998 | #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */ |
| 9999 | #define CAN_F9R2_FB3 CAN_F9R2_FB3_Msk /*!< Filter bit 3 */ |
9999 | #define CAN_F9R2_FB4_Pos (4U) |
| 10000 | #define CAN_F9R2_FB4_Pos (4U) |
10000 | #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ |
| 10001 | #define CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos) /*!< 0x00000010 */ |
10001 | #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */ |
| 10002 | #define CAN_F9R2_FB4 CAN_F9R2_FB4_Msk /*!< Filter bit 4 */ |
10002 | #define CAN_F9R2_FB5_Pos (5U) |
| 10003 | #define CAN_F9R2_FB5_Pos (5U) |
10003 | #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ |
| 10004 | #define CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos) /*!< 0x00000020 */ |
10004 | #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */ |
| 10005 | #define CAN_F9R2_FB5 CAN_F9R2_FB5_Msk /*!< Filter bit 5 */ |
10005 | #define CAN_F9R2_FB6_Pos (6U) |
| 10006 | #define CAN_F9R2_FB6_Pos (6U) |
10006 | #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ |
| 10007 | #define CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos) /*!< 0x00000040 */ |
10007 | #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */ |
| 10008 | #define CAN_F9R2_FB6 CAN_F9R2_FB6_Msk /*!< Filter bit 6 */ |
10008 | #define CAN_F9R2_FB7_Pos (7U) |
| 10009 | #define CAN_F9R2_FB7_Pos (7U) |
10009 | #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ |
| 10010 | #define CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos) /*!< 0x00000080 */ |
10010 | #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */ |
| 10011 | #define CAN_F9R2_FB7 CAN_F9R2_FB7_Msk /*!< Filter bit 7 */ |
10011 | #define CAN_F9R2_FB8_Pos (8U) |
| 10012 | #define CAN_F9R2_FB8_Pos (8U) |
10012 | #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ |
| 10013 | #define CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos) /*!< 0x00000100 */ |
10013 | #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */ |
| 10014 | #define CAN_F9R2_FB8 CAN_F9R2_FB8_Msk /*!< Filter bit 8 */ |
10014 | #define CAN_F9R2_FB9_Pos (9U) |
| 10015 | #define CAN_F9R2_FB9_Pos (9U) |
10015 | #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ |
| 10016 | #define CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos) /*!< 0x00000200 */ |
10016 | #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */ |
| 10017 | #define CAN_F9R2_FB9 CAN_F9R2_FB9_Msk /*!< Filter bit 9 */ |
10017 | #define CAN_F9R2_FB10_Pos (10U) |
| 10018 | #define CAN_F9R2_FB10_Pos (10U) |
10018 | #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ |
| 10019 | #define CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos) /*!< 0x00000400 */ |
10019 | #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */ |
| 10020 | #define CAN_F9R2_FB10 CAN_F9R2_FB10_Msk /*!< Filter bit 10 */ |
10020 | #define CAN_F9R2_FB11_Pos (11U) |
| 10021 | #define CAN_F9R2_FB11_Pos (11U) |
10021 | #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ |
| 10022 | #define CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos) /*!< 0x00000800 */ |
10022 | #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */ |
| 10023 | #define CAN_F9R2_FB11 CAN_F9R2_FB11_Msk /*!< Filter bit 11 */ |
10023 | #define CAN_F9R2_FB12_Pos (12U) |
| 10024 | #define CAN_F9R2_FB12_Pos (12U) |
10024 | #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ |
| 10025 | #define CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos) /*!< 0x00001000 */ |
10025 | #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */ |
| 10026 | #define CAN_F9R2_FB12 CAN_F9R2_FB12_Msk /*!< Filter bit 12 */ |
10026 | #define CAN_F9R2_FB13_Pos (13U) |
| 10027 | #define CAN_F9R2_FB13_Pos (13U) |
10027 | #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ |
| 10028 | #define CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos) /*!< 0x00002000 */ |
10028 | #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */ |
| 10029 | #define CAN_F9R2_FB13 CAN_F9R2_FB13_Msk /*!< Filter bit 13 */ |
10029 | #define CAN_F9R2_FB14_Pos (14U) |
| 10030 | #define CAN_F9R2_FB14_Pos (14U) |
10030 | #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ |
| 10031 | #define CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos) /*!< 0x00004000 */ |
10031 | #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */ |
| 10032 | #define CAN_F9R2_FB14 CAN_F9R2_FB14_Msk /*!< Filter bit 14 */ |
10032 | #define CAN_F9R2_FB15_Pos (15U) |
| 10033 | #define CAN_F9R2_FB15_Pos (15U) |
10033 | #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ |
| 10034 | #define CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos) /*!< 0x00008000 */ |
10034 | #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */ |
| 10035 | #define CAN_F9R2_FB15 CAN_F9R2_FB15_Msk /*!< Filter bit 15 */ |
10035 | #define CAN_F9R2_FB16_Pos (16U) |
| 10036 | #define CAN_F9R2_FB16_Pos (16U) |
10036 | #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ |
| 10037 | #define CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos) /*!< 0x00010000 */ |
10037 | #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */ |
| 10038 | #define CAN_F9R2_FB16 CAN_F9R2_FB16_Msk /*!< Filter bit 16 */ |
10038 | #define CAN_F9R2_FB17_Pos (17U) |
| 10039 | #define CAN_F9R2_FB17_Pos (17U) |
10039 | #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ |
| 10040 | #define CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos) /*!< 0x00020000 */ |
10040 | #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */ |
| 10041 | #define CAN_F9R2_FB17 CAN_F9R2_FB17_Msk /*!< Filter bit 17 */ |
10041 | #define CAN_F9R2_FB18_Pos (18U) |
| 10042 | #define CAN_F9R2_FB18_Pos (18U) |
10042 | #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ |
| 10043 | #define CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos) /*!< 0x00040000 */ |
10043 | #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */ |
| 10044 | #define CAN_F9R2_FB18 CAN_F9R2_FB18_Msk /*!< Filter bit 18 */ |
10044 | #define CAN_F9R2_FB19_Pos (19U) |
| 10045 | #define CAN_F9R2_FB19_Pos (19U) |
10045 | #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ |
| 10046 | #define CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos) /*!< 0x00080000 */ |
10046 | #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */ |
| 10047 | #define CAN_F9R2_FB19 CAN_F9R2_FB19_Msk /*!< Filter bit 19 */ |
10047 | #define CAN_F9R2_FB20_Pos (20U) |
| 10048 | #define CAN_F9R2_FB20_Pos (20U) |
10048 | #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ |
| 10049 | #define CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos) /*!< 0x00100000 */ |
10049 | #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */ |
| 10050 | #define CAN_F9R2_FB20 CAN_F9R2_FB20_Msk /*!< Filter bit 20 */ |
10050 | #define CAN_F9R2_FB21_Pos (21U) |
| 10051 | #define CAN_F9R2_FB21_Pos (21U) |
10051 | #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ |
| 10052 | #define CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos) /*!< 0x00200000 */ |
10052 | #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */ |
| 10053 | #define CAN_F9R2_FB21 CAN_F9R2_FB21_Msk /*!< Filter bit 21 */ |
10053 | #define CAN_F9R2_FB22_Pos (22U) |
| 10054 | #define CAN_F9R2_FB22_Pos (22U) |
10054 | #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ |
| 10055 | #define CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos) /*!< 0x00400000 */ |
10055 | #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */ |
| 10056 | #define CAN_F9R2_FB22 CAN_F9R2_FB22_Msk /*!< Filter bit 22 */ |
10056 | #define CAN_F9R2_FB23_Pos (23U) |
| 10057 | #define CAN_F9R2_FB23_Pos (23U) |
10057 | #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ |
| 10058 | #define CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos) /*!< 0x00800000 */ |
10058 | #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */ |
| 10059 | #define CAN_F9R2_FB23 CAN_F9R2_FB23_Msk /*!< Filter bit 23 */ |
10059 | #define CAN_F9R2_FB24_Pos (24U) |
| 10060 | #define CAN_F9R2_FB24_Pos (24U) |
10060 | #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ |
| 10061 | #define CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos) /*!< 0x01000000 */ |
10061 | #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */ |
| 10062 | #define CAN_F9R2_FB24 CAN_F9R2_FB24_Msk /*!< Filter bit 24 */ |
10062 | #define CAN_F9R2_FB25_Pos (25U) |
| 10063 | #define CAN_F9R2_FB25_Pos (25U) |
10063 | #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ |
| 10064 | #define CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos) /*!< 0x02000000 */ |
10064 | #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */ |
| 10065 | #define CAN_F9R2_FB25 CAN_F9R2_FB25_Msk /*!< Filter bit 25 */ |
10065 | #define CAN_F9R2_FB26_Pos (26U) |
| 10066 | #define CAN_F9R2_FB26_Pos (26U) |
10066 | #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ |
| 10067 | #define CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos) /*!< 0x04000000 */ |
10067 | #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */ |
| 10068 | #define CAN_F9R2_FB26 CAN_F9R2_FB26_Msk /*!< Filter bit 26 */ |
10068 | #define CAN_F9R2_FB27_Pos (27U) |
| 10069 | #define CAN_F9R2_FB27_Pos (27U) |
10069 | #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ |
| 10070 | #define CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos) /*!< 0x08000000 */ |
10070 | #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */ |
| 10071 | #define CAN_F9R2_FB27 CAN_F9R2_FB27_Msk /*!< Filter bit 27 */ |
10071 | #define CAN_F9R2_FB28_Pos (28U) |
| 10072 | #define CAN_F9R2_FB28_Pos (28U) |
10072 | #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ |
| 10073 | #define CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos) /*!< 0x10000000 */ |
10073 | #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */ |
| 10074 | #define CAN_F9R2_FB28 CAN_F9R2_FB28_Msk /*!< Filter bit 28 */ |
10074 | #define CAN_F9R2_FB29_Pos (29U) |
| 10075 | #define CAN_F9R2_FB29_Pos (29U) |
10075 | #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ |
| 10076 | #define CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos) /*!< 0x20000000 */ |
10076 | #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */ |
| 10077 | #define CAN_F9R2_FB29 CAN_F9R2_FB29_Msk /*!< Filter bit 29 */ |
10077 | #define CAN_F9R2_FB30_Pos (30U) |
| 10078 | #define CAN_F9R2_FB30_Pos (30U) |
10078 | #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ |
| 10079 | #define CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos) /*!< 0x40000000 */ |
10079 | #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */ |
| 10080 | #define CAN_F9R2_FB30 CAN_F9R2_FB30_Msk /*!< Filter bit 30 */ |
10080 | #define CAN_F9R2_FB31_Pos (31U) |
| 10081 | #define CAN_F9R2_FB31_Pos (31U) |
10081 | #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ |
| 10082 | #define CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos) /*!< 0x80000000 */ |
10082 | #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */ |
| 10083 | #define CAN_F9R2_FB31 CAN_F9R2_FB31_Msk /*!< Filter bit 31 */ |
10083 | |
| 10084 | 10084 | /******************* Bit definition for CAN_F10R2 register ******************/ |
|
| 10085 | /******************* Bit definition for CAN_F10R2 register ******************/ |
10085 | #define CAN_F10R2_FB0_Pos (0U) |
| 10086 | #define CAN_F10R2_FB0_Pos (0U) |
10086 | #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ |
| 10087 | #define CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos) /*!< 0x00000001 */ |
10087 | #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */ |
| 10088 | #define CAN_F10R2_FB0 CAN_F10R2_FB0_Msk /*!< Filter bit 0 */ |
10088 | #define CAN_F10R2_FB1_Pos (1U) |
| 10089 | #define CAN_F10R2_FB1_Pos (1U) |
10089 | #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ |
| 10090 | #define CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos) /*!< 0x00000002 */ |
10090 | #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */ |
| 10091 | #define CAN_F10R2_FB1 CAN_F10R2_FB1_Msk /*!< Filter bit 1 */ |
10091 | #define CAN_F10R2_FB2_Pos (2U) |
| 10092 | #define CAN_F10R2_FB2_Pos (2U) |
10092 | #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ |
| 10093 | #define CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos) /*!< 0x00000004 */ |
10093 | #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */ |
| 10094 | #define CAN_F10R2_FB2 CAN_F10R2_FB2_Msk /*!< Filter bit 2 */ |
10094 | #define CAN_F10R2_FB3_Pos (3U) |
| 10095 | #define CAN_F10R2_FB3_Pos (3U) |
10095 | #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ |
| 10096 | #define CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos) /*!< 0x00000008 */ |
10096 | #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */ |
| 10097 | #define CAN_F10R2_FB3 CAN_F10R2_FB3_Msk /*!< Filter bit 3 */ |
10097 | #define CAN_F10R2_FB4_Pos (4U) |
| 10098 | #define CAN_F10R2_FB4_Pos (4U) |
10098 | #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ |
| 10099 | #define CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos) /*!< 0x00000010 */ |
10099 | #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */ |
| 10100 | #define CAN_F10R2_FB4 CAN_F10R2_FB4_Msk /*!< Filter bit 4 */ |
10100 | #define CAN_F10R2_FB5_Pos (5U) |
| 10101 | #define CAN_F10R2_FB5_Pos (5U) |
10101 | #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ |
| 10102 | #define CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos) /*!< 0x00000020 */ |
10102 | #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */ |
| 10103 | #define CAN_F10R2_FB5 CAN_F10R2_FB5_Msk /*!< Filter bit 5 */ |
10103 | #define CAN_F10R2_FB6_Pos (6U) |
| 10104 | #define CAN_F10R2_FB6_Pos (6U) |
10104 | #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ |
| 10105 | #define CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos) /*!< 0x00000040 */ |
10105 | #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */ |
| 10106 | #define CAN_F10R2_FB6 CAN_F10R2_FB6_Msk /*!< Filter bit 6 */ |
10106 | #define CAN_F10R2_FB7_Pos (7U) |
| 10107 | #define CAN_F10R2_FB7_Pos (7U) |
10107 | #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ |
| 10108 | #define CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos) /*!< 0x00000080 */ |
10108 | #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */ |
| 10109 | #define CAN_F10R2_FB7 CAN_F10R2_FB7_Msk /*!< Filter bit 7 */ |
10109 | #define CAN_F10R2_FB8_Pos (8U) |
| 10110 | #define CAN_F10R2_FB8_Pos (8U) |
10110 | #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ |
| 10111 | #define CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos) /*!< 0x00000100 */ |
10111 | #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */ |
| 10112 | #define CAN_F10R2_FB8 CAN_F10R2_FB8_Msk /*!< Filter bit 8 */ |
10112 | #define CAN_F10R2_FB9_Pos (9U) |
| 10113 | #define CAN_F10R2_FB9_Pos (9U) |
10113 | #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ |
| 10114 | #define CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos) /*!< 0x00000200 */ |
10114 | #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */ |
| 10115 | #define CAN_F10R2_FB9 CAN_F10R2_FB9_Msk /*!< Filter bit 9 */ |
10115 | #define CAN_F10R2_FB10_Pos (10U) |
| 10116 | #define CAN_F10R2_FB10_Pos (10U) |
10116 | #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ |
| 10117 | #define CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos) /*!< 0x00000400 */ |
10117 | #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */ |
| 10118 | #define CAN_F10R2_FB10 CAN_F10R2_FB10_Msk /*!< Filter bit 10 */ |
10118 | #define CAN_F10R2_FB11_Pos (11U) |
| 10119 | #define CAN_F10R2_FB11_Pos (11U) |
10119 | #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ |
| 10120 | #define CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos) /*!< 0x00000800 */ |
10120 | #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */ |
| 10121 | #define CAN_F10R2_FB11 CAN_F10R2_FB11_Msk /*!< Filter bit 11 */ |
10121 | #define CAN_F10R2_FB12_Pos (12U) |
| 10122 | #define CAN_F10R2_FB12_Pos (12U) |
10122 | #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ |
| 10123 | #define CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos) /*!< 0x00001000 */ |
10123 | #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */ |
| 10124 | #define CAN_F10R2_FB12 CAN_F10R2_FB12_Msk /*!< Filter bit 12 */ |
10124 | #define CAN_F10R2_FB13_Pos (13U) |
| 10125 | #define CAN_F10R2_FB13_Pos (13U) |
10125 | #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ |
| 10126 | #define CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos) /*!< 0x00002000 */ |
10126 | #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */ |
| 10127 | #define CAN_F10R2_FB13 CAN_F10R2_FB13_Msk /*!< Filter bit 13 */ |
10127 | #define CAN_F10R2_FB14_Pos (14U) |
| 10128 | #define CAN_F10R2_FB14_Pos (14U) |
10128 | #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ |
| 10129 | #define CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos) /*!< 0x00004000 */ |
10129 | #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */ |
| 10130 | #define CAN_F10R2_FB14 CAN_F10R2_FB14_Msk /*!< Filter bit 14 */ |
10130 | #define CAN_F10R2_FB15_Pos (15U) |
| 10131 | #define CAN_F10R2_FB15_Pos (15U) |
10131 | #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ |
| 10132 | #define CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos) /*!< 0x00008000 */ |
10132 | #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */ |
| 10133 | #define CAN_F10R2_FB15 CAN_F10R2_FB15_Msk /*!< Filter bit 15 */ |
10133 | #define CAN_F10R2_FB16_Pos (16U) |
| 10134 | #define CAN_F10R2_FB16_Pos (16U) |
10134 | #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ |
| 10135 | #define CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos) /*!< 0x00010000 */ |
10135 | #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */ |
| 10136 | #define CAN_F10R2_FB16 CAN_F10R2_FB16_Msk /*!< Filter bit 16 */ |
10136 | #define CAN_F10R2_FB17_Pos (17U) |
| 10137 | #define CAN_F10R2_FB17_Pos (17U) |
10137 | #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ |
| 10138 | #define CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos) /*!< 0x00020000 */ |
10138 | #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */ |
| 10139 | #define CAN_F10R2_FB17 CAN_F10R2_FB17_Msk /*!< Filter bit 17 */ |
10139 | #define CAN_F10R2_FB18_Pos (18U) |
| 10140 | #define CAN_F10R2_FB18_Pos (18U) |
10140 | #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ |
| 10141 | #define CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos) /*!< 0x00040000 */ |
10141 | #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */ |
| 10142 | #define CAN_F10R2_FB18 CAN_F10R2_FB18_Msk /*!< Filter bit 18 */ |
10142 | #define CAN_F10R2_FB19_Pos (19U) |
| 10143 | #define CAN_F10R2_FB19_Pos (19U) |
10143 | #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ |
| 10144 | #define CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos) /*!< 0x00080000 */ |
10144 | #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */ |
| 10145 | #define CAN_F10R2_FB19 CAN_F10R2_FB19_Msk /*!< Filter bit 19 */ |
10145 | #define CAN_F10R2_FB20_Pos (20U) |
| 10146 | #define CAN_F10R2_FB20_Pos (20U) |
10146 | #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ |
| 10147 | #define CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos) /*!< 0x00100000 */ |
10147 | #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */ |
| 10148 | #define CAN_F10R2_FB20 CAN_F10R2_FB20_Msk /*!< Filter bit 20 */ |
10148 | #define CAN_F10R2_FB21_Pos (21U) |
| 10149 | #define CAN_F10R2_FB21_Pos (21U) |
10149 | #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ |
| 10150 | #define CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos) /*!< 0x00200000 */ |
10150 | #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */ |
| 10151 | #define CAN_F10R2_FB21 CAN_F10R2_FB21_Msk /*!< Filter bit 21 */ |
10151 | #define CAN_F10R2_FB22_Pos (22U) |
| 10152 | #define CAN_F10R2_FB22_Pos (22U) |
10152 | #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ |
| 10153 | #define CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos) /*!< 0x00400000 */ |
10153 | #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */ |
| 10154 | #define CAN_F10R2_FB22 CAN_F10R2_FB22_Msk /*!< Filter bit 22 */ |
10154 | #define CAN_F10R2_FB23_Pos (23U) |
| 10155 | #define CAN_F10R2_FB23_Pos (23U) |
10155 | #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ |
| 10156 | #define CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos) /*!< 0x00800000 */ |
10156 | #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */ |
| 10157 | #define CAN_F10R2_FB23 CAN_F10R2_FB23_Msk /*!< Filter bit 23 */ |
10157 | #define CAN_F10R2_FB24_Pos (24U) |
| 10158 | #define CAN_F10R2_FB24_Pos (24U) |
10158 | #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ |
| 10159 | #define CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos) /*!< 0x01000000 */ |
10159 | #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */ |
| 10160 | #define CAN_F10R2_FB24 CAN_F10R2_FB24_Msk /*!< Filter bit 24 */ |
10160 | #define CAN_F10R2_FB25_Pos (25U) |
| 10161 | #define CAN_F10R2_FB25_Pos (25U) |
10161 | #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ |
| 10162 | #define CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos) /*!< 0x02000000 */ |
10162 | #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */ |
| 10163 | #define CAN_F10R2_FB25 CAN_F10R2_FB25_Msk /*!< Filter bit 25 */ |
10163 | #define CAN_F10R2_FB26_Pos (26U) |
| 10164 | #define CAN_F10R2_FB26_Pos (26U) |
10164 | #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ |
| 10165 | #define CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos) /*!< 0x04000000 */ |
10165 | #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */ |
| 10166 | #define CAN_F10R2_FB26 CAN_F10R2_FB26_Msk /*!< Filter bit 26 */ |
10166 | #define CAN_F10R2_FB27_Pos (27U) |
| 10167 | #define CAN_F10R2_FB27_Pos (27U) |
10167 | #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ |
| 10168 | #define CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos) /*!< 0x08000000 */ |
10168 | #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */ |
| 10169 | #define CAN_F10R2_FB27 CAN_F10R2_FB27_Msk /*!< Filter bit 27 */ |
10169 | #define CAN_F10R2_FB28_Pos (28U) |
| 10170 | #define CAN_F10R2_FB28_Pos (28U) |
10170 | #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ |
| 10171 | #define CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos) /*!< 0x10000000 */ |
10171 | #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */ |
| 10172 | #define CAN_F10R2_FB28 CAN_F10R2_FB28_Msk /*!< Filter bit 28 */ |
10172 | #define CAN_F10R2_FB29_Pos (29U) |
| 10173 | #define CAN_F10R2_FB29_Pos (29U) |
10173 | #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ |
| 10174 | #define CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos) /*!< 0x20000000 */ |
10174 | #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */ |
| 10175 | #define CAN_F10R2_FB29 CAN_F10R2_FB29_Msk /*!< Filter bit 29 */ |
10175 | #define CAN_F10R2_FB30_Pos (30U) |
| 10176 | #define CAN_F10R2_FB30_Pos (30U) |
10176 | #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ |
| 10177 | #define CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos) /*!< 0x40000000 */ |
10177 | #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */ |
| 10178 | #define CAN_F10R2_FB30 CAN_F10R2_FB30_Msk /*!< Filter bit 30 */ |
10178 | #define CAN_F10R2_FB31_Pos (31U) |
| 10179 | #define CAN_F10R2_FB31_Pos (31U) |
10179 | #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ |
| 10180 | #define CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos) /*!< 0x80000000 */ |
10180 | #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */ |
| 10181 | #define CAN_F10R2_FB31 CAN_F10R2_FB31_Msk /*!< Filter bit 31 */ |
10181 | |
| 10182 | 10182 | /******************* Bit definition for CAN_F11R2 register ******************/ |
|
| 10183 | /******************* Bit definition for CAN_F11R2 register ******************/ |
10183 | #define CAN_F11R2_FB0_Pos (0U) |
| 10184 | #define CAN_F11R2_FB0_Pos (0U) |
10184 | #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ |
| 10185 | #define CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos) /*!< 0x00000001 */ |
10185 | #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */ |
| 10186 | #define CAN_F11R2_FB0 CAN_F11R2_FB0_Msk /*!< Filter bit 0 */ |
10186 | #define CAN_F11R2_FB1_Pos (1U) |
| 10187 | #define CAN_F11R2_FB1_Pos (1U) |
10187 | #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ |
| 10188 | #define CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos) /*!< 0x00000002 */ |
10188 | #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */ |
| 10189 | #define CAN_F11R2_FB1 CAN_F11R2_FB1_Msk /*!< Filter bit 1 */ |
10189 | #define CAN_F11R2_FB2_Pos (2U) |
| 10190 | #define CAN_F11R2_FB2_Pos (2U) |
10190 | #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ |
| 10191 | #define CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos) /*!< 0x00000004 */ |
10191 | #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */ |
| 10192 | #define CAN_F11R2_FB2 CAN_F11R2_FB2_Msk /*!< Filter bit 2 */ |
10192 | #define CAN_F11R2_FB3_Pos (3U) |
| 10193 | #define CAN_F11R2_FB3_Pos (3U) |
10193 | #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ |
| 10194 | #define CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos) /*!< 0x00000008 */ |
10194 | #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */ |
| 10195 | #define CAN_F11R2_FB3 CAN_F11R2_FB3_Msk /*!< Filter bit 3 */ |
10195 | #define CAN_F11R2_FB4_Pos (4U) |
| 10196 | #define CAN_F11R2_FB4_Pos (4U) |
10196 | #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ |
| 10197 | #define CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos) /*!< 0x00000010 */ |
10197 | #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */ |
| 10198 | #define CAN_F11R2_FB4 CAN_F11R2_FB4_Msk /*!< Filter bit 4 */ |
10198 | #define CAN_F11R2_FB5_Pos (5U) |
| 10199 | #define CAN_F11R2_FB5_Pos (5U) |
10199 | #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ |
| 10200 | #define CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos) /*!< 0x00000020 */ |
10200 | #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */ |
| 10201 | #define CAN_F11R2_FB5 CAN_F11R2_FB5_Msk /*!< Filter bit 5 */ |
10201 | #define CAN_F11R2_FB6_Pos (6U) |
| 10202 | #define CAN_F11R2_FB6_Pos (6U) |
10202 | #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ |
| 10203 | #define CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos) /*!< 0x00000040 */ |
10203 | #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */ |
| 10204 | #define CAN_F11R2_FB6 CAN_F11R2_FB6_Msk /*!< Filter bit 6 */ |
10204 | #define CAN_F11R2_FB7_Pos (7U) |
| 10205 | #define CAN_F11R2_FB7_Pos (7U) |
10205 | #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ |
| 10206 | #define CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos) /*!< 0x00000080 */ |
10206 | #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */ |
| 10207 | #define CAN_F11R2_FB7 CAN_F11R2_FB7_Msk /*!< Filter bit 7 */ |
10207 | #define CAN_F11R2_FB8_Pos (8U) |
| 10208 | #define CAN_F11R2_FB8_Pos (8U) |
10208 | #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ |
| 10209 | #define CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos) /*!< 0x00000100 */ |
10209 | #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */ |
| 10210 | #define CAN_F11R2_FB8 CAN_F11R2_FB8_Msk /*!< Filter bit 8 */ |
10210 | #define CAN_F11R2_FB9_Pos (9U) |
| 10211 | #define CAN_F11R2_FB9_Pos (9U) |
10211 | #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ |
| 10212 | #define CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos) /*!< 0x00000200 */ |
10212 | #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */ |
| 10213 | #define CAN_F11R2_FB9 CAN_F11R2_FB9_Msk /*!< Filter bit 9 */ |
10213 | #define CAN_F11R2_FB10_Pos (10U) |
| 10214 | #define CAN_F11R2_FB10_Pos (10U) |
10214 | #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ |
| 10215 | #define CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos) /*!< 0x00000400 */ |
10215 | #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */ |
| 10216 | #define CAN_F11R2_FB10 CAN_F11R2_FB10_Msk /*!< Filter bit 10 */ |
10216 | #define CAN_F11R2_FB11_Pos (11U) |
| 10217 | #define CAN_F11R2_FB11_Pos (11U) |
10217 | #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ |
| 10218 | #define CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos) /*!< 0x00000800 */ |
10218 | #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */ |
| 10219 | #define CAN_F11R2_FB11 CAN_F11R2_FB11_Msk /*!< Filter bit 11 */ |
10219 | #define CAN_F11R2_FB12_Pos (12U) |
| 10220 | #define CAN_F11R2_FB12_Pos (12U) |
10220 | #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ |
| 10221 | #define CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos) /*!< 0x00001000 */ |
10221 | #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */ |
| 10222 | #define CAN_F11R2_FB12 CAN_F11R2_FB12_Msk /*!< Filter bit 12 */ |
10222 | #define CAN_F11R2_FB13_Pos (13U) |
| 10223 | #define CAN_F11R2_FB13_Pos (13U) |
10223 | #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ |
| 10224 | #define CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos) /*!< 0x00002000 */ |
10224 | #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */ |
| 10225 | #define CAN_F11R2_FB13 CAN_F11R2_FB13_Msk /*!< Filter bit 13 */ |
10225 | #define CAN_F11R2_FB14_Pos (14U) |
| 10226 | #define CAN_F11R2_FB14_Pos (14U) |
10226 | #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ |
| 10227 | #define CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos) /*!< 0x00004000 */ |
10227 | #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */ |
| 10228 | #define CAN_F11R2_FB14 CAN_F11R2_FB14_Msk /*!< Filter bit 14 */ |
10228 | #define CAN_F11R2_FB15_Pos (15U) |
| 10229 | #define CAN_F11R2_FB15_Pos (15U) |
10229 | #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ |
| 10230 | #define CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos) /*!< 0x00008000 */ |
10230 | #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */ |
| 10231 | #define CAN_F11R2_FB15 CAN_F11R2_FB15_Msk /*!< Filter bit 15 */ |
10231 | #define CAN_F11R2_FB16_Pos (16U) |
| 10232 | #define CAN_F11R2_FB16_Pos (16U) |
10232 | #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ |
| 10233 | #define CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos) /*!< 0x00010000 */ |
10233 | #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */ |
| 10234 | #define CAN_F11R2_FB16 CAN_F11R2_FB16_Msk /*!< Filter bit 16 */ |
10234 | #define CAN_F11R2_FB17_Pos (17U) |
| 10235 | #define CAN_F11R2_FB17_Pos (17U) |
10235 | #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ |
| 10236 | #define CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos) /*!< 0x00020000 */ |
10236 | #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */ |
| 10237 | #define CAN_F11R2_FB17 CAN_F11R2_FB17_Msk /*!< Filter bit 17 */ |
10237 | #define CAN_F11R2_FB18_Pos (18U) |
| 10238 | #define CAN_F11R2_FB18_Pos (18U) |
10238 | #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ |
| 10239 | #define CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos) /*!< 0x00040000 */ |
10239 | #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */ |
| 10240 | #define CAN_F11R2_FB18 CAN_F11R2_FB18_Msk /*!< Filter bit 18 */ |
10240 | #define CAN_F11R2_FB19_Pos (19U) |
| 10241 | #define CAN_F11R2_FB19_Pos (19U) |
10241 | #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ |
| 10242 | #define CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos) /*!< 0x00080000 */ |
10242 | #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */ |
| 10243 | #define CAN_F11R2_FB19 CAN_F11R2_FB19_Msk /*!< Filter bit 19 */ |
10243 | #define CAN_F11R2_FB20_Pos (20U) |
| 10244 | #define CAN_F11R2_FB20_Pos (20U) |
10244 | #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ |
| 10245 | #define CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos) /*!< 0x00100000 */ |
10245 | #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */ |
| 10246 | #define CAN_F11R2_FB20 CAN_F11R2_FB20_Msk /*!< Filter bit 20 */ |
10246 | #define CAN_F11R2_FB21_Pos (21U) |
| 10247 | #define CAN_F11R2_FB21_Pos (21U) |
10247 | #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ |
| 10248 | #define CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos) /*!< 0x00200000 */ |
10248 | #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */ |
| 10249 | #define CAN_F11R2_FB21 CAN_F11R2_FB21_Msk /*!< Filter bit 21 */ |
10249 | #define CAN_F11R2_FB22_Pos (22U) |
| 10250 | #define CAN_F11R2_FB22_Pos (22U) |
10250 | #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ |
| 10251 | #define CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos) /*!< 0x00400000 */ |
10251 | #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */ |
| 10252 | #define CAN_F11R2_FB22 CAN_F11R2_FB22_Msk /*!< Filter bit 22 */ |
10252 | #define CAN_F11R2_FB23_Pos (23U) |
| 10253 | #define CAN_F11R2_FB23_Pos (23U) |
10253 | #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ |
| 10254 | #define CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos) /*!< 0x00800000 */ |
10254 | #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */ |
| 10255 | #define CAN_F11R2_FB23 CAN_F11R2_FB23_Msk /*!< Filter bit 23 */ |
10255 | #define CAN_F11R2_FB24_Pos (24U) |
| 10256 | #define CAN_F11R2_FB24_Pos (24U) |
10256 | #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ |
| 10257 | #define CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos) /*!< 0x01000000 */ |
10257 | #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */ |
| 10258 | #define CAN_F11R2_FB24 CAN_F11R2_FB24_Msk /*!< Filter bit 24 */ |
10258 | #define CAN_F11R2_FB25_Pos (25U) |
| 10259 | #define CAN_F11R2_FB25_Pos (25U) |
10259 | #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ |
| 10260 | #define CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos) /*!< 0x02000000 */ |
10260 | #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */ |
| 10261 | #define CAN_F11R2_FB25 CAN_F11R2_FB25_Msk /*!< Filter bit 25 */ |
10261 | #define CAN_F11R2_FB26_Pos (26U) |
| 10262 | #define CAN_F11R2_FB26_Pos (26U) |
10262 | #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ |
| 10263 | #define CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos) /*!< 0x04000000 */ |
10263 | #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */ |
| 10264 | #define CAN_F11R2_FB26 CAN_F11R2_FB26_Msk /*!< Filter bit 26 */ |
10264 | #define CAN_F11R2_FB27_Pos (27U) |
| 10265 | #define CAN_F11R2_FB27_Pos (27U) |
10265 | #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ |
| 10266 | #define CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos) /*!< 0x08000000 */ |
10266 | #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */ |
| 10267 | #define CAN_F11R2_FB27 CAN_F11R2_FB27_Msk /*!< Filter bit 27 */ |
10267 | #define CAN_F11R2_FB28_Pos (28U) |
| 10268 | #define CAN_F11R2_FB28_Pos (28U) |
10268 | #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ |
| 10269 | #define CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos) /*!< 0x10000000 */ |
10269 | #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */ |
| 10270 | #define CAN_F11R2_FB28 CAN_F11R2_FB28_Msk /*!< Filter bit 28 */ |
10270 | #define CAN_F11R2_FB29_Pos (29U) |
| 10271 | #define CAN_F11R2_FB29_Pos (29U) |
10271 | #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ |
| 10272 | #define CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos) /*!< 0x20000000 */ |
10272 | #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */ |
| 10273 | #define CAN_F11R2_FB29 CAN_F11R2_FB29_Msk /*!< Filter bit 29 */ |
10273 | #define CAN_F11R2_FB30_Pos (30U) |
| 10274 | #define CAN_F11R2_FB30_Pos (30U) |
10274 | #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ |
| 10275 | #define CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos) /*!< 0x40000000 */ |
10275 | #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */ |
| 10276 | #define CAN_F11R2_FB30 CAN_F11R2_FB30_Msk /*!< Filter bit 30 */ |
10276 | #define CAN_F11R2_FB31_Pos (31U) |
| 10277 | #define CAN_F11R2_FB31_Pos (31U) |
10277 | #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ |
| 10278 | #define CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos) /*!< 0x80000000 */ |
10278 | #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */ |
| 10279 | #define CAN_F11R2_FB31 CAN_F11R2_FB31_Msk /*!< Filter bit 31 */ |
10279 | |
| 10280 | 10280 | /******************* Bit definition for CAN_F12R2 register ******************/ |
|
| 10281 | /******************* Bit definition for CAN_F12R2 register ******************/ |
10281 | #define CAN_F12R2_FB0_Pos (0U) |
| 10282 | #define CAN_F12R2_FB0_Pos (0U) |
10282 | #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ |
| 10283 | #define CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos) /*!< 0x00000001 */ |
10283 | #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */ |
| 10284 | #define CAN_F12R2_FB0 CAN_F12R2_FB0_Msk /*!< Filter bit 0 */ |
10284 | #define CAN_F12R2_FB1_Pos (1U) |
| 10285 | #define CAN_F12R2_FB1_Pos (1U) |
10285 | #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ |
| 10286 | #define CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos) /*!< 0x00000002 */ |
10286 | #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */ |
| 10287 | #define CAN_F12R2_FB1 CAN_F12R2_FB1_Msk /*!< Filter bit 1 */ |
10287 | #define CAN_F12R2_FB2_Pos (2U) |
| 10288 | #define CAN_F12R2_FB2_Pos (2U) |
10288 | #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ |
| 10289 | #define CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos) /*!< 0x00000004 */ |
10289 | #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */ |
| 10290 | #define CAN_F12R2_FB2 CAN_F12R2_FB2_Msk /*!< Filter bit 2 */ |
10290 | #define CAN_F12R2_FB3_Pos (3U) |
| 10291 | #define CAN_F12R2_FB3_Pos (3U) |
10291 | #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ |
| 10292 | #define CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos) /*!< 0x00000008 */ |
10292 | #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */ |
| 10293 | #define CAN_F12R2_FB3 CAN_F12R2_FB3_Msk /*!< Filter bit 3 */ |
10293 | #define CAN_F12R2_FB4_Pos (4U) |
| 10294 | #define CAN_F12R2_FB4_Pos (4U) |
10294 | #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ |
| 10295 | #define CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos) /*!< 0x00000010 */ |
10295 | #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */ |
| 10296 | #define CAN_F12R2_FB4 CAN_F12R2_FB4_Msk /*!< Filter bit 4 */ |
10296 | #define CAN_F12R2_FB5_Pos (5U) |
| 10297 | #define CAN_F12R2_FB5_Pos (5U) |
10297 | #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ |
| 10298 | #define CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos) /*!< 0x00000020 */ |
10298 | #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */ |
| 10299 | #define CAN_F12R2_FB5 CAN_F12R2_FB5_Msk /*!< Filter bit 5 */ |
10299 | #define CAN_F12R2_FB6_Pos (6U) |
| 10300 | #define CAN_F12R2_FB6_Pos (6U) |
10300 | #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ |
| 10301 | #define CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos) /*!< 0x00000040 */ |
10301 | #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */ |
| 10302 | #define CAN_F12R2_FB6 CAN_F12R2_FB6_Msk /*!< Filter bit 6 */ |
10302 | #define CAN_F12R2_FB7_Pos (7U) |
| 10303 | #define CAN_F12R2_FB7_Pos (7U) |
10303 | #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ |
| 10304 | #define CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos) /*!< 0x00000080 */ |
10304 | #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */ |
| 10305 | #define CAN_F12R2_FB7 CAN_F12R2_FB7_Msk /*!< Filter bit 7 */ |
10305 | #define CAN_F12R2_FB8_Pos (8U) |
| 10306 | #define CAN_F12R2_FB8_Pos (8U) |
10306 | #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ |
| 10307 | #define CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos) /*!< 0x00000100 */ |
10307 | #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */ |
| 10308 | #define CAN_F12R2_FB8 CAN_F12R2_FB8_Msk /*!< Filter bit 8 */ |
10308 | #define CAN_F12R2_FB9_Pos (9U) |
| 10309 | #define CAN_F12R2_FB9_Pos (9U) |
10309 | #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ |
| 10310 | #define CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos) /*!< 0x00000200 */ |
10310 | #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */ |
| 10311 | #define CAN_F12R2_FB9 CAN_F12R2_FB9_Msk /*!< Filter bit 9 */ |
10311 | #define CAN_F12R2_FB10_Pos (10U) |
| 10312 | #define CAN_F12R2_FB10_Pos (10U) |
10312 | #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ |
| 10313 | #define CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos) /*!< 0x00000400 */ |
10313 | #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */ |
| 10314 | #define CAN_F12R2_FB10 CAN_F12R2_FB10_Msk /*!< Filter bit 10 */ |
10314 | #define CAN_F12R2_FB11_Pos (11U) |
| 10315 | #define CAN_F12R2_FB11_Pos (11U) |
10315 | #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ |
| 10316 | #define CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos) /*!< 0x00000800 */ |
10316 | #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */ |
| 10317 | #define CAN_F12R2_FB11 CAN_F12R2_FB11_Msk /*!< Filter bit 11 */ |
10317 | #define CAN_F12R2_FB12_Pos (12U) |
| 10318 | #define CAN_F12R2_FB12_Pos (12U) |
10318 | #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ |
| 10319 | #define CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos) /*!< 0x00001000 */ |
10319 | #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */ |
| 10320 | #define CAN_F12R2_FB12 CAN_F12R2_FB12_Msk /*!< Filter bit 12 */ |
10320 | #define CAN_F12R2_FB13_Pos (13U) |
| 10321 | #define CAN_F12R2_FB13_Pos (13U) |
10321 | #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ |
| 10322 | #define CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos) /*!< 0x00002000 */ |
10322 | #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */ |
| 10323 | #define CAN_F12R2_FB13 CAN_F12R2_FB13_Msk /*!< Filter bit 13 */ |
10323 | #define CAN_F12R2_FB14_Pos (14U) |
| 10324 | #define CAN_F12R2_FB14_Pos (14U) |
10324 | #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ |
| 10325 | #define CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos) /*!< 0x00004000 */ |
10325 | #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */ |
| 10326 | #define CAN_F12R2_FB14 CAN_F12R2_FB14_Msk /*!< Filter bit 14 */ |
10326 | #define CAN_F12R2_FB15_Pos (15U) |
| 10327 | #define CAN_F12R2_FB15_Pos (15U) |
10327 | #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ |
| 10328 | #define CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos) /*!< 0x00008000 */ |
10328 | #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */ |
| 10329 | #define CAN_F12R2_FB15 CAN_F12R2_FB15_Msk /*!< Filter bit 15 */ |
10329 | #define CAN_F12R2_FB16_Pos (16U) |
| 10330 | #define CAN_F12R2_FB16_Pos (16U) |
10330 | #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ |
| 10331 | #define CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos) /*!< 0x00010000 */ |
10331 | #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */ |
| 10332 | #define CAN_F12R2_FB16 CAN_F12R2_FB16_Msk /*!< Filter bit 16 */ |
10332 | #define CAN_F12R2_FB17_Pos (17U) |
| 10333 | #define CAN_F12R2_FB17_Pos (17U) |
10333 | #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ |
| 10334 | #define CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos) /*!< 0x00020000 */ |
10334 | #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */ |
| 10335 | #define CAN_F12R2_FB17 CAN_F12R2_FB17_Msk /*!< Filter bit 17 */ |
10335 | #define CAN_F12R2_FB18_Pos (18U) |
| 10336 | #define CAN_F12R2_FB18_Pos (18U) |
10336 | #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ |
| 10337 | #define CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos) /*!< 0x00040000 */ |
10337 | #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */ |
| 10338 | #define CAN_F12R2_FB18 CAN_F12R2_FB18_Msk /*!< Filter bit 18 */ |
10338 | #define CAN_F12R2_FB19_Pos (19U) |
| 10339 | #define CAN_F12R2_FB19_Pos (19U) |
10339 | #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ |
| 10340 | #define CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos) /*!< 0x00080000 */ |
10340 | #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */ |
| 10341 | #define CAN_F12R2_FB19 CAN_F12R2_FB19_Msk /*!< Filter bit 19 */ |
10341 | #define CAN_F12R2_FB20_Pos (20U) |
| 10342 | #define CAN_F12R2_FB20_Pos (20U) |
10342 | #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ |
| 10343 | #define CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos) /*!< 0x00100000 */ |
10343 | #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */ |
| 10344 | #define CAN_F12R2_FB20 CAN_F12R2_FB20_Msk /*!< Filter bit 20 */ |
10344 | #define CAN_F12R2_FB21_Pos (21U) |
| 10345 | #define CAN_F12R2_FB21_Pos (21U) |
10345 | #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ |
| 10346 | #define CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos) /*!< 0x00200000 */ |
10346 | #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */ |
| 10347 | #define CAN_F12R2_FB21 CAN_F12R2_FB21_Msk /*!< Filter bit 21 */ |
10347 | #define CAN_F12R2_FB22_Pos (22U) |
| 10348 | #define CAN_F12R2_FB22_Pos (22U) |
10348 | #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ |
| 10349 | #define CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos) /*!< 0x00400000 */ |
10349 | #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */ |
| 10350 | #define CAN_F12R2_FB22 CAN_F12R2_FB22_Msk /*!< Filter bit 22 */ |
10350 | #define CAN_F12R2_FB23_Pos (23U) |
| 10351 | #define CAN_F12R2_FB23_Pos (23U) |
10351 | #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ |
| 10352 | #define CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos) /*!< 0x00800000 */ |
10352 | #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */ |
| 10353 | #define CAN_F12R2_FB23 CAN_F12R2_FB23_Msk /*!< Filter bit 23 */ |
10353 | #define CAN_F12R2_FB24_Pos (24U) |
| 10354 | #define CAN_F12R2_FB24_Pos (24U) |
10354 | #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ |
| 10355 | #define CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos) /*!< 0x01000000 */ |
10355 | #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */ |
| 10356 | #define CAN_F12R2_FB24 CAN_F12R2_FB24_Msk /*!< Filter bit 24 */ |
10356 | #define CAN_F12R2_FB25_Pos (25U) |
| 10357 | #define CAN_F12R2_FB25_Pos (25U) |
10357 | #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ |
| 10358 | #define CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos) /*!< 0x02000000 */ |
10358 | #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */ |
| 10359 | #define CAN_F12R2_FB25 CAN_F12R2_FB25_Msk /*!< Filter bit 25 */ |
10359 | #define CAN_F12R2_FB26_Pos (26U) |
| 10360 | #define CAN_F12R2_FB26_Pos (26U) |
10360 | #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ |
| 10361 | #define CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos) /*!< 0x04000000 */ |
10361 | #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */ |
| 10362 | #define CAN_F12R2_FB26 CAN_F12R2_FB26_Msk /*!< Filter bit 26 */ |
10362 | #define CAN_F12R2_FB27_Pos (27U) |
| 10363 | #define CAN_F12R2_FB27_Pos (27U) |
10363 | #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ |
| 10364 | #define CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos) /*!< 0x08000000 */ |
10364 | #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */ |
| 10365 | #define CAN_F12R2_FB27 CAN_F12R2_FB27_Msk /*!< Filter bit 27 */ |
10365 | #define CAN_F12R2_FB28_Pos (28U) |
| 10366 | #define CAN_F12R2_FB28_Pos (28U) |
10366 | #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ |
| 10367 | #define CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos) /*!< 0x10000000 */ |
10367 | #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */ |
| 10368 | #define CAN_F12R2_FB28 CAN_F12R2_FB28_Msk /*!< Filter bit 28 */ |
10368 | #define CAN_F12R2_FB29_Pos (29U) |
| 10369 | #define CAN_F12R2_FB29_Pos (29U) |
10369 | #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ |
| 10370 | #define CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos) /*!< 0x20000000 */ |
10370 | #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */ |
| 10371 | #define CAN_F12R2_FB29 CAN_F12R2_FB29_Msk /*!< Filter bit 29 */ |
10371 | #define CAN_F12R2_FB30_Pos (30U) |
| 10372 | #define CAN_F12R2_FB30_Pos (30U) |
10372 | #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ |
| 10373 | #define CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos) /*!< 0x40000000 */ |
10373 | #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */ |
| 10374 | #define CAN_F12R2_FB30 CAN_F12R2_FB30_Msk /*!< Filter bit 30 */ |
10374 | #define CAN_F12R2_FB31_Pos (31U) |
| 10375 | #define CAN_F12R2_FB31_Pos (31U) |
10375 | #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ |
| 10376 | #define CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos) /*!< 0x80000000 */ |
10376 | #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */ |
| 10377 | #define CAN_F12R2_FB31 CAN_F12R2_FB31_Msk /*!< Filter bit 31 */ |
10377 | |
| 10378 | 10378 | /******************* Bit definition for CAN_F13R2 register ******************/ |
|
| 10379 | /******************* Bit definition for CAN_F13R2 register ******************/ |
10379 | #define CAN_F13R2_FB0_Pos (0U) |
| 10380 | #define CAN_F13R2_FB0_Pos (0U) |
10380 | #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ |
| 10381 | #define CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos) /*!< 0x00000001 */ |
10381 | #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */ |
| 10382 | #define CAN_F13R2_FB0 CAN_F13R2_FB0_Msk /*!< Filter bit 0 */ |
10382 | #define CAN_F13R2_FB1_Pos (1U) |
| 10383 | #define CAN_F13R2_FB1_Pos (1U) |
10383 | #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ |
| 10384 | #define CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos) /*!< 0x00000002 */ |
10384 | #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */ |
| 10385 | #define CAN_F13R2_FB1 CAN_F13R2_FB1_Msk /*!< Filter bit 1 */ |
10385 | #define CAN_F13R2_FB2_Pos (2U) |
| 10386 | #define CAN_F13R2_FB2_Pos (2U) |
10386 | #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ |
| 10387 | #define CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos) /*!< 0x00000004 */ |
10387 | #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */ |
| 10388 | #define CAN_F13R2_FB2 CAN_F13R2_FB2_Msk /*!< Filter bit 2 */ |
10388 | #define CAN_F13R2_FB3_Pos (3U) |
| 10389 | #define CAN_F13R2_FB3_Pos (3U) |
10389 | #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ |
| 10390 | #define CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos) /*!< 0x00000008 */ |
10390 | #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */ |
| 10391 | #define CAN_F13R2_FB3 CAN_F13R2_FB3_Msk /*!< Filter bit 3 */ |
10391 | #define CAN_F13R2_FB4_Pos (4U) |
| 10392 | #define CAN_F13R2_FB4_Pos (4U) |
10392 | #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ |
| 10393 | #define CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos) /*!< 0x00000010 */ |
10393 | #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */ |
| 10394 | #define CAN_F13R2_FB4 CAN_F13R2_FB4_Msk /*!< Filter bit 4 */ |
10394 | #define CAN_F13R2_FB5_Pos (5U) |
| 10395 | #define CAN_F13R2_FB5_Pos (5U) |
10395 | #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ |
| 10396 | #define CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos) /*!< 0x00000020 */ |
10396 | #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */ |
| 10397 | #define CAN_F13R2_FB5 CAN_F13R2_FB5_Msk /*!< Filter bit 5 */ |
10397 | #define CAN_F13R2_FB6_Pos (6U) |
| 10398 | #define CAN_F13R2_FB6_Pos (6U) |
10398 | #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ |
| 10399 | #define CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos) /*!< 0x00000040 */ |
10399 | #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */ |
| 10400 | #define CAN_F13R2_FB6 CAN_F13R2_FB6_Msk /*!< Filter bit 6 */ |
10400 | #define CAN_F13R2_FB7_Pos (7U) |
| 10401 | #define CAN_F13R2_FB7_Pos (7U) |
10401 | #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ |
| 10402 | #define CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos) /*!< 0x00000080 */ |
10402 | #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */ |
| 10403 | #define CAN_F13R2_FB7 CAN_F13R2_FB7_Msk /*!< Filter bit 7 */ |
10403 | #define CAN_F13R2_FB8_Pos (8U) |
| 10404 | #define CAN_F13R2_FB8_Pos (8U) |
10404 | #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ |
| 10405 | #define CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos) /*!< 0x00000100 */ |
10405 | #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */ |
| 10406 | #define CAN_F13R2_FB8 CAN_F13R2_FB8_Msk /*!< Filter bit 8 */ |
10406 | #define CAN_F13R2_FB9_Pos (9U) |
| 10407 | #define CAN_F13R2_FB9_Pos (9U) |
10407 | #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ |
| 10408 | #define CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos) /*!< 0x00000200 */ |
10408 | #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */ |
| 10409 | #define CAN_F13R2_FB9 CAN_F13R2_FB9_Msk /*!< Filter bit 9 */ |
10409 | #define CAN_F13R2_FB10_Pos (10U) |
| 10410 | #define CAN_F13R2_FB10_Pos (10U) |
10410 | #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ |
| 10411 | #define CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos) /*!< 0x00000400 */ |
10411 | #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */ |
| 10412 | #define CAN_F13R2_FB10 CAN_F13R2_FB10_Msk /*!< Filter bit 10 */ |
10412 | #define CAN_F13R2_FB11_Pos (11U) |
| 10413 | #define CAN_F13R2_FB11_Pos (11U) |
10413 | #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ |
| 10414 | #define CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos) /*!< 0x00000800 */ |
10414 | #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */ |
| 10415 | #define CAN_F13R2_FB11 CAN_F13R2_FB11_Msk /*!< Filter bit 11 */ |
10415 | #define CAN_F13R2_FB12_Pos (12U) |
| 10416 | #define CAN_F13R2_FB12_Pos (12U) |
10416 | #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ |
| 10417 | #define CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos) /*!< 0x00001000 */ |
10417 | #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */ |
| 10418 | #define CAN_F13R2_FB12 CAN_F13R2_FB12_Msk /*!< Filter bit 12 */ |
10418 | #define CAN_F13R2_FB13_Pos (13U) |
| 10419 | #define CAN_F13R2_FB13_Pos (13U) |
10419 | #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ |
| 10420 | #define CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos) /*!< 0x00002000 */ |
10420 | #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */ |
| 10421 | #define CAN_F13R2_FB13 CAN_F13R2_FB13_Msk /*!< Filter bit 13 */ |
10421 | #define CAN_F13R2_FB14_Pos (14U) |
| 10422 | #define CAN_F13R2_FB14_Pos (14U) |
10422 | #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ |
| 10423 | #define CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos) /*!< 0x00004000 */ |
10423 | #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */ |
| 10424 | #define CAN_F13R2_FB14 CAN_F13R2_FB14_Msk /*!< Filter bit 14 */ |
10424 | #define CAN_F13R2_FB15_Pos (15U) |
| 10425 | #define CAN_F13R2_FB15_Pos (15U) |
10425 | #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ |
| 10426 | #define CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos) /*!< 0x00008000 */ |
10426 | #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */ |
| 10427 | #define CAN_F13R2_FB15 CAN_F13R2_FB15_Msk /*!< Filter bit 15 */ |
10427 | #define CAN_F13R2_FB16_Pos (16U) |
| 10428 | #define CAN_F13R2_FB16_Pos (16U) |
10428 | #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ |
| 10429 | #define CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos) /*!< 0x00010000 */ |
10429 | #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */ |
| 10430 | #define CAN_F13R2_FB16 CAN_F13R2_FB16_Msk /*!< Filter bit 16 */ |
10430 | #define CAN_F13R2_FB17_Pos (17U) |
| 10431 | #define CAN_F13R2_FB17_Pos (17U) |
10431 | #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ |
| 10432 | #define CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos) /*!< 0x00020000 */ |
10432 | #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */ |
| 10433 | #define CAN_F13R2_FB17 CAN_F13R2_FB17_Msk /*!< Filter bit 17 */ |
10433 | #define CAN_F13R2_FB18_Pos (18U) |
| 10434 | #define CAN_F13R2_FB18_Pos (18U) |
10434 | #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ |
| 10435 | #define CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos) /*!< 0x00040000 */ |
10435 | #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */ |
| 10436 | #define CAN_F13R2_FB18 CAN_F13R2_FB18_Msk /*!< Filter bit 18 */ |
10436 | #define CAN_F13R2_FB19_Pos (19U) |
| 10437 | #define CAN_F13R2_FB19_Pos (19U) |
10437 | #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ |
| 10438 | #define CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos) /*!< 0x00080000 */ |
10438 | #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */ |
| 10439 | #define CAN_F13R2_FB19 CAN_F13R2_FB19_Msk /*!< Filter bit 19 */ |
10439 | #define CAN_F13R2_FB20_Pos (20U) |
| 10440 | #define CAN_F13R2_FB20_Pos (20U) |
10440 | #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ |
| 10441 | #define CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos) /*!< 0x00100000 */ |
10441 | #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */ |
| 10442 | #define CAN_F13R2_FB20 CAN_F13R2_FB20_Msk /*!< Filter bit 20 */ |
10442 | #define CAN_F13R2_FB21_Pos (21U) |
| 10443 | #define CAN_F13R2_FB21_Pos (21U) |
10443 | #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ |
| 10444 | #define CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos) /*!< 0x00200000 */ |
10444 | #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */ |
| 10445 | #define CAN_F13R2_FB21 CAN_F13R2_FB21_Msk /*!< Filter bit 21 */ |
10445 | #define CAN_F13R2_FB22_Pos (22U) |
| 10446 | #define CAN_F13R2_FB22_Pos (22U) |
10446 | #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ |
| 10447 | #define CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos) /*!< 0x00400000 */ |
10447 | #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */ |
| 10448 | #define CAN_F13R2_FB22 CAN_F13R2_FB22_Msk /*!< Filter bit 22 */ |
10448 | #define CAN_F13R2_FB23_Pos (23U) |
| 10449 | #define CAN_F13R2_FB23_Pos (23U) |
10449 | #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ |
| 10450 | #define CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos) /*!< 0x00800000 */ |
10450 | #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */ |
| 10451 | #define CAN_F13R2_FB23 CAN_F13R2_FB23_Msk /*!< Filter bit 23 */ |
10451 | #define CAN_F13R2_FB24_Pos (24U) |
| 10452 | #define CAN_F13R2_FB24_Pos (24U) |
10452 | #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ |
| 10453 | #define CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos) /*!< 0x01000000 */ |
10453 | #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */ |
| 10454 | #define CAN_F13R2_FB24 CAN_F13R2_FB24_Msk /*!< Filter bit 24 */ |
10454 | #define CAN_F13R2_FB25_Pos (25U) |
| 10455 | #define CAN_F13R2_FB25_Pos (25U) |
10455 | #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ |
| 10456 | #define CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos) /*!< 0x02000000 */ |
10456 | #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */ |
| 10457 | #define CAN_F13R2_FB25 CAN_F13R2_FB25_Msk /*!< Filter bit 25 */ |
10457 | #define CAN_F13R2_FB26_Pos (26U) |
| 10458 | #define CAN_F13R2_FB26_Pos (26U) |
10458 | #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ |
| 10459 | #define CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos) /*!< 0x04000000 */ |
10459 | #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */ |
| 10460 | #define CAN_F13R2_FB26 CAN_F13R2_FB26_Msk /*!< Filter bit 26 */ |
10460 | #define CAN_F13R2_FB27_Pos (27U) |
| 10461 | #define CAN_F13R2_FB27_Pos (27U) |
10461 | #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ |
| 10462 | #define CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos) /*!< 0x08000000 */ |
10462 | #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */ |
| 10463 | #define CAN_F13R2_FB27 CAN_F13R2_FB27_Msk /*!< Filter bit 27 */ |
10463 | #define CAN_F13R2_FB28_Pos (28U) |
| 10464 | #define CAN_F13R2_FB28_Pos (28U) |
10464 | #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ |
| 10465 | #define CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos) /*!< 0x10000000 */ |
10465 | #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */ |
| 10466 | #define CAN_F13R2_FB28 CAN_F13R2_FB28_Msk /*!< Filter bit 28 */ |
10466 | #define CAN_F13R2_FB29_Pos (29U) |
| 10467 | #define CAN_F13R2_FB29_Pos (29U) |
10467 | #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ |
| 10468 | #define CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos) /*!< 0x20000000 */ |
10468 | #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */ |
| 10469 | #define CAN_F13R2_FB29 CAN_F13R2_FB29_Msk /*!< Filter bit 29 */ |
10469 | #define CAN_F13R2_FB30_Pos (30U) |
| 10470 | #define CAN_F13R2_FB30_Pos (30U) |
10470 | #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ |
| 10471 | #define CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos) /*!< 0x40000000 */ |
10471 | #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */ |
| 10472 | #define CAN_F13R2_FB30 CAN_F13R2_FB30_Msk /*!< Filter bit 30 */ |
10472 | #define CAN_F13R2_FB31_Pos (31U) |
| 10473 | #define CAN_F13R2_FB31_Pos (31U) |
10473 | #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ |
| 10474 | #define CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos) /*!< 0x80000000 */ |
10474 | #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */ |
| 10475 | #define CAN_F13R2_FB31 CAN_F13R2_FB31_Msk /*!< Filter bit 31 */ |
10475 | |
| 10476 | 10476 | /******************* Bit definition for CAN_F14R2 register ******************/ |
|
| 10477 | /******************* Bit definition for CAN_F14R2 register ******************/ |
10477 | #define CAN_F14R2_FB0_Pos (0U) |
| 10478 | #define CAN_F14R2_FB0_Pos (0U) |
10478 | #define CAN_F14R2_FB0_Msk (0x1UL << CAN_F14R2_FB0_Pos) /*!< 0x00000001 */ |
| 10479 | #define CAN_F14R2_FB0_Msk (0x1UL << CAN_F14R2_FB0_Pos) /*!< 0x00000001 */ |
10479 | #define CAN_F14R2_FB0 CAN_F14R2_FB0_Msk /*!< Filter bit 0 */ |
| 10480 | #define CAN_F14R2_FB0 CAN_F14R2_FB0_Msk /*!< Filter bit 0 */ |
10480 | #define CAN_F14R2_FB1_Pos (1U) |
| 10481 | #define CAN_F14R2_FB1_Pos (1U) |
10481 | #define CAN_F14R2_FB1_Msk (0x1UL << CAN_F14R2_FB1_Pos) /*!< 0x00000002 */ |
| 10482 | #define CAN_F14R2_FB1_Msk (0x1UL << CAN_F14R2_FB1_Pos) /*!< 0x00000002 */ |
10482 | #define CAN_F14R2_FB1 CAN_F14R2_FB1_Msk /*!< Filter bit 1 */ |
| 10483 | #define CAN_F14R2_FB1 CAN_F14R2_FB1_Msk /*!< Filter bit 1 */ |
10483 | #define CAN_F14R2_FB2_Pos (2U) |
| 10484 | #define CAN_F14R2_FB2_Pos (2U) |
10484 | #define CAN_F14R2_FB2_Msk (0x1UL << CAN_F14R2_FB2_Pos) /*!< 0x00000004 */ |
| 10485 | #define CAN_F14R2_FB2_Msk (0x1UL << CAN_F14R2_FB2_Pos) /*!< 0x00000004 */ |
10485 | #define CAN_F14R2_FB2 CAN_F14R2_FB2_Msk /*!< Filter bit 2 */ |
| 10486 | #define CAN_F14R2_FB2 CAN_F14R2_FB2_Msk /*!< Filter bit 2 */ |
10486 | #define CAN_F14R2_FB3_Pos (3U) |
| 10487 | #define CAN_F14R2_FB3_Pos (3U) |
10487 | #define CAN_F14R2_FB3_Msk (0x1UL << CAN_F14R2_FB3_Pos) /*!< 0x00000008 */ |
| 10488 | #define CAN_F14R2_FB3_Msk (0x1UL << CAN_F14R2_FB3_Pos) /*!< 0x00000008 */ |
10488 | #define CAN_F14R2_FB3 CAN_F14R2_FB3_Msk /*!< Filter bit 3 */ |
| 10489 | #define CAN_F14R2_FB3 CAN_F14R2_FB3_Msk /*!< Filter bit 3 */ |
10489 | #define CAN_F14R2_FB4_Pos (4U) |
| 10490 | #define CAN_F14R2_FB4_Pos (4U) |
10490 | #define CAN_F14R2_FB4_Msk (0x1UL << CAN_F14R2_FB4_Pos) /*!< 0x00000010 */ |
| 10491 | #define CAN_F14R2_FB4_Msk (0x1UL << CAN_F14R2_FB4_Pos) /*!< 0x00000010 */ |
10491 | #define CAN_F14R2_FB4 CAN_F14R2_FB4_Msk /*!< Filter bit 4 */ |
| 10492 | #define CAN_F14R2_FB4 CAN_F14R2_FB4_Msk /*!< Filter bit 4 */ |
10492 | #define CAN_F14R2_FB5_Pos (5U) |
| 10493 | #define CAN_F14R2_FB5_Pos (5U) |
10493 | #define CAN_F14R2_FB5_Msk (0x1UL << CAN_F14R2_FB5_Pos) /*!< 0x00000020 */ |
| 10494 | #define CAN_F14R2_FB5_Msk (0x1UL << CAN_F14R2_FB5_Pos) /*!< 0x00000020 */ |
10494 | #define CAN_F14R2_FB5 CAN_F14R2_FB5_Msk /*!< Filter bit 5 */ |
| 10495 | #define CAN_F14R2_FB5 CAN_F14R2_FB5_Msk /*!< Filter bit 5 */ |
10495 | #define CAN_F14R2_FB6_Pos (6U) |
| 10496 | #define CAN_F14R2_FB6_Pos (6U) |
10496 | #define CAN_F14R2_FB6_Msk (0x1UL << CAN_F14R2_FB6_Pos) /*!< 0x00000040 */ |
| 10497 | #define CAN_F14R2_FB6_Msk (0x1UL << CAN_F14R2_FB6_Pos) /*!< 0x00000040 */ |
10497 | #define CAN_F14R2_FB6 CAN_F14R2_FB6_Msk /*!< Filter bit 6 */ |
| 10498 | #define CAN_F14R2_FB6 CAN_F14R2_FB6_Msk /*!< Filter bit 6 */ |
10498 | #define CAN_F14R2_FB7_Pos (7U) |
| 10499 | #define CAN_F14R2_FB7_Pos (7U) |
10499 | #define CAN_F14R2_FB7_Msk (0x1UL << CAN_F14R2_FB7_Pos) /*!< 0x00000080 */ |
| 10500 | #define CAN_F14R2_FB7_Msk (0x1UL << CAN_F14R2_FB7_Pos) /*!< 0x00000080 */ |
10500 | #define CAN_F14R2_FB7 CAN_F14R2_FB7_Msk /*!< Filter bit 7 */ |
| 10501 | #define CAN_F14R2_FB7 CAN_F14R2_FB7_Msk /*!< Filter bit 7 */ |
10501 | #define CAN_F14R2_FB8_Pos (8U) |
| 10502 | #define CAN_F14R2_FB8_Pos (8U) |
10502 | #define CAN_F14R2_FB8_Msk (0x1UL << CAN_F14R2_FB8_Pos) /*!< 0x00000100 */ |
| 10503 | #define CAN_F14R2_FB8_Msk (0x1UL << CAN_F14R2_FB8_Pos) /*!< 0x00000100 */ |
10503 | #define CAN_F14R2_FB8 CAN_F14R2_FB8_Msk /*!< Filter bit 8 */ |
| 10504 | #define CAN_F14R2_FB8 CAN_F14R2_FB8_Msk /*!< Filter bit 8 */ |
10504 | #define CAN_F14R2_FB9_Pos (9U) |
| 10505 | #define CAN_F14R2_FB9_Pos (9U) |
10505 | #define CAN_F14R2_FB9_Msk (0x1UL << CAN_F14R2_FB9_Pos) /*!< 0x00000200 */ |
| 10506 | #define CAN_F14R2_FB9_Msk (0x1UL << CAN_F14R2_FB9_Pos) /*!< 0x00000200 */ |
10506 | #define CAN_F14R2_FB9 CAN_F14R2_FB9_Msk /*!< Filter bit 9 */ |
| 10507 | #define CAN_F14R2_FB9 CAN_F14R2_FB9_Msk /*!< Filter bit 9 */ |
10507 | #define CAN_F14R2_FB10_Pos (10U) |
| 10508 | #define CAN_F14R2_FB10_Pos (10U) |
10508 | #define CAN_F14R2_FB10_Msk (0x1UL << CAN_F14R2_FB10_Pos) /*!< 0x00000400 */ |
| 10509 | #define CAN_F14R2_FB10_Msk (0x1UL << CAN_F14R2_FB10_Pos) /*!< 0x00000400 */ |
10509 | #define CAN_F14R2_FB10 CAN_F14R2_FB10_Msk /*!< Filter bit 10 */ |
| 10510 | #define CAN_F14R2_FB10 CAN_F14R2_FB10_Msk /*!< Filter bit 10 */ |
10510 | #define CAN_F14R2_FB11_Pos (11U) |
| 10511 | #define CAN_F14R2_FB11_Pos (11U) |
10511 | #define CAN_F14R2_FB11_Msk (0x1UL << CAN_F14R2_FB11_Pos) /*!< 0x00000800 */ |
| 10512 | #define CAN_F14R2_FB11_Msk (0x1UL << CAN_F14R2_FB11_Pos) /*!< 0x00000800 */ |
10512 | #define CAN_F14R2_FB11 CAN_F14R2_FB11_Msk /*!< Filter bit 11 */ |
| 10513 | #define CAN_F14R2_FB11 CAN_F14R2_FB11_Msk /*!< Filter bit 11 */ |
10513 | #define CAN_F14R2_FB12_Pos (12U) |
| 10514 | #define CAN_F14R2_FB12_Pos (12U) |
10514 | #define CAN_F14R2_FB12_Msk (0x1UL << CAN_F14R2_FB12_Pos) /*!< 0x00001000 */ |
| 10515 | #define CAN_F14R2_FB12_Msk (0x1UL << CAN_F14R2_FB12_Pos) /*!< 0x00001000 */ |
10515 | #define CAN_F14R2_FB12 CAN_F14R2_FB12_Msk /*!< Filter bit 12 */ |
| 10516 | #define CAN_F14R2_FB12 CAN_F14R2_FB12_Msk /*!< Filter bit 12 */ |
10516 | #define CAN_F14R2_FB13_Pos (13U) |
| 10517 | #define CAN_F14R2_FB13_Pos (13U) |
10517 | #define CAN_F14R2_FB13_Msk (0x1UL << CAN_F14R2_FB13_Pos) /*!< 0x00002000 */ |
| 10518 | #define CAN_F14R2_FB13_Msk (0x1UL << CAN_F14R2_FB13_Pos) /*!< 0x00002000 */ |
10518 | #define CAN_F14R2_FB13 CAN_F14R2_FB13_Msk /*!< Filter bit 13 */ |
| 10519 | #define CAN_F14R2_FB13 CAN_F14R2_FB13_Msk /*!< Filter bit 13 */ |
10519 | #define CAN_F14R2_FB14_Pos (14U) |
| 10520 | #define CAN_F14R2_FB14_Pos (14U) |
10520 | #define CAN_F14R2_FB14_Msk (0x1UL << CAN_F14R2_FB14_Pos) /*!< 0x00004000 */ |
| 10521 | #define CAN_F14R2_FB14_Msk (0x1UL << CAN_F14R2_FB14_Pos) /*!< 0x00004000 */ |
10521 | #define CAN_F14R2_FB14 CAN_F14R2_FB14_Msk /*!< Filter bit 14 */ |
| 10522 | #define CAN_F14R2_FB14 CAN_F14R2_FB14_Msk /*!< Filter bit 14 */ |
10522 | #define CAN_F14R2_FB15_Pos (15U) |
| 10523 | #define CAN_F14R2_FB15_Pos (15U) |
10523 | #define CAN_F14R2_FB15_Msk (0x1UL << CAN_F14R2_FB15_Pos) /*!< 0x00008000 */ |
| 10524 | #define CAN_F14R2_FB15_Msk (0x1UL << CAN_F14R2_FB15_Pos) /*!< 0x00008000 */ |
10524 | #define CAN_F14R2_FB15 CAN_F14R2_FB15_Msk /*!< Filter bit 15 */ |
| 10525 | #define CAN_F14R2_FB15 CAN_F14R2_FB15_Msk /*!< Filter bit 15 */ |
10525 | #define CAN_F14R2_FB16_Pos (16U) |
| 10526 | #define CAN_F14R2_FB16_Pos (16U) |
10526 | #define CAN_F14R2_FB16_Msk (0x1UL << CAN_F14R2_FB16_Pos) /*!< 0x00010000 */ |
| 10527 | #define CAN_F14R2_FB16_Msk (0x1UL << CAN_F14R2_FB16_Pos) /*!< 0x00010000 */ |
10527 | #define CAN_F14R2_FB16 CAN_F14R2_FB16_Msk /*!< Filter bit 16 */ |
| 10528 | #define CAN_F14R2_FB16 CAN_F14R2_FB16_Msk /*!< Filter bit 16 */ |
10528 | #define CAN_F14R2_FB17_Pos (17U) |
| 10529 | #define CAN_F14R2_FB17_Pos (17U) |
10529 | #define CAN_F14R2_FB17_Msk (0x1UL << CAN_F14R2_FB17_Pos) /*!< 0x00020000 */ |
| 10530 | #define CAN_F14R2_FB17_Msk (0x1UL << CAN_F14R2_FB17_Pos) /*!< 0x00020000 */ |
10530 | #define CAN_F14R2_FB17 CAN_F14R2_FB17_Msk /*!< Filter bit 17 */ |
| 10531 | #define CAN_F14R2_FB17 CAN_F14R2_FB17_Msk /*!< Filter bit 17 */ |
10531 | #define CAN_F14R2_FB18_Pos (18U) |
| 10532 | #define CAN_F14R2_FB18_Pos (18U) |
10532 | #define CAN_F14R2_FB18_Msk (0x1UL << CAN_F14R2_FB18_Pos) /*!< 0x00040000 */ |
| 10533 | #define CAN_F14R2_FB18_Msk (0x1UL << CAN_F14R2_FB18_Pos) /*!< 0x00040000 */ |
10533 | #define CAN_F14R2_FB18 CAN_F14R2_FB18_Msk /*!< Filter bit 18 */ |
| 10534 | #define CAN_F14R2_FB18 CAN_F14R2_FB18_Msk /*!< Filter bit 18 */ |
10534 | #define CAN_F14R2_FB19_Pos (19U) |
| 10535 | #define CAN_F14R2_FB19_Pos (19U) |
10535 | #define CAN_F14R2_FB19_Msk (0x1UL << CAN_F14R2_FB19_Pos) /*!< 0x00080000 */ |
| 10536 | #define CAN_F14R2_FB19_Msk (0x1UL << CAN_F14R2_FB19_Pos) /*!< 0x00080000 */ |
10536 | #define CAN_F14R2_FB19 CAN_F14R2_FB19_Msk /*!< Filter bit 19 */ |
| 10537 | #define CAN_F14R2_FB19 CAN_F14R2_FB19_Msk /*!< Filter bit 19 */ |
10537 | #define CAN_F14R2_FB20_Pos (20U) |
| 10538 | #define CAN_F14R2_FB20_Pos (20U) |
10538 | #define CAN_F14R2_FB20_Msk (0x1UL << CAN_F14R2_FB20_Pos) /*!< 0x00100000 */ |
| 10539 | #define CAN_F14R2_FB20_Msk (0x1UL << CAN_F14R2_FB20_Pos) /*!< 0x00100000 */ |
10539 | #define CAN_F14R2_FB20 CAN_F14R2_FB20_Msk /*!< Filter bit 20 */ |
| 10540 | #define CAN_F14R2_FB20 CAN_F14R2_FB20_Msk /*!< Filter bit 20 */ |
10540 | #define CAN_F14R2_FB21_Pos (21U) |
| 10541 | #define CAN_F14R2_FB21_Pos (21U) |
10541 | #define CAN_F14R2_FB21_Msk (0x1UL << CAN_F14R2_FB21_Pos) /*!< 0x00200000 */ |
| 10542 | #define CAN_F14R2_FB21_Msk (0x1UL << CAN_F14R2_FB21_Pos) /*!< 0x00200000 */ |
10542 | #define CAN_F14R2_FB21 CAN_F14R2_FB21_Msk /*!< Filter bit 21 */ |
| 10543 | #define CAN_F14R2_FB21 CAN_F14R2_FB21_Msk /*!< Filter bit 21 */ |
10543 | #define CAN_F14R2_FB22_Pos (22U) |
| 10544 | #define CAN_F14R2_FB22_Pos (22U) |
10544 | #define CAN_F14R2_FB22_Msk (0x1UL << CAN_F14R2_FB22_Pos) /*!< 0x00400000 */ |
| 10545 | #define CAN_F14R2_FB22_Msk (0x1UL << CAN_F14R2_FB22_Pos) /*!< 0x00400000 */ |
10545 | #define CAN_F14R2_FB22 CAN_F14R2_FB22_Msk /*!< Filter bit 22 */ |
| 10546 | #define CAN_F14R2_FB22 CAN_F14R2_FB22_Msk /*!< Filter bit 22 */ |
10546 | #define CAN_F14R2_FB23_Pos (23U) |
| 10547 | #define CAN_F14R2_FB23_Pos (23U) |
10547 | #define CAN_F14R2_FB23_Msk (0x1UL << CAN_F14R2_FB23_Pos) /*!< 0x00800000 */ |
| 10548 | #define CAN_F14R2_FB23_Msk (0x1UL << CAN_F14R2_FB23_Pos) /*!< 0x00800000 */ |
10548 | #define CAN_F14R2_FB23 CAN_F14R2_FB23_Msk /*!< Filter bit 23 */ |
| 10549 | #define CAN_F14R2_FB23 CAN_F14R2_FB23_Msk /*!< Filter bit 23 */ |
10549 | #define CAN_F14R2_FB24_Pos (24U) |
| 10550 | #define CAN_F14R2_FB24_Pos (24U) |
10550 | #define CAN_F14R2_FB24_Msk (0x1UL << CAN_F14R2_FB24_Pos) /*!< 0x01000000 */ |
| 10551 | #define CAN_F14R2_FB24_Msk (0x1UL << CAN_F14R2_FB24_Pos) /*!< 0x01000000 */ |
10551 | #define CAN_F14R2_FB24 CAN_F14R2_FB24_Msk /*!< Filter bit 24 */ |
| 10552 | #define CAN_F14R2_FB24 CAN_F14R2_FB24_Msk /*!< Filter bit 24 */ |
10552 | #define CAN_F14R2_FB25_Pos (25U) |
| 10553 | #define CAN_F14R2_FB25_Pos (25U) |
10553 | #define CAN_F14R2_FB25_Msk (0x1UL << CAN_F14R2_FB25_Pos) /*!< 0x02000000 */ |
| 10554 | #define CAN_F14R2_FB25_Msk (0x1UL << CAN_F14R2_FB25_Pos) /*!< 0x02000000 */ |
10554 | #define CAN_F14R2_FB25 CAN_F14R2_FB25_Msk /*!< Filter bit 25 */ |
| 10555 | #define CAN_F14R2_FB25 CAN_F14R2_FB25_Msk /*!< Filter bit 25 */ |
10555 | #define CAN_F14R2_FB26_Pos (26U) |
| 10556 | #define CAN_F14R2_FB26_Pos (26U) |
10556 | #define CAN_F14R2_FB26_Msk (0x1UL << CAN_F14R2_FB26_Pos) /*!< 0x04000000 */ |
| 10557 | #define CAN_F14R2_FB26_Msk (0x1UL << CAN_F14R2_FB26_Pos) /*!< 0x04000000 */ |
10557 | #define CAN_F14R2_FB26 CAN_F14R2_FB26_Msk /*!< Filter bit 26 */ |
| 10558 | #define CAN_F14R2_FB26 CAN_F14R2_FB26_Msk /*!< Filter bit 26 */ |
10558 | #define CAN_F14R2_FB27_Pos (27U) |
| 10559 | #define CAN_F14R2_FB27_Pos (27U) |
10559 | #define CAN_F14R2_FB27_Msk (0x1UL << CAN_F14R2_FB27_Pos) /*!< 0x08000000 */ |
| 10560 | #define CAN_F14R2_FB27_Msk (0x1UL << CAN_F14R2_FB27_Pos) /*!< 0x08000000 */ |
10560 | #define CAN_F14R2_FB27 CAN_F14R2_FB27_Msk /*!< Filter bit 27 */ |
| 10561 | #define CAN_F14R2_FB27 CAN_F14R2_FB27_Msk /*!< Filter bit 27 */ |
10561 | #define CAN_F14R2_FB28_Pos (28U) |
| 10562 | #define CAN_F14R2_FB28_Pos (28U) |
10562 | #define CAN_F14R2_FB28_Msk (0x1UL << CAN_F14R2_FB28_Pos) /*!< 0x10000000 */ |
| 10563 | #define CAN_F14R2_FB28_Msk (0x1UL << CAN_F14R2_FB28_Pos) /*!< 0x10000000 */ |
10563 | #define CAN_F14R2_FB28 CAN_F14R2_FB28_Msk /*!< Filter bit 28 */ |
| 10564 | #define CAN_F14R2_FB28 CAN_F14R2_FB28_Msk /*!< Filter bit 28 */ |
10564 | #define CAN_F14R2_FB29_Pos (29U) |
| 10565 | #define CAN_F14R2_FB29_Pos (29U) |
10565 | #define CAN_F14R2_FB29_Msk (0x1UL << CAN_F14R2_FB29_Pos) /*!< 0x20000000 */ |
| 10566 | #define CAN_F14R2_FB29_Msk (0x1UL << CAN_F14R2_FB29_Pos) /*!< 0x20000000 */ |
10566 | #define CAN_F14R2_FB29 CAN_F14R2_FB29_Msk /*!< Filter bit 29 */ |
| 10567 | #define CAN_F14R2_FB29 CAN_F14R2_FB29_Msk /*!< Filter bit 29 */ |
10567 | #define CAN_F14R2_FB30_Pos (30U) |
| 10568 | #define CAN_F14R2_FB30_Pos (30U) |
10568 | #define CAN_F14R2_FB30_Msk (0x1UL << CAN_F14R2_FB30_Pos) /*!< 0x40000000 */ |
| 10569 | #define CAN_F14R2_FB30_Msk (0x1UL << CAN_F14R2_FB30_Pos) /*!< 0x40000000 */ |
10569 | #define CAN_F14R2_FB30 CAN_F14R2_FB30_Msk /*!< Filter bit 30 */ |
| 10570 | #define CAN_F14R2_FB30 CAN_F14R2_FB30_Msk /*!< Filter bit 30 */ |
10570 | #define CAN_F14R2_FB31_Pos (31U) |
| 10571 | #define CAN_F14R2_FB31_Pos (31U) |
10571 | #define CAN_F14R2_FB31_Msk (0x1UL << CAN_F14R2_FB31_Pos) /*!< 0x80000000 */ |
| 10572 | #define CAN_F14R2_FB31_Msk (0x1UL << CAN_F14R2_FB31_Pos) /*!< 0x80000000 */ |
10572 | #define CAN_F14R2_FB31 CAN_F14R2_FB31_Msk /*!< Filter bit 31 */ |
| 10573 | #define CAN_F14R2_FB31 CAN_F14R2_FB31_Msk /*!< Filter bit 31 */ |
10573 | |
| 10574 | 10574 | /******************* Bit definition for CAN_F15R2 register ******************/ |
|
| 10575 | /******************* Bit definition for CAN_F15R2 register ******************/ |
10575 | #define CAN_F15R2_FB0_Pos (0U) |
| 10576 | #define CAN_F15R2_FB0_Pos (0U) |
10576 | #define CAN_F15R2_FB0_Msk (0x1UL << CAN_F15R2_FB0_Pos) /*!< 0x00000001 */ |
| 10577 | #define CAN_F15R2_FB0_Msk (0x1UL << CAN_F15R2_FB0_Pos) /*!< 0x00000001 */ |
10577 | #define CAN_F15R2_FB0 CAN_F15R2_FB0_Msk /*!< Filter bit 0 */ |
| 10578 | #define CAN_F15R2_FB0 CAN_F15R2_FB0_Msk /*!< Filter bit 0 */ |
10578 | #define CAN_F15R2_FB1_Pos (1U) |
| 10579 | #define CAN_F15R2_FB1_Pos (1U) |
10579 | #define CAN_F15R2_FB1_Msk (0x1UL << CAN_F15R2_FB1_Pos) /*!< 0x00000002 */ |
| 10580 | #define CAN_F15R2_FB1_Msk (0x1UL << CAN_F15R2_FB1_Pos) /*!< 0x00000002 */ |
10580 | #define CAN_F15R2_FB1 CAN_F15R2_FB1_Msk /*!< Filter bit 1 */ |
| 10581 | #define CAN_F15R2_FB1 CAN_F15R2_FB1_Msk /*!< Filter bit 1 */ |
10581 | #define CAN_F15R2_FB2_Pos (2U) |
| 10582 | #define CAN_F15R2_FB2_Pos (2U) |
10582 | #define CAN_F15R2_FB2_Msk (0x1UL << CAN_F15R2_FB2_Pos) /*!< 0x00000004 */ |
| 10583 | #define CAN_F15R2_FB2_Msk (0x1UL << CAN_F15R2_FB2_Pos) /*!< 0x00000004 */ |
10583 | #define CAN_F15R2_FB2 CAN_F15R2_FB2_Msk /*!< Filter bit 2 */ |
| 10584 | #define CAN_F15R2_FB2 CAN_F15R2_FB2_Msk /*!< Filter bit 2 */ |
10584 | #define CAN_F15R2_FB3_Pos (3U) |
| 10585 | #define CAN_F15R2_FB3_Pos (3U) |
10585 | #define CAN_F15R2_FB3_Msk (0x1UL << CAN_F15R2_FB3_Pos) /*!< 0x00000008 */ |
| 10586 | #define CAN_F15R2_FB3_Msk (0x1UL << CAN_F15R2_FB3_Pos) /*!< 0x00000008 */ |
10586 | #define CAN_F15R2_FB3 CAN_F15R2_FB3_Msk /*!< Filter bit 3 */ |
| 10587 | #define CAN_F15R2_FB3 CAN_F15R2_FB3_Msk /*!< Filter bit 3 */ |
10587 | #define CAN_F15R2_FB4_Pos (4U) |
| 10588 | #define CAN_F15R2_FB4_Pos (4U) |
10588 | #define CAN_F15R2_FB4_Msk (0x1UL << CAN_F15R2_FB4_Pos) /*!< 0x00000010 */ |
| 10589 | #define CAN_F15R2_FB4_Msk (0x1UL << CAN_F15R2_FB4_Pos) /*!< 0x00000010 */ |
10589 | #define CAN_F15R2_FB4 CAN_F15R2_FB4_Msk /*!< Filter bit 4 */ |
| 10590 | #define CAN_F15R2_FB4 CAN_F15R2_FB4_Msk /*!< Filter bit 4 */ |
10590 | #define CAN_F15R2_FB5_Pos (5U) |
| 10591 | #define CAN_F15R2_FB5_Pos (5U) |
10591 | #define CAN_F15R2_FB5_Msk (0x1UL << CAN_F15R2_FB5_Pos) /*!< 0x00000020 */ |
| 10592 | #define CAN_F15R2_FB5_Msk (0x1UL << CAN_F15R2_FB5_Pos) /*!< 0x00000020 */ |
10592 | #define CAN_F15R2_FB5 CAN_F15R2_FB5_Msk /*!< Filter bit 5 */ |
| 10593 | #define CAN_F15R2_FB5 CAN_F15R2_FB5_Msk /*!< Filter bit 5 */ |
10593 | #define CAN_F15R2_FB6_Pos (6U) |
| 10594 | #define CAN_F15R2_FB6_Pos (6U) |
10594 | #define CAN_F15R2_FB6_Msk (0x1UL << CAN_F15R2_FB6_Pos) /*!< 0x00000040 */ |
| 10595 | #define CAN_F15R2_FB6_Msk (0x1UL << CAN_F15R2_FB6_Pos) /*!< 0x00000040 */ |
10595 | #define CAN_F15R2_FB6 CAN_F15R2_FB6_Msk /*!< Filter bit 6 */ |
| 10596 | #define CAN_F15R2_FB6 CAN_F15R2_FB6_Msk /*!< Filter bit 6 */ |
10596 | #define CAN_F15R2_FB7_Pos (7U) |
| 10597 | #define CAN_F15R2_FB7_Pos (7U) |
10597 | #define CAN_F15R2_FB7_Msk (0x1UL << CAN_F15R2_FB7_Pos) /*!< 0x00000080 */ |
| 10598 | #define CAN_F15R2_FB7_Msk (0x1UL << CAN_F15R2_FB7_Pos) /*!< 0x00000080 */ |
10598 | #define CAN_F15R2_FB7 CAN_F15R2_FB7_Msk /*!< Filter bit 7 */ |
| 10599 | #define CAN_F15R2_FB7 CAN_F15R2_FB7_Msk /*!< Filter bit 7 */ |
10599 | #define CAN_F15R2_FB8_Pos (8U) |
| 10600 | #define CAN_F15R2_FB8_Pos (8U) |
10600 | #define CAN_F15R2_FB8_Msk (0x1UL << CAN_F15R2_FB8_Pos) /*!< 0x00000100 */ |
| 10601 | #define CAN_F15R2_FB8_Msk (0x1UL << CAN_F15R2_FB8_Pos) /*!< 0x00000100 */ |
10601 | #define CAN_F15R2_FB8 CAN_F15R2_FB8_Msk /*!< Filter bit 8 */ |
| 10602 | #define CAN_F15R2_FB8 CAN_F15R2_FB8_Msk /*!< Filter bit 8 */ |
10602 | #define CAN_F15R2_FB9_Pos (9U) |
| 10603 | #define CAN_F15R2_FB9_Pos (9U) |
10603 | #define CAN_F15R2_FB9_Msk (0x1UL << CAN_F15R2_FB9_Pos) /*!< 0x00000200 */ |
| 10604 | #define CAN_F15R2_FB9_Msk (0x1UL << CAN_F15R2_FB9_Pos) /*!< 0x00000200 */ |
10604 | #define CAN_F15R2_FB9 CAN_F15R2_FB9_Msk /*!< Filter bit 9 */ |
| 10605 | #define CAN_F15R2_FB9 CAN_F15R2_FB9_Msk /*!< Filter bit 9 */ |
10605 | #define CAN_F15R2_FB10_Pos (10U) |
| 10606 | #define CAN_F15R2_FB10_Pos (10U) |
10606 | #define CAN_F15R2_FB10_Msk (0x1UL << CAN_F15R2_FB10_Pos) /*!< 0x00000400 */ |
| 10607 | #define CAN_F15R2_FB10_Msk (0x1UL << CAN_F15R2_FB10_Pos) /*!< 0x00000400 */ |
10607 | #define CAN_F15R2_FB10 CAN_F15R2_FB10_Msk /*!< Filter bit 10 */ |
| 10608 | #define CAN_F15R2_FB10 CAN_F15R2_FB10_Msk /*!< Filter bit 10 */ |
10608 | #define CAN_F15R2_FB11_Pos (11U) |
| 10609 | #define CAN_F15R2_FB11_Pos (11U) |
10609 | #define CAN_F15R2_FB11_Msk (0x1UL << CAN_F15R2_FB11_Pos) /*!< 0x00000800 */ |
| 10610 | #define CAN_F15R2_FB11_Msk (0x1UL << CAN_F15R2_FB11_Pos) /*!< 0x00000800 */ |
10610 | #define CAN_F15R2_FB11 CAN_F15R2_FB11_Msk /*!< Filter bit 11 */ |
| 10611 | #define CAN_F15R2_FB11 CAN_F15R2_FB11_Msk /*!< Filter bit 11 */ |
10611 | #define CAN_F15R2_FB12_Pos (12U) |
| 10612 | #define CAN_F15R2_FB12_Pos (12U) |
10612 | #define CAN_F15R2_FB12_Msk (0x1UL << CAN_F15R2_FB12_Pos) /*!< 0x00001000 */ |
| 10613 | #define CAN_F15R2_FB12_Msk (0x1UL << CAN_F15R2_FB12_Pos) /*!< 0x00001000 */ |
10613 | #define CAN_F15R2_FB12 CAN_F15R2_FB12_Msk /*!< Filter bit 12 */ |
| 10614 | #define CAN_F15R2_FB12 CAN_F15R2_FB12_Msk /*!< Filter bit 12 */ |
10614 | #define CAN_F15R2_FB13_Pos (13U) |
| 10615 | #define CAN_F15R2_FB13_Pos (13U) |
10615 | #define CAN_F15R2_FB13_Msk (0x1UL << CAN_F15R2_FB13_Pos) /*!< 0x00002000 */ |
| 10616 | #define CAN_F15R2_FB13_Msk (0x1UL << CAN_F15R2_FB13_Pos) /*!< 0x00002000 */ |
10616 | #define CAN_F15R2_FB13 CAN_F15R2_FB13_Msk /*!< Filter bit 13 */ |
| 10617 | #define CAN_F15R2_FB13 CAN_F15R2_FB13_Msk /*!< Filter bit 13 */ |
10617 | #define CAN_F15R2_FB14_Pos (14U) |
| 10618 | #define CAN_F15R2_FB14_Pos (14U) |
10618 | #define CAN_F15R2_FB14_Msk (0x1UL << CAN_F15R2_FB14_Pos) /*!< 0x00004000 */ |
| 10619 | #define CAN_F15R2_FB14_Msk (0x1UL << CAN_F15R2_FB14_Pos) /*!< 0x00004000 */ |
10619 | #define CAN_F15R2_FB14 CAN_F15R2_FB14_Msk /*!< Filter bit 14 */ |
| 10620 | #define CAN_F15R2_FB14 CAN_F15R2_FB14_Msk /*!< Filter bit 14 */ |
10620 | #define CAN_F15R2_FB15_Pos (15U) |
| 10621 | #define CAN_F15R2_FB15_Pos (15U) |
10621 | #define CAN_F15R2_FB15_Msk (0x1UL << CAN_F15R2_FB15_Pos) /*!< 0x00008000 */ |
| 10622 | #define CAN_F15R2_FB15_Msk (0x1UL << CAN_F15R2_FB15_Pos) /*!< 0x00008000 */ |
10622 | #define CAN_F15R2_FB15 CAN_F15R2_FB15_Msk /*!< Filter bit 15 */ |
| 10623 | #define CAN_F15R2_FB15 CAN_F15R2_FB15_Msk /*!< Filter bit 15 */ |
10623 | #define CAN_F15R2_FB16_Pos (16U) |
| 10624 | #define CAN_F15R2_FB16_Pos (16U) |
10624 | #define CAN_F15R2_FB16_Msk (0x1UL << CAN_F15R2_FB16_Pos) /*!< 0x00010000 */ |
| 10625 | #define CAN_F15R2_FB16_Msk (0x1UL << CAN_F15R2_FB16_Pos) /*!< 0x00010000 */ |
10625 | #define CAN_F15R2_FB16 CAN_F15R2_FB16_Msk /*!< Filter bit 16 */ |
| 10626 | #define CAN_F15R2_FB16 CAN_F15R2_FB16_Msk /*!< Filter bit 16 */ |
10626 | #define CAN_F15R2_FB17_Pos (17U) |
| 10627 | #define CAN_F15R2_FB17_Pos (17U) |
10627 | #define CAN_F15R2_FB17_Msk (0x1UL << CAN_F15R2_FB17_Pos) /*!< 0x00020000 */ |
| 10628 | #define CAN_F15R2_FB17_Msk (0x1UL << CAN_F15R2_FB17_Pos) /*!< 0x00020000 */ |
10628 | #define CAN_F15R2_FB17 CAN_F15R2_FB17_Msk /*!< Filter bit 17 */ |
| 10629 | #define CAN_F15R2_FB17 CAN_F15R2_FB17_Msk /*!< Filter bit 17 */ |
10629 | #define CAN_F15R2_FB18_Pos (18U) |
| 10630 | #define CAN_F15R2_FB18_Pos (18U) |
10630 | #define CAN_F15R2_FB18_Msk (0x1UL << CAN_F15R2_FB18_Pos) /*!< 0x00040000 */ |
| 10631 | #define CAN_F15R2_FB18_Msk (0x1UL << CAN_F15R2_FB18_Pos) /*!< 0x00040000 */ |
10631 | #define CAN_F15R2_FB18 CAN_F15R2_FB18_Msk /*!< Filter bit 18 */ |
| 10632 | #define CAN_F15R2_FB18 CAN_F15R2_FB18_Msk /*!< Filter bit 18 */ |
10632 | #define CAN_F15R2_FB19_Pos (19U) |
| 10633 | #define CAN_F15R2_FB19_Pos (19U) |
10633 | #define CAN_F15R2_FB19_Msk (0x1UL << CAN_F15R2_FB19_Pos) /*!< 0x00080000 */ |
| 10634 | #define CAN_F15R2_FB19_Msk (0x1UL << CAN_F15R2_FB19_Pos) /*!< 0x00080000 */ |
10634 | #define CAN_F15R2_FB19 CAN_F15R2_FB19_Msk /*!< Filter bit 19 */ |
| 10635 | #define CAN_F15R2_FB19 CAN_F15R2_FB19_Msk /*!< Filter bit 19 */ |
10635 | #define CAN_F15R2_FB20_Pos (20U) |
| 10636 | #define CAN_F15R2_FB20_Pos (20U) |
10636 | #define CAN_F15R2_FB20_Msk (0x1UL << CAN_F15R2_FB20_Pos) /*!< 0x00100000 */ |
| 10637 | #define CAN_F15R2_FB20_Msk (0x1UL << CAN_F15R2_FB20_Pos) /*!< 0x00100000 */ |
10637 | #define CAN_F15R2_FB20 CAN_F15R2_FB20_Msk /*!< Filter bit 20 */ |
| 10638 | #define CAN_F15R2_FB20 CAN_F15R2_FB20_Msk /*!< Filter bit 20 */ |
10638 | #define CAN_F15R2_FB21_Pos (21U) |
| 10639 | #define CAN_F15R2_FB21_Pos (21U) |
10639 | #define CAN_F15R2_FB21_Msk (0x1UL << CAN_F15R2_FB21_Pos) /*!< 0x00200000 */ |
| 10640 | #define CAN_F15R2_FB21_Msk (0x1UL << CAN_F15R2_FB21_Pos) /*!< 0x00200000 */ |
10640 | #define CAN_F15R2_FB21 CAN_F15R2_FB21_Msk /*!< Filter bit 21 */ |
| 10641 | #define CAN_F15R2_FB21 CAN_F15R2_FB21_Msk /*!< Filter bit 21 */ |
10641 | #define CAN_F15R2_FB22_Pos (22U) |
| 10642 | #define CAN_F15R2_FB22_Pos (22U) |
10642 | #define CAN_F15R2_FB22_Msk (0x1UL << CAN_F15R2_FB22_Pos) /*!< 0x00400000 */ |
| 10643 | #define CAN_F15R2_FB22_Msk (0x1UL << CAN_F15R2_FB22_Pos) /*!< 0x00400000 */ |
10643 | #define CAN_F15R2_FB22 CAN_F15R2_FB22_Msk /*!< Filter bit 22 */ |
| 10644 | #define CAN_F15R2_FB22 CAN_F15R2_FB22_Msk /*!< Filter bit 22 */ |
10644 | #define CAN_F15R2_FB23_Pos (23U) |
| 10645 | #define CAN_F15R2_FB23_Pos (23U) |
10645 | #define CAN_F15R2_FB23_Msk (0x1UL << CAN_F15R2_FB23_Pos) /*!< 0x00800000 */ |
| 10646 | #define CAN_F15R2_FB23_Msk (0x1UL << CAN_F15R2_FB23_Pos) /*!< 0x00800000 */ |
10646 | #define CAN_F15R2_FB23 CAN_F15R2_FB23_Msk /*!< Filter bit 23 */ |
| 10647 | #define CAN_F15R2_FB23 CAN_F15R2_FB23_Msk /*!< Filter bit 23 */ |
10647 | #define CAN_F15R2_FB24_Pos (24U) |
| 10648 | #define CAN_F15R2_FB24_Pos (24U) |
10648 | #define CAN_F15R2_FB24_Msk (0x1UL << CAN_F15R2_FB24_Pos) /*!< 0x01000000 */ |
| 10649 | #define CAN_F15R2_FB24_Msk (0x1UL << CAN_F15R2_FB24_Pos) /*!< 0x01000000 */ |
10649 | #define CAN_F15R2_FB24 CAN_F15R2_FB24_Msk /*!< Filter bit 24 */ |
| 10650 | #define CAN_F15R2_FB24 CAN_F15R2_FB24_Msk /*!< Filter bit 24 */ |
10650 | #define CAN_F15R2_FB25_Pos (25U) |
| 10651 | #define CAN_F15R2_FB25_Pos (25U) |
10651 | #define CAN_F15R2_FB25_Msk (0x1UL << CAN_F15R2_FB25_Pos) /*!< 0x02000000 */ |
| 10652 | #define CAN_F15R2_FB25_Msk (0x1UL << CAN_F15R2_FB25_Pos) /*!< 0x02000000 */ |
10652 | #define CAN_F15R2_FB25 CAN_F15R2_FB25_Msk /*!< Filter bit 25 */ |
| 10653 | #define CAN_F15R2_FB25 CAN_F15R2_FB25_Msk /*!< Filter bit 25 */ |
10653 | #define CAN_F15R2_FB26_Pos (26U) |
| 10654 | #define CAN_F15R2_FB26_Pos (26U) |
10654 | #define CAN_F15R2_FB26_Msk (0x1UL << CAN_F15R2_FB26_Pos) /*!< 0x04000000 */ |
| 10655 | #define CAN_F15R2_FB26_Msk (0x1UL << CAN_F15R2_FB26_Pos) /*!< 0x04000000 */ |
10655 | #define CAN_F15R2_FB26 CAN_F15R2_FB26_Msk /*!< Filter bit 26 */ |
| 10656 | #define CAN_F15R2_FB26 CAN_F15R2_FB26_Msk /*!< Filter bit 26 */ |
10656 | #define CAN_F15R2_FB27_Pos (27U) |
| 10657 | #define CAN_F15R2_FB27_Pos (27U) |
10657 | #define CAN_F15R2_FB27_Msk (0x1UL << CAN_F15R2_FB27_Pos) /*!< 0x08000000 */ |
| 10658 | #define CAN_F15R2_FB27_Msk (0x1UL << CAN_F15R2_FB27_Pos) /*!< 0x08000000 */ |
10658 | #define CAN_F15R2_FB27 CAN_F15R2_FB27_Msk /*!< Filter bit 27 */ |
| 10659 | #define CAN_F15R2_FB27 CAN_F15R2_FB27_Msk /*!< Filter bit 27 */ |
10659 | #define CAN_F15R2_FB28_Pos (28U) |
| 10660 | #define CAN_F15R2_FB28_Pos (28U) |
10660 | #define CAN_F15R2_FB28_Msk (0x1UL << CAN_F15R2_FB28_Pos) /*!< 0x10000000 */ |
| 10661 | #define CAN_F15R2_FB28_Msk (0x1UL << CAN_F15R2_FB28_Pos) /*!< 0x10000000 */ |
10661 | #define CAN_F15R2_FB28 CAN_F15R2_FB28_Msk /*!< Filter bit 28 */ |
| 10662 | #define CAN_F15R2_FB28 CAN_F15R2_FB28_Msk /*!< Filter bit 28 */ |
10662 | #define CAN_F15R2_FB29_Pos (29U) |
| 10663 | #define CAN_F15R2_FB29_Pos (29U) |
10663 | #define CAN_F15R2_FB29_Msk (0x1UL << CAN_F15R2_FB29_Pos) /*!< 0x20000000 */ |
| 10664 | #define CAN_F15R2_FB29_Msk (0x1UL << CAN_F15R2_FB29_Pos) /*!< 0x20000000 */ |
10664 | #define CAN_F15R2_FB29 CAN_F15R2_FB29_Msk /*!< Filter bit 29 */ |
| 10665 | #define CAN_F15R2_FB29 CAN_F15R2_FB29_Msk /*!< Filter bit 29 */ |
10665 | #define CAN_F15R2_FB30_Pos (30U) |
| 10666 | #define CAN_F15R2_FB30_Pos (30U) |
10666 | #define CAN_F15R2_FB30_Msk (0x1UL << CAN_F15R2_FB30_Pos) /*!< 0x40000000 */ |
| 10667 | #define CAN_F15R2_FB30_Msk (0x1UL << CAN_F15R2_FB30_Pos) /*!< 0x40000000 */ |
10667 | #define CAN_F15R2_FB30 CAN_F15R2_FB30_Msk /*!< Filter bit 30 */ |
| 10668 | #define CAN_F15R2_FB30 CAN_F15R2_FB30_Msk /*!< Filter bit 30 */ |
10668 | #define CAN_F15R2_FB31_Pos (31U) |
| 10669 | #define CAN_F15R2_FB31_Pos (31U) |
10669 | #define CAN_F15R2_FB31_Msk (0x1UL << CAN_F15R2_FB31_Pos) /*!< 0x80000000 */ |
| 10670 | #define CAN_F15R2_FB31_Msk (0x1UL << CAN_F15R2_FB31_Pos) /*!< 0x80000000 */ |
10670 | #define CAN_F15R2_FB31 CAN_F15R2_FB31_Msk /*!< Filter bit 31 */ |
| 10671 | #define CAN_F15R2_FB31 CAN_F15R2_FB31_Msk /*!< Filter bit 31 */ |
10671 | |
| 10672 | 10672 | /******************* Bit definition for CAN_F16R2 register ******************/ |
|
| 10673 | /******************* Bit definition for CAN_F16R2 register ******************/ |
10673 | #define CAN_F16R2_FB0_Pos (0U) |
| 10674 | #define CAN_F16R2_FB0_Pos (0U) |
10674 | #define CAN_F16R2_FB0_Msk (0x1UL << CAN_F16R2_FB0_Pos) /*!< 0x00000001 */ |
| 10675 | #define CAN_F16R2_FB0_Msk (0x1UL << CAN_F16R2_FB0_Pos) /*!< 0x00000001 */ |
10675 | #define CAN_F16R2_FB0 CAN_F16R2_FB0_Msk /*!< Filter bit 0 */ |
| 10676 | #define CAN_F16R2_FB0 CAN_F16R2_FB0_Msk /*!< Filter bit 0 */ |
10676 | #define CAN_F16R2_FB1_Pos (1U) |
| 10677 | #define CAN_F16R2_FB1_Pos (1U) |
10677 | #define CAN_F16R2_FB1_Msk (0x1UL << CAN_F16R2_FB1_Pos) /*!< 0x00000002 */ |
| 10678 | #define CAN_F16R2_FB1_Msk (0x1UL << CAN_F16R2_FB1_Pos) /*!< 0x00000002 */ |
10678 | #define CAN_F16R2_FB1 CAN_F16R2_FB1_Msk /*!< Filter bit 1 */ |
| 10679 | #define CAN_F16R2_FB1 CAN_F16R2_FB1_Msk /*!< Filter bit 1 */ |
10679 | #define CAN_F16R2_FB2_Pos (2U) |
| 10680 | #define CAN_F16R2_FB2_Pos (2U) |
10680 | #define CAN_F16R2_FB2_Msk (0x1UL << CAN_F16R2_FB2_Pos) /*!< 0x00000004 */ |
| 10681 | #define CAN_F16R2_FB2_Msk (0x1UL << CAN_F16R2_FB2_Pos) /*!< 0x00000004 */ |
10681 | #define CAN_F16R2_FB2 CAN_F16R2_FB2_Msk /*!< Filter bit 2 */ |
| 10682 | #define CAN_F16R2_FB2 CAN_F16R2_FB2_Msk /*!< Filter bit 2 */ |
10682 | #define CAN_F16R2_FB3_Pos (3U) |
| 10683 | #define CAN_F16R2_FB3_Pos (3U) |
10683 | #define CAN_F16R2_FB3_Msk (0x1UL << CAN_F16R2_FB3_Pos) /*!< 0x00000008 */ |
| 10684 | #define CAN_F16R2_FB3_Msk (0x1UL << CAN_F16R2_FB3_Pos) /*!< 0x00000008 */ |
10684 | #define CAN_F16R2_FB3 CAN_F16R2_FB3_Msk /*!< Filter bit 3 */ |
| 10685 | #define CAN_F16R2_FB3 CAN_F16R2_FB3_Msk /*!< Filter bit 3 */ |
10685 | #define CAN_F16R2_FB4_Pos (4U) |
| 10686 | #define CAN_F16R2_FB4_Pos (4U) |
10686 | #define CAN_F16R2_FB4_Msk (0x1UL << CAN_F16R2_FB4_Pos) /*!< 0x00000010 */ |
| 10687 | #define CAN_F16R2_FB4_Msk (0x1UL << CAN_F16R2_FB4_Pos) /*!< 0x00000010 */ |
10687 | #define CAN_F16R2_FB4 CAN_F16R2_FB4_Msk /*!< Filter bit 4 */ |
| 10688 | #define CAN_F16R2_FB4 CAN_F16R2_FB4_Msk /*!< Filter bit 4 */ |
10688 | #define CAN_F16R2_FB5_Pos (5U) |
| 10689 | #define CAN_F16R2_FB5_Pos (5U) |
10689 | #define CAN_F16R2_FB5_Msk (0x1UL << CAN_F16R2_FB5_Pos) /*!< 0x00000020 */ |
| 10690 | #define CAN_F16R2_FB5_Msk (0x1UL << CAN_F16R2_FB5_Pos) /*!< 0x00000020 */ |
10690 | #define CAN_F16R2_FB5 CAN_F16R2_FB5_Msk /*!< Filter bit 5 */ |
| 10691 | #define CAN_F16R2_FB5 CAN_F16R2_FB5_Msk /*!< Filter bit 5 */ |
10691 | #define CAN_F16R2_FB6_Pos (6U) |
| 10692 | #define CAN_F16R2_FB6_Pos (6U) |
10692 | #define CAN_F16R2_FB6_Msk (0x1UL << CAN_F16R2_FB6_Pos) /*!< 0x00000040 */ |
| 10693 | #define CAN_F16R2_FB6_Msk (0x1UL << CAN_F16R2_FB6_Pos) /*!< 0x00000040 */ |
10693 | #define CAN_F16R2_FB6 CAN_F16R2_FB6_Msk /*!< Filter bit 6 */ |
| 10694 | #define CAN_F16R2_FB6 CAN_F16R2_FB6_Msk /*!< Filter bit 6 */ |
10694 | #define CAN_F16R2_FB7_Pos (7U) |
| 10695 | #define CAN_F16R2_FB7_Pos (7U) |
10695 | #define CAN_F16R2_FB7_Msk (0x1UL << CAN_F16R2_FB7_Pos) /*!< 0x00000080 */ |
| 10696 | #define CAN_F16R2_FB7_Msk (0x1UL << CAN_F16R2_FB7_Pos) /*!< 0x00000080 */ |
10696 | #define CAN_F16R2_FB7 CAN_F16R2_FB7_Msk /*!< Filter bit 7 */ |
| 10697 | #define CAN_F16R2_FB7 CAN_F16R2_FB7_Msk /*!< Filter bit 7 */ |
10697 | #define CAN_F16R2_FB8_Pos (8U) |
| 10698 | #define CAN_F16R2_FB8_Pos (8U) |
10698 | #define CAN_F16R2_FB8_Msk (0x1UL << CAN_F16R2_FB8_Pos) /*!< 0x00000100 */ |
| 10699 | #define CAN_F16R2_FB8_Msk (0x1UL << CAN_F16R2_FB8_Pos) /*!< 0x00000100 */ |
10699 | #define CAN_F16R2_FB8 CAN_F16R2_FB8_Msk /*!< Filter bit 8 */ |
| 10700 | #define CAN_F16R2_FB8 CAN_F16R2_FB8_Msk /*!< Filter bit 8 */ |
10700 | #define CAN_F16R2_FB9_Pos (9U) |
| 10701 | #define CAN_F16R2_FB9_Pos (9U) |
10701 | #define CAN_F16R2_FB9_Msk (0x1UL << CAN_F16R2_FB9_Pos) /*!< 0x00000200 */ |
| 10702 | #define CAN_F16R2_FB9_Msk (0x1UL << CAN_F16R2_FB9_Pos) /*!< 0x00000200 */ |
10702 | #define CAN_F16R2_FB9 CAN_F16R2_FB9_Msk /*!< Filter bit 9 */ |
| 10703 | #define CAN_F16R2_FB9 CAN_F16R2_FB9_Msk /*!< Filter bit 9 */ |
10703 | #define CAN_F16R2_FB10_Pos (10U) |
| 10704 | #define CAN_F16R2_FB10_Pos (10U) |
10704 | #define CAN_F16R2_FB10_Msk (0x1UL << CAN_F16R2_FB10_Pos) /*!< 0x00000400 */ |
| 10705 | #define CAN_F16R2_FB10_Msk (0x1UL << CAN_F16R2_FB10_Pos) /*!< 0x00000400 */ |
10705 | #define CAN_F16R2_FB10 CAN_F16R2_FB10_Msk /*!< Filter bit 10 */ |
| 10706 | #define CAN_F16R2_FB10 CAN_F16R2_FB10_Msk /*!< Filter bit 10 */ |
10706 | #define CAN_F16R2_FB11_Pos (11U) |
| 10707 | #define CAN_F16R2_FB11_Pos (11U) |
10707 | #define CAN_F16R2_FB11_Msk (0x1UL << CAN_F16R2_FB11_Pos) /*!< 0x00000800 */ |
| 10708 | #define CAN_F16R2_FB11_Msk (0x1UL << CAN_F16R2_FB11_Pos) /*!< 0x00000800 */ |
10708 | #define CAN_F16R2_FB11 CAN_F16R2_FB11_Msk /*!< Filter bit 11 */ |
| 10709 | #define CAN_F16R2_FB11 CAN_F16R2_FB11_Msk /*!< Filter bit 11 */ |
10709 | #define CAN_F16R2_FB12_Pos (12U) |
| 10710 | #define CAN_F16R2_FB12_Pos (12U) |
10710 | #define CAN_F16R2_FB12_Msk (0x1UL << CAN_F16R2_FB12_Pos) /*!< 0x00001000 */ |
| 10711 | #define CAN_F16R2_FB12_Msk (0x1UL << CAN_F16R2_FB12_Pos) /*!< 0x00001000 */ |
10711 | #define CAN_F16R2_FB12 CAN_F16R2_FB12_Msk /*!< Filter bit 12 */ |
| 10712 | #define CAN_F16R2_FB12 CAN_F16R2_FB12_Msk /*!< Filter bit 12 */ |
10712 | #define CAN_F16R2_FB13_Pos (13U) |
| 10713 | #define CAN_F16R2_FB13_Pos (13U) |
10713 | #define CAN_F16R2_FB13_Msk (0x1UL << CAN_F16R2_FB13_Pos) /*!< 0x00002000 */ |
| 10714 | #define CAN_F16R2_FB13_Msk (0x1UL << CAN_F16R2_FB13_Pos) /*!< 0x00002000 */ |
10714 | #define CAN_F16R2_FB13 CAN_F16R2_FB13_Msk /*!< Filter bit 13 */ |
| 10715 | #define CAN_F16R2_FB13 CAN_F16R2_FB13_Msk /*!< Filter bit 13 */ |
10715 | #define CAN_F16R2_FB14_Pos (14U) |
| 10716 | #define CAN_F16R2_FB14_Pos (14U) |
10716 | #define CAN_F16R2_FB14_Msk (0x1UL << CAN_F16R2_FB14_Pos) /*!< 0x00004000 */ |
| 10717 | #define CAN_F16R2_FB14_Msk (0x1UL << CAN_F16R2_FB14_Pos) /*!< 0x00004000 */ |
10717 | #define CAN_F16R2_FB14 CAN_F16R2_FB14_Msk /*!< Filter bit 14 */ |
| 10718 | #define CAN_F16R2_FB14 CAN_F16R2_FB14_Msk /*!< Filter bit 14 */ |
10718 | #define CAN_F16R2_FB15_Pos (15U) |
| 10719 | #define CAN_F16R2_FB15_Pos (15U) |
10719 | #define CAN_F16R2_FB15_Msk (0x1UL << CAN_F16R2_FB15_Pos) /*!< 0x00008000 */ |
| 10720 | #define CAN_F16R2_FB15_Msk (0x1UL << CAN_F16R2_FB15_Pos) /*!< 0x00008000 */ |
10720 | #define CAN_F16R2_FB15 CAN_F16R2_FB15_Msk /*!< Filter bit 15 */ |
| 10721 | #define CAN_F16R2_FB15 CAN_F16R2_FB15_Msk /*!< Filter bit 15 */ |
10721 | #define CAN_F16R2_FB16_Pos (16U) |
| 10722 | #define CAN_F16R2_FB16_Pos (16U) |
10722 | #define CAN_F16R2_FB16_Msk (0x1UL << CAN_F16R2_FB16_Pos) /*!< 0x00010000 */ |
| 10723 | #define CAN_F16R2_FB16_Msk (0x1UL << CAN_F16R2_FB16_Pos) /*!< 0x00010000 */ |
10723 | #define CAN_F16R2_FB16 CAN_F16R2_FB16_Msk /*!< Filter bit 16 */ |
| 10724 | #define CAN_F16R2_FB16 CAN_F16R2_FB16_Msk /*!< Filter bit 16 */ |
10724 | #define CAN_F16R2_FB17_Pos (17U) |
| 10725 | #define CAN_F16R2_FB17_Pos (17U) |
10725 | #define CAN_F16R2_FB17_Msk (0x1UL << CAN_F16R2_FB17_Pos) /*!< 0x00020000 */ |
| 10726 | #define CAN_F16R2_FB17_Msk (0x1UL << CAN_F16R2_FB17_Pos) /*!< 0x00020000 */ |
10726 | #define CAN_F16R2_FB17 CAN_F16R2_FB17_Msk /*!< Filter bit 17 */ |
| 10727 | #define CAN_F16R2_FB17 CAN_F16R2_FB17_Msk /*!< Filter bit 17 */ |
10727 | #define CAN_F16R2_FB18_Pos (18U) |
| 10728 | #define CAN_F16R2_FB18_Pos (18U) |
10728 | #define CAN_F16R2_FB18_Msk (0x1UL << CAN_F16R2_FB18_Pos) /*!< 0x00040000 */ |
| 10729 | #define CAN_F16R2_FB18_Msk (0x1UL << CAN_F16R2_FB18_Pos) /*!< 0x00040000 */ |
10729 | #define CAN_F16R2_FB18 CAN_F16R2_FB18_Msk /*!< Filter bit 18 */ |
| 10730 | #define CAN_F16R2_FB18 CAN_F16R2_FB18_Msk /*!< Filter bit 18 */ |
10730 | #define CAN_F16R2_FB19_Pos (19U) |
| 10731 | #define CAN_F16R2_FB19_Pos (19U) |
10731 | #define CAN_F16R2_FB19_Msk (0x1UL << CAN_F16R2_FB19_Pos) /*!< 0x00080000 */ |
| 10732 | #define CAN_F16R2_FB19_Msk (0x1UL << CAN_F16R2_FB19_Pos) /*!< 0x00080000 */ |
10732 | #define CAN_F16R2_FB19 CAN_F16R2_FB19_Msk /*!< Filter bit 19 */ |
| 10733 | #define CAN_F16R2_FB19 CAN_F16R2_FB19_Msk /*!< Filter bit 19 */ |
10733 | #define CAN_F16R2_FB20_Pos (20U) |
| 10734 | #define CAN_F16R2_FB20_Pos (20U) |
10734 | #define CAN_F16R2_FB20_Msk (0x1UL << CAN_F16R2_FB20_Pos) /*!< 0x00100000 */ |
| 10735 | #define CAN_F16R2_FB20_Msk (0x1UL << CAN_F16R2_FB20_Pos) /*!< 0x00100000 */ |
10735 | #define CAN_F16R2_FB20 CAN_F16R2_FB20_Msk /*!< Filter bit 20 */ |
| 10736 | #define CAN_F16R2_FB20 CAN_F16R2_FB20_Msk /*!< Filter bit 20 */ |
10736 | #define CAN_F16R2_FB21_Pos (21U) |
| 10737 | #define CAN_F16R2_FB21_Pos (21U) |
10737 | #define CAN_F16R2_FB21_Msk (0x1UL << CAN_F16R2_FB21_Pos) /*!< 0x00200000 */ |
| 10738 | #define CAN_F16R2_FB21_Msk (0x1UL << CAN_F16R2_FB21_Pos) /*!< 0x00200000 */ |
10738 | #define CAN_F16R2_FB21 CAN_F16R2_FB21_Msk /*!< Filter bit 21 */ |
| 10739 | #define CAN_F16R2_FB21 CAN_F16R2_FB21_Msk /*!< Filter bit 21 */ |
10739 | #define CAN_F16R2_FB22_Pos (22U) |
| 10740 | #define CAN_F16R2_FB22_Pos (22U) |
10740 | #define CAN_F16R2_FB22_Msk (0x1UL << CAN_F16R2_FB22_Pos) /*!< 0x00400000 */ |
| 10741 | #define CAN_F16R2_FB22_Msk (0x1UL << CAN_F16R2_FB22_Pos) /*!< 0x00400000 */ |
10741 | #define CAN_F16R2_FB22 CAN_F16R2_FB22_Msk /*!< Filter bit 22 */ |
| 10742 | #define CAN_F16R2_FB22 CAN_F16R2_FB22_Msk /*!< Filter bit 22 */ |
10742 | #define CAN_F16R2_FB23_Pos (23U) |
| 10743 | #define CAN_F16R2_FB23_Pos (23U) |
10743 | #define CAN_F16R2_FB23_Msk (0x1UL << CAN_F16R2_FB23_Pos) /*!< 0x00800000 */ |
| 10744 | #define CAN_F16R2_FB23_Msk (0x1UL << CAN_F16R2_FB23_Pos) /*!< 0x00800000 */ |
10744 | #define CAN_F16R2_FB23 CAN_F16R2_FB23_Msk /*!< Filter bit 23 */ |
| 10745 | #define CAN_F16R2_FB23 CAN_F16R2_FB23_Msk /*!< Filter bit 23 */ |
10745 | #define CAN_F16R2_FB24_Pos (24U) |
| 10746 | #define CAN_F16R2_FB24_Pos (24U) |
10746 | #define CAN_F16R2_FB24_Msk (0x1UL << CAN_F16R2_FB24_Pos) /*!< 0x01000000 */ |
| 10747 | #define CAN_F16R2_FB24_Msk (0x1UL << CAN_F16R2_FB24_Pos) /*!< 0x01000000 */ |
10747 | #define CAN_F16R2_FB24 CAN_F16R2_FB24_Msk /*!< Filter bit 24 */ |
| 10748 | #define CAN_F16R2_FB24 CAN_F16R2_FB24_Msk /*!< Filter bit 24 */ |
10748 | #define CAN_F16R2_FB25_Pos (25U) |
| 10749 | #define CAN_F16R2_FB25_Pos (25U) |
10749 | #define CAN_F16R2_FB25_Msk (0x1UL << CAN_F16R2_FB25_Pos) /*!< 0x02000000 */ |
| 10750 | #define CAN_F16R2_FB25_Msk (0x1UL << CAN_F16R2_FB25_Pos) /*!< 0x02000000 */ |
10750 | #define CAN_F16R2_FB25 CAN_F16R2_FB25_Msk /*!< Filter bit 25 */ |
| 10751 | #define CAN_F16R2_FB25 CAN_F16R2_FB25_Msk /*!< Filter bit 25 */ |
10751 | #define CAN_F16R2_FB26_Pos (26U) |
| 10752 | #define CAN_F16R2_FB26_Pos (26U) |
10752 | #define CAN_F16R2_FB26_Msk (0x1UL << CAN_F16R2_FB26_Pos) /*!< 0x04000000 */ |
| 10753 | #define CAN_F16R2_FB26_Msk (0x1UL << CAN_F16R2_FB26_Pos) /*!< 0x04000000 */ |
10753 | #define CAN_F16R2_FB26 CAN_F16R2_FB26_Msk /*!< Filter bit 26 */ |
| 10754 | #define CAN_F16R2_FB26 CAN_F16R2_FB26_Msk /*!< Filter bit 26 */ |
10754 | #define CAN_F16R2_FB27_Pos (27U) |
| 10755 | #define CAN_F16R2_FB27_Pos (27U) |
10755 | #define CAN_F16R2_FB27_Msk (0x1UL << CAN_F16R2_FB27_Pos) /*!< 0x08000000 */ |
| 10756 | #define CAN_F16R2_FB27_Msk (0x1UL << CAN_F16R2_FB27_Pos) /*!< 0x08000000 */ |
10756 | #define CAN_F16R2_FB27 CAN_F16R2_FB27_Msk /*!< Filter bit 27 */ |
| 10757 | #define CAN_F16R2_FB27 CAN_F16R2_FB27_Msk /*!< Filter bit 27 */ |
10757 | #define CAN_F16R2_FB28_Pos (28U) |
| 10758 | #define CAN_F16R2_FB28_Pos (28U) |
10758 | #define CAN_F16R2_FB28_Msk (0x1UL << CAN_F16R2_FB28_Pos) /*!< 0x10000000 */ |
| 10759 | #define CAN_F16R2_FB28_Msk (0x1UL << CAN_F16R2_FB28_Pos) /*!< 0x10000000 */ |
10759 | #define CAN_F16R2_FB28 CAN_F16R2_FB28_Msk /*!< Filter bit 28 */ |
| 10760 | #define CAN_F16R2_FB28 CAN_F16R2_FB28_Msk /*!< Filter bit 28 */ |
10760 | #define CAN_F16R2_FB29_Pos (29U) |
| 10761 | #define CAN_F16R2_FB29_Pos (29U) |
10761 | #define CAN_F16R2_FB29_Msk (0x1UL << CAN_F16R2_FB29_Pos) /*!< 0x20000000 */ |
| 10762 | #define CAN_F16R2_FB29_Msk (0x1UL << CAN_F16R2_FB29_Pos) /*!< 0x20000000 */ |
10762 | #define CAN_F16R2_FB29 CAN_F16R2_FB29_Msk /*!< Filter bit 29 */ |
| 10763 | #define CAN_F16R2_FB29 CAN_F16R2_FB29_Msk /*!< Filter bit 29 */ |
10763 | #define CAN_F16R2_FB30_Pos (30U) |
| 10764 | #define CAN_F16R2_FB30_Pos (30U) |
10764 | #define CAN_F16R2_FB30_Msk (0x1UL << CAN_F16R2_FB30_Pos) /*!< 0x40000000 */ |
| 10765 | #define CAN_F16R2_FB30_Msk (0x1UL << CAN_F16R2_FB30_Pos) /*!< 0x40000000 */ |
10765 | #define CAN_F16R2_FB30 CAN_F16R2_FB30_Msk /*!< Filter bit 30 */ |
| 10766 | #define CAN_F16R2_FB30 CAN_F16R2_FB30_Msk /*!< Filter bit 30 */ |
10766 | #define CAN_F16R2_FB31_Pos (31U) |
| 10767 | #define CAN_F16R2_FB31_Pos (31U) |
10767 | #define CAN_F16R2_FB31_Msk (0x1UL << CAN_F16R2_FB31_Pos) /*!< 0x80000000 */ |
| 10768 | #define CAN_F16R2_FB31_Msk (0x1UL << CAN_F16R2_FB31_Pos) /*!< 0x80000000 */ |
10768 | #define CAN_F16R2_FB31 CAN_F16R2_FB31_Msk /*!< Filter bit 31 */ |
| 10769 | #define CAN_F16R2_FB31 CAN_F16R2_FB31_Msk /*!< Filter bit 31 */ |
10769 | |
| 10770 | 10770 | /******************* Bit definition for CAN_F17R2 register ******************/ |
|
| 10771 | /******************* Bit definition for CAN_F17R2 register ******************/ |
10771 | #define CAN_F17R2_FB0_Pos (0U) |
| 10772 | #define CAN_F17R2_FB0_Pos (0U) |
10772 | #define CAN_F17R2_FB0_Msk (0x1UL << CAN_F17R2_FB0_Pos) /*!< 0x00000001 */ |
| 10773 | #define CAN_F17R2_FB0_Msk (0x1UL << CAN_F17R2_FB0_Pos) /*!< 0x00000001 */ |
10773 | #define CAN_F17R2_FB0 CAN_F17R2_FB0_Msk /*!< Filter bit 0 */ |
| 10774 | #define CAN_F17R2_FB0 CAN_F17R2_FB0_Msk /*!< Filter bit 0 */ |
10774 | #define CAN_F17R2_FB1_Pos (1U) |
| 10775 | #define CAN_F17R2_FB1_Pos (1U) |
10775 | #define CAN_F17R2_FB1_Msk (0x1UL << CAN_F17R2_FB1_Pos) /*!< 0x00000002 */ |
| 10776 | #define CAN_F17R2_FB1_Msk (0x1UL << CAN_F17R2_FB1_Pos) /*!< 0x00000002 */ |
10776 | #define CAN_F17R2_FB1 CAN_F17R2_FB1_Msk /*!< Filter bit 1 */ |
| 10777 | #define CAN_F17R2_FB1 CAN_F17R2_FB1_Msk /*!< Filter bit 1 */ |
10777 | #define CAN_F17R2_FB2_Pos (2U) |
| 10778 | #define CAN_F17R2_FB2_Pos (2U) |
10778 | #define CAN_F17R2_FB2_Msk (0x1UL << CAN_F17R2_FB2_Pos) /*!< 0x00000004 */ |
| 10779 | #define CAN_F17R2_FB2_Msk (0x1UL << CAN_F17R2_FB2_Pos) /*!< 0x00000004 */ |
10779 | #define CAN_F17R2_FB2 CAN_F17R2_FB2_Msk /*!< Filter bit 2 */ |
| 10780 | #define CAN_F17R2_FB2 CAN_F17R2_FB2_Msk /*!< Filter bit 2 */ |
10780 | #define CAN_F17R2_FB3_Pos (3U) |
| 10781 | #define CAN_F17R2_FB3_Pos (3U) |
10781 | #define CAN_F17R2_FB3_Msk (0x1UL << CAN_F17R2_FB3_Pos) /*!< 0x00000008 */ |
| 10782 | #define CAN_F17R2_FB3_Msk (0x1UL << CAN_F17R2_FB3_Pos) /*!< 0x00000008 */ |
10782 | #define CAN_F17R2_FB3 CAN_F17R2_FB3_Msk /*!< Filter bit 3 */ |
| 10783 | #define CAN_F17R2_FB3 CAN_F17R2_FB3_Msk /*!< Filter bit 3 */ |
10783 | #define CAN_F17R2_FB4_Pos (4U) |
| 10784 | #define CAN_F17R2_FB4_Pos (4U) |
10784 | #define CAN_F17R2_FB4_Msk (0x1UL << CAN_F17R2_FB4_Pos) /*!< 0x00000010 */ |
| 10785 | #define CAN_F17R2_FB4_Msk (0x1UL << CAN_F17R2_FB4_Pos) /*!< 0x00000010 */ |
10785 | #define CAN_F17R2_FB4 CAN_F17R2_FB4_Msk /*!< Filter bit 4 */ |
| 10786 | #define CAN_F17R2_FB4 CAN_F17R2_FB4_Msk /*!< Filter bit 4 */ |
10786 | #define CAN_F17R2_FB5_Pos (5U) |
| 10787 | #define CAN_F17R2_FB5_Pos (5U) |
10787 | #define CAN_F17R2_FB5_Msk (0x1UL << CAN_F17R2_FB5_Pos) /*!< 0x00000020 */ |
| 10788 | #define CAN_F17R2_FB5_Msk (0x1UL << CAN_F17R2_FB5_Pos) /*!< 0x00000020 */ |
10788 | #define CAN_F17R2_FB5 CAN_F17R2_FB5_Msk /*!< Filter bit 5 */ |
| 10789 | #define CAN_F17R2_FB5 CAN_F17R2_FB5_Msk /*!< Filter bit 5 */ |
10789 | #define CAN_F17R2_FB6_Pos (6U) |
| 10790 | #define CAN_F17R2_FB6_Pos (6U) |
10790 | #define CAN_F17R2_FB6_Msk (0x1UL << CAN_F17R2_FB6_Pos) /*!< 0x00000040 */ |
| 10791 | #define CAN_F17R2_FB6_Msk (0x1UL << CAN_F17R2_FB6_Pos) /*!< 0x00000040 */ |
10791 | #define CAN_F17R2_FB6 CAN_F17R2_FB6_Msk /*!< Filter bit 6 */ |
| 10792 | #define CAN_F17R2_FB6 CAN_F17R2_FB6_Msk /*!< Filter bit 6 */ |
10792 | #define CAN_F17R2_FB7_Pos (7U) |
| 10793 | #define CAN_F17R2_FB7_Pos (7U) |
10793 | #define CAN_F17R2_FB7_Msk (0x1UL << CAN_F17R2_FB7_Pos) /*!< 0x00000080 */ |
| 10794 | #define CAN_F17R2_FB7_Msk (0x1UL << CAN_F17R2_FB7_Pos) /*!< 0x00000080 */ |
10794 | #define CAN_F17R2_FB7 CAN_F17R2_FB7_Msk /*!< Filter bit 7 */ |
| 10795 | #define CAN_F17R2_FB7 CAN_F17R2_FB7_Msk /*!< Filter bit 7 */ |
10795 | #define CAN_F17R2_FB8_Pos (8U) |
| 10796 | #define CAN_F17R2_FB8_Pos (8U) |
10796 | #define CAN_F17R2_FB8_Msk (0x1UL << CAN_F17R2_FB8_Pos) /*!< 0x00000100 */ |
| 10797 | #define CAN_F17R2_FB8_Msk (0x1UL << CAN_F17R2_FB8_Pos) /*!< 0x00000100 */ |
10797 | #define CAN_F17R2_FB8 CAN_F17R2_FB8_Msk /*!< Filter bit 8 */ |
| 10798 | #define CAN_F17R2_FB8 CAN_F17R2_FB8_Msk /*!< Filter bit 8 */ |
10798 | #define CAN_F17R2_FB9_Pos (9U) |
| 10799 | #define CAN_F17R2_FB9_Pos (9U) |
10799 | #define CAN_F17R2_FB9_Msk (0x1UL << CAN_F17R2_FB9_Pos) /*!< 0x00000200 */ |
| 10800 | #define CAN_F17R2_FB9_Msk (0x1UL << CAN_F17R2_FB9_Pos) /*!< 0x00000200 */ |
10800 | #define CAN_F17R2_FB9 CAN_F17R2_FB9_Msk /*!< Filter bit 9 */ |
| 10801 | #define CAN_F17R2_FB9 CAN_F17R2_FB9_Msk /*!< Filter bit 9 */ |
10801 | #define CAN_F17R2_FB10_Pos (10U) |
| 10802 | #define CAN_F17R2_FB10_Pos (10U) |
10802 | #define CAN_F17R2_FB10_Msk (0x1UL << CAN_F17R2_FB10_Pos) /*!< 0x00000400 */ |
| 10803 | #define CAN_F17R2_FB10_Msk (0x1UL << CAN_F17R2_FB10_Pos) /*!< 0x00000400 */ |
10803 | #define CAN_F17R2_FB10 CAN_F17R2_FB10_Msk /*!< Filter bit 10 */ |
| 10804 | #define CAN_F17R2_FB10 CAN_F17R2_FB10_Msk /*!< Filter bit 10 */ |
10804 | #define CAN_F17R2_FB11_Pos (11U) |
| 10805 | #define CAN_F17R2_FB11_Pos (11U) |
10805 | #define CAN_F17R2_FB11_Msk (0x1UL << CAN_F17R2_FB11_Pos) /*!< 0x00000800 */ |
| 10806 | #define CAN_F17R2_FB11_Msk (0x1UL << CAN_F17R2_FB11_Pos) /*!< 0x00000800 */ |
10806 | #define CAN_F17R2_FB11 CAN_F17R2_FB11_Msk /*!< Filter bit 11 */ |
| 10807 | #define CAN_F17R2_FB11 CAN_F17R2_FB11_Msk /*!< Filter bit 11 */ |
10807 | #define CAN_F17R2_FB12_Pos (12U) |
| 10808 | #define CAN_F17R2_FB12_Pos (12U) |
10808 | #define CAN_F17R2_FB12_Msk (0x1UL << CAN_F17R2_FB12_Pos) /*!< 0x00001000 */ |
| 10809 | #define CAN_F17R2_FB12_Msk (0x1UL << CAN_F17R2_FB12_Pos) /*!< 0x00001000 */ |
10809 | #define CAN_F17R2_FB12 CAN_F17R2_FB12_Msk /*!< Filter bit 12 */ |
| 10810 | #define CAN_F17R2_FB12 CAN_F17R2_FB12_Msk /*!< Filter bit 12 */ |
10810 | #define CAN_F17R2_FB13_Pos (13U) |
| 10811 | #define CAN_F17R2_FB13_Pos (13U) |
10811 | #define CAN_F17R2_FB13_Msk (0x1UL << CAN_F17R2_FB13_Pos) /*!< 0x00002000 */ |
| 10812 | #define CAN_F17R2_FB13_Msk (0x1UL << CAN_F17R2_FB13_Pos) /*!< 0x00002000 */ |
10812 | #define CAN_F17R2_FB13 CAN_F17R2_FB13_Msk /*!< Filter bit 13 */ |
| 10813 | #define CAN_F17R2_FB13 CAN_F17R2_FB13_Msk /*!< Filter bit 13 */ |
10813 | #define CAN_F17R2_FB14_Pos (14U) |
| 10814 | #define CAN_F17R2_FB14_Pos (14U) |
10814 | #define CAN_F17R2_FB14_Msk (0x1UL << CAN_F17R2_FB14_Pos) /*!< 0x00004000 */ |
| 10815 | #define CAN_F17R2_FB14_Msk (0x1UL << CAN_F17R2_FB14_Pos) /*!< 0x00004000 */ |
10815 | #define CAN_F17R2_FB14 CAN_F17R2_FB14_Msk /*!< Filter bit 14 */ |
| 10816 | #define CAN_F17R2_FB14 CAN_F17R2_FB14_Msk /*!< Filter bit 14 */ |
10816 | #define CAN_F17R2_FB15_Pos (15U) |
| 10817 | #define CAN_F17R2_FB15_Pos (15U) |
10817 | #define CAN_F17R2_FB15_Msk (0x1UL << CAN_F17R2_FB15_Pos) /*!< 0x00008000 */ |
| 10818 | #define CAN_F17R2_FB15_Msk (0x1UL << CAN_F17R2_FB15_Pos) /*!< 0x00008000 */ |
10818 | #define CAN_F17R2_FB15 CAN_F17R2_FB15_Msk /*!< Filter bit 15 */ |
| 10819 | #define CAN_F17R2_FB15 CAN_F17R2_FB15_Msk /*!< Filter bit 15 */ |
10819 | #define CAN_F17R2_FB16_Pos (16U) |
| 10820 | #define CAN_F17R2_FB16_Pos (16U) |
10820 | #define CAN_F17R2_FB16_Msk (0x1UL << CAN_F17R2_FB16_Pos) /*!< 0x00010000 */ |
| 10821 | #define CAN_F17R2_FB16_Msk (0x1UL << CAN_F17R2_FB16_Pos) /*!< 0x00010000 */ |
10821 | #define CAN_F17R2_FB16 CAN_F17R2_FB16_Msk /*!< Filter bit 16 */ |
| 10822 | #define CAN_F17R2_FB16 CAN_F17R2_FB16_Msk /*!< Filter bit 16 */ |
10822 | #define CAN_F17R2_FB17_Pos (17U) |
| 10823 | #define CAN_F17R2_FB17_Pos (17U) |
10823 | #define CAN_F17R2_FB17_Msk (0x1UL << CAN_F17R2_FB17_Pos) /*!< 0x00020000 */ |
| 10824 | #define CAN_F17R2_FB17_Msk (0x1UL << CAN_F17R2_FB17_Pos) /*!< 0x00020000 */ |
10824 | #define CAN_F17R2_FB17 CAN_F17R2_FB17_Msk /*!< Filter bit 17 */ |
| 10825 | #define CAN_F17R2_FB17 CAN_F17R2_FB17_Msk /*!< Filter bit 17 */ |
10825 | #define CAN_F17R2_FB18_Pos (18U) |
| 10826 | #define CAN_F17R2_FB18_Pos (18U) |
10826 | #define CAN_F17R2_FB18_Msk (0x1UL << CAN_F17R2_FB18_Pos) /*!< 0x00040000 */ |
| 10827 | #define CAN_F17R2_FB18_Msk (0x1UL << CAN_F17R2_FB18_Pos) /*!< 0x00040000 */ |
10827 | #define CAN_F17R2_FB18 CAN_F17R2_FB18_Msk /*!< Filter bit 18 */ |
| 10828 | #define CAN_F17R2_FB18 CAN_F17R2_FB18_Msk /*!< Filter bit 18 */ |
10828 | #define CAN_F17R2_FB19_Pos (19U) |
| 10829 | #define CAN_F17R2_FB19_Pos (19U) |
10829 | #define CAN_F17R2_FB19_Msk (0x1UL << CAN_F17R2_FB19_Pos) /*!< 0x00080000 */ |
| 10830 | #define CAN_F17R2_FB19_Msk (0x1UL << CAN_F17R2_FB19_Pos) /*!< 0x00080000 */ |
10830 | #define CAN_F17R2_FB19 CAN_F17R2_FB19_Msk /*!< Filter bit 19 */ |
| 10831 | #define CAN_F17R2_FB19 CAN_F17R2_FB19_Msk /*!< Filter bit 19 */ |
10831 | #define CAN_F17R2_FB20_Pos (20U) |
| 10832 | #define CAN_F17R2_FB20_Pos (20U) |
10832 | #define CAN_F17R2_FB20_Msk (0x1UL << CAN_F17R2_FB20_Pos) /*!< 0x00100000 */ |
| 10833 | #define CAN_F17R2_FB20_Msk (0x1UL << CAN_F17R2_FB20_Pos) /*!< 0x00100000 */ |
10833 | #define CAN_F17R2_FB20 CAN_F17R2_FB20_Msk /*!< Filter bit 20 */ |
| 10834 | #define CAN_F17R2_FB20 CAN_F17R2_FB20_Msk /*!< Filter bit 20 */ |
10834 | #define CAN_F17R2_FB21_Pos (21U) |
| 10835 | #define CAN_F17R2_FB21_Pos (21U) |
10835 | #define CAN_F17R2_FB21_Msk (0x1UL << CAN_F17R2_FB21_Pos) /*!< 0x00200000 */ |
| 10836 | #define CAN_F17R2_FB21_Msk (0x1UL << CAN_F17R2_FB21_Pos) /*!< 0x00200000 */ |
10836 | #define CAN_F17R2_FB21 CAN_F17R2_FB21_Msk /*!< Filter bit 21 */ |
| 10837 | #define CAN_F17R2_FB21 CAN_F17R2_FB21_Msk /*!< Filter bit 21 */ |
10837 | #define CAN_F17R2_FB22_Pos (22U) |
| 10838 | #define CAN_F17R2_FB22_Pos (22U) |
10838 | #define CAN_F17R2_FB22_Msk (0x1UL << CAN_F17R2_FB22_Pos) /*!< 0x00400000 */ |
| 10839 | #define CAN_F17R2_FB22_Msk (0x1UL << CAN_F17R2_FB22_Pos) /*!< 0x00400000 */ |
10839 | #define CAN_F17R2_FB22 CAN_F17R2_FB22_Msk /*!< Filter bit 22 */ |
| 10840 | #define CAN_F17R2_FB22 CAN_F17R2_FB22_Msk /*!< Filter bit 22 */ |
10840 | #define CAN_F17R2_FB23_Pos (23U) |
| 10841 | #define CAN_F17R2_FB23_Pos (23U) |
10841 | #define CAN_F17R2_FB23_Msk (0x1UL << CAN_F17R2_FB23_Pos) /*!< 0x00800000 */ |
| 10842 | #define CAN_F17R2_FB23_Msk (0x1UL << CAN_F17R2_FB23_Pos) /*!< 0x00800000 */ |
10842 | #define CAN_F17R2_FB23 CAN_F17R2_FB23_Msk /*!< Filter bit 23 */ |
| 10843 | #define CAN_F17R2_FB23 CAN_F17R2_FB23_Msk /*!< Filter bit 23 */ |
10843 | #define CAN_F17R2_FB24_Pos (24U) |
| 10844 | #define CAN_F17R2_FB24_Pos (24U) |
10844 | #define CAN_F17R2_FB24_Msk (0x1UL << CAN_F17R2_FB24_Pos) /*!< 0x01000000 */ |
| 10845 | #define CAN_F17R2_FB24_Msk (0x1UL << CAN_F17R2_FB24_Pos) /*!< 0x01000000 */ |
10845 | #define CAN_F17R2_FB24 CAN_F17R2_FB24_Msk /*!< Filter bit 24 */ |
| 10846 | #define CAN_F17R2_FB24 CAN_F17R2_FB24_Msk /*!< Filter bit 24 */ |
10846 | #define CAN_F17R2_FB25_Pos (25U) |
| 10847 | #define CAN_F17R2_FB25_Pos (25U) |
10847 | #define CAN_F17R2_FB25_Msk (0x1UL << CAN_F17R2_FB25_Pos) /*!< 0x02000000 */ |
| 10848 | #define CAN_F17R2_FB25_Msk (0x1UL << CAN_F17R2_FB25_Pos) /*!< 0x02000000 */ |
10848 | #define CAN_F17R2_FB25 CAN_F17R2_FB25_Msk /*!< Filter bit 25 */ |
| 10849 | #define CAN_F17R2_FB25 CAN_F17R2_FB25_Msk /*!< Filter bit 25 */ |
10849 | #define CAN_F17R2_FB26_Pos (26U) |
| 10850 | #define CAN_F17R2_FB26_Pos (26U) |
10850 | #define CAN_F17R2_FB26_Msk (0x1UL << CAN_F17R2_FB26_Pos) /*!< 0x04000000 */ |
| 10851 | #define CAN_F17R2_FB26_Msk (0x1UL << CAN_F17R2_FB26_Pos) /*!< 0x04000000 */ |
10851 | #define CAN_F17R2_FB26 CAN_F17R2_FB26_Msk /*!< Filter bit 26 */ |
| 10852 | #define CAN_F17R2_FB26 CAN_F17R2_FB26_Msk /*!< Filter bit 26 */ |
10852 | #define CAN_F17R2_FB27_Pos (27U) |
| 10853 | #define CAN_F17R2_FB27_Pos (27U) |
10853 | #define CAN_F17R2_FB27_Msk (0x1UL << CAN_F17R2_FB27_Pos) /*!< 0x08000000 */ |
| 10854 | #define CAN_F17R2_FB27_Msk (0x1UL << CAN_F17R2_FB27_Pos) /*!< 0x08000000 */ |
10854 | #define CAN_F17R2_FB27 CAN_F17R2_FB27_Msk /*!< Filter bit 27 */ |
| 10855 | #define CAN_F17R2_FB27 CAN_F17R2_FB27_Msk /*!< Filter bit 27 */ |
10855 | #define CAN_F17R2_FB28_Pos (28U) |
| 10856 | #define CAN_F17R2_FB28_Pos (28U) |
10856 | #define CAN_F17R2_FB28_Msk (0x1UL << CAN_F17R2_FB28_Pos) /*!< 0x10000000 */ |
| 10857 | #define CAN_F17R2_FB28_Msk (0x1UL << CAN_F17R2_FB28_Pos) /*!< 0x10000000 */ |
10857 | #define CAN_F17R2_FB28 CAN_F17R2_FB28_Msk /*!< Filter bit 28 */ |
| 10858 | #define CAN_F17R2_FB28 CAN_F17R2_FB28_Msk /*!< Filter bit 28 */ |
10858 | #define CAN_F17R2_FB29_Pos (29U) |
| 10859 | #define CAN_F17R2_FB29_Pos (29U) |
10859 | #define CAN_F17R2_FB29_Msk (0x1UL << CAN_F17R2_FB29_Pos) /*!< 0x20000000 */ |
| 10860 | #define CAN_F17R2_FB29_Msk (0x1UL << CAN_F17R2_FB29_Pos) /*!< 0x20000000 */ |
10860 | #define CAN_F17R2_FB29 CAN_F17R2_FB29_Msk /*!< Filter bit 29 */ |
| 10861 | #define CAN_F17R2_FB29 CAN_F17R2_FB29_Msk /*!< Filter bit 29 */ |
10861 | #define CAN_F17R2_FB30_Pos (30U) |
| 10862 | #define CAN_F17R2_FB30_Pos (30U) |
10862 | #define CAN_F17R2_FB30_Msk (0x1UL << CAN_F17R2_FB30_Pos) /*!< 0x40000000 */ |
| 10863 | #define CAN_F17R2_FB30_Msk (0x1UL << CAN_F17R2_FB30_Pos) /*!< 0x40000000 */ |
10863 | #define CAN_F17R2_FB30 CAN_F17R2_FB30_Msk /*!< Filter bit 30 */ |
| 10864 | #define CAN_F17R2_FB30 CAN_F17R2_FB30_Msk /*!< Filter bit 30 */ |
10864 | #define CAN_F17R2_FB31_Pos (31U) |
| 10865 | #define CAN_F17R2_FB31_Pos (31U) |
10865 | #define CAN_F17R2_FB31_Msk (0x1UL << CAN_F17R2_FB31_Pos) /*!< 0x80000000 */ |
| 10866 | #define CAN_F17R2_FB31_Msk (0x1UL << CAN_F17R2_FB31_Pos) /*!< 0x80000000 */ |
10866 | #define CAN_F17R2_FB31 CAN_F17R2_FB31_Msk /*!< Filter bit 31 */ |
| 10867 | #define CAN_F17R2_FB31 CAN_F17R2_FB31_Msk /*!< Filter bit 31 */ |
10867 | |
| 10868 | 10868 | /******************* Bit definition for CAN_F18R2 register ******************/ |
|
| 10869 | /******************* Bit definition for CAN_F18R2 register ******************/ |
10869 | #define CAN_F18R2_FB0_Pos (0U) |
| 10870 | #define CAN_F18R2_FB0_Pos (0U) |
10870 | #define CAN_F18R2_FB0_Msk (0x1UL << CAN_F18R2_FB0_Pos) /*!< 0x00000001 */ |
| 10871 | #define CAN_F18R2_FB0_Msk (0x1UL << CAN_F18R2_FB0_Pos) /*!< 0x00000001 */ |
10871 | #define CAN_F18R2_FB0 CAN_F18R2_FB0_Msk /*!< Filter bit 0 */ |
| 10872 | #define CAN_F18R2_FB0 CAN_F18R2_FB0_Msk /*!< Filter bit 0 */ |
10872 | #define CAN_F18R2_FB1_Pos (1U) |
| 10873 | #define CAN_F18R2_FB1_Pos (1U) |
10873 | #define CAN_F18R2_FB1_Msk (0x1UL << CAN_F18R2_FB1_Pos) /*!< 0x00000002 */ |
| 10874 | #define CAN_F18R2_FB1_Msk (0x1UL << CAN_F18R2_FB1_Pos) /*!< 0x00000002 */ |
10874 | #define CAN_F18R2_FB1 CAN_F18R2_FB1_Msk /*!< Filter bit 1 */ |
| 10875 | #define CAN_F18R2_FB1 CAN_F18R2_FB1_Msk /*!< Filter bit 1 */ |
10875 | #define CAN_F18R2_FB2_Pos (2U) |
| 10876 | #define CAN_F18R2_FB2_Pos (2U) |
10876 | #define CAN_F18R2_FB2_Msk (0x1UL << CAN_F18R2_FB2_Pos) /*!< 0x00000004 */ |
| 10877 | #define CAN_F18R2_FB2_Msk (0x1UL << CAN_F18R2_FB2_Pos) /*!< 0x00000004 */ |
10877 | #define CAN_F18R2_FB2 CAN_F18R2_FB2_Msk /*!< Filter bit 2 */ |
| 10878 | #define CAN_F18R2_FB2 CAN_F18R2_FB2_Msk /*!< Filter bit 2 */ |
10878 | #define CAN_F18R2_FB3_Pos (3U) |
| 10879 | #define CAN_F18R2_FB3_Pos (3U) |
10879 | #define CAN_F18R2_FB3_Msk (0x1UL << CAN_F18R2_FB3_Pos) /*!< 0x00000008 */ |
| 10880 | #define CAN_F18R2_FB3_Msk (0x1UL << CAN_F18R2_FB3_Pos) /*!< 0x00000008 */ |
10880 | #define CAN_F18R2_FB3 CAN_F18R2_FB3_Msk /*!< Filter bit 3 */ |
| 10881 | #define CAN_F18R2_FB3 CAN_F18R2_FB3_Msk /*!< Filter bit 3 */ |
10881 | #define CAN_F18R2_FB4_Pos (4U) |
| 10882 | #define CAN_F18R2_FB4_Pos (4U) |
10882 | #define CAN_F18R2_FB4_Msk (0x1UL << CAN_F18R2_FB4_Pos) /*!< 0x00000010 */ |
| 10883 | #define CAN_F18R2_FB4_Msk (0x1UL << CAN_F18R2_FB4_Pos) /*!< 0x00000010 */ |
10883 | #define CAN_F18R2_FB4 CAN_F18R2_FB4_Msk /*!< Filter bit 4 */ |
| 10884 | #define CAN_F18R2_FB4 CAN_F18R2_FB4_Msk /*!< Filter bit 4 */ |
10884 | #define CAN_F18R2_FB5_Pos (5U) |
| 10885 | #define CAN_F18R2_FB5_Pos (5U) |
10885 | #define CAN_F18R2_FB5_Msk (0x1UL << CAN_F18R2_FB5_Pos) /*!< 0x00000020 */ |
| 10886 | #define CAN_F18R2_FB5_Msk (0x1UL << CAN_F18R2_FB5_Pos) /*!< 0x00000020 */ |
10886 | #define CAN_F18R2_FB5 CAN_F18R2_FB5_Msk /*!< Filter bit 5 */ |
| 10887 | #define CAN_F18R2_FB5 CAN_F18R2_FB5_Msk /*!< Filter bit 5 */ |
10887 | #define CAN_F18R2_FB6_Pos (6U) |
| 10888 | #define CAN_F18R2_FB6_Pos (6U) |
10888 | #define CAN_F18R2_FB6_Msk (0x1UL << CAN_F18R2_FB6_Pos) /*!< 0x00000040 */ |
| 10889 | #define CAN_F18R2_FB6_Msk (0x1UL << CAN_F18R2_FB6_Pos) /*!< 0x00000040 */ |
10889 | #define CAN_F18R2_FB6 CAN_F18R2_FB6_Msk /*!< Filter bit 6 */ |
| 10890 | #define CAN_F18R2_FB6 CAN_F18R2_FB6_Msk /*!< Filter bit 6 */ |
10890 | #define CAN_F18R2_FB7_Pos (7U) |
| 10891 | #define CAN_F18R2_FB7_Pos (7U) |
10891 | #define CAN_F18R2_FB7_Msk (0x1UL << CAN_F18R2_FB7_Pos) /*!< 0x00000080 */ |
| 10892 | #define CAN_F18R2_FB7_Msk (0x1UL << CAN_F18R2_FB7_Pos) /*!< 0x00000080 */ |
10892 | #define CAN_F18R2_FB7 CAN_F18R2_FB7_Msk /*!< Filter bit 7 */ |
| 10893 | #define CAN_F18R2_FB7 CAN_F18R2_FB7_Msk /*!< Filter bit 7 */ |
10893 | #define CAN_F18R2_FB8_Pos (8U) |
| 10894 | #define CAN_F18R2_FB8_Pos (8U) |
10894 | #define CAN_F18R2_FB8_Msk (0x1UL << CAN_F18R2_FB8_Pos) /*!< 0x00000100 */ |
| 10895 | #define CAN_F18R2_FB8_Msk (0x1UL << CAN_F18R2_FB8_Pos) /*!< 0x00000100 */ |
10895 | #define CAN_F18R2_FB8 CAN_F18R2_FB8_Msk /*!< Filter bit 8 */ |
| 10896 | #define CAN_F18R2_FB8 CAN_F18R2_FB8_Msk /*!< Filter bit 8 */ |
10896 | #define CAN_F18R2_FB9_Pos (9U) |
| 10897 | #define CAN_F18R2_FB9_Pos (9U) |
10897 | #define CAN_F18R2_FB9_Msk (0x1UL << CAN_F18R2_FB9_Pos) /*!< 0x00000200 */ |
| 10898 | #define CAN_F18R2_FB9_Msk (0x1UL << CAN_F18R2_FB9_Pos) /*!< 0x00000200 */ |
10898 | #define CAN_F18R2_FB9 CAN_F18R2_FB9_Msk /*!< Filter bit 9 */ |
| 10899 | #define CAN_F18R2_FB9 CAN_F18R2_FB9_Msk /*!< Filter bit 9 */ |
10899 | #define CAN_F18R2_FB10_Pos (10U) |
| 10900 | #define CAN_F18R2_FB10_Pos (10U) |
10900 | #define CAN_F18R2_FB10_Msk (0x1UL << CAN_F18R2_FB10_Pos) /*!< 0x00000400 */ |
| 10901 | #define CAN_F18R2_FB10_Msk (0x1UL << CAN_F18R2_FB10_Pos) /*!< 0x00000400 */ |
10901 | #define CAN_F18R2_FB10 CAN_F18R2_FB10_Msk /*!< Filter bit 10 */ |
| 10902 | #define CAN_F18R2_FB10 CAN_F18R2_FB10_Msk /*!< Filter bit 10 */ |
10902 | #define CAN_F18R2_FB11_Pos (11U) |
| 10903 | #define CAN_F18R2_FB11_Pos (11U) |
10903 | #define CAN_F18R2_FB11_Msk (0x1UL << CAN_F18R2_FB11_Pos) /*!< 0x00000800 */ |
| 10904 | #define CAN_F18R2_FB11_Msk (0x1UL << CAN_F18R2_FB11_Pos) /*!< 0x00000800 */ |
10904 | #define CAN_F18R2_FB11 CAN_F18R2_FB11_Msk /*!< Filter bit 11 */ |
| 10905 | #define CAN_F18R2_FB11 CAN_F18R2_FB11_Msk /*!< Filter bit 11 */ |
10905 | #define CAN_F18R2_FB12_Pos (12U) |
| 10906 | #define CAN_F18R2_FB12_Pos (12U) |
10906 | #define CAN_F18R2_FB12_Msk (0x1UL << CAN_F18R2_FB12_Pos) /*!< 0x00001000 */ |
| 10907 | #define CAN_F18R2_FB12_Msk (0x1UL << CAN_F18R2_FB12_Pos) /*!< 0x00001000 */ |
10907 | #define CAN_F18R2_FB12 CAN_F18R2_FB12_Msk /*!< Filter bit 12 */ |
| 10908 | #define CAN_F18R2_FB12 CAN_F18R2_FB12_Msk /*!< Filter bit 12 */ |
10908 | #define CAN_F18R2_FB13_Pos (13U) |
| 10909 | #define CAN_F18R2_FB13_Pos (13U) |
10909 | #define CAN_F18R2_FB13_Msk (0x1UL << CAN_F18R2_FB13_Pos) /*!< 0x00002000 */ |
| 10910 | #define CAN_F18R2_FB13_Msk (0x1UL << CAN_F18R2_FB13_Pos) /*!< 0x00002000 */ |
10910 | #define CAN_F18R2_FB13 CAN_F18R2_FB13_Msk /*!< Filter bit 13 */ |
| 10911 | #define CAN_F18R2_FB13 CAN_F18R2_FB13_Msk /*!< Filter bit 13 */ |
10911 | #define CAN_F18R2_FB14_Pos (14U) |
| 10912 | #define CAN_F18R2_FB14_Pos (14U) |
10912 | #define CAN_F18R2_FB14_Msk (0x1UL << CAN_F18R2_FB14_Pos) /*!< 0x00004000 */ |
| 10913 | #define CAN_F18R2_FB14_Msk (0x1UL << CAN_F18R2_FB14_Pos) /*!< 0x00004000 */ |
10913 | #define CAN_F18R2_FB14 CAN_F18R2_FB14_Msk /*!< Filter bit 14 */ |
| 10914 | #define CAN_F18R2_FB14 CAN_F18R2_FB14_Msk /*!< Filter bit 14 */ |
10914 | #define CAN_F18R2_FB15_Pos (15U) |
| 10915 | #define CAN_F18R2_FB15_Pos (15U) |
10915 | #define CAN_F18R2_FB15_Msk (0x1UL << CAN_F18R2_FB15_Pos) /*!< 0x00008000 */ |
| 10916 | #define CAN_F18R2_FB15_Msk (0x1UL << CAN_F18R2_FB15_Pos) /*!< 0x00008000 */ |
10916 | #define CAN_F18R2_FB15 CAN_F18R2_FB15_Msk /*!< Filter bit 15 */ |
| 10917 | #define CAN_F18R2_FB15 CAN_F18R2_FB15_Msk /*!< Filter bit 15 */ |
10917 | #define CAN_F18R2_FB16_Pos (16U) |
| 10918 | #define CAN_F18R2_FB16_Pos (16U) |
10918 | #define CAN_F18R2_FB16_Msk (0x1UL << CAN_F18R2_FB16_Pos) /*!< 0x00010000 */ |
| 10919 | #define CAN_F18R2_FB16_Msk (0x1UL << CAN_F18R2_FB16_Pos) /*!< 0x00010000 */ |
10919 | #define CAN_F18R2_FB16 CAN_F18R2_FB16_Msk /*!< Filter bit 16 */ |
| 10920 | #define CAN_F18R2_FB16 CAN_F18R2_FB16_Msk /*!< Filter bit 16 */ |
10920 | #define CAN_F18R2_FB17_Pos (17U) |
| 10921 | #define CAN_F18R2_FB17_Pos (17U) |
10921 | #define CAN_F18R2_FB17_Msk (0x1UL << CAN_F18R2_FB17_Pos) /*!< 0x00020000 */ |
| 10922 | #define CAN_F18R2_FB17_Msk (0x1UL << CAN_F18R2_FB17_Pos) /*!< 0x00020000 */ |
10922 | #define CAN_F18R2_FB17 CAN_F18R2_FB17_Msk /*!< Filter bit 17 */ |
| 10923 | #define CAN_F18R2_FB17 CAN_F18R2_FB17_Msk /*!< Filter bit 17 */ |
10923 | #define CAN_F18R2_FB18_Pos (18U) |
| 10924 | #define CAN_F18R2_FB18_Pos (18U) |
10924 | #define CAN_F18R2_FB18_Msk (0x1UL << CAN_F18R2_FB18_Pos) /*!< 0x00040000 */ |
| 10925 | #define CAN_F18R2_FB18_Msk (0x1UL << CAN_F18R2_FB18_Pos) /*!< 0x00040000 */ |
10925 | #define CAN_F18R2_FB18 CAN_F18R2_FB18_Msk /*!< Filter bit 18 */ |
| 10926 | #define CAN_F18R2_FB18 CAN_F18R2_FB18_Msk /*!< Filter bit 18 */ |
10926 | #define CAN_F18R2_FB19_Pos (19U) |
| 10927 | #define CAN_F18R2_FB19_Pos (19U) |
10927 | #define CAN_F18R2_FB19_Msk (0x1UL << CAN_F18R2_FB19_Pos) /*!< 0x00080000 */ |
| 10928 | #define CAN_F18R2_FB19_Msk (0x1UL << CAN_F18R2_FB19_Pos) /*!< 0x00080000 */ |
10928 | #define CAN_F18R2_FB19 CAN_F18R2_FB19_Msk /*!< Filter bit 19 */ |
| 10929 | #define CAN_F18R2_FB19 CAN_F18R2_FB19_Msk /*!< Filter bit 19 */ |
10929 | #define CAN_F18R2_FB20_Pos (20U) |
| 10930 | #define CAN_F18R2_FB20_Pos (20U) |
10930 | #define CAN_F18R2_FB20_Msk (0x1UL << CAN_F18R2_FB20_Pos) /*!< 0x00100000 */ |
| 10931 | #define CAN_F18R2_FB20_Msk (0x1UL << CAN_F18R2_FB20_Pos) /*!< 0x00100000 */ |
10931 | #define CAN_F18R2_FB20 CAN_F18R2_FB20_Msk /*!< Filter bit 20 */ |
| 10932 | #define CAN_F18R2_FB20 CAN_F18R2_FB20_Msk /*!< Filter bit 20 */ |
10932 | #define CAN_F18R2_FB21_Pos (21U) |
| 10933 | #define CAN_F18R2_FB21_Pos (21U) |
10933 | #define CAN_F18R2_FB21_Msk (0x1UL << CAN_F18R2_FB21_Pos) /*!< 0x00200000 */ |
| 10934 | #define CAN_F18R2_FB21_Msk (0x1UL << CAN_F18R2_FB21_Pos) /*!< 0x00200000 */ |
10934 | #define CAN_F18R2_FB21 CAN_F18R2_FB21_Msk /*!< Filter bit 21 */ |
| 10935 | #define CAN_F18R2_FB21 CAN_F18R2_FB21_Msk /*!< Filter bit 21 */ |
10935 | #define CAN_F18R2_FB22_Pos (22U) |
| 10936 | #define CAN_F18R2_FB22_Pos (22U) |
10936 | #define CAN_F18R2_FB22_Msk (0x1UL << CAN_F18R2_FB22_Pos) /*!< 0x00400000 */ |
| 10937 | #define CAN_F18R2_FB22_Msk (0x1UL << CAN_F18R2_FB22_Pos) /*!< 0x00400000 */ |
10937 | #define CAN_F18R2_FB22 CAN_F18R2_FB22_Msk /*!< Filter bit 22 */ |
| 10938 | #define CAN_F18R2_FB22 CAN_F18R2_FB22_Msk /*!< Filter bit 22 */ |
10938 | #define CAN_F18R2_FB23_Pos (23U) |
| 10939 | #define CAN_F18R2_FB23_Pos (23U) |
10939 | #define CAN_F18R2_FB23_Msk (0x1UL << CAN_F18R2_FB23_Pos) /*!< 0x00800000 */ |
| 10940 | #define CAN_F18R2_FB23_Msk (0x1UL << CAN_F18R2_FB23_Pos) /*!< 0x00800000 */ |
10940 | #define CAN_F18R2_FB23 CAN_F18R2_FB23_Msk /*!< Filter bit 23 */ |
| 10941 | #define CAN_F18R2_FB23 CAN_F18R2_FB23_Msk /*!< Filter bit 23 */ |
10941 | #define CAN_F18R2_FB24_Pos (24U) |
| 10942 | #define CAN_F18R2_FB24_Pos (24U) |
10942 | #define CAN_F18R2_FB24_Msk (0x1UL << CAN_F18R2_FB24_Pos) /*!< 0x01000000 */ |
| 10943 | #define CAN_F18R2_FB24_Msk (0x1UL << CAN_F18R2_FB24_Pos) /*!< 0x01000000 */ |
10943 | #define CAN_F18R2_FB24 CAN_F18R2_FB24_Msk /*!< Filter bit 24 */ |
| 10944 | #define CAN_F18R2_FB24 CAN_F18R2_FB24_Msk /*!< Filter bit 24 */ |
10944 | #define CAN_F18R2_FB25_Pos (25U) |
| 10945 | #define CAN_F18R2_FB25_Pos (25U) |
10945 | #define CAN_F18R2_FB25_Msk (0x1UL << CAN_F18R2_FB25_Pos) /*!< 0x02000000 */ |
| 10946 | #define CAN_F18R2_FB25_Msk (0x1UL << CAN_F18R2_FB25_Pos) /*!< 0x02000000 */ |
10946 | #define CAN_F18R2_FB25 CAN_F18R2_FB25_Msk /*!< Filter bit 25 */ |
| 10947 | #define CAN_F18R2_FB25 CAN_F18R2_FB25_Msk /*!< Filter bit 25 */ |
10947 | #define CAN_F18R2_FB26_Pos (26U) |
| 10948 | #define CAN_F18R2_FB26_Pos (26U) |
10948 | #define CAN_F18R2_FB26_Msk (0x1UL << CAN_F18R2_FB26_Pos) /*!< 0x04000000 */ |
| 10949 | #define CAN_F18R2_FB26_Msk (0x1UL << CAN_F18R2_FB26_Pos) /*!< 0x04000000 */ |
10949 | #define CAN_F18R2_FB26 CAN_F18R2_FB26_Msk /*!< Filter bit 26 */ |
| 10950 | #define CAN_F18R2_FB26 CAN_F18R2_FB26_Msk /*!< Filter bit 26 */ |
10950 | #define CAN_F18R2_FB27_Pos (27U) |
| 10951 | #define CAN_F18R2_FB27_Pos (27U) |
10951 | #define CAN_F18R2_FB27_Msk (0x1UL << CAN_F18R2_FB27_Pos) /*!< 0x08000000 */ |
| 10952 | #define CAN_F18R2_FB27_Msk (0x1UL << CAN_F18R2_FB27_Pos) /*!< 0x08000000 */ |
10952 | #define CAN_F18R2_FB27 CAN_F18R2_FB27_Msk /*!< Filter bit 27 */ |
| 10953 | #define CAN_F18R2_FB27 CAN_F18R2_FB27_Msk /*!< Filter bit 27 */ |
10953 | #define CAN_F18R2_FB28_Pos (28U) |
| 10954 | #define CAN_F18R2_FB28_Pos (28U) |
10954 | #define CAN_F18R2_FB28_Msk (0x1UL << CAN_F18R2_FB28_Pos) /*!< 0x10000000 */ |
| 10955 | #define CAN_F18R2_FB28_Msk (0x1UL << CAN_F18R2_FB28_Pos) /*!< 0x10000000 */ |
10955 | #define CAN_F18R2_FB28 CAN_F18R2_FB28_Msk /*!< Filter bit 28 */ |
| 10956 | #define CAN_F18R2_FB28 CAN_F18R2_FB28_Msk /*!< Filter bit 28 */ |
10956 | #define CAN_F18R2_FB29_Pos (29U) |
| 10957 | #define CAN_F18R2_FB29_Pos (29U) |
10957 | #define CAN_F18R2_FB29_Msk (0x1UL << CAN_F18R2_FB29_Pos) /*!< 0x20000000 */ |
| 10958 | #define CAN_F18R2_FB29_Msk (0x1UL << CAN_F18R2_FB29_Pos) /*!< 0x20000000 */ |
10958 | #define CAN_F18R2_FB29 CAN_F18R2_FB29_Msk /*!< Filter bit 29 */ |
| 10959 | #define CAN_F18R2_FB29 CAN_F18R2_FB29_Msk /*!< Filter bit 29 */ |
10959 | #define CAN_F18R2_FB30_Pos (30U) |
| 10960 | #define CAN_F18R2_FB30_Pos (30U) |
10960 | #define CAN_F18R2_FB30_Msk (0x1UL << CAN_F18R2_FB30_Pos) /*!< 0x40000000 */ |
| 10961 | #define CAN_F18R2_FB30_Msk (0x1UL << CAN_F18R2_FB30_Pos) /*!< 0x40000000 */ |
10961 | #define CAN_F18R2_FB30 CAN_F18R2_FB30_Msk /*!< Filter bit 30 */ |
| 10962 | #define CAN_F18R2_FB30 CAN_F18R2_FB30_Msk /*!< Filter bit 30 */ |
10962 | #define CAN_F18R2_FB31_Pos (31U) |
| 10963 | #define CAN_F18R2_FB31_Pos (31U) |
10963 | #define CAN_F18R2_FB31_Msk (0x1UL << CAN_F18R2_FB31_Pos) /*!< 0x80000000 */ |
| 10964 | #define CAN_F18R2_FB31_Msk (0x1UL << CAN_F18R2_FB31_Pos) /*!< 0x80000000 */ |
10964 | #define CAN_F18R2_FB31 CAN_F18R2_FB31_Msk /*!< Filter bit 31 */ |
| 10965 | #define CAN_F18R2_FB31 CAN_F18R2_FB31_Msk /*!< Filter bit 31 */ |
10965 | |
| 10966 | 10966 | /******************* Bit definition for CAN_F19R2 register ******************/ |
|
| 10967 | /******************* Bit definition for CAN_F19R2 register ******************/ |
10967 | #define CAN_F19R2_FB0_Pos (0U) |
| 10968 | #define CAN_F19R2_FB0_Pos (0U) |
10968 | #define CAN_F19R2_FB0_Msk (0x1UL << CAN_F19R2_FB0_Pos) /*!< 0x00000001 */ |
| 10969 | #define CAN_F19R2_FB0_Msk (0x1UL << CAN_F19R2_FB0_Pos) /*!< 0x00000001 */ |
10969 | #define CAN_F19R2_FB0 CAN_F19R2_FB0_Msk /*!< Filter bit 0 */ |
| 10970 | #define CAN_F19R2_FB0 CAN_F19R2_FB0_Msk /*!< Filter bit 0 */ |
10970 | #define CAN_F19R2_FB1_Pos (1U) |
| 10971 | #define CAN_F19R2_FB1_Pos (1U) |
10971 | #define CAN_F19R2_FB1_Msk (0x1UL << CAN_F19R2_FB1_Pos) /*!< 0x00000002 */ |
| 10972 | #define CAN_F19R2_FB1_Msk (0x1UL << CAN_F19R2_FB1_Pos) /*!< 0x00000002 */ |
10972 | #define CAN_F19R2_FB1 CAN_F19R2_FB1_Msk /*!< Filter bit 1 */ |
| 10973 | #define CAN_F19R2_FB1 CAN_F19R2_FB1_Msk /*!< Filter bit 1 */ |
10973 | #define CAN_F19R2_FB2_Pos (2U) |
| 10974 | #define CAN_F19R2_FB2_Pos (2U) |
10974 | #define CAN_F19R2_FB2_Msk (0x1UL << CAN_F19R2_FB2_Pos) /*!< 0x00000004 */ |
| 10975 | #define CAN_F19R2_FB2_Msk (0x1UL << CAN_F19R2_FB2_Pos) /*!< 0x00000004 */ |
10975 | #define CAN_F19R2_FB2 CAN_F19R2_FB2_Msk /*!< Filter bit 2 */ |
| 10976 | #define CAN_F19R2_FB2 CAN_F19R2_FB2_Msk /*!< Filter bit 2 */ |
10976 | #define CAN_F19R2_FB3_Pos (3U) |
| 10977 | #define CAN_F19R2_FB3_Pos (3U) |
10977 | #define CAN_F19R2_FB3_Msk (0x1UL << CAN_F19R2_FB3_Pos) /*!< 0x00000008 */ |
| 10978 | #define CAN_F19R2_FB3_Msk (0x1UL << CAN_F19R2_FB3_Pos) /*!< 0x00000008 */ |
10978 | #define CAN_F19R2_FB3 CAN_F19R2_FB3_Msk /*!< Filter bit 3 */ |
| 10979 | #define CAN_F19R2_FB3 CAN_F19R2_FB3_Msk /*!< Filter bit 3 */ |
10979 | #define CAN_F19R2_FB4_Pos (4U) |
| 10980 | #define CAN_F19R2_FB4_Pos (4U) |
10980 | #define CAN_F19R2_FB4_Msk (0x1UL << CAN_F19R2_FB4_Pos) /*!< 0x00000010 */ |
| 10981 | #define CAN_F19R2_FB4_Msk (0x1UL << CAN_F19R2_FB4_Pos) /*!< 0x00000010 */ |
10981 | #define CAN_F19R2_FB4 CAN_F19R2_FB4_Msk /*!< Filter bit 4 */ |
| 10982 | #define CAN_F19R2_FB4 CAN_F19R2_FB4_Msk /*!< Filter bit 4 */ |
10982 | #define CAN_F19R2_FB5_Pos (5U) |
| 10983 | #define CAN_F19R2_FB5_Pos (5U) |
10983 | #define CAN_F19R2_FB5_Msk (0x1UL << CAN_F19R2_FB5_Pos) /*!< 0x00000020 */ |
| 10984 | #define CAN_F19R2_FB5_Msk (0x1UL << CAN_F19R2_FB5_Pos) /*!< 0x00000020 */ |
10984 | #define CAN_F19R2_FB5 CAN_F19R2_FB5_Msk /*!< Filter bit 5 */ |
| 10985 | #define CAN_F19R2_FB5 CAN_F19R2_FB5_Msk /*!< Filter bit 5 */ |
10985 | #define CAN_F19R2_FB6_Pos (6U) |
| 10986 | #define CAN_F19R2_FB6_Pos (6U) |
10986 | #define CAN_F19R2_FB6_Msk (0x1UL << CAN_F19R2_FB6_Pos) /*!< 0x00000040 */ |
| 10987 | #define CAN_F19R2_FB6_Msk (0x1UL << CAN_F19R2_FB6_Pos) /*!< 0x00000040 */ |
10987 | #define CAN_F19R2_FB6 CAN_F19R2_FB6_Msk /*!< Filter bit 6 */ |
| 10988 | #define CAN_F19R2_FB6 CAN_F19R2_FB6_Msk /*!< Filter bit 6 */ |
10988 | #define CAN_F19R2_FB7_Pos (7U) |
| 10989 | #define CAN_F19R2_FB7_Pos (7U) |
10989 | #define CAN_F19R2_FB7_Msk (0x1UL << CAN_F19R2_FB7_Pos) /*!< 0x00000080 */ |
| 10990 | #define CAN_F19R2_FB7_Msk (0x1UL << CAN_F19R2_FB7_Pos) /*!< 0x00000080 */ |
10990 | #define CAN_F19R2_FB7 CAN_F19R2_FB7_Msk /*!< Filter bit 7 */ |
| 10991 | #define CAN_F19R2_FB7 CAN_F19R2_FB7_Msk /*!< Filter bit 7 */ |
10991 | #define CAN_F19R2_FB8_Pos (8U) |
| 10992 | #define CAN_F19R2_FB8_Pos (8U) |
10992 | #define CAN_F19R2_FB8_Msk (0x1UL << CAN_F19R2_FB8_Pos) /*!< 0x00000100 */ |
| 10993 | #define CAN_F19R2_FB8_Msk (0x1UL << CAN_F19R2_FB8_Pos) /*!< 0x00000100 */ |
10993 | #define CAN_F19R2_FB8 CAN_F19R2_FB8_Msk /*!< Filter bit 8 */ |
| 10994 | #define CAN_F19R2_FB8 CAN_F19R2_FB8_Msk /*!< Filter bit 8 */ |
10994 | #define CAN_F19R2_FB9_Pos (9U) |
| 10995 | #define CAN_F19R2_FB9_Pos (9U) |
10995 | #define CAN_F19R2_FB9_Msk (0x1UL << CAN_F19R2_FB9_Pos) /*!< 0x00000200 */ |
| 10996 | #define CAN_F19R2_FB9_Msk (0x1UL << CAN_F19R2_FB9_Pos) /*!< 0x00000200 */ |
10996 | #define CAN_F19R2_FB9 CAN_F19R2_FB9_Msk /*!< Filter bit 9 */ |
| 10997 | #define CAN_F19R2_FB9 CAN_F19R2_FB9_Msk /*!< Filter bit 9 */ |
10997 | #define CAN_F19R2_FB10_Pos (10U) |
| 10998 | #define CAN_F19R2_FB10_Pos (10U) |
10998 | #define CAN_F19R2_FB10_Msk (0x1UL << CAN_F19R2_FB10_Pos) /*!< 0x00000400 */ |
| 10999 | #define CAN_F19R2_FB10_Msk (0x1UL << CAN_F19R2_FB10_Pos) /*!< 0x00000400 */ |
10999 | #define CAN_F19R2_FB10 CAN_F19R2_FB10_Msk /*!< Filter bit 10 */ |
| 11000 | #define CAN_F19R2_FB10 CAN_F19R2_FB10_Msk /*!< Filter bit 10 */ |
11000 | #define CAN_F19R2_FB11_Pos (11U) |
| 11001 | #define CAN_F19R2_FB11_Pos (11U) |
11001 | #define CAN_F19R2_FB11_Msk (0x1UL << CAN_F19R2_FB11_Pos) /*!< 0x00000800 */ |
| 11002 | #define CAN_F19R2_FB11_Msk (0x1UL << CAN_F19R2_FB11_Pos) /*!< 0x00000800 */ |
11002 | #define CAN_F19R2_FB11 CAN_F19R2_FB11_Msk /*!< Filter bit 11 */ |
| 11003 | #define CAN_F19R2_FB11 CAN_F19R2_FB11_Msk /*!< Filter bit 11 */ |
11003 | #define CAN_F19R2_FB12_Pos (12U) |
| 11004 | #define CAN_F19R2_FB12_Pos (12U) |
11004 | #define CAN_F19R2_FB12_Msk (0x1UL << CAN_F19R2_FB12_Pos) /*!< 0x00001000 */ |
| 11005 | #define CAN_F19R2_FB12_Msk (0x1UL << CAN_F19R2_FB12_Pos) /*!< 0x00001000 */ |
11005 | #define CAN_F19R2_FB12 CAN_F19R2_FB12_Msk /*!< Filter bit 12 */ |
| 11006 | #define CAN_F19R2_FB12 CAN_F19R2_FB12_Msk /*!< Filter bit 12 */ |
11006 | #define CAN_F19R2_FB13_Pos (13U) |
| 11007 | #define CAN_F19R2_FB13_Pos (13U) |
11007 | #define CAN_F19R2_FB13_Msk (0x1UL << CAN_F19R2_FB13_Pos) /*!< 0x00002000 */ |
| 11008 | #define CAN_F19R2_FB13_Msk (0x1UL << CAN_F19R2_FB13_Pos) /*!< 0x00002000 */ |
11008 | #define CAN_F19R2_FB13 CAN_F19R2_FB13_Msk /*!< Filter bit 13 */ |
| 11009 | #define CAN_F19R2_FB13 CAN_F19R2_FB13_Msk /*!< Filter bit 13 */ |
11009 | #define CAN_F19R2_FB14_Pos (14U) |
| 11010 | #define CAN_F19R2_FB14_Pos (14U) |
11010 | #define CAN_F19R2_FB14_Msk (0x1UL << CAN_F19R2_FB14_Pos) /*!< 0x00004000 */ |
| 11011 | #define CAN_F19R2_FB14_Msk (0x1UL << CAN_F19R2_FB14_Pos) /*!< 0x00004000 */ |
11011 | #define CAN_F19R2_FB14 CAN_F19R2_FB14_Msk /*!< Filter bit 14 */ |
| 11012 | #define CAN_F19R2_FB14 CAN_F19R2_FB14_Msk /*!< Filter bit 14 */ |
11012 | #define CAN_F19R2_FB15_Pos (15U) |
| 11013 | #define CAN_F19R2_FB15_Pos (15U) |
11013 | #define CAN_F19R2_FB15_Msk (0x1UL << CAN_F19R2_FB15_Pos) /*!< 0x00008000 */ |
| 11014 | #define CAN_F19R2_FB15_Msk (0x1UL << CAN_F19R2_FB15_Pos) /*!< 0x00008000 */ |
11014 | #define CAN_F19R2_FB15 CAN_F19R2_FB15_Msk /*!< Filter bit 15 */ |
| 11015 | #define CAN_F19R2_FB15 CAN_F19R2_FB15_Msk /*!< Filter bit 15 */ |
11015 | #define CAN_F19R2_FB16_Pos (16U) |
| 11016 | #define CAN_F19R2_FB16_Pos (16U) |
11016 | #define CAN_F19R2_FB16_Msk (0x1UL << CAN_F19R2_FB16_Pos) /*!< 0x00010000 */ |
| 11017 | #define CAN_F19R2_FB16_Msk (0x1UL << CAN_F19R2_FB16_Pos) /*!< 0x00010000 */ |
11017 | #define CAN_F19R2_FB16 CAN_F19R2_FB16_Msk /*!< Filter bit 16 */ |
| 11018 | #define CAN_F19R2_FB16 CAN_F19R2_FB16_Msk /*!< Filter bit 16 */ |
11018 | #define CAN_F19R2_FB17_Pos (17U) |
| 11019 | #define CAN_F19R2_FB17_Pos (17U) |
11019 | #define CAN_F19R2_FB17_Msk (0x1UL << CAN_F19R2_FB17_Pos) /*!< 0x00020000 */ |
| 11020 | #define CAN_F19R2_FB17_Msk (0x1UL << CAN_F19R2_FB17_Pos) /*!< 0x00020000 */ |
11020 | #define CAN_F19R2_FB17 CAN_F19R2_FB17_Msk /*!< Filter bit 17 */ |
| 11021 | #define CAN_F19R2_FB17 CAN_F19R2_FB17_Msk /*!< Filter bit 17 */ |
11021 | #define CAN_F19R2_FB18_Pos (18U) |
| 11022 | #define CAN_F19R2_FB18_Pos (18U) |
11022 | #define CAN_F19R2_FB18_Msk (0x1UL << CAN_F19R2_FB18_Pos) /*!< 0x00040000 */ |
| 11023 | #define CAN_F19R2_FB18_Msk (0x1UL << CAN_F19R2_FB18_Pos) /*!< 0x00040000 */ |
11023 | #define CAN_F19R2_FB18 CAN_F19R2_FB18_Msk /*!< Filter bit 18 */ |
| 11024 | #define CAN_F19R2_FB18 CAN_F19R2_FB18_Msk /*!< Filter bit 18 */ |
11024 | #define CAN_F19R2_FB19_Pos (19U) |
| 11025 | #define CAN_F19R2_FB19_Pos (19U) |
11025 | #define CAN_F19R2_FB19_Msk (0x1UL << CAN_F19R2_FB19_Pos) /*!< 0x00080000 */ |
| 11026 | #define CAN_F19R2_FB19_Msk (0x1UL << CAN_F19R2_FB19_Pos) /*!< 0x00080000 */ |
11026 | #define CAN_F19R2_FB19 CAN_F19R2_FB19_Msk /*!< Filter bit 19 */ |
| 11027 | #define CAN_F19R2_FB19 CAN_F19R2_FB19_Msk /*!< Filter bit 19 */ |
11027 | #define CAN_F19R2_FB20_Pos (20U) |
| 11028 | #define CAN_F19R2_FB20_Pos (20U) |
11028 | #define CAN_F19R2_FB20_Msk (0x1UL << CAN_F19R2_FB20_Pos) /*!< 0x00100000 */ |
| 11029 | #define CAN_F19R2_FB20_Msk (0x1UL << CAN_F19R2_FB20_Pos) /*!< 0x00100000 */ |
11029 | #define CAN_F19R2_FB20 CAN_F19R2_FB20_Msk /*!< Filter bit 20 */ |
| 11030 | #define CAN_F19R2_FB20 CAN_F19R2_FB20_Msk /*!< Filter bit 20 */ |
11030 | #define CAN_F19R2_FB21_Pos (21U) |
| 11031 | #define CAN_F19R2_FB21_Pos (21U) |
11031 | #define CAN_F19R2_FB21_Msk (0x1UL << CAN_F19R2_FB21_Pos) /*!< 0x00200000 */ |
| 11032 | #define CAN_F19R2_FB21_Msk (0x1UL << CAN_F19R2_FB21_Pos) /*!< 0x00200000 */ |
11032 | #define CAN_F19R2_FB21 CAN_F19R2_FB21_Msk /*!< Filter bit 21 */ |
| 11033 | #define CAN_F19R2_FB21 CAN_F19R2_FB21_Msk /*!< Filter bit 21 */ |
11033 | #define CAN_F19R2_FB22_Pos (22U) |
| 11034 | #define CAN_F19R2_FB22_Pos (22U) |
11034 | #define CAN_F19R2_FB22_Msk (0x1UL << CAN_F19R2_FB22_Pos) /*!< 0x00400000 */ |
| 11035 | #define CAN_F19R2_FB22_Msk (0x1UL << CAN_F19R2_FB22_Pos) /*!< 0x00400000 */ |
11035 | #define CAN_F19R2_FB22 CAN_F19R2_FB22_Msk /*!< Filter bit 22 */ |
| 11036 | #define CAN_F19R2_FB22 CAN_F19R2_FB22_Msk /*!< Filter bit 22 */ |
11036 | #define CAN_F19R2_FB23_Pos (23U) |
| 11037 | #define CAN_F19R2_FB23_Pos (23U) |
11037 | #define CAN_F19R2_FB23_Msk (0x1UL << CAN_F19R2_FB23_Pos) /*!< 0x00800000 */ |
| 11038 | #define CAN_F19R2_FB23_Msk (0x1UL << CAN_F19R2_FB23_Pos) /*!< 0x00800000 */ |
11038 | #define CAN_F19R2_FB23 CAN_F19R2_FB23_Msk /*!< Filter bit 23 */ |
| 11039 | #define CAN_F19R2_FB23 CAN_F19R2_FB23_Msk /*!< Filter bit 23 */ |
11039 | #define CAN_F19R2_FB24_Pos (24U) |
| 11040 | #define CAN_F19R2_FB24_Pos (24U) |
11040 | #define CAN_F19R2_FB24_Msk (0x1UL << CAN_F19R2_FB24_Pos) /*!< 0x01000000 */ |
| 11041 | #define CAN_F19R2_FB24_Msk (0x1UL << CAN_F19R2_FB24_Pos) /*!< 0x01000000 */ |
11041 | #define CAN_F19R2_FB24 CAN_F19R2_FB24_Msk /*!< Filter bit 24 */ |
| 11042 | #define CAN_F19R2_FB24 CAN_F19R2_FB24_Msk /*!< Filter bit 24 */ |
11042 | #define CAN_F19R2_FB25_Pos (25U) |
| 11043 | #define CAN_F19R2_FB25_Pos (25U) |
11043 | #define CAN_F19R2_FB25_Msk (0x1UL << CAN_F19R2_FB25_Pos) /*!< 0x02000000 */ |
| 11044 | #define CAN_F19R2_FB25_Msk (0x1UL << CAN_F19R2_FB25_Pos) /*!< 0x02000000 */ |
11044 | #define CAN_F19R2_FB25 CAN_F19R2_FB25_Msk /*!< Filter bit 25 */ |
| 11045 | #define CAN_F19R2_FB25 CAN_F19R2_FB25_Msk /*!< Filter bit 25 */ |
11045 | #define CAN_F19R2_FB26_Pos (26U) |
| 11046 | #define CAN_F19R2_FB26_Pos (26U) |
11046 | #define CAN_F19R2_FB26_Msk (0x1UL << CAN_F19R2_FB26_Pos) /*!< 0x04000000 */ |
| 11047 | #define CAN_F19R2_FB26_Msk (0x1UL << CAN_F19R2_FB26_Pos) /*!< 0x04000000 */ |
11047 | #define CAN_F19R2_FB26 CAN_F19R2_FB26_Msk /*!< Filter bit 26 */ |
| 11048 | #define CAN_F19R2_FB26 CAN_F19R2_FB26_Msk /*!< Filter bit 26 */ |
11048 | #define CAN_F19R2_FB27_Pos (27U) |
| 11049 | #define CAN_F19R2_FB27_Pos (27U) |
11049 | #define CAN_F19R2_FB27_Msk (0x1UL << CAN_F19R2_FB27_Pos) /*!< 0x08000000 */ |
| 11050 | #define CAN_F19R2_FB27_Msk (0x1UL << CAN_F19R2_FB27_Pos) /*!< 0x08000000 */ |
11050 | #define CAN_F19R2_FB27 CAN_F19R2_FB27_Msk /*!< Filter bit 27 */ |
| 11051 | #define CAN_F19R2_FB27 CAN_F19R2_FB27_Msk /*!< Filter bit 27 */ |
11051 | #define CAN_F19R2_FB28_Pos (28U) |
| 11052 | #define CAN_F19R2_FB28_Pos (28U) |
11052 | #define CAN_F19R2_FB28_Msk (0x1UL << CAN_F19R2_FB28_Pos) /*!< 0x10000000 */ |
| 11053 | #define CAN_F19R2_FB28_Msk (0x1UL << CAN_F19R2_FB28_Pos) /*!< 0x10000000 */ |
11053 | #define CAN_F19R2_FB28 CAN_F19R2_FB28_Msk /*!< Filter bit 28 */ |
| 11054 | #define CAN_F19R2_FB28 CAN_F19R2_FB28_Msk /*!< Filter bit 28 */ |
11054 | #define CAN_F19R2_FB29_Pos (29U) |
| 11055 | #define CAN_F19R2_FB29_Pos (29U) |
11055 | #define CAN_F19R2_FB29_Msk (0x1UL << CAN_F19R2_FB29_Pos) /*!< 0x20000000 */ |
| 11056 | #define CAN_F19R2_FB29_Msk (0x1UL << CAN_F19R2_FB29_Pos) /*!< 0x20000000 */ |
11056 | #define CAN_F19R2_FB29 CAN_F19R2_FB29_Msk /*!< Filter bit 29 */ |
| 11057 | #define CAN_F19R2_FB29 CAN_F19R2_FB29_Msk /*!< Filter bit 29 */ |
11057 | #define CAN_F19R2_FB30_Pos (30U) |
| 11058 | #define CAN_F19R2_FB30_Pos (30U) |
11058 | #define CAN_F19R2_FB30_Msk (0x1UL << CAN_F19R2_FB30_Pos) /*!< 0x40000000 */ |
| 11059 | #define CAN_F19R2_FB30_Msk (0x1UL << CAN_F19R2_FB30_Pos) /*!< 0x40000000 */ |
11059 | #define CAN_F19R2_FB30 CAN_F19R2_FB30_Msk /*!< Filter bit 30 */ |
| 11060 | #define CAN_F19R2_FB30 CAN_F19R2_FB30_Msk /*!< Filter bit 30 */ |
11060 | #define CAN_F19R2_FB31_Pos (31U) |
| 11061 | #define CAN_F19R2_FB31_Pos (31U) |
11061 | #define CAN_F19R2_FB31_Msk (0x1UL << CAN_F19R2_FB31_Pos) /*!< 0x80000000 */ |
| 11062 | #define CAN_F19R2_FB31_Msk (0x1UL << CAN_F19R2_FB31_Pos) /*!< 0x80000000 */ |
11062 | #define CAN_F19R2_FB31 CAN_F19R2_FB31_Msk /*!< Filter bit 31 */ |
| 11063 | #define CAN_F19R2_FB31 CAN_F19R2_FB31_Msk /*!< Filter bit 31 */ |
11063 | |
| 11064 | 11064 | /******************* Bit definition for CAN_F20R2 register ******************/ |
|
| 11065 | /******************* Bit definition for CAN_F20R2 register ******************/ |
11065 | #define CAN_F20R2_FB0_Pos (0U) |
| 11066 | #define CAN_F20R2_FB0_Pos (0U) |
11066 | #define CAN_F20R2_FB0_Msk (0x1UL << CAN_F20R2_FB0_Pos) /*!< 0x00000001 */ |
| 11067 | #define CAN_F20R2_FB0_Msk (0x1UL << CAN_F20R2_FB0_Pos) /*!< 0x00000001 */ |
11067 | #define CAN_F20R2_FB0 CAN_F20R2_FB0_Msk /*!< Filter bit 0 */ |
| 11068 | #define CAN_F20R2_FB0 CAN_F20R2_FB0_Msk /*!< Filter bit 0 */ |
11068 | #define CAN_F20R2_FB1_Pos (1U) |
| 11069 | #define CAN_F20R2_FB1_Pos (1U) |
11069 | #define CAN_F20R2_FB1_Msk (0x1UL << CAN_F20R2_FB1_Pos) /*!< 0x00000002 */ |
| 11070 | #define CAN_F20R2_FB1_Msk (0x1UL << CAN_F20R2_FB1_Pos) /*!< 0x00000002 */ |
11070 | #define CAN_F20R2_FB1 CAN_F20R2_FB1_Msk /*!< Filter bit 1 */ |
| 11071 | #define CAN_F20R2_FB1 CAN_F20R2_FB1_Msk /*!< Filter bit 1 */ |
11071 | #define CAN_F20R2_FB2_Pos (2U) |
| 11072 | #define CAN_F20R2_FB2_Pos (2U) |
11072 | #define CAN_F20R2_FB2_Msk (0x1UL << CAN_F20R2_FB2_Pos) /*!< 0x00000004 */ |
| 11073 | #define CAN_F20R2_FB2_Msk (0x1UL << CAN_F20R2_FB2_Pos) /*!< 0x00000004 */ |
11073 | #define CAN_F20R2_FB2 CAN_F20R2_FB2_Msk /*!< Filter bit 2 */ |
| 11074 | #define CAN_F20R2_FB2 CAN_F20R2_FB2_Msk /*!< Filter bit 2 */ |
11074 | #define CAN_F20R2_FB3_Pos (3U) |
| 11075 | #define CAN_F20R2_FB3_Pos (3U) |
11075 | #define CAN_F20R2_FB3_Msk (0x1UL << CAN_F20R2_FB3_Pos) /*!< 0x00000008 */ |
| 11076 | #define CAN_F20R2_FB3_Msk (0x1UL << CAN_F20R2_FB3_Pos) /*!< 0x00000008 */ |
11076 | #define CAN_F20R2_FB3 CAN_F20R2_FB3_Msk /*!< Filter bit 3 */ |
| 11077 | #define CAN_F20R2_FB3 CAN_F20R2_FB3_Msk /*!< Filter bit 3 */ |
11077 | #define CAN_F20R2_FB4_Pos (4U) |
| 11078 | #define CAN_F20R2_FB4_Pos (4U) |
11078 | #define CAN_F20R2_FB4_Msk (0x1UL << CAN_F20R2_FB4_Pos) /*!< 0x00000010 */ |
| 11079 | #define CAN_F20R2_FB4_Msk (0x1UL << CAN_F20R2_FB4_Pos) /*!< 0x00000010 */ |
11079 | #define CAN_F20R2_FB4 CAN_F20R2_FB4_Msk /*!< Filter bit 4 */ |
| 11080 | #define CAN_F20R2_FB4 CAN_F20R2_FB4_Msk /*!< Filter bit 4 */ |
11080 | #define CAN_F20R2_FB5_Pos (5U) |
| 11081 | #define CAN_F20R2_FB5_Pos (5U) |
11081 | #define CAN_F20R2_FB5_Msk (0x1UL << CAN_F20R2_FB5_Pos) /*!< 0x00000020 */ |
| 11082 | #define CAN_F20R2_FB5_Msk (0x1UL << CAN_F20R2_FB5_Pos) /*!< 0x00000020 */ |
11082 | #define CAN_F20R2_FB5 CAN_F20R2_FB5_Msk /*!< Filter bit 5 */ |
| 11083 | #define CAN_F20R2_FB5 CAN_F20R2_FB5_Msk /*!< Filter bit 5 */ |
11083 | #define CAN_F20R2_FB6_Pos (6U) |
| 11084 | #define CAN_F20R2_FB6_Pos (6U) |
11084 | #define CAN_F20R2_FB6_Msk (0x1UL << CAN_F20R2_FB6_Pos) /*!< 0x00000040 */ |
| 11085 | #define CAN_F20R2_FB6_Msk (0x1UL << CAN_F20R2_FB6_Pos) /*!< 0x00000040 */ |
11085 | #define CAN_F20R2_FB6 CAN_F20R2_FB6_Msk /*!< Filter bit 6 */ |
| 11086 | #define CAN_F20R2_FB6 CAN_F20R2_FB6_Msk /*!< Filter bit 6 */ |
11086 | #define CAN_F20R2_FB7_Pos (7U) |
| 11087 | #define CAN_F20R2_FB7_Pos (7U) |
11087 | #define CAN_F20R2_FB7_Msk (0x1UL << CAN_F20R2_FB7_Pos) /*!< 0x00000080 */ |
| 11088 | #define CAN_F20R2_FB7_Msk (0x1UL << CAN_F20R2_FB7_Pos) /*!< 0x00000080 */ |
11088 | #define CAN_F20R2_FB7 CAN_F20R2_FB7_Msk /*!< Filter bit 7 */ |
| 11089 | #define CAN_F20R2_FB7 CAN_F20R2_FB7_Msk /*!< Filter bit 7 */ |
11089 | #define CAN_F20R2_FB8_Pos (8U) |
| 11090 | #define CAN_F20R2_FB8_Pos (8U) |
11090 | #define CAN_F20R2_FB8_Msk (0x1UL << CAN_F20R2_FB8_Pos) /*!< 0x00000100 */ |
| 11091 | #define CAN_F20R2_FB8_Msk (0x1UL << CAN_F20R2_FB8_Pos) /*!< 0x00000100 */ |
11091 | #define CAN_F20R2_FB8 CAN_F20R2_FB8_Msk /*!< Filter bit 8 */ |
| 11092 | #define CAN_F20R2_FB8 CAN_F20R2_FB8_Msk /*!< Filter bit 8 */ |
11092 | #define CAN_F20R2_FB9_Pos (9U) |
| 11093 | #define CAN_F20R2_FB9_Pos (9U) |
11093 | #define CAN_F20R2_FB9_Msk (0x1UL << CAN_F20R2_FB9_Pos) /*!< 0x00000200 */ |
| 11094 | #define CAN_F20R2_FB9_Msk (0x1UL << CAN_F20R2_FB9_Pos) /*!< 0x00000200 */ |
11094 | #define CAN_F20R2_FB9 CAN_F20R2_FB9_Msk /*!< Filter bit 9 */ |
| 11095 | #define CAN_F20R2_FB9 CAN_F20R2_FB9_Msk /*!< Filter bit 9 */ |
11095 | #define CAN_F20R2_FB10_Pos (10U) |
| 11096 | #define CAN_F20R2_FB10_Pos (10U) |
11096 | #define CAN_F20R2_FB10_Msk (0x1UL << CAN_F20R2_FB10_Pos) /*!< 0x00000400 */ |
| 11097 | #define CAN_F20R2_FB10_Msk (0x1UL << CAN_F20R2_FB10_Pos) /*!< 0x00000400 */ |
11097 | #define CAN_F20R2_FB10 CAN_F20R2_FB10_Msk /*!< Filter bit 10 */ |
| 11098 | #define CAN_F20R2_FB10 CAN_F20R2_FB10_Msk /*!< Filter bit 10 */ |
11098 | #define CAN_F20R2_FB11_Pos (11U) |
| 11099 | #define CAN_F20R2_FB11_Pos (11U) |
11099 | #define CAN_F20R2_FB11_Msk (0x1UL << CAN_F20R2_FB11_Pos) /*!< 0x00000800 */ |
| 11100 | #define CAN_F20R2_FB11_Msk (0x1UL << CAN_F20R2_FB11_Pos) /*!< 0x00000800 */ |
11100 | #define CAN_F20R2_FB11 CAN_F20R2_FB11_Msk /*!< Filter bit 11 */ |
| 11101 | #define CAN_F20R2_FB11 CAN_F20R2_FB11_Msk /*!< Filter bit 11 */ |
11101 | #define CAN_F20R2_FB12_Pos (12U) |
| 11102 | #define CAN_F20R2_FB12_Pos (12U) |
11102 | #define CAN_F20R2_FB12_Msk (0x1UL << CAN_F20R2_FB12_Pos) /*!< 0x00001000 */ |
| 11103 | #define CAN_F20R2_FB12_Msk (0x1UL << CAN_F20R2_FB12_Pos) /*!< 0x00001000 */ |
11103 | #define CAN_F20R2_FB12 CAN_F20R2_FB12_Msk /*!< Filter bit 12 */ |
| 11104 | #define CAN_F20R2_FB12 CAN_F20R2_FB12_Msk /*!< Filter bit 12 */ |
11104 | #define CAN_F20R2_FB13_Pos (13U) |
| 11105 | #define CAN_F20R2_FB13_Pos (13U) |
11105 | #define CAN_F20R2_FB13_Msk (0x1UL << CAN_F20R2_FB13_Pos) /*!< 0x00002000 */ |
| 11106 | #define CAN_F20R2_FB13_Msk (0x1UL << CAN_F20R2_FB13_Pos) /*!< 0x00002000 */ |
11106 | #define CAN_F20R2_FB13 CAN_F20R2_FB13_Msk /*!< Filter bit 13 */ |
| 11107 | #define CAN_F20R2_FB13 CAN_F20R2_FB13_Msk /*!< Filter bit 13 */ |
11107 | #define CAN_F20R2_FB14_Pos (14U) |
| 11108 | #define CAN_F20R2_FB14_Pos (14U) |
11108 | #define CAN_F20R2_FB14_Msk (0x1UL << CAN_F20R2_FB14_Pos) /*!< 0x00004000 */ |
| 11109 | #define CAN_F20R2_FB14_Msk (0x1UL << CAN_F20R2_FB14_Pos) /*!< 0x00004000 */ |
11109 | #define CAN_F20R2_FB14 CAN_F20R2_FB14_Msk /*!< Filter bit 14 */ |
| 11110 | #define CAN_F20R2_FB14 CAN_F20R2_FB14_Msk /*!< Filter bit 14 */ |
11110 | #define CAN_F20R2_FB15_Pos (15U) |
| 11111 | #define CAN_F20R2_FB15_Pos (15U) |
11111 | #define CAN_F20R2_FB15_Msk (0x1UL << CAN_F20R2_FB15_Pos) /*!< 0x00008000 */ |
| 11112 | #define CAN_F20R2_FB15_Msk (0x1UL << CAN_F20R2_FB15_Pos) /*!< 0x00008000 */ |
11112 | #define CAN_F20R2_FB15 CAN_F20R2_FB15_Msk /*!< Filter bit 15 */ |
| 11113 | #define CAN_F20R2_FB15 CAN_F20R2_FB15_Msk /*!< Filter bit 15 */ |
11113 | #define CAN_F20R2_FB16_Pos (16U) |
| 11114 | #define CAN_F20R2_FB16_Pos (16U) |
11114 | #define CAN_F20R2_FB16_Msk (0x1UL << CAN_F20R2_FB16_Pos) /*!< 0x00010000 */ |
| 11115 | #define CAN_F20R2_FB16_Msk (0x1UL << CAN_F20R2_FB16_Pos) /*!< 0x00010000 */ |
11115 | #define CAN_F20R2_FB16 CAN_F20R2_FB16_Msk /*!< Filter bit 16 */ |
| 11116 | #define CAN_F20R2_FB16 CAN_F20R2_FB16_Msk /*!< Filter bit 16 */ |
11116 | #define CAN_F20R2_FB17_Pos (17U) |
| 11117 | #define CAN_F20R2_FB17_Pos (17U) |
11117 | #define CAN_F20R2_FB17_Msk (0x1UL << CAN_F20R2_FB17_Pos) /*!< 0x00020000 */ |
| 11118 | #define CAN_F20R2_FB17_Msk (0x1UL << CAN_F20R2_FB17_Pos) /*!< 0x00020000 */ |
11118 | #define CAN_F20R2_FB17 CAN_F20R2_FB17_Msk /*!< Filter bit 17 */ |
| 11119 | #define CAN_F20R2_FB17 CAN_F20R2_FB17_Msk /*!< Filter bit 17 */ |
11119 | #define CAN_F20R2_FB18_Pos (18U) |
| 11120 | #define CAN_F20R2_FB18_Pos (18U) |
11120 | #define CAN_F20R2_FB18_Msk (0x1UL << CAN_F20R2_FB18_Pos) /*!< 0x00040000 */ |
| 11121 | #define CAN_F20R2_FB18_Msk (0x1UL << CAN_F20R2_FB18_Pos) /*!< 0x00040000 */ |
11121 | #define CAN_F20R2_FB18 CAN_F20R2_FB18_Msk /*!< Filter bit 18 */ |
| 11122 | #define CAN_F20R2_FB18 CAN_F20R2_FB18_Msk /*!< Filter bit 18 */ |
11122 | #define CAN_F20R2_FB19_Pos (19U) |
| 11123 | #define CAN_F20R2_FB19_Pos (19U) |
11123 | #define CAN_F20R2_FB19_Msk (0x1UL << CAN_F20R2_FB19_Pos) /*!< 0x00080000 */ |
| 11124 | #define CAN_F20R2_FB19_Msk (0x1UL << CAN_F20R2_FB19_Pos) /*!< 0x00080000 */ |
11124 | #define CAN_F20R2_FB19 CAN_F20R2_FB19_Msk /*!< Filter bit 19 */ |
| 11125 | #define CAN_F20R2_FB19 CAN_F20R2_FB19_Msk /*!< Filter bit 19 */ |
11125 | #define CAN_F20R2_FB20_Pos (20U) |
| 11126 | #define CAN_F20R2_FB20_Pos (20U) |
11126 | #define CAN_F20R2_FB20_Msk (0x1UL << CAN_F20R2_FB20_Pos) /*!< 0x00100000 */ |
| 11127 | #define CAN_F20R2_FB20_Msk (0x1UL << CAN_F20R2_FB20_Pos) /*!< 0x00100000 */ |
11127 | #define CAN_F20R2_FB20 CAN_F20R2_FB20_Msk /*!< Filter bit 20 */ |
| 11128 | #define CAN_F20R2_FB20 CAN_F20R2_FB20_Msk /*!< Filter bit 20 */ |
11128 | #define CAN_F20R2_FB21_Pos (21U) |
| 11129 | #define CAN_F20R2_FB21_Pos (21U) |
11129 | #define CAN_F20R2_FB21_Msk (0x1UL << CAN_F20R2_FB21_Pos) /*!< 0x00200000 */ |
| 11130 | #define CAN_F20R2_FB21_Msk (0x1UL << CAN_F20R2_FB21_Pos) /*!< 0x00200000 */ |
11130 | #define CAN_F20R2_FB21 CAN_F20R2_FB21_Msk /*!< Filter bit 21 */ |
| 11131 | #define CAN_F20R2_FB21 CAN_F20R2_FB21_Msk /*!< Filter bit 21 */ |
11131 | #define CAN_F20R2_FB22_Pos (22U) |
| 11132 | #define CAN_F20R2_FB22_Pos (22U) |
11132 | #define CAN_F20R2_FB22_Msk (0x1UL << CAN_F20R2_FB22_Pos) /*!< 0x00400000 */ |
| 11133 | #define CAN_F20R2_FB22_Msk (0x1UL << CAN_F20R2_FB22_Pos) /*!< 0x00400000 */ |
11133 | #define CAN_F20R2_FB22 CAN_F20R2_FB22_Msk /*!< Filter bit 22 */ |
| 11134 | #define CAN_F20R2_FB22 CAN_F20R2_FB22_Msk /*!< Filter bit 22 */ |
11134 | #define CAN_F20R2_FB23_Pos (23U) |
| 11135 | #define CAN_F20R2_FB23_Pos (23U) |
11135 | #define CAN_F20R2_FB23_Msk (0x1UL << CAN_F20R2_FB23_Pos) /*!< 0x00800000 */ |
| 11136 | #define CAN_F20R2_FB23_Msk (0x1UL << CAN_F20R2_FB23_Pos) /*!< 0x00800000 */ |
11136 | #define CAN_F20R2_FB23 CAN_F20R2_FB23_Msk /*!< Filter bit 23 */ |
| 11137 | #define CAN_F20R2_FB23 CAN_F20R2_FB23_Msk /*!< Filter bit 23 */ |
11137 | #define CAN_F20R2_FB24_Pos (24U) |
| 11138 | #define CAN_F20R2_FB24_Pos (24U) |
11138 | #define CAN_F20R2_FB24_Msk (0x1UL << CAN_F20R2_FB24_Pos) /*!< 0x01000000 */ |
| 11139 | #define CAN_F20R2_FB24_Msk (0x1UL << CAN_F20R2_FB24_Pos) /*!< 0x01000000 */ |
11139 | #define CAN_F20R2_FB24 CAN_F20R2_FB24_Msk /*!< Filter bit 24 */ |
| 11140 | #define CAN_F20R2_FB24 CAN_F20R2_FB24_Msk /*!< Filter bit 24 */ |
11140 | #define CAN_F20R2_FB25_Pos (25U) |
| 11141 | #define CAN_F20R2_FB25_Pos (25U) |
11141 | #define CAN_F20R2_FB25_Msk (0x1UL << CAN_F20R2_FB25_Pos) /*!< 0x02000000 */ |
| 11142 | #define CAN_F20R2_FB25_Msk (0x1UL << CAN_F20R2_FB25_Pos) /*!< 0x02000000 */ |
11142 | #define CAN_F20R2_FB25 CAN_F20R2_FB25_Msk /*!< Filter bit 25 */ |
| 11143 | #define CAN_F20R2_FB25 CAN_F20R2_FB25_Msk /*!< Filter bit 25 */ |
11143 | #define CAN_F20R2_FB26_Pos (26U) |
| 11144 | #define CAN_F20R2_FB26_Pos (26U) |
11144 | #define CAN_F20R2_FB26_Msk (0x1UL << CAN_F20R2_FB26_Pos) /*!< 0x04000000 */ |
| 11145 | #define CAN_F20R2_FB26_Msk (0x1UL << CAN_F20R2_FB26_Pos) /*!< 0x04000000 */ |
11145 | #define CAN_F20R2_FB26 CAN_F20R2_FB26_Msk /*!< Filter bit 26 */ |
| 11146 | #define CAN_F20R2_FB26 CAN_F20R2_FB26_Msk /*!< Filter bit 26 */ |
11146 | #define CAN_F20R2_FB27_Pos (27U) |
| 11147 | #define CAN_F20R2_FB27_Pos (27U) |
11147 | #define CAN_F20R2_FB27_Msk (0x1UL << CAN_F20R2_FB27_Pos) /*!< 0x08000000 */ |
| 11148 | #define CAN_F20R2_FB27_Msk (0x1UL << CAN_F20R2_FB27_Pos) /*!< 0x08000000 */ |
11148 | #define CAN_F20R2_FB27 CAN_F20R2_FB27_Msk /*!< Filter bit 27 */ |
| 11149 | #define CAN_F20R2_FB27 CAN_F20R2_FB27_Msk /*!< Filter bit 27 */ |
11149 | #define CAN_F20R2_FB28_Pos (28U) |
| 11150 | #define CAN_F20R2_FB28_Pos (28U) |
11150 | #define CAN_F20R2_FB28_Msk (0x1UL << CAN_F20R2_FB28_Pos) /*!< 0x10000000 */ |
| 11151 | #define CAN_F20R2_FB28_Msk (0x1UL << CAN_F20R2_FB28_Pos) /*!< 0x10000000 */ |
11151 | #define CAN_F20R2_FB28 CAN_F20R2_FB28_Msk /*!< Filter bit 28 */ |
| 11152 | #define CAN_F20R2_FB28 CAN_F20R2_FB28_Msk /*!< Filter bit 28 */ |
11152 | #define CAN_F20R2_FB29_Pos (29U) |
| 11153 | #define CAN_F20R2_FB29_Pos (29U) |
11153 | #define CAN_F20R2_FB29_Msk (0x1UL << CAN_F20R2_FB29_Pos) /*!< 0x20000000 */ |
| 11154 | #define CAN_F20R2_FB29_Msk (0x1UL << CAN_F20R2_FB29_Pos) /*!< 0x20000000 */ |
11154 | #define CAN_F20R2_FB29 CAN_F20R2_FB29_Msk /*!< Filter bit 29 */ |
| 11155 | #define CAN_F20R2_FB29 CAN_F20R2_FB29_Msk /*!< Filter bit 29 */ |
11155 | #define CAN_F20R2_FB30_Pos (30U) |
| 11156 | #define CAN_F20R2_FB30_Pos (30U) |
11156 | #define CAN_F20R2_FB30_Msk (0x1UL << CAN_F20R2_FB30_Pos) /*!< 0x40000000 */ |
| 11157 | #define CAN_F20R2_FB30_Msk (0x1UL << CAN_F20R2_FB30_Pos) /*!< 0x40000000 */ |
11157 | #define CAN_F20R2_FB30 CAN_F20R2_FB30_Msk /*!< Filter bit 30 */ |
| 11158 | #define CAN_F20R2_FB30 CAN_F20R2_FB30_Msk /*!< Filter bit 30 */ |
11158 | #define CAN_F20R2_FB31_Pos (31U) |
| 11159 | #define CAN_F20R2_FB31_Pos (31U) |
11159 | #define CAN_F20R2_FB31_Msk (0x1UL << CAN_F20R2_FB31_Pos) /*!< 0x80000000 */ |
| 11160 | #define CAN_F20R2_FB31_Msk (0x1UL << CAN_F20R2_FB31_Pos) /*!< 0x80000000 */ |
11160 | #define CAN_F20R2_FB31 CAN_F20R2_FB31_Msk /*!< Filter bit 31 */ |
| 11161 | #define CAN_F20R2_FB31 CAN_F20R2_FB31_Msk /*!< Filter bit 31 */ |
11161 | |
| 11162 | 11162 | /******************* Bit definition for CAN_F21R2 register ******************/ |
|
| 11163 | /******************* Bit definition for CAN_F21R2 register ******************/ |
11163 | #define CAN_F21R2_FB0_Pos (0U) |
| 11164 | #define CAN_F21R2_FB0_Pos (0U) |
11164 | #define CAN_F21R2_FB0_Msk (0x1UL << CAN_F21R2_FB0_Pos) /*!< 0x00000001 */ |
| 11165 | #define CAN_F21R2_FB0_Msk (0x1UL << CAN_F21R2_FB0_Pos) /*!< 0x00000001 */ |
11165 | #define CAN_F21R2_FB0 CAN_F21R2_FB0_Msk /*!< Filter bit 0 */ |
| 11166 | #define CAN_F21R2_FB0 CAN_F21R2_FB0_Msk /*!< Filter bit 0 */ |
11166 | #define CAN_F21R2_FB1_Pos (1U) |
| 11167 | #define CAN_F21R2_FB1_Pos (1U) |
11167 | #define CAN_F21R2_FB1_Msk (0x1UL << CAN_F21R2_FB1_Pos) /*!< 0x00000002 */ |
| 11168 | #define CAN_F21R2_FB1_Msk (0x1UL << CAN_F21R2_FB1_Pos) /*!< 0x00000002 */ |
11168 | #define CAN_F21R2_FB1 CAN_F21R2_FB1_Msk /*!< Filter bit 1 */ |
| 11169 | #define CAN_F21R2_FB1 CAN_F21R2_FB1_Msk /*!< Filter bit 1 */ |
11169 | #define CAN_F21R2_FB2_Pos (2U) |
| 11170 | #define CAN_F21R2_FB2_Pos (2U) |
11170 | #define CAN_F21R2_FB2_Msk (0x1UL << CAN_F21R2_FB2_Pos) /*!< 0x00000004 */ |
| 11171 | #define CAN_F21R2_FB2_Msk (0x1UL << CAN_F21R2_FB2_Pos) /*!< 0x00000004 */ |
11171 | #define CAN_F21R2_FB2 CAN_F21R2_FB2_Msk /*!< Filter bit 2 */ |
| 11172 | #define CAN_F21R2_FB2 CAN_F21R2_FB2_Msk /*!< Filter bit 2 */ |
11172 | #define CAN_F21R2_FB3_Pos (3U) |
| 11173 | #define CAN_F21R2_FB3_Pos (3U) |
11173 | #define CAN_F21R2_FB3_Msk (0x1UL << CAN_F21R2_FB3_Pos) /*!< 0x00000008 */ |
| 11174 | #define CAN_F21R2_FB3_Msk (0x1UL << CAN_F21R2_FB3_Pos) /*!< 0x00000008 */ |
11174 | #define CAN_F21R2_FB3 CAN_F21R2_FB3_Msk /*!< Filter bit 3 */ |
| 11175 | #define CAN_F21R2_FB3 CAN_F21R2_FB3_Msk /*!< Filter bit 3 */ |
11175 | #define CAN_F21R2_FB4_Pos (4U) |
| 11176 | #define CAN_F21R2_FB4_Pos (4U) |
11176 | #define CAN_F21R2_FB4_Msk (0x1UL << CAN_F21R2_FB4_Pos) /*!< 0x00000010 */ |
| 11177 | #define CAN_F21R2_FB4_Msk (0x1UL << CAN_F21R2_FB4_Pos) /*!< 0x00000010 */ |
11177 | #define CAN_F21R2_FB4 CAN_F21R2_FB4_Msk /*!< Filter bit 4 */ |
| 11178 | #define CAN_F21R2_FB4 CAN_F21R2_FB4_Msk /*!< Filter bit 4 */ |
11178 | #define CAN_F21R2_FB5_Pos (5U) |
| 11179 | #define CAN_F21R2_FB5_Pos (5U) |
11179 | #define CAN_F21R2_FB5_Msk (0x1UL << CAN_F21R2_FB5_Pos) /*!< 0x00000020 */ |
| 11180 | #define CAN_F21R2_FB5_Msk (0x1UL << CAN_F21R2_FB5_Pos) /*!< 0x00000020 */ |
11180 | #define CAN_F21R2_FB5 CAN_F21R2_FB5_Msk /*!< Filter bit 5 */ |
| 11181 | #define CAN_F21R2_FB5 CAN_F21R2_FB5_Msk /*!< Filter bit 5 */ |
11181 | #define CAN_F21R2_FB6_Pos (6U) |
| 11182 | #define CAN_F21R2_FB6_Pos (6U) |
11182 | #define CAN_F21R2_FB6_Msk (0x1UL << CAN_F21R2_FB6_Pos) /*!< 0x00000040 */ |
| 11183 | #define CAN_F21R2_FB6_Msk (0x1UL << CAN_F21R2_FB6_Pos) /*!< 0x00000040 */ |
11183 | #define CAN_F21R2_FB6 CAN_F21R2_FB6_Msk /*!< Filter bit 6 */ |
| 11184 | #define CAN_F21R2_FB6 CAN_F21R2_FB6_Msk /*!< Filter bit 6 */ |
11184 | #define CAN_F21R2_FB7_Pos (7U) |
| 11185 | #define CAN_F21R2_FB7_Pos (7U) |
11185 | #define CAN_F21R2_FB7_Msk (0x1UL << CAN_F21R2_FB7_Pos) /*!< 0x00000080 */ |
| 11186 | #define CAN_F21R2_FB7_Msk (0x1UL << CAN_F21R2_FB7_Pos) /*!< 0x00000080 */ |
11186 | #define CAN_F21R2_FB7 CAN_F21R2_FB7_Msk /*!< Filter bit 7 */ |
| 11187 | #define CAN_F21R2_FB7 CAN_F21R2_FB7_Msk /*!< Filter bit 7 */ |
11187 | #define CAN_F21R2_FB8_Pos (8U) |
| 11188 | #define CAN_F21R2_FB8_Pos (8U) |
11188 | #define CAN_F21R2_FB8_Msk (0x1UL << CAN_F21R2_FB8_Pos) /*!< 0x00000100 */ |
| 11189 | #define CAN_F21R2_FB8_Msk (0x1UL << CAN_F21R2_FB8_Pos) /*!< 0x00000100 */ |
11189 | #define CAN_F21R2_FB8 CAN_F21R2_FB8_Msk /*!< Filter bit 8 */ |
| 11190 | #define CAN_F21R2_FB8 CAN_F21R2_FB8_Msk /*!< Filter bit 8 */ |
11190 | #define CAN_F21R2_FB9_Pos (9U) |
| 11191 | #define CAN_F21R2_FB9_Pos (9U) |
11191 | #define CAN_F21R2_FB9_Msk (0x1UL << CAN_F21R2_FB9_Pos) /*!< 0x00000200 */ |
| 11192 | #define CAN_F21R2_FB9_Msk (0x1UL << CAN_F21R2_FB9_Pos) /*!< 0x00000200 */ |
11192 | #define CAN_F21R2_FB9 CAN_F21R2_FB9_Msk /*!< Filter bit 9 */ |
| 11193 | #define CAN_F21R2_FB9 CAN_F21R2_FB9_Msk /*!< Filter bit 9 */ |
11193 | #define CAN_F21R2_FB10_Pos (10U) |
| 11194 | #define CAN_F21R2_FB10_Pos (10U) |
11194 | #define CAN_F21R2_FB10_Msk (0x1UL << CAN_F21R2_FB10_Pos) /*!< 0x00000400 */ |
| 11195 | #define CAN_F21R2_FB10_Msk (0x1UL << CAN_F21R2_FB10_Pos) /*!< 0x00000400 */ |
11195 | #define CAN_F21R2_FB10 CAN_F21R2_FB10_Msk /*!< Filter bit 10 */ |
| 11196 | #define CAN_F21R2_FB10 CAN_F21R2_FB10_Msk /*!< Filter bit 10 */ |
11196 | #define CAN_F21R2_FB11_Pos (11U) |
| 11197 | #define CAN_F21R2_FB11_Pos (11U) |
11197 | #define CAN_F21R2_FB11_Msk (0x1UL << CAN_F21R2_FB11_Pos) /*!< 0x00000800 */ |
| 11198 | #define CAN_F21R2_FB11_Msk (0x1UL << CAN_F21R2_FB11_Pos) /*!< 0x00000800 */ |
11198 | #define CAN_F21R2_FB11 CAN_F21R2_FB11_Msk /*!< Filter bit 11 */ |
| 11199 | #define CAN_F21R2_FB11 CAN_F21R2_FB11_Msk /*!< Filter bit 11 */ |
11199 | #define CAN_F21R2_FB12_Pos (12U) |
| 11200 | #define CAN_F21R2_FB12_Pos (12U) |
11200 | #define CAN_F21R2_FB12_Msk (0x1UL << CAN_F21R2_FB12_Pos) /*!< 0x00001000 */ |
| 11201 | #define CAN_F21R2_FB12_Msk (0x1UL << CAN_F21R2_FB12_Pos) /*!< 0x00001000 */ |
11201 | #define CAN_F21R2_FB12 CAN_F21R2_FB12_Msk /*!< Filter bit 12 */ |
| 11202 | #define CAN_F21R2_FB12 CAN_F21R2_FB12_Msk /*!< Filter bit 12 */ |
11202 | #define CAN_F21R2_FB13_Pos (13U) |
| 11203 | #define CAN_F21R2_FB13_Pos (13U) |
11203 | #define CAN_F21R2_FB13_Msk (0x1UL << CAN_F21R2_FB13_Pos) /*!< 0x00002000 */ |
| 11204 | #define CAN_F21R2_FB13_Msk (0x1UL << CAN_F21R2_FB13_Pos) /*!< 0x00002000 */ |
11204 | #define CAN_F21R2_FB13 CAN_F21R2_FB13_Msk /*!< Filter bit 13 */ |
| 11205 | #define CAN_F21R2_FB13 CAN_F21R2_FB13_Msk /*!< Filter bit 13 */ |
11205 | #define CAN_F21R2_FB14_Pos (14U) |
| 11206 | #define CAN_F21R2_FB14_Pos (14U) |
11206 | #define CAN_F21R2_FB14_Msk (0x1UL << CAN_F21R2_FB14_Pos) /*!< 0x00004000 */ |
| 11207 | #define CAN_F21R2_FB14_Msk (0x1UL << CAN_F21R2_FB14_Pos) /*!< 0x00004000 */ |
11207 | #define CAN_F21R2_FB14 CAN_F21R2_FB14_Msk /*!< Filter bit 14 */ |
| 11208 | #define CAN_F21R2_FB14 CAN_F21R2_FB14_Msk /*!< Filter bit 14 */ |
11208 | #define CAN_F21R2_FB15_Pos (15U) |
| 11209 | #define CAN_F21R2_FB15_Pos (15U) |
11209 | #define CAN_F21R2_FB15_Msk (0x1UL << CAN_F21R2_FB15_Pos) /*!< 0x00008000 */ |
| 11210 | #define CAN_F21R2_FB15_Msk (0x1UL << CAN_F21R2_FB15_Pos) /*!< 0x00008000 */ |
11210 | #define CAN_F21R2_FB15 CAN_F21R2_FB15_Msk /*!< Filter bit 15 */ |
| 11211 | #define CAN_F21R2_FB15 CAN_F21R2_FB15_Msk /*!< Filter bit 15 */ |
11211 | #define CAN_F21R2_FB16_Pos (16U) |
| 11212 | #define CAN_F21R2_FB16_Pos (16U) |
11212 | #define CAN_F21R2_FB16_Msk (0x1UL << CAN_F21R2_FB16_Pos) /*!< 0x00010000 */ |
| 11213 | #define CAN_F21R2_FB16_Msk (0x1UL << CAN_F21R2_FB16_Pos) /*!< 0x00010000 */ |
11213 | #define CAN_F21R2_FB16 CAN_F21R2_FB16_Msk /*!< Filter bit 16 */ |
| 11214 | #define CAN_F21R2_FB16 CAN_F21R2_FB16_Msk /*!< Filter bit 16 */ |
11214 | #define CAN_F21R2_FB17_Pos (17U) |
| 11215 | #define CAN_F21R2_FB17_Pos (17U) |
11215 | #define CAN_F21R2_FB17_Msk (0x1UL << CAN_F21R2_FB17_Pos) /*!< 0x00020000 */ |
| 11216 | #define CAN_F21R2_FB17_Msk (0x1UL << CAN_F21R2_FB17_Pos) /*!< 0x00020000 */ |
11216 | #define CAN_F21R2_FB17 CAN_F21R2_FB17_Msk /*!< Filter bit 17 */ |
| 11217 | #define CAN_F21R2_FB17 CAN_F21R2_FB17_Msk /*!< Filter bit 17 */ |
11217 | #define CAN_F21R2_FB18_Pos (18U) |
| 11218 | #define CAN_F21R2_FB18_Pos (18U) |
11218 | #define CAN_F21R2_FB18_Msk (0x1UL << CAN_F21R2_FB18_Pos) /*!< 0x00040000 */ |
| 11219 | #define CAN_F21R2_FB18_Msk (0x1UL << CAN_F21R2_FB18_Pos) /*!< 0x00040000 */ |
11219 | #define CAN_F21R2_FB18 CAN_F21R2_FB18_Msk /*!< Filter bit 18 */ |
| 11220 | #define CAN_F21R2_FB18 CAN_F21R2_FB18_Msk /*!< Filter bit 18 */ |
11220 | #define CAN_F21R2_FB19_Pos (19U) |
| 11221 | #define CAN_F21R2_FB19_Pos (19U) |
11221 | #define CAN_F21R2_FB19_Msk (0x1UL << CAN_F21R2_FB19_Pos) /*!< 0x00080000 */ |
| 11222 | #define CAN_F21R2_FB19_Msk (0x1UL << CAN_F21R2_FB19_Pos) /*!< 0x00080000 */ |
11222 | #define CAN_F21R2_FB19 CAN_F21R2_FB19_Msk /*!< Filter bit 19 */ |
| 11223 | #define CAN_F21R2_FB19 CAN_F21R2_FB19_Msk /*!< Filter bit 19 */ |
11223 | #define CAN_F21R2_FB20_Pos (20U) |
| 11224 | #define CAN_F21R2_FB20_Pos (20U) |
11224 | #define CAN_F21R2_FB20_Msk (0x1UL << CAN_F21R2_FB20_Pos) /*!< 0x00100000 */ |
| 11225 | #define CAN_F21R2_FB20_Msk (0x1UL << CAN_F21R2_FB20_Pos) /*!< 0x00100000 */ |
11225 | #define CAN_F21R2_FB20 CAN_F21R2_FB20_Msk /*!< Filter bit 20 */ |
| 11226 | #define CAN_F21R2_FB20 CAN_F21R2_FB20_Msk /*!< Filter bit 20 */ |
11226 | #define CAN_F21R2_FB21_Pos (21U) |
| 11227 | #define CAN_F21R2_FB21_Pos (21U) |
11227 | #define CAN_F21R2_FB21_Msk (0x1UL << CAN_F21R2_FB21_Pos) /*!< 0x00200000 */ |
| 11228 | #define CAN_F21R2_FB21_Msk (0x1UL << CAN_F21R2_FB21_Pos) /*!< 0x00200000 */ |
11228 | #define CAN_F21R2_FB21 CAN_F21R2_FB21_Msk /*!< Filter bit 21 */ |
| 11229 | #define CAN_F21R2_FB21 CAN_F21R2_FB21_Msk /*!< Filter bit 21 */ |
11229 | #define CAN_F21R2_FB22_Pos (22U) |
| 11230 | #define CAN_F21R2_FB22_Pos (22U) |
11230 | #define CAN_F21R2_FB22_Msk (0x1UL << CAN_F21R2_FB22_Pos) /*!< 0x00400000 */ |
| 11231 | #define CAN_F21R2_FB22_Msk (0x1UL << CAN_F21R2_FB22_Pos) /*!< 0x00400000 */ |
11231 | #define CAN_F21R2_FB22 CAN_F21R2_FB22_Msk /*!< Filter bit 22 */ |
| 11232 | #define CAN_F21R2_FB22 CAN_F21R2_FB22_Msk /*!< Filter bit 22 */ |
11232 | #define CAN_F21R2_FB23_Pos (23U) |
| 11233 | #define CAN_F21R2_FB23_Pos (23U) |
11233 | #define CAN_F21R2_FB23_Msk (0x1UL << CAN_F21R2_FB23_Pos) /*!< 0x00800000 */ |
| 11234 | #define CAN_F21R2_FB23_Msk (0x1UL << CAN_F21R2_FB23_Pos) /*!< 0x00800000 */ |
11234 | #define CAN_F21R2_FB23 CAN_F21R2_FB23_Msk /*!< Filter bit 23 */ |
| 11235 | #define CAN_F21R2_FB23 CAN_F21R2_FB23_Msk /*!< Filter bit 23 */ |
11235 | #define CAN_F21R2_FB24_Pos (24U) |
| 11236 | #define CAN_F21R2_FB24_Pos (24U) |
11236 | #define CAN_F21R2_FB24_Msk (0x1UL << CAN_F21R2_FB24_Pos) /*!< 0x01000000 */ |
| 11237 | #define CAN_F21R2_FB24_Msk (0x1UL << CAN_F21R2_FB24_Pos) /*!< 0x01000000 */ |
11237 | #define CAN_F21R2_FB24 CAN_F21R2_FB24_Msk /*!< Filter bit 24 */ |
| 11238 | #define CAN_F21R2_FB24 CAN_F21R2_FB24_Msk /*!< Filter bit 24 */ |
11238 | #define CAN_F21R2_FB25_Pos (25U) |
| 11239 | #define CAN_F21R2_FB25_Pos (25U) |
11239 | #define CAN_F21R2_FB25_Msk (0x1UL << CAN_F21R2_FB25_Pos) /*!< 0x02000000 */ |
| 11240 | #define CAN_F21R2_FB25_Msk (0x1UL << CAN_F21R2_FB25_Pos) /*!< 0x02000000 */ |
11240 | #define CAN_F21R2_FB25 CAN_F21R2_FB25_Msk /*!< Filter bit 25 */ |
| 11241 | #define CAN_F21R2_FB25 CAN_F21R2_FB25_Msk /*!< Filter bit 25 */ |
11241 | #define CAN_F21R2_FB26_Pos (26U) |
| 11242 | #define CAN_F21R2_FB26_Pos (26U) |
11242 | #define CAN_F21R2_FB26_Msk (0x1UL << CAN_F21R2_FB26_Pos) /*!< 0x04000000 */ |
| 11243 | #define CAN_F21R2_FB26_Msk (0x1UL << CAN_F21R2_FB26_Pos) /*!< 0x04000000 */ |
11243 | #define CAN_F21R2_FB26 CAN_F21R2_FB26_Msk /*!< Filter bit 26 */ |
| 11244 | #define CAN_F21R2_FB26 CAN_F21R2_FB26_Msk /*!< Filter bit 26 */ |
11244 | #define CAN_F21R2_FB27_Pos (27U) |
| 11245 | #define CAN_F21R2_FB27_Pos (27U) |
11245 | #define CAN_F21R2_FB27_Msk (0x1UL << CAN_F21R2_FB27_Pos) /*!< 0x08000000 */ |
| 11246 | #define CAN_F21R2_FB27_Msk (0x1UL << CAN_F21R2_FB27_Pos) /*!< 0x08000000 */ |
11246 | #define CAN_F21R2_FB27 CAN_F21R2_FB27_Msk /*!< Filter bit 27 */ |
| 11247 | #define CAN_F21R2_FB27 CAN_F21R2_FB27_Msk /*!< Filter bit 27 */ |
11247 | #define CAN_F21R2_FB28_Pos (28U) |
| 11248 | #define CAN_F21R2_FB28_Pos (28U) |
11248 | #define CAN_F21R2_FB28_Msk (0x1UL << CAN_F21R2_FB28_Pos) /*!< 0x10000000 */ |
| 11249 | #define CAN_F21R2_FB28_Msk (0x1UL << CAN_F21R2_FB28_Pos) /*!< 0x10000000 */ |
11249 | #define CAN_F21R2_FB28 CAN_F21R2_FB28_Msk /*!< Filter bit 28 */ |
| 11250 | #define CAN_F21R2_FB28 CAN_F21R2_FB28_Msk /*!< Filter bit 28 */ |
11250 | #define CAN_F21R2_FB29_Pos (29U) |
| 11251 | #define CAN_F21R2_FB29_Pos (29U) |
11251 | #define CAN_F21R2_FB29_Msk (0x1UL << CAN_F21R2_FB29_Pos) /*!< 0x20000000 */ |
| 11252 | #define CAN_F21R2_FB29_Msk (0x1UL << CAN_F21R2_FB29_Pos) /*!< 0x20000000 */ |
11252 | #define CAN_F21R2_FB29 CAN_F21R2_FB29_Msk /*!< Filter bit 29 */ |
| 11253 | #define CAN_F21R2_FB29 CAN_F21R2_FB29_Msk /*!< Filter bit 29 */ |
11253 | #define CAN_F21R2_FB30_Pos (30U) |
| 11254 | #define CAN_F21R2_FB30_Pos (30U) |
11254 | #define CAN_F21R2_FB30_Msk (0x1UL << CAN_F21R2_FB30_Pos) /*!< 0x40000000 */ |
| 11255 | #define CAN_F21R2_FB30_Msk (0x1UL << CAN_F21R2_FB30_Pos) /*!< 0x40000000 */ |
11255 | #define CAN_F21R2_FB30 CAN_F21R2_FB30_Msk /*!< Filter bit 30 */ |
| 11256 | #define CAN_F21R2_FB30 CAN_F21R2_FB30_Msk /*!< Filter bit 30 */ |
11256 | #define CAN_F21R2_FB31_Pos (31U) |
| 11257 | #define CAN_F21R2_FB31_Pos (31U) |
11257 | #define CAN_F21R2_FB31_Msk (0x1UL << CAN_F21R2_FB31_Pos) /*!< 0x80000000 */ |
| 11258 | #define CAN_F21R2_FB31_Msk (0x1UL << CAN_F21R2_FB31_Pos) /*!< 0x80000000 */ |
11258 | #define CAN_F21R2_FB31 CAN_F21R2_FB31_Msk /*!< Filter bit 31 */ |
| 11259 | #define CAN_F21R2_FB31 CAN_F21R2_FB31_Msk /*!< Filter bit 31 */ |
11259 | |
| 11260 | 11260 | /******************* Bit definition for CAN_F22R2 register ******************/ |
|
| 11261 | /******************* Bit definition for CAN_F22R2 register ******************/ |
11261 | #define CAN_F22R2_FB0_Pos (0U) |
| 11262 | #define CAN_F22R2_FB0_Pos (0U) |
11262 | #define CAN_F22R2_FB0_Msk (0x1UL << CAN_F22R2_FB0_Pos) /*!< 0x00000001 */ |
| 11263 | #define CAN_F22R2_FB0_Msk (0x1UL << CAN_F22R2_FB0_Pos) /*!< 0x00000001 */ |
11263 | #define CAN_F22R2_FB0 CAN_F22R2_FB0_Msk /*!< Filter bit 0 */ |
| 11264 | #define CAN_F22R2_FB0 CAN_F22R2_FB0_Msk /*!< Filter bit 0 */ |
11264 | #define CAN_F22R2_FB1_Pos (1U) |
| 11265 | #define CAN_F22R2_FB1_Pos (1U) |
11265 | #define CAN_F22R2_FB1_Msk (0x1UL << CAN_F22R2_FB1_Pos) /*!< 0x00000002 */ |
| 11266 | #define CAN_F22R2_FB1_Msk (0x1UL << CAN_F22R2_FB1_Pos) /*!< 0x00000002 */ |
11266 | #define CAN_F22R2_FB1 CAN_F22R2_FB1_Msk /*!< Filter bit 1 */ |
| 11267 | #define CAN_F22R2_FB1 CAN_F22R2_FB1_Msk /*!< Filter bit 1 */ |
11267 | #define CAN_F22R2_FB2_Pos (2U) |
| 11268 | #define CAN_F22R2_FB2_Pos (2U) |
11268 | #define CAN_F22R2_FB2_Msk (0x1UL << CAN_F22R2_FB2_Pos) /*!< 0x00000004 */ |
| 11269 | #define CAN_F22R2_FB2_Msk (0x1UL << CAN_F22R2_FB2_Pos) /*!< 0x00000004 */ |
11269 | #define CAN_F22R2_FB2 CAN_F22R2_FB2_Msk /*!< Filter bit 2 */ |
| 11270 | #define CAN_F22R2_FB2 CAN_F22R2_FB2_Msk /*!< Filter bit 2 */ |
11270 | #define CAN_F22R2_FB3_Pos (3U) |
| 11271 | #define CAN_F22R2_FB3_Pos (3U) |
11271 | #define CAN_F22R2_FB3_Msk (0x1UL << CAN_F22R2_FB3_Pos) /*!< 0x00000008 */ |
| 11272 | #define CAN_F22R2_FB3_Msk (0x1UL << CAN_F22R2_FB3_Pos) /*!< 0x00000008 */ |
11272 | #define CAN_F22R2_FB3 CAN_F22R2_FB3_Msk /*!< Filter bit 3 */ |
| 11273 | #define CAN_F22R2_FB3 CAN_F22R2_FB3_Msk /*!< Filter bit 3 */ |
11273 | #define CAN_F22R2_FB4_Pos (4U) |
| 11274 | #define CAN_F22R2_FB4_Pos (4U) |
11274 | #define CAN_F22R2_FB4_Msk (0x1UL << CAN_F22R2_FB4_Pos) /*!< 0x00000010 */ |
| 11275 | #define CAN_F22R2_FB4_Msk (0x1UL << CAN_F22R2_FB4_Pos) /*!< 0x00000010 */ |
11275 | #define CAN_F22R2_FB4 CAN_F22R2_FB4_Msk /*!< Filter bit 4 */ |
| 11276 | #define CAN_F22R2_FB4 CAN_F22R2_FB4_Msk /*!< Filter bit 4 */ |
11276 | #define CAN_F22R2_FB5_Pos (5U) |
| 11277 | #define CAN_F22R2_FB5_Pos (5U) |
11277 | #define CAN_F22R2_FB5_Msk (0x1UL << CAN_F22R2_FB5_Pos) /*!< 0x00000020 */ |
| 11278 | #define CAN_F22R2_FB5_Msk (0x1UL << CAN_F22R2_FB5_Pos) /*!< 0x00000020 */ |
11278 | #define CAN_F22R2_FB5 CAN_F22R2_FB5_Msk /*!< Filter bit 5 */ |
| 11279 | #define CAN_F22R2_FB5 CAN_F22R2_FB5_Msk /*!< Filter bit 5 */ |
11279 | #define CAN_F22R2_FB6_Pos (6U) |
| 11280 | #define CAN_F22R2_FB6_Pos (6U) |
11280 | #define CAN_F22R2_FB6_Msk (0x1UL << CAN_F22R2_FB6_Pos) /*!< 0x00000040 */ |
| 11281 | #define CAN_F22R2_FB6_Msk (0x1UL << CAN_F22R2_FB6_Pos) /*!< 0x00000040 */ |
11281 | #define CAN_F22R2_FB6 CAN_F22R2_FB6_Msk /*!< Filter bit 6 */ |
| 11282 | #define CAN_F22R2_FB6 CAN_F22R2_FB6_Msk /*!< Filter bit 6 */ |
11282 | #define CAN_F22R2_FB7_Pos (7U) |
| 11283 | #define CAN_F22R2_FB7_Pos (7U) |
11283 | #define CAN_F22R2_FB7_Msk (0x1UL << CAN_F22R2_FB7_Pos) /*!< 0x00000080 */ |
| 11284 | #define CAN_F22R2_FB7_Msk (0x1UL << CAN_F22R2_FB7_Pos) /*!< 0x00000080 */ |
11284 | #define CAN_F22R2_FB7 CAN_F22R2_FB7_Msk /*!< Filter bit 7 */ |
| 11285 | #define CAN_F22R2_FB7 CAN_F22R2_FB7_Msk /*!< Filter bit 7 */ |
11285 | #define CAN_F22R2_FB8_Pos (8U) |
| 11286 | #define CAN_F22R2_FB8_Pos (8U) |
11286 | #define CAN_F22R2_FB8_Msk (0x1UL << CAN_F22R2_FB8_Pos) /*!< 0x00000100 */ |
| 11287 | #define CAN_F22R2_FB8_Msk (0x1UL << CAN_F22R2_FB8_Pos) /*!< 0x00000100 */ |
11287 | #define CAN_F22R2_FB8 CAN_F22R2_FB8_Msk /*!< Filter bit 8 */ |
| 11288 | #define CAN_F22R2_FB8 CAN_F22R2_FB8_Msk /*!< Filter bit 8 */ |
11288 | #define CAN_F22R2_FB9_Pos (9U) |
| 11289 | #define CAN_F22R2_FB9_Pos (9U) |
11289 | #define CAN_F22R2_FB9_Msk (0x1UL << CAN_F22R2_FB9_Pos) /*!< 0x00000200 */ |
| 11290 | #define CAN_F22R2_FB9_Msk (0x1UL << CAN_F22R2_FB9_Pos) /*!< 0x00000200 */ |
11290 | #define CAN_F22R2_FB9 CAN_F22R2_FB9_Msk /*!< Filter bit 9 */ |
| 11291 | #define CAN_F22R2_FB9 CAN_F22R2_FB9_Msk /*!< Filter bit 9 */ |
11291 | #define CAN_F22R2_FB10_Pos (10U) |
| 11292 | #define CAN_F22R2_FB10_Pos (10U) |
11292 | #define CAN_F22R2_FB10_Msk (0x1UL << CAN_F22R2_FB10_Pos) /*!< 0x00000400 */ |
| 11293 | #define CAN_F22R2_FB10_Msk (0x1UL << CAN_F22R2_FB10_Pos) /*!< 0x00000400 */ |
11293 | #define CAN_F22R2_FB10 CAN_F22R2_FB10_Msk /*!< Filter bit 10 */ |
| 11294 | #define CAN_F22R2_FB10 CAN_F22R2_FB10_Msk /*!< Filter bit 10 */ |
11294 | #define CAN_F22R2_FB11_Pos (11U) |
| 11295 | #define CAN_F22R2_FB11_Pos (11U) |
11295 | #define CAN_F22R2_FB11_Msk (0x1UL << CAN_F22R2_FB11_Pos) /*!< 0x00000800 */ |
| 11296 | #define CAN_F22R2_FB11_Msk (0x1UL << CAN_F22R2_FB11_Pos) /*!< 0x00000800 */ |
11296 | #define CAN_F22R2_FB11 CAN_F22R2_FB11_Msk /*!< Filter bit 11 */ |
| 11297 | #define CAN_F22R2_FB11 CAN_F22R2_FB11_Msk /*!< Filter bit 11 */ |
11297 | #define CAN_F22R2_FB12_Pos (12U) |
| 11298 | #define CAN_F22R2_FB12_Pos (12U) |
11298 | #define CAN_F22R2_FB12_Msk (0x1UL << CAN_F22R2_FB12_Pos) /*!< 0x00001000 */ |
| 11299 | #define CAN_F22R2_FB12_Msk (0x1UL << CAN_F22R2_FB12_Pos) /*!< 0x00001000 */ |
11299 | #define CAN_F22R2_FB12 CAN_F22R2_FB12_Msk /*!< Filter bit 12 */ |
| 11300 | #define CAN_F22R2_FB12 CAN_F22R2_FB12_Msk /*!< Filter bit 12 */ |
11300 | #define CAN_F22R2_FB13_Pos (13U) |
| 11301 | #define CAN_F22R2_FB13_Pos (13U) |
11301 | #define CAN_F22R2_FB13_Msk (0x1UL << CAN_F22R2_FB13_Pos) /*!< 0x00002000 */ |
| 11302 | #define CAN_F22R2_FB13_Msk (0x1UL << CAN_F22R2_FB13_Pos) /*!< 0x00002000 */ |
11302 | #define CAN_F22R2_FB13 CAN_F22R2_FB13_Msk /*!< Filter bit 13 */ |
| 11303 | #define CAN_F22R2_FB13 CAN_F22R2_FB13_Msk /*!< Filter bit 13 */ |
11303 | #define CAN_F22R2_FB14_Pos (14U) |
| 11304 | #define CAN_F22R2_FB14_Pos (14U) |
11304 | #define CAN_F22R2_FB14_Msk (0x1UL << CAN_F22R2_FB14_Pos) /*!< 0x00004000 */ |
| 11305 | #define CAN_F22R2_FB14_Msk (0x1UL << CAN_F22R2_FB14_Pos) /*!< 0x00004000 */ |
11305 | #define CAN_F22R2_FB14 CAN_F22R2_FB14_Msk /*!< Filter bit 14 */ |
| 11306 | #define CAN_F22R2_FB14 CAN_F22R2_FB14_Msk /*!< Filter bit 14 */ |
11306 | #define CAN_F22R2_FB15_Pos (15U) |
| 11307 | #define CAN_F22R2_FB15_Pos (15U) |
11307 | #define CAN_F22R2_FB15_Msk (0x1UL << CAN_F22R2_FB15_Pos) /*!< 0x00008000 */ |
| 11308 | #define CAN_F22R2_FB15_Msk (0x1UL << CAN_F22R2_FB15_Pos) /*!< 0x00008000 */ |
11308 | #define CAN_F22R2_FB15 CAN_F22R2_FB15_Msk /*!< Filter bit 15 */ |
| 11309 | #define CAN_F22R2_FB15 CAN_F22R2_FB15_Msk /*!< Filter bit 15 */ |
11309 | #define CAN_F22R2_FB16_Pos (16U) |
| 11310 | #define CAN_F22R2_FB16_Pos (16U) |
11310 | #define CAN_F22R2_FB16_Msk (0x1UL << CAN_F22R2_FB16_Pos) /*!< 0x00010000 */ |
| 11311 | #define CAN_F22R2_FB16_Msk (0x1UL << CAN_F22R2_FB16_Pos) /*!< 0x00010000 */ |
11311 | #define CAN_F22R2_FB16 CAN_F22R2_FB16_Msk /*!< Filter bit 16 */ |
| 11312 | #define CAN_F22R2_FB16 CAN_F22R2_FB16_Msk /*!< Filter bit 16 */ |
11312 | #define CAN_F22R2_FB17_Pos (17U) |
| 11313 | #define CAN_F22R2_FB17_Pos (17U) |
11313 | #define CAN_F22R2_FB17_Msk (0x1UL << CAN_F22R2_FB17_Pos) /*!< 0x00020000 */ |
| 11314 | #define CAN_F22R2_FB17_Msk (0x1UL << CAN_F22R2_FB17_Pos) /*!< 0x00020000 */ |
11314 | #define CAN_F22R2_FB17 CAN_F22R2_FB17_Msk /*!< Filter bit 17 */ |
| 11315 | #define CAN_F22R2_FB17 CAN_F22R2_FB17_Msk /*!< Filter bit 17 */ |
11315 | #define CAN_F22R2_FB18_Pos (18U) |
| 11316 | #define CAN_F22R2_FB18_Pos (18U) |
11316 | #define CAN_F22R2_FB18_Msk (0x1UL << CAN_F22R2_FB18_Pos) /*!< 0x00040000 */ |
| 11317 | #define CAN_F22R2_FB18_Msk (0x1UL << CAN_F22R2_FB18_Pos) /*!< 0x00040000 */ |
11317 | #define CAN_F22R2_FB18 CAN_F22R2_FB18_Msk /*!< Filter bit 18 */ |
| 11318 | #define CAN_F22R2_FB18 CAN_F22R2_FB18_Msk /*!< Filter bit 18 */ |
11318 | #define CAN_F22R2_FB19_Pos (19U) |
| 11319 | #define CAN_F22R2_FB19_Pos (19U) |
11319 | #define CAN_F22R2_FB19_Msk (0x1UL << CAN_F22R2_FB19_Pos) /*!< 0x00080000 */ |
| 11320 | #define CAN_F22R2_FB19_Msk (0x1UL << CAN_F22R2_FB19_Pos) /*!< 0x00080000 */ |
11320 | #define CAN_F22R2_FB19 CAN_F22R2_FB19_Msk /*!< Filter bit 19 */ |
| 11321 | #define CAN_F22R2_FB19 CAN_F22R2_FB19_Msk /*!< Filter bit 19 */ |
11321 | #define CAN_F22R2_FB20_Pos (20U) |
| 11322 | #define CAN_F22R2_FB20_Pos (20U) |
11322 | #define CAN_F22R2_FB20_Msk (0x1UL << CAN_F22R2_FB20_Pos) /*!< 0x00100000 */ |
| 11323 | #define CAN_F22R2_FB20_Msk (0x1UL << CAN_F22R2_FB20_Pos) /*!< 0x00100000 */ |
11323 | #define CAN_F22R2_FB20 CAN_F22R2_FB20_Msk /*!< Filter bit 20 */ |
| 11324 | #define CAN_F22R2_FB20 CAN_F22R2_FB20_Msk /*!< Filter bit 20 */ |
11324 | #define CAN_F22R2_FB21_Pos (21U) |
| 11325 | #define CAN_F22R2_FB21_Pos (21U) |
11325 | #define CAN_F22R2_FB21_Msk (0x1UL << CAN_F22R2_FB21_Pos) /*!< 0x00200000 */ |
| 11326 | #define CAN_F22R2_FB21_Msk (0x1UL << CAN_F22R2_FB21_Pos) /*!< 0x00200000 */ |
11326 | #define CAN_F22R2_FB21 CAN_F22R2_FB21_Msk /*!< Filter bit 21 */ |
| 11327 | #define CAN_F22R2_FB21 CAN_F22R2_FB21_Msk /*!< Filter bit 21 */ |
11327 | #define CAN_F22R2_FB22_Pos (22U) |
| 11328 | #define CAN_F22R2_FB22_Pos (22U) |
11328 | #define CAN_F22R2_FB22_Msk (0x1UL << CAN_F22R2_FB22_Pos) /*!< 0x00400000 */ |
| 11329 | #define CAN_F22R2_FB22_Msk (0x1UL << CAN_F22R2_FB22_Pos) /*!< 0x00400000 */ |
11329 | #define CAN_F22R2_FB22 CAN_F22R2_FB22_Msk /*!< Filter bit 22 */ |
| 11330 | #define CAN_F22R2_FB22 CAN_F22R2_FB22_Msk /*!< Filter bit 22 */ |
11330 | #define CAN_F22R2_FB23_Pos (23U) |
| 11331 | #define CAN_F22R2_FB23_Pos (23U) |
11331 | #define CAN_F22R2_FB23_Msk (0x1UL << CAN_F22R2_FB23_Pos) /*!< 0x00800000 */ |
| 11332 | #define CAN_F22R2_FB23_Msk (0x1UL << CAN_F22R2_FB23_Pos) /*!< 0x00800000 */ |
11332 | #define CAN_F22R2_FB23 CAN_F22R2_FB23_Msk /*!< Filter bit 23 */ |
| 11333 | #define CAN_F22R2_FB23 CAN_F22R2_FB23_Msk /*!< Filter bit 23 */ |
11333 | #define CAN_F22R2_FB24_Pos (24U) |
| 11334 | #define CAN_F22R2_FB24_Pos (24U) |
11334 | #define CAN_F22R2_FB24_Msk (0x1UL << CAN_F22R2_FB24_Pos) /*!< 0x01000000 */ |
| 11335 | #define CAN_F22R2_FB24_Msk (0x1UL << CAN_F22R2_FB24_Pos) /*!< 0x01000000 */ |
11335 | #define CAN_F22R2_FB24 CAN_F22R2_FB24_Msk /*!< Filter bit 24 */ |
| 11336 | #define CAN_F22R2_FB24 CAN_F22R2_FB24_Msk /*!< Filter bit 24 */ |
11336 | #define CAN_F22R2_FB25_Pos (25U) |
| 11337 | #define CAN_F22R2_FB25_Pos (25U) |
11337 | #define CAN_F22R2_FB25_Msk (0x1UL << CAN_F22R2_FB25_Pos) /*!< 0x02000000 */ |
| 11338 | #define CAN_F22R2_FB25_Msk (0x1UL << CAN_F22R2_FB25_Pos) /*!< 0x02000000 */ |
11338 | #define CAN_F22R2_FB25 CAN_F22R2_FB25_Msk /*!< Filter bit 25 */ |
| 11339 | #define CAN_F22R2_FB25 CAN_F22R2_FB25_Msk /*!< Filter bit 25 */ |
11339 | #define CAN_F22R2_FB26_Pos (26U) |
| 11340 | #define CAN_F22R2_FB26_Pos (26U) |
11340 | #define CAN_F22R2_FB26_Msk (0x1UL << CAN_F22R2_FB26_Pos) /*!< 0x04000000 */ |
| 11341 | #define CAN_F22R2_FB26_Msk (0x1UL << CAN_F22R2_FB26_Pos) /*!< 0x04000000 */ |
11341 | #define CAN_F22R2_FB26 CAN_F22R2_FB26_Msk /*!< Filter bit 26 */ |
| 11342 | #define CAN_F22R2_FB26 CAN_F22R2_FB26_Msk /*!< Filter bit 26 */ |
11342 | #define CAN_F22R2_FB27_Pos (27U) |
| 11343 | #define CAN_F22R2_FB27_Pos (27U) |
11343 | #define CAN_F22R2_FB27_Msk (0x1UL << CAN_F22R2_FB27_Pos) /*!< 0x08000000 */ |
| 11344 | #define CAN_F22R2_FB27_Msk (0x1UL << CAN_F22R2_FB27_Pos) /*!< 0x08000000 */ |
11344 | #define CAN_F22R2_FB27 CAN_F22R2_FB27_Msk /*!< Filter bit 27 */ |
| 11345 | #define CAN_F22R2_FB27 CAN_F22R2_FB27_Msk /*!< Filter bit 27 */ |
11345 | #define CAN_F22R2_FB28_Pos (28U) |
| 11346 | #define CAN_F22R2_FB28_Pos (28U) |
11346 | #define CAN_F22R2_FB28_Msk (0x1UL << CAN_F22R2_FB28_Pos) /*!< 0x10000000 */ |
| 11347 | #define CAN_F22R2_FB28_Msk (0x1UL << CAN_F22R2_FB28_Pos) /*!< 0x10000000 */ |
11347 | #define CAN_F22R2_FB28 CAN_F22R2_FB28_Msk /*!< Filter bit 28 */ |
| 11348 | #define CAN_F22R2_FB28 CAN_F22R2_FB28_Msk /*!< Filter bit 28 */ |
11348 | #define CAN_F22R2_FB29_Pos (29U) |
| 11349 | #define CAN_F22R2_FB29_Pos (29U) |
11349 | #define CAN_F22R2_FB29_Msk (0x1UL << CAN_F22R2_FB29_Pos) /*!< 0x20000000 */ |
| 11350 | #define CAN_F22R2_FB29_Msk (0x1UL << CAN_F22R2_FB29_Pos) /*!< 0x20000000 */ |
11350 | #define CAN_F22R2_FB29 CAN_F22R2_FB29_Msk /*!< Filter bit 29 */ |
| 11351 | #define CAN_F22R2_FB29 CAN_F22R2_FB29_Msk /*!< Filter bit 29 */ |
11351 | #define CAN_F22R2_FB30_Pos (30U) |
| 11352 | #define CAN_F22R2_FB30_Pos (30U) |
11352 | #define CAN_F22R2_FB30_Msk (0x1UL << CAN_F22R2_FB30_Pos) /*!< 0x40000000 */ |
| 11353 | #define CAN_F22R2_FB30_Msk (0x1UL << CAN_F22R2_FB30_Pos) /*!< 0x40000000 */ |
11353 | #define CAN_F22R2_FB30 CAN_F22R2_FB30_Msk /*!< Filter bit 30 */ |
| 11354 | #define CAN_F22R2_FB30 CAN_F22R2_FB30_Msk /*!< Filter bit 30 */ |
11354 | #define CAN_F22R2_FB31_Pos (31U) |
| 11355 | #define CAN_F22R2_FB31_Pos (31U) |
11355 | #define CAN_F22R2_FB31_Msk (0x1UL << CAN_F22R2_FB31_Pos) /*!< 0x80000000 */ |
| 11356 | #define CAN_F22R2_FB31_Msk (0x1UL << CAN_F22R2_FB31_Pos) /*!< 0x80000000 */ |
11356 | #define CAN_F22R2_FB31 CAN_F22R2_FB31_Msk /*!< Filter bit 31 */ |
| 11357 | #define CAN_F22R2_FB31 CAN_F22R2_FB31_Msk /*!< Filter bit 31 */ |
11357 | |
| 11358 | 11358 | /******************* Bit definition for CAN_F23R2 register ******************/ |
|
| 11359 | /******************* Bit definition for CAN_F23R2 register ******************/ |
11359 | #define CAN_F23R2_FB0_Pos (0U) |
| 11360 | #define CAN_F23R2_FB0_Pos (0U) |
11360 | #define CAN_F23R2_FB0_Msk (0x1UL << CAN_F23R2_FB0_Pos) /*!< 0x00000001 */ |
| 11361 | #define CAN_F23R2_FB0_Msk (0x1UL << CAN_F23R2_FB0_Pos) /*!< 0x00000001 */ |
11361 | #define CAN_F23R2_FB0 CAN_F23R2_FB0_Msk /*!< Filter bit 0 */ |
| 11362 | #define CAN_F23R2_FB0 CAN_F23R2_FB0_Msk /*!< Filter bit 0 */ |
11362 | #define CAN_F23R2_FB1_Pos (1U) |
| 11363 | #define CAN_F23R2_FB1_Pos (1U) |
11363 | #define CAN_F23R2_FB1_Msk (0x1UL << CAN_F23R2_FB1_Pos) /*!< 0x00000002 */ |
| 11364 | #define CAN_F23R2_FB1_Msk (0x1UL << CAN_F23R2_FB1_Pos) /*!< 0x00000002 */ |
11364 | #define CAN_F23R2_FB1 CAN_F23R2_FB1_Msk /*!< Filter bit 1 */ |
| 11365 | #define CAN_F23R2_FB1 CAN_F23R2_FB1_Msk /*!< Filter bit 1 */ |
11365 | #define CAN_F23R2_FB2_Pos (2U) |
| 11366 | #define CAN_F23R2_FB2_Pos (2U) |
11366 | #define CAN_F23R2_FB2_Msk (0x1UL << CAN_F23R2_FB2_Pos) /*!< 0x00000004 */ |
| 11367 | #define CAN_F23R2_FB2_Msk (0x1UL << CAN_F23R2_FB2_Pos) /*!< 0x00000004 */ |
11367 | #define CAN_F23R2_FB2 CAN_F23R2_FB2_Msk /*!< Filter bit 2 */ |
| 11368 | #define CAN_F23R2_FB2 CAN_F23R2_FB2_Msk /*!< Filter bit 2 */ |
11368 | #define CAN_F23R2_FB3_Pos (3U) |
| 11369 | #define CAN_F23R2_FB3_Pos (3U) |
11369 | #define CAN_F23R2_FB3_Msk (0x1UL << CAN_F23R2_FB3_Pos) /*!< 0x00000008 */ |
| 11370 | #define CAN_F23R2_FB3_Msk (0x1UL << CAN_F23R2_FB3_Pos) /*!< 0x00000008 */ |
11370 | #define CAN_F23R2_FB3 CAN_F23R2_FB3_Msk /*!< Filter bit 3 */ |
| 11371 | #define CAN_F23R2_FB3 CAN_F23R2_FB3_Msk /*!< Filter bit 3 */ |
11371 | #define CAN_F23R2_FB4_Pos (4U) |
| 11372 | #define CAN_F23R2_FB4_Pos (4U) |
11372 | #define CAN_F23R2_FB4_Msk (0x1UL << CAN_F23R2_FB4_Pos) /*!< 0x00000010 */ |
| 11373 | #define CAN_F23R2_FB4_Msk (0x1UL << CAN_F23R2_FB4_Pos) /*!< 0x00000010 */ |
11373 | #define CAN_F23R2_FB4 CAN_F23R2_FB4_Msk /*!< Filter bit 4 */ |
| 11374 | #define CAN_F23R2_FB4 CAN_F23R2_FB4_Msk /*!< Filter bit 4 */ |
11374 | #define CAN_F23R2_FB5_Pos (5U) |
| 11375 | #define CAN_F23R2_FB5_Pos (5U) |
11375 | #define CAN_F23R2_FB5_Msk (0x1UL << CAN_F23R2_FB5_Pos) /*!< 0x00000020 */ |
| 11376 | #define CAN_F23R2_FB5_Msk (0x1UL << CAN_F23R2_FB5_Pos) /*!< 0x00000020 */ |
11376 | #define CAN_F23R2_FB5 CAN_F23R2_FB5_Msk /*!< Filter bit 5 */ |
| 11377 | #define CAN_F23R2_FB5 CAN_F23R2_FB5_Msk /*!< Filter bit 5 */ |
11377 | #define CAN_F23R2_FB6_Pos (6U) |
| 11378 | #define CAN_F23R2_FB6_Pos (6U) |
11378 | #define CAN_F23R2_FB6_Msk (0x1UL << CAN_F23R2_FB6_Pos) /*!< 0x00000040 */ |
| 11379 | #define CAN_F23R2_FB6_Msk (0x1UL << CAN_F23R2_FB6_Pos) /*!< 0x00000040 */ |
11379 | #define CAN_F23R2_FB6 CAN_F23R2_FB6_Msk /*!< Filter bit 6 */ |
| 11380 | #define CAN_F23R2_FB6 CAN_F23R2_FB6_Msk /*!< Filter bit 6 */ |
11380 | #define CAN_F23R2_FB7_Pos (7U) |
| 11381 | #define CAN_F23R2_FB7_Pos (7U) |
11381 | #define CAN_F23R2_FB7_Msk (0x1UL << CAN_F23R2_FB7_Pos) /*!< 0x00000080 */ |
| 11382 | #define CAN_F23R2_FB7_Msk (0x1UL << CAN_F23R2_FB7_Pos) /*!< 0x00000080 */ |
11382 | #define CAN_F23R2_FB7 CAN_F23R2_FB7_Msk /*!< Filter bit 7 */ |
| 11383 | #define CAN_F23R2_FB7 CAN_F23R2_FB7_Msk /*!< Filter bit 7 */ |
11383 | #define CAN_F23R2_FB8_Pos (8U) |
| 11384 | #define CAN_F23R2_FB8_Pos (8U) |
11384 | #define CAN_F23R2_FB8_Msk (0x1UL << CAN_F23R2_FB8_Pos) /*!< 0x00000100 */ |
| 11385 | #define CAN_F23R2_FB8_Msk (0x1UL << CAN_F23R2_FB8_Pos) /*!< 0x00000100 */ |
11385 | #define CAN_F23R2_FB8 CAN_F23R2_FB8_Msk /*!< Filter bit 8 */ |
| 11386 | #define CAN_F23R2_FB8 CAN_F23R2_FB8_Msk /*!< Filter bit 8 */ |
11386 | #define CAN_F23R2_FB9_Pos (9U) |
| 11387 | #define CAN_F23R2_FB9_Pos (9U) |
11387 | #define CAN_F23R2_FB9_Msk (0x1UL << CAN_F23R2_FB9_Pos) /*!< 0x00000200 */ |
| 11388 | #define CAN_F23R2_FB9_Msk (0x1UL << CAN_F23R2_FB9_Pos) /*!< 0x00000200 */ |
11388 | #define CAN_F23R2_FB9 CAN_F23R2_FB9_Msk /*!< Filter bit 9 */ |
| 11389 | #define CAN_F23R2_FB9 CAN_F23R2_FB9_Msk /*!< Filter bit 9 */ |
11389 | #define CAN_F23R2_FB10_Pos (10U) |
| 11390 | #define CAN_F23R2_FB10_Pos (10U) |
11390 | #define CAN_F23R2_FB10_Msk (0x1UL << CAN_F23R2_FB10_Pos) /*!< 0x00000400 */ |
| 11391 | #define CAN_F23R2_FB10_Msk (0x1UL << CAN_F23R2_FB10_Pos) /*!< 0x00000400 */ |
11391 | #define CAN_F23R2_FB10 CAN_F23R2_FB10_Msk /*!< Filter bit 10 */ |
| 11392 | #define CAN_F23R2_FB10 CAN_F23R2_FB10_Msk /*!< Filter bit 10 */ |
11392 | #define CAN_F23R2_FB11_Pos (11U) |
| 11393 | #define CAN_F23R2_FB11_Pos (11U) |
11393 | #define CAN_F23R2_FB11_Msk (0x1UL << CAN_F23R2_FB11_Pos) /*!< 0x00000800 */ |
| 11394 | #define CAN_F23R2_FB11_Msk (0x1UL << CAN_F23R2_FB11_Pos) /*!< 0x00000800 */ |
11394 | #define CAN_F23R2_FB11 CAN_F23R2_FB11_Msk /*!< Filter bit 11 */ |
| 11395 | #define CAN_F23R2_FB11 CAN_F23R2_FB11_Msk /*!< Filter bit 11 */ |
11395 | #define CAN_F23R2_FB12_Pos (12U) |
| 11396 | #define CAN_F23R2_FB12_Pos (12U) |
11396 | #define CAN_F23R2_FB12_Msk (0x1UL << CAN_F23R2_FB12_Pos) /*!< 0x00001000 */ |
| 11397 | #define CAN_F23R2_FB12_Msk (0x1UL << CAN_F23R2_FB12_Pos) /*!< 0x00001000 */ |
11397 | #define CAN_F23R2_FB12 CAN_F23R2_FB12_Msk /*!< Filter bit 12 */ |
| 11398 | #define CAN_F23R2_FB12 CAN_F23R2_FB12_Msk /*!< Filter bit 12 */ |
11398 | #define CAN_F23R2_FB13_Pos (13U) |
| 11399 | #define CAN_F23R2_FB13_Pos (13U) |
11399 | #define CAN_F23R2_FB13_Msk (0x1UL << CAN_F23R2_FB13_Pos) /*!< 0x00002000 */ |
| 11400 | #define CAN_F23R2_FB13_Msk (0x1UL << CAN_F23R2_FB13_Pos) /*!< 0x00002000 */ |
11400 | #define CAN_F23R2_FB13 CAN_F23R2_FB13_Msk /*!< Filter bit 13 */ |
| 11401 | #define CAN_F23R2_FB13 CAN_F23R2_FB13_Msk /*!< Filter bit 13 */ |
11401 | #define CAN_F23R2_FB14_Pos (14U) |
| 11402 | #define CAN_F23R2_FB14_Pos (14U) |
11402 | #define CAN_F23R2_FB14_Msk (0x1UL << CAN_F23R2_FB14_Pos) /*!< 0x00004000 */ |
| 11403 | #define CAN_F23R2_FB14_Msk (0x1UL << CAN_F23R2_FB14_Pos) /*!< 0x00004000 */ |
11403 | #define CAN_F23R2_FB14 CAN_F23R2_FB14_Msk /*!< Filter bit 14 */ |
| 11404 | #define CAN_F23R2_FB14 CAN_F23R2_FB14_Msk /*!< Filter bit 14 */ |
11404 | #define CAN_F23R2_FB15_Pos (15U) |
| 11405 | #define CAN_F23R2_FB15_Pos (15U) |
11405 | #define CAN_F23R2_FB15_Msk (0x1UL << CAN_F23R2_FB15_Pos) /*!< 0x00008000 */ |
| 11406 | #define CAN_F23R2_FB15_Msk (0x1UL << CAN_F23R2_FB15_Pos) /*!< 0x00008000 */ |
11406 | #define CAN_F23R2_FB15 CAN_F23R2_FB15_Msk /*!< Filter bit 15 */ |
| 11407 | #define CAN_F23R2_FB15 CAN_F23R2_FB15_Msk /*!< Filter bit 15 */ |
11407 | #define CAN_F23R2_FB16_Pos (16U) |
| 11408 | #define CAN_F23R2_FB16_Pos (16U) |
11408 | #define CAN_F23R2_FB16_Msk (0x1UL << CAN_F23R2_FB16_Pos) /*!< 0x00010000 */ |
| 11409 | #define CAN_F23R2_FB16_Msk (0x1UL << CAN_F23R2_FB16_Pos) /*!< 0x00010000 */ |
11409 | #define CAN_F23R2_FB16 CAN_F23R2_FB16_Msk /*!< Filter bit 16 */ |
| 11410 | #define CAN_F23R2_FB16 CAN_F23R2_FB16_Msk /*!< Filter bit 16 */ |
11410 | #define CAN_F23R2_FB17_Pos (17U) |
| 11411 | #define CAN_F23R2_FB17_Pos (17U) |
11411 | #define CAN_F23R2_FB17_Msk (0x1UL << CAN_F23R2_FB17_Pos) /*!< 0x00020000 */ |
| 11412 | #define CAN_F23R2_FB17_Msk (0x1UL << CAN_F23R2_FB17_Pos) /*!< 0x00020000 */ |
11412 | #define CAN_F23R2_FB17 CAN_F23R2_FB17_Msk /*!< Filter bit 17 */ |
| 11413 | #define CAN_F23R2_FB17 CAN_F23R2_FB17_Msk /*!< Filter bit 17 */ |
11413 | #define CAN_F23R2_FB18_Pos (18U) |
| 11414 | #define CAN_F23R2_FB18_Pos (18U) |
11414 | #define CAN_F23R2_FB18_Msk (0x1UL << CAN_F23R2_FB18_Pos) /*!< 0x00040000 */ |
| 11415 | #define CAN_F23R2_FB18_Msk (0x1UL << CAN_F23R2_FB18_Pos) /*!< 0x00040000 */ |
11415 | #define CAN_F23R2_FB18 CAN_F23R2_FB18_Msk /*!< Filter bit 18 */ |
| 11416 | #define CAN_F23R2_FB18 CAN_F23R2_FB18_Msk /*!< Filter bit 18 */ |
11416 | #define CAN_F23R2_FB19_Pos (19U) |
| 11417 | #define CAN_F23R2_FB19_Pos (19U) |
11417 | #define CAN_F23R2_FB19_Msk (0x1UL << CAN_F23R2_FB19_Pos) /*!< 0x00080000 */ |
| 11418 | #define CAN_F23R2_FB19_Msk (0x1UL << CAN_F23R2_FB19_Pos) /*!< 0x00080000 */ |
11418 | #define CAN_F23R2_FB19 CAN_F23R2_FB19_Msk /*!< Filter bit 19 */ |
| 11419 | #define CAN_F23R2_FB19 CAN_F23R2_FB19_Msk /*!< Filter bit 19 */ |
11419 | #define CAN_F23R2_FB20_Pos (20U) |
| 11420 | #define CAN_F23R2_FB20_Pos (20U) |
11420 | #define CAN_F23R2_FB20_Msk (0x1UL << CAN_F23R2_FB20_Pos) /*!< 0x00100000 */ |
| 11421 | #define CAN_F23R2_FB20_Msk (0x1UL << CAN_F23R2_FB20_Pos) /*!< 0x00100000 */ |
11421 | #define CAN_F23R2_FB20 CAN_F23R2_FB20_Msk /*!< Filter bit 20 */ |
| 11422 | #define CAN_F23R2_FB20 CAN_F23R2_FB20_Msk /*!< Filter bit 20 */ |
11422 | #define CAN_F23R2_FB21_Pos (21U) |
| 11423 | #define CAN_F23R2_FB21_Pos (21U) |
11423 | #define CAN_F23R2_FB21_Msk (0x1UL << CAN_F23R2_FB21_Pos) /*!< 0x00200000 */ |
| 11424 | #define CAN_F23R2_FB21_Msk (0x1UL << CAN_F23R2_FB21_Pos) /*!< 0x00200000 */ |
11424 | #define CAN_F23R2_FB21 CAN_F23R2_FB21_Msk /*!< Filter bit 21 */ |
| 11425 | #define CAN_F23R2_FB21 CAN_F23R2_FB21_Msk /*!< Filter bit 21 */ |
11425 | #define CAN_F23R2_FB22_Pos (22U) |
| 11426 | #define CAN_F23R2_FB22_Pos (22U) |
11426 | #define CAN_F23R2_FB22_Msk (0x1UL << CAN_F23R2_FB22_Pos) /*!< 0x00400000 */ |
| 11427 | #define CAN_F23R2_FB22_Msk (0x1UL << CAN_F23R2_FB22_Pos) /*!< 0x00400000 */ |
11427 | #define CAN_F23R2_FB22 CAN_F23R2_FB22_Msk /*!< Filter bit 22 */ |
| 11428 | #define CAN_F23R2_FB22 CAN_F23R2_FB22_Msk /*!< Filter bit 22 */ |
11428 | #define CAN_F23R2_FB23_Pos (23U) |
| 11429 | #define CAN_F23R2_FB23_Pos (23U) |
11429 | #define CAN_F23R2_FB23_Msk (0x1UL << CAN_F23R2_FB23_Pos) /*!< 0x00800000 */ |
| 11430 | #define CAN_F23R2_FB23_Msk (0x1UL << CAN_F23R2_FB23_Pos) /*!< 0x00800000 */ |
11430 | #define CAN_F23R2_FB23 CAN_F23R2_FB23_Msk /*!< Filter bit 23 */ |
| 11431 | #define CAN_F23R2_FB23 CAN_F23R2_FB23_Msk /*!< Filter bit 23 */ |
11431 | #define CAN_F23R2_FB24_Pos (24U) |
| 11432 | #define CAN_F23R2_FB24_Pos (24U) |
11432 | #define CAN_F23R2_FB24_Msk (0x1UL << CAN_F23R2_FB24_Pos) /*!< 0x01000000 */ |
| 11433 | #define CAN_F23R2_FB24_Msk (0x1UL << CAN_F23R2_FB24_Pos) /*!< 0x01000000 */ |
11433 | #define CAN_F23R2_FB24 CAN_F23R2_FB24_Msk /*!< Filter bit 24 */ |
| 11434 | #define CAN_F23R2_FB24 CAN_F23R2_FB24_Msk /*!< Filter bit 24 */ |
11434 | #define CAN_F23R2_FB25_Pos (25U) |
| 11435 | #define CAN_F23R2_FB25_Pos (25U) |
11435 | #define CAN_F23R2_FB25_Msk (0x1UL << CAN_F23R2_FB25_Pos) /*!< 0x02000000 */ |
| 11436 | #define CAN_F23R2_FB25_Msk (0x1UL << CAN_F23R2_FB25_Pos) /*!< 0x02000000 */ |
11436 | #define CAN_F23R2_FB25 CAN_F23R2_FB25_Msk /*!< Filter bit 25 */ |
| 11437 | #define CAN_F23R2_FB25 CAN_F23R2_FB25_Msk /*!< Filter bit 25 */ |
11437 | #define CAN_F23R2_FB26_Pos (26U) |
| 11438 | #define CAN_F23R2_FB26_Pos (26U) |
11438 | #define CAN_F23R2_FB26_Msk (0x1UL << CAN_F23R2_FB26_Pos) /*!< 0x04000000 */ |
| 11439 | #define CAN_F23R2_FB26_Msk (0x1UL << CAN_F23R2_FB26_Pos) /*!< 0x04000000 */ |
11439 | #define CAN_F23R2_FB26 CAN_F23R2_FB26_Msk /*!< Filter bit 26 */ |
| 11440 | #define CAN_F23R2_FB26 CAN_F23R2_FB26_Msk /*!< Filter bit 26 */ |
11440 | #define CAN_F23R2_FB27_Pos (27U) |
| 11441 | #define CAN_F23R2_FB27_Pos (27U) |
11441 | #define CAN_F23R2_FB27_Msk (0x1UL << CAN_F23R2_FB27_Pos) /*!< 0x08000000 */ |
| 11442 | #define CAN_F23R2_FB27_Msk (0x1UL << CAN_F23R2_FB27_Pos) /*!< 0x08000000 */ |
11442 | #define CAN_F23R2_FB27 CAN_F23R2_FB27_Msk /*!< Filter bit 27 */ |
| 11443 | #define CAN_F23R2_FB27 CAN_F23R2_FB27_Msk /*!< Filter bit 27 */ |
11443 | #define CAN_F23R2_FB28_Pos (28U) |
| 11444 | #define CAN_F23R2_FB28_Pos (28U) |
11444 | #define CAN_F23R2_FB28_Msk (0x1UL << CAN_F23R2_FB28_Pos) /*!< 0x10000000 */ |
| 11445 | #define CAN_F23R2_FB28_Msk (0x1UL << CAN_F23R2_FB28_Pos) /*!< 0x10000000 */ |
11445 | #define CAN_F23R2_FB28 CAN_F23R2_FB28_Msk /*!< Filter bit 28 */ |
| 11446 | #define CAN_F23R2_FB28 CAN_F23R2_FB28_Msk /*!< Filter bit 28 */ |
11446 | #define CAN_F23R2_FB29_Pos (29U) |
| 11447 | #define CAN_F23R2_FB29_Pos (29U) |
11447 | #define CAN_F23R2_FB29_Msk (0x1UL << CAN_F23R2_FB29_Pos) /*!< 0x20000000 */ |
| 11448 | #define CAN_F23R2_FB29_Msk (0x1UL << CAN_F23R2_FB29_Pos) /*!< 0x20000000 */ |
11448 | #define CAN_F23R2_FB29 CAN_F23R2_FB29_Msk /*!< Filter bit 29 */ |
| 11449 | #define CAN_F23R2_FB29 CAN_F23R2_FB29_Msk /*!< Filter bit 29 */ |
11449 | #define CAN_F23R2_FB30_Pos (30U) |
| 11450 | #define CAN_F23R2_FB30_Pos (30U) |
11450 | #define CAN_F23R2_FB30_Msk (0x1UL << CAN_F23R2_FB30_Pos) /*!< 0x40000000 */ |
| 11451 | #define CAN_F23R2_FB30_Msk (0x1UL << CAN_F23R2_FB30_Pos) /*!< 0x40000000 */ |
11451 | #define CAN_F23R2_FB30 CAN_F23R2_FB30_Msk /*!< Filter bit 30 */ |
| 11452 | #define CAN_F23R2_FB30 CAN_F23R2_FB30_Msk /*!< Filter bit 30 */ |
11452 | #define CAN_F23R2_FB31_Pos (31U) |
| 11453 | #define CAN_F23R2_FB31_Pos (31U) |
11453 | #define CAN_F23R2_FB31_Msk (0x1UL << CAN_F23R2_FB31_Pos) /*!< 0x80000000 */ |
| 11454 | #define CAN_F23R2_FB31_Msk (0x1UL << CAN_F23R2_FB31_Pos) /*!< 0x80000000 */ |
11454 | #define CAN_F23R2_FB31 CAN_F23R2_FB31_Msk /*!< Filter bit 31 */ |
| 11455 | #define CAN_F23R2_FB31 CAN_F23R2_FB31_Msk /*!< Filter bit 31 */ |
11455 | |
| 11456 | 11456 | /******************* Bit definition for CAN_F24R2 register ******************/ |
|
| 11457 | /******************* Bit definition for CAN_F24R2 register ******************/ |
11457 | #define CAN_F24R2_FB0_Pos (0U) |
| 11458 | #define CAN_F24R2_FB0_Pos (0U) |
11458 | #define CAN_F24R2_FB0_Msk (0x1UL << CAN_F24R2_FB0_Pos) /*!< 0x00000001 */ |
| 11459 | #define CAN_F24R2_FB0_Msk (0x1UL << CAN_F24R2_FB0_Pos) /*!< 0x00000001 */ |
11459 | #define CAN_F24R2_FB0 CAN_F24R2_FB0_Msk /*!< Filter bit 0 */ |
| 11460 | #define CAN_F24R2_FB0 CAN_F24R2_FB0_Msk /*!< Filter bit 0 */ |
11460 | #define CAN_F24R2_FB1_Pos (1U) |
| 11461 | #define CAN_F24R2_FB1_Pos (1U) |
11461 | #define CAN_F24R2_FB1_Msk (0x1UL << CAN_F24R2_FB1_Pos) /*!< 0x00000002 */ |
| 11462 | #define CAN_F24R2_FB1_Msk (0x1UL << CAN_F24R2_FB1_Pos) /*!< 0x00000002 */ |
11462 | #define CAN_F24R2_FB1 CAN_F24R2_FB1_Msk /*!< Filter bit 1 */ |
| 11463 | #define CAN_F24R2_FB1 CAN_F24R2_FB1_Msk /*!< Filter bit 1 */ |
11463 | #define CAN_F24R2_FB2_Pos (2U) |
| 11464 | #define CAN_F24R2_FB2_Pos (2U) |
11464 | #define CAN_F24R2_FB2_Msk (0x1UL << CAN_F24R2_FB2_Pos) /*!< 0x00000004 */ |
| 11465 | #define CAN_F24R2_FB2_Msk (0x1UL << CAN_F24R2_FB2_Pos) /*!< 0x00000004 */ |
11465 | #define CAN_F24R2_FB2 CAN_F24R2_FB2_Msk /*!< Filter bit 2 */ |
| 11466 | #define CAN_F24R2_FB2 CAN_F24R2_FB2_Msk /*!< Filter bit 2 */ |
11466 | #define CAN_F24R2_FB3_Pos (3U) |
| 11467 | #define CAN_F24R2_FB3_Pos (3U) |
11467 | #define CAN_F24R2_FB3_Msk (0x1UL << CAN_F24R2_FB3_Pos) /*!< 0x00000008 */ |
| 11468 | #define CAN_F24R2_FB3_Msk (0x1UL << CAN_F24R2_FB3_Pos) /*!< 0x00000008 */ |
11468 | #define CAN_F24R2_FB3 CAN_F24R2_FB3_Msk /*!< Filter bit 3 */ |
| 11469 | #define CAN_F24R2_FB3 CAN_F24R2_FB3_Msk /*!< Filter bit 3 */ |
11469 | #define CAN_F24R2_FB4_Pos (4U) |
| 11470 | #define CAN_F24R2_FB4_Pos (4U) |
11470 | #define CAN_F24R2_FB4_Msk (0x1UL << CAN_F24R2_FB4_Pos) /*!< 0x00000010 */ |
| 11471 | #define CAN_F24R2_FB4_Msk (0x1UL << CAN_F24R2_FB4_Pos) /*!< 0x00000010 */ |
11471 | #define CAN_F24R2_FB4 CAN_F24R2_FB4_Msk /*!< Filter bit 4 */ |
| 11472 | #define CAN_F24R2_FB4 CAN_F24R2_FB4_Msk /*!< Filter bit 4 */ |
11472 | #define CAN_F24R2_FB5_Pos (5U) |
| 11473 | #define CAN_F24R2_FB5_Pos (5U) |
11473 | #define CAN_F24R2_FB5_Msk (0x1UL << CAN_F24R2_FB5_Pos) /*!< 0x00000020 */ |
| 11474 | #define CAN_F24R2_FB5_Msk (0x1UL << CAN_F24R2_FB5_Pos) /*!< 0x00000020 */ |
11474 | #define CAN_F24R2_FB5 CAN_F24R2_FB5_Msk /*!< Filter bit 5 */ |
| 11475 | #define CAN_F24R2_FB5 CAN_F24R2_FB5_Msk /*!< Filter bit 5 */ |
11475 | #define CAN_F24R2_FB6_Pos (6U) |
| 11476 | #define CAN_F24R2_FB6_Pos (6U) |
11476 | #define CAN_F24R2_FB6_Msk (0x1UL << CAN_F24R2_FB6_Pos) /*!< 0x00000040 */ |
| 11477 | #define CAN_F24R2_FB6_Msk (0x1UL << CAN_F24R2_FB6_Pos) /*!< 0x00000040 */ |
11477 | #define CAN_F24R2_FB6 CAN_F24R2_FB6_Msk /*!< Filter bit 6 */ |
| 11478 | #define CAN_F24R2_FB6 CAN_F24R2_FB6_Msk /*!< Filter bit 6 */ |
11478 | #define CAN_F24R2_FB7_Pos (7U) |
| 11479 | #define CAN_F24R2_FB7_Pos (7U) |
11479 | #define CAN_F24R2_FB7_Msk (0x1UL << CAN_F24R2_FB7_Pos) /*!< 0x00000080 */ |
| 11480 | #define CAN_F24R2_FB7_Msk (0x1UL << CAN_F24R2_FB7_Pos) /*!< 0x00000080 */ |
11480 | #define CAN_F24R2_FB7 CAN_F24R2_FB7_Msk /*!< Filter bit 7 */ |
| 11481 | #define CAN_F24R2_FB7 CAN_F24R2_FB7_Msk /*!< Filter bit 7 */ |
11481 | #define CAN_F24R2_FB8_Pos (8U) |
| 11482 | #define CAN_F24R2_FB8_Pos (8U) |
11482 | #define CAN_F24R2_FB8_Msk (0x1UL << CAN_F24R2_FB8_Pos) /*!< 0x00000100 */ |
| 11483 | #define CAN_F24R2_FB8_Msk (0x1UL << CAN_F24R2_FB8_Pos) /*!< 0x00000100 */ |
11483 | #define CAN_F24R2_FB8 CAN_F24R2_FB8_Msk /*!< Filter bit 8 */ |
| 11484 | #define CAN_F24R2_FB8 CAN_F24R2_FB8_Msk /*!< Filter bit 8 */ |
11484 | #define CAN_F24R2_FB9_Pos (9U) |
| 11485 | #define CAN_F24R2_FB9_Pos (9U) |
11485 | #define CAN_F24R2_FB9_Msk (0x1UL << CAN_F24R2_FB9_Pos) /*!< 0x00000200 */ |
| 11486 | #define CAN_F24R2_FB9_Msk (0x1UL << CAN_F24R2_FB9_Pos) /*!< 0x00000200 */ |
11486 | #define CAN_F24R2_FB9 CAN_F24R2_FB9_Msk /*!< Filter bit 9 */ |
| 11487 | #define CAN_F24R2_FB9 CAN_F24R2_FB9_Msk /*!< Filter bit 9 */ |
11487 | #define CAN_F24R2_FB10_Pos (10U) |
| 11488 | #define CAN_F24R2_FB10_Pos (10U) |
11488 | #define CAN_F24R2_FB10_Msk (0x1UL << CAN_F24R2_FB10_Pos) /*!< 0x00000400 */ |
| 11489 | #define CAN_F24R2_FB10_Msk (0x1UL << CAN_F24R2_FB10_Pos) /*!< 0x00000400 */ |
11489 | #define CAN_F24R2_FB10 CAN_F24R2_FB10_Msk /*!< Filter bit 10 */ |
| 11490 | #define CAN_F24R2_FB10 CAN_F24R2_FB10_Msk /*!< Filter bit 10 */ |
11490 | #define CAN_F24R2_FB11_Pos (11U) |
| 11491 | #define CAN_F24R2_FB11_Pos (11U) |
11491 | #define CAN_F24R2_FB11_Msk (0x1UL << CAN_F24R2_FB11_Pos) /*!< 0x00000800 */ |
| 11492 | #define CAN_F24R2_FB11_Msk (0x1UL << CAN_F24R2_FB11_Pos) /*!< 0x00000800 */ |
11492 | #define CAN_F24R2_FB11 CAN_F24R2_FB11_Msk /*!< Filter bit 11 */ |
| 11493 | #define CAN_F24R2_FB11 CAN_F24R2_FB11_Msk /*!< Filter bit 11 */ |
11493 | #define CAN_F24R2_FB12_Pos (12U) |
| 11494 | #define CAN_F24R2_FB12_Pos (12U) |
11494 | #define CAN_F24R2_FB12_Msk (0x1UL << CAN_F24R2_FB12_Pos) /*!< 0x00001000 */ |
| 11495 | #define CAN_F24R2_FB12_Msk (0x1UL << CAN_F24R2_FB12_Pos) /*!< 0x00001000 */ |
11495 | #define CAN_F24R2_FB12 CAN_F24R2_FB12_Msk /*!< Filter bit 12 */ |
| 11496 | #define CAN_F24R2_FB12 CAN_F24R2_FB12_Msk /*!< Filter bit 12 */ |
11496 | #define CAN_F24R2_FB13_Pos (13U) |
| 11497 | #define CAN_F24R2_FB13_Pos (13U) |
11497 | #define CAN_F24R2_FB13_Msk (0x1UL << CAN_F24R2_FB13_Pos) /*!< 0x00002000 */ |
| 11498 | #define CAN_F24R2_FB13_Msk (0x1UL << CAN_F24R2_FB13_Pos) /*!< 0x00002000 */ |
11498 | #define CAN_F24R2_FB13 CAN_F24R2_FB13_Msk /*!< Filter bit 13 */ |
| 11499 | #define CAN_F24R2_FB13 CAN_F24R2_FB13_Msk /*!< Filter bit 13 */ |
11499 | #define CAN_F24R2_FB14_Pos (14U) |
| 11500 | #define CAN_F24R2_FB14_Pos (14U) |
11500 | #define CAN_F24R2_FB14_Msk (0x1UL << CAN_F24R2_FB14_Pos) /*!< 0x00004000 */ |
| 11501 | #define CAN_F24R2_FB14_Msk (0x1UL << CAN_F24R2_FB14_Pos) /*!< 0x00004000 */ |
11501 | #define CAN_F24R2_FB14 CAN_F24R2_FB14_Msk /*!< Filter bit 14 */ |
| 11502 | #define CAN_F24R2_FB14 CAN_F24R2_FB14_Msk /*!< Filter bit 14 */ |
11502 | #define CAN_F24R2_FB15_Pos (15U) |
| 11503 | #define CAN_F24R2_FB15_Pos (15U) |
11503 | #define CAN_F24R2_FB15_Msk (0x1UL << CAN_F24R2_FB15_Pos) /*!< 0x00008000 */ |
| 11504 | #define CAN_F24R2_FB15_Msk (0x1UL << CAN_F24R2_FB15_Pos) /*!< 0x00008000 */ |
11504 | #define CAN_F24R2_FB15 CAN_F24R2_FB15_Msk /*!< Filter bit 15 */ |
| 11505 | #define CAN_F24R2_FB15 CAN_F24R2_FB15_Msk /*!< Filter bit 15 */ |
11505 | #define CAN_F24R2_FB16_Pos (16U) |
| 11506 | #define CAN_F24R2_FB16_Pos (16U) |
11506 | #define CAN_F24R2_FB16_Msk (0x1UL << CAN_F24R2_FB16_Pos) /*!< 0x00010000 */ |
| 11507 | #define CAN_F24R2_FB16_Msk (0x1UL << CAN_F24R2_FB16_Pos) /*!< 0x00010000 */ |
11507 | #define CAN_F24R2_FB16 CAN_F24R2_FB16_Msk /*!< Filter bit 16 */ |
| 11508 | #define CAN_F24R2_FB16 CAN_F24R2_FB16_Msk /*!< Filter bit 16 */ |
11508 | #define CAN_F24R2_FB17_Pos (17U) |
| 11509 | #define CAN_F24R2_FB17_Pos (17U) |
11509 | #define CAN_F24R2_FB17_Msk (0x1UL << CAN_F24R2_FB17_Pos) /*!< 0x00020000 */ |
| 11510 | #define CAN_F24R2_FB17_Msk (0x1UL << CAN_F24R2_FB17_Pos) /*!< 0x00020000 */ |
11510 | #define CAN_F24R2_FB17 CAN_F24R2_FB17_Msk /*!< Filter bit 17 */ |
| 11511 | #define CAN_F24R2_FB17 CAN_F24R2_FB17_Msk /*!< Filter bit 17 */ |
11511 | #define CAN_F24R2_FB18_Pos (18U) |
| 11512 | #define CAN_F24R2_FB18_Pos (18U) |
11512 | #define CAN_F24R2_FB18_Msk (0x1UL << CAN_F24R2_FB18_Pos) /*!< 0x00040000 */ |
| 11513 | #define CAN_F24R2_FB18_Msk (0x1UL << CAN_F24R2_FB18_Pos) /*!< 0x00040000 */ |
11513 | #define CAN_F24R2_FB18 CAN_F24R2_FB18_Msk /*!< Filter bit 18 */ |
| 11514 | #define CAN_F24R2_FB18 CAN_F24R2_FB18_Msk /*!< Filter bit 18 */ |
11514 | #define CAN_F24R2_FB19_Pos (19U) |
| 11515 | #define CAN_F24R2_FB19_Pos (19U) |
11515 | #define CAN_F24R2_FB19_Msk (0x1UL << CAN_F24R2_FB19_Pos) /*!< 0x00080000 */ |
| 11516 | #define CAN_F24R2_FB19_Msk (0x1UL << CAN_F24R2_FB19_Pos) /*!< 0x00080000 */ |
11516 | #define CAN_F24R2_FB19 CAN_F24R2_FB19_Msk /*!< Filter bit 19 */ |
| 11517 | #define CAN_F24R2_FB19 CAN_F24R2_FB19_Msk /*!< Filter bit 19 */ |
11517 | #define CAN_F24R2_FB20_Pos (20U) |
| 11518 | #define CAN_F24R2_FB20_Pos (20U) |
11518 | #define CAN_F24R2_FB20_Msk (0x1UL << CAN_F24R2_FB20_Pos) /*!< 0x00100000 */ |
| 11519 | #define CAN_F24R2_FB20_Msk (0x1UL << CAN_F24R2_FB20_Pos) /*!< 0x00100000 */ |
11519 | #define CAN_F24R2_FB20 CAN_F24R2_FB20_Msk /*!< Filter bit 20 */ |
| 11520 | #define CAN_F24R2_FB20 CAN_F24R2_FB20_Msk /*!< Filter bit 20 */ |
11520 | #define CAN_F24R2_FB21_Pos (21U) |
| 11521 | #define CAN_F24R2_FB21_Pos (21U) |
11521 | #define CAN_F24R2_FB21_Msk (0x1UL << CAN_F24R2_FB21_Pos) /*!< 0x00200000 */ |
| 11522 | #define CAN_F24R2_FB21_Msk (0x1UL << CAN_F24R2_FB21_Pos) /*!< 0x00200000 */ |
11522 | #define CAN_F24R2_FB21 CAN_F24R2_FB21_Msk /*!< Filter bit 21 */ |
| 11523 | #define CAN_F24R2_FB21 CAN_F24R2_FB21_Msk /*!< Filter bit 21 */ |
11523 | #define CAN_F24R2_FB22_Pos (22U) |
| 11524 | #define CAN_F24R2_FB22_Pos (22U) |
11524 | #define CAN_F24R2_FB22_Msk (0x1UL << CAN_F24R2_FB22_Pos) /*!< 0x00400000 */ |
| 11525 | #define CAN_F24R2_FB22_Msk (0x1UL << CAN_F24R2_FB22_Pos) /*!< 0x00400000 */ |
11525 | #define CAN_F24R2_FB22 CAN_F24R2_FB22_Msk /*!< Filter bit 22 */ |
| 11526 | #define CAN_F24R2_FB22 CAN_F24R2_FB22_Msk /*!< Filter bit 22 */ |
11526 | #define CAN_F24R2_FB23_Pos (23U) |
| 11527 | #define CAN_F24R2_FB23_Pos (23U) |
11527 | #define CAN_F24R2_FB23_Msk (0x1UL << CAN_F24R2_FB23_Pos) /*!< 0x00800000 */ |
| 11528 | #define CAN_F24R2_FB23_Msk (0x1UL << CAN_F24R2_FB23_Pos) /*!< 0x00800000 */ |
11528 | #define CAN_F24R2_FB23 CAN_F24R2_FB23_Msk /*!< Filter bit 23 */ |
| 11529 | #define CAN_F24R2_FB23 CAN_F24R2_FB23_Msk /*!< Filter bit 23 */ |
11529 | #define CAN_F24R2_FB24_Pos (24U) |
| 11530 | #define CAN_F24R2_FB24_Pos (24U) |
11530 | #define CAN_F24R2_FB24_Msk (0x1UL << CAN_F24R2_FB24_Pos) /*!< 0x01000000 */ |
| 11531 | #define CAN_F24R2_FB24_Msk (0x1UL << CAN_F24R2_FB24_Pos) /*!< 0x01000000 */ |
11531 | #define CAN_F24R2_FB24 CAN_F24R2_FB24_Msk /*!< Filter bit 24 */ |
| 11532 | #define CAN_F24R2_FB24 CAN_F24R2_FB24_Msk /*!< Filter bit 24 */ |
11532 | #define CAN_F24R2_FB25_Pos (25U) |
| 11533 | #define CAN_F24R2_FB25_Pos (25U) |
11533 | #define CAN_F24R2_FB25_Msk (0x1UL << CAN_F24R2_FB25_Pos) /*!< 0x02000000 */ |
| 11534 | #define CAN_F24R2_FB25_Msk (0x1UL << CAN_F24R2_FB25_Pos) /*!< 0x02000000 */ |
11534 | #define CAN_F24R2_FB25 CAN_F24R2_FB25_Msk /*!< Filter bit 25 */ |
| 11535 | #define CAN_F24R2_FB25 CAN_F24R2_FB25_Msk /*!< Filter bit 25 */ |
11535 | #define CAN_F24R2_FB26_Pos (26U) |
| 11536 | #define CAN_F24R2_FB26_Pos (26U) |
11536 | #define CAN_F24R2_FB26_Msk (0x1UL << CAN_F24R2_FB26_Pos) /*!< 0x04000000 */ |
| 11537 | #define CAN_F24R2_FB26_Msk (0x1UL << CAN_F24R2_FB26_Pos) /*!< 0x04000000 */ |
11537 | #define CAN_F24R2_FB26 CAN_F24R2_FB26_Msk /*!< Filter bit 26 */ |
| 11538 | #define CAN_F24R2_FB26 CAN_F24R2_FB26_Msk /*!< Filter bit 26 */ |
11538 | #define CAN_F24R2_FB27_Pos (27U) |
| 11539 | #define CAN_F24R2_FB27_Pos (27U) |
11539 | #define CAN_F24R2_FB27_Msk (0x1UL << CAN_F24R2_FB27_Pos) /*!< 0x08000000 */ |
| 11540 | #define CAN_F24R2_FB27_Msk (0x1UL << CAN_F24R2_FB27_Pos) /*!< 0x08000000 */ |
11540 | #define CAN_F24R2_FB27 CAN_F24R2_FB27_Msk /*!< Filter bit 27 */ |
| 11541 | #define CAN_F24R2_FB27 CAN_F24R2_FB27_Msk /*!< Filter bit 27 */ |
11541 | #define CAN_F24R2_FB28_Pos (28U) |
| 11542 | #define CAN_F24R2_FB28_Pos (28U) |
11542 | #define CAN_F24R2_FB28_Msk (0x1UL << CAN_F24R2_FB28_Pos) /*!< 0x10000000 */ |
| 11543 | #define CAN_F24R2_FB28_Msk (0x1UL << CAN_F24R2_FB28_Pos) /*!< 0x10000000 */ |
11543 | #define CAN_F24R2_FB28 CAN_F24R2_FB28_Msk /*!< Filter bit 28 */ |
| 11544 | #define CAN_F24R2_FB28 CAN_F24R2_FB28_Msk /*!< Filter bit 28 */ |
11544 | #define CAN_F24R2_FB29_Pos (29U) |
| 11545 | #define CAN_F24R2_FB29_Pos (29U) |
11545 | #define CAN_F24R2_FB29_Msk (0x1UL << CAN_F24R2_FB29_Pos) /*!< 0x20000000 */ |
| 11546 | #define CAN_F24R2_FB29_Msk (0x1UL << CAN_F24R2_FB29_Pos) /*!< 0x20000000 */ |
11546 | #define CAN_F24R2_FB29 CAN_F24R2_FB29_Msk /*!< Filter bit 29 */ |
| 11547 | #define CAN_F24R2_FB29 CAN_F24R2_FB29_Msk /*!< Filter bit 29 */ |
11547 | #define CAN_F24R2_FB30_Pos (30U) |
| 11548 | #define CAN_F24R2_FB30_Pos (30U) |
11548 | #define CAN_F24R2_FB30_Msk (0x1UL << CAN_F24R2_FB30_Pos) /*!< 0x40000000 */ |
| 11549 | #define CAN_F24R2_FB30_Msk (0x1UL << CAN_F24R2_FB30_Pos) /*!< 0x40000000 */ |
11549 | #define CAN_F24R2_FB30 CAN_F24R2_FB30_Msk /*!< Filter bit 30 */ |
| 11550 | #define CAN_F24R2_FB30 CAN_F24R2_FB30_Msk /*!< Filter bit 30 */ |
11550 | #define CAN_F24R2_FB31_Pos (31U) |
| 11551 | #define CAN_F24R2_FB31_Pos (31U) |
11551 | #define CAN_F24R2_FB31_Msk (0x1UL << CAN_F24R2_FB31_Pos) /*!< 0x80000000 */ |
| 11552 | #define CAN_F24R2_FB31_Msk (0x1UL << CAN_F24R2_FB31_Pos) /*!< 0x80000000 */ |
11552 | #define CAN_F24R2_FB31 CAN_F24R2_FB31_Msk /*!< Filter bit 31 */ |
| 11553 | #define CAN_F24R2_FB31 CAN_F24R2_FB31_Msk /*!< Filter bit 31 */ |
11553 | |
| 11554 | 11554 | /******************* Bit definition for CAN_F25R2 register ******************/ |
|
| 11555 | /******************* Bit definition for CAN_F25R2 register ******************/ |
11555 | #define CAN_F25R2_FB0_Pos (0U) |
| 11556 | #define CAN_F25R2_FB0_Pos (0U) |
11556 | #define CAN_F25R2_FB0_Msk (0x1UL << CAN_F25R2_FB0_Pos) /*!< 0x00000001 */ |
| 11557 | #define CAN_F25R2_FB0_Msk (0x1UL << CAN_F25R2_FB0_Pos) /*!< 0x00000001 */ |
11557 | #define CAN_F25R2_FB0 CAN_F25R2_FB0_Msk /*!< Filter bit 0 */ |
| 11558 | #define CAN_F25R2_FB0 CAN_F25R2_FB0_Msk /*!< Filter bit 0 */ |
11558 | #define CAN_F25R2_FB1_Pos (1U) |
| 11559 | #define CAN_F25R2_FB1_Pos (1U) |
11559 | #define CAN_F25R2_FB1_Msk (0x1UL << CAN_F25R2_FB1_Pos) /*!< 0x00000002 */ |
| 11560 | #define CAN_F25R2_FB1_Msk (0x1UL << CAN_F25R2_FB1_Pos) /*!< 0x00000002 */ |
11560 | #define CAN_F25R2_FB1 CAN_F25R2_FB1_Msk /*!< Filter bit 1 */ |
| 11561 | #define CAN_F25R2_FB1 CAN_F25R2_FB1_Msk /*!< Filter bit 1 */ |
11561 | #define CAN_F25R2_FB2_Pos (2U) |
| 11562 | #define CAN_F25R2_FB2_Pos (2U) |
11562 | #define CAN_F25R2_FB2_Msk (0x1UL << CAN_F25R2_FB2_Pos) /*!< 0x00000004 */ |
| 11563 | #define CAN_F25R2_FB2_Msk (0x1UL << CAN_F25R2_FB2_Pos) /*!< 0x00000004 */ |
11563 | #define CAN_F25R2_FB2 CAN_F25R2_FB2_Msk /*!< Filter bit 2 */ |
| 11564 | #define CAN_F25R2_FB2 CAN_F25R2_FB2_Msk /*!< Filter bit 2 */ |
11564 | #define CAN_F25R2_FB3_Pos (3U) |
| 11565 | #define CAN_F25R2_FB3_Pos (3U) |
11565 | #define CAN_F25R2_FB3_Msk (0x1UL << CAN_F25R2_FB3_Pos) /*!< 0x00000008 */ |
| 11566 | #define CAN_F25R2_FB3_Msk (0x1UL << CAN_F25R2_FB3_Pos) /*!< 0x00000008 */ |
11566 | #define CAN_F25R2_FB3 CAN_F25R2_FB3_Msk /*!< Filter bit 3 */ |
| 11567 | #define CAN_F25R2_FB3 CAN_F25R2_FB3_Msk /*!< Filter bit 3 */ |
11567 | #define CAN_F25R2_FB4_Pos (4U) |
| 11568 | #define CAN_F25R2_FB4_Pos (4U) |
11568 | #define CAN_F25R2_FB4_Msk (0x1UL << CAN_F25R2_FB4_Pos) /*!< 0x00000010 */ |
| 11569 | #define CAN_F25R2_FB4_Msk (0x1UL << CAN_F25R2_FB4_Pos) /*!< 0x00000010 */ |
11569 | #define CAN_F25R2_FB4 CAN_F25R2_FB4_Msk /*!< Filter bit 4 */ |
| 11570 | #define CAN_F25R2_FB4 CAN_F25R2_FB4_Msk /*!< Filter bit 4 */ |
11570 | #define CAN_F25R2_FB5_Pos (5U) |
| 11571 | #define CAN_F25R2_FB5_Pos (5U) |
11571 | #define CAN_F25R2_FB5_Msk (0x1UL << CAN_F25R2_FB5_Pos) /*!< 0x00000020 */ |
| 11572 | #define CAN_F25R2_FB5_Msk (0x1UL << CAN_F25R2_FB5_Pos) /*!< 0x00000020 */ |
11572 | #define CAN_F25R2_FB5 CAN_F25R2_FB5_Msk /*!< Filter bit 5 */ |
| 11573 | #define CAN_F25R2_FB5 CAN_F25R2_FB5_Msk /*!< Filter bit 5 */ |
11573 | #define CAN_F25R2_FB6_Pos (6U) |
| 11574 | #define CAN_F25R2_FB6_Pos (6U) |
11574 | #define CAN_F25R2_FB6_Msk (0x1UL << CAN_F25R2_FB6_Pos) /*!< 0x00000040 */ |
| 11575 | #define CAN_F25R2_FB6_Msk (0x1UL << CAN_F25R2_FB6_Pos) /*!< 0x00000040 */ |
11575 | #define CAN_F25R2_FB6 CAN_F25R2_FB6_Msk /*!< Filter bit 6 */ |
| 11576 | #define CAN_F25R2_FB6 CAN_F25R2_FB6_Msk /*!< Filter bit 6 */ |
11576 | #define CAN_F25R2_FB7_Pos (7U) |
| 11577 | #define CAN_F25R2_FB7_Pos (7U) |
11577 | #define CAN_F25R2_FB7_Msk (0x1UL << CAN_F25R2_FB7_Pos) /*!< 0x00000080 */ |
| 11578 | #define CAN_F25R2_FB7_Msk (0x1UL << CAN_F25R2_FB7_Pos) /*!< 0x00000080 */ |
11578 | #define CAN_F25R2_FB7 CAN_F25R2_FB7_Msk /*!< Filter bit 7 */ |
| 11579 | #define CAN_F25R2_FB7 CAN_F25R2_FB7_Msk /*!< Filter bit 7 */ |
11579 | #define CAN_F25R2_FB8_Pos (8U) |
| 11580 | #define CAN_F25R2_FB8_Pos (8U) |
11580 | #define CAN_F25R2_FB8_Msk (0x1UL << CAN_F25R2_FB8_Pos) /*!< 0x00000100 */ |
| 11581 | #define CAN_F25R2_FB8_Msk (0x1UL << CAN_F25R2_FB8_Pos) /*!< 0x00000100 */ |
11581 | #define CAN_F25R2_FB8 CAN_F25R2_FB8_Msk /*!< Filter bit 8 */ |
| 11582 | #define CAN_F25R2_FB8 CAN_F25R2_FB8_Msk /*!< Filter bit 8 */ |
11582 | #define CAN_F25R2_FB9_Pos (9U) |
| 11583 | #define CAN_F25R2_FB9_Pos (9U) |
11583 | #define CAN_F25R2_FB9_Msk (0x1UL << CAN_F25R2_FB9_Pos) /*!< 0x00000200 */ |
| 11584 | #define CAN_F25R2_FB9_Msk (0x1UL << CAN_F25R2_FB9_Pos) /*!< 0x00000200 */ |
11584 | #define CAN_F25R2_FB9 CAN_F25R2_FB9_Msk /*!< Filter bit 9 */ |
| 11585 | #define CAN_F25R2_FB9 CAN_F25R2_FB9_Msk /*!< Filter bit 9 */ |
11585 | #define CAN_F25R2_FB10_Pos (10U) |
| 11586 | #define CAN_F25R2_FB10_Pos (10U) |
11586 | #define CAN_F25R2_FB10_Msk (0x1UL << CAN_F25R2_FB10_Pos) /*!< 0x00000400 */ |
| 11587 | #define CAN_F25R2_FB10_Msk (0x1UL << CAN_F25R2_FB10_Pos) /*!< 0x00000400 */ |
11587 | #define CAN_F25R2_FB10 CAN_F25R2_FB10_Msk /*!< Filter bit 10 */ |
| 11588 | #define CAN_F25R2_FB10 CAN_F25R2_FB10_Msk /*!< Filter bit 10 */ |
11588 | #define CAN_F25R2_FB11_Pos (11U) |
| 11589 | #define CAN_F25R2_FB11_Pos (11U) |
11589 | #define CAN_F25R2_FB11_Msk (0x1UL << CAN_F25R2_FB11_Pos) /*!< 0x00000800 */ |
| 11590 | #define CAN_F25R2_FB11_Msk (0x1UL << CAN_F25R2_FB11_Pos) /*!< 0x00000800 */ |
11590 | #define CAN_F25R2_FB11 CAN_F25R2_FB11_Msk /*!< Filter bit 11 */ |
| 11591 | #define CAN_F25R2_FB11 CAN_F25R2_FB11_Msk /*!< Filter bit 11 */ |
11591 | #define CAN_F25R2_FB12_Pos (12U) |
| 11592 | #define CAN_F25R2_FB12_Pos (12U) |
11592 | #define CAN_F25R2_FB12_Msk (0x1UL << CAN_F25R2_FB12_Pos) /*!< 0x00001000 */ |
| 11593 | #define CAN_F25R2_FB12_Msk (0x1UL << CAN_F25R2_FB12_Pos) /*!< 0x00001000 */ |
11593 | #define CAN_F25R2_FB12 CAN_F25R2_FB12_Msk /*!< Filter bit 12 */ |
| 11594 | #define CAN_F25R2_FB12 CAN_F25R2_FB12_Msk /*!< Filter bit 12 */ |
11594 | #define CAN_F25R2_FB13_Pos (13U) |
| 11595 | #define CAN_F25R2_FB13_Pos (13U) |
11595 | #define CAN_F25R2_FB13_Msk (0x1UL << CAN_F25R2_FB13_Pos) /*!< 0x00002000 */ |
| 11596 | #define CAN_F25R2_FB13_Msk (0x1UL << CAN_F25R2_FB13_Pos) /*!< 0x00002000 */ |
11596 | #define CAN_F25R2_FB13 CAN_F25R2_FB13_Msk /*!< Filter bit 13 */ |
| 11597 | #define CAN_F25R2_FB13 CAN_F25R2_FB13_Msk /*!< Filter bit 13 */ |
11597 | #define CAN_F25R2_FB14_Pos (14U) |
| 11598 | #define CAN_F25R2_FB14_Pos (14U) |
11598 | #define CAN_F25R2_FB14_Msk (0x1UL << CAN_F25R2_FB14_Pos) /*!< 0x00004000 */ |
| 11599 | #define CAN_F25R2_FB14_Msk (0x1UL << CAN_F25R2_FB14_Pos) /*!< 0x00004000 */ |
11599 | #define CAN_F25R2_FB14 CAN_F25R2_FB14_Msk /*!< Filter bit 14 */ |
| 11600 | #define CAN_F25R2_FB14 CAN_F25R2_FB14_Msk /*!< Filter bit 14 */ |
11600 | #define CAN_F25R2_FB15_Pos (15U) |
| 11601 | #define CAN_F25R2_FB15_Pos (15U) |
11601 | #define CAN_F25R2_FB15_Msk (0x1UL << CAN_F25R2_FB15_Pos) /*!< 0x00008000 */ |
| 11602 | #define CAN_F25R2_FB15_Msk (0x1UL << CAN_F25R2_FB15_Pos) /*!< 0x00008000 */ |
11602 | #define CAN_F25R2_FB15 CAN_F25R2_FB15_Msk /*!< Filter bit 15 */ |
| 11603 | #define CAN_F25R2_FB15 CAN_F25R2_FB15_Msk /*!< Filter bit 15 */ |
11603 | #define CAN_F25R2_FB16_Pos (16U) |
| 11604 | #define CAN_F25R2_FB16_Pos (16U) |
11604 | #define CAN_F25R2_FB16_Msk (0x1UL << CAN_F25R2_FB16_Pos) /*!< 0x00010000 */ |
| 11605 | #define CAN_F25R2_FB16_Msk (0x1UL << CAN_F25R2_FB16_Pos) /*!< 0x00010000 */ |
11605 | #define CAN_F25R2_FB16 CAN_F25R2_FB16_Msk /*!< Filter bit 16 */ |
| 11606 | #define CAN_F25R2_FB16 CAN_F25R2_FB16_Msk /*!< Filter bit 16 */ |
11606 | #define CAN_F25R2_FB17_Pos (17U) |
| 11607 | #define CAN_F25R2_FB17_Pos (17U) |
11607 | #define CAN_F25R2_FB17_Msk (0x1UL << CAN_F25R2_FB17_Pos) /*!< 0x00020000 */ |
| 11608 | #define CAN_F25R2_FB17_Msk (0x1UL << CAN_F25R2_FB17_Pos) /*!< 0x00020000 */ |
11608 | #define CAN_F25R2_FB17 CAN_F25R2_FB17_Msk /*!< Filter bit 17 */ |
| 11609 | #define CAN_F25R2_FB17 CAN_F25R2_FB17_Msk /*!< Filter bit 17 */ |
11609 | #define CAN_F25R2_FB18_Pos (18U) |
| 11610 | #define CAN_F25R2_FB18_Pos (18U) |
11610 | #define CAN_F25R2_FB18_Msk (0x1UL << CAN_F25R2_FB18_Pos) /*!< 0x00040000 */ |
| 11611 | #define CAN_F25R2_FB18_Msk (0x1UL << CAN_F25R2_FB18_Pos) /*!< 0x00040000 */ |
11611 | #define CAN_F25R2_FB18 CAN_F25R2_FB18_Msk /*!< Filter bit 18 */ |
| 11612 | #define CAN_F25R2_FB18 CAN_F25R2_FB18_Msk /*!< Filter bit 18 */ |
11612 | #define CAN_F25R2_FB19_Pos (19U) |
| 11613 | #define CAN_F25R2_FB19_Pos (19U) |
11613 | #define CAN_F25R2_FB19_Msk (0x1UL << CAN_F25R2_FB19_Pos) /*!< 0x00080000 */ |
| 11614 | #define CAN_F25R2_FB19_Msk (0x1UL << CAN_F25R2_FB19_Pos) /*!< 0x00080000 */ |
11614 | #define CAN_F25R2_FB19 CAN_F25R2_FB19_Msk /*!< Filter bit 19 */ |
| 11615 | #define CAN_F25R2_FB19 CAN_F25R2_FB19_Msk /*!< Filter bit 19 */ |
11615 | #define CAN_F25R2_FB20_Pos (20U) |
| 11616 | #define CAN_F25R2_FB20_Pos (20U) |
11616 | #define CAN_F25R2_FB20_Msk (0x1UL << CAN_F25R2_FB20_Pos) /*!< 0x00100000 */ |
| 11617 | #define CAN_F25R2_FB20_Msk (0x1UL << CAN_F25R2_FB20_Pos) /*!< 0x00100000 */ |
11617 | #define CAN_F25R2_FB20 CAN_F25R2_FB20_Msk /*!< Filter bit 20 */ |
| 11618 | #define CAN_F25R2_FB20 CAN_F25R2_FB20_Msk /*!< Filter bit 20 */ |
11618 | #define CAN_F25R2_FB21_Pos (21U) |
| 11619 | #define CAN_F25R2_FB21_Pos (21U) |
11619 | #define CAN_F25R2_FB21_Msk (0x1UL << CAN_F25R2_FB21_Pos) /*!< 0x00200000 */ |
| 11620 | #define CAN_F25R2_FB21_Msk (0x1UL << CAN_F25R2_FB21_Pos) /*!< 0x00200000 */ |
11620 | #define CAN_F25R2_FB21 CAN_F25R2_FB21_Msk /*!< Filter bit 21 */ |
| 11621 | #define CAN_F25R2_FB21 CAN_F25R2_FB21_Msk /*!< Filter bit 21 */ |
11621 | #define CAN_F25R2_FB22_Pos (22U) |
| 11622 | #define CAN_F25R2_FB22_Pos (22U) |
11622 | #define CAN_F25R2_FB22_Msk (0x1UL << CAN_F25R2_FB22_Pos) /*!< 0x00400000 */ |
| 11623 | #define CAN_F25R2_FB22_Msk (0x1UL << CAN_F25R2_FB22_Pos) /*!< 0x00400000 */ |
11623 | #define CAN_F25R2_FB22 CAN_F25R2_FB22_Msk /*!< Filter bit 22 */ |
| 11624 | #define CAN_F25R2_FB22 CAN_F25R2_FB22_Msk /*!< Filter bit 22 */ |
11624 | #define CAN_F25R2_FB23_Pos (23U) |
| 11625 | #define CAN_F25R2_FB23_Pos (23U) |
11625 | #define CAN_F25R2_FB23_Msk (0x1UL << CAN_F25R2_FB23_Pos) /*!< 0x00800000 */ |
| 11626 | #define CAN_F25R2_FB23_Msk (0x1UL << CAN_F25R2_FB23_Pos) /*!< 0x00800000 */ |
11626 | #define CAN_F25R2_FB23 CAN_F25R2_FB23_Msk /*!< Filter bit 23 */ |
| 11627 | #define CAN_F25R2_FB23 CAN_F25R2_FB23_Msk /*!< Filter bit 23 */ |
11627 | #define CAN_F25R2_FB24_Pos (24U) |
| 11628 | #define CAN_F25R2_FB24_Pos (24U) |
11628 | #define CAN_F25R2_FB24_Msk (0x1UL << CAN_F25R2_FB24_Pos) /*!< 0x01000000 */ |
| 11629 | #define CAN_F25R2_FB24_Msk (0x1UL << CAN_F25R2_FB24_Pos) /*!< 0x01000000 */ |
11629 | #define CAN_F25R2_FB24 CAN_F25R2_FB24_Msk /*!< Filter bit 24 */ |
| 11630 | #define CAN_F25R2_FB24 CAN_F25R2_FB24_Msk /*!< Filter bit 24 */ |
11630 | #define CAN_F25R2_FB25_Pos (25U) |
| 11631 | #define CAN_F25R2_FB25_Pos (25U) |
11631 | #define CAN_F25R2_FB25_Msk (0x1UL << CAN_F25R2_FB25_Pos) /*!< 0x02000000 */ |
| 11632 | #define CAN_F25R2_FB25_Msk (0x1UL << CAN_F25R2_FB25_Pos) /*!< 0x02000000 */ |
11632 | #define CAN_F25R2_FB25 CAN_F25R2_FB25_Msk /*!< Filter bit 25 */ |
| 11633 | #define CAN_F25R2_FB25 CAN_F25R2_FB25_Msk /*!< Filter bit 25 */ |
11633 | #define CAN_F25R2_FB26_Pos (26U) |
| 11634 | #define CAN_F25R2_FB26_Pos (26U) |
11634 | #define CAN_F25R2_FB26_Msk (0x1UL << CAN_F25R2_FB26_Pos) /*!< 0x04000000 */ |
| 11635 | #define CAN_F25R2_FB26_Msk (0x1UL << CAN_F25R2_FB26_Pos) /*!< 0x04000000 */ |
11635 | #define CAN_F25R2_FB26 CAN_F25R2_FB26_Msk /*!< Filter bit 26 */ |
| 11636 | #define CAN_F25R2_FB26 CAN_F25R2_FB26_Msk /*!< Filter bit 26 */ |
11636 | #define CAN_F25R2_FB27_Pos (27U) |
| 11637 | #define CAN_F25R2_FB27_Pos (27U) |
11637 | #define CAN_F25R2_FB27_Msk (0x1UL << CAN_F25R2_FB27_Pos) /*!< 0x08000000 */ |
| 11638 | #define CAN_F25R2_FB27_Msk (0x1UL << CAN_F25R2_FB27_Pos) /*!< 0x08000000 */ |
11638 | #define CAN_F25R2_FB27 CAN_F25R2_FB27_Msk /*!< Filter bit 27 */ |
| 11639 | #define CAN_F25R2_FB27 CAN_F25R2_FB27_Msk /*!< Filter bit 27 */ |
11639 | #define CAN_F25R2_FB28_Pos (28U) |
| 11640 | #define CAN_F25R2_FB28_Pos (28U) |
11640 | #define CAN_F25R2_FB28_Msk (0x1UL << CAN_F25R2_FB28_Pos) /*!< 0x10000000 */ |
| 11641 | #define CAN_F25R2_FB28_Msk (0x1UL << CAN_F25R2_FB28_Pos) /*!< 0x10000000 */ |
11641 | #define CAN_F25R2_FB28 CAN_F25R2_FB28_Msk /*!< Filter bit 28 */ |
| 11642 | #define CAN_F25R2_FB28 CAN_F25R2_FB28_Msk /*!< Filter bit 28 */ |
11642 | #define CAN_F25R2_FB29_Pos (29U) |
| 11643 | #define CAN_F25R2_FB29_Pos (29U) |
11643 | #define CAN_F25R2_FB29_Msk (0x1UL << CAN_F25R2_FB29_Pos) /*!< 0x20000000 */ |
| 11644 | #define CAN_F25R2_FB29_Msk (0x1UL << CAN_F25R2_FB29_Pos) /*!< 0x20000000 */ |
11644 | #define CAN_F25R2_FB29 CAN_F25R2_FB29_Msk /*!< Filter bit 29 */ |
| 11645 | #define CAN_F25R2_FB29 CAN_F25R2_FB29_Msk /*!< Filter bit 29 */ |
11645 | #define CAN_F25R2_FB30_Pos (30U) |
| 11646 | #define CAN_F25R2_FB30_Pos (30U) |
11646 | #define CAN_F25R2_FB30_Msk (0x1UL << CAN_F25R2_FB30_Pos) /*!< 0x40000000 */ |
| 11647 | #define CAN_F25R2_FB30_Msk (0x1UL << CAN_F25R2_FB30_Pos) /*!< 0x40000000 */ |
11647 | #define CAN_F25R2_FB30 CAN_F25R2_FB30_Msk /*!< Filter bit 30 */ |
| 11648 | #define CAN_F25R2_FB30 CAN_F25R2_FB30_Msk /*!< Filter bit 30 */ |
11648 | #define CAN_F25R2_FB31_Pos (31U) |
| 11649 | #define CAN_F25R2_FB31_Pos (31U) |
11649 | #define CAN_F25R2_FB31_Msk (0x1UL << CAN_F25R2_FB31_Pos) /*!< 0x80000000 */ |
| 11650 | #define CAN_F25R2_FB31_Msk (0x1UL << CAN_F25R2_FB31_Pos) /*!< 0x80000000 */ |
11650 | #define CAN_F25R2_FB31 CAN_F25R2_FB31_Msk /*!< Filter bit 31 */ |
| 11651 | #define CAN_F25R2_FB31 CAN_F25R2_FB31_Msk /*!< Filter bit 31 */ |
11651 | |
| 11652 | 11652 | /******************* Bit definition for CAN_F26R2 register ******************/ |
|
| 11653 | /******************* Bit definition for CAN_F26R2 register ******************/ |
11653 | #define CAN_F26R2_FB0_Pos (0U) |
| 11654 | #define CAN_F26R2_FB0_Pos (0U) |
11654 | #define CAN_F26R2_FB0_Msk (0x1UL << CAN_F26R2_FB0_Pos) /*!< 0x00000001 */ |
| 11655 | #define CAN_F26R2_FB0_Msk (0x1UL << CAN_F26R2_FB0_Pos) /*!< 0x00000001 */ |
11655 | #define CAN_F26R2_FB0 CAN_F26R2_FB0_Msk /*!< Filter bit 0 */ |
| 11656 | #define CAN_F26R2_FB0 CAN_F26R2_FB0_Msk /*!< Filter bit 0 */ |
11656 | #define CAN_F26R2_FB1_Pos (1U) |
| 11657 | #define CAN_F26R2_FB1_Pos (1U) |
11657 | #define CAN_F26R2_FB1_Msk (0x1UL << CAN_F26R2_FB1_Pos) /*!< 0x00000002 */ |
| 11658 | #define CAN_F26R2_FB1_Msk (0x1UL << CAN_F26R2_FB1_Pos) /*!< 0x00000002 */ |
11658 | #define CAN_F26R2_FB1 CAN_F26R2_FB1_Msk /*!< Filter bit 1 */ |
| 11659 | #define CAN_F26R2_FB1 CAN_F26R2_FB1_Msk /*!< Filter bit 1 */ |
11659 | #define CAN_F26R2_FB2_Pos (2U) |
| 11660 | #define CAN_F26R2_FB2_Pos (2U) |
11660 | #define CAN_F26R2_FB2_Msk (0x1UL << CAN_F26R2_FB2_Pos) /*!< 0x00000004 */ |
| 11661 | #define CAN_F26R2_FB2_Msk (0x1UL << CAN_F26R2_FB2_Pos) /*!< 0x00000004 */ |
11661 | #define CAN_F26R2_FB2 CAN_F26R2_FB2_Msk /*!< Filter bit 2 */ |
| 11662 | #define CAN_F26R2_FB2 CAN_F26R2_FB2_Msk /*!< Filter bit 2 */ |
11662 | #define CAN_F26R2_FB3_Pos (3U) |
| 11663 | #define CAN_F26R2_FB3_Pos (3U) |
11663 | #define CAN_F26R2_FB3_Msk (0x1UL << CAN_F26R2_FB3_Pos) /*!< 0x00000008 */ |
| 11664 | #define CAN_F26R2_FB3_Msk (0x1UL << CAN_F26R2_FB3_Pos) /*!< 0x00000008 */ |
11664 | #define CAN_F26R2_FB3 CAN_F26R2_FB3_Msk /*!< Filter bit 3 */ |
| 11665 | #define CAN_F26R2_FB3 CAN_F26R2_FB3_Msk /*!< Filter bit 3 */ |
11665 | #define CAN_F26R2_FB4_Pos (4U) |
| 11666 | #define CAN_F26R2_FB4_Pos (4U) |
11666 | #define CAN_F26R2_FB4_Msk (0x1UL << CAN_F26R2_FB4_Pos) /*!< 0x00000010 */ |
| 11667 | #define CAN_F26R2_FB4_Msk (0x1UL << CAN_F26R2_FB4_Pos) /*!< 0x00000010 */ |
11667 | #define CAN_F26R2_FB4 CAN_F26R2_FB4_Msk /*!< Filter bit 4 */ |
| 11668 | #define CAN_F26R2_FB4 CAN_F26R2_FB4_Msk /*!< Filter bit 4 */ |
11668 | #define CAN_F26R2_FB5_Pos (5U) |
| 11669 | #define CAN_F26R2_FB5_Pos (5U) |
11669 | #define CAN_F26R2_FB5_Msk (0x1UL << CAN_F26R2_FB5_Pos) /*!< 0x00000020 */ |
| 11670 | #define CAN_F26R2_FB5_Msk (0x1UL << CAN_F26R2_FB5_Pos) /*!< 0x00000020 */ |
11670 | #define CAN_F26R2_FB5 CAN_F26R2_FB5_Msk /*!< Filter bit 5 */ |
| 11671 | #define CAN_F26R2_FB5 CAN_F26R2_FB5_Msk /*!< Filter bit 5 */ |
11671 | #define CAN_F26R2_FB6_Pos (6U) |
| 11672 | #define CAN_F26R2_FB6_Pos (6U) |
11672 | #define CAN_F26R2_FB6_Msk (0x1UL << CAN_F26R2_FB6_Pos) /*!< 0x00000040 */ |
| 11673 | #define CAN_F26R2_FB6_Msk (0x1UL << CAN_F26R2_FB6_Pos) /*!< 0x00000040 */ |
11673 | #define CAN_F26R2_FB6 CAN_F26R2_FB6_Msk /*!< Filter bit 6 */ |
| 11674 | #define CAN_F26R2_FB6 CAN_F26R2_FB6_Msk /*!< Filter bit 6 */ |
11674 | #define CAN_F26R2_FB7_Pos (7U) |
| 11675 | #define CAN_F26R2_FB7_Pos (7U) |
11675 | #define CAN_F26R2_FB7_Msk (0x1UL << CAN_F26R2_FB7_Pos) /*!< 0x00000080 */ |
| 11676 | #define CAN_F26R2_FB7_Msk (0x1UL << CAN_F26R2_FB7_Pos) /*!< 0x00000080 */ |
11676 | #define CAN_F26R2_FB7 CAN_F26R2_FB7_Msk /*!< Filter bit 7 */ |
| 11677 | #define CAN_F26R2_FB7 CAN_F26R2_FB7_Msk /*!< Filter bit 7 */ |
11677 | #define CAN_F26R2_FB8_Pos (8U) |
| 11678 | #define CAN_F26R2_FB8_Pos (8U) |
11678 | #define CAN_F26R2_FB8_Msk (0x1UL << CAN_F26R2_FB8_Pos) /*!< 0x00000100 */ |
| 11679 | #define CAN_F26R2_FB8_Msk (0x1UL << CAN_F26R2_FB8_Pos) /*!< 0x00000100 */ |
11679 | #define CAN_F26R2_FB8 CAN_F26R2_FB8_Msk /*!< Filter bit 8 */ |
| 11680 | #define CAN_F26R2_FB8 CAN_F26R2_FB8_Msk /*!< Filter bit 8 */ |
11680 | #define CAN_F26R2_FB9_Pos (9U) |
| 11681 | #define CAN_F26R2_FB9_Pos (9U) |
11681 | #define CAN_F26R2_FB9_Msk (0x1UL << CAN_F26R2_FB9_Pos) /*!< 0x00000200 */ |
| 11682 | #define CAN_F26R2_FB9_Msk (0x1UL << CAN_F26R2_FB9_Pos) /*!< 0x00000200 */ |
11682 | #define CAN_F26R2_FB9 CAN_F26R2_FB9_Msk /*!< Filter bit 9 */ |
| 11683 | #define CAN_F26R2_FB9 CAN_F26R2_FB9_Msk /*!< Filter bit 9 */ |
11683 | #define CAN_F26R2_FB10_Pos (10U) |
| 11684 | #define CAN_F26R2_FB10_Pos (10U) |
11684 | #define CAN_F26R2_FB10_Msk (0x1UL << CAN_F26R2_FB10_Pos) /*!< 0x00000400 */ |
| 11685 | #define CAN_F26R2_FB10_Msk (0x1UL << CAN_F26R2_FB10_Pos) /*!< 0x00000400 */ |
11685 | #define CAN_F26R2_FB10 CAN_F26R2_FB10_Msk /*!< Filter bit 10 */ |
| 11686 | #define CAN_F26R2_FB10 CAN_F26R2_FB10_Msk /*!< Filter bit 10 */ |
11686 | #define CAN_F26R2_FB11_Pos (11U) |
| 11687 | #define CAN_F26R2_FB11_Pos (11U) |
11687 | #define CAN_F26R2_FB11_Msk (0x1UL << CAN_F26R2_FB11_Pos) /*!< 0x00000800 */ |
| 11688 | #define CAN_F26R2_FB11_Msk (0x1UL << CAN_F26R2_FB11_Pos) /*!< 0x00000800 */ |
11688 | #define CAN_F26R2_FB11 CAN_F26R2_FB11_Msk /*!< Filter bit 11 */ |
| 11689 | #define CAN_F26R2_FB11 CAN_F26R2_FB11_Msk /*!< Filter bit 11 */ |
11689 | #define CAN_F26R2_FB12_Pos (12U) |
| 11690 | #define CAN_F26R2_FB12_Pos (12U) |
11690 | #define CAN_F26R2_FB12_Msk (0x1UL << CAN_F26R2_FB12_Pos) /*!< 0x00001000 */ |
| 11691 | #define CAN_F26R2_FB12_Msk (0x1UL << CAN_F26R2_FB12_Pos) /*!< 0x00001000 */ |
11691 | #define CAN_F26R2_FB12 CAN_F26R2_FB12_Msk /*!< Filter bit 12 */ |
| 11692 | #define CAN_F26R2_FB12 CAN_F26R2_FB12_Msk /*!< Filter bit 12 */ |
11692 | #define CAN_F26R2_FB13_Pos (13U) |
| 11693 | #define CAN_F26R2_FB13_Pos (13U) |
11693 | #define CAN_F26R2_FB13_Msk (0x1UL << CAN_F26R2_FB13_Pos) /*!< 0x00002000 */ |
| 11694 | #define CAN_F26R2_FB13_Msk (0x1UL << CAN_F26R2_FB13_Pos) /*!< 0x00002000 */ |
11694 | #define CAN_F26R2_FB13 CAN_F26R2_FB13_Msk /*!< Filter bit 13 */ |
| 11695 | #define CAN_F26R2_FB13 CAN_F26R2_FB13_Msk /*!< Filter bit 13 */ |
11695 | #define CAN_F26R2_FB14_Pos (14U) |
| 11696 | #define CAN_F26R2_FB14_Pos (14U) |
11696 | #define CAN_F26R2_FB14_Msk (0x1UL << CAN_F26R2_FB14_Pos) /*!< 0x00004000 */ |
| 11697 | #define CAN_F26R2_FB14_Msk (0x1UL << CAN_F26R2_FB14_Pos) /*!< 0x00004000 */ |
11697 | #define CAN_F26R2_FB14 CAN_F26R2_FB14_Msk /*!< Filter bit 14 */ |
| 11698 | #define CAN_F26R2_FB14 CAN_F26R2_FB14_Msk /*!< Filter bit 14 */ |
11698 | #define CAN_F26R2_FB15_Pos (15U) |
| 11699 | #define CAN_F26R2_FB15_Pos (15U) |
11699 | #define CAN_F26R2_FB15_Msk (0x1UL << CAN_F26R2_FB15_Pos) /*!< 0x00008000 */ |
| 11700 | #define CAN_F26R2_FB15_Msk (0x1UL << CAN_F26R2_FB15_Pos) /*!< 0x00008000 */ |
11700 | #define CAN_F26R2_FB15 CAN_F26R2_FB15_Msk /*!< Filter bit 15 */ |
| 11701 | #define CAN_F26R2_FB15 CAN_F26R2_FB15_Msk /*!< Filter bit 15 */ |
11701 | #define CAN_F26R2_FB16_Pos (16U) |
| 11702 | #define CAN_F26R2_FB16_Pos (16U) |
11702 | #define CAN_F26R2_FB16_Msk (0x1UL << CAN_F26R2_FB16_Pos) /*!< 0x00010000 */ |
| 11703 | #define CAN_F26R2_FB16_Msk (0x1UL << CAN_F26R2_FB16_Pos) /*!< 0x00010000 */ |
11703 | #define CAN_F26R2_FB16 CAN_F26R2_FB16_Msk /*!< Filter bit 16 */ |
| 11704 | #define CAN_F26R2_FB16 CAN_F26R2_FB16_Msk /*!< Filter bit 16 */ |
11704 | #define CAN_F26R2_FB17_Pos (17U) |
| 11705 | #define CAN_F26R2_FB17_Pos (17U) |
11705 | #define CAN_F26R2_FB17_Msk (0x1UL << CAN_F26R2_FB17_Pos) /*!< 0x00020000 */ |
| 11706 | #define CAN_F26R2_FB17_Msk (0x1UL << CAN_F26R2_FB17_Pos) /*!< 0x00020000 */ |
11706 | #define CAN_F26R2_FB17 CAN_F26R2_FB17_Msk /*!< Filter bit 17 */ |
| 11707 | #define CAN_F26R2_FB17 CAN_F26R2_FB17_Msk /*!< Filter bit 17 */ |
11707 | #define CAN_F26R2_FB18_Pos (18U) |
| 11708 | #define CAN_F26R2_FB18_Pos (18U) |
11708 | #define CAN_F26R2_FB18_Msk (0x1UL << CAN_F26R2_FB18_Pos) /*!< 0x00040000 */ |
| 11709 | #define CAN_F26R2_FB18_Msk (0x1UL << CAN_F26R2_FB18_Pos) /*!< 0x00040000 */ |
11709 | #define CAN_F26R2_FB18 CAN_F26R2_FB18_Msk /*!< Filter bit 18 */ |
| 11710 | #define CAN_F26R2_FB18 CAN_F26R2_FB18_Msk /*!< Filter bit 18 */ |
11710 | #define CAN_F26R2_FB19_Pos (19U) |
| 11711 | #define CAN_F26R2_FB19_Pos (19U) |
11711 | #define CAN_F26R2_FB19_Msk (0x1UL << CAN_F26R2_FB19_Pos) /*!< 0x00080000 */ |
| 11712 | #define CAN_F26R2_FB19_Msk (0x1UL << CAN_F26R2_FB19_Pos) /*!< 0x00080000 */ |
11712 | #define CAN_F26R2_FB19 CAN_F26R2_FB19_Msk /*!< Filter bit 19 */ |
| 11713 | #define CAN_F26R2_FB19 CAN_F26R2_FB19_Msk /*!< Filter bit 19 */ |
11713 | #define CAN_F26R2_FB20_Pos (20U) |
| 11714 | #define CAN_F26R2_FB20_Pos (20U) |
11714 | #define CAN_F26R2_FB20_Msk (0x1UL << CAN_F26R2_FB20_Pos) /*!< 0x00100000 */ |
| 11715 | #define CAN_F26R2_FB20_Msk (0x1UL << CAN_F26R2_FB20_Pos) /*!< 0x00100000 */ |
11715 | #define CAN_F26R2_FB20 CAN_F26R2_FB20_Msk /*!< Filter bit 20 */ |
| 11716 | #define CAN_F26R2_FB20 CAN_F26R2_FB20_Msk /*!< Filter bit 20 */ |
11716 | #define CAN_F26R2_FB21_Pos (21U) |
| 11717 | #define CAN_F26R2_FB21_Pos (21U) |
11717 | #define CAN_F26R2_FB21_Msk (0x1UL << CAN_F26R2_FB21_Pos) /*!< 0x00200000 */ |
| 11718 | #define CAN_F26R2_FB21_Msk (0x1UL << CAN_F26R2_FB21_Pos) /*!< 0x00200000 */ |
11718 | #define CAN_F26R2_FB21 CAN_F26R2_FB21_Msk /*!< Filter bit 21 */ |
| 11719 | #define CAN_F26R2_FB21 CAN_F26R2_FB21_Msk /*!< Filter bit 21 */ |
11719 | #define CAN_F26R2_FB22_Pos (22U) |
| 11720 | #define CAN_F26R2_FB22_Pos (22U) |
11720 | #define CAN_F26R2_FB22_Msk (0x1UL << CAN_F26R2_FB22_Pos) /*!< 0x00400000 */ |
| 11721 | #define CAN_F26R2_FB22_Msk (0x1UL << CAN_F26R2_FB22_Pos) /*!< 0x00400000 */ |
11721 | #define CAN_F26R2_FB22 CAN_F26R2_FB22_Msk /*!< Filter bit 22 */ |
| 11722 | #define CAN_F26R2_FB22 CAN_F26R2_FB22_Msk /*!< Filter bit 22 */ |
11722 | #define CAN_F26R2_FB23_Pos (23U) |
| 11723 | #define CAN_F26R2_FB23_Pos (23U) |
11723 | #define CAN_F26R2_FB23_Msk (0x1UL << CAN_F26R2_FB23_Pos) /*!< 0x00800000 */ |
| 11724 | #define CAN_F26R2_FB23_Msk (0x1UL << CAN_F26R2_FB23_Pos) /*!< 0x00800000 */ |
11724 | #define CAN_F26R2_FB23 CAN_F26R2_FB23_Msk /*!< Filter bit 23 */ |
| 11725 | #define CAN_F26R2_FB23 CAN_F26R2_FB23_Msk /*!< Filter bit 23 */ |
11725 | #define CAN_F26R2_FB24_Pos (24U) |
| 11726 | #define CAN_F26R2_FB24_Pos (24U) |
11726 | #define CAN_F26R2_FB24_Msk (0x1UL << CAN_F26R2_FB24_Pos) /*!< 0x01000000 */ |
| 11727 | #define CAN_F26R2_FB24_Msk (0x1UL << CAN_F26R2_FB24_Pos) /*!< 0x01000000 */ |
11727 | #define CAN_F26R2_FB24 CAN_F26R2_FB24_Msk /*!< Filter bit 24 */ |
| 11728 | #define CAN_F26R2_FB24 CAN_F26R2_FB24_Msk /*!< Filter bit 24 */ |
11728 | #define CAN_F26R2_FB25_Pos (25U) |
| 11729 | #define CAN_F26R2_FB25_Pos (25U) |
11729 | #define CAN_F26R2_FB25_Msk (0x1UL << CAN_F26R2_FB25_Pos) /*!< 0x02000000 */ |
| 11730 | #define CAN_F26R2_FB25_Msk (0x1UL << CAN_F26R2_FB25_Pos) /*!< 0x02000000 */ |
11730 | #define CAN_F26R2_FB25 CAN_F26R2_FB25_Msk /*!< Filter bit 25 */ |
| 11731 | #define CAN_F26R2_FB25 CAN_F26R2_FB25_Msk /*!< Filter bit 25 */ |
11731 | #define CAN_F26R2_FB26_Pos (26U) |
| 11732 | #define CAN_F26R2_FB26_Pos (26U) |
11732 | #define CAN_F26R2_FB26_Msk (0x1UL << CAN_F26R2_FB26_Pos) /*!< 0x04000000 */ |
| 11733 | #define CAN_F26R2_FB26_Msk (0x1UL << CAN_F26R2_FB26_Pos) /*!< 0x04000000 */ |
11733 | #define CAN_F26R2_FB26 CAN_F26R2_FB26_Msk /*!< Filter bit 26 */ |
| 11734 | #define CAN_F26R2_FB26 CAN_F26R2_FB26_Msk /*!< Filter bit 26 */ |
11734 | #define CAN_F26R2_FB27_Pos (27U) |
| 11735 | #define CAN_F26R2_FB27_Pos (27U) |
11735 | #define CAN_F26R2_FB27_Msk (0x1UL << CAN_F26R2_FB27_Pos) /*!< 0x08000000 */ |
| 11736 | #define CAN_F26R2_FB27_Msk (0x1UL << CAN_F26R2_FB27_Pos) /*!< 0x08000000 */ |
11736 | #define CAN_F26R2_FB27 CAN_F26R2_FB27_Msk /*!< Filter bit 27 */ |
| 11737 | #define CAN_F26R2_FB27 CAN_F26R2_FB27_Msk /*!< Filter bit 27 */ |
11737 | #define CAN_F26R2_FB28_Pos (28U) |
| 11738 | #define CAN_F26R2_FB28_Pos (28U) |
11738 | #define CAN_F26R2_FB28_Msk (0x1UL << CAN_F26R2_FB28_Pos) /*!< 0x10000000 */ |
| 11739 | #define CAN_F26R2_FB28_Msk (0x1UL << CAN_F26R2_FB28_Pos) /*!< 0x10000000 */ |
11739 | #define CAN_F26R2_FB28 CAN_F26R2_FB28_Msk /*!< Filter bit 28 */ |
| 11740 | #define CAN_F26R2_FB28 CAN_F26R2_FB28_Msk /*!< Filter bit 28 */ |
11740 | #define CAN_F26R2_FB29_Pos (29U) |
| 11741 | #define CAN_F26R2_FB29_Pos (29U) |
11741 | #define CAN_F26R2_FB29_Msk (0x1UL << CAN_F26R2_FB29_Pos) /*!< 0x20000000 */ |
| 11742 | #define CAN_F26R2_FB29_Msk (0x1UL << CAN_F26R2_FB29_Pos) /*!< 0x20000000 */ |
11742 | #define CAN_F26R2_FB29 CAN_F26R2_FB29_Msk /*!< Filter bit 29 */ |
| 11743 | #define CAN_F26R2_FB29 CAN_F26R2_FB29_Msk /*!< Filter bit 29 */ |
11743 | #define CAN_F26R2_FB30_Pos (30U) |
| 11744 | #define CAN_F26R2_FB30_Pos (30U) |
11744 | #define CAN_F26R2_FB30_Msk (0x1UL << CAN_F26R2_FB30_Pos) /*!< 0x40000000 */ |
| 11745 | #define CAN_F26R2_FB30_Msk (0x1UL << CAN_F26R2_FB30_Pos) /*!< 0x40000000 */ |
11745 | #define CAN_F26R2_FB30 CAN_F26R2_FB30_Msk /*!< Filter bit 30 */ |
| 11746 | #define CAN_F26R2_FB30 CAN_F26R2_FB30_Msk /*!< Filter bit 30 */ |
11746 | #define CAN_F26R2_FB31_Pos (31U) |
| 11747 | #define CAN_F26R2_FB31_Pos (31U) |
11747 | #define CAN_F26R2_FB31_Msk (0x1UL << CAN_F26R2_FB31_Pos) /*!< 0x80000000 */ |
| 11748 | #define CAN_F26R2_FB31_Msk (0x1UL << CAN_F26R2_FB31_Pos) /*!< 0x80000000 */ |
11748 | #define CAN_F26R2_FB31 CAN_F26R2_FB31_Msk /*!< Filter bit 31 */ |
| 11749 | #define CAN_F26R2_FB31 CAN_F26R2_FB31_Msk /*!< Filter bit 31 */ |
11749 | |
| 11750 | 11750 | /******************* Bit definition for CAN_F27R2 register ******************/ |
|
| 11751 | /******************* Bit definition for CAN_F27R2 register ******************/ |
11751 | #define CAN_F27R2_FB0_Pos (0U) |
| 11752 | #define CAN_F27R2_FB0_Pos (0U) |
11752 | #define CAN_F27R2_FB0_Msk (0x1UL << CAN_F27R2_FB0_Pos) /*!< 0x00000001 */ |
| 11753 | #define CAN_F27R2_FB0_Msk (0x1UL << CAN_F27R2_FB0_Pos) /*!< 0x00000001 */ |
11753 | #define CAN_F27R2_FB0 CAN_F27R2_FB0_Msk /*!< Filter bit 0 */ |
| 11754 | #define CAN_F27R2_FB0 CAN_F27R2_FB0_Msk /*!< Filter bit 0 */ |
11754 | #define CAN_F27R2_FB1_Pos (1U) |
| 11755 | #define CAN_F27R2_FB1_Pos (1U) |
11755 | #define CAN_F27R2_FB1_Msk (0x1UL << CAN_F27R2_FB1_Pos) /*!< 0x00000002 */ |
| 11756 | #define CAN_F27R2_FB1_Msk (0x1UL << CAN_F27R2_FB1_Pos) /*!< 0x00000002 */ |
11756 | #define CAN_F27R2_FB1 CAN_F27R2_FB1_Msk /*!< Filter bit 1 */ |
| 11757 | #define CAN_F27R2_FB1 CAN_F27R2_FB1_Msk /*!< Filter bit 1 */ |
11757 | #define CAN_F27R2_FB2_Pos (2U) |
| 11758 | #define CAN_F27R2_FB2_Pos (2U) |
11758 | #define CAN_F27R2_FB2_Msk (0x1UL << CAN_F27R2_FB2_Pos) /*!< 0x00000004 */ |
| 11759 | #define CAN_F27R2_FB2_Msk (0x1UL << CAN_F27R2_FB2_Pos) /*!< 0x00000004 */ |
11759 | #define CAN_F27R2_FB2 CAN_F27R2_FB2_Msk /*!< Filter bit 2 */ |
| 11760 | #define CAN_F27R2_FB2 CAN_F27R2_FB2_Msk /*!< Filter bit 2 */ |
11760 | #define CAN_F27R2_FB3_Pos (3U) |
| 11761 | #define CAN_F27R2_FB3_Pos (3U) |
11761 | #define CAN_F27R2_FB3_Msk (0x1UL << CAN_F27R2_FB3_Pos) /*!< 0x00000008 */ |
| 11762 | #define CAN_F27R2_FB3_Msk (0x1UL << CAN_F27R2_FB3_Pos) /*!< 0x00000008 */ |
11762 | #define CAN_F27R2_FB3 CAN_F27R2_FB3_Msk /*!< Filter bit 3 */ |
| 11763 | #define CAN_F27R2_FB3 CAN_F27R2_FB3_Msk /*!< Filter bit 3 */ |
11763 | #define CAN_F27R2_FB4_Pos (4U) |
| 11764 | #define CAN_F27R2_FB4_Pos (4U) |
11764 | #define CAN_F27R2_FB4_Msk (0x1UL << CAN_F27R2_FB4_Pos) /*!< 0x00000010 */ |
| 11765 | #define CAN_F27R2_FB4_Msk (0x1UL << CAN_F27R2_FB4_Pos) /*!< 0x00000010 */ |
11765 | #define CAN_F27R2_FB4 CAN_F27R2_FB4_Msk /*!< Filter bit 4 */ |
| 11766 | #define CAN_F27R2_FB4 CAN_F27R2_FB4_Msk /*!< Filter bit 4 */ |
11766 | #define CAN_F27R2_FB5_Pos (5U) |
| 11767 | #define CAN_F27R2_FB5_Pos (5U) |
11767 | #define CAN_F27R2_FB5_Msk (0x1UL << CAN_F27R2_FB5_Pos) /*!< 0x00000020 */ |
| 11768 | #define CAN_F27R2_FB5_Msk (0x1UL << CAN_F27R2_FB5_Pos) /*!< 0x00000020 */ |
11768 | #define CAN_F27R2_FB5 CAN_F27R2_FB5_Msk /*!< Filter bit 5 */ |
| 11769 | #define CAN_F27R2_FB5 CAN_F27R2_FB5_Msk /*!< Filter bit 5 */ |
11769 | #define CAN_F27R2_FB6_Pos (6U) |
| 11770 | #define CAN_F27R2_FB6_Pos (6U) |
11770 | #define CAN_F27R2_FB6_Msk (0x1UL << CAN_F27R2_FB6_Pos) /*!< 0x00000040 */ |
| 11771 | #define CAN_F27R2_FB6_Msk (0x1UL << CAN_F27R2_FB6_Pos) /*!< 0x00000040 */ |
11771 | #define CAN_F27R2_FB6 CAN_F27R2_FB6_Msk /*!< Filter bit 6 */ |
| 11772 | #define CAN_F27R2_FB6 CAN_F27R2_FB6_Msk /*!< Filter bit 6 */ |
11772 | #define CAN_F27R2_FB7_Pos (7U) |
| 11773 | #define CAN_F27R2_FB7_Pos (7U) |
11773 | #define CAN_F27R2_FB7_Msk (0x1UL << CAN_F27R2_FB7_Pos) /*!< 0x00000080 */ |
| 11774 | #define CAN_F27R2_FB7_Msk (0x1UL << CAN_F27R2_FB7_Pos) /*!< 0x00000080 */ |
11774 | #define CAN_F27R2_FB7 CAN_F27R2_FB7_Msk /*!< Filter bit 7 */ |
| 11775 | #define CAN_F27R2_FB7 CAN_F27R2_FB7_Msk /*!< Filter bit 7 */ |
11775 | #define CAN_F27R2_FB8_Pos (8U) |
| 11776 | #define CAN_F27R2_FB8_Pos (8U) |
11776 | #define CAN_F27R2_FB8_Msk (0x1UL << CAN_F27R2_FB8_Pos) /*!< 0x00000100 */ |
| 11777 | #define CAN_F27R2_FB8_Msk (0x1UL << CAN_F27R2_FB8_Pos) /*!< 0x00000100 */ |
11777 | #define CAN_F27R2_FB8 CAN_F27R2_FB8_Msk /*!< Filter bit 8 */ |
| 11778 | #define CAN_F27R2_FB8 CAN_F27R2_FB8_Msk /*!< Filter bit 8 */ |
11778 | #define CAN_F27R2_FB9_Pos (9U) |
| 11779 | #define CAN_F27R2_FB9_Pos (9U) |
11779 | #define CAN_F27R2_FB9_Msk (0x1UL << CAN_F27R2_FB9_Pos) /*!< 0x00000200 */ |
| 11780 | #define CAN_F27R2_FB9_Msk (0x1UL << CAN_F27R2_FB9_Pos) /*!< 0x00000200 */ |
11780 | #define CAN_F27R2_FB9 CAN_F27R2_FB9_Msk /*!< Filter bit 9 */ |
| 11781 | #define CAN_F27R2_FB9 CAN_F27R2_FB9_Msk /*!< Filter bit 9 */ |
11781 | #define CAN_F27R2_FB10_Pos (10U) |
| 11782 | #define CAN_F27R2_FB10_Pos (10U) |
11782 | #define CAN_F27R2_FB10_Msk (0x1UL << CAN_F27R2_FB10_Pos) /*!< 0x00000400 */ |
| 11783 | #define CAN_F27R2_FB10_Msk (0x1UL << CAN_F27R2_FB10_Pos) /*!< 0x00000400 */ |
11783 | #define CAN_F27R2_FB10 CAN_F27R2_FB10_Msk /*!< Filter bit 10 */ |
| 11784 | #define CAN_F27R2_FB10 CAN_F27R2_FB10_Msk /*!< Filter bit 10 */ |
11784 | #define CAN_F27R2_FB11_Pos (11U) |
| 11785 | #define CAN_F27R2_FB11_Pos (11U) |
11785 | #define CAN_F27R2_FB11_Msk (0x1UL << CAN_F27R2_FB11_Pos) /*!< 0x00000800 */ |
| 11786 | #define CAN_F27R2_FB11_Msk (0x1UL << CAN_F27R2_FB11_Pos) /*!< 0x00000800 */ |
11786 | #define CAN_F27R2_FB11 CAN_F27R2_FB11_Msk /*!< Filter bit 11 */ |
| 11787 | #define CAN_F27R2_FB11 CAN_F27R2_FB11_Msk /*!< Filter bit 11 */ |
11787 | #define CAN_F27R2_FB12_Pos (12U) |
| 11788 | #define CAN_F27R2_FB12_Pos (12U) |
11788 | #define CAN_F27R2_FB12_Msk (0x1UL << CAN_F27R2_FB12_Pos) /*!< 0x00001000 */ |
| 11789 | #define CAN_F27R2_FB12_Msk (0x1UL << CAN_F27R2_FB12_Pos) /*!< 0x00001000 */ |
11789 | #define CAN_F27R2_FB12 CAN_F27R2_FB12_Msk /*!< Filter bit 12 */ |
| 11790 | #define CAN_F27R2_FB12 CAN_F27R2_FB12_Msk /*!< Filter bit 12 */ |
11790 | #define CAN_F27R2_FB13_Pos (13U) |
| 11791 | #define CAN_F27R2_FB13_Pos (13U) |
11791 | #define CAN_F27R2_FB13_Msk (0x1UL << CAN_F27R2_FB13_Pos) /*!< 0x00002000 */ |
| 11792 | #define CAN_F27R2_FB13_Msk (0x1UL << CAN_F27R2_FB13_Pos) /*!< 0x00002000 */ |
11792 | #define CAN_F27R2_FB13 CAN_F27R2_FB13_Msk /*!< Filter bit 13 */ |
| 11793 | #define CAN_F27R2_FB13 CAN_F27R2_FB13_Msk /*!< Filter bit 13 */ |
11793 | #define CAN_F27R2_FB14_Pos (14U) |
| 11794 | #define CAN_F27R2_FB14_Pos (14U) |
11794 | #define CAN_F27R2_FB14_Msk (0x1UL << CAN_F27R2_FB14_Pos) /*!< 0x00004000 */ |
| 11795 | #define CAN_F27R2_FB14_Msk (0x1UL << CAN_F27R2_FB14_Pos) /*!< 0x00004000 */ |
11795 | #define CAN_F27R2_FB14 CAN_F27R2_FB14_Msk /*!< Filter bit 14 */ |
| 11796 | #define CAN_F27R2_FB14 CAN_F27R2_FB14_Msk /*!< Filter bit 14 */ |
11796 | #define CAN_F27R2_FB15_Pos (15U) |
| 11797 | #define CAN_F27R2_FB15_Pos (15U) |
11797 | #define CAN_F27R2_FB15_Msk (0x1UL << CAN_F27R2_FB15_Pos) /*!< 0x00008000 */ |
| 11798 | #define CAN_F27R2_FB15_Msk (0x1UL << CAN_F27R2_FB15_Pos) /*!< 0x00008000 */ |
11798 | #define CAN_F27R2_FB15 CAN_F27R2_FB15_Msk /*!< Filter bit 15 */ |
| 11799 | #define CAN_F27R2_FB15 CAN_F27R2_FB15_Msk /*!< Filter bit 15 */ |
11799 | #define CAN_F27R2_FB16_Pos (16U) |
| 11800 | #define CAN_F27R2_FB16_Pos (16U) |
11800 | #define CAN_F27R2_FB16_Msk (0x1UL << CAN_F27R2_FB16_Pos) /*!< 0x00010000 */ |
| 11801 | #define CAN_F27R2_FB16_Msk (0x1UL << CAN_F27R2_FB16_Pos) /*!< 0x00010000 */ |
11801 | #define CAN_F27R2_FB16 CAN_F27R2_FB16_Msk /*!< Filter bit 16 */ |
| 11802 | #define CAN_F27R2_FB16 CAN_F27R2_FB16_Msk /*!< Filter bit 16 */ |
11802 | #define CAN_F27R2_FB17_Pos (17U) |
| 11803 | #define CAN_F27R2_FB17_Pos (17U) |
11803 | #define CAN_F27R2_FB17_Msk (0x1UL << CAN_F27R2_FB17_Pos) /*!< 0x00020000 */ |
| 11804 | #define CAN_F27R2_FB17_Msk (0x1UL << CAN_F27R2_FB17_Pos) /*!< 0x00020000 */ |
11804 | #define CAN_F27R2_FB17 CAN_F27R2_FB17_Msk /*!< Filter bit 17 */ |
| 11805 | #define CAN_F27R2_FB17 CAN_F27R2_FB17_Msk /*!< Filter bit 17 */ |
11805 | #define CAN_F27R2_FB18_Pos (18U) |
| 11806 | #define CAN_F27R2_FB18_Pos (18U) |
11806 | #define CAN_F27R2_FB18_Msk (0x1UL << CAN_F27R2_FB18_Pos) /*!< 0x00040000 */ |
| 11807 | #define CAN_F27R2_FB18_Msk (0x1UL << CAN_F27R2_FB18_Pos) /*!< 0x00040000 */ |
11807 | #define CAN_F27R2_FB18 CAN_F27R2_FB18_Msk /*!< Filter bit 18 */ |
| 11808 | #define CAN_F27R2_FB18 CAN_F27R2_FB18_Msk /*!< Filter bit 18 */ |
11808 | #define CAN_F27R2_FB19_Pos (19U) |
| 11809 | #define CAN_F27R2_FB19_Pos (19U) |
11809 | #define CAN_F27R2_FB19_Msk (0x1UL << CAN_F27R2_FB19_Pos) /*!< 0x00080000 */ |
| 11810 | #define CAN_F27R2_FB19_Msk (0x1UL << CAN_F27R2_FB19_Pos) /*!< 0x00080000 */ |
11810 | #define CAN_F27R2_FB19 CAN_F27R2_FB19_Msk /*!< Filter bit 19 */ |
| 11811 | #define CAN_F27R2_FB19 CAN_F27R2_FB19_Msk /*!< Filter bit 19 */ |
11811 | #define CAN_F27R2_FB20_Pos (20U) |
| 11812 | #define CAN_F27R2_FB20_Pos (20U) |
11812 | #define CAN_F27R2_FB20_Msk (0x1UL << CAN_F27R2_FB20_Pos) /*!< 0x00100000 */ |
| 11813 | #define CAN_F27R2_FB20_Msk (0x1UL << CAN_F27R2_FB20_Pos) /*!< 0x00100000 */ |
11813 | #define CAN_F27R2_FB20 CAN_F27R2_FB20_Msk /*!< Filter bit 20 */ |
| 11814 | #define CAN_F27R2_FB20 CAN_F27R2_FB20_Msk /*!< Filter bit 20 */ |
11814 | #define CAN_F27R2_FB21_Pos (21U) |
| 11815 | #define CAN_F27R2_FB21_Pos (21U) |
11815 | #define CAN_F27R2_FB21_Msk (0x1UL << CAN_F27R2_FB21_Pos) /*!< 0x00200000 */ |
| 11816 | #define CAN_F27R2_FB21_Msk (0x1UL << CAN_F27R2_FB21_Pos) /*!< 0x00200000 */ |
11816 | #define CAN_F27R2_FB21 CAN_F27R2_FB21_Msk /*!< Filter bit 21 */ |
| 11817 | #define CAN_F27R2_FB21 CAN_F27R2_FB21_Msk /*!< Filter bit 21 */ |
11817 | #define CAN_F27R2_FB22_Pos (22U) |
| 11818 | #define CAN_F27R2_FB22_Pos (22U) |
11818 | #define CAN_F27R2_FB22_Msk (0x1UL << CAN_F27R2_FB22_Pos) /*!< 0x00400000 */ |
| 11819 | #define CAN_F27R2_FB22_Msk (0x1UL << CAN_F27R2_FB22_Pos) /*!< 0x00400000 */ |
11819 | #define CAN_F27R2_FB22 CAN_F27R2_FB22_Msk /*!< Filter bit 22 */ |
| 11820 | #define CAN_F27R2_FB22 CAN_F27R2_FB22_Msk /*!< Filter bit 22 */ |
11820 | #define CAN_F27R2_FB23_Pos (23U) |
| 11821 | #define CAN_F27R2_FB23_Pos (23U) |
11821 | #define CAN_F27R2_FB23_Msk (0x1UL << CAN_F27R2_FB23_Pos) /*!< 0x00800000 */ |
| 11822 | #define CAN_F27R2_FB23_Msk (0x1UL << CAN_F27R2_FB23_Pos) /*!< 0x00800000 */ |
11822 | #define CAN_F27R2_FB23 CAN_F27R2_FB23_Msk /*!< Filter bit 23 */ |
| 11823 | #define CAN_F27R2_FB23 CAN_F27R2_FB23_Msk /*!< Filter bit 23 */ |
11823 | #define CAN_F27R2_FB24_Pos (24U) |
| 11824 | #define CAN_F27R2_FB24_Pos (24U) |
11824 | #define CAN_F27R2_FB24_Msk (0x1UL << CAN_F27R2_FB24_Pos) /*!< 0x01000000 */ |
| 11825 | #define CAN_F27R2_FB24_Msk (0x1UL << CAN_F27R2_FB24_Pos) /*!< 0x01000000 */ |
11825 | #define CAN_F27R2_FB24 CAN_F27R2_FB24_Msk /*!< Filter bit 24 */ |
| 11826 | #define CAN_F27R2_FB24 CAN_F27R2_FB24_Msk /*!< Filter bit 24 */ |
11826 | #define CAN_F27R2_FB25_Pos (25U) |
| 11827 | #define CAN_F27R2_FB25_Pos (25U) |
11827 | #define CAN_F27R2_FB25_Msk (0x1UL << CAN_F27R2_FB25_Pos) /*!< 0x02000000 */ |
| 11828 | #define CAN_F27R2_FB25_Msk (0x1UL << CAN_F27R2_FB25_Pos) /*!< 0x02000000 */ |
11828 | #define CAN_F27R2_FB25 CAN_F27R2_FB25_Msk /*!< Filter bit 25 */ |
| 11829 | #define CAN_F27R2_FB25 CAN_F27R2_FB25_Msk /*!< Filter bit 25 */ |
11829 | #define CAN_F27R2_FB26_Pos (26U) |
| 11830 | #define CAN_F27R2_FB26_Pos (26U) |
11830 | #define CAN_F27R2_FB26_Msk (0x1UL << CAN_F27R2_FB26_Pos) /*!< 0x04000000 */ |
| 11831 | #define CAN_F27R2_FB26_Msk (0x1UL << CAN_F27R2_FB26_Pos) /*!< 0x04000000 */ |
11831 | #define CAN_F27R2_FB26 CAN_F27R2_FB26_Msk /*!< Filter bit 26 */ |
| 11832 | #define CAN_F27R2_FB26 CAN_F27R2_FB26_Msk /*!< Filter bit 26 */ |
11832 | #define CAN_F27R2_FB27_Pos (27U) |
| 11833 | #define CAN_F27R2_FB27_Pos (27U) |
11833 | #define CAN_F27R2_FB27_Msk (0x1UL << CAN_F27R2_FB27_Pos) /*!< 0x08000000 */ |
| 11834 | #define CAN_F27R2_FB27_Msk (0x1UL << CAN_F27R2_FB27_Pos) /*!< 0x08000000 */ |
11834 | #define CAN_F27R2_FB27 CAN_F27R2_FB27_Msk /*!< Filter bit 27 */ |
| 11835 | #define CAN_F27R2_FB27 CAN_F27R2_FB27_Msk /*!< Filter bit 27 */ |
11835 | #define CAN_F27R2_FB28_Pos (28U) |
| 11836 | #define CAN_F27R2_FB28_Pos (28U) |
11836 | #define CAN_F27R2_FB28_Msk (0x1UL << CAN_F27R2_FB28_Pos) /*!< 0x10000000 */ |
| 11837 | #define CAN_F27R2_FB28_Msk (0x1UL << CAN_F27R2_FB28_Pos) /*!< 0x10000000 */ |
11837 | #define CAN_F27R2_FB28 CAN_F27R2_FB28_Msk /*!< Filter bit 28 */ |
| 11838 | #define CAN_F27R2_FB28 CAN_F27R2_FB28_Msk /*!< Filter bit 28 */ |
11838 | #define CAN_F27R2_FB29_Pos (29U) |
| 11839 | #define CAN_F27R2_FB29_Pos (29U) |
11839 | #define CAN_F27R2_FB29_Msk (0x1UL << CAN_F27R2_FB29_Pos) /*!< 0x20000000 */ |
| 11840 | #define CAN_F27R2_FB29_Msk (0x1UL << CAN_F27R2_FB29_Pos) /*!< 0x20000000 */ |
11840 | #define CAN_F27R2_FB29 CAN_F27R2_FB29_Msk /*!< Filter bit 29 */ |
| 11841 | #define CAN_F27R2_FB29 CAN_F27R2_FB29_Msk /*!< Filter bit 29 */ |
11841 | #define CAN_F27R2_FB30_Pos (30U) |
| 11842 | #define CAN_F27R2_FB30_Pos (30U) |
11842 | #define CAN_F27R2_FB30_Msk (0x1UL << CAN_F27R2_FB30_Pos) /*!< 0x40000000 */ |
| 11843 | #define CAN_F27R2_FB30_Msk (0x1UL << CAN_F27R2_FB30_Pos) /*!< 0x40000000 */ |
11843 | #define CAN_F27R2_FB30 CAN_F27R2_FB30_Msk /*!< Filter bit 30 */ |
| 11844 | #define CAN_F27R2_FB30 CAN_F27R2_FB30_Msk /*!< Filter bit 30 */ |
11844 | #define CAN_F27R2_FB31_Pos (31U) |
| 11845 | #define CAN_F27R2_FB31_Pos (31U) |
11845 | #define CAN_F27R2_FB31_Msk (0x1UL << CAN_F27R2_FB31_Pos) /*!< 0x80000000 */ |
| 11846 | #define CAN_F27R2_FB31_Msk (0x1UL << CAN_F27R2_FB31_Pos) /*!< 0x80000000 */ |
11846 | #define CAN_F27R2_FB31 CAN_F27R2_FB31_Msk /*!< Filter bit 31 */ |
| 11847 | #define CAN_F27R2_FB31 CAN_F27R2_FB31_Msk /*!< Filter bit 31 */ |
11847 | |
| 11848 | 11848 | /******************************************************************************/ |
|
| 11849 | /******************************************************************************/ |
11849 | /* */ |
| 11850 | /* */ |
11850 | /* Serial Peripheral Interface */ |
| 11851 | /* Serial Peripheral Interface */ |
11851 | /* */ |
| 11852 | /* */ |
11852 | /******************************************************************************/ |
| 11853 | /******************************************************************************/ |
11853 | /* |
| 11854 | /* |
11854 | * @brief Specific device feature definitions (not present on all devices in the STM32F1 series) |
| 11855 | * @brief Specific device feature definitions (not present on all devices in the STM32F1 serie) |
11855 | */ |
| 11856 | */ |
11856 | #define SPI_I2S_SUPPORT /*!< I2S support */ |
| 11857 | #define SPI_I2S_SUPPORT /*!< I2S support */ |
11857 | #define I2S2_I2S3_CLOCK_FEATURE |
| 11858 | #define I2S2_I2S3_CLOCK_FEATURE |
11858 | |
| 11859 | 11859 | /******************* Bit definition for SPI_CR1 register ********************/ |
|
| 11860 | /******************* Bit definition for SPI_CR1 register ********************/ |
11860 | #define SPI_CR1_CPHA_Pos (0U) |
| 11861 | #define SPI_CR1_CPHA_Pos (0U) |
11861 | #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ |
| 11862 | #define SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */ |
11862 | #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ |
| 11863 | #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */ |
11863 | #define SPI_CR1_CPOL_Pos (1U) |
| 11864 | #define SPI_CR1_CPOL_Pos (1U) |
11864 | #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ |
| 11865 | #define SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */ |
11865 | #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ |
| 11866 | #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */ |
11866 | #define SPI_CR1_MSTR_Pos (2U) |
| 11867 | #define SPI_CR1_MSTR_Pos (2U) |
11867 | #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ |
| 11868 | #define SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */ |
11868 | #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ |
| 11869 | #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */ |
11869 | |
| 11870 | 11870 | #define SPI_CR1_BR_Pos (3U) |
|
| 11871 | #define SPI_CR1_BR_Pos (3U) |
11871 | #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ |
| 11872 | #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ |
11872 | #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ |
| 11873 | #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */ |
11873 | #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ |
| 11874 | #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */ |
11874 | #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ |
| 11875 | #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */ |
11875 | #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ |
| 11876 | #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */ |
11876 | |
| 11877 | 11877 | #define SPI_CR1_SPE_Pos (6U) |
|
| 11878 | #define SPI_CR1_SPE_Pos (6U) |
11878 | #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ |
| 11879 | #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ |
11879 | #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ |
| 11880 | #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */ |
11880 | #define SPI_CR1_LSBFIRST_Pos (7U) |
| 11881 | #define SPI_CR1_LSBFIRST_Pos (7U) |
11881 | #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ |
| 11882 | #define SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */ |
11882 | #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ |
| 11883 | #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */ |
11883 | #define SPI_CR1_SSI_Pos (8U) |
| 11884 | #define SPI_CR1_SSI_Pos (8U) |
11884 | #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ |
| 11885 | #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00000100 */ |
11885 | #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ |
| 11886 | #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */ |
11886 | #define SPI_CR1_SSM_Pos (9U) |
| 11887 | #define SPI_CR1_SSM_Pos (9U) |
11887 | #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ |
| 11888 | #define SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos) /*!< 0x00000200 */ |
11888 | #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ |
| 11889 | #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */ |
11889 | #define SPI_CR1_RXONLY_Pos (10U) |
| 11890 | #define SPI_CR1_RXONLY_Pos (10U) |
11890 | #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ |
| 11891 | #define SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */ |
11891 | #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ |
| 11892 | #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */ |
11892 | #define SPI_CR1_DFF_Pos (11U) |
| 11893 | #define SPI_CR1_DFF_Pos (11U) |
11893 | #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ |
| 11894 | #define SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos) /*!< 0x00000800 */ |
11894 | #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ |
| 11895 | #define SPI_CR1_DFF SPI_CR1_DFF_Msk /*!< Data Frame Format */ |
11895 | #define SPI_CR1_CRCNEXT_Pos (12U) |
| 11896 | #define SPI_CR1_CRCNEXT_Pos (12U) |
11896 | #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ |
| 11897 | #define SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */ |
11897 | #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ |
| 11898 | #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */ |
11898 | #define SPI_CR1_CRCEN_Pos (13U) |
| 11899 | #define SPI_CR1_CRCEN_Pos (13U) |
11899 | #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ |
| 11900 | #define SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */ |
11900 | #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ |
| 11901 | #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */ |
11901 | #define SPI_CR1_BIDIOE_Pos (14U) |
| 11902 | #define SPI_CR1_BIDIOE_Pos (14U) |
11902 | #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ |
| 11903 | #define SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */ |
11903 | #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ |
| 11904 | #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */ |
11904 | #define SPI_CR1_BIDIMODE_Pos (15U) |
| 11905 | #define SPI_CR1_BIDIMODE_Pos (15U) |
11905 | #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ |
| 11906 | #define SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */ |
11906 | #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ |
| 11907 | #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */ |
11907 | |
| 11908 | 11908 | /******************* Bit definition for SPI_CR2 register ********************/ |
|
| 11909 | /******************* Bit definition for SPI_CR2 register ********************/ |
11909 | #define SPI_CR2_RXDMAEN_Pos (0U) |
| 11910 | #define SPI_CR2_RXDMAEN_Pos (0U) |
11910 | #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ |
| 11911 | #define SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */ |
11911 | #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ |
| 11912 | #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */ |
11912 | #define SPI_CR2_TXDMAEN_Pos (1U) |
| 11913 | #define SPI_CR2_TXDMAEN_Pos (1U) |
11913 | #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ |
| 11914 | #define SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */ |
11914 | #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ |
| 11915 | #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */ |
11915 | #define SPI_CR2_SSOE_Pos (2U) |
| 11916 | #define SPI_CR2_SSOE_Pos (2U) |
11916 | #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ |
| 11917 | #define SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */ |
11917 | #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ |
| 11918 | #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */ |
11918 | #define SPI_CR2_ERRIE_Pos (5U) |
| 11919 | #define SPI_CR2_ERRIE_Pos (5U) |
11919 | #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ |
| 11920 | #define SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */ |
11920 | #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ |
| 11921 | #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */ |
11921 | #define SPI_CR2_RXNEIE_Pos (6U) |
| 11922 | #define SPI_CR2_RXNEIE_Pos (6U) |
11922 | #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ |
| 11923 | #define SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */ |
11923 | #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ |
| 11924 | #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */ |
11924 | #define SPI_CR2_TXEIE_Pos (7U) |
| 11925 | #define SPI_CR2_TXEIE_Pos (7U) |
11925 | #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ |
| 11926 | #define SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */ |
11926 | #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ |
| 11927 | #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */ |
11927 | |
| 11928 | 11928 | /******************** Bit definition for SPI_SR register ********************/ |
|
| 11929 | /******************** Bit definition for SPI_SR register ********************/ |
11929 | #define SPI_SR_RXNE_Pos (0U) |
| 11930 | #define SPI_SR_RXNE_Pos (0U) |
11930 | #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ |
| 11931 | #define SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos) /*!< 0x00000001 */ |
11931 | #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ |
| 11932 | #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */ |
11932 | #define SPI_SR_TXE_Pos (1U) |
| 11933 | #define SPI_SR_TXE_Pos (1U) |
11933 | #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ |
| 11934 | #define SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos) /*!< 0x00000002 */ |
11934 | #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ |
| 11935 | #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */ |
11935 | #define SPI_SR_CHSIDE_Pos (2U) |
| 11936 | #define SPI_SR_CHSIDE_Pos (2U) |
11936 | #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ |
| 11937 | #define SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */ |
11937 | #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ |
| 11938 | #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */ |
11938 | #define SPI_SR_UDR_Pos (3U) |
| 11939 | #define SPI_SR_UDR_Pos (3U) |
11939 | #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ |
| 11940 | #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000008 */ |
11940 | #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ |
| 11941 | #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */ |
11941 | #define SPI_SR_CRCERR_Pos (4U) |
| 11942 | #define SPI_SR_CRCERR_Pos (4U) |
11942 | #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ |
| 11943 | #define SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */ |
11943 | #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ |
| 11944 | #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */ |
11944 | #define SPI_SR_MODF_Pos (5U) |
| 11945 | #define SPI_SR_MODF_Pos (5U) |
11945 | #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ |
| 11946 | #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000020 */ |
11946 | #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ |
| 11947 | #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */ |
11947 | #define SPI_SR_OVR_Pos (6U) |
| 11948 | #define SPI_SR_OVR_Pos (6U) |
11948 | #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ |
| 11949 | #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */ |
11949 | #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ |
| 11950 | #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */ |
11950 | #define SPI_SR_BSY_Pos (7U) |
| 11951 | #define SPI_SR_BSY_Pos (7U) |
11951 | #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ |
| 11952 | #define SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos) /*!< 0x00000080 */ |
11952 | #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ |
| 11953 | #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */ |
11953 | |
| 11954 | 11954 | /******************** Bit definition for SPI_DR register ********************/ |
|
| 11955 | /******************** Bit definition for SPI_DR register ********************/ |
11955 | #define SPI_DR_DR_Pos (0U) |
| 11956 | #define SPI_DR_DR_Pos (0U) |
11956 | #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ |
| 11957 | #define SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos) /*!< 0x0000FFFF */ |
11957 | #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ |
| 11958 | #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */ |
11958 | |
| 11959 | 11959 | /******************* Bit definition for SPI_CRCPR register ******************/ |
|
| 11960 | /******************* Bit definition for SPI_CRCPR register ******************/ |
11960 | #define SPI_CRCPR_CRCPOLY_Pos (0U) |
| 11961 | #define SPI_CRCPR_CRCPOLY_Pos (0U) |
11961 | #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ |
| 11962 | #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos) /*!< 0x0000FFFF */ |
11962 | #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ |
| 11963 | #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */ |
11963 | |
| 11964 | 11964 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
|
| 11965 | /****************** Bit definition for SPI_RXCRCR register ******************/ |
11965 | #define SPI_RXCRCR_RXCRC_Pos (0U) |
| 11966 | #define SPI_RXCRCR_RXCRC_Pos (0U) |
11966 | #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ |
| 11967 | #define SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos) /*!< 0x0000FFFF */ |
11967 | #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ |
| 11968 | #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */ |
11968 | |
| 11969 | 11969 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
|
| 11970 | /****************** Bit definition for SPI_TXCRCR register ******************/ |
11970 | #define SPI_TXCRCR_TXCRC_Pos (0U) |
| 11971 | #define SPI_TXCRCR_TXCRC_Pos (0U) |
11971 | #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ |
| 11972 | #define SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos) /*!< 0x0000FFFF */ |
11972 | #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ |
| 11973 | #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */ |
11973 | |
| 11974 | 11974 | /****************** Bit definition for SPI_I2SCFGR register *****************/ |
|
| 11975 | /****************** Bit definition for SPI_I2SCFGR register *****************/ |
11975 | #define SPI_I2SCFGR_CHLEN_Pos (0U) |
| 11976 | #define SPI_I2SCFGR_CHLEN_Pos (0U) |
11976 | #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ |
| 11977 | #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */ |
11977 | #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */ |
| 11978 | #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!< Channel length (number of bits per audio channel) */ |
11978 | |
| 11979 | 11979 | #define SPI_I2SCFGR_DATLEN_Pos (1U) |
|
| 11980 | #define SPI_I2SCFGR_DATLEN_Pos (1U) |
11980 | #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ |
| 11981 | #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */ |
11981 | #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */ |
| 11982 | #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!< DATLEN[1:0] bits (Data length to be transferred) */ |
11982 | #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ |
| 11983 | #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */ |
11983 | #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ |
| 11984 | #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */ |
11984 | |
| 11985 | 11985 | #define SPI_I2SCFGR_CKPOL_Pos (3U) |
|
| 11986 | #define SPI_I2SCFGR_CKPOL_Pos (3U) |
11986 | #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ |
| 11987 | #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */ |
11987 | #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */ |
| 11988 | #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!< steady state clock polarity */ |
11988 | |
| 11989 | 11989 | #define SPI_I2SCFGR_I2SSTD_Pos (4U) |
|
| 11990 | #define SPI_I2SCFGR_I2SSTD_Pos (4U) |
11990 | #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ |
| 11991 | #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */ |
11991 | #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */ |
| 11992 | #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!< I2SSTD[1:0] bits (I2S standard selection) */ |
11992 | #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ |
| 11993 | #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */ |
11993 | #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ |
| 11994 | #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */ |
11994 | |
| 11995 | 11995 | #define SPI_I2SCFGR_PCMSYNC_Pos (7U) |
|
| 11996 | #define SPI_I2SCFGR_PCMSYNC_Pos (7U) |
11996 | #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ |
| 11997 | #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */ |
11997 | #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */ |
| 11998 | #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!< PCM frame synchronization */ |
11998 | |
| 11999 | 11999 | #define SPI_I2SCFGR_I2SCFG_Pos (8U) |
|
| 12000 | #define SPI_I2SCFGR_I2SCFG_Pos (8U) |
12000 | #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ |
| 12001 | #define SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */ |
12001 | #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */ |
| 12002 | #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!< I2SCFG[1:0] bits (I2S configuration mode) */ |
12002 | #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ |
| 12003 | #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */ |
12003 | #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ |
| 12004 | #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */ |
12004 | |
| 12005 | 12005 | #define SPI_I2SCFGR_I2SE_Pos (10U) |
|
| 12006 | #define SPI_I2SCFGR_I2SE_Pos (10U) |
12006 | #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ |
| 12007 | #define SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */ |
12007 | #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */ |
| 12008 | #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!< I2S Enable */ |
12008 | #define SPI_I2SCFGR_I2SMOD_Pos (11U) |
| 12009 | #define SPI_I2SCFGR_I2SMOD_Pos (11U) |
12009 | #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ |
| 12010 | #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */ |
12010 | #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ |
| 12011 | #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!< I2S mode selection */ |
12011 | /****************** Bit definition for SPI_I2SPR register *******************/ |
| 12012 | /****************** Bit definition for SPI_I2SPR register *******************/ |
12012 | #define SPI_I2SPR_I2SDIV_Pos (0U) |
| 12013 | #define SPI_I2SPR_I2SDIV_Pos (0U) |
12013 | #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ |
| 12014 | #define SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */ |
12014 | #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */ |
| 12015 | #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!< I2S Linear prescaler */ |
12015 | #define SPI_I2SPR_ODD_Pos (8U) |
| 12016 | #define SPI_I2SPR_ODD_Pos (8U) |
12016 | #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ |
| 12017 | #define SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */ |
12017 | #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */ |
| 12018 | #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!< Odd factor for the prescaler */ |
12018 | #define SPI_I2SPR_MCKOE_Pos (9U) |
| 12019 | #define SPI_I2SPR_MCKOE_Pos (9U) |
12019 | #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ |
| 12020 | #define SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */ |
12020 | #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */ |
| 12021 | #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!< Master Clock Output Enable */ |
12021 | |
| 12022 | 12022 | /******************************************************************************/ |
|
| 12023 | /******************************************************************************/ |
12023 | /* */ |
| 12024 | /* */ |
12024 | /* Inter-integrated Circuit Interface */ |
| 12025 | /* Inter-integrated Circuit Interface */ |
12025 | /* */ |
| 12026 | /* */ |
12026 | /******************************************************************************/ |
| 12027 | /******************************************************************************/ |
12027 | |
| 12028 | 12028 | /******************* Bit definition for I2C_CR1 register ********************/ |
|
| 12029 | /******************* Bit definition for I2C_CR1 register ********************/ |
12029 | #define I2C_CR1_PE_Pos (0U) |
| 12030 | #define I2C_CR1_PE_Pos (0U) |
12030 | #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ |
| 12031 | #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ |
12031 | #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ |
| 12032 | #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral Enable */ |
12032 | #define I2C_CR1_SMBUS_Pos (1U) |
| 12033 | #define I2C_CR1_SMBUS_Pos (1U) |
12033 | #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ |
| 12034 | #define I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos) /*!< 0x00000002 */ |
12034 | #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ |
| 12035 | #define I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk /*!< SMBus Mode */ |
12035 | #define I2C_CR1_SMBTYPE_Pos (3U) |
| 12036 | #define I2C_CR1_SMBTYPE_Pos (3U) |
12036 | #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ |
| 12037 | #define I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos) /*!< 0x00000008 */ |
12037 | #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ |
| 12038 | #define I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk /*!< SMBus Type */ |
12038 | #define I2C_CR1_ENARP_Pos (4U) |
| 12039 | #define I2C_CR1_ENARP_Pos (4U) |
12039 | #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ |
| 12040 | #define I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos) /*!< 0x00000010 */ |
12040 | #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ |
| 12041 | #define I2C_CR1_ENARP I2C_CR1_ENARP_Msk /*!< ARP Enable */ |
12041 | #define I2C_CR1_ENPEC_Pos (5U) |
| 12042 | #define I2C_CR1_ENPEC_Pos (5U) |
12042 | #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ |
| 12043 | #define I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos) /*!< 0x00000020 */ |
12043 | #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ |
| 12044 | #define I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk /*!< PEC Enable */ |
12044 | #define I2C_CR1_ENGC_Pos (6U) |
| 12045 | #define I2C_CR1_ENGC_Pos (6U) |
12045 | #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ |
| 12046 | #define I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos) /*!< 0x00000040 */ |
12046 | #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ |
| 12047 | #define I2C_CR1_ENGC I2C_CR1_ENGC_Msk /*!< General Call Enable */ |
12047 | #define I2C_CR1_NOSTRETCH_Pos (7U) |
| 12048 | #define I2C_CR1_NOSTRETCH_Pos (7U) |
12048 | #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ |
| 12049 | #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00000080 */ |
12049 | #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ |
| 12050 | #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock Stretching Disable (Slave mode) */ |
12050 | #define I2C_CR1_START_Pos (8U) |
| 12051 | #define I2C_CR1_START_Pos (8U) |
12051 | #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */ |
| 12052 | #define I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos) /*!< 0x00000100 */ |
12052 | #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ |
| 12053 | #define I2C_CR1_START I2C_CR1_START_Msk /*!< Start Generation */ |
12053 | #define I2C_CR1_STOP_Pos (9U) |
| 12054 | #define I2C_CR1_STOP_Pos (9U) |
12054 | #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ |
| 12055 | #define I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos) /*!< 0x00000200 */ |
12055 | #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ |
| 12056 | #define I2C_CR1_STOP I2C_CR1_STOP_Msk /*!< Stop Generation */ |
12056 | #define I2C_CR1_ACK_Pos (10U) |
| 12057 | #define I2C_CR1_ACK_Pos (10U) |
12057 | #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ |
| 12058 | #define I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos) /*!< 0x00000400 */ |
12058 | #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ |
| 12059 | #define I2C_CR1_ACK I2C_CR1_ACK_Msk /*!< Acknowledge Enable */ |
12059 | #define I2C_CR1_POS_Pos (11U) |
| 12060 | #define I2C_CR1_POS_Pos (11U) |
12060 | #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */ |
| 12061 | #define I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos) /*!< 0x00000800 */ |
12061 | #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ |
| 12062 | #define I2C_CR1_POS I2C_CR1_POS_Msk /*!< Acknowledge/PEC Position (for data reception) */ |
12062 | #define I2C_CR1_PEC_Pos (12U) |
| 12063 | #define I2C_CR1_PEC_Pos (12U) |
12063 | #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ |
| 12064 | #define I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos) /*!< 0x00001000 */ |
12064 | #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ |
| 12065 | #define I2C_CR1_PEC I2C_CR1_PEC_Msk /*!< Packet Error Checking */ |
12065 | #define I2C_CR1_ALERT_Pos (13U) |
| 12066 | #define I2C_CR1_ALERT_Pos (13U) |
12066 | #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ |
| 12067 | #define I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos) /*!< 0x00002000 */ |
12067 | #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ |
| 12068 | #define I2C_CR1_ALERT I2C_CR1_ALERT_Msk /*!< SMBus Alert */ |
12068 | #define I2C_CR1_SWRST_Pos (15U) |
| 12069 | #define I2C_CR1_SWRST_Pos (15U) |
12069 | #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ |
| 12070 | #define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00008000 */ |
12070 | #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ |
| 12071 | #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software Reset */ |
12071 | |
| 12072 | 12072 | /******************* Bit definition for I2C_CR2 register ********************/ |
|
| 12073 | /******************* Bit definition for I2C_CR2 register ********************/ |
12073 | #define I2C_CR2_FREQ_Pos (0U) |
| 12074 | #define I2C_CR2_FREQ_Pos (0U) |
12074 | #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ |
| 12075 | #define I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos) /*!< 0x0000003F */ |
12075 | #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ |
| 12076 | #define I2C_CR2_FREQ I2C_CR2_FREQ_Msk /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */ |
12076 | #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ |
| 12077 | #define I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos) /*!< 0x00000001 */ |
12077 | #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ |
| 12078 | #define I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos) /*!< 0x00000002 */ |
12078 | #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ |
| 12079 | #define I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos) /*!< 0x00000004 */ |
12079 | #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ |
| 12080 | #define I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos) /*!< 0x00000008 */ |
12080 | #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ |
| 12081 | #define I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos) /*!< 0x00000010 */ |
12081 | #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ |
| 12082 | #define I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos) /*!< 0x00000020 */ |
12082 | |
| 12083 | 12083 | #define I2C_CR2_ITERREN_Pos (8U) |
|
| 12084 | #define I2C_CR2_ITERREN_Pos (8U) |
12084 | #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ |
| 12085 | #define I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos) /*!< 0x00000100 */ |
12085 | #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ |
| 12086 | #define I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk /*!< Error Interrupt Enable */ |
12086 | #define I2C_CR2_ITEVTEN_Pos (9U) |
| 12087 | #define I2C_CR2_ITEVTEN_Pos (9U) |
12087 | #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ |
| 12088 | #define I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos) /*!< 0x00000200 */ |
12088 | #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ |
| 12089 | #define I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk /*!< Event Interrupt Enable */ |
12089 | #define I2C_CR2_ITBUFEN_Pos (10U) |
| 12090 | #define I2C_CR2_ITBUFEN_Pos (10U) |
12090 | #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ |
| 12091 | #define I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos) /*!< 0x00000400 */ |
12091 | #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ |
| 12092 | #define I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk /*!< Buffer Interrupt Enable */ |
12092 | #define I2C_CR2_DMAEN_Pos (11U) |
| 12093 | #define I2C_CR2_DMAEN_Pos (11U) |
12093 | #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ |
| 12094 | #define I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos) /*!< 0x00000800 */ |
12094 | #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ |
| 12095 | #define I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk /*!< DMA Requests Enable */ |
12095 | #define I2C_CR2_LAST_Pos (12U) |
| 12096 | #define I2C_CR2_LAST_Pos (12U) |
12096 | #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ |
| 12097 | #define I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos) /*!< 0x00001000 */ |
12097 | #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ |
| 12098 | #define I2C_CR2_LAST I2C_CR2_LAST_Msk /*!< DMA Last Transfer */ |
12098 | |
| 12099 | 12099 | /******************* Bit definition for I2C_OAR1 register *******************/ |
|
| 12100 | /******************* Bit definition for I2C_OAR1 register *******************/ |
12100 | #define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */ |
| 12101 | #define I2C_OAR1_ADD1_7 0x000000FEU /*!< Interface Address */ |
12101 | #define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */ |
| 12102 | #define I2C_OAR1_ADD8_9 0x00000300U /*!< Interface Address */ |
12102 | |
| 12103 | 12103 | #define I2C_OAR1_ADD0_Pos (0U) |
|
| 12104 | #define I2C_OAR1_ADD0_Pos (0U) |
12104 | #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ |
| 12105 | #define I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos) /*!< 0x00000001 */ |
12105 | #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ |
| 12106 | #define I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk /*!< Bit 0 */ |
12106 | #define I2C_OAR1_ADD1_Pos (1U) |
| 12107 | #define I2C_OAR1_ADD1_Pos (1U) |
12107 | #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ |
| 12108 | #define I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos) /*!< 0x00000002 */ |
12108 | #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ |
| 12109 | #define I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk /*!< Bit 1 */ |
12109 | #define I2C_OAR1_ADD2_Pos (2U) |
| 12110 | #define I2C_OAR1_ADD2_Pos (2U) |
12110 | #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ |
| 12111 | #define I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos) /*!< 0x00000004 */ |
12111 | #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ |
| 12112 | #define I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk /*!< Bit 2 */ |
12112 | #define I2C_OAR1_ADD3_Pos (3U) |
| 12113 | #define I2C_OAR1_ADD3_Pos (3U) |
12113 | #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ |
| 12114 | #define I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos) /*!< 0x00000008 */ |
12114 | #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ |
| 12115 | #define I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk /*!< Bit 3 */ |
12115 | #define I2C_OAR1_ADD4_Pos (4U) |
| 12116 | #define I2C_OAR1_ADD4_Pos (4U) |
12116 | #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ |
| 12117 | #define I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos) /*!< 0x00000010 */ |
12117 | #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ |
| 12118 | #define I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk /*!< Bit 4 */ |
12118 | #define I2C_OAR1_ADD5_Pos (5U) |
| 12119 | #define I2C_OAR1_ADD5_Pos (5U) |
12119 | #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ |
| 12120 | #define I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos) /*!< 0x00000020 */ |
12120 | #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ |
| 12121 | #define I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk /*!< Bit 5 */ |
12121 | #define I2C_OAR1_ADD6_Pos (6U) |
| 12122 | #define I2C_OAR1_ADD6_Pos (6U) |
12122 | #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ |
| 12123 | #define I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos) /*!< 0x00000040 */ |
12123 | #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ |
| 12124 | #define I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk /*!< Bit 6 */ |
12124 | #define I2C_OAR1_ADD7_Pos (7U) |
| 12125 | #define I2C_OAR1_ADD7_Pos (7U) |
12125 | #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ |
| 12126 | #define I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos) /*!< 0x00000080 */ |
12126 | #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ |
| 12127 | #define I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk /*!< Bit 7 */ |
12127 | #define I2C_OAR1_ADD8_Pos (8U) |
| 12128 | #define I2C_OAR1_ADD8_Pos (8U) |
12128 | #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ |
| 12129 | #define I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos) /*!< 0x00000100 */ |
12129 | #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ |
| 12130 | #define I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk /*!< Bit 8 */ |
12130 | #define I2C_OAR1_ADD9_Pos (9U) |
| 12131 | #define I2C_OAR1_ADD9_Pos (9U) |
12131 | #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ |
| 12132 | #define I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos) /*!< 0x00000200 */ |
12132 | #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ |
| 12133 | #define I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk /*!< Bit 9 */ |
12133 | |
| 12134 | 12134 | #define I2C_OAR1_ADDMODE_Pos (15U) |
|
| 12135 | #define I2C_OAR1_ADDMODE_Pos (15U) |
12135 | #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ |
| 12136 | #define I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos) /*!< 0x00008000 */ |
12136 | #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ |
| 12137 | #define I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk /*!< Addressing Mode (Slave mode) */ |
12137 | |
| 12138 | 12138 | /******************* Bit definition for I2C_OAR2 register *******************/ |
|
| 12139 | /******************* Bit definition for I2C_OAR2 register *******************/ |
12139 | #define I2C_OAR2_ENDUAL_Pos (0U) |
| 12140 | #define I2C_OAR2_ENDUAL_Pos (0U) |
12140 | #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ |
| 12141 | #define I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos) /*!< 0x00000001 */ |
12141 | #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ |
| 12142 | #define I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk /*!< Dual addressing mode enable */ |
12142 | #define I2C_OAR2_ADD2_Pos (1U) |
| 12143 | #define I2C_OAR2_ADD2_Pos (1U) |
12143 | #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ |
| 12144 | #define I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos) /*!< 0x000000FE */ |
12144 | #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ |
| 12145 | #define I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk /*!< Interface address */ |
12145 | |
| 12146 | 12146 | /******************** Bit definition for I2C_DR register ********************/ |
|
| 12147 | /******************** Bit definition for I2C_DR register ********************/ |
12147 | #define I2C_DR_DR_Pos (0U) |
| 12148 | #define I2C_DR_DR_Pos (0U) |
12148 | #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */ |
| 12149 | #define I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos) /*!< 0x000000FF */ |
12149 | #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ |
| 12150 | #define I2C_DR_DR I2C_DR_DR_Msk /*!< 8-bit Data Register */ |
12150 | |
| 12151 | 12151 | /******************* Bit definition for I2C_SR1 register ********************/ |
|
| 12152 | /******************* Bit definition for I2C_SR1 register ********************/ |
12152 | #define I2C_SR1_SB_Pos (0U) |
| 12153 | #define I2C_SR1_SB_Pos (0U) |
12153 | #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */ |
| 12154 | #define I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos) /*!< 0x00000001 */ |
12154 | #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ |
| 12155 | #define I2C_SR1_SB I2C_SR1_SB_Msk /*!< Start Bit (Master mode) */ |
12155 | #define I2C_SR1_ADDR_Pos (1U) |
| 12156 | #define I2C_SR1_ADDR_Pos (1U) |
12156 | #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ |
| 12157 | #define I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos) /*!< 0x00000002 */ |
12157 | #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ |
| 12158 | #define I2C_SR1_ADDR I2C_SR1_ADDR_Msk /*!< Address sent (master mode)/matched (slave mode) */ |
12158 | #define I2C_SR1_BTF_Pos (2U) |
| 12159 | #define I2C_SR1_BTF_Pos (2U) |
12159 | #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ |
| 12160 | #define I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos) /*!< 0x00000004 */ |
12160 | #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ |
| 12161 | #define I2C_SR1_BTF I2C_SR1_BTF_Msk /*!< Byte Transfer Finished */ |
12161 | #define I2C_SR1_ADD10_Pos (3U) |
| 12162 | #define I2C_SR1_ADD10_Pos (3U) |
12162 | #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ |
| 12163 | #define I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos) /*!< 0x00000008 */ |
12163 | #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ |
| 12164 | #define I2C_SR1_ADD10 I2C_SR1_ADD10_Msk /*!< 10-bit header sent (Master mode) */ |
12164 | #define I2C_SR1_STOPF_Pos (4U) |
| 12165 | #define I2C_SR1_STOPF_Pos (4U) |
12165 | #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ |
| 12166 | #define I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos) /*!< 0x00000010 */ |
12166 | #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ |
| 12167 | #define I2C_SR1_STOPF I2C_SR1_STOPF_Msk /*!< Stop detection (Slave mode) */ |
12167 | #define I2C_SR1_RXNE_Pos (6U) |
| 12168 | #define I2C_SR1_RXNE_Pos (6U) |
12168 | #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ |
| 12169 | #define I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos) /*!< 0x00000040 */ |
12169 | #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ |
| 12170 | #define I2C_SR1_RXNE I2C_SR1_RXNE_Msk /*!< Data Register not Empty (receivers) */ |
12170 | #define I2C_SR1_TXE_Pos (7U) |
| 12171 | #define I2C_SR1_TXE_Pos (7U) |
12171 | #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ |
| 12172 | #define I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos) /*!< 0x00000080 */ |
12172 | #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ |
| 12173 | #define I2C_SR1_TXE I2C_SR1_TXE_Msk /*!< Data Register Empty (transmitters) */ |
12173 | #define I2C_SR1_BERR_Pos (8U) |
| 12174 | #define I2C_SR1_BERR_Pos (8U) |
12174 | #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ |
| 12175 | #define I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos) /*!< 0x00000100 */ |
12175 | #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ |
| 12176 | #define I2C_SR1_BERR I2C_SR1_BERR_Msk /*!< Bus Error */ |
12176 | #define I2C_SR1_ARLO_Pos (9U) |
| 12177 | #define I2C_SR1_ARLO_Pos (9U) |
12177 | #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ |
| 12178 | #define I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos) /*!< 0x00000200 */ |
12178 | #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ |
| 12179 | #define I2C_SR1_ARLO I2C_SR1_ARLO_Msk /*!< Arbitration Lost (master mode) */ |
12179 | #define I2C_SR1_AF_Pos (10U) |
| 12180 | #define I2C_SR1_AF_Pos (10U) |
12180 | #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */ |
| 12181 | #define I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos) /*!< 0x00000400 */ |
12181 | #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ |
| 12182 | #define I2C_SR1_AF I2C_SR1_AF_Msk /*!< Acknowledge Failure */ |
12182 | #define I2C_SR1_OVR_Pos (11U) |
| 12183 | #define I2C_SR1_OVR_Pos (11U) |
12183 | #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ |
| 12184 | #define I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos) /*!< 0x00000800 */ |
12184 | #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ |
| 12185 | #define I2C_SR1_OVR I2C_SR1_OVR_Msk /*!< Overrun/Underrun */ |
12185 | #define I2C_SR1_PECERR_Pos (12U) |
| 12186 | #define I2C_SR1_PECERR_Pos (12U) |
12186 | #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ |
| 12187 | #define I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos) /*!< 0x00001000 */ |
12187 | #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ |
| 12188 | #define I2C_SR1_PECERR I2C_SR1_PECERR_Msk /*!< PEC Error in reception */ |
12188 | #define I2C_SR1_TIMEOUT_Pos (14U) |
| 12189 | #define I2C_SR1_TIMEOUT_Pos (14U) |
12189 | #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ |
| 12190 | #define I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos) /*!< 0x00004000 */ |
12190 | #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ |
| 12191 | #define I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk /*!< Timeout or Tlow Error */ |
12191 | #define I2C_SR1_SMBALERT_Pos (15U) |
| 12192 | #define I2C_SR1_SMBALERT_Pos (15U) |
12192 | #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ |
| 12193 | #define I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos) /*!< 0x00008000 */ |
12193 | #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ |
| 12194 | #define I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk /*!< SMBus Alert */ |
12194 | |
| 12195 | 12195 | /******************* Bit definition for I2C_SR2 register ********************/ |
|
| 12196 | /******************* Bit definition for I2C_SR2 register ********************/ |
12196 | #define I2C_SR2_MSL_Pos (0U) |
| 12197 | #define I2C_SR2_MSL_Pos (0U) |
12197 | #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ |
| 12198 | #define I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos) /*!< 0x00000001 */ |
12198 | #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ |
| 12199 | #define I2C_SR2_MSL I2C_SR2_MSL_Msk /*!< Master/Slave */ |
12199 | #define I2C_SR2_BUSY_Pos (1U) |
| 12200 | #define I2C_SR2_BUSY_Pos (1U) |
12200 | #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ |
| 12201 | #define I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos) /*!< 0x00000002 */ |
12201 | #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ |
| 12202 | #define I2C_SR2_BUSY I2C_SR2_BUSY_Msk /*!< Bus Busy */ |
12202 | #define I2C_SR2_TRA_Pos (2U) |
| 12203 | #define I2C_SR2_TRA_Pos (2U) |
12203 | #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ |
| 12204 | #define I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos) /*!< 0x00000004 */ |
12204 | #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ |
| 12205 | #define I2C_SR2_TRA I2C_SR2_TRA_Msk /*!< Transmitter/Receiver */ |
12205 | #define I2C_SR2_GENCALL_Pos (4U) |
| 12206 | #define I2C_SR2_GENCALL_Pos (4U) |
12206 | #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ |
| 12207 | #define I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos) /*!< 0x00000010 */ |
12207 | #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ |
| 12208 | #define I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk /*!< General Call Address (Slave mode) */ |
12208 | #define I2C_SR2_SMBDEFAULT_Pos (5U) |
| 12209 | #define I2C_SR2_SMBDEFAULT_Pos (5U) |
12209 | #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ |
| 12210 | #define I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos) /*!< 0x00000020 */ |
12210 | #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ |
| 12211 | #define I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk /*!< SMBus Device Default Address (Slave mode) */ |
12211 | #define I2C_SR2_SMBHOST_Pos (6U) |
| 12212 | #define I2C_SR2_SMBHOST_Pos (6U) |
12212 | #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ |
| 12213 | #define I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos) /*!< 0x00000040 */ |
12213 | #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ |
| 12214 | #define I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk /*!< SMBus Host Header (Slave mode) */ |
12214 | #define I2C_SR2_DUALF_Pos (7U) |
| 12215 | #define I2C_SR2_DUALF_Pos (7U) |
12215 | #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ |
| 12216 | #define I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos) /*!< 0x00000080 */ |
12216 | #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ |
| 12217 | #define I2C_SR2_DUALF I2C_SR2_DUALF_Msk /*!< Dual Flag (Slave mode) */ |
12217 | #define I2C_SR2_PEC_Pos (8U) |
| 12218 | #define I2C_SR2_PEC_Pos (8U) |
12218 | #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ |
| 12219 | #define I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos) /*!< 0x0000FF00 */ |
12219 | #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ |
| 12220 | #define I2C_SR2_PEC I2C_SR2_PEC_Msk /*!< Packet Error Checking Register */ |
12220 | |
| 12221 | 12221 | /******************* Bit definition for I2C_CCR register ********************/ |
|
| 12222 | /******************* Bit definition for I2C_CCR register ********************/ |
12222 | #define I2C_CCR_CCR_Pos (0U) |
| 12223 | #define I2C_CCR_CCR_Pos (0U) |
12223 | #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ |
| 12224 | #define I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos) /*!< 0x00000FFF */ |
12224 | #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ |
| 12225 | #define I2C_CCR_CCR I2C_CCR_CCR_Msk /*!< Clock Control Register in Fast/Standard mode (Master mode) */ |
12225 | #define I2C_CCR_DUTY_Pos (14U) |
| 12226 | #define I2C_CCR_DUTY_Pos (14U) |
12226 | #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ |
| 12227 | #define I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos) /*!< 0x00004000 */ |
12227 | #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ |
| 12228 | #define I2C_CCR_DUTY I2C_CCR_DUTY_Msk /*!< Fast Mode Duty Cycle */ |
12228 | #define I2C_CCR_FS_Pos (15U) |
| 12229 | #define I2C_CCR_FS_Pos (15U) |
12229 | #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */ |
| 12230 | #define I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos) /*!< 0x00008000 */ |
12230 | #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ |
| 12231 | #define I2C_CCR_FS I2C_CCR_FS_Msk /*!< I2C Master Mode Selection */ |
12231 | |
| 12232 | 12232 | /****************** Bit definition for I2C_TRISE register *******************/ |
|
| 12233 | /****************** Bit definition for I2C_TRISE register *******************/ |
12233 | #define I2C_TRISE_TRISE_Pos (0U) |
| 12234 | #define I2C_TRISE_TRISE_Pos (0U) |
12234 | #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ |
| 12235 | #define I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos) /*!< 0x0000003F */ |
12235 | #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ |
| 12236 | #define I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */ |
12236 | |
| 12237 | 12237 | /******************************************************************************/ |
|
| 12238 | /******************************************************************************/ |
12238 | /* */ |
| 12239 | /* */ |
12239 | /* Universal Synchronous Asynchronous Receiver Transmitter */ |
| 12240 | /* Universal Synchronous Asynchronous Receiver Transmitter */ |
12240 | /* */ |
| 12241 | /* */ |
12241 | /******************************************************************************/ |
| 12242 | /******************************************************************************/ |
12242 | |
| 12243 | 12243 | /******************* Bit definition for USART_SR register *******************/ |
|
| 12244 | /******************* Bit definition for USART_SR register *******************/ |
12244 | #define USART_SR_PE_Pos (0U) |
| 12245 | #define USART_SR_PE_Pos (0U) |
12245 | #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */ |
| 12246 | #define USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos) /*!< 0x00000001 */ |
12246 | #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ |
| 12247 | #define USART_SR_PE USART_SR_PE_Msk /*!< Parity Error */ |
12247 | #define USART_SR_FE_Pos (1U) |
| 12248 | #define USART_SR_FE_Pos (1U) |
12248 | #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */ |
| 12249 | #define USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos) /*!< 0x00000002 */ |
12249 | #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ |
| 12250 | #define USART_SR_FE USART_SR_FE_Msk /*!< Framing Error */ |
12250 | #define USART_SR_NE_Pos (2U) |
| 12251 | #define USART_SR_NE_Pos (2U) |
12251 | #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */ |
| 12252 | #define USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos) /*!< 0x00000004 */ |
12252 | #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ |
| 12253 | #define USART_SR_NE USART_SR_NE_Msk /*!< Noise Error Flag */ |
12253 | #define USART_SR_ORE_Pos (3U) |
| 12254 | #define USART_SR_ORE_Pos (3U) |
12254 | #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */ |
| 12255 | #define USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos) /*!< 0x00000008 */ |
12255 | #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ |
| 12256 | #define USART_SR_ORE USART_SR_ORE_Msk /*!< OverRun Error */ |
12256 | #define USART_SR_IDLE_Pos (4U) |
| 12257 | #define USART_SR_IDLE_Pos (4U) |
12257 | #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */ |
| 12258 | #define USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos) /*!< 0x00000010 */ |
12258 | #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ |
| 12259 | #define USART_SR_IDLE USART_SR_IDLE_Msk /*!< IDLE line detected */ |
12259 | #define USART_SR_RXNE_Pos (5U) |
| 12260 | #define USART_SR_RXNE_Pos (5U) |
12260 | #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */ |
| 12261 | #define USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos) /*!< 0x00000020 */ |
12261 | #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ |
| 12262 | #define USART_SR_RXNE USART_SR_RXNE_Msk /*!< Read Data Register Not Empty */ |
12262 | #define USART_SR_TC_Pos (6U) |
| 12263 | #define USART_SR_TC_Pos (6U) |
12263 | #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */ |
| 12264 | #define USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos) /*!< 0x00000040 */ |
12264 | #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ |
| 12265 | #define USART_SR_TC USART_SR_TC_Msk /*!< Transmission Complete */ |
12265 | #define USART_SR_TXE_Pos (7U) |
| 12266 | #define USART_SR_TXE_Pos (7U) |
12266 | #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */ |
| 12267 | #define USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos) /*!< 0x00000080 */ |
12267 | #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ |
| 12268 | #define USART_SR_TXE USART_SR_TXE_Msk /*!< Transmit Data Register Empty */ |
12268 | #define USART_SR_LBD_Pos (8U) |
| 12269 | #define USART_SR_LBD_Pos (8U) |
12269 | #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */ |
| 12270 | #define USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos) /*!< 0x00000100 */ |
12270 | #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ |
| 12271 | #define USART_SR_LBD USART_SR_LBD_Msk /*!< LIN Break Detection Flag */ |
12271 | #define USART_SR_CTS_Pos (9U) |
| 12272 | #define USART_SR_CTS_Pos (9U) |
12272 | #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */ |
| 12273 | #define USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos) /*!< 0x00000200 */ |
12273 | #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ |
| 12274 | #define USART_SR_CTS USART_SR_CTS_Msk /*!< CTS Flag */ |
12274 | |
| 12275 | 12275 | /******************* Bit definition for USART_DR register *******************/ |
|
| 12276 | /******************* Bit definition for USART_DR register *******************/ |
12276 | #define USART_DR_DR_Pos (0U) |
| 12277 | #define USART_DR_DR_Pos (0U) |
12277 | #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */ |
| 12278 | #define USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos) /*!< 0x000001FF */ |
12278 | #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ |
| 12279 | #define USART_DR_DR USART_DR_DR_Msk /*!< Data value */ |
12279 | |
| 12280 | 12280 | /****************** Bit definition for USART_BRR register *******************/ |
|
| 12281 | /****************** Bit definition for USART_BRR register *******************/ |
12281 | #define USART_BRR_DIV_Fraction_Pos (0U) |
| 12282 | #define USART_BRR_DIV_Fraction_Pos (0U) |
12282 | #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ |
| 12283 | #define USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos) /*!< 0x0000000F */ |
12283 | #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */ |
| 12284 | #define USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk /*!< Fraction of USARTDIV */ |
12284 | #define USART_BRR_DIV_Mantissa_Pos (4U) |
| 12285 | #define USART_BRR_DIV_Mantissa_Pos (4U) |
12285 | #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ |
| 12286 | #define USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos) /*!< 0x0000FFF0 */ |
12286 | #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */ |
| 12287 | #define USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk /*!< Mantissa of USARTDIV */ |
12287 | |
| 12288 | 12288 | /****************** Bit definition for USART_CR1 register *******************/ |
|
| 12289 | /****************** Bit definition for USART_CR1 register *******************/ |
12289 | #define USART_CR1_SBK_Pos (0U) |
| 12290 | #define USART_CR1_SBK_Pos (0U) |
12290 | #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */ |
| 12291 | #define USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos) /*!< 0x00000001 */ |
12291 | #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ |
| 12292 | #define USART_CR1_SBK USART_CR1_SBK_Msk /*!< Send Break */ |
12292 | #define USART_CR1_RWU_Pos (1U) |
| 12293 | #define USART_CR1_RWU_Pos (1U) |
12293 | #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */ |
| 12294 | #define USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos) /*!< 0x00000002 */ |
12294 | #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ |
| 12295 | #define USART_CR1_RWU USART_CR1_RWU_Msk /*!< Receiver wakeup */ |
12295 | #define USART_CR1_RE_Pos (2U) |
| 12296 | #define USART_CR1_RE_Pos (2U) |
12296 | #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ |
| 12297 | #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ |
12297 | #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ |
| 12298 | #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ |
12298 | #define USART_CR1_TE_Pos (3U) |
| 12299 | #define USART_CR1_TE_Pos (3U) |
12299 | #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ |
| 12300 | #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ |
12300 | #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ |
| 12301 | #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ |
12301 | #define USART_CR1_IDLEIE_Pos (4U) |
| 12302 | #define USART_CR1_IDLEIE_Pos (4U) |
12302 | #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ |
| 12303 | #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ |
12303 | #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ |
| 12304 | #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ |
12304 | #define USART_CR1_RXNEIE_Pos (5U) |
| 12305 | #define USART_CR1_RXNEIE_Pos (5U) |
12305 | #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ |
| 12306 | #define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ |
12306 | #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ |
| 12307 | #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ |
12307 | #define USART_CR1_TCIE_Pos (6U) |
| 12308 | #define USART_CR1_TCIE_Pos (6U) |
12308 | #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ |
| 12309 | #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ |
12309 | #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ |
| 12310 | #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ |
12310 | #define USART_CR1_TXEIE_Pos (7U) |
| 12311 | #define USART_CR1_TXEIE_Pos (7U) |
12311 | #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ |
| 12312 | #define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ |
12312 | #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ |
| 12313 | #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< PE Interrupt Enable */ |
12313 | #define USART_CR1_PEIE_Pos (8U) |
| 12314 | #define USART_CR1_PEIE_Pos (8U) |
12314 | #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ |
| 12315 | #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ |
12315 | #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ |
| 12316 | #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ |
12316 | #define USART_CR1_PS_Pos (9U) |
| 12317 | #define USART_CR1_PS_Pos (9U) |
12317 | #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ |
| 12318 | #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ |
12318 | #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ |
| 12319 | #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ |
12319 | #define USART_CR1_PCE_Pos (10U) |
| 12320 | #define USART_CR1_PCE_Pos (10U) |
12320 | #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ |
| 12321 | #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ |
12321 | #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ |
| 12322 | #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ |
12322 | #define USART_CR1_WAKE_Pos (11U) |
| 12323 | #define USART_CR1_WAKE_Pos (11U) |
12323 | #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ |
| 12324 | #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ |
12324 | #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ |
| 12325 | #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Wakeup method */ |
12325 | #define USART_CR1_M_Pos (12U) |
| 12326 | #define USART_CR1_M_Pos (12U) |
12326 | #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ |
| 12327 | #define USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos) /*!< 0x00001000 */ |
12327 | #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ |
| 12328 | #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ |
12328 | #define USART_CR1_UE_Pos (13U) |
| 12329 | #define USART_CR1_UE_Pos (13U) |
12329 | #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */ |
| 12330 | #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00002000 */ |
12330 | #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ |
| 12331 | #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ |
12331 | |
| 12332 | 12332 | /****************** Bit definition for USART_CR2 register *******************/ |
|
| 12333 | /****************** Bit definition for USART_CR2 register *******************/ |
12333 | #define USART_CR2_ADD_Pos (0U) |
| 12334 | #define USART_CR2_ADD_Pos (0U) |
12334 | #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */ |
| 12335 | #define USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos) /*!< 0x0000000F */ |
12335 | #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ |
| 12336 | #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ |
12336 | #define USART_CR2_LBDL_Pos (5U) |
| 12337 | #define USART_CR2_LBDL_Pos (5U) |
12337 | #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ |
| 12338 | #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ |
12338 | #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ |
| 12339 | #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ |
12339 | #define USART_CR2_LBDIE_Pos (6U) |
| 12340 | #define USART_CR2_LBDIE_Pos (6U) |
12340 | #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ |
| 12341 | #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ |
12341 | #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ |
| 12342 | #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ |
12342 | #define USART_CR2_LBCL_Pos (8U) |
| 12343 | #define USART_CR2_LBCL_Pos (8U) |
12343 | #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ |
| 12344 | #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ |
12344 | #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ |
| 12345 | #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ |
12345 | #define USART_CR2_CPHA_Pos (9U) |
| 12346 | #define USART_CR2_CPHA_Pos (9U) |
12346 | #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ |
| 12347 | #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ |
12347 | #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ |
| 12348 | #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ |
12348 | #define USART_CR2_CPOL_Pos (10U) |
| 12349 | #define USART_CR2_CPOL_Pos (10U) |
12349 | #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ |
| 12350 | #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ |
12350 | #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ |
| 12351 | #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ |
12351 | #define USART_CR2_CLKEN_Pos (11U) |
| 12352 | #define USART_CR2_CLKEN_Pos (11U) |
12352 | #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ |
| 12353 | #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ |
12353 | #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ |
| 12354 | #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ |
12354 | |
| 12355 | 12355 | #define USART_CR2_STOP_Pos (12U) |
|
| 12356 | #define USART_CR2_STOP_Pos (12U) |
12356 | #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ |
| 12357 | #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ |
12357 | #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ |
| 12358 | #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ |
12358 | #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ |
| 12359 | #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ |
12359 | #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ |
| 12360 | #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ |
12360 | |
| 12361 | 12361 | #define USART_CR2_LINEN_Pos (14U) |
|
| 12362 | #define USART_CR2_LINEN_Pos (14U) |
12362 | #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ |
| 12363 | #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ |
12363 | #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ |
| 12364 | #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ |
12364 | |
| 12365 | 12365 | /****************** Bit definition for USART_CR3 register *******************/ |
|
| 12366 | /****************** Bit definition for USART_CR3 register *******************/ |
12366 | #define USART_CR3_EIE_Pos (0U) |
| 12367 | #define USART_CR3_EIE_Pos (0U) |
12367 | #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ |
| 12368 | #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ |
12368 | #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ |
| 12369 | #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ |
12369 | #define USART_CR3_IREN_Pos (1U) |
| 12370 | #define USART_CR3_IREN_Pos (1U) |
12370 | #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ |
| 12371 | #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ |
12371 | #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ |
| 12372 | #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ |
12372 | #define USART_CR3_IRLP_Pos (2U) |
| 12373 | #define USART_CR3_IRLP_Pos (2U) |
12373 | #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ |
| 12374 | #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ |
12374 | #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ |
| 12375 | #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ |
12375 | #define USART_CR3_HDSEL_Pos (3U) |
| 12376 | #define USART_CR3_HDSEL_Pos (3U) |
12376 | #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ |
| 12377 | #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ |
12377 | #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ |
| 12378 | #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ |
12378 | #define USART_CR3_NACK_Pos (4U) |
| 12379 | #define USART_CR3_NACK_Pos (4U) |
12379 | #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ |
| 12380 | #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ |
12380 | #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ |
| 12381 | #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< Smartcard NACK enable */ |
12381 | #define USART_CR3_SCEN_Pos (5U) |
| 12382 | #define USART_CR3_SCEN_Pos (5U) |
12382 | #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ |
| 12383 | #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ |
12383 | #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ |
| 12384 | #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< Smartcard mode enable */ |
12384 | #define USART_CR3_DMAR_Pos (6U) |
| 12385 | #define USART_CR3_DMAR_Pos (6U) |
12385 | #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ |
| 12386 | #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ |
12386 | #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ |
| 12387 | #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ |
12387 | #define USART_CR3_DMAT_Pos (7U) |
| 12388 | #define USART_CR3_DMAT_Pos (7U) |
12388 | #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ |
| 12389 | #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ |
12389 | #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ |
| 12390 | #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ |
12390 | #define USART_CR3_RTSE_Pos (8U) |
| 12391 | #define USART_CR3_RTSE_Pos (8U) |
12391 | #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ |
| 12392 | #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ |
12392 | #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ |
| 12393 | #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ |
12393 | #define USART_CR3_CTSE_Pos (9U) |
| 12394 | #define USART_CR3_CTSE_Pos (9U) |
12394 | #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ |
| 12395 | #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ |
12395 | #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ |
| 12396 | #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ |
12396 | #define USART_CR3_CTSIE_Pos (10U) |
| 12397 | #define USART_CR3_CTSIE_Pos (10U) |
12397 | #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ |
| 12398 | #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ |
12398 | #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ |
| 12399 | #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ |
12399 | |
| 12400 | 12400 | /****************** Bit definition for USART_GTPR register ******************/ |
|
| 12401 | /****************** Bit definition for USART_GTPR register ******************/ |
12401 | #define USART_GTPR_PSC_Pos (0U) |
| 12402 | #define USART_GTPR_PSC_Pos (0U) |
12402 | #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ |
| 12403 | #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ |
12403 | #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ |
| 12404 | #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ |
12404 | #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ |
| 12405 | #define USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos) /*!< 0x00000001 */ |
12405 | #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ |
| 12406 | #define USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos) /*!< 0x00000002 */ |
12406 | #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ |
| 12407 | #define USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos) /*!< 0x00000004 */ |
12407 | #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ |
| 12408 | #define USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos) /*!< 0x00000008 */ |
12408 | #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ |
| 12409 | #define USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos) /*!< 0x00000010 */ |
12409 | #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ |
| 12410 | #define USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos) /*!< 0x00000020 */ |
12410 | #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ |
| 12411 | #define USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos) /*!< 0x00000040 */ |
12411 | #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ |
| 12412 | #define USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos) /*!< 0x00000080 */ |
12412 | |
| 12413 | 12413 | #define USART_GTPR_GT_Pos (8U) |
|
| 12414 | #define USART_GTPR_GT_Pos (8U) |
12414 | #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ |
| 12415 | #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ |
12415 | #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ |
| 12416 | #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< Guard time value */ |
12416 | |
| 12417 | 12417 | /******************************************************************************/ |
|
| 12418 | /******************************************************************************/ |
12418 | /* */ |
| 12419 | /* */ |
12419 | /* Debug MCU */ |
| 12420 | /* Debug MCU */ |
12420 | /* */ |
| 12421 | /* */ |
12421 | /******************************************************************************/ |
| 12422 | /******************************************************************************/ |
12422 | |
| 12423 | 12423 | /**************** Bit definition for DBGMCU_IDCODE register *****************/ |
|
| 12424 | /**************** Bit definition for DBGMCU_IDCODE register *****************/ |
12424 | #define DBGMCU_IDCODE_DEV_ID_Pos (0U) |
| 12425 | #define DBGMCU_IDCODE_DEV_ID_Pos (0U) |
12425 | #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ |
| 12426 | #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ |
12426 | #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ |
| 12427 | #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */ |
12427 | |
| 12428 | 12428 | #define DBGMCU_IDCODE_REV_ID_Pos (16U) |
|
| 12429 | #define DBGMCU_IDCODE_REV_ID_Pos (16U) |
12429 | #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ |
| 12430 | #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ |
12430 | #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ |
| 12431 | #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */ |
12431 | #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ |
| 12432 | #define DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */ |
12432 | #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ |
| 12433 | #define DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */ |
12433 | #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ |
| 12434 | #define DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */ |
12434 | #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ |
| 12435 | #define DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */ |
12435 | #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ |
| 12436 | #define DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */ |
12436 | #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ |
| 12437 | #define DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */ |
12437 | #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ |
| 12438 | #define DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */ |
12438 | #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ |
| 12439 | #define DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */ |
12439 | #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ |
| 12440 | #define DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */ |
12440 | #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ |
| 12441 | #define DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */ |
12441 | #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ |
| 12442 | #define DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */ |
12442 | #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ |
| 12443 | #define DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */ |
12443 | #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ |
| 12444 | #define DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */ |
12444 | #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ |
| 12445 | #define DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */ |
12445 | #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ |
| 12446 | #define DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */ |
12446 | #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ |
| 12447 | #define DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */ |
12447 | |
| 12448 | 12448 | /****************** Bit definition for DBGMCU_CR register *******************/ |
|
| 12449 | /****************** Bit definition for DBGMCU_CR register *******************/ |
12449 | #define DBGMCU_CR_DBG_SLEEP_Pos (0U) |
| 12450 | #define DBGMCU_CR_DBG_SLEEP_Pos (0U) |
12450 | #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ |
| 12451 | #define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ |
12451 | #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ |
| 12452 | #define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk /*!< Debug Sleep Mode */ |
12452 | #define DBGMCU_CR_DBG_STOP_Pos (1U) |
| 12453 | #define DBGMCU_CR_DBG_STOP_Pos (1U) |
12453 | #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ |
| 12454 | #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ |
12454 | #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ |
| 12455 | #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */ |
12455 | #define DBGMCU_CR_DBG_STANDBY_Pos (2U) |
| 12456 | #define DBGMCU_CR_DBG_STANDBY_Pos (2U) |
12456 | #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ |
| 12457 | #define DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */ |
12457 | #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ |
| 12458 | #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */ |
12458 | #define DBGMCU_CR_TRACE_IOEN_Pos (5U) |
| 12459 | #define DBGMCU_CR_TRACE_IOEN_Pos (5U) |
12459 | #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ |
| 12460 | #define DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos) /*!< 0x00000020 */ |
12460 | #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ |
| 12461 | #define DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk /*!< Trace Pin Assignment Control */ |
12461 | |
| 12462 | 12462 | #define DBGMCU_CR_TRACE_MODE_Pos (6U) |
|
| 12463 | #define DBGMCU_CR_TRACE_MODE_Pos (6U) |
12463 | #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ |
| 12464 | #define DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x000000C0 */ |
12464 | #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ |
| 12465 | #define DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */ |
12465 | #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ |
| 12466 | #define DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000040 */ |
12466 | #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ |
| 12467 | #define DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos) /*!< 0x00000080 */ |
12467 | |
| 12468 | 12468 | #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) |
|
| 12469 | #define DBGMCU_CR_DBG_IWDG_STOP_Pos (8U) |
12469 | #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */ |
| 12470 | #define DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos) /*!< 0x00000100 */ |
12470 | #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ |
| 12471 | #define DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */ |
12471 | #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) |
| 12472 | #define DBGMCU_CR_DBG_WWDG_STOP_Pos (9U) |
12472 | #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */ |
| 12473 | #define DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos) /*!< 0x00000200 */ |
12473 | #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ |
| 12474 | #define DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */ |
12474 | #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U) |
| 12475 | #define DBGMCU_CR_DBG_TIM1_STOP_Pos (10U) |
12475 | #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */ |
| 12476 | #define DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos) /*!< 0x00000400 */ |
12476 | #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ |
| 12477 | #define DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */ |
12477 | #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) |
| 12478 | #define DBGMCU_CR_DBG_TIM2_STOP_Pos (11U) |
12478 | #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */ |
| 12479 | #define DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos) /*!< 0x00000800 */ |
12479 | #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ |
| 12480 | #define DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */ |
12480 | #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) |
| 12481 | #define DBGMCU_CR_DBG_TIM3_STOP_Pos (12U) |
12481 | #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */ |
| 12482 | #define DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos) /*!< 0x00001000 */ |
12482 | #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ |
| 12483 | #define DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */ |
12483 | #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U) |
| 12484 | #define DBGMCU_CR_DBG_TIM4_STOP_Pos (13U) |
12484 | #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */ |
| 12485 | #define DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos) /*!< 0x00002000 */ |
12485 | #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ |
| 12486 | #define DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk /*!< TIM4 counter stopped when core is halted */ |
12486 | #define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U) |
| 12487 | #define DBGMCU_CR_DBG_CAN1_STOP_Pos (14U) |
12487 | #define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */ |
| 12488 | #define DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos) /*!< 0x00004000 */ |
12488 | #define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */ |
| 12489 | #define DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk /*!< Debug CAN1 stopped when Core is halted */ |
12489 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) |
| 12490 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U) |
12490 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */ |
| 12491 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00008000 */ |
12491 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ |
| 12492 | #define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ |
12492 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U) |
| 12493 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U) |
12493 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */ |
| 12494 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00010000 */ |
12494 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ |
| 12495 | #define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk /*!< SMBUS timeout mode stopped when Core is halted */ |
12495 | #define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U) |
| 12496 | #define DBGMCU_CR_DBG_TIM5_STOP_Pos (18U) |
12496 | #define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */ |
| 12497 | #define DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM5_STOP_Pos) /*!< 0x00040000 */ |
12497 | #define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */ |
| 12498 | #define DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk /*!< TIM5 counter stopped when core is halted */ |
12498 | #define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U) |
| 12499 | #define DBGMCU_CR_DBG_TIM6_STOP_Pos (19U) |
12499 | #define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */ |
| 12500 | #define DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM6_STOP_Pos) /*!< 0x00080000 */ |
12500 | #define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ |
| 12501 | #define DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk /*!< TIM6 counter stopped when core is halted */ |
12501 | #define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U) |
| 12502 | #define DBGMCU_CR_DBG_TIM7_STOP_Pos (20U) |
12502 | #define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */ |
| 12503 | #define DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM7_STOP_Pos) /*!< 0x00100000 */ |
12503 | #define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */ |
| 12504 | #define DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk /*!< TIM7 counter stopped when core is halted */ |
12504 | #define DBGMCU_CR_DBG_CAN2_STOP_Pos (21U) |
| 12505 | #define DBGMCU_CR_DBG_CAN2_STOP_Pos (21U) |
12505 | #define DBGMCU_CR_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN2_STOP_Pos) /*!< 0x00200000 */ |
| 12506 | #define DBGMCU_CR_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN2_STOP_Pos) /*!< 0x00200000 */ |
12506 | #define DBGMCU_CR_DBG_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP_Msk /*!< Debug CAN2 stopped when Core is halted */ |
| 12507 | #define DBGMCU_CR_DBG_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP_Msk /*!< Debug CAN2 stopped when Core is halted */ |
12507 | #define DBGMCU_CR_DBG_TIM9_STOP_Pos (28U) |
| 12508 | #define DBGMCU_CR_DBG_TIM9_STOP_Pos (28U) |
12508 | #define DBGMCU_CR_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM9_STOP_Pos) /*!< 0x10000000 */ |
| 12509 | #define DBGMCU_CR_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM9_STOP_Pos) /*!< 0x10000000 */ |
12509 | #define DBGMCU_CR_DBG_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP_Msk /*!< Debug TIM9 stopped when Core is halted */ |
| 12510 | #define DBGMCU_CR_DBG_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP_Msk /*!< Debug TIM9 stopped when Core is halted */ |
12510 | #define DBGMCU_CR_DBG_TIM10_STOP_Pos (29U) |
| 12511 | #define DBGMCU_CR_DBG_TIM10_STOP_Pos (29U) |
12511 | #define DBGMCU_CR_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM10_STOP_Pos) /*!< 0x20000000 */ |
| 12512 | #define DBGMCU_CR_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM10_STOP_Pos) /*!< 0x20000000 */ |
12512 | #define DBGMCU_CR_DBG_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP_Msk /*!< Debug TIM10 stopped when Core is halted */ |
| 12513 | #define DBGMCU_CR_DBG_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP_Msk /*!< Debug TIM10 stopped when Core is halted */ |
12513 | #define DBGMCU_CR_DBG_TIM11_STOP_Pos (30U) |
| 12514 | #define DBGMCU_CR_DBG_TIM11_STOP_Pos (30U) |
12514 | #define DBGMCU_CR_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM11_STOP_Pos) /*!< 0x40000000 */ |
| 12515 | #define DBGMCU_CR_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM11_STOP_Pos) /*!< 0x40000000 */ |
12515 | #define DBGMCU_CR_DBG_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP_Msk /*!< Debug TIM11 stopped when Core is halted */ |
| 12516 | #define DBGMCU_CR_DBG_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP_Msk /*!< Debug TIM11 stopped when Core is halted */ |
12516 | |
| 12517 | 12517 | /******************************************************************************/ |
|
| 12518 | /******************************************************************************/ |
12518 | /* */ |
| 12519 | /* */ |
12519 | /* FLASH and Option Bytes Registers */ |
| 12520 | /* FLASH and Option Bytes Registers */ |
12520 | /* */ |
| 12521 | /* */ |
12521 | /******************************************************************************/ |
| 12522 | /******************************************************************************/ |
12522 | /******************* Bit definition for FLASH_ACR register ******************/ |
| 12523 | /******************* Bit definition for FLASH_ACR register ******************/ |
12523 | #define FLASH_ACR_LATENCY_Pos (0U) |
| 12524 | #define FLASH_ACR_LATENCY_Pos (0U) |
12524 | #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ |
| 12525 | #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ |
12525 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */ |
| 12526 | #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY[2:0] bits (Latency) */ |
12526 | #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
| 12527 | #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ |
12527 | #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ |
| 12528 | #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ |
12528 | #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ |
| 12529 | #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ |
12529 | |
| 12530 | 12530 | #define FLASH_ACR_HLFCYA_Pos (3U) |
|
| 12531 | #define FLASH_ACR_HLFCYA_Pos (3U) |
12531 | #define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ |
| 12532 | #define FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos) /*!< 0x00000008 */ |
12532 | #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ |
| 12533 | #define FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk /*!< Flash Half Cycle Access Enable */ |
12533 | #define FLASH_ACR_PRFTBE_Pos (4U) |
| 12534 | #define FLASH_ACR_PRFTBE_Pos (4U) |
12534 | #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ |
| 12535 | #define FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */ |
12535 | #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ |
| 12536 | #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */ |
12536 | #define FLASH_ACR_PRFTBS_Pos (5U) |
| 12537 | #define FLASH_ACR_PRFTBS_Pos (5U) |
12537 | #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ |
| 12538 | #define FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */ |
12538 | #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ |
| 12539 | #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */ |
12539 | |
| 12540 | 12540 | /****************** Bit definition for FLASH_KEYR register ******************/ |
|
| 12541 | /****************** Bit definition for FLASH_KEYR register ******************/ |
12541 | #define FLASH_KEYR_FKEYR_Pos (0U) |
| 12542 | #define FLASH_KEYR_FKEYR_Pos (0U) |
12542 | #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ |
| 12543 | #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */ |
12543 | #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ |
| 12544 | #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */ |
12544 | |
| 12545 | 12545 | #define RDP_KEY_Pos (0U) |
|
| 12546 | #define RDP_KEY_Pos (0U) |
12546 | #define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos) /*!< 0x000000A5 */ |
| 12547 | #define RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos) /*!< 0x000000A5 */ |
12547 | #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ |
| 12548 | #define RDP_KEY RDP_KEY_Msk /*!< RDP Key */ |
12548 | #define FLASH_KEY1_Pos (0U) |
| 12549 | #define FLASH_KEY1_Pos (0U) |
12549 | #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ |
| 12550 | #define FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos) /*!< 0x45670123 */ |
12550 | #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ |
| 12551 | #define FLASH_KEY1 FLASH_KEY1_Msk /*!< FPEC Key1 */ |
12551 | #define FLASH_KEY2_Pos (0U) |
| 12552 | #define FLASH_KEY2_Pos (0U) |
12552 | #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ |
| 12553 | #define FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */ |
12553 | #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ |
| 12554 | #define FLASH_KEY2 FLASH_KEY2_Msk /*!< FPEC Key2 */ |
12554 | |
| 12555 | 12555 | /***************** Bit definition for FLASH_OPTKEYR register ****************/ |
|
| 12556 | /***************** Bit definition for FLASH_OPTKEYR register ****************/ |
12556 | #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) |
| 12557 | #define FLASH_OPTKEYR_OPTKEYR_Pos (0U) |
12557 | #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ |
| 12558 | #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */ |
12558 | #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ |
| 12559 | #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */ |
12559 | |
| 12560 | 12560 | #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ |
|
| 12561 | #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */ |
12561 | #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ |
| 12562 | #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */ |
12562 | |
| 12563 | 12563 | /****************** Bit definition for FLASH_SR register ********************/ |
|
| 12564 | /****************** Bit definition for FLASH_SR register ********************/ |
12564 | #define FLASH_SR_BSY_Pos (0U) |
| 12565 | #define FLASH_SR_BSY_Pos (0U) |
12565 | #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ |
| 12566 | #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ |
12566 | #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ |
| 12567 | #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */ |
12567 | #define FLASH_SR_PGERR_Pos (2U) |
| 12568 | #define FLASH_SR_PGERR_Pos (2U) |
12568 | #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ |
| 12569 | #define FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */ |
12569 | #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ |
| 12570 | #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */ |
12570 | #define FLASH_SR_WRPRTERR_Pos (4U) |
| 12571 | #define FLASH_SR_WRPRTERR_Pos (4U) |
12571 | #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ |
| 12572 | #define FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */ |
12572 | #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ |
| 12573 | #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */ |
12573 | #define FLASH_SR_EOP_Pos (5U) |
| 12574 | #define FLASH_SR_EOP_Pos (5U) |
12574 | #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ |
| 12575 | #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000020 */ |
12575 | #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ |
| 12576 | #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */ |
12576 | |
| 12577 | 12577 | /******************* Bit definition for FLASH_CR register *******************/ |
|
| 12578 | /******************* Bit definition for FLASH_CR register *******************/ |
12578 | #define FLASH_CR_PG_Pos (0U) |
| 12579 | #define FLASH_CR_PG_Pos (0U) |
12579 | #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ |
| 12580 | #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ |
12580 | #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ |
| 12581 | #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */ |
12581 | #define FLASH_CR_PER_Pos (1U) |
| 12582 | #define FLASH_CR_PER_Pos (1U) |
12582 | #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ |
| 12583 | #define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ |
12583 | #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ |
| 12584 | #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */ |
12584 | #define FLASH_CR_MER_Pos (2U) |
| 12585 | #define FLASH_CR_MER_Pos (2U) |
12585 | #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ |
| 12586 | #define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ |
12586 | #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ |
| 12587 | #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */ |
12587 | #define FLASH_CR_OPTPG_Pos (4U) |
| 12588 | #define FLASH_CR_OPTPG_Pos (4U) |
12588 | #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ |
| 12589 | #define FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */ |
12589 | #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ |
| 12590 | #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */ |
12590 | #define FLASH_CR_OPTER_Pos (5U) |
| 12591 | #define FLASH_CR_OPTER_Pos (5U) |
12591 | #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ |
| 12592 | #define FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */ |
12592 | #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ |
| 12593 | #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */ |
12593 | #define FLASH_CR_STRT_Pos (6U) |
| 12594 | #define FLASH_CR_STRT_Pos (6U) |
12594 | #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ |
| 12595 | #define FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos) /*!< 0x00000040 */ |
12595 | #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ |
| 12596 | #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */ |
12596 | #define FLASH_CR_LOCK_Pos (7U) |
| 12597 | #define FLASH_CR_LOCK_Pos (7U) |
12597 | #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ |
| 12598 | #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */ |
12598 | #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ |
| 12599 | #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */ |
12599 | #define FLASH_CR_OPTWRE_Pos (9U) |
| 12600 | #define FLASH_CR_OPTWRE_Pos (9U) |
12600 | #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ |
| 12601 | #define FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */ |
12601 | #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ |
| 12602 | #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */ |
12602 | #define FLASH_CR_ERRIE_Pos (10U) |
| 12603 | #define FLASH_CR_ERRIE_Pos (10U) |
12603 | #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ |
| 12604 | #define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */ |
12604 | #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ |
| 12605 | #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */ |
12605 | #define FLASH_CR_EOPIE_Pos (12U) |
| 12606 | #define FLASH_CR_EOPIE_Pos (12U) |
12606 | #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ |
| 12607 | #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */ |
12607 | #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ |
| 12608 | #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */ |
12608 | |
| 12609 | 12609 | /******************* Bit definition for FLASH_AR register *******************/ |
|
| 12610 | /******************* Bit definition for FLASH_AR register *******************/ |
12610 | #define FLASH_AR_FAR_Pos (0U) |
| 12611 | #define FLASH_AR_FAR_Pos (0U) |
12611 | #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ |
| 12612 | #define FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */ |
12612 | #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ |
| 12613 | #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */ |
12613 | |
| 12614 | 12614 | /****************** Bit definition for FLASH_OBR register *******************/ |
|
| 12615 | /****************** Bit definition for FLASH_OBR register *******************/ |
12615 | #define FLASH_OBR_OPTERR_Pos (0U) |
| 12616 | #define FLASH_OBR_OPTERR_Pos (0U) |
12616 | #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ |
| 12617 | #define FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */ |
12617 | #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ |
| 12618 | #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */ |
12618 | #define FLASH_OBR_RDPRT_Pos (1U) |
| 12619 | #define FLASH_OBR_RDPRT_Pos (1U) |
12619 | #define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ |
| 12620 | #define FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos) /*!< 0x00000002 */ |
12620 | #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ |
| 12621 | #define FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk /*!< Read protection */ |
12621 | |
| 12622 | 12622 | #define FLASH_OBR_IWDG_SW_Pos (2U) |
|
| 12623 | #define FLASH_OBR_IWDG_SW_Pos (2U) |
12623 | #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */ |
| 12624 | #define FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000004 */ |
12624 | #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ |
| 12625 | #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */ |
12625 | #define FLASH_OBR_nRST_STOP_Pos (3U) |
| 12626 | #define FLASH_OBR_nRST_STOP_Pos (3U) |
12626 | #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */ |
| 12627 | #define FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000008 */ |
12627 | #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ |
| 12628 | #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */ |
12628 | #define FLASH_OBR_nRST_STDBY_Pos (4U) |
| 12629 | #define FLASH_OBR_nRST_STDBY_Pos (4U) |
12629 | #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */ |
| 12630 | #define FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000010 */ |
12630 | #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ |
| 12631 | #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */ |
12631 | #define FLASH_OBR_USER_Pos (2U) |
| 12632 | #define FLASH_OBR_USER_Pos (2U) |
12632 | #define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos) /*!< 0x0000001C */ |
| 12633 | #define FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos) /*!< 0x0000001C */ |
12633 | #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ |
| 12634 | #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */ |
12634 | #define FLASH_OBR_DATA0_Pos (10U) |
| 12635 | #define FLASH_OBR_DATA0_Pos (10U) |
12635 | #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */ |
| 12636 | #define FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos) /*!< 0x0003FC00 */ |
12636 | #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ |
| 12637 | #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */ |
12637 | #define FLASH_OBR_DATA1_Pos (18U) |
| 12638 | #define FLASH_OBR_DATA1_Pos (18U) |
12638 | #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */ |
| 12639 | #define FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos) /*!< 0x03FC0000 */ |
12639 | #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ |
| 12640 | #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */ |
12640 | |
| 12641 | 12641 | /****************** Bit definition for FLASH_WRPR register ******************/ |
|
| 12642 | /****************** Bit definition for FLASH_WRPR register ******************/ |
12642 | #define FLASH_WRPR_WRP_Pos (0U) |
| 12643 | #define FLASH_WRPR_WRP_Pos (0U) |
12643 | #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ |
| 12644 | #define FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos) /*!< 0xFFFFFFFF */ |
12644 | #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ |
| 12645 | #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */ |
12645 | |
| 12646 | 12646 | /*----------------------------------------------------------------------------*/ |
|
| 12647 | /*----------------------------------------------------------------------------*/ |
12647 | |
| 12648 | 12648 | /****************** Bit definition for FLASH_RDP register *******************/ |
|
| 12649 | /****************** Bit definition for FLASH_RDP register *******************/ |
12649 | #define FLASH_RDP_RDP_Pos (0U) |
| 12650 | #define FLASH_RDP_RDP_Pos (0U) |
12650 | #define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */ |
| 12651 | #define FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos) /*!< 0x000000FF */ |
12651 | #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */ |
| 12652 | #define FLASH_RDP_RDP FLASH_RDP_RDP_Msk /*!< Read protection option byte */ |
12652 | #define FLASH_RDP_nRDP_Pos (8U) |
| 12653 | #define FLASH_RDP_nRDP_Pos (8U) |
12653 | #define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */ |
| 12654 | #define FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos) /*!< 0x0000FF00 */ |
12654 | #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */ |
| 12655 | #define FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk /*!< Read protection complemented option byte */ |
12655 | |
| 12656 | 12656 | /****************** Bit definition for FLASH_USER register ******************/ |
|
| 12657 | /****************** Bit definition for FLASH_USER register ******************/ |
12657 | #define FLASH_USER_USER_Pos (16U) |
| 12658 | #define FLASH_USER_USER_Pos (16U) |
12658 | #define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */ |
| 12659 | #define FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos) /*!< 0x00FF0000 */ |
12659 | #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */ |
| 12660 | #define FLASH_USER_USER FLASH_USER_USER_Msk /*!< User option byte */ |
12660 | #define FLASH_USER_nUSER_Pos (24U) |
| 12661 | #define FLASH_USER_nUSER_Pos (24U) |
12661 | #define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */ |
| 12662 | #define FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos) /*!< 0xFF000000 */ |
12662 | #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */ |
| 12663 | #define FLASH_USER_nUSER FLASH_USER_nUSER_Msk /*!< User complemented option byte */ |
12663 | |
| 12664 | 12664 | /****************** Bit definition for FLASH_Data0 register *****************/ |
|
| 12665 | /****************** Bit definition for FLASH_Data0 register *****************/ |
12665 | #define FLASH_DATA0_DATA0_Pos (0U) |
| 12666 | #define FLASH_DATA0_DATA0_Pos (0U) |
12666 | #define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ |
| 12667 | #define FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos) /*!< 0x000000FF */ |
12667 | #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */ |
| 12668 | #define FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk /*!< User data storage option byte */ |
12668 | #define FLASH_DATA0_nDATA0_Pos (8U) |
| 12669 | #define FLASH_DATA0_nDATA0_Pos (8U) |
12669 | #define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ |
| 12670 | #define FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos) /*!< 0x0000FF00 */ |
12670 | #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */ |
| 12671 | #define FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk /*!< User data storage complemented option byte */ |
12671 | |
| 12672 | 12672 | /****************** Bit definition for FLASH_Data1 register *****************/ |
|
| 12673 | /****************** Bit definition for FLASH_Data1 register *****************/ |
12673 | #define FLASH_DATA1_DATA1_Pos (16U) |
| 12674 | #define FLASH_DATA1_DATA1_Pos (16U) |
12674 | #define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ |
| 12675 | #define FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos) /*!< 0x00FF0000 */ |
12675 | #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */ |
| 12676 | #define FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk /*!< User data storage option byte */ |
12676 | #define FLASH_DATA1_nDATA1_Pos (24U) |
| 12677 | #define FLASH_DATA1_nDATA1_Pos (24U) |
12677 | #define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ |
| 12678 | #define FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos) /*!< 0xFF000000 */ |
12678 | #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */ |
| 12679 | #define FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk /*!< User data storage complemented option byte */ |
12679 | |
| 12680 | 12680 | /****************** Bit definition for FLASH_WRP0 register ******************/ |
|
| 12681 | /****************** Bit definition for FLASH_WRP0 register ******************/ |
12681 | #define FLASH_WRP0_WRP0_Pos (0U) |
| 12682 | #define FLASH_WRP0_WRP0_Pos (0U) |
12682 | #define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */ |
| 12683 | #define FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos) /*!< 0x000000FF */ |
12683 | #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ |
| 12684 | #define FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */ |
12684 | #define FLASH_WRP0_nWRP0_Pos (8U) |
| 12685 | #define FLASH_WRP0_nWRP0_Pos (8U) |
12685 | #define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ |
| 12686 | #define FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */ |
12686 | #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ |
| 12687 | #define FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */ |
12687 | |
| 12688 | 12688 | /****************** Bit definition for FLASH_WRP1 register ******************/ |
|
| 12689 | /****************** Bit definition for FLASH_WRP1 register ******************/ |
12689 | #define FLASH_WRP1_WRP1_Pos (16U) |
| 12690 | #define FLASH_WRP1_WRP1_Pos (16U) |
12690 | #define FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ |
| 12691 | #define FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos) /*!< 0x00FF0000 */ |
12691 | #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ |
| 12692 | #define FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk /*!< Flash memory write protection option bytes */ |
12692 | #define FLASH_WRP1_nWRP1_Pos (24U) |
| 12693 | #define FLASH_WRP1_nWRP1_Pos (24U) |
12693 | #define FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ |
| 12694 | #define FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos) /*!< 0xFF000000 */ |
12694 | #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ |
| 12695 | #define FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk /*!< Flash memory write protection complemented option bytes */ |
12695 | |
| 12696 | 12696 | /****************** Bit definition for FLASH_WRP2 register ******************/ |
|
| 12697 | /****************** Bit definition for FLASH_WRP2 register ******************/ |
12697 | #define FLASH_WRP2_WRP2_Pos (0U) |
| 12698 | #define FLASH_WRP2_WRP2_Pos (0U) |
12698 | #define FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */ |
| 12699 | #define FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos) /*!< 0x000000FF */ |
12699 | #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ |
| 12700 | #define FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk /*!< Flash memory write protection option bytes */ |
12700 | #define FLASH_WRP2_nWRP2_Pos (8U) |
| 12701 | #define FLASH_WRP2_nWRP2_Pos (8U) |
12701 | #define FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ |
| 12702 | #define FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos) /*!< 0x0000FF00 */ |
12702 | #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ |
| 12703 | #define FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk /*!< Flash memory write protection complemented option bytes */ |
12703 | |
| 12704 | 12704 | /****************** Bit definition for FLASH_WRP3 register ******************/ |
|
| 12705 | /****************** Bit definition for FLASH_WRP3 register ******************/ |
12705 | #define FLASH_WRP3_WRP3_Pos (16U) |
| 12706 | #define FLASH_WRP3_WRP3_Pos (16U) |
12706 | #define FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ |
| 12707 | #define FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos) /*!< 0x00FF0000 */ |
12707 | #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ |
| 12708 | #define FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk /*!< Flash memory write protection option bytes */ |
12708 | #define FLASH_WRP3_nWRP3_Pos (24U) |
| 12709 | #define FLASH_WRP3_nWRP3_Pos (24U) |
12709 | #define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ |
| 12710 | #define FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos) /*!< 0xFF000000 */ |
12710 | #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ |
| 12711 | #define FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk /*!< Flash memory write protection complemented option bytes */ |
12711 | |
| 12712 | 12712 | /******************************************************************************/ |
|
| 12713 | /******************************************************************************/ |
12713 | /* Ethernet MAC Registers bits definitions */ |
| 12714 | /* Ethernet MAC Registers bits definitions */ |
12714 | /******************************************************************************/ |
| 12715 | /******************************************************************************/ |
12715 | /* Bit definition for Ethernet MAC Control Register register */ |
| 12716 | /* Bit definition for Ethernet MAC Control Register register */ |
12716 | #define ETH_MACCR_WD_Pos (23U) |
| 12717 | #define ETH_MACCR_WD_Pos (23U) |
12717 | #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */ |
| 12718 | #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00800000 */ |
12718 | #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */ |
| 12719 | #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */ |
12719 | #define ETH_MACCR_JD_Pos (22U) |
| 12720 | #define ETH_MACCR_JD_Pos (22U) |
12720 | #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */ |
| 12721 | #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00400000 */ |
12721 | #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */ |
| 12722 | #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */ |
12722 | #define ETH_MACCR_IFG_Pos (17U) |
| 12723 | #define ETH_MACCR_IFG_Pos (17U) |
12723 | #define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */ |
| 12724 | #define ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos) /*!< 0x000E0000 */ |
12724 | #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */ |
| 12725 | #define ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */ |
12725 | #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */ |
| 12726 | #define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */ |
12726 | #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */ |
| 12727 | #define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */ |
12727 | #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */ |
| 12728 | #define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */ |
12728 | #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */ |
| 12729 | #define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */ |
12729 | #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */ |
| 12730 | #define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */ |
12730 | #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */ |
| 12731 | #define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */ |
12731 | #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */ |
| 12732 | #define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */ |
12732 | #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */ |
| 12733 | #define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */ |
12733 | #define ETH_MACCR_CSD_Pos (16U) |
| 12734 | #define ETH_MACCR_CSD_Pos (16U) |
12734 | #define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */ |
| 12735 | #define ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos) /*!< 0x00010000 */ |
12735 | #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */ |
| 12736 | #define ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */ |
12736 | #define ETH_MACCR_FES_Pos (14U) |
| 12737 | #define ETH_MACCR_FES_Pos (14U) |
12737 | #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */ |
| 12738 | #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */ |
12738 | #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */ |
| 12739 | #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */ |
12739 | #define ETH_MACCR_ROD_Pos (13U) |
| 12740 | #define ETH_MACCR_ROD_Pos (13U) |
12740 | #define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */ |
| 12741 | #define ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos) /*!< 0x00002000 */ |
12741 | #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */ |
| 12742 | #define ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */ |
12742 | #define ETH_MACCR_LM_Pos (12U) |
| 12743 | #define ETH_MACCR_LM_Pos (12U) |
12743 | #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */ |
| 12744 | #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */ |
12744 | #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */ |
| 12745 | #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */ |
12745 | #define ETH_MACCR_DM_Pos (11U) |
| 12746 | #define ETH_MACCR_DM_Pos (11U) |
12746 | #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */ |
| 12747 | #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00000800 */ |
12747 | #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */ |
| 12748 | #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */ |
12748 | #define ETH_MACCR_IPCO_Pos (10U) |
| 12749 | #define ETH_MACCR_IPCO_Pos (10U) |
12749 | #define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */ |
| 12750 | #define ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos) /*!< 0x00000400 */ |
12750 | #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */ |
| 12751 | #define ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */ |
12751 | #define ETH_MACCR_RD_Pos (9U) |
| 12752 | #define ETH_MACCR_RD_Pos (9U) |
12752 | #define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */ |
| 12753 | #define ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos) /*!< 0x00000200 */ |
12753 | #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */ |
| 12754 | #define ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */ |
12754 | #define ETH_MACCR_APCS_Pos (7U) |
| 12755 | #define ETH_MACCR_APCS_Pos (7U) |
12755 | #define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */ |
| 12756 | #define ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos) /*!< 0x00000080 */ |
12756 | #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */ |
| 12757 | #define ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */ |
12757 | #define ETH_MACCR_BL_Pos (5U) |
| 12758 | #define ETH_MACCR_BL_Pos (5U) |
12758 | #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ |
| 12759 | #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */ |
12759 | #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling |
| 12760 | #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit: random integer number (r) of slot time delays before rescheduling |
12760 | a transmission attempt during retries after a collision: 0 =< r <2^k */ |
| 12761 | a transmission attempt during retries after a collision: 0 =< r <2^k */ |
12761 | #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */ |
| 12762 | #define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */ |
12762 | #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */ |
| 12763 | #define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */ |
12763 | #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */ |
| 12764 | #define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */ |
12764 | #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */ |
| 12765 | #define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */ |
12765 | #define ETH_MACCR_DC_Pos (4U) |
| 12766 | #define ETH_MACCR_DC_Pos (4U) |
12766 | #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ |
| 12767 | #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */ |
12767 | #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */ |
| 12768 | #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */ |
12768 | #define ETH_MACCR_TE_Pos (3U) |
| 12769 | #define ETH_MACCR_TE_Pos (3U) |
12769 | #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */ |
| 12770 | #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000008 */ |
12770 | #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */ |
| 12771 | #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */ |
12771 | #define ETH_MACCR_RE_Pos (2U) |
| 12772 | #define ETH_MACCR_RE_Pos (2U) |
12772 | #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */ |
| 12773 | #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000004 */ |
12773 | #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */ |
| 12774 | #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */ |
12774 | |
| 12775 | 12775 | /* Bit definition for Ethernet MAC Frame Filter Register */ |
|
| 12776 | /* Bit definition for Ethernet MAC Frame Filter Register */ |
12776 | #define ETH_MACFFR_RA_Pos (31U) |
| 12777 | #define ETH_MACFFR_RA_Pos (31U) |
12777 | #define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */ |
| 12778 | #define ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos) /*!< 0x80000000 */ |
12778 | #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */ |
| 12779 | #define ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */ |
12779 | #define ETH_MACFFR_HPF_Pos (10U) |
| 12780 | #define ETH_MACFFR_HPF_Pos (10U) |
12780 | #define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */ |
| 12781 | #define ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos) /*!< 0x00000400 */ |
12781 | #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */ |
| 12782 | #define ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */ |
12782 | #define ETH_MACFFR_SAF_Pos (9U) |
| 12783 | #define ETH_MACFFR_SAF_Pos (9U) |
12783 | #define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */ |
| 12784 | #define ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos) /*!< 0x00000200 */ |
12784 | #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */ |
| 12785 | #define ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */ |
12785 | #define ETH_MACFFR_SAIF_Pos (8U) |
| 12786 | #define ETH_MACFFR_SAIF_Pos (8U) |
12786 | #define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */ |
| 12787 | #define ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos) /*!< 0x00000100 */ |
12787 | #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */ |
| 12788 | #define ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */ |
12788 | #define ETH_MACFFR_PCF_Pos (6U) |
| 12789 | #define ETH_MACFFR_PCF_Pos (6U) |
12789 | #define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */ |
| 12790 | #define ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos) /*!< 0x000000C0 */ |
12790 | #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */ |
| 12791 | #define ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */ |
12791 | #define ETH_MACFFR_PCF_BlockAll_Pos (6U) |
| 12792 | #define ETH_MACFFR_PCF_BlockAll_Pos (6U) |
12792 | #define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */ |
| 12793 | #define ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos) /*!< 0x00000040 */ |
12793 | #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */ |
| 12794 | #define ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */ |
12794 | #define ETH_MACFFR_PCF_ForwardAll_Pos (7U) |
| 12795 | #define ETH_MACFFR_PCF_ForwardAll_Pos (7U) |
12795 | #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */ |
| 12796 | #define ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos) /*!< 0x00000080 */ |
12796 | #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */ |
| 12797 | #define ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */ |
12797 | #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U) |
| 12798 | #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U) |
12798 | #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */ |
| 12799 | #define ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos) /*!< 0x000000C0 */ |
12799 | #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */ |
| 12800 | #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */ |
12800 | #define ETH_MACFFR_BFD_Pos (5U) |
| 12801 | #define ETH_MACFFR_BFD_Pos (5U) |
12801 | #define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */ |
| 12802 | #define ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos) /*!< 0x00000020 */ |
12802 | #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */ |
| 12803 | #define ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */ |
12803 | #define ETH_MACFFR_PAM_Pos (4U) |
| 12804 | #define ETH_MACFFR_PAM_Pos (4U) |
12804 | #define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */ |
| 12805 | #define ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos) /*!< 0x00000010 */ |
12805 | #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */ |
| 12806 | #define ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */ |
12806 | #define ETH_MACFFR_DAIF_Pos (3U) |
| 12807 | #define ETH_MACFFR_DAIF_Pos (3U) |
12807 | #define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */ |
| 12808 | #define ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos) /*!< 0x00000008 */ |
12808 | #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */ |
| 12809 | #define ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */ |
12809 | #define ETH_MACFFR_HM_Pos (2U) |
| 12810 | #define ETH_MACFFR_HM_Pos (2U) |
12810 | #define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */ |
| 12811 | #define ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos) /*!< 0x00000004 */ |
12811 | #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */ |
| 12812 | #define ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */ |
12812 | #define ETH_MACFFR_HU_Pos (1U) |
| 12813 | #define ETH_MACFFR_HU_Pos (1U) |
12813 | #define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */ |
| 12814 | #define ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos) /*!< 0x00000002 */ |
12814 | #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */ |
| 12815 | #define ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */ |
12815 | #define ETH_MACFFR_PM_Pos (0U) |
| 12816 | #define ETH_MACFFR_PM_Pos (0U) |
12816 | #define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */ |
| 12817 | #define ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos) /*!< 0x00000001 */ |
12817 | #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */ |
| 12818 | #define ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */ |
12818 | |
| 12819 | 12819 | /* Bit definition for Ethernet MAC Hash Table High Register */ |
|
| 12820 | /* Bit definition for Ethernet MAC Hash Table High Register */ |
12820 | #define ETH_MACHTHR_HTH_Pos (0U) |
| 12821 | #define ETH_MACHTHR_HTH_Pos (0U) |
12821 | #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */ |
| 12822 | #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */ |
12822 | #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */ |
| 12823 | #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */ |
12823 | |
| 12824 | 12824 | /* Bit definition for Ethernet MAC Hash Table Low Register */ |
|
| 12825 | /* Bit definition for Ethernet MAC Hash Table Low Register */ |
12825 | #define ETH_MACHTLR_HTL_Pos (0U) |
| 12826 | #define ETH_MACHTLR_HTL_Pos (0U) |
12826 | #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */ |
| 12827 | #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */ |
12827 | #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */ |
| 12828 | #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */ |
12828 | |
| 12829 | 12829 | /* Bit definition for Ethernet MAC MII Address Register */ |
|
| 12830 | /* Bit definition for Ethernet MAC MII Address Register */ |
12830 | #define ETH_MACMIIAR_PA_Pos (11U) |
| 12831 | #define ETH_MACMIIAR_PA_Pos (11U) |
12831 | #define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */ |
| 12832 | #define ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos) /*!< 0x0000F800 */ |
12832 | #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */ |
| 12833 | #define ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */ |
12833 | #define ETH_MACMIIAR_MR_Pos (6U) |
| 12834 | #define ETH_MACMIIAR_MR_Pos (6U) |
12834 | #define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */ |
| 12835 | #define ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos) /*!< 0x000007C0 */ |
12835 | #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */ |
| 12836 | #define ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */ |
12836 | #define ETH_MACMIIAR_CR_Pos (2U) |
| 12837 | #define ETH_MACMIIAR_CR_Pos (2U) |
12837 | #define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */ |
| 12838 | #define ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos) /*!< 0x0000001C */ |
12838 | #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */ |
| 12839 | #define ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */ |
12839 | #define ETH_MACMIIAR_CR_DIV42 0x00000000U /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ |
| 12840 | #define ETH_MACMIIAR_CR_DIV42 0x00000000U /* HCLK:60-72 MHz; MDC clock= HCLK/42 */ |
12840 | #define ETH_MACMIIAR_CR_DIV16_Pos (3U) |
| 12841 | #define ETH_MACMIIAR_CR_DIV16_Pos (3U) |
12841 | #define ETH_MACMIIAR_CR_DIV16_Msk (0x1UL << ETH_MACMIIAR_CR_DIV16_Pos) /*!< 0x00000008 */ |
| 12842 | #define ETH_MACMIIAR_CR_DIV16_Msk (0x1UL << ETH_MACMIIAR_CR_DIV16_Pos) /*!< 0x00000008 */ |
12842 | #define ETH_MACMIIAR_CR_DIV16 ETH_MACMIIAR_CR_DIV16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
| 12843 | #define ETH_MACMIIAR_CR_DIV16 ETH_MACMIIAR_CR_DIV16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ |
12843 | #define ETH_MACMIIAR_CR_DIV26_Pos (2U) |
| 12844 | #define ETH_MACMIIAR_CR_DIV26_Pos (2U) |
12844 | #define ETH_MACMIIAR_CR_DIV26_Msk (0x3UL << ETH_MACMIIAR_CR_DIV26_Pos) /*!< 0x0000000C */ |
| 12845 | #define ETH_MACMIIAR_CR_DIV26_Msk (0x3UL << ETH_MACMIIAR_CR_DIV26_Pos) /*!< 0x0000000C */ |
12845 | #define ETH_MACMIIAR_CR_DIV26 ETH_MACMIIAR_CR_DIV26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
| 12846 | #define ETH_MACMIIAR_CR_DIV26 ETH_MACMIIAR_CR_DIV26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ |
12846 | #define ETH_MACMIIAR_MW_Pos (1U) |
| 12847 | #define ETH_MACMIIAR_MW_Pos (1U) |
12847 | #define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */ |
| 12848 | #define ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos) /*!< 0x00000002 */ |
12848 | #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */ |
| 12849 | #define ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */ |
12849 | #define ETH_MACMIIAR_MB_Pos (0U) |
| 12850 | #define ETH_MACMIIAR_MB_Pos (0U) |
12850 | #define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */ |
| 12851 | #define ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos) /*!< 0x00000001 */ |
12851 | #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */ |
| 12852 | #define ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */ |
12852 | |
| 12853 | 12853 | /* Bit definition for Ethernet MAC MII Data Register */ |
|
| 12854 | /* Bit definition for Ethernet MAC MII Data Register */ |
12854 | #define ETH_MACMIIDR_MD_Pos (0U) |
| 12855 | #define ETH_MACMIIDR_MD_Pos (0U) |
12855 | #define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */ |
| 12856 | #define ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos) /*!< 0x0000FFFF */ |
12856 | #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */ |
| 12857 | #define ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */ |
12857 | |
| 12858 | 12858 | /* Bit definition for Ethernet MAC Flow Control Register */ |
|
| 12859 | /* Bit definition for Ethernet MAC Flow Control Register */ |
12859 | #define ETH_MACFCR_PT_Pos (16U) |
| 12860 | #define ETH_MACFCR_PT_Pos (16U) |
12860 | #define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */ |
| 12861 | #define ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos) /*!< 0xFFFF0000 */ |
12861 | #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */ |
| 12862 | #define ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */ |
12862 | #define ETH_MACFCR_ZQPD_Pos (7U) |
| 12863 | #define ETH_MACFCR_ZQPD_Pos (7U) |
12863 | #define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */ |
| 12864 | #define ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos) /*!< 0x00000080 */ |
12864 | #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */ |
| 12865 | #define ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */ |
12865 | #define ETH_MACFCR_PLT_Pos (4U) |
| 12866 | #define ETH_MACFCR_PLT_Pos (4U) |
12866 | #define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */ |
| 12867 | #define ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos) /*!< 0x00000030 */ |
12867 | #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */ |
| 12868 | #define ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */ |
12868 | #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */ |
| 12869 | #define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */ |
12869 | #define ETH_MACFCR_PLT_Minus28_Pos (4U) |
| 12870 | #define ETH_MACFCR_PLT_Minus28_Pos (4U) |
12870 | #define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */ |
| 12871 | #define ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos) /*!< 0x00000010 */ |
12871 | #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */ |
| 12872 | #define ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */ |
12872 | #define ETH_MACFCR_PLT_Minus144_Pos (5U) |
| 12873 | #define ETH_MACFCR_PLT_Minus144_Pos (5U) |
12873 | #define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */ |
| 12874 | #define ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos) /*!< 0x00000020 */ |
12874 | #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */ |
| 12875 | #define ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */ |
12875 | #define ETH_MACFCR_PLT_Minus256_Pos (4U) |
| 12876 | #define ETH_MACFCR_PLT_Minus256_Pos (4U) |
12876 | #define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */ |
| 12877 | #define ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos) /*!< 0x00000030 */ |
12877 | #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */ |
| 12878 | #define ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */ |
12878 | #define ETH_MACFCR_UPFD_Pos (3U) |
| 12879 | #define ETH_MACFCR_UPFD_Pos (3U) |
12879 | #define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */ |
| 12880 | #define ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos) /*!< 0x00000008 */ |
12880 | #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */ |
| 12881 | #define ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */ |
12881 | #define ETH_MACFCR_RFCE_Pos (2U) |
| 12882 | #define ETH_MACFCR_RFCE_Pos (2U) |
12882 | #define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */ |
| 12883 | #define ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos) /*!< 0x00000004 */ |
12883 | #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */ |
| 12884 | #define ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */ |
12884 | #define ETH_MACFCR_TFCE_Pos (1U) |
| 12885 | #define ETH_MACFCR_TFCE_Pos (1U) |
12885 | #define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */ |
| 12886 | #define ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos) /*!< 0x00000002 */ |
12886 | #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */ |
| 12887 | #define ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */ |
12887 | #define ETH_MACFCR_FCBBPA_Pos (0U) |
| 12888 | #define ETH_MACFCR_FCBBPA_Pos (0U) |
12888 | #define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */ |
| 12889 | #define ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos) /*!< 0x00000001 */ |
12889 | #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */ |
| 12890 | #define ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */ |
12890 | |
| 12891 | 12891 | /* Bit definition for Ethernet MAC VLAN Tag Register */ |
|
| 12892 | /* Bit definition for Ethernet MAC VLAN Tag Register */ |
12892 | #define ETH_MACVLANTR_VLANTC_Pos (16U) |
| 12893 | #define ETH_MACVLANTR_VLANTC_Pos (16U) |
12893 | #define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */ |
| 12894 | #define ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos) /*!< 0x00010000 */ |
12894 | #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */ |
| 12895 | #define ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */ |
12895 | #define ETH_MACVLANTR_VLANTI_Pos (0U) |
| 12896 | #define ETH_MACVLANTR_VLANTI_Pos (0U) |
12896 | #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */ |
| 12897 | #define ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos) /*!< 0x0000FFFF */ |
12897 | #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */ |
| 12898 | #define ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */ |
12898 | |
| 12899 | 12899 | /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ |
|
| 12900 | /* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ |
12900 | #define ETH_MACRWUFFR_D_Pos (0U) |
| 12901 | #define ETH_MACRWUFFR_D_Pos (0U) |
12901 | #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */ |
| 12902 | #define ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos) /*!< 0xFFFFFFFF */ |
12902 | #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */ |
| 12903 | #define ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */ |
12903 | /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. |
| 12904 | /* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. |
12904 | Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ |
| 12905 | Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ |
12905 | /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask |
| 12906 | /* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask |
12906 | Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask |
| 12907 | Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask |
12907 | Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask |
| 12908 | Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask |
12908 | Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask |
| 12909 | Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask |
12909 | Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - |
| 12910 | Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - |
12910 | RSVD - Filter1 Command - RSVD - Filter0 Command |
| 12911 | RSVD - Filter1 Command - RSVD - Filter0 Command |
12911 | Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset |
| 12912 | Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset |
12912 | Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 |
| 12913 | Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 |
12913 | Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ |
| 12914 | Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ |
12914 | |
| 12915 | 12915 | /* Bit definition for Ethernet MAC PMT Control and Status Register */ |
|
| 12916 | /* Bit definition for Ethernet MAC PMT Control and Status Register */ |
12916 | #define ETH_MACPMTCSR_WFFRPR_Pos (31U) |
| 12917 | #define ETH_MACPMTCSR_WFFRPR_Pos (31U) |
12917 | #define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */ |
| 12918 | #define ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos) /*!< 0x80000000 */ |
12918 | #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */ |
| 12919 | #define ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */ |
12919 | #define ETH_MACPMTCSR_GU_Pos (9U) |
| 12920 | #define ETH_MACPMTCSR_GU_Pos (9U) |
12920 | #define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */ |
| 12921 | #define ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos) /*!< 0x00000200 */ |
12921 | #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */ |
| 12922 | #define ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */ |
12922 | #define ETH_MACPMTCSR_WFR_Pos (6U) |
| 12923 | #define ETH_MACPMTCSR_WFR_Pos (6U) |
12923 | #define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */ |
| 12924 | #define ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos) /*!< 0x00000040 */ |
12924 | #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */ |
| 12925 | #define ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */ |
12925 | #define ETH_MACPMTCSR_MPR_Pos (5U) |
| 12926 | #define ETH_MACPMTCSR_MPR_Pos (5U) |
12926 | #define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */ |
| 12927 | #define ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos) /*!< 0x00000020 */ |
12927 | #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */ |
| 12928 | #define ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */ |
12928 | #define ETH_MACPMTCSR_WFE_Pos (2U) |
| 12929 | #define ETH_MACPMTCSR_WFE_Pos (2U) |
12929 | #define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */ |
| 12930 | #define ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos) /*!< 0x00000004 */ |
12930 | #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */ |
| 12931 | #define ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */ |
12931 | #define ETH_MACPMTCSR_MPE_Pos (1U) |
| 12932 | #define ETH_MACPMTCSR_MPE_Pos (1U) |
12932 | #define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */ |
| 12933 | #define ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos) /*!< 0x00000002 */ |
12933 | #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */ |
| 12934 | #define ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */ |
12934 | #define ETH_MACPMTCSR_PD_Pos (0U) |
| 12935 | #define ETH_MACPMTCSR_PD_Pos (0U) |
12935 | #define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */ |
| 12936 | #define ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos) /*!< 0x00000001 */ |
12936 | #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */ |
| 12937 | #define ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */ |
12937 | |
| 12938 | 12938 | /* Bit definition for Ethernet MAC Status Register */ |
|
| 12939 | /* Bit definition for Ethernet MAC Status Register */ |
12939 | #define ETH_MACSR_TSTS_Pos (9U) |
| 12940 | #define ETH_MACSR_TSTS_Pos (9U) |
12940 | #define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */ |
| 12941 | #define ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos) /*!< 0x00000200 */ |
12941 | #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */ |
| 12942 | #define ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */ |
12942 | #define ETH_MACSR_MMCTS_Pos (6U) |
| 12943 | #define ETH_MACSR_MMCTS_Pos (6U) |
12943 | #define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */ |
| 12944 | #define ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos) /*!< 0x00000040 */ |
12944 | #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */ |
| 12945 | #define ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */ |
12945 | #define ETH_MACSR_MMMCRS_Pos (5U) |
| 12946 | #define ETH_MACSR_MMMCRS_Pos (5U) |
12946 | #define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */ |
| 12947 | #define ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos) /*!< 0x00000020 */ |
12947 | #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */ |
| 12948 | #define ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */ |
12948 | #define ETH_MACSR_MMCS_Pos (4U) |
| 12949 | #define ETH_MACSR_MMCS_Pos (4U) |
12949 | #define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */ |
| 12950 | #define ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos) /*!< 0x00000010 */ |
12950 | #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */ |
| 12951 | #define ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */ |
12951 | #define ETH_MACSR_PMTS_Pos (3U) |
| 12952 | #define ETH_MACSR_PMTS_Pos (3U) |
12952 | #define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */ |
| 12953 | #define ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos) /*!< 0x00000008 */ |
12953 | #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */ |
| 12954 | #define ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */ |
12954 | |
| 12955 | 12955 | /* Bit definition for Ethernet MAC Interrupt Mask Register */ |
|
| 12956 | /* Bit definition for Ethernet MAC Interrupt Mask Register */ |
12956 | #define ETH_MACIMR_TSTIM_Pos (9U) |
| 12957 | #define ETH_MACIMR_TSTIM_Pos (9U) |
12957 | #define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */ |
| 12958 | #define ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos) /*!< 0x00000200 */ |
12958 | #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */ |
| 12959 | #define ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */ |
12959 | #define ETH_MACIMR_PMTIM_Pos (3U) |
| 12960 | #define ETH_MACIMR_PMTIM_Pos (3U) |
12960 | #define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */ |
| 12961 | #define ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos) /*!< 0x00000008 */ |
12961 | #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */ |
| 12962 | #define ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */ |
12962 | |
| 12963 | 12963 | /* Bit definition for Ethernet MAC Address0 High Register */ |
|
| 12964 | /* Bit definition for Ethernet MAC Address0 High Register */ |
12964 | #define ETH_MACA0HR_MACA0H_Pos (0U) |
| 12965 | #define ETH_MACA0HR_MACA0H_Pos (0U) |
12965 | #define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */ |
| 12966 | #define ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos) /*!< 0x0000FFFF */ |
12966 | #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */ |
| 12967 | #define ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */ |
12967 | |
| 12968 | 12968 | /* Bit definition for Ethernet MAC Address0 Low Register */ |
|
| 12969 | /* Bit definition for Ethernet MAC Address0 Low Register */ |
12969 | #define ETH_MACA0LR_MACA0L_Pos (0U) |
| 12970 | #define ETH_MACA0LR_MACA0L_Pos (0U) |
12970 | #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */ |
| 12971 | #define ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos) /*!< 0xFFFFFFFF */ |
12971 | #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */ |
| 12972 | #define ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */ |
12972 | |
| 12973 | 12973 | /* Bit definition for Ethernet MAC Address1 High Register */ |
|
| 12974 | /* Bit definition for Ethernet MAC Address1 High Register */ |
12974 | #define ETH_MACA1HR_AE_Pos (31U) |
| 12975 | #define ETH_MACA1HR_AE_Pos (31U) |
12975 | #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */ |
| 12976 | #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */ |
12976 | #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */ |
| 12977 | #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */ |
12977 | #define ETH_MACA1HR_SA_Pos (30U) |
| 12978 | #define ETH_MACA1HR_SA_Pos (30U) |
12978 | #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */ |
| 12979 | #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */ |
12979 | #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */ |
| 12980 | #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */ |
12980 | #define ETH_MACA1HR_MBC_Pos (24U) |
| 12981 | #define ETH_MACA1HR_MBC_Pos (24U) |
12981 | #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */ |
| 12982 | #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */ |
12982 | #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
| 12983 | #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ |
12983 | #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
| 12984 | #define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
12984 | #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
| 12985 | #define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
12985 | #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
| 12986 | #define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
12986 | #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
| 12987 | #define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
12987 | #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
| 12988 | #define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
12988 | #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */ |
| 12989 | #define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */ |
12989 | #define ETH_MACA1HR_MACA1H_Pos (0U) |
| 12990 | #define ETH_MACA1HR_MACA1H_Pos (0U) |
12990 | #define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */ |
| 12991 | #define ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos) /*!< 0x0000FFFF */ |
12991 | #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */ |
| 12992 | #define ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */ |
12992 | |
| 12993 | 12993 | /* Bit definition for Ethernet MAC Address1 Low Register */ |
|
| 12994 | /* Bit definition for Ethernet MAC Address1 Low Register */ |
12994 | #define ETH_MACA1LR_MACA1L_Pos (0U) |
| 12995 | #define ETH_MACA1LR_MACA1L_Pos (0U) |
12995 | #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */ |
| 12996 | #define ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos) /*!< 0xFFFFFFFF */ |
12996 | #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */ |
| 12997 | #define ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */ |
12997 | |
| 12998 | 12998 | /* Bit definition for Ethernet MAC Address2 High Register */ |
|
| 12999 | /* Bit definition for Ethernet MAC Address2 High Register */ |
12999 | #define ETH_MACA2HR_AE_Pos (31U) |
| 13000 | #define ETH_MACA2HR_AE_Pos (31U) |
13000 | #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */ |
| 13001 | #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */ |
13001 | #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */ |
| 13002 | #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */ |
13002 | #define ETH_MACA2HR_SA_Pos (30U) |
| 13003 | #define ETH_MACA2HR_SA_Pos (30U) |
13003 | #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */ |
| 13004 | #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */ |
13004 | #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */ |
| 13005 | #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */ |
13005 | #define ETH_MACA2HR_MBC_Pos (24U) |
| 13006 | #define ETH_MACA2HR_MBC_Pos (24U) |
13006 | #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */ |
| 13007 | #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */ |
13007 | #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */ |
| 13008 | #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */ |
13008 | #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
| 13009 | #define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
13009 | #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
| 13010 | #define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
13010 | #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
| 13011 | #define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
13011 | #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
| 13012 | #define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
13012 | #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
| 13013 | #define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
13013 | #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ |
| 13014 | #define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ |
13014 | #define ETH_MACA2HR_MACA2H_Pos (0U) |
| 13015 | #define ETH_MACA2HR_MACA2H_Pos (0U) |
13015 | #define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */ |
| 13016 | #define ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos) /*!< 0x0000FFFF */ |
13016 | #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */ |
| 13017 | #define ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */ |
13017 | |
| 13018 | 13018 | /* Bit definition for Ethernet MAC Address2 Low Register */ |
|
| 13019 | /* Bit definition for Ethernet MAC Address2 Low Register */ |
13019 | #define ETH_MACA2LR_MACA2L_Pos (0U) |
| 13020 | #define ETH_MACA2LR_MACA2L_Pos (0U) |
13020 | #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */ |
| 13021 | #define ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos) /*!< 0xFFFFFFFF */ |
13021 | #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */ |
| 13022 | #define ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */ |
13022 | |
| 13023 | 13023 | /* Bit definition for Ethernet MAC Address3 High Register */ |
|
| 13024 | /* Bit definition for Ethernet MAC Address3 High Register */ |
13024 | #define ETH_MACA3HR_AE_Pos (31U) |
| 13025 | #define ETH_MACA3HR_AE_Pos (31U) |
13025 | #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */ |
| 13026 | #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */ |
13026 | #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */ |
| 13027 | #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */ |
13027 | #define ETH_MACA3HR_SA_Pos (30U) |
| 13028 | #define ETH_MACA3HR_SA_Pos (30U) |
13028 | #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */ |
| 13029 | #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */ |
13029 | #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */ |
| 13030 | #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */ |
13030 | #define ETH_MACA3HR_MBC_Pos (24U) |
| 13031 | #define ETH_MACA3HR_MBC_Pos (24U) |
13031 | #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */ |
| 13032 | #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */ |
13032 | #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */ |
| 13033 | #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */ |
13033 | #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
| 13034 | #define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */ |
13034 | #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
| 13035 | #define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */ |
13035 | #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
| 13036 | #define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */ |
13036 | #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
| 13037 | #define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */ |
13037 | #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
| 13038 | #define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */ |
13038 | #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ |
| 13039 | #define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */ |
13039 | #define ETH_MACA3HR_MACA3H_Pos (0U) |
| 13040 | #define ETH_MACA3HR_MACA3H_Pos (0U) |
13040 | #define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */ |
| 13041 | #define ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos) /*!< 0x0000FFFF */ |
13041 | #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */ |
| 13042 | #define ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */ |
13042 | |
| 13043 | 13043 | /* Bit definition for Ethernet MAC Address3 Low Register */ |
|
| 13044 | /* Bit definition for Ethernet MAC Address3 Low Register */ |
13044 | #define ETH_MACA3LR_MACA3L_Pos (0U) |
| 13045 | #define ETH_MACA3LR_MACA3L_Pos (0U) |
13045 | #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */ |
| 13046 | #define ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos) /*!< 0xFFFFFFFF */ |
13046 | #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */ |
| 13047 | #define ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */ |
13047 | |
| 13048 | 13048 | /******************************************************************************/ |
|
| 13049 | /******************************************************************************/ |
13049 | /* Ethernet MMC Registers bits definition */ |
| 13050 | /* Ethernet MMC Registers bits definition */ |
13050 | /******************************************************************************/ |
| 13051 | /******************************************************************************/ |
13051 | |
| 13052 | 13052 | /* Bit definition for Ethernet MMC Control Register */ |
|
| 13053 | /* Bit definition for Ethernet MMC Contol Register */ |
13053 | #define ETH_MMCCR_MCF_Pos (3U) |
| 13054 | #define ETH_MMCCR_MCF_Pos (3U) |
13054 | #define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */ |
| 13055 | #define ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos) /*!< 0x00000008 */ |
13055 | #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */ |
| 13056 | #define ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */ |
13056 | #define ETH_MMCCR_ROR_Pos (2U) |
| 13057 | #define ETH_MMCCR_ROR_Pos (2U) |
13057 | #define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */ |
| 13058 | #define ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos) /*!< 0x00000004 */ |
13058 | #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */ |
| 13059 | #define ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */ |
13059 | #define ETH_MMCCR_CSR_Pos (1U) |
| 13060 | #define ETH_MMCCR_CSR_Pos (1U) |
13060 | #define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */ |
| 13061 | #define ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos) /*!< 0x00000002 */ |
13061 | #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */ |
| 13062 | #define ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */ |
13062 | #define ETH_MMCCR_CR_Pos (0U) |
| 13063 | #define ETH_MMCCR_CR_Pos (0U) |
13063 | #define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */ |
| 13064 | #define ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos) /*!< 0x00000001 */ |
13064 | #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */ |
| 13065 | #define ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */ |
13065 | |
| 13066 | 13066 | /* Bit definition for Ethernet MMC Receive Interrupt Register */ |
|
| 13067 | /* Bit definition for Ethernet MMC Receive Interrupt Register */ |
13067 | #define ETH_MMCRIR_RGUFS_Pos (17U) |
| 13068 | #define ETH_MMCRIR_RGUFS_Pos (17U) |
13068 | #define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */ |
| 13069 | #define ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos) /*!< 0x00020000 */ |
13069 | #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */ |
| 13070 | #define ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */ |
13070 | #define ETH_MMCRIR_RFAES_Pos (6U) |
| 13071 | #define ETH_MMCRIR_RFAES_Pos (6U) |
13071 | #define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */ |
| 13072 | #define ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos) /*!< 0x00000040 */ |
13072 | #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */ |
| 13073 | #define ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */ |
13073 | #define ETH_MMCRIR_RFCES_Pos (5U) |
| 13074 | #define ETH_MMCRIR_RFCES_Pos (5U) |
13074 | #define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */ |
| 13075 | #define ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos) /*!< 0x00000020 */ |
13075 | #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */ |
| 13076 | #define ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */ |
13076 | |
| 13077 | 13077 | /* Bit definition for Ethernet MMC Transmit Interrupt Register */ |
|
| 13078 | /* Bit definition for Ethernet MMC Transmit Interrupt Register */ |
13078 | #define ETH_MMCTIR_TGFS_Pos (21U) |
| 13079 | #define ETH_MMCTIR_TGFS_Pos (21U) |
13079 | #define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */ |
| 13080 | #define ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos) /*!< 0x00200000 */ |
13080 | #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */ |
| 13081 | #define ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */ |
13081 | #define ETH_MMCTIR_TGFMSCS_Pos (15U) |
| 13082 | #define ETH_MMCTIR_TGFMSCS_Pos (15U) |
13082 | #define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */ |
| 13083 | #define ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos) /*!< 0x00008000 */ |
13083 | #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */ |
| 13084 | #define ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */ |
13084 | #define ETH_MMCTIR_TGFSCS_Pos (14U) |
| 13085 | #define ETH_MMCTIR_TGFSCS_Pos (14U) |
13085 | #define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */ |
| 13086 | #define ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos) /*!< 0x00004000 */ |
13086 | #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */ |
| 13087 | #define ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */ |
13087 | |
| 13088 | 13088 | /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ |
|
| 13089 | /* Bit definition for Ethernet MMC Receive Interrupt Mask Register */ |
13089 | #define ETH_MMCRIMR_RGUFM_Pos (17U) |
| 13090 | #define ETH_MMCRIMR_RGUFM_Pos (17U) |
13090 | #define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */ |
| 13091 | #define ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos) /*!< 0x00020000 */ |
13091 | #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
| 13092 | #define ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ |
13092 | #define ETH_MMCRIMR_RFAEM_Pos (6U) |
| 13093 | #define ETH_MMCRIMR_RFAEM_Pos (6U) |
13093 | #define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */ |
| 13094 | #define ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos) /*!< 0x00000040 */ |
13094 | #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
| 13095 | #define ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ |
13095 | #define ETH_MMCRIMR_RFCEM_Pos (5U) |
| 13096 | #define ETH_MMCRIMR_RFCEM_Pos (5U) |
13096 | #define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */ |
| 13097 | #define ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos) /*!< 0x00000020 */ |
13097 | #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
| 13098 | #define ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ |
13098 | |
| 13099 | 13099 | /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ |
|
| 13100 | /* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */ |
13100 | #define ETH_MMCTIMR_TGFM_Pos (21U) |
| 13101 | #define ETH_MMCTIMR_TGFM_Pos (21U) |
13101 | #define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */ |
| 13102 | #define ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos) /*!< 0x00200000 */ |
13102 | #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
| 13103 | #define ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ |
13103 | #define ETH_MMCTIMR_TGFMSCM_Pos (15U) |
| 13104 | #define ETH_MMCTIMR_TGFMSCM_Pos (15U) |
13104 | #define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */ |
| 13105 | #define ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos) /*!< 0x00008000 */ |
13105 | #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
| 13106 | #define ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ |
13106 | #define ETH_MMCTIMR_TGFSCM_Pos (14U) |
| 13107 | #define ETH_MMCTIMR_TGFSCM_Pos (14U) |
13107 | #define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */ |
| 13108 | #define ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos) /*!< 0x00004000 */ |
13108 | #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
| 13109 | #define ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ |
13109 | |
| 13110 | 13110 | /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ |
|
| 13111 | /* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */ |
13111 | #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U) |
| 13112 | #define ETH_MMCTGFSCCR_TGFSCC_Pos (0U) |
13112 | #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */ |
| 13113 | #define ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos) /*!< 0xFFFFFFFF */ |
13113 | #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
| 13114 | #define ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ |
13114 | |
| 13115 | 13115 | /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ |
|
| 13116 | /* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */ |
13116 | #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U) |
| 13117 | #define ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U) |
13117 | #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */ |
| 13118 | #define ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos) /*!< 0xFFFFFFFF */ |
13118 | #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
| 13119 | #define ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ |
13119 | |
| 13120 | 13120 | /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ |
|
| 13121 | /* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */ |
13121 | #define ETH_MMCTGFCR_TGFC_Pos (0U) |
| 13122 | #define ETH_MMCTGFCR_TGFC_Pos (0U) |
13122 | #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */ |
| 13123 | #define ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos) /*!< 0xFFFFFFFF */ |
13123 | #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */ |
| 13124 | #define ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */ |
13124 | |
| 13125 | 13125 | /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ |
|
| 13126 | /* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */ |
13126 | #define ETH_MMCRFCECR_RFCEC_Pos (0U) |
| 13127 | #define ETH_MMCRFCECR_RFCEC_Pos (0U) |
13127 | #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */ |
| 13128 | #define ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos) /*!< 0xFFFFFFFF */ |
13128 | #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */ |
| 13129 | #define ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */ |
13129 | |
| 13130 | 13130 | /* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */ |
|
| 13131 | /* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */ |
13131 | #define ETH_MMCRFAECR_RFAEC_Pos (0U) |
| 13132 | #define ETH_MMCRFAECR_RFAEC_Pos (0U) |
13132 | #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */ |
| 13133 | #define ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos) /*!< 0xFFFFFFFF */ |
13133 | #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */ |
| 13134 | #define ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */ |
13134 | |
| 13135 | 13135 | /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ |
|
| 13136 | /* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */ |
13136 | #define ETH_MMCRGUFCR_RGUFC_Pos (0U) |
| 13137 | #define ETH_MMCRGUFCR_RGUFC_Pos (0U) |
13137 | #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */ |
| 13138 | #define ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos) /*!< 0xFFFFFFFF */ |
13138 | #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */ |
| 13139 | #define ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */ |
13139 | |
| 13140 | 13140 | /******************************************************************************/ |
|
| 13141 | /******************************************************************************/ |
13141 | /* Ethernet PTP Registers bits definition */ |
| 13142 | /* Ethernet PTP Registers bits definition */ |
13142 | /******************************************************************************/ |
| 13143 | /******************************************************************************/ |
13143 | |
| 13144 | 13144 | /* Bit definition for Ethernet PTP Time Stamp Control Register */ |
|
| 13145 | /* Bit definition for Ethernet PTP Time Stamp Contol Register */ |
13145 | #define ETH_PTPTSCR_TSARU_Pos (5U) |
| 13146 | #define ETH_PTPTSCR_TSARU_Pos (5U) |
13146 | #define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */ |
| 13147 | #define ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos) /*!< 0x00000020 */ |
13147 | #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */ |
| 13148 | #define ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */ |
13148 | #define ETH_PTPTSCR_TSITE_Pos (4U) |
| 13149 | #define ETH_PTPTSCR_TSITE_Pos (4U) |
13149 | #define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */ |
| 13150 | #define ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos) /*!< 0x00000010 */ |
13150 | #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */ |
| 13151 | #define ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */ |
13151 | #define ETH_PTPTSCR_TSSTU_Pos (3U) |
| 13152 | #define ETH_PTPTSCR_TSSTU_Pos (3U) |
13152 | #define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */ |
| 13153 | #define ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos) /*!< 0x00000008 */ |
13153 | #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */ |
| 13154 | #define ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */ |
13154 | #define ETH_PTPTSCR_TSSTI_Pos (2U) |
| 13155 | #define ETH_PTPTSCR_TSSTI_Pos (2U) |
13155 | #define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */ |
| 13156 | #define ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos) /*!< 0x00000004 */ |
13156 | #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */ |
| 13157 | #define ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */ |
13157 | #define ETH_PTPTSCR_TSFCU_Pos (1U) |
| 13158 | #define ETH_PTPTSCR_TSFCU_Pos (1U) |
13158 | #define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */ |
| 13159 | #define ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos) /*!< 0x00000002 */ |
13159 | #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */ |
| 13160 | #define ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */ |
13160 | #define ETH_PTPTSCR_TSE_Pos (0U) |
| 13161 | #define ETH_PTPTSCR_TSE_Pos (0U) |
13161 | #define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */ |
| 13162 | #define ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos) /*!< 0x00000001 */ |
13162 | #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */ |
| 13163 | #define ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */ |
13163 | |
| 13164 | 13164 | /* Bit definition for Ethernet PTP Sub-Second Increment Register */ |
|
| 13165 | /* Bit definition for Ethernet PTP Sub-Second Increment Register */ |
13165 | #define ETH_PTPSSIR_STSSI_Pos (0U) |
| 13166 | #define ETH_PTPSSIR_STSSI_Pos (0U) |
13166 | #define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */ |
| 13167 | #define ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos) /*!< 0x000000FF */ |
13167 | #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */ |
| 13168 | #define ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */ |
13168 | |
| 13169 | 13169 | /* Bit definition for Ethernet PTP Time Stamp High Register */ |
|
| 13170 | /* Bit definition for Ethernet PTP Time Stamp High Register */ |
13170 | #define ETH_PTPTSHR_STS_Pos (0U) |
| 13171 | #define ETH_PTPTSHR_STS_Pos (0U) |
13171 | #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */ |
| 13172 | #define ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos) /*!< 0xFFFFFFFF */ |
13172 | #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */ |
| 13173 | #define ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */ |
13173 | |
| 13174 | 13174 | /* Bit definition for Ethernet PTP Time Stamp Low Register */ |
|
| 13175 | /* Bit definition for Ethernet PTP Time Stamp Low Register */ |
13175 | #define ETH_PTPTSLR_STPNS_Pos (31U) |
| 13176 | #define ETH_PTPTSLR_STPNS_Pos (31U) |
13176 | #define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */ |
| 13177 | #define ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos) /*!< 0x80000000 */ |
13177 | #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */ |
| 13178 | #define ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */ |
13178 | #define ETH_PTPTSLR_STSS_Pos (0U) |
| 13179 | #define ETH_PTPTSLR_STSS_Pos (0U) |
13179 | #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */ |
| 13180 | #define ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos) /*!< 0x7FFFFFFF */ |
13180 | #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */ |
| 13181 | #define ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */ |
13181 | |
| 13182 | 13182 | /* Bit definition for Ethernet PTP Time Stamp High Update Register */ |
|
| 13183 | /* Bit definition for Ethernet PTP Time Stamp High Update Register */ |
13183 | #define ETH_PTPTSHUR_TSUS_Pos (0U) |
| 13184 | #define ETH_PTPTSHUR_TSUS_Pos (0U) |
13184 | #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */ |
| 13185 | #define ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos) /*!< 0xFFFFFFFF */ |
13185 | #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */ |
| 13186 | #define ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */ |
13186 | |
| 13187 | 13187 | /* Bit definition for Ethernet PTP Time Stamp Low Update Register */ |
|
| 13188 | /* Bit definition for Ethernet PTP Time Stamp Low Update Register */ |
13188 | #define ETH_PTPTSLUR_TSUPNS_Pos (31U) |
| 13189 | #define ETH_PTPTSLUR_TSUPNS_Pos (31U) |
13189 | #define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */ |
| 13190 | #define ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos) /*!< 0x80000000 */ |
13190 | #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */ |
| 13191 | #define ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */ |
13191 | #define ETH_PTPTSLUR_TSUSS_Pos (0U) |
| 13192 | #define ETH_PTPTSLUR_TSUSS_Pos (0U) |
13192 | #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */ |
| 13193 | #define ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos) /*!< 0x7FFFFFFF */ |
13193 | #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */ |
| 13194 | #define ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */ |
13194 | |
| 13195 | 13195 | /* Bit definition for Ethernet PTP Time Stamp Addend Register */ |
|
| 13196 | /* Bit definition for Ethernet PTP Time Stamp Addend Register */ |
13196 | #define ETH_PTPTSAR_TSA_Pos (0U) |
| 13197 | #define ETH_PTPTSAR_TSA_Pos (0U) |
13197 | #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */ |
| 13198 | #define ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos) /*!< 0xFFFFFFFF */ |
13198 | #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */ |
| 13199 | #define ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */ |
13199 | |
| 13200 | 13200 | /* Bit definition for Ethernet PTP Target Time High Register */ |
|
| 13201 | /* Bit definition for Ethernet PTP Target Time High Register */ |
13201 | #define ETH_PTPTTHR_TTSH_Pos (0U) |
| 13202 | #define ETH_PTPTTHR_TTSH_Pos (0U) |
13202 | #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */ |
| 13203 | #define ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos) /*!< 0xFFFFFFFF */ |
13203 | #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */ |
| 13204 | #define ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */ |
13204 | |
| 13205 | 13205 | /* Bit definition for Ethernet PTP Target Time Low Register */ |
|
| 13206 | /* Bit definition for Ethernet PTP Target Time Low Register */ |
13206 | #define ETH_PTPTTLR_TTSL_Pos (0U) |
| 13207 | #define ETH_PTPTTLR_TTSL_Pos (0U) |
13207 | #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */ |
| 13208 | #define ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos) /*!< 0xFFFFFFFF */ |
13208 | #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */ |
| 13209 | #define ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */ |
13209 | |
| 13210 | 13210 | /******************************************************************************/ |
|
| 13211 | /******************************************************************************/ |
13211 | /* Ethernet DMA Registers bits definition */ |
| 13212 | /* Ethernet DMA Registers bits definition */ |
13212 | /******************************************************************************/ |
| 13213 | /******************************************************************************/ |
13213 | |
| 13214 | 13214 | /* Bit definition for Ethernet DMA Bus Mode Register */ |
|
| 13215 | /* Bit definition for Ethernet DMA Bus Mode Register */ |
13215 | #define ETH_DMABMR_AAB_Pos (25U) |
| 13216 | #define ETH_DMABMR_AAB_Pos (25U) |
13216 | #define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */ |
| 13217 | #define ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos) /*!< 0x02000000 */ |
13217 | #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */ |
| 13218 | #define ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */ |
13218 | #define ETH_DMABMR_FPM_Pos (24U) |
| 13219 | #define ETH_DMABMR_FPM_Pos (24U) |
13219 | #define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */ |
| 13220 | #define ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos) /*!< 0x01000000 */ |
13220 | #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */ |
| 13221 | #define ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */ |
13221 | #define ETH_DMABMR_USP_Pos (23U) |
| 13222 | #define ETH_DMABMR_USP_Pos (23U) |
13222 | #define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */ |
| 13223 | #define ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos) /*!< 0x00800000 */ |
13223 | #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */ |
| 13224 | #define ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */ |
13224 | #define ETH_DMABMR_RDP_Pos (17U) |
| 13225 | #define ETH_DMABMR_RDP_Pos (17U) |
13225 | #define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */ |
| 13226 | #define ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos) /*!< 0x007E0000 */ |
13226 | #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */ |
| 13227 | #define ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */ |
13227 | #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
| 13228 | #define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ |
13228 | #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
| 13229 | #define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ |
13229 | #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| 13230 | #define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
13230 | #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| 13231 | #define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
13231 | #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| 13232 | #define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
13232 | #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| 13233 | #define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
13233 | #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
| 13234 | #define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ |
13234 | #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
| 13235 | #define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ |
13235 | #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
| 13236 | #define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ |
13236 | #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
| 13237 | #define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ |
13237 | #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
| 13238 | #define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ |
13238 | #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
| 13239 | #define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ |
13239 | #define ETH_DMABMR_FB_Pos (16U) |
| 13240 | #define ETH_DMABMR_FB_Pos (16U) |
13240 | #define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */ |
| 13241 | #define ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos) /*!< 0x00010000 */ |
13241 | #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */ |
| 13242 | #define ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */ |
13242 | #define ETH_DMABMR_RTPR_Pos (14U) |
| 13243 | #define ETH_DMABMR_RTPR_Pos (14U) |
13243 | #define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */ |
| 13244 | #define ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos) /*!< 0x0000C000 */ |
13244 | #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */ |
| 13245 | #define ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */ |
13245 | #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */ |
| 13246 | #define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */ |
13246 | #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */ |
| 13247 | #define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */ |
13247 | #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */ |
| 13248 | #define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */ |
13248 | #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */ |
| 13249 | #define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */ |
13249 | #define ETH_DMABMR_PBL_Pos (8U) |
| 13250 | #define ETH_DMABMR_PBL_Pos (8U) |
13250 | #define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */ |
| 13251 | #define ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos) /*!< 0x00003F00 */ |
13251 | #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */ |
| 13252 | #define ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */ |
13252 | #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
| 13253 | #define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ |
13253 | #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
| 13254 | #define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ |
13254 | #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| 13255 | #define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
13255 | #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| 13256 | #define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
13256 | #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| 13257 | #define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
13257 | #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| 13258 | #define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
13258 | #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
| 13259 | #define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ |
13259 | #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
| 13260 | #define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ |
13260 | #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
| 13261 | #define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ |
13261 | #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
| 13262 | #define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ |
13262 | #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
| 13263 | #define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ |
13263 | #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
| 13264 | #define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ |
13264 | #define ETH_DMABMR_DSL_Pos (2U) |
| 13265 | #define ETH_DMABMR_DSL_Pos (2U) |
13265 | #define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */ |
| 13266 | #define ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos) /*!< 0x0000007C */ |
13266 | #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */ |
| 13267 | #define ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */ |
13267 | #define ETH_DMABMR_DA_Pos (1U) |
| 13268 | #define ETH_DMABMR_DA_Pos (1U) |
13268 | #define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */ |
| 13269 | #define ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos) /*!< 0x00000002 */ |
13269 | #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */ |
| 13270 | #define ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */ |
13270 | #define ETH_DMABMR_SR_Pos (0U) |
| 13271 | #define ETH_DMABMR_SR_Pos (0U) |
13271 | #define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */ |
| 13272 | #define ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos) /*!< 0x00000001 */ |
13272 | #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */ |
| 13273 | #define ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */ |
13273 | |
| 13274 | 13274 | /* Bit definition for Ethernet DMA Transmit Poll Demand Register */ |
|
| 13275 | /* Bit definition for Ethernet DMA Transmit Poll Demand Register */ |
13275 | #define ETH_DMATPDR_TPD_Pos (0U) |
| 13276 | #define ETH_DMATPDR_TPD_Pos (0U) |
13276 | #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */ |
| 13277 | #define ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos) /*!< 0xFFFFFFFF */ |
13277 | #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */ |
| 13278 | #define ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */ |
13278 | |
| 13279 | 13279 | /* Bit definition for Ethernet DMA Receive Poll Demand Register */ |
|
| 13280 | /* Bit definition for Ethernet DMA Receive Poll Demand Register */ |
13280 | #define ETH_DMARPDR_RPD_Pos (0U) |
| 13281 | #define ETH_DMARPDR_RPD_Pos (0U) |
13281 | #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */ |
| 13282 | #define ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos) /*!< 0xFFFFFFFF */ |
13282 | #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */ |
| 13283 | #define ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */ |
13283 | |
| 13284 | 13284 | /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ |
|
| 13285 | /* Bit definition for Ethernet DMA Receive Descriptor List Address Register */ |
13285 | #define ETH_DMARDLAR_SRL_Pos (0U) |
| 13286 | #define ETH_DMARDLAR_SRL_Pos (0U) |
13286 | #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */ |
| 13287 | #define ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos) /*!< 0xFFFFFFFF */ |
13287 | #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */ |
| 13288 | #define ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */ |
13288 | |
| 13289 | 13289 | /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ |
|
| 13290 | /* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */ |
13290 | #define ETH_DMATDLAR_STL_Pos (0U) |
| 13291 | #define ETH_DMATDLAR_STL_Pos (0U) |
13291 | #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */ |
| 13292 | #define ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos) /*!< 0xFFFFFFFF */ |
13292 | #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */ |
| 13293 | #define ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */ |
13293 | |
| 13294 | 13294 | /* Bit definition for Ethernet DMA Status Register */ |
|
| 13295 | /* Bit definition for Ethernet DMA Status Register */ |
13295 | #define ETH_DMASR_TSTS_Pos (29U) |
| 13296 | #define ETH_DMASR_TSTS_Pos (29U) |
13296 | #define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */ |
| 13297 | #define ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos) /*!< 0x20000000 */ |
13297 | #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */ |
| 13298 | #define ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */ |
13298 | #define ETH_DMASR_PMTS_Pos (28U) |
| 13299 | #define ETH_DMASR_PMTS_Pos (28U) |
13299 | #define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */ |
| 13300 | #define ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos) /*!< 0x10000000 */ |
13300 | #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */ |
| 13301 | #define ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */ |
13301 | #define ETH_DMASR_MMCS_Pos (27U) |
| 13302 | #define ETH_DMASR_MMCS_Pos (27U) |
13302 | #define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */ |
| 13303 | #define ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos) /*!< 0x08000000 */ |
13303 | #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */ |
| 13304 | #define ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */ |
13304 | #define ETH_DMASR_EBS_Pos (23U) |
| 13305 | #define ETH_DMASR_EBS_Pos (23U) |
13305 | #define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */ |
| 13306 | #define ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos) /*!< 0x03800000 */ |
13306 | #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */ |
| 13307 | #define ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */ |
13307 | /* combination with EBS[2:0] for GetFlagStatus function */ |
| 13308 | /* combination with EBS[2:0] for GetFlagStatus function */ |
13308 | #define ETH_DMASR_EBS_DescAccess_Pos (25U) |
| 13309 | #define ETH_DMASR_EBS_DescAccess_Pos (25U) |
13309 | #define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */ |
| 13310 | #define ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos) /*!< 0x02000000 */ |
13310 | #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */ |
| 13311 | #define ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */ |
13311 | #define ETH_DMASR_EBS_ReadTransf_Pos (24U) |
| 13312 | #define ETH_DMASR_EBS_ReadTransf_Pos (24U) |
13312 | #define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */ |
| 13313 | #define ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos) /*!< 0x01000000 */ |
13313 | #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */ |
| 13314 | #define ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */ |
13314 | #define ETH_DMASR_EBS_DataTransfTx_Pos (23U) |
| 13315 | #define ETH_DMASR_EBS_DataTransfTx_Pos (23U) |
13315 | #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */ |
| 13316 | #define ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos) /*!< 0x00800000 */ |
13316 | #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */ |
| 13317 | #define ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */ |
13317 | #define ETH_DMASR_TPS_Pos (20U) |
| 13318 | #define ETH_DMASR_TPS_Pos (20U) |
13318 | #define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */ |
| 13319 | #define ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos) /*!< 0x00700000 */ |
13319 | #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */ |
| 13320 | #define ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */ |
13320 | #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */ |
| 13321 | #define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */ |
13321 | #define ETH_DMASR_TPS_Fetching_Pos (20U) |
| 13322 | #define ETH_DMASR_TPS_Fetching_Pos (20U) |
13322 | #define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */ |
| 13323 | #define ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos) /*!< 0x00100000 */ |
13323 | #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */ |
| 13324 | #define ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */ |
13324 | #define ETH_DMASR_TPS_Waiting_Pos (21U) |
| 13325 | #define ETH_DMASR_TPS_Waiting_Pos (21U) |
13325 | #define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */ |
| 13326 | #define ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos) /*!< 0x00200000 */ |
13326 | #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */ |
| 13327 | #define ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */ |
13327 | #define ETH_DMASR_TPS_Reading_Pos (20U) |
| 13328 | #define ETH_DMASR_TPS_Reading_Pos (20U) |
13328 | #define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */ |
| 13329 | #define ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos) /*!< 0x00300000 */ |
13329 | #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */ |
| 13330 | #define ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */ |
13330 | #define ETH_DMASR_TPS_Suspended_Pos (21U) |
| 13331 | #define ETH_DMASR_TPS_Suspended_Pos (21U) |
13331 | #define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */ |
| 13332 | #define ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos) /*!< 0x00600000 */ |
13332 | #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */ |
| 13333 | #define ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */ |
13333 | #define ETH_DMASR_TPS_Closing_Pos (20U) |
| 13334 | #define ETH_DMASR_TPS_Closing_Pos (20U) |
13334 | #define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */ |
| 13335 | #define ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos) /*!< 0x00700000 */ |
13335 | #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */ |
| 13336 | #define ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */ |
13336 | #define ETH_DMASR_RPS_Pos (17U) |
| 13337 | #define ETH_DMASR_RPS_Pos (17U) |
13337 | #define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */ |
| 13338 | #define ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos) /*!< 0x000E0000 */ |
13338 | #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */ |
| 13339 | #define ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */ |
13339 | #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */ |
| 13340 | #define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */ |
13340 | #define ETH_DMASR_RPS_Fetching_Pos (17U) |
| 13341 | #define ETH_DMASR_RPS_Fetching_Pos (17U) |
13341 | #define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */ |
| 13342 | #define ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos) /*!< 0x00020000 */ |
13342 | #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */ |
| 13343 | #define ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */ |
13343 | #define ETH_DMASR_RPS_Waiting_Pos (17U) |
| 13344 | #define ETH_DMASR_RPS_Waiting_Pos (17U) |
13344 | #define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */ |
| 13345 | #define ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos) /*!< 0x00060000 */ |
13345 | #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */ |
| 13346 | #define ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */ |
13346 | #define ETH_DMASR_RPS_Suspended_Pos (19U) |
| 13347 | #define ETH_DMASR_RPS_Suspended_Pos (19U) |
13347 | #define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */ |
| 13348 | #define ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos) /*!< 0x00080000 */ |
13348 | #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */ |
| 13349 | #define ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */ |
13349 | #define ETH_DMASR_RPS_Closing_Pos (17U) |
| 13350 | #define ETH_DMASR_RPS_Closing_Pos (17U) |
13350 | #define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */ |
| 13351 | #define ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos) /*!< 0x000A0000 */ |
13351 | #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ |
| 13352 | #define ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */ |
13352 | #define ETH_DMASR_RPS_Queuing_Pos (17U) |
| 13353 | #define ETH_DMASR_RPS_Queuing_Pos (17U) |
13353 | #define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ |
| 13354 | #define ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos) /*!< 0x000E0000 */ |
13354 | #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the receive frame into host memory */ |
| 13355 | #define ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */ |
13355 | #define ETH_DMASR_NIS_Pos (16U) |
| 13356 | #define ETH_DMASR_NIS_Pos (16U) |
13356 | #define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ |
| 13357 | #define ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos) /*!< 0x00010000 */ |
13357 | #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ |
| 13358 | #define ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */ |
13358 | #define ETH_DMASR_AIS_Pos (15U) |
| 13359 | #define ETH_DMASR_AIS_Pos (15U) |
13359 | #define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */ |
| 13360 | #define ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos) /*!< 0x00008000 */ |
13360 | #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */ |
| 13361 | #define ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */ |
13361 | #define ETH_DMASR_ERS_Pos (14U) |
| 13362 | #define ETH_DMASR_ERS_Pos (14U) |
13362 | #define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */ |
| 13363 | #define ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos) /*!< 0x00004000 */ |
13363 | #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */ |
| 13364 | #define ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */ |
13364 | #define ETH_DMASR_FBES_Pos (13U) |
| 13365 | #define ETH_DMASR_FBES_Pos (13U) |
13365 | #define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */ |
| 13366 | #define ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos) /*!< 0x00002000 */ |
13366 | #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */ |
| 13367 | #define ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */ |
13367 | #define ETH_DMASR_ETS_Pos (10U) |
| 13368 | #define ETH_DMASR_ETS_Pos (10U) |
13368 | #define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */ |
| 13369 | #define ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos) /*!< 0x00000400 */ |
13369 | #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */ |
| 13370 | #define ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */ |
13370 | #define ETH_DMASR_RWTS_Pos (9U) |
| 13371 | #define ETH_DMASR_RWTS_Pos (9U) |
13371 | #define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */ |
| 13372 | #define ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos) /*!< 0x00000200 */ |
13372 | #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */ |
| 13373 | #define ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */ |
13373 | #define ETH_DMASR_RPSS_Pos (8U) |
| 13374 | #define ETH_DMASR_RPSS_Pos (8U) |
13374 | #define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */ |
| 13375 | #define ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos) /*!< 0x00000100 */ |
13375 | #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */ |
| 13376 | #define ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */ |
13376 | #define ETH_DMASR_RBUS_Pos (7U) |
| 13377 | #define ETH_DMASR_RBUS_Pos (7U) |
13377 | #define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */ |
| 13378 | #define ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos) /*!< 0x00000080 */ |
13378 | #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */ |
| 13379 | #define ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */ |
13379 | #define ETH_DMASR_RS_Pos (6U) |
| 13380 | #define ETH_DMASR_RS_Pos (6U) |
13380 | #define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */ |
| 13381 | #define ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos) /*!< 0x00000040 */ |
13381 | #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */ |
| 13382 | #define ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */ |
13382 | #define ETH_DMASR_TUS_Pos (5U) |
| 13383 | #define ETH_DMASR_TUS_Pos (5U) |
13383 | #define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */ |
| 13384 | #define ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos) /*!< 0x00000020 */ |
13384 | #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */ |
| 13385 | #define ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */ |
13385 | #define ETH_DMASR_ROS_Pos (4U) |
| 13386 | #define ETH_DMASR_ROS_Pos (4U) |
13386 | #define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */ |
| 13387 | #define ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos) /*!< 0x00000010 */ |
13387 | #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */ |
| 13388 | #define ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */ |
13388 | #define ETH_DMASR_TJTS_Pos (3U) |
| 13389 | #define ETH_DMASR_TJTS_Pos (3U) |
13389 | #define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */ |
| 13390 | #define ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos) /*!< 0x00000008 */ |
13390 | #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */ |
| 13391 | #define ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */ |
13391 | #define ETH_DMASR_TBUS_Pos (2U) |
| 13392 | #define ETH_DMASR_TBUS_Pos (2U) |
13392 | #define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */ |
| 13393 | #define ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos) /*!< 0x00000004 */ |
13393 | #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */ |
| 13394 | #define ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */ |
13394 | #define ETH_DMASR_TPSS_Pos (1U) |
| 13395 | #define ETH_DMASR_TPSS_Pos (1U) |
13395 | #define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */ |
| 13396 | #define ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos) /*!< 0x00000002 */ |
13396 | #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */ |
| 13397 | #define ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */ |
13397 | #define ETH_DMASR_TS_Pos (0U) |
| 13398 | #define ETH_DMASR_TS_Pos (0U) |
13398 | #define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */ |
| 13399 | #define ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos) /*!< 0x00000001 */ |
13399 | #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */ |
| 13400 | #define ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */ |
13400 | |
| 13401 | 13401 | /* Bit definition for Ethernet DMA Operation Mode Register */ |
|
| 13402 | /* Bit definition for Ethernet DMA Operation Mode Register */ |
13402 | #define ETH_DMAOMR_DTCEFD_Pos (26U) |
| 13403 | #define ETH_DMAOMR_DTCEFD_Pos (26U) |
13403 | #define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */ |
| 13404 | #define ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos) /*!< 0x04000000 */ |
13404 | #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */ |
| 13405 | #define ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */ |
13405 | #define ETH_DMAOMR_RSF_Pos (25U) |
| 13406 | #define ETH_DMAOMR_RSF_Pos (25U) |
13406 | #define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */ |
| 13407 | #define ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos) /*!< 0x02000000 */ |
13407 | #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */ |
| 13408 | #define ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */ |
13408 | #define ETH_DMAOMR_DFRF_Pos (24U) |
| 13409 | #define ETH_DMAOMR_DFRF_Pos (24U) |
13409 | #define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */ |
| 13410 | #define ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos) /*!< 0x01000000 */ |
13410 | #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */ |
| 13411 | #define ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */ |
13411 | #define ETH_DMAOMR_TSF_Pos (21U) |
| 13412 | #define ETH_DMAOMR_TSF_Pos (21U) |
13412 | #define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */ |
| 13413 | #define ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos) /*!< 0x00200000 */ |
13413 | #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */ |
| 13414 | #define ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */ |
13414 | #define ETH_DMAOMR_FTF_Pos (20U) |
| 13415 | #define ETH_DMAOMR_FTF_Pos (20U) |
13415 | #define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */ |
| 13416 | #define ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos) /*!< 0x00100000 */ |
13416 | #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */ |
| 13417 | #define ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */ |
13417 | #define ETH_DMAOMR_TTC_Pos (14U) |
| 13418 | #define ETH_DMAOMR_TTC_Pos (14U) |
13418 | #define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */ |
| 13419 | #define ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos) /*!< 0x0001C000 */ |
13419 | #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */ |
| 13420 | #define ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */ |
13420 | #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
| 13421 | #define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */ |
13421 | #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
| 13422 | #define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */ |
13422 | #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
| 13423 | #define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */ |
13423 | #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
| 13424 | #define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */ |
13424 | #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
| 13425 | #define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */ |
13425 | #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
| 13426 | #define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */ |
13426 | #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
| 13427 | #define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */ |
13427 | #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
| 13428 | #define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */ |
13428 | #define ETH_DMAOMR_ST_Pos (13U) |
| 13429 | #define ETH_DMAOMR_ST_Pos (13U) |
13429 | #define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */ |
| 13430 | #define ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos) /*!< 0x00002000 */ |
13430 | #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */ |
| 13431 | #define ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */ |
13431 | #define ETH_DMAOMR_FEF_Pos (7U) |
| 13432 | #define ETH_DMAOMR_FEF_Pos (7U) |
13432 | #define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */ |
| 13433 | #define ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos) /*!< 0x00000080 */ |
13433 | #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */ |
| 13434 | #define ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */ |
13434 | #define ETH_DMAOMR_FUGF_Pos (6U) |
| 13435 | #define ETH_DMAOMR_FUGF_Pos (6U) |
13435 | #define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */ |
| 13436 | #define ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos) /*!< 0x00000040 */ |
13436 | #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */ |
| 13437 | #define ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */ |
13437 | #define ETH_DMAOMR_RTC_Pos (3U) |
| 13438 | #define ETH_DMAOMR_RTC_Pos (3U) |
13438 | #define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */ |
| 13439 | #define ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos) /*!< 0x00000018 */ |
13439 | #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */ |
| 13440 | #define ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */ |
13440 | #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
| 13441 | #define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */ |
13441 | #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
| 13442 | #define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */ |
13442 | #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
| 13443 | #define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */ |
13443 | #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
| 13444 | #define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */ |
13444 | #define ETH_DMAOMR_OSF_Pos (2U) |
| 13445 | #define ETH_DMAOMR_OSF_Pos (2U) |
13445 | #define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */ |
| 13446 | #define ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos) /*!< 0x00000004 */ |
13446 | #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */ |
| 13447 | #define ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */ |
13447 | #define ETH_DMAOMR_SR_Pos (1U) |
| 13448 | #define ETH_DMAOMR_SR_Pos (1U) |
13448 | #define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */ |
| 13449 | #define ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos) /*!< 0x00000002 */ |
13449 | #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */ |
| 13450 | #define ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */ |
13450 | |
| 13451 | 13451 | /* Bit definition for Ethernet DMA Interrupt Enable Register */ |
|
| 13452 | /* Bit definition for Ethernet DMA Interrupt Enable Register */ |
13452 | #define ETH_DMAIER_NISE_Pos (16U) |
| 13453 | #define ETH_DMAIER_NISE_Pos (16U) |
13453 | #define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */ |
| 13454 | #define ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos) /*!< 0x00010000 */ |
13454 | #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */ |
| 13455 | #define ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */ |
13455 | #define ETH_DMAIER_AISE_Pos (15U) |
| 13456 | #define ETH_DMAIER_AISE_Pos (15U) |
13456 | #define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */ |
| 13457 | #define ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos) /*!< 0x00008000 */ |
13457 | #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */ |
| 13458 | #define ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */ |
13458 | #define ETH_DMAIER_ERIE_Pos (14U) |
| 13459 | #define ETH_DMAIER_ERIE_Pos (14U) |
13459 | #define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */ |
| 13460 | #define ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos) /*!< 0x00004000 */ |
13460 | #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */ |
| 13461 | #define ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */ |
13461 | #define ETH_DMAIER_FBEIE_Pos (13U) |
| 13462 | #define ETH_DMAIER_FBEIE_Pos (13U) |
13462 | #define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */ |
| 13463 | #define ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos) /*!< 0x00002000 */ |
13463 | #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */ |
| 13464 | #define ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */ |
13464 | #define ETH_DMAIER_ETIE_Pos (10U) |
| 13465 | #define ETH_DMAIER_ETIE_Pos (10U) |
13465 | #define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */ |
| 13466 | #define ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos) /*!< 0x00000400 */ |
13466 | #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */ |
| 13467 | #define ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */ |
13467 | #define ETH_DMAIER_RWTIE_Pos (9U) |
| 13468 | #define ETH_DMAIER_RWTIE_Pos (9U) |
13468 | #define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */ |
| 13469 | #define ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos) /*!< 0x00000200 */ |
13469 | #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */ |
| 13470 | #define ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */ |
13470 | #define ETH_DMAIER_RPSIE_Pos (8U) |
| 13471 | #define ETH_DMAIER_RPSIE_Pos (8U) |
13471 | #define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */ |
| 13472 | #define ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos) /*!< 0x00000100 */ |
13472 | #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */ |
| 13473 | #define ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */ |
13473 | #define ETH_DMAIER_RBUIE_Pos (7U) |
| 13474 | #define ETH_DMAIER_RBUIE_Pos (7U) |
13474 | #define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */ |
| 13475 | #define ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos) /*!< 0x00000080 */ |
13475 | #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */ |
| 13476 | #define ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */ |
13476 | #define ETH_DMAIER_RIE_Pos (6U) |
| 13477 | #define ETH_DMAIER_RIE_Pos (6U) |
13477 | #define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */ |
| 13478 | #define ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos) /*!< 0x00000040 */ |
13478 | #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */ |
| 13479 | #define ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */ |
13479 | #define ETH_DMAIER_TUIE_Pos (5U) |
| 13480 | #define ETH_DMAIER_TUIE_Pos (5U) |
13480 | #define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */ |
| 13481 | #define ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos) /*!< 0x00000020 */ |
13481 | #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */ |
| 13482 | #define ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */ |
13482 | #define ETH_DMAIER_ROIE_Pos (4U) |
| 13483 | #define ETH_DMAIER_ROIE_Pos (4U) |
13483 | #define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */ |
| 13484 | #define ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos) /*!< 0x00000010 */ |
13484 | #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */ |
| 13485 | #define ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */ |
13485 | #define ETH_DMAIER_TJTIE_Pos (3U) |
| 13486 | #define ETH_DMAIER_TJTIE_Pos (3U) |
13486 | #define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */ |
| 13487 | #define ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos) /*!< 0x00000008 */ |
13487 | #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */ |
| 13488 | #define ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */ |
13488 | #define ETH_DMAIER_TBUIE_Pos (2U) |
| 13489 | #define ETH_DMAIER_TBUIE_Pos (2U) |
13489 | #define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */ |
| 13490 | #define ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos) /*!< 0x00000004 */ |
13490 | #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */ |
| 13491 | #define ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */ |
13491 | #define ETH_DMAIER_TPSIE_Pos (1U) |
| 13492 | #define ETH_DMAIER_TPSIE_Pos (1U) |
13492 | #define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */ |
| 13493 | #define ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos) /*!< 0x00000002 */ |
13493 | #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */ |
| 13494 | #define ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */ |
13494 | #define ETH_DMAIER_TIE_Pos (0U) |
| 13495 | #define ETH_DMAIER_TIE_Pos (0U) |
13495 | #define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */ |
| 13496 | #define ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos) /*!< 0x00000001 */ |
13496 | #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */ |
| 13497 | #define ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */ |
13497 | |
| 13498 | 13498 | /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ |
|
| 13499 | /* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */ |
13499 | #define ETH_DMAMFBOCR_OFOC_Pos (28U) |
| 13500 | #define ETH_DMAMFBOCR_OFOC_Pos (28U) |
13500 | #define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */ |
| 13501 | #define ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos) /*!< 0x10000000 */ |
13501 | #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */ |
| 13502 | #define ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */ |
13502 | #define ETH_DMAMFBOCR_MFA_Pos (17U) |
| 13503 | #define ETH_DMAMFBOCR_MFA_Pos (17U) |
13503 | #define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */ |
| 13504 | #define ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos) /*!< 0x0FFE0000 */ |
13504 | #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */ |
| 13505 | #define ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */ |
13505 | #define ETH_DMAMFBOCR_OMFC_Pos (16U) |
| 13506 | #define ETH_DMAMFBOCR_OMFC_Pos (16U) |
13506 | #define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */ |
| 13507 | #define ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos) /*!< 0x00010000 */ |
13507 | #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */ |
| 13508 | #define ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */ |
13508 | #define ETH_DMAMFBOCR_MFC_Pos (0U) |
| 13509 | #define ETH_DMAMFBOCR_MFC_Pos (0U) |
13509 | #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */ |
| 13510 | #define ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos) /*!< 0x0000FFFF */ |
13510 | #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */ |
| 13511 | #define ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */ |
13511 | |
| 13512 | 13512 | /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ |
|
| 13513 | /* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */ |
13513 | #define ETH_DMACHTDR_HTDAP_Pos (0U) |
| 13514 | #define ETH_DMACHTDR_HTDAP_Pos (0U) |
13514 | #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */ |
| 13515 | #define ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos) /*!< 0xFFFFFFFF */ |
13515 | #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */ |
| 13516 | #define ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */ |
13516 | |
| 13517 | 13517 | /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ |
|
| 13518 | /* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */ |
13518 | #define ETH_DMACHRDR_HRDAP_Pos (0U) |
| 13519 | #define ETH_DMACHRDR_HRDAP_Pos (0U) |
13519 | #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */ |
| 13520 | #define ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos) /*!< 0xFFFFFFFF */ |
13520 | #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */ |
| 13521 | #define ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */ |
13521 | |
| 13522 | 13522 | /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ |
|
| 13523 | /* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */ |
13523 | #define ETH_DMACHTBAR_HTBAP_Pos (0U) |
| 13524 | #define ETH_DMACHTBAR_HTBAP_Pos (0U) |
13524 | #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */ |
| 13525 | #define ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos) /*!< 0xFFFFFFFF */ |
13525 | #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */ |
| 13526 | #define ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */ |
13526 | |
| 13527 | 13527 | /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ |
|
| 13528 | /* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */ |
13528 | #define ETH_DMACHRBAR_HRBAP_Pos (0U) |
| 13529 | #define ETH_DMACHRBAR_HRBAP_Pos (0U) |
13529 | #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */ |
| 13530 | #define ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos) /*!< 0xFFFFFFFF */ |
13530 | #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */ |
| 13531 | #define ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */ |
13531 | |
| 13532 | 13532 | /******************************************************************************/ |
|
| 13533 | /******************************************************************************/ |
13533 | /* */ |
| 13534 | /* */ |
13534 | /* USB_OTG */ |
| 13535 | /* USB_OTG */ |
13535 | /* */ |
| 13536 | /* */ |
13536 | /******************************************************************************/ |
| 13537 | /******************************************************************************/ |
13537 | /******************** Bit definition for USB_OTG_GOTGCTL register ***********/ |
| 13538 | /******************** Bit definition for USB_OTG_GOTGCTL register ***********/ |
13538 | #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) |
| 13539 | #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) |
13539 | #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ |
| 13540 | #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ |
13540 | #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ |
| 13541 | #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ |
13541 | #define USB_OTG_GOTGCTL_SRQ_Pos (1U) |
| 13542 | #define USB_OTG_GOTGCTL_SRQ_Pos (1U) |
13542 | #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ |
| 13543 | #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ |
13543 | #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ |
| 13544 | #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ |
13544 | #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) |
| 13545 | #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) |
13545 | #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ |
| 13546 | #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ |
13546 | #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ |
| 13547 | #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ |
13547 | #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) |
| 13548 | #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) |
13548 | #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ |
| 13549 | #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ |
13549 | #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ |
| 13550 | #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ |
13550 | #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) |
| 13551 | #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) |
13551 | #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ |
| 13552 | #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ |
13552 | #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ |
| 13553 | #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ |
13553 | #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) |
| 13554 | #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) |
13554 | #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ |
| 13555 | #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ |
13555 | #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ |
| 13556 | #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ |
13556 | #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) |
| 13557 | #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) |
13557 | #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ |
| 13558 | #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ |
13558 | #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ |
| 13559 | #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ |
13559 | #define USB_OTG_GOTGCTL_DBCT_Pos (17U) |
| 13560 | #define USB_OTG_GOTGCTL_DBCT_Pos (17U) |
13560 | #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ |
| 13561 | #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ |
13561 | #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ |
| 13562 | #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ |
13562 | #define USB_OTG_GOTGCTL_ASVLD_Pos (18U) |
| 13563 | #define USB_OTG_GOTGCTL_ASVLD_Pos (18U) |
13563 | #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ |
| 13564 | #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ |
13564 | #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ |
| 13565 | #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ |
13565 | #define USB_OTG_GOTGCTL_BSVLD_Pos (19U) |
| 13566 | #define USB_OTG_GOTGCTL_BSVLD_Pos (19U) |
13566 | #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ |
| 13567 | #define USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos) /*!< 0x00080000 */ |
13567 | #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ |
| 13568 | #define USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk /*!< B-session valid */ |
13568 | |
| 13569 | 13569 | /******************** Bit definition for USB_OTG_HCFG register ********************/ |
|
| 13570 | /******************** Bit definition for USB_OTG_HCFG register ********************/ |
13570 | |
| 13571 | 13571 | #define USB_OTG_HCFG_FSLSPCS_Pos (0U) |
|
| 13572 | #define USB_OTG_HCFG_FSLSPCS_Pos (0U) |
13572 | #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ |
| 13573 | #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ |
13573 | #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ |
| 13574 | #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ |
13574 | #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ |
| 13575 | #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ |
13575 | #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ |
| 13576 | #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ |
13576 | #define USB_OTG_HCFG_FSLSS_Pos (2U) |
| 13577 | #define USB_OTG_HCFG_FSLSS_Pos (2U) |
13577 | #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ |
| 13578 | #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ |
13578 | #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ |
| 13579 | #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ |
13579 | |
| 13580 | 13580 | /******************** Bit definition for USB_OTG_DCFG register ********************/ |
|
| 13581 | /******************** Bit definition for USB_OTG_DCFG register ********************/ |
13581 | |
| 13582 | 13582 | #define USB_OTG_DCFG_DSPD_Pos (0U) |
|
| 13583 | #define USB_OTG_DCFG_DSPD_Pos (0U) |
13583 | #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ |
| 13584 | #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ |
13584 | #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ |
| 13585 | #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ |
13585 | #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ |
| 13586 | #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ |
13586 | #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ |
| 13587 | #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ |
13587 | #define USB_OTG_DCFG_NZLSOHSK_Pos (2U) |
| 13588 | #define USB_OTG_DCFG_NZLSOHSK_Pos (2U) |
13588 | #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ |
| 13589 | #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ |
13589 | #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ |
| 13590 | #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ |
13590 | |
| 13591 | 13591 | #define USB_OTG_DCFG_DAD_Pos (4U) |
|
| 13592 | #define USB_OTG_DCFG_DAD_Pos (4U) |
13592 | #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ |
| 13593 | #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ |
13593 | #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ |
| 13594 | #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ |
13594 | #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ |
| 13595 | #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ |
13595 | #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ |
| 13596 | #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ |
13596 | #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ |
| 13597 | #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ |
13597 | #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ |
| 13598 | #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ |
13598 | #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ |
| 13599 | #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ |
13599 | #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ |
| 13600 | #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ |
13600 | #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ |
| 13601 | #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ |
13601 | |
| 13602 | 13602 | #define USB_OTG_DCFG_PFIVL_Pos (11U) |
|
| 13603 | #define USB_OTG_DCFG_PFIVL_Pos (11U) |
13603 | #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ |
| 13604 | #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ |
13604 | #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ |
| 13605 | #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ |
13605 | #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ |
| 13606 | #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ |
13606 | #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ |
| 13607 | #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ |
13607 | |
| 13608 | 13608 | #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) |
|
| 13609 | #define USB_OTG_DCFG_PERSCHIVL_Pos (24U) |
13609 | #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ |
| 13610 | #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ |
13610 | #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ |
| 13611 | #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ |
13611 | #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ |
| 13612 | #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ |
13612 | #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ |
| 13613 | #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ |
13613 | |
| 13614 | 13614 | /******************** Bit definition for USB_OTG_PCGCR register ********************/ |
|
| 13615 | /******************** Bit definition for USB_OTG_PCGCR register ********************/ |
13615 | #define USB_OTG_PCGCR_STPPCLK_Pos (0U) |
| 13616 | #define USB_OTG_PCGCR_STPPCLK_Pos (0U) |
13616 | #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ |
| 13617 | #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ |
13617 | #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ |
| 13618 | #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ |
13618 | #define USB_OTG_PCGCR_GATEHCLK_Pos (1U) |
| 13619 | #define USB_OTG_PCGCR_GATEHCLK_Pos (1U) |
13619 | #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ |
| 13620 | #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ |
13620 | #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ |
| 13621 | #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ |
13621 | #define USB_OTG_PCGCR_PHYSUSP_Pos (4U) |
| 13622 | #define USB_OTG_PCGCR_PHYSUSP_Pos (4U) |
13622 | #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ |
| 13623 | #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ |
13623 | #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ |
| 13624 | #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ |
13624 | |
| 13625 | 13625 | /******************** Bit definition for USB_OTG_GOTGINT register ********************/ |
|
| 13626 | /******************** Bit definition for USB_OTG_GOTGINT register ********************/ |
13626 | #define USB_OTG_GOTGINT_SEDET_Pos (2U) |
| 13627 | #define USB_OTG_GOTGINT_SEDET_Pos (2U) |
13627 | #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ |
| 13628 | #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ |
13628 | #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ |
| 13629 | #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ |
13629 | #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) |
| 13630 | #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) |
13630 | #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ |
| 13631 | #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ |
13631 | #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ |
| 13632 | #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ |
13632 | #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) |
| 13633 | #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) |
13633 | #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ |
| 13634 | #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ |
13634 | #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ |
| 13635 | #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ |
13635 | #define USB_OTG_GOTGINT_HNGDET_Pos (17U) |
| 13636 | #define USB_OTG_GOTGINT_HNGDET_Pos (17U) |
13636 | #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ |
| 13637 | #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ |
13637 | #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ |
| 13638 | #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ |
13638 | #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) |
| 13639 | #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) |
13639 | #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ |
| 13640 | #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ |
13640 | #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ |
| 13641 | #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ |
13641 | #define USB_OTG_GOTGINT_DBCDNE_Pos (19U) |
| 13642 | #define USB_OTG_GOTGINT_DBCDNE_Pos (19U) |
13642 | #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ |
| 13643 | #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ |
13643 | #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ |
| 13644 | #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ |
13644 | |
| 13645 | 13645 | /******************** Bit definition for USB_OTG_DCTL register ********************/ |
|
| 13646 | /******************** Bit definition for USB_OTG_DCTL register ********************/ |
13646 | #define USB_OTG_DCTL_RWUSIG_Pos (0U) |
| 13647 | #define USB_OTG_DCTL_RWUSIG_Pos (0U) |
13647 | #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ |
| 13648 | #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ |
13648 | #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ |
| 13649 | #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ |
13649 | #define USB_OTG_DCTL_SDIS_Pos (1U) |
| 13650 | #define USB_OTG_DCTL_SDIS_Pos (1U) |
13650 | #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ |
| 13651 | #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ |
13651 | #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ |
| 13652 | #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ |
13652 | #define USB_OTG_DCTL_GINSTS_Pos (2U) |
| 13653 | #define USB_OTG_DCTL_GINSTS_Pos (2U) |
13653 | #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ |
| 13654 | #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ |
13654 | #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ |
| 13655 | #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ |
13655 | #define USB_OTG_DCTL_GONSTS_Pos (3U) |
| 13656 | #define USB_OTG_DCTL_GONSTS_Pos (3U) |
13656 | #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ |
| 13657 | #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ |
13657 | #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ |
| 13658 | #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ |
13658 | |
| 13659 | 13659 | #define USB_OTG_DCTL_TCTL_Pos (4U) |
|
| 13660 | #define USB_OTG_DCTL_TCTL_Pos (4U) |
13660 | #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ |
| 13661 | #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ |
13661 | #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ |
| 13662 | #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ |
13662 | #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ |
| 13663 | #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ |
13663 | #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ |
| 13664 | #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ |
13664 | #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ |
| 13665 | #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ |
13665 | #define USB_OTG_DCTL_SGINAK_Pos (7U) |
| 13666 | #define USB_OTG_DCTL_SGINAK_Pos (7U) |
13666 | #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ |
| 13667 | #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ |
13667 | #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ |
| 13668 | #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ |
13668 | #define USB_OTG_DCTL_CGINAK_Pos (8U) |
| 13669 | #define USB_OTG_DCTL_CGINAK_Pos (8U) |
13669 | #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ |
| 13670 | #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ |
13670 | #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ |
| 13671 | #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ |
13671 | #define USB_OTG_DCTL_SGONAK_Pos (9U) |
| 13672 | #define USB_OTG_DCTL_SGONAK_Pos (9U) |
13672 | #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ |
| 13673 | #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ |
13673 | #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ |
| 13674 | #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ |
13674 | #define USB_OTG_DCTL_CGONAK_Pos (10U) |
| 13675 | #define USB_OTG_DCTL_CGONAK_Pos (10U) |
13675 | #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ |
| 13676 | #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ |
13676 | #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ |
| 13677 | #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ |
13677 | #define USB_OTG_DCTL_POPRGDNE_Pos (11U) |
| 13678 | #define USB_OTG_DCTL_POPRGDNE_Pos (11U) |
13678 | #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ |
| 13679 | #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ |
13679 | #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ |
| 13680 | #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ |
13680 | |
| 13681 | 13681 | /******************** Bit definition for USB_OTG_HFIR register ********************/ |
|
| 13682 | /******************** Bit definition for USB_OTG_HFIR register ********************/ |
13682 | #define USB_OTG_HFIR_FRIVL_Pos (0U) |
| 13683 | #define USB_OTG_HFIR_FRIVL_Pos (0U) |
13683 | #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ |
| 13684 | #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ |
13684 | #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ |
| 13685 | #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ |
13685 | |
| 13686 | 13686 | /******************** Bit definition for USB_OTG_HFNUM register ********************/ |
|
| 13687 | /******************** Bit definition for USB_OTG_HFNUM register ********************/ |
13687 | #define USB_OTG_HFNUM_FRNUM_Pos (0U) |
| 13688 | #define USB_OTG_HFNUM_FRNUM_Pos (0U) |
13688 | #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ |
| 13689 | #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ |
13689 | #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ |
| 13690 | #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ |
13690 | #define USB_OTG_HFNUM_FTREM_Pos (16U) |
| 13691 | #define USB_OTG_HFNUM_FTREM_Pos (16U) |
13691 | #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ |
| 13692 | #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ |
13692 | #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ |
| 13693 | #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ |
13693 | |
| 13694 | 13694 | /******************** Bit definition for USB_OTG_DSTS register ********************/ |
|
| 13695 | /******************** Bit definition for USB_OTG_DSTS register ********************/ |
13695 | #define USB_OTG_DSTS_SUSPSTS_Pos (0U) |
| 13696 | #define USB_OTG_DSTS_SUSPSTS_Pos (0U) |
13696 | #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ |
| 13697 | #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ |
13697 | #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ |
| 13698 | #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ |
13698 | |
| 13699 | 13699 | #define USB_OTG_DSTS_ENUMSPD_Pos (1U) |
|
| 13700 | #define USB_OTG_DSTS_ENUMSPD_Pos (1U) |
13700 | #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ |
| 13701 | #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ |
13701 | #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ |
| 13702 | #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ |
13702 | #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ |
| 13703 | #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ |
13703 | #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ |
| 13704 | #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ |
13704 | #define USB_OTG_DSTS_EERR_Pos (3U) |
| 13705 | #define USB_OTG_DSTS_EERR_Pos (3U) |
13705 | #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ |
| 13706 | #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ |
13706 | #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ |
| 13707 | #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ |
13707 | #define USB_OTG_DSTS_FNSOF_Pos (8U) |
| 13708 | #define USB_OTG_DSTS_FNSOF_Pos (8U) |
13708 | #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ |
| 13709 | #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ |
13709 | #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ |
| 13710 | #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ |
13710 | |
| 13711 | 13711 | /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ |
|
| 13712 | /******************** Bit definition for USB_OTG_GAHBCFG register ********************/ |
13712 | #define USB_OTG_GAHBCFG_GINT_Pos (0U) |
| 13713 | #define USB_OTG_GAHBCFG_GINT_Pos (0U) |
13713 | #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ |
| 13714 | #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ |
13714 | #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ |
| 13715 | #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ |
13715 | #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) |
| 13716 | #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) |
13716 | #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ |
| 13717 | #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ |
13717 | #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ |
| 13718 | #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ |
13718 | #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ |
| 13719 | #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ |
13719 | #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ |
| 13720 | #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ |
13720 | #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ |
| 13721 | #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ |
13721 | #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ |
| 13722 | #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ |
13722 | #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ |
| 13723 | #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ |
13723 | #define USB_OTG_GAHBCFG_DMAEN_Pos (5U) |
| 13724 | #define USB_OTG_GAHBCFG_DMAEN_Pos (5U) |
13724 | #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ |
| 13725 | #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ |
13725 | #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ |
| 13726 | #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ |
13726 | #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) |
| 13727 | #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) |
13727 | #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ |
| 13728 | #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ |
13728 | #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ |
| 13729 | #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ |
13729 | #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) |
| 13730 | #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) |
13730 | #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ |
| 13731 | #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ |
13731 | #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ |
| 13732 | #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ |
13732 | |
| 13733 | 13733 | /******************** Bit definition for USB_OTG_GUSBCFG register ********************/ |
|
| 13734 | /******************** Bit definition for USB_OTG_GUSBCFG register ********************/ |
13734 | |
| 13735 | 13735 | #define USB_OTG_GUSBCFG_TOCAL_Pos (0U) |
|
| 13736 | #define USB_OTG_GUSBCFG_TOCAL_Pos (0U) |
13736 | #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ |
| 13737 | #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ |
13737 | #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ |
| 13738 | #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ |
13738 | #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ |
| 13739 | #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ |
13739 | #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ |
| 13740 | #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ |
13740 | #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ |
| 13741 | #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ |
13741 | #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) |
| 13742 | #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) |
13742 | #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ |
| 13743 | #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ |
13743 | #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ |
| 13744 | #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ |
13744 | #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) |
| 13745 | #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) |
13745 | #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ |
| 13746 | #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ |
13746 | #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ |
| 13747 | #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ |
13747 | #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) |
| 13748 | #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) |
13748 | #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ |
| 13749 | #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ |
13749 | #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ |
| 13750 | #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ |
13750 | #define USB_OTG_GUSBCFG_TRDT_Pos (10U) |
| 13751 | #define USB_OTG_GUSBCFG_TRDT_Pos (10U) |
13751 | #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ |
| 13752 | #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ |
13752 | #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ |
| 13753 | #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ |
13753 | #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ |
| 13754 | #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ |
13754 | #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ |
| 13755 | #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ |
13755 | #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ |
| 13756 | #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ |
13756 | #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ |
| 13757 | #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ |
13757 | #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) |
| 13758 | #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) |
13758 | #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ |
| 13759 | #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ |
13759 | #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ |
| 13760 | #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ |
13760 | #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) |
| 13761 | #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) |
13761 | #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ |
| 13762 | #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ |
13762 | #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ |
| 13763 | #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ |
13763 | #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) |
| 13764 | #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) |
13764 | #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ |
| 13765 | #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ |
13765 | #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ |
| 13766 | #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ |
13766 | #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) |
| 13767 | #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) |
13767 | #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ |
| 13768 | #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ |
13768 | #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ |
| 13769 | #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ |
13769 | #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) |
| 13770 | #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) |
13770 | #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ |
| 13771 | #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ |
13771 | #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ |
| 13772 | #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ |
13772 | #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) |
| 13773 | #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) |
13773 | #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ |
| 13774 | #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ |
13774 | #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ |
| 13775 | #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ |
13775 | #define USB_OTG_GUSBCFG_TSDPS_Pos (22U) |
| 13776 | #define USB_OTG_GUSBCFG_TSDPS_Pos (22U) |
13776 | #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ |
| 13777 | #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ |
13777 | #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ |
| 13778 | #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ |
13778 | #define USB_OTG_GUSBCFG_PCCI_Pos (23U) |
| 13779 | #define USB_OTG_GUSBCFG_PCCI_Pos (23U) |
13779 | #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ |
| 13780 | #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ |
13780 | #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ |
| 13781 | #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ |
13781 | #define USB_OTG_GUSBCFG_PTCI_Pos (24U) |
| 13782 | #define USB_OTG_GUSBCFG_PTCI_Pos (24U) |
13782 | #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ |
| 13783 | #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ |
13783 | #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ |
| 13784 | #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ |
13784 | #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) |
| 13785 | #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) |
13785 | #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ |
| 13786 | #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ |
13786 | #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ |
| 13787 | #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ |
13787 | #define USB_OTG_GUSBCFG_FHMOD_Pos (29U) |
| 13788 | #define USB_OTG_GUSBCFG_FHMOD_Pos (29U) |
13788 | #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ |
| 13789 | #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ |
13789 | #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ |
| 13790 | #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ |
13790 | #define USB_OTG_GUSBCFG_FDMOD_Pos (30U) |
| 13791 | #define USB_OTG_GUSBCFG_FDMOD_Pos (30U) |
13791 | #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ |
| 13792 | #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ |
13792 | #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ |
| 13793 | #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ |
13793 | #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) |
| 13794 | #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) |
13794 | #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ |
| 13795 | #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ |
13795 | #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ |
| 13796 | #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ |
13796 | |
| 13797 | 13797 | /******************** Bit definition for USB_OTG_GRSTCTL register ********************/ |
|
| 13798 | /******************** Bit definition for USB_OTG_GRSTCTL register ********************/ |
13798 | #define USB_OTG_GRSTCTL_CSRST_Pos (0U) |
| 13799 | #define USB_OTG_GRSTCTL_CSRST_Pos (0U) |
13799 | #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ |
| 13800 | #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ |
13800 | #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ |
| 13801 | #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ |
13801 | #define USB_OTG_GRSTCTL_HSRST_Pos (1U) |
| 13802 | #define USB_OTG_GRSTCTL_HSRST_Pos (1U) |
13802 | #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ |
| 13803 | #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ |
13803 | #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ |
| 13804 | #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ |
13804 | #define USB_OTG_GRSTCTL_FCRST_Pos (2U) |
| 13805 | #define USB_OTG_GRSTCTL_FCRST_Pos (2U) |
13805 | #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ |
| 13806 | #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ |
13806 | #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ |
| 13807 | #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ |
13807 | #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) |
| 13808 | #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) |
13808 | #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ |
| 13809 | #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ |
13809 | #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ |
| 13810 | #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ |
13810 | #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) |
| 13811 | #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) |
13811 | #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ |
| 13812 | #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ |
13812 | #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ |
| 13813 | #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ |
13813 | |
| 13814 | 13814 | ||
| 13815 | 13815 | #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) |
|
| 13816 | #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) |
13816 | #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ |
| 13817 | #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ |
13817 | #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ |
| 13818 | #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ |
13818 | #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ |
| 13819 | #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ |
13819 | #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ |
| 13820 | #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ |
13820 | #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ |
| 13821 | #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ |
13821 | #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ |
| 13822 | #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ |
13822 | #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ |
| 13823 | #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ |
13823 | #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) |
| 13824 | #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) |
13824 | #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ |
| 13825 | #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ |
13825 | #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ |
| 13826 | #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ |
13826 | #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) |
| 13827 | #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) |
13827 | #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ |
| 13828 | #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ |
13828 | #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ |
| 13829 | #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ |
13829 | |
| 13830 | 13830 | /******************** Bit definition for USB_OTG_DIEPMSK register ********************/ |
|
| 13831 | /******************** Bit definition for USB_OTG_DIEPMSK register ********************/ |
13831 | #define USB_OTG_DIEPMSK_XFRCM_Pos (0U) |
| 13832 | #define USB_OTG_DIEPMSK_XFRCM_Pos (0U) |
13832 | #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ |
| 13833 | #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ |
13833 | #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| 13834 | #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
13834 | #define USB_OTG_DIEPMSK_EPDM_Pos (1U) |
| 13835 | #define USB_OTG_DIEPMSK_EPDM_Pos (1U) |
13835 | #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ |
| 13836 | #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ |
13836 | #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| 13837 | #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
13837 | #define USB_OTG_DIEPMSK_TOM_Pos (3U) |
| 13838 | #define USB_OTG_DIEPMSK_TOM_Pos (3U) |
13838 | #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ |
| 13839 | #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ |
13839 | #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ |
| 13840 | #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ |
13840 | #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) |
| 13841 | #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) |
13841 | #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
| 13842 | #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
13842 | #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
| 13843 | #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
13843 | #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) |
| 13844 | #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) |
13844 | #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ |
| 13845 | #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ |
13845 | #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
| 13846 | #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
13846 | #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) |
| 13847 | #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) |
13847 | #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ |
| 13848 | #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ |
13848 | #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
| 13849 | #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
13849 | #define USB_OTG_DIEPMSK_TXFURM_Pos (8U) |
| 13850 | #define USB_OTG_DIEPMSK_TXFURM_Pos (8U) |
13850 | #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ |
| 13851 | #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ |
13851 | #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ |
| 13852 | #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ |
13852 | #define USB_OTG_DIEPMSK_BIM_Pos (9U) |
| 13853 | #define USB_OTG_DIEPMSK_BIM_Pos (9U) |
13853 | #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ |
| 13854 | #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ |
13854 | #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ |
| 13855 | #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ |
13855 | |
| 13856 | 13856 | /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ |
|
| 13857 | /******************** Bit definition for USB_OTG_HPTXSTS register ********************/ |
13857 | #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) |
| 13858 | #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) |
13858 | #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ |
| 13859 | #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ |
13859 | #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ |
| 13860 | #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ |
13860 | #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) |
| 13861 | #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) |
13861 | #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ |
| 13862 | #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ |
13862 | #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ |
| 13863 | #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ |
13863 | #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ |
| 13864 | #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ |
13864 | #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ |
| 13865 | #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ |
13865 | #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ |
| 13866 | #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ |
13866 | #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ |
| 13867 | #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ |
13867 | #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ |
| 13868 | #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ |
13868 | #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ |
| 13869 | #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ |
13869 | #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ |
| 13870 | #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ |
13870 | #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ |
| 13871 | #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ |
13871 | |
| 13872 | 13872 | #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) |
|
| 13873 | #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) |
13873 | #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ |
| 13874 | #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ |
13874 | #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ |
| 13875 | #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ |
13875 | #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ |
| 13876 | #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ |
13876 | #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ |
| 13877 | #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ |
13877 | #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ |
| 13878 | #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ |
13878 | #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ |
| 13879 | #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ |
13879 | #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ |
| 13880 | #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ |
13880 | #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ |
| 13881 | #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ |
13881 | #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ |
| 13882 | #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ |
13882 | #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ |
| 13883 | #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ |
13883 | |
| 13884 | 13884 | /******************** Bit definition for USB_OTG_HAINT register ********************/ |
|
| 13885 | /******************** Bit definition for USB_OTG_HAINT register ********************/ |
13885 | #define USB_OTG_HAINT_HAINT_Pos (0U) |
| 13886 | #define USB_OTG_HAINT_HAINT_Pos (0U) |
13886 | #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ |
| 13887 | #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ |
13887 | #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ |
| 13888 | #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ |
13888 | |
| 13889 | 13889 | /******************** Bit definition for USB_OTG_DOEPMSK register ********************/ |
|
| 13890 | /******************** Bit definition for USB_OTG_DOEPMSK register ********************/ |
13890 | #define USB_OTG_DOEPMSK_XFRCM_Pos (0U) |
| 13891 | #define USB_OTG_DOEPMSK_XFRCM_Pos (0U) |
13891 | #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ |
| 13892 | #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ |
13892 | #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| 13893 | #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
13893 | #define USB_OTG_DOEPMSK_EPDM_Pos (1U) |
| 13894 | #define USB_OTG_DOEPMSK_EPDM_Pos (1U) |
13894 | #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ |
| 13895 | #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ |
13895 | #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| 13896 | #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
13896 | #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) |
| 13897 | #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) |
13897 | #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ |
| 13898 | #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ |
13898 | #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ |
| 13899 | #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ |
13899 | #define USB_OTG_DOEPMSK_STUPM_Pos (3U) |
| 13900 | #define USB_OTG_DOEPMSK_STUPM_Pos (3U) |
13900 | #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ |
| 13901 | #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ |
13901 | #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ |
| 13902 | #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ |
13902 | #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) |
| 13903 | #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) |
13903 | #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ |
| 13904 | #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ |
13904 | #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ |
| 13905 | #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ |
13905 | #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) |
| 13906 | #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) |
13906 | #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ |
| 13907 | #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ |
13907 | #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ |
| 13908 | #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ |
13908 | #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) |
| 13909 | #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) |
13909 | #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ |
| 13910 | #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ |
13910 | #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ |
| 13911 | #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ |
13911 | #define USB_OTG_DOEPMSK_OPEM_Pos (8U) |
| 13912 | #define USB_OTG_DOEPMSK_OPEM_Pos (8U) |
13912 | #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ |
| 13913 | #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ |
13913 | #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ |
| 13914 | #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ |
13914 | #define USB_OTG_DOEPMSK_BOIM_Pos (9U) |
| 13915 | #define USB_OTG_DOEPMSK_BOIM_Pos (9U) |
13915 | #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ |
| 13916 | #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ |
13916 | #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ |
| 13917 | #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ |
13917 | #define USB_OTG_DOEPMSK_BERRM_Pos (12U) |
| 13918 | #define USB_OTG_DOEPMSK_BERRM_Pos (12U) |
13918 | #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ |
| 13919 | #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ |
13919 | #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ |
| 13920 | #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ |
13920 | #define USB_OTG_DOEPMSK_NAKM_Pos (13U) |
| 13921 | #define USB_OTG_DOEPMSK_NAKM_Pos (13U) |
13921 | #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ |
| 13922 | #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ |
13922 | #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ |
| 13923 | #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ |
13923 | #define USB_OTG_DOEPMSK_NYETM_Pos (14U) |
| 13924 | #define USB_OTG_DOEPMSK_NYETM_Pos (14U) |
13924 | #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ |
| 13925 | #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ |
13925 | #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ |
| 13926 | #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ |
13926 | /******************** Bit definition for USB_OTG_GINTSTS register ********************/ |
| 13927 | /******************** Bit definition for USB_OTG_GINTSTS register ********************/ |
13927 | #define USB_OTG_GINTSTS_CMOD_Pos (0U) |
| 13928 | #define USB_OTG_GINTSTS_CMOD_Pos (0U) |
13928 | #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ |
| 13929 | #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ |
13929 | #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ |
| 13930 | #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ |
13930 | #define USB_OTG_GINTSTS_MMIS_Pos (1U) |
| 13931 | #define USB_OTG_GINTSTS_MMIS_Pos (1U) |
13931 | #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ |
| 13932 | #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ |
13932 | #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ |
| 13933 | #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ |
13933 | #define USB_OTG_GINTSTS_OTGINT_Pos (2U) |
| 13934 | #define USB_OTG_GINTSTS_OTGINT_Pos (2U) |
13934 | #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ |
| 13935 | #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ |
13935 | #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ |
| 13936 | #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ |
13936 | #define USB_OTG_GINTSTS_SOF_Pos (3U) |
| 13937 | #define USB_OTG_GINTSTS_SOF_Pos (3U) |
13937 | #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ |
| 13938 | #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ |
13938 | #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ |
| 13939 | #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ |
13939 | #define USB_OTG_GINTSTS_RXFLVL_Pos (4U) |
| 13940 | #define USB_OTG_GINTSTS_RXFLVL_Pos (4U) |
13940 | #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ |
| 13941 | #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ |
13941 | #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ |
| 13942 | #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ |
13942 | #define USB_OTG_GINTSTS_NPTXFE_Pos (5U) |
| 13943 | #define USB_OTG_GINTSTS_NPTXFE_Pos (5U) |
13943 | #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ |
| 13944 | #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ |
13944 | #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ |
| 13945 | #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ |
13945 | #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) |
| 13946 | #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) |
13946 | #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ |
| 13947 | #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ |
13947 | #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ |
| 13948 | #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ |
13948 | #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) |
| 13949 | #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) |
13949 | #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ |
| 13950 | #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ |
13950 | #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ |
| 13951 | #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ |
13951 | #define USB_OTG_GINTSTS_ESUSP_Pos (10U) |
| 13952 | #define USB_OTG_GINTSTS_ESUSP_Pos (10U) |
13952 | #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ |
| 13953 | #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ |
13953 | #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ |
| 13954 | #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ |
13954 | #define USB_OTG_GINTSTS_USBSUSP_Pos (11U) |
| 13955 | #define USB_OTG_GINTSTS_USBSUSP_Pos (11U) |
13955 | #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ |
| 13956 | #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ |
13956 | #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ |
| 13957 | #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ |
13957 | #define USB_OTG_GINTSTS_USBRST_Pos (12U) |
| 13958 | #define USB_OTG_GINTSTS_USBRST_Pos (12U) |
13958 | #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ |
| 13959 | #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ |
13959 | #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ |
| 13960 | #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ |
13960 | #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) |
| 13961 | #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) |
13961 | #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ |
| 13962 | #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ |
13962 | #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ |
| 13963 | #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ |
13963 | #define USB_OTG_GINTSTS_ISOODRP_Pos (14U) |
| 13964 | #define USB_OTG_GINTSTS_ISOODRP_Pos (14U) |
13964 | #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ |
| 13965 | #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ |
13965 | #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ |
| 13966 | #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ |
13966 | #define USB_OTG_GINTSTS_EOPF_Pos (15U) |
| 13967 | #define USB_OTG_GINTSTS_EOPF_Pos (15U) |
13967 | #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ |
| 13968 | #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ |
13968 | #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ |
| 13969 | #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ |
13969 | #define USB_OTG_GINTSTS_IEPINT_Pos (18U) |
| 13970 | #define USB_OTG_GINTSTS_IEPINT_Pos (18U) |
13970 | #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ |
| 13971 | #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ |
13971 | #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ |
| 13972 | #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ |
13972 | #define USB_OTG_GINTSTS_OEPINT_Pos (19U) |
| 13973 | #define USB_OTG_GINTSTS_OEPINT_Pos (19U) |
13973 | #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ |
| 13974 | #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ |
13974 | #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ |
| 13975 | #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ |
13975 | #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) |
| 13976 | #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) |
13976 | #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ |
| 13977 | #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ |
13977 | #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ |
| 13978 | #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ |
13978 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) |
| 13979 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) |
13979 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ |
| 13980 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ |
13980 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ |
| 13981 | #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ |
13981 | #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) |
| 13982 | #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) |
13982 | #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ |
| 13983 | #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ |
13983 | #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ |
| 13984 | #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ |
13984 | #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) |
| 13985 | #define USB_OTG_GINTSTS_HPRTINT_Pos (24U) |
13985 | #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ |
| 13986 | #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ |
13986 | #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ |
| 13987 | #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ |
13987 | #define USB_OTG_GINTSTS_HCINT_Pos (25U) |
| 13988 | #define USB_OTG_GINTSTS_HCINT_Pos (25U) |
13988 | #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ |
| 13989 | #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ |
13989 | #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ |
| 13990 | #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ |
13990 | #define USB_OTG_GINTSTS_PTXFE_Pos (26U) |
| 13991 | #define USB_OTG_GINTSTS_PTXFE_Pos (26U) |
13991 | #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ |
| 13992 | #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ |
13992 | #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ |
| 13993 | #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ |
13993 | #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) |
| 13994 | #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) |
13994 | #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ |
| 13995 | #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ |
13995 | #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ |
| 13996 | #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ |
13996 | #define USB_OTG_GINTSTS_DISCINT_Pos (29U) |
| 13997 | #define USB_OTG_GINTSTS_DISCINT_Pos (29U) |
13997 | #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ |
| 13998 | #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ |
13998 | #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ |
| 13999 | #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ |
13999 | #define USB_OTG_GINTSTS_SRQINT_Pos (30U) |
| 14000 | #define USB_OTG_GINTSTS_SRQINT_Pos (30U) |
14000 | #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ |
| 14001 | #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ |
14001 | #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ |
| 14002 | #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ |
14002 | #define USB_OTG_GINTSTS_WKUINT_Pos (31U) |
| 14003 | #define USB_OTG_GINTSTS_WKUINT_Pos (31U) |
14003 | #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ |
| 14004 | #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ |
14004 | #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ |
| 14005 | #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ |
14005 | |
| 14006 | 14006 | /******************** Bit definition for USB_OTG_GINTMSK register ********************/ |
|
| 14007 | /******************** Bit definition for USB_OTG_GINTMSK register ********************/ |
14007 | #define USB_OTG_GINTMSK_MMISM_Pos (1U) |
| 14008 | #define USB_OTG_GINTMSK_MMISM_Pos (1U) |
14008 | #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ |
| 14009 | #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ |
14009 | #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ |
| 14010 | #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ |
14010 | #define USB_OTG_GINTMSK_OTGINT_Pos (2U) |
| 14011 | #define USB_OTG_GINTMSK_OTGINT_Pos (2U) |
14011 | #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ |
| 14012 | #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ |
14012 | #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ |
| 14013 | #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ |
14013 | #define USB_OTG_GINTMSK_SOFM_Pos (3U) |
| 14014 | #define USB_OTG_GINTMSK_SOFM_Pos (3U) |
14014 | #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ |
| 14015 | #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ |
14015 | #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ |
| 14016 | #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ |
14016 | #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) |
| 14017 | #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) |
14017 | #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ |
| 14018 | #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ |
14018 | #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ |
| 14019 | #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ |
14019 | #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) |
| 14020 | #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) |
14020 | #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ |
| 14021 | #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ |
14021 | #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ |
| 14022 | #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ |
14022 | #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) |
| 14023 | #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) |
14023 | #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ |
| 14024 | #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ |
14024 | #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ |
| 14025 | #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ |
14025 | #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) |
| 14026 | #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) |
14026 | #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ |
| 14027 | #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ |
14027 | #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ |
| 14028 | #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ |
14028 | #define USB_OTG_GINTMSK_ESUSPM_Pos (10U) |
| 14029 | #define USB_OTG_GINTMSK_ESUSPM_Pos (10U) |
14029 | #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ |
| 14030 | #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ |
14030 | #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ |
| 14031 | #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ |
14031 | #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) |
| 14032 | #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) |
14032 | #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ |
| 14033 | #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ |
14033 | #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ |
| 14034 | #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ |
14034 | #define USB_OTG_GINTMSK_USBRST_Pos (12U) |
| 14035 | #define USB_OTG_GINTMSK_USBRST_Pos (12U) |
14035 | #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ |
| 14036 | #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ |
14036 | #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ |
| 14037 | #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ |
14037 | #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) |
| 14038 | #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) |
14038 | #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ |
| 14039 | #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ |
14039 | #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ |
| 14040 | #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ |
14040 | #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) |
| 14041 | #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) |
14041 | #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ |
| 14042 | #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ |
14042 | #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ |
| 14043 | #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ |
14043 | #define USB_OTG_GINTMSK_EOPFM_Pos (15U) |
| 14044 | #define USB_OTG_GINTMSK_EOPFM_Pos (15U) |
14044 | #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ |
| 14045 | #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ |
14045 | #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ |
| 14046 | #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ |
14046 | #define USB_OTG_GINTMSK_EPMISM_Pos (17U) |
| 14047 | #define USB_OTG_GINTMSK_EPMISM_Pos (17U) |
14047 | #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ |
| 14048 | #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ |
14048 | #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ |
| 14049 | #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ |
14049 | #define USB_OTG_GINTMSK_IEPINT_Pos (18U) |
| 14050 | #define USB_OTG_GINTMSK_IEPINT_Pos (18U) |
14050 | #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ |
| 14051 | #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ |
14051 | #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ |
| 14052 | #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ |
14052 | #define USB_OTG_GINTMSK_OEPINT_Pos (19U) |
| 14053 | #define USB_OTG_GINTMSK_OEPINT_Pos (19U) |
14053 | #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ |
| 14054 | #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ |
14054 | #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ |
| 14055 | #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ |
14055 | #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) |
| 14056 | #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) |
14056 | #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ |
| 14057 | #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ |
14057 | #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ |
| 14058 | #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ |
14058 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) |
| 14059 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) |
14059 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ |
| 14060 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ |
14060 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ |
| 14061 | #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ |
14061 | #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) |
| 14062 | #define USB_OTG_GINTMSK_FSUSPM_Pos (22U) |
14062 | #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ |
| 14063 | #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ |
14063 | #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ |
| 14064 | #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ |
14064 | #define USB_OTG_GINTMSK_PRTIM_Pos (24U) |
| 14065 | #define USB_OTG_GINTMSK_PRTIM_Pos (24U) |
14065 | #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ |
| 14066 | #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ |
14066 | #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ |
| 14067 | #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ |
14067 | #define USB_OTG_GINTMSK_HCIM_Pos (25U) |
| 14068 | #define USB_OTG_GINTMSK_HCIM_Pos (25U) |
14068 | #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ |
| 14069 | #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ |
14069 | #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ |
| 14070 | #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ |
14070 | #define USB_OTG_GINTMSK_PTXFEM_Pos (26U) |
| 14071 | #define USB_OTG_GINTMSK_PTXFEM_Pos (26U) |
14071 | #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ |
| 14072 | #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ |
14072 | #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ |
| 14073 | #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ |
14073 | #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) |
| 14074 | #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) |
14074 | #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ |
| 14075 | #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ |
14075 | #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ |
| 14076 | #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ |
14076 | #define USB_OTG_GINTMSK_DISCINT_Pos (29U) |
| 14077 | #define USB_OTG_GINTMSK_DISCINT_Pos (29U) |
14077 | #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ |
| 14078 | #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ |
14078 | #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ |
| 14079 | #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ |
14079 | #define USB_OTG_GINTMSK_SRQIM_Pos (30U) |
| 14080 | #define USB_OTG_GINTMSK_SRQIM_Pos (30U) |
14080 | #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ |
| 14081 | #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ |
14081 | #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ |
| 14082 | #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ |
14082 | #define USB_OTG_GINTMSK_WUIM_Pos (31U) |
| 14083 | #define USB_OTG_GINTMSK_WUIM_Pos (31U) |
14083 | #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ |
| 14084 | #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ |
14084 | #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ |
| 14085 | #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ |
14085 | |
| 14086 | 14086 | /******************** Bit definition for USB_OTG_DAINT register ********************/ |
|
| 14087 | /******************** Bit definition for USB_OTG_DAINT register ********************/ |
14087 | #define USB_OTG_DAINT_IEPINT_Pos (0U) |
| 14088 | #define USB_OTG_DAINT_IEPINT_Pos (0U) |
14088 | #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ |
| 14089 | #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ |
14089 | #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ |
| 14090 | #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ |
14090 | #define USB_OTG_DAINT_OEPINT_Pos (16U) |
| 14091 | #define USB_OTG_DAINT_OEPINT_Pos (16U) |
14091 | #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ |
| 14092 | #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ |
14092 | #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ |
| 14093 | #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ |
14093 | |
| 14094 | 14094 | /******************** Bit definition for USB_OTG_HAINTMSK register ********************/ |
|
| 14095 | /******************** Bit definition for USB_OTG_HAINTMSK register ********************/ |
14095 | #define USB_OTG_HAINTMSK_HAINTM_Pos (0U) |
| 14096 | #define USB_OTG_HAINTMSK_HAINTM_Pos (0U) |
14096 | #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ |
| 14097 | #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ |
14097 | #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ |
| 14098 | #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ |
14098 | |
| 14099 | 14099 | /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ |
|
| 14100 | /******************** Bit definition for USB_OTG_GRXSTSP register ********************/ |
14100 | #define USB_OTG_GRXSTSP_EPNUM_Pos (0U) |
| 14101 | #define USB_OTG_GRXSTSP_EPNUM_Pos (0U) |
14101 | #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ |
| 14102 | #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ |
14102 | #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ |
| 14103 | #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ |
14103 | #define USB_OTG_GRXSTSP_BCNT_Pos (4U) |
| 14104 | #define USB_OTG_GRXSTSP_BCNT_Pos (4U) |
14104 | #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ |
| 14105 | #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ |
14105 | #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ |
| 14106 | #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ |
14106 | #define USB_OTG_GRXSTSP_DPID_Pos (15U) |
| 14107 | #define USB_OTG_GRXSTSP_DPID_Pos (15U) |
14107 | #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ |
| 14108 | #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ |
14108 | #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ |
| 14109 | #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ |
14109 | #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) |
| 14110 | #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) |
14110 | #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ |
| 14111 | #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ |
14111 | #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ |
| 14112 | #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ |
14112 | |
| 14113 | 14113 | /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ |
|
| 14114 | /******************** Bit definition for USB_OTG_DAINTMSK register ********************/ |
14114 | #define USB_OTG_DAINTMSK_IEPM_Pos (0U) |
| 14115 | #define USB_OTG_DAINTMSK_IEPM_Pos (0U) |
14115 | #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ |
| 14116 | #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ |
14116 | #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ |
| 14117 | #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ |
14117 | #define USB_OTG_DAINTMSK_OEPM_Pos (16U) |
| 14118 | #define USB_OTG_DAINTMSK_OEPM_Pos (16U) |
14118 | #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ |
| 14119 | #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ |
14119 | #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ |
| 14120 | #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ |
14120 | |
| 14121 | 14121 | /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ |
|
| 14122 | /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ |
14122 | #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) |
| 14123 | #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) |
14123 | #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ |
| 14124 | #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ |
14124 | #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ |
| 14125 | #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ |
14125 | |
| 14126 | 14126 | /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ |
|
| 14127 | /******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ |
14127 | #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) |
| 14128 | #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) |
14128 | #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ |
| 14129 | #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ |
14129 | #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ |
| 14130 | #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ |
14130 | |
| 14131 | 14131 | /******************** Bit definition for OTG register ********************/ |
|
| 14132 | /******************** Bit definition for OTG register ********************/ |
14132 | #define USB_OTG_NPTXFSA_Pos (0U) |
| 14133 | #define USB_OTG_NPTXFSA_Pos (0U) |
14133 | #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ |
| 14134 | #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ |
14134 | #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ |
| 14135 | #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ |
14135 | #define USB_OTG_NPTXFD_Pos (16U) |
| 14136 | #define USB_OTG_NPTXFD_Pos (16U) |
14136 | #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ |
| 14137 | #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ |
14137 | #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ |
| 14138 | #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ |
14138 | #define USB_OTG_TX0FSA_Pos (0U) |
| 14139 | #define USB_OTG_TX0FSA_Pos (0U) |
14139 | #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ |
| 14140 | #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ |
14140 | #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ |
| 14141 | #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ |
14141 | #define USB_OTG_TX0FD_Pos (16U) |
| 14142 | #define USB_OTG_TX0FD_Pos (16U) |
14142 | #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ |
| 14143 | #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ |
14143 | #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ |
| 14144 | #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ |
14144 | |
| 14145 | 14145 | /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ |
|
| 14146 | /******************** Bit definition for USB_OTG_DVBUSPULSE register ********************/ |
14146 | #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) |
| 14147 | #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) |
14147 | #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ |
| 14148 | #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ |
14148 | #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ |
| 14149 | #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ |
14149 | |
| 14150 | 14150 | /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ |
|
| 14151 | /******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ |
14151 | #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) |
| 14152 | #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) |
14152 | #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ |
| 14153 | #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ |
14153 | #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ |
| 14154 | #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ |
14154 | |
| 14155 | 14155 | #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) |
|
| 14156 | #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) |
14156 | #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ |
| 14157 | #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ |
14157 | #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ |
| 14158 | #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ |
14158 | #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ |
| 14159 | #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ |
14159 | #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ |
| 14160 | #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ |
14160 | #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ |
| 14161 | #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ |
14161 | #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ |
| 14162 | #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ |
14162 | #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ |
| 14163 | #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ |
14163 | #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ |
| 14164 | #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ |
14164 | #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ |
| 14165 | #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ |
14165 | #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ |
| 14166 | #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ |
14166 | |
| 14167 | 14167 | #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) |
|
| 14168 | #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) |
14168 | #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ |
| 14169 | #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ |
14169 | #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ |
| 14170 | #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ |
14170 | #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ |
| 14171 | #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ |
14171 | #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ |
| 14172 | #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ |
14172 | #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ |
| 14173 | #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ |
14173 | #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ |
| 14174 | #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ |
14174 | #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ |
| 14175 | #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ |
14175 | #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ |
| 14176 | #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ |
14176 | #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ |
| 14177 | #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ |
14177 | |
| 14178 | 14178 | /******************** Bit definition for USB_OTG_DTHRCTL register ********************/ |
|
| 14179 | /******************** Bit definition for USB_OTG_DTHRCTL register ********************/ |
14179 | #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) |
| 14180 | #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) |
14180 | #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ |
| 14181 | #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ |
14181 | #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ |
| 14182 | #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ |
14182 | #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) |
| 14183 | #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) |
14183 | #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ |
| 14184 | #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ |
14184 | #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ |
| 14185 | #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ |
14185 | |
| 14186 | 14186 | #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) |
|
| 14187 | #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) |
14187 | #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ |
| 14188 | #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ |
14188 | #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ |
| 14189 | #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ |
14189 | #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ |
| 14190 | #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ |
14190 | #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ |
| 14191 | #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ |
14191 | #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ |
| 14192 | #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ |
14192 | #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ |
| 14193 | #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ |
14193 | #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ |
| 14194 | #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ |
14194 | #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ |
| 14195 | #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ |
14195 | #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ |
| 14196 | #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ |
14196 | #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ |
| 14197 | #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ |
14197 | #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ |
| 14198 | #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ |
14198 | #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) |
| 14199 | #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) |
14199 | #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ |
| 14200 | #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ |
14200 | #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ |
| 14201 | #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ |
14201 | |
| 14202 | 14202 | #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) |
|
| 14203 | #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) |
14203 | #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ |
| 14204 | #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ |
14204 | #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ |
| 14205 | #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ |
14205 | #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ |
| 14206 | #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ |
14206 | #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ |
| 14207 | #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ |
14207 | #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ |
| 14208 | #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ |
14208 | #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ |
| 14209 | #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ |
14209 | #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ |
| 14210 | #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ |
14210 | #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ |
| 14211 | #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ |
14211 | #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ |
| 14212 | #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ |
14212 | #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ |
| 14213 | #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ |
14213 | #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ |
| 14214 | #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ |
14214 | #define USB_OTG_DTHRCTL_ARPEN_Pos (27U) |
| 14215 | #define USB_OTG_DTHRCTL_ARPEN_Pos (27U) |
14215 | #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ |
| 14216 | #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ |
14216 | #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ |
| 14217 | #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ |
14217 | |
| 14218 | 14218 | /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ |
|
| 14219 | /******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ |
14219 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) |
| 14220 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) |
14220 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ |
| 14221 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ |
14221 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ |
| 14222 | #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ |
14222 | |
| 14223 | 14223 | /******************** Bit definition for USB_OTG_DEACHINT register ********************/ |
|
| 14224 | /******************** Bit definition for USB_OTG_DEACHINT register ********************/ |
14224 | #define USB_OTG_DEACHINT_IEP1INT_Pos (1U) |
| 14225 | #define USB_OTG_DEACHINT_IEP1INT_Pos (1U) |
14225 | #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ |
| 14226 | #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ |
14226 | #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ |
| 14227 | #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ |
14227 | #define USB_OTG_DEACHINT_OEP1INT_Pos (17U) |
| 14228 | #define USB_OTG_DEACHINT_OEP1INT_Pos (17U) |
14228 | #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ |
| 14229 | #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ |
14229 | #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ |
| 14230 | #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ |
14230 | |
| 14231 | 14231 | /******************** Bit definition for USB_OTG_GCCFG register ********************/ |
|
| 14232 | /******************** Bit definition for USB_OTG_GCCFG register ********************/ |
14232 | #define USB_OTG_GCCFG_PWRDWN_Pos (16U) |
| 14233 | #define USB_OTG_GCCFG_PWRDWN_Pos (16U) |
14233 | #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ |
| 14234 | #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ |
14234 | #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ |
| 14235 | #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ |
14235 | #define USB_OTG_GCCFG_VBUSASEN_Pos (18U) |
| 14236 | #define USB_OTG_GCCFG_VBUSASEN_Pos (18U) |
14236 | #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ |
| 14237 | #define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ |
14237 | #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ |
| 14238 | #define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ |
14238 | #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) |
| 14239 | #define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) |
14239 | #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ |
| 14240 | #define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ |
14240 | #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ |
| 14241 | #define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ |
14241 | #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) |
| 14242 | #define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) |
14242 | #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ |
| 14243 | #define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ |
14243 | #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ |
| 14244 | #define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ |
14244 | |
| 14245 | 14245 | /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ |
|
| 14246 | /******************** Bit definition for USB_OTG_DEACHINTMSK register ********************/ |
14246 | #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) |
| 14247 | #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) |
14247 | #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ |
| 14248 | #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ |
14248 | #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ |
| 14249 | #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ |
14249 | #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) |
| 14250 | #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) |
14250 | #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ |
| 14251 | #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ |
14251 | #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ |
| 14252 | #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ |
14252 | |
| 14253 | 14253 | /******************** Bit definition for USB_OTG_CID register ********************/ |
|
| 14254 | /******************** Bit definition for USB_OTG_CID register ********************/ |
14254 | #define USB_OTG_CID_PRODUCT_ID_Pos (0U) |
| 14255 | #define USB_OTG_CID_PRODUCT_ID_Pos (0U) |
14255 | #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ |
| 14256 | #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ |
14256 | #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ |
| 14257 | #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ |
14257 | |
| 14258 | 14258 | /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ |
|
| 14259 | /******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ |
14259 | #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) |
| 14260 | #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) |
14260 | #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ |
| 14261 | #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ |
14261 | #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| 14262 | #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
14262 | #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) |
| 14263 | #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) |
14263 | #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ |
| 14264 | #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ |
14264 | #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| 14265 | #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
14265 | #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) |
| 14266 | #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) |
14266 | #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ |
| 14267 | #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ |
14267 | #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ |
| 14268 | #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ |
14268 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) |
| 14269 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) |
14269 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
| 14270 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
14270 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
| 14271 | #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
14271 | #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) |
| 14272 | #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) |
14272 | #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ |
| 14273 | #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ |
14273 | #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
| 14274 | #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
14274 | #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) |
| 14275 | #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) |
14275 | #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ |
| 14276 | #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ |
14276 | #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
| 14277 | #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
14277 | #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) |
| 14278 | #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) |
14278 | #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ |
| 14279 | #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ |
14279 | #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ |
| 14280 | #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ |
14280 | #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) |
| 14281 | #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) |
14281 | #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ |
| 14282 | #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ |
14282 | #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ |
| 14283 | #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ |
14283 | #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) |
| 14284 | #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) |
14284 | #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ |
| 14285 | #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ |
14285 | #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ |
| 14286 | #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ |
14286 | |
| 14287 | 14287 | /******************** Bit definition for USB_OTG_HPRT register ********************/ |
|
| 14288 | /******************** Bit definition for USB_OTG_HPRT register ********************/ |
14288 | #define USB_OTG_HPRT_PCSTS_Pos (0U) |
| 14289 | #define USB_OTG_HPRT_PCSTS_Pos (0U) |
14289 | #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ |
| 14290 | #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ |
14290 | #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ |
| 14291 | #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ |
14291 | #define USB_OTG_HPRT_PCDET_Pos (1U) |
| 14292 | #define USB_OTG_HPRT_PCDET_Pos (1U) |
14292 | #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ |
| 14293 | #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ |
14293 | #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ |
| 14294 | #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ |
14294 | #define USB_OTG_HPRT_PENA_Pos (2U) |
| 14295 | #define USB_OTG_HPRT_PENA_Pos (2U) |
14295 | #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ |
| 14296 | #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ |
14296 | #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ |
| 14297 | #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ |
14297 | #define USB_OTG_HPRT_PENCHNG_Pos (3U) |
| 14298 | #define USB_OTG_HPRT_PENCHNG_Pos (3U) |
14298 | #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ |
| 14299 | #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ |
14299 | #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ |
| 14300 | #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ |
14300 | #define USB_OTG_HPRT_POCA_Pos (4U) |
| 14301 | #define USB_OTG_HPRT_POCA_Pos (4U) |
14301 | #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ |
| 14302 | #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ |
14302 | #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ |
| 14303 | #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ |
14303 | #define USB_OTG_HPRT_POCCHNG_Pos (5U) |
| 14304 | #define USB_OTG_HPRT_POCCHNG_Pos (5U) |
14304 | #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ |
| 14305 | #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ |
14305 | #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ |
| 14306 | #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ |
14306 | #define USB_OTG_HPRT_PRES_Pos (6U) |
| 14307 | #define USB_OTG_HPRT_PRES_Pos (6U) |
14307 | #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ |
| 14308 | #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ |
14308 | #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ |
| 14309 | #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ |
14309 | #define USB_OTG_HPRT_PSUSP_Pos (7U) |
| 14310 | #define USB_OTG_HPRT_PSUSP_Pos (7U) |
14310 | #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ |
| 14311 | #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ |
14311 | #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ |
| 14312 | #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ |
14312 | #define USB_OTG_HPRT_PRST_Pos (8U) |
| 14313 | #define USB_OTG_HPRT_PRST_Pos (8U) |
14313 | #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ |
| 14314 | #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ |
14314 | #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ |
| 14315 | #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ |
14315 | |
| 14316 | 14316 | #define USB_OTG_HPRT_PLSTS_Pos (10U) |
|
| 14317 | #define USB_OTG_HPRT_PLSTS_Pos (10U) |
14317 | #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ |
| 14318 | #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ |
14318 | #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ |
| 14319 | #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ |
14319 | #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ |
| 14320 | #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ |
14320 | #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ |
| 14321 | #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ |
14321 | #define USB_OTG_HPRT_PPWR_Pos (12U) |
| 14322 | #define USB_OTG_HPRT_PPWR_Pos (12U) |
14322 | #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ |
| 14323 | #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ |
14323 | #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ |
| 14324 | #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ |
14324 | |
| 14325 | 14325 | #define USB_OTG_HPRT_PTCTL_Pos (13U) |
|
| 14326 | #define USB_OTG_HPRT_PTCTL_Pos (13U) |
14326 | #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ |
| 14327 | #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ |
14327 | #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ |
| 14328 | #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ |
14328 | #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ |
| 14329 | #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ |
14329 | #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ |
| 14330 | #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ |
14330 | #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ |
| 14331 | #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ |
14331 | #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ |
| 14332 | #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ |
14332 | |
| 14333 | 14333 | #define USB_OTG_HPRT_PSPD_Pos (17U) |
|
| 14334 | #define USB_OTG_HPRT_PSPD_Pos (17U) |
14334 | #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ |
| 14335 | #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ |
14335 | #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ |
| 14336 | #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ |
14336 | #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ |
| 14337 | #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ |
14337 | #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ |
| 14338 | #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ |
14338 | |
| 14339 | 14339 | /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ |
|
| 14340 | /******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ |
14340 | #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) |
| 14341 | #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) |
14341 | #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ |
| 14342 | #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ |
14342 | #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
| 14343 | #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ |
14343 | #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) |
| 14344 | #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) |
14344 | #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ |
| 14345 | #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ |
14345 | #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
| 14346 | #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ |
14346 | #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) |
| 14347 | #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) |
14347 | #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ |
| 14348 | #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ |
14348 | #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ |
| 14349 | #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ |
14349 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) |
| 14350 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) |
14350 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
| 14351 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ |
14351 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
| 14352 | #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ |
14352 | #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) |
| 14353 | #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) |
14353 | #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ |
| 14354 | #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ |
14354 | #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
| 14355 | #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ |
14355 | #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) |
| 14356 | #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) |
14356 | #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ |
| 14357 | #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ |
14357 | #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
| 14358 | #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ |
14358 | #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) |
| 14359 | #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) |
14359 | #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ |
| 14360 | #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ |
14360 | #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ |
| 14361 | #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ |
14361 | #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) |
| 14362 | #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) |
14362 | #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ |
| 14363 | #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ |
14363 | #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ |
| 14364 | #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ |
14364 | #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) |
| 14365 | #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) |
14365 | #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ |
| 14366 | #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ |
14366 | #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ |
| 14367 | #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ |
14367 | #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) |
| 14368 | #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) |
14368 | #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ |
| 14369 | #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ |
14369 | #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ |
| 14370 | #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ |
14370 | #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) |
| 14371 | #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) |
14371 | #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ |
| 14372 | #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ |
14372 | #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ |
| 14373 | #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ |
14373 | |
| 14374 | 14374 | /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ |
|
| 14375 | /******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ |
14375 | #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) |
| 14376 | #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) |
14376 | #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ |
| 14377 | #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ |
14377 | #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ |
| 14378 | #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ |
14378 | #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) |
| 14379 | #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) |
14379 | #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ |
| 14380 | #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ |
14380 | #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ |
| 14381 | #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ |
14381 | |
| 14382 | 14382 | /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ |
|
| 14383 | /******************** Bit definition for USB_OTG_DIEPCTL register ********************/ |
14383 | #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) |
| 14384 | #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) |
14384 | #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ |
| 14385 | #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ |
14385 | #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ |
| 14386 | #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ |
14386 | #define USB_OTG_DIEPCTL_USBAEP_Pos (15U) |
| 14387 | #define USB_OTG_DIEPCTL_USBAEP_Pos (15U) |
14387 | #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ |
| 14388 | #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ |
14388 | #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ |
| 14389 | #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ |
14389 | #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) |
| 14390 | #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) |
14390 | #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ |
| 14391 | #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ |
14391 | #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ |
| 14392 | #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ |
14392 | #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) |
| 14393 | #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) |
14393 | #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ |
| 14394 | #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ |
14394 | #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ |
| 14395 | #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ |
14395 | |
| 14396 | 14396 | #define USB_OTG_DIEPCTL_EPTYP_Pos (18U) |
|
| 14397 | #define USB_OTG_DIEPCTL_EPTYP_Pos (18U) |
14397 | #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ |
| 14398 | #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ |
14398 | #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ |
| 14399 | #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ |
14399 | #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ |
| 14400 | #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ |
14400 | #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ |
| 14401 | #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ |
14401 | #define USB_OTG_DIEPCTL_STALL_Pos (21U) |
| 14402 | #define USB_OTG_DIEPCTL_STALL_Pos (21U) |
14402 | #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ |
| 14403 | #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ |
14403 | #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ |
| 14404 | #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ |
14404 | |
| 14405 | 14405 | #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) |
|
| 14406 | #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) |
14406 | #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ |
| 14407 | #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ |
14407 | #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ |
| 14408 | #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ |
14408 | #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ |
| 14409 | #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ |
14409 | #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ |
| 14410 | #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ |
14410 | #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ |
| 14411 | #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ |
14411 | #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ |
| 14412 | #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ |
14412 | #define USB_OTG_DIEPCTL_CNAK_Pos (26U) |
| 14413 | #define USB_OTG_DIEPCTL_CNAK_Pos (26U) |
14413 | #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ |
| 14414 | #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ |
14414 | #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ |
| 14415 | #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ |
14415 | #define USB_OTG_DIEPCTL_SNAK_Pos (27U) |
| 14416 | #define USB_OTG_DIEPCTL_SNAK_Pos (27U) |
14416 | #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ |
| 14417 | #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ |
14417 | #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ |
| 14418 | #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ |
14418 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) |
| 14419 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) |
14419 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ |
| 14420 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ |
14420 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ |
| 14421 | #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ |
14421 | #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) |
| 14422 | #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) |
14422 | #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ |
| 14423 | #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ |
14423 | #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ |
| 14424 | #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ |
14424 | #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) |
| 14425 | #define USB_OTG_DIEPCTL_EPDIS_Pos (30U) |
14425 | #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ |
| 14426 | #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ |
14426 | #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ |
| 14427 | #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ |
14427 | #define USB_OTG_DIEPCTL_EPENA_Pos (31U) |
| 14428 | #define USB_OTG_DIEPCTL_EPENA_Pos (31U) |
14428 | #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ |
| 14429 | #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ |
14429 | #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ |
| 14430 | #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ |
14430 | |
| 14431 | 14431 | /******************** Bit definition for USB_OTG_HCCHAR register ********************/ |
|
| 14432 | /******************** Bit definition for USB_OTG_HCCHAR register ********************/ |
14432 | #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) |
| 14433 | #define USB_OTG_HCCHAR_MPSIZ_Pos (0U) |
14433 | #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ |
| 14434 | #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ |
14434 | #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ |
| 14435 | #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ |
14435 | |
| 14436 | 14436 | #define USB_OTG_HCCHAR_EPNUM_Pos (11U) |
|
| 14437 | #define USB_OTG_HCCHAR_EPNUM_Pos (11U) |
14437 | #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ |
| 14438 | #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ |
14438 | #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ |
| 14439 | #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ |
14439 | #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ |
| 14440 | #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ |
14440 | #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ |
| 14441 | #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ |
14441 | #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ |
| 14442 | #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ |
14442 | #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ |
| 14443 | #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ |
14443 | #define USB_OTG_HCCHAR_EPDIR_Pos (15U) |
| 14444 | #define USB_OTG_HCCHAR_EPDIR_Pos (15U) |
14444 | #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ |
| 14445 | #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ |
14445 | #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ |
| 14446 | #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ |
14446 | #define USB_OTG_HCCHAR_LSDEV_Pos (17U) |
| 14447 | #define USB_OTG_HCCHAR_LSDEV_Pos (17U) |
14447 | #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ |
| 14448 | #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ |
14448 | #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ |
| 14449 | #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ |
14449 | |
| 14450 | 14450 | #define USB_OTG_HCCHAR_EPTYP_Pos (18U) |
|
| 14451 | #define USB_OTG_HCCHAR_EPTYP_Pos (18U) |
14451 | #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ |
| 14452 | #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ |
14452 | #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ |
| 14453 | #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ |
14453 | #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ |
| 14454 | #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ |
14454 | #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ |
| 14455 | #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ |
14455 | |
| 14456 | 14456 | #define USB_OTG_HCCHAR_MC_Pos (20U) |
|
| 14457 | #define USB_OTG_HCCHAR_MC_Pos (20U) |
14457 | #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ |
| 14458 | #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ |
14458 | #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ |
| 14459 | #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ |
14459 | #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ |
| 14460 | #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ |
14460 | #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ |
| 14461 | #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ |
14461 | |
| 14462 | 14462 | #define USB_OTG_HCCHAR_DAD_Pos (22U) |
|
| 14463 | #define USB_OTG_HCCHAR_DAD_Pos (22U) |
14463 | #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ |
| 14464 | #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ |
14464 | #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ |
| 14465 | #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ |
14465 | #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ |
| 14466 | #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ |
14466 | #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ |
| 14467 | #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ |
14467 | #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ |
| 14468 | #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ |
14468 | #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ |
| 14469 | #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ |
14469 | #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ |
| 14470 | #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ |
14470 | #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ |
| 14471 | #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ |
14471 | #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ |
| 14472 | #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ |
14472 | #define USB_OTG_HCCHAR_ODDFRM_Pos (29U) |
| 14473 | #define USB_OTG_HCCHAR_ODDFRM_Pos (29U) |
14473 | #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ |
| 14474 | #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ |
14474 | #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ |
| 14475 | #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ |
14475 | #define USB_OTG_HCCHAR_CHDIS_Pos (30U) |
| 14476 | #define USB_OTG_HCCHAR_CHDIS_Pos (30U) |
14476 | #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ |
| 14477 | #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ |
14477 | #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ |
| 14478 | #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ |
14478 | #define USB_OTG_HCCHAR_CHENA_Pos (31U) |
| 14479 | #define USB_OTG_HCCHAR_CHENA_Pos (31U) |
14479 | #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ |
| 14480 | #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ |
14480 | #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ |
| 14481 | #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ |
14481 | |
| 14482 | 14482 | /******************** Bit definition for USB_OTG_HCSPLT register ********************/ |
|
| 14483 | /******************** Bit definition for USB_OTG_HCSPLT register ********************/ |
14483 | |
| 14484 | 14484 | #define USB_OTG_HCSPLT_PRTADDR_Pos (0U) |
|
| 14485 | #define USB_OTG_HCSPLT_PRTADDR_Pos (0U) |
14485 | #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ |
| 14486 | #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ |
14486 | #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ |
| 14487 | #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ |
14487 | #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ |
| 14488 | #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ |
14488 | #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ |
| 14489 | #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ |
14489 | #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ |
| 14490 | #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ |
14490 | #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ |
| 14491 | #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ |
14491 | #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ |
| 14492 | #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ |
14492 | #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ |
| 14493 | #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ |
14493 | #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ |
| 14494 | #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ |
14494 | |
| 14495 | 14495 | #define USB_OTG_HCSPLT_HUBADDR_Pos (7U) |
|
| 14496 | #define USB_OTG_HCSPLT_HUBADDR_Pos (7U) |
14496 | #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ |
| 14497 | #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ |
14497 | #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ |
| 14498 | #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ |
14498 | #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ |
| 14499 | #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ |
14499 | #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ |
| 14500 | #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ |
14500 | #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ |
| 14501 | #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ |
14501 | #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ |
| 14502 | #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ |
14502 | #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ |
| 14503 | #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ |
14503 | #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ |
| 14504 | #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ |
14504 | #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ |
| 14505 | #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ |
14505 | |
| 14506 | 14506 | #define USB_OTG_HCSPLT_XACTPOS_Pos (14U) |
|
| 14507 | #define USB_OTG_HCSPLT_XACTPOS_Pos (14U) |
14507 | #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ |
| 14508 | #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ |
14508 | #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ |
| 14509 | #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ |
14509 | #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ |
| 14510 | #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ |
14510 | #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ |
| 14511 | #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ |
14511 | #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) |
| 14512 | #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) |
14512 | #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ |
| 14513 | #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ |
14513 | #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ |
| 14514 | #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ |
14514 | #define USB_OTG_HCSPLT_SPLITEN_Pos (31U) |
| 14515 | #define USB_OTG_HCSPLT_SPLITEN_Pos (31U) |
14515 | #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ |
| 14516 | #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ |
14516 | #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ |
| 14517 | #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ |
14517 | |
| 14518 | 14518 | /******************** Bit definition for USB_OTG_HCINT register ********************/ |
|
| 14519 | /******************** Bit definition for USB_OTG_HCINT register ********************/ |
14519 | #define USB_OTG_HCINT_XFRC_Pos (0U) |
| 14520 | #define USB_OTG_HCINT_XFRC_Pos (0U) |
14520 | #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ |
| 14521 | #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ |
14521 | #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ |
| 14522 | #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ |
14522 | #define USB_OTG_HCINT_CHH_Pos (1U) |
| 14523 | #define USB_OTG_HCINT_CHH_Pos (1U) |
14523 | #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ |
| 14524 | #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ |
14524 | #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ |
| 14525 | #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ |
14525 | #define USB_OTG_HCINT_AHBERR_Pos (2U) |
| 14526 | #define USB_OTG_HCINT_AHBERR_Pos (2U) |
14526 | #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ |
| 14527 | #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ |
14527 | #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ |
| 14528 | #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ |
14528 | #define USB_OTG_HCINT_STALL_Pos (3U) |
| 14529 | #define USB_OTG_HCINT_STALL_Pos (3U) |
14529 | #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ |
| 14530 | #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ |
14530 | #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ |
| 14531 | #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ |
14531 | #define USB_OTG_HCINT_NAK_Pos (4U) |
| 14532 | #define USB_OTG_HCINT_NAK_Pos (4U) |
14532 | #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ |
| 14533 | #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ |
14533 | #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ |
| 14534 | #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ |
14534 | #define USB_OTG_HCINT_ACK_Pos (5U) |
| 14535 | #define USB_OTG_HCINT_ACK_Pos (5U) |
14535 | #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ |
| 14536 | #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ |
14536 | #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ |
| 14537 | #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ |
14537 | #define USB_OTG_HCINT_NYET_Pos (6U) |
| 14538 | #define USB_OTG_HCINT_NYET_Pos (6U) |
14538 | #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ |
| 14539 | #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ |
14539 | #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ |
| 14540 | #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ |
14540 | #define USB_OTG_HCINT_TXERR_Pos (7U) |
| 14541 | #define USB_OTG_HCINT_TXERR_Pos (7U) |
14541 | #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ |
| 14542 | #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ |
14542 | #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ |
| 14543 | #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ |
14543 | #define USB_OTG_HCINT_BBERR_Pos (8U) |
| 14544 | #define USB_OTG_HCINT_BBERR_Pos (8U) |
14544 | #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ |
| 14545 | #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ |
14545 | #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ |
| 14546 | #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ |
14546 | #define USB_OTG_HCINT_FRMOR_Pos (9U) |
| 14547 | #define USB_OTG_HCINT_FRMOR_Pos (9U) |
14547 | #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ |
| 14548 | #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ |
14548 | #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ |
| 14549 | #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ |
14549 | #define USB_OTG_HCINT_DTERR_Pos (10U) |
| 14550 | #define USB_OTG_HCINT_DTERR_Pos (10U) |
14550 | #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ |
| 14551 | #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ |
14551 | #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ |
| 14552 | #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ |
14552 | |
| 14553 | 14553 | /******************** Bit definition for USB_OTG_DIEPINT register ********************/ |
|
| 14554 | /******************** Bit definition for USB_OTG_DIEPINT register ********************/ |
14554 | #define USB_OTG_DIEPINT_XFRC_Pos (0U) |
| 14555 | #define USB_OTG_DIEPINT_XFRC_Pos (0U) |
14555 | #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ |
| 14556 | #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ |
14556 | #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ |
| 14557 | #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ |
14557 | #define USB_OTG_DIEPINT_EPDISD_Pos (1U) |
| 14558 | #define USB_OTG_DIEPINT_EPDISD_Pos (1U) |
14558 | #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ |
| 14559 | #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ |
14559 | #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ |
| 14560 | #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ |
14560 | #define USB_OTG_DIEPINT_AHBERR_Pos (2U) |
| 14561 | #define USB_OTG_DIEPINT_AHBERR_Pos (2U) |
14561 | #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ |
| 14562 | #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ |
14562 | #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ |
| 14563 | #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ |
14563 | #define USB_OTG_DIEPINT_TOC_Pos (3U) |
| 14564 | #define USB_OTG_DIEPINT_TOC_Pos (3U) |
14564 | #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ |
| 14565 | #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ |
14565 | #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ |
| 14566 | #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ |
14566 | #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) |
| 14567 | #define USB_OTG_DIEPINT_ITTXFE_Pos (4U) |
14567 | #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ |
| 14568 | #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ |
14568 | #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ |
| 14569 | #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ |
14569 | #define USB_OTG_DIEPINT_INEPNM_Pos (5U) |
| 14570 | #define USB_OTG_DIEPINT_INEPNM_Pos (5U) |
14570 | #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ |
| 14571 | #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ |
14571 | #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ |
| 14572 | #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ |
14572 | #define USB_OTG_DIEPINT_INEPNE_Pos (6U) |
| 14573 | #define USB_OTG_DIEPINT_INEPNE_Pos (6U) |
14573 | #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ |
| 14574 | #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ |
14574 | #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ |
| 14575 | #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ |
14575 | #define USB_OTG_DIEPINT_TXFE_Pos (7U) |
| 14576 | #define USB_OTG_DIEPINT_TXFE_Pos (7U) |
14576 | #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ |
| 14577 | #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ |
14577 | #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ |
| 14578 | #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ |
14578 | #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) |
| 14579 | #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) |
14579 | #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ |
| 14580 | #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ |
14580 | #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ |
| 14581 | #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ |
14581 | #define USB_OTG_DIEPINT_BNA_Pos (9U) |
| 14582 | #define USB_OTG_DIEPINT_BNA_Pos (9U) |
14582 | #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ |
| 14583 | #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ |
14583 | #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ |
| 14584 | #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ |
14584 | #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) |
| 14585 | #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) |
14585 | #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ |
| 14586 | #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ |
14586 | #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ |
| 14587 | #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ |
14587 | #define USB_OTG_DIEPINT_BERR_Pos (12U) |
| 14588 | #define USB_OTG_DIEPINT_BERR_Pos (12U) |
14588 | #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ |
| 14589 | #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ |
14589 | #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ |
| 14590 | #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ |
14590 | #define USB_OTG_DIEPINT_NAK_Pos (13U) |
| 14591 | #define USB_OTG_DIEPINT_NAK_Pos (13U) |
14591 | #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ |
| 14592 | #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ |
14592 | #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ |
| 14593 | #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ |
14593 | |
| 14594 | 14594 | /******************** Bit definition for USB_OTG_HCINTMSK register ********************/ |
|
| 14595 | /******************** Bit definition for USB_OTG_HCINTMSK register ********************/ |
14595 | #define USB_OTG_HCINTMSK_XFRCM_Pos (0U) |
| 14596 | #define USB_OTG_HCINTMSK_XFRCM_Pos (0U) |
14596 | #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ |
| 14597 | #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ |
14597 | #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ |
| 14598 | #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ |
14598 | #define USB_OTG_HCINTMSK_CHHM_Pos (1U) |
| 14599 | #define USB_OTG_HCINTMSK_CHHM_Pos (1U) |
14599 | #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ |
| 14600 | #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ |
14600 | #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ |
| 14601 | #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ |
14601 | #define USB_OTG_HCINTMSK_AHBERR_Pos (2U) |
| 14602 | #define USB_OTG_HCINTMSK_AHBERR_Pos (2U) |
14602 | #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ |
| 14603 | #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ |
14603 | #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ |
| 14604 | #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ |
14604 | #define USB_OTG_HCINTMSK_STALLM_Pos (3U) |
| 14605 | #define USB_OTG_HCINTMSK_STALLM_Pos (3U) |
14605 | #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ |
| 14606 | #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ |
14606 | #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ |
| 14607 | #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ |
14607 | #define USB_OTG_HCINTMSK_NAKM_Pos (4U) |
| 14608 | #define USB_OTG_HCINTMSK_NAKM_Pos (4U) |
14608 | #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ |
| 14609 | #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ |
14609 | #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ |
| 14610 | #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ |
14610 | #define USB_OTG_HCINTMSK_ACKM_Pos (5U) |
| 14611 | #define USB_OTG_HCINTMSK_ACKM_Pos (5U) |
14611 | #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ |
| 14612 | #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ |
14612 | #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ |
| 14613 | #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ |
14613 | #define USB_OTG_HCINTMSK_NYET_Pos (6U) |
| 14614 | #define USB_OTG_HCINTMSK_NYET_Pos (6U) |
14614 | #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ |
| 14615 | #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ |
14615 | #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ |
| 14616 | #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ |
14616 | #define USB_OTG_HCINTMSK_TXERRM_Pos (7U) |
| 14617 | #define USB_OTG_HCINTMSK_TXERRM_Pos (7U) |
14617 | #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ |
| 14618 | #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ |
14618 | #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ |
| 14619 | #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ |
14619 | #define USB_OTG_HCINTMSK_BBERRM_Pos (8U) |
| 14620 | #define USB_OTG_HCINTMSK_BBERRM_Pos (8U) |
14620 | #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ |
| 14621 | #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ |
14621 | #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ |
| 14622 | #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ |
14622 | #define USB_OTG_HCINTMSK_FRMORM_Pos (9U) |
| 14623 | #define USB_OTG_HCINTMSK_FRMORM_Pos (9U) |
14623 | #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ |
| 14624 | #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ |
14624 | #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ |
| 14625 | #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ |
14625 | #define USB_OTG_HCINTMSK_DTERRM_Pos (10U) |
| 14626 | #define USB_OTG_HCINTMSK_DTERRM_Pos (10U) |
14626 | #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ |
| 14627 | #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ |
14627 | #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ |
| 14628 | #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ |
14628 | |
| 14629 | 14629 | /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ |
|
| 14630 | /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ |
14630 | |
| 14631 | 14631 | #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) |
|
| 14632 | #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) |
14632 | #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
| 14633 | #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
14633 | #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
| 14634 | #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
14634 | #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) |
| 14635 | #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) |
14635 | #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
| 14636 | #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
14636 | #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ |
| 14637 | #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ |
14637 | #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) |
| 14638 | #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) |
14638 | #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ |
| 14639 | #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ |
14639 | #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ |
| 14640 | #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ |
14640 | /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ |
| 14641 | /******************** Bit definition for USB_OTG_HCTSIZ register ********************/ |
14641 | #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) |
| 14642 | #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) |
14642 | #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
| 14643 | #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
14643 | #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
| 14644 | #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
14644 | #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) |
| 14645 | #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) |
14645 | #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
| 14646 | #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
14646 | #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ |
| 14647 | #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ |
14647 | #define USB_OTG_HCTSIZ_DOPING_Pos (31U) |
| 14648 | #define USB_OTG_HCTSIZ_DOPING_Pos (31U) |
14648 | #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ |
| 14649 | #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ |
14649 | #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ |
| 14650 | #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ |
14650 | #define USB_OTG_HCTSIZ_DPID_Pos (29U) |
| 14651 | #define USB_OTG_HCTSIZ_DPID_Pos (29U) |
14651 | #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ |
| 14652 | #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ |
14652 | #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ |
| 14653 | #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ |
14653 | #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ |
| 14654 | #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ |
14654 | #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ |
| 14655 | #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ |
14655 | |
| 14656 | 14656 | /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ |
|
| 14657 | /******************** Bit definition for USB_OTG_DIEPDMA register ********************/ |
14657 | #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) |
| 14658 | #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) |
14658 | #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ |
| 14659 | #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ |
14659 | #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ |
| 14660 | #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ |
14660 | |
| 14661 | 14661 | /******************** Bit definition for USB_OTG_HCDMA register ********************/ |
|
| 14662 | /******************** Bit definition for USB_OTG_HCDMA register ********************/ |
14662 | #define USB_OTG_HCDMA_DMAADDR_Pos (0U) |
| 14663 | #define USB_OTG_HCDMA_DMAADDR_Pos (0U) |
14663 | #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ |
| 14664 | #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ |
14664 | #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ |
| 14665 | #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ |
14665 | |
| 14666 | 14666 | /******************** Bit definition for USB_OTG_DTXFSTS register ********************/ |
|
| 14667 | /******************** Bit definition for USB_OTG_DTXFSTS register ********************/ |
14667 | #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) |
| 14668 | #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) |
14668 | #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ |
| 14669 | #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ |
14669 | #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ |
| 14670 | #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ |
14670 | |
| 14671 | 14671 | /******************** Bit definition for USB_OTG_DIEPTXF register ********************/ |
|
| 14672 | /******************** Bit definition for USB_OTG_DIEPTXF register ********************/ |
14672 | #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) |
| 14673 | #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) |
14673 | #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ |
| 14674 | #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ |
14674 | #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ |
| 14675 | #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ |
14675 | #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) |
| 14676 | #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) |
14676 | #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ |
| 14677 | #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ |
14677 | #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ |
| 14678 | #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ |
14678 | |
| 14679 | 14679 | /******************** Bit definition for USB_OTG_DOEPCTL register ********************/ |
|
| 14680 | /******************** Bit definition for USB_OTG_DOEPCTL register ********************/ |
14680 | |
| 14681 | 14681 | #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) |
|
| 14682 | #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) |
14682 | #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ |
| 14683 | #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ |
14683 | #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */ |
| 14684 | #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */ |
14684 | #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) |
| 14685 | #define USB_OTG_DOEPCTL_USBAEP_Pos (15U) |
14685 | #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ |
| 14686 | #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */ |
14686 | #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ |
| 14687 | #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */ |
14687 | #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) |
| 14688 | #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U) |
14688 | #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ |
| 14689 | #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ |
14689 | #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ |
| 14690 | #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */ |
14690 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) |
| 14691 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U) |
14691 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ |
| 14692 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ |
14692 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ |
| 14693 | #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ |
14693 | #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) |
| 14694 | #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U) |
14694 | #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ |
| 14695 | #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ |
14695 | #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ |
| 14696 | #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */ |
14696 | #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) |
| 14697 | #define USB_OTG_DOEPCTL_EPTYP_Pos (18U) |
14697 | #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ |
| 14698 | #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ |
14698 | #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ |
| 14699 | #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */ |
14699 | #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */ |
| 14700 | #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */ |
14700 | #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */ |
| 14701 | #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */ |
14701 | #define USB_OTG_DOEPCTL_SNPM_Pos (20U) |
| 14702 | #define USB_OTG_DOEPCTL_SNPM_Pos (20U) |
14702 | #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */ |
| 14703 | #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */ |
14703 | #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */ |
| 14704 | #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */ |
14704 | #define USB_OTG_DOEPCTL_STALL_Pos (21U) |
| 14705 | #define USB_OTG_DOEPCTL_STALL_Pos (21U) |
14705 | #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */ |
| 14706 | #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */ |
14706 | #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */ |
| 14707 | #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */ |
14707 | #define USB_OTG_DOEPCTL_CNAK_Pos (26U) |
| 14708 | #define USB_OTG_DOEPCTL_CNAK_Pos (26U) |
14708 | #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */ |
| 14709 | #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */ |
14709 | #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */ |
| 14710 | #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */ |
14710 | #define USB_OTG_DOEPCTL_SNAK_Pos (27U) |
| 14711 | #define USB_OTG_DOEPCTL_SNAK_Pos (27U) |
14711 | #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ |
| 14712 | #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */ |
14712 | #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ |
| 14713 | #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */ |
14713 | #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) |
| 14714 | #define USB_OTG_DOEPCTL_EPDIS_Pos (30U) |
14714 | #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ |
| 14715 | #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */ |
14715 | #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ |
| 14716 | #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */ |
14716 | #define USB_OTG_DOEPCTL_EPENA_Pos (31U) |
| 14717 | #define USB_OTG_DOEPCTL_EPENA_Pos (31U) |
14717 | #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */ |
| 14718 | #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */ |
14718 | #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */ |
| 14719 | #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */ |
14719 | |
| 14720 | 14720 | /******************** Bit definition for USB_OTG_DOEPINT register ********************/ |
|
| 14721 | /******************** Bit definition for USB_OTG_DOEPINT register ********************/ |
14721 | #define USB_OTG_DOEPINT_XFRC_Pos (0U) |
| 14722 | #define USB_OTG_DOEPINT_XFRC_Pos (0U) |
14722 | #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */ |
| 14723 | #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */ |
14723 | #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */ |
| 14724 | #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */ |
14724 | #define USB_OTG_DOEPINT_EPDISD_Pos (1U) |
| 14725 | #define USB_OTG_DOEPINT_EPDISD_Pos (1U) |
14725 | #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ |
| 14726 | #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */ |
14726 | #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ |
| 14727 | #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ |
14727 | #define USB_OTG_DOEPINT_AHBERR_Pos (2U) |
| 14728 | #define USB_OTG_DOEPINT_AHBERR_Pos (2U) |
14728 | #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ |
| 14729 | #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */ |
14729 | #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */ |
| 14730 | #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */ |
14730 | #define USB_OTG_DOEPINT_STUP_Pos (3U) |
| 14731 | #define USB_OTG_DOEPINT_STUP_Pos (3U) |
14731 | #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ |
| 14732 | #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */ |
14732 | #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ |
| 14733 | #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */ |
14733 | #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) |
| 14734 | #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U) |
14734 | #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ |
| 14735 | #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */ |
14735 | #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ |
| 14736 | #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */ |
14736 | #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U) |
| 14737 | #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U) |
14737 | #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */ |
| 14738 | #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */ |
14738 | #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */ |
| 14739 | #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< Status Phase Received For Control Write */ |
14739 | #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) |
| 14740 | #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U) |
14740 | #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ |
| 14741 | #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */ |
14741 | #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ |
| 14742 | #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */ |
14742 | #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) |
| 14743 | #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U) |
14743 | #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ |
| 14744 | #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */ |
14744 | #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ |
| 14745 | #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */ |
14745 | #define USB_OTG_DOEPINT_NAK_Pos (13U) |
| 14746 | #define USB_OTG_DOEPINT_NAK_Pos (13U) |
14746 | #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ |
| 14747 | #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */ |
14747 | #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */ |
| 14748 | #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */ |
14748 | #define USB_OTG_DOEPINT_NYET_Pos (14U) |
| 14749 | #define USB_OTG_DOEPINT_NYET_Pos (14U) |
14749 | #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ |
| 14750 | #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */ |
14750 | #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ |
| 14751 | #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */ |
14751 | #define USB_OTG_DOEPINT_STPKTRX_Pos (15U) |
| 14752 | #define USB_OTG_DOEPINT_STPKTRX_Pos (15U) |
14752 | #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ |
| 14753 | #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */ |
14753 | #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */ |
| 14754 | #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */ |
14754 | /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ |
| 14755 | /******************** Bit definition for USB_OTG_DOEPTSIZ register ********************/ |
14755 | |
| 14756 | 14756 | #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) |
|
| 14757 | #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U) |
14757 | #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
| 14758 | #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ |
14758 | #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
| 14759 | #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ |
14759 | #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) |
| 14760 | #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U) |
14760 | #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
| 14761 | #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ |
14761 | #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ |
| 14762 | #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */ |
14762 | |
| 14763 | 14763 | #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) |
|
| 14764 | #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U) |
14764 | #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ |
| 14765 | #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */ |
14765 | #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ |
| 14766 | #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */ |
14766 | #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ |
| 14767 | #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */ |
14767 | #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ |
| 14768 | #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */ |
14768 | |
| 14769 | 14769 | /******************** Bit definition for PCGCCTL register ********************/ |
|
| 14770 | /******************** Bit definition for PCGCCTL register ********************/ |
14770 | #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) |
| 14771 | #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U) |
14771 | #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ |
| 14772 | #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */ |
14772 | #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ |
| 14773 | #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */ |
14773 | #define USB_OTG_PCGCCTL_GATECLK_Pos (1U) |
| 14774 | #define USB_OTG_PCGCCTL_GATECLK_Pos (1U) |
14774 | #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ |
| 14775 | #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */ |
14775 | #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */ |
| 14776 | #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */ |
14776 | #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) |
| 14777 | #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U) |
14777 | #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ |
| 14778 | #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ |
14778 | #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ |
| 14779 | #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ |
14779 | |
| 14780 | 14780 | /* Legacy define */ |
|
| 14781 | /* Legacy define */ |
14781 | /******************** Bit definition for OTG register ********************/ |
| 14782 | /******************** Bit definition for OTG register ********************/ |
14782 | #define USB_OTG_CHNUM_Pos (0U) |
| 14783 | #define USB_OTG_CHNUM_Pos (0U) |
14783 | #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ |
| 14784 | #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ |
14784 | #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ |
| 14785 | #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ |
14785 | #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ |
| 14786 | #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ |
14786 | #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ |
| 14787 | #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ |
14787 | #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ |
| 14788 | #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ |
14788 | #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ |
| 14789 | #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ |
14789 | #define USB_OTG_BCNT_Pos (4U) |
| 14790 | #define USB_OTG_BCNT_Pos (4U) |
14790 | #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ |
| 14791 | #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ |
14791 | #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ |
| 14792 | #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ |
14792 | |
| 14793 | 14793 | #define USB_OTG_DPID_Pos (15U) |
|
| 14794 | #define USB_OTG_DPID_Pos (15U) |
14794 | #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */ |
| 14795 | #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */ |
14795 | #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ |
| 14796 | #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ |
14796 | #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */ |
| 14797 | #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */ |
14797 | #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */ |
| 14798 | #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */ |
14798 | |
| 14799 | 14799 | #define USB_OTG_PKTSTS_Pos (17U) |
|
| 14800 | #define USB_OTG_PKTSTS_Pos (17U) |
14800 | #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ |
| 14801 | #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ |
14801 | #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ |
| 14802 | #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ |
14802 | #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ |
| 14803 | #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ |
14803 | #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ |
| 14804 | #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ |
14804 | #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ |
| 14805 | #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ |
14805 | #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ |
| 14806 | #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ |
14806 | |
| 14807 | 14807 | #define USB_OTG_EPNUM_Pos (0U) |
|
| 14808 | #define USB_OTG_EPNUM_Pos (0U) |
14808 | #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ |
| 14809 | #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ |
14809 | #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ |
| 14810 | #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ |
14810 | #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ |
| 14811 | #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ |
14811 | #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ |
| 14812 | #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ |
14812 | #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ |
| 14813 | #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ |
14813 | #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ |
| 14814 | #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ |
14814 | |
| 14815 | 14815 | #define USB_OTG_FRMNUM_Pos (21U) |
|
| 14816 | #define USB_OTG_FRMNUM_Pos (21U) |
14816 | #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ |
| 14817 | #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ |
14817 | #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ |
| 14818 | #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ |
14818 | #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ |
| 14819 | #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ |
14819 | #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ |
| 14820 | #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ |
14820 | #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ |
| 14821 | #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ |
14821 | #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ |
| 14822 | #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ |
14822 | |
| 14823 | 14823 | /** |
|
| 14824 | /** |
14824 | * @} |
| 14825 | * @} |
14825 | */ |
| 14826 | */ |
14826 | |
| 14827 | 14827 | /** |
|
| 14828 | /** |
14828 | * @} |
| 14829 | * @} |
14829 | */ |
| 14830 | */ |
14830 | |
| 14831 | 14831 | /** @addtogroup Exported_macro |
|
| 14832 | /** @addtogroup Exported_macro |
14832 | * @{ |
| 14833 | * @{ |
14833 | */ |
| 14834 | */ |
14834 | |
| 14835 | 14835 | /****************************** ADC Instances *********************************/ |
|
| 14836 | /****************************** ADC Instances *********************************/ |
14836 | #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ |
| 14837 | #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \ |
14837 | ((INSTANCE) == ADC2)) |
| 14838 | ((INSTANCE) == ADC2)) |
14838 | |
| 14839 | 14839 | #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) |
|
| 14840 | #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON) |
14840 | |
| 14841 | 14841 | #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
|
| 14842 | #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
14842 | |
| 14843 | 14843 | #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
|
| 14844 | #define IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) |
14844 | |
| 14845 | 14845 | /****************************** CAN Instances *********************************/ |
|
| 14846 | /****************************** CAN Instances *********************************/ |
14846 | #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \ |
| 14847 | #define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \ |
14847 | ((INSTANCE) == CAN2)) |
| 14848 | ((INSTANCE) == CAN2)) |
14848 | |
| 14849 | 14849 | /****************************** CRC Instances *********************************/ |
|
| 14850 | /****************************** CRC Instances *********************************/ |
14850 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
| 14851 | #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC) |
14851 | |
| 14852 | 14852 | /****************************** DAC Instances *********************************/ |
|
| 14853 | /****************************** DAC Instances *********************************/ |
14853 | #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
| 14854 | #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1) |
14854 | |
| 14855 | 14855 | /****************************** DMA Instances *********************************/ |
|
| 14856 | /****************************** DMA Instances *********************************/ |
14856 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
| 14857 | #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \ |
14857 | ((INSTANCE) == DMA1_Channel2) || \ |
| 14858 | ((INSTANCE) == DMA1_Channel2) || \ |
14858 | ((INSTANCE) == DMA1_Channel3) || \ |
| 14859 | ((INSTANCE) == DMA1_Channel3) || \ |
14859 | ((INSTANCE) == DMA1_Channel4) || \ |
| 14860 | ((INSTANCE) == DMA1_Channel4) || \ |
14860 | ((INSTANCE) == DMA1_Channel5) || \ |
| 14861 | ((INSTANCE) == DMA1_Channel5) || \ |
14861 | ((INSTANCE) == DMA1_Channel6) || \ |
| 14862 | ((INSTANCE) == DMA1_Channel6) || \ |
14862 | ((INSTANCE) == DMA1_Channel7) || \ |
| 14863 | ((INSTANCE) == DMA1_Channel7) || \ |
14863 | ((INSTANCE) == DMA2_Channel1) || \ |
| 14864 | ((INSTANCE) == DMA2_Channel1) || \ |
14864 | ((INSTANCE) == DMA2_Channel2) || \ |
| 14865 | ((INSTANCE) == DMA2_Channel2) || \ |
14865 | ((INSTANCE) == DMA2_Channel3) || \ |
| 14866 | ((INSTANCE) == DMA2_Channel3) || \ |
14866 | ((INSTANCE) == DMA2_Channel4) || \ |
| 14867 | ((INSTANCE) == DMA2_Channel4) || \ |
14867 | ((INSTANCE) == DMA2_Channel5)) |
| 14868 | ((INSTANCE) == DMA2_Channel5)) |
14868 | |
| 14869 | 14869 | /******************************* GPIO Instances *******************************/ |
|
| 14870 | /******************************* GPIO Instances *******************************/ |
14870 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
| 14871 | #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \ |
14871 | ((INSTANCE) == GPIOB) || \ |
| 14872 | ((INSTANCE) == GPIOB) || \ |
14872 | ((INSTANCE) == GPIOC) || \ |
| 14873 | ((INSTANCE) == GPIOC) || \ |
14873 | ((INSTANCE) == GPIOD) || \ |
| 14874 | ((INSTANCE) == GPIOD) || \ |
14874 | ((INSTANCE) == GPIOE)) |
| 14875 | ((INSTANCE) == GPIOE)) |
14875 | |
| 14876 | 14876 | /**************************** GPIO Alternate Function Instances ***************/ |
|
| 14877 | /**************************** GPIO Alternate Function Instances ***************/ |
14877 | #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| 14878 | #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
14878 | |
| 14879 | 14879 | /**************************** GPIO Lock Instances *****************************/ |
|
| 14880 | /**************************** GPIO Lock Instances *****************************/ |
14880 | #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
| 14881 | #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) |
14881 | |
| 14882 | 14882 | /******************************** I2C Instances *******************************/ |
|
| 14883 | /******************************** I2C Instances *******************************/ |
14883 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
| 14884 | #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \ |
14884 | ((INSTANCE) == I2C2)) |
| 14885 | ((INSTANCE) == I2C2)) |
14885 | |
| 14886 | 14886 | /******************************* SMBUS Instances ******************************/ |
|
| 14887 | /******************************* SMBUS Instances ******************************/ |
14887 | #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE |
| 14888 | #define IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE |
14888 | |
| 14889 | 14889 | /******************************** I2S Instances *******************************/ |
|
| 14890 | /******************************** I2S Instances *******************************/ |
14890 | #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ |
| 14891 | #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI2) || \ |
14891 | ((INSTANCE) == SPI3)) |
| 14892 | ((INSTANCE) == SPI3)) |
14892 | |
| 14893 | 14893 | /****************************** IWDG Instances ********************************/ |
|
| 14894 | /****************************** IWDG Instances ********************************/ |
14894 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
| 14895 | #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG) |
14895 | |
| 14896 | 14896 | /******************************** SPI Instances *******************************/ |
|
| 14897 | /******************************** SPI Instances *******************************/ |
14897 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
| 14898 | #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ |
14898 | ((INSTANCE) == SPI2) || \ |
| 14899 | ((INSTANCE) == SPI2) || \ |
14899 | ((INSTANCE) == SPI3)) |
| 14900 | ((INSTANCE) == SPI3)) |
14900 | |
| 14901 | 14901 | /****************************** START TIM Instances ***************************/ |
|
| 14902 | /****************************** START TIM Instances ***************************/ |
14902 | /****************************** TIM Instances *********************************/ |
| 14903 | /****************************** TIM Instances *********************************/ |
14903 | #define IS_TIM_INSTANCE(INSTANCE)\ |
| 14904 | #define IS_TIM_INSTANCE(INSTANCE)\ |
14904 | (((INSTANCE) == TIM1) || \ |
| 14905 | (((INSTANCE) == TIM1) || \ |
14905 | ((INSTANCE) == TIM2) || \ |
| 14906 | ((INSTANCE) == TIM2) || \ |
14906 | ((INSTANCE) == TIM3) || \ |
| 14907 | ((INSTANCE) == TIM3) || \ |
14907 | ((INSTANCE) == TIM4) || \ |
| 14908 | ((INSTANCE) == TIM4) || \ |
14908 | ((INSTANCE) == TIM5) || \ |
| 14909 | ((INSTANCE) == TIM5) || \ |
14909 | ((INSTANCE) == TIM6) || \ |
| 14910 | ((INSTANCE) == TIM6) || \ |
14910 | ((INSTANCE) == TIM7)) |
| 14911 | ((INSTANCE) == TIM7)) |
14911 | |
| 14912 | 14912 | #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) |
|
| 14913 | #define IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) |
14913 | |
| 14914 | 14914 | #define IS_TIM_CC1_INSTANCE(INSTANCE)\ |
|
| 14915 | #define IS_TIM_CC1_INSTANCE(INSTANCE)\ |
14915 | (((INSTANCE) == TIM1) || \ |
| 14916 | (((INSTANCE) == TIM1) || \ |
14916 | ((INSTANCE) == TIM2) || \ |
| 14917 | ((INSTANCE) == TIM2) || \ |
14917 | ((INSTANCE) == TIM3) || \ |
| 14918 | ((INSTANCE) == TIM3) || \ |
14918 | ((INSTANCE) == TIM4) || \ |
| 14919 | ((INSTANCE) == TIM4) || \ |
14919 | ((INSTANCE) == TIM5)) |
| 14920 | ((INSTANCE) == TIM5)) |
14920 | |
| 14921 | 14921 | #define IS_TIM_CC2_INSTANCE(INSTANCE)\ |
|
| 14922 | #define IS_TIM_CC2_INSTANCE(INSTANCE)\ |
14922 | (((INSTANCE) == TIM1) || \ |
| 14923 | (((INSTANCE) == TIM1) || \ |
14923 | ((INSTANCE) == TIM2) || \ |
| 14924 | ((INSTANCE) == TIM2) || \ |
14924 | ((INSTANCE) == TIM3) || \ |
| 14925 | ((INSTANCE) == TIM3) || \ |
14925 | ((INSTANCE) == TIM4) || \ |
| 14926 | ((INSTANCE) == TIM4) || \ |
14926 | ((INSTANCE) == TIM5)) |
| 14927 | ((INSTANCE) == TIM5)) |
14927 | |
| 14928 | 14928 | #define IS_TIM_CC3_INSTANCE(INSTANCE)\ |
|
| 14929 | #define IS_TIM_CC3_INSTANCE(INSTANCE)\ |
14929 | (((INSTANCE) == TIM1) || \ |
| 14930 | (((INSTANCE) == TIM1) || \ |
14930 | ((INSTANCE) == TIM2) || \ |
| 14931 | ((INSTANCE) == TIM2) || \ |
14931 | ((INSTANCE) == TIM3) || \ |
| 14932 | ((INSTANCE) == TIM3) || \ |
14932 | ((INSTANCE) == TIM4) || \ |
| 14933 | ((INSTANCE) == TIM4) || \ |
14933 | ((INSTANCE) == TIM5)) |
| 14934 | ((INSTANCE) == TIM5)) |
14934 | |
| 14935 | 14935 | #define IS_TIM_CC4_INSTANCE(INSTANCE)\ |
|
| 14936 | #define IS_TIM_CC4_INSTANCE(INSTANCE)\ |
14936 | (((INSTANCE) == TIM1) || \ |
| 14937 | (((INSTANCE) == TIM1) || \ |
14937 | ((INSTANCE) == TIM2) || \ |
| 14938 | ((INSTANCE) == TIM2) || \ |
14938 | ((INSTANCE) == TIM3) || \ |
| 14939 | ((INSTANCE) == TIM3) || \ |
14939 | ((INSTANCE) == TIM4) || \ |
| 14940 | ((INSTANCE) == TIM4) || \ |
14940 | ((INSTANCE) == TIM5)) |
| 14941 | ((INSTANCE) == TIM5)) |
14941 | |
| 14942 | 14942 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ |
|
| 14943 | #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\ |
14943 | (((INSTANCE) == TIM1) || \ |
| 14944 | (((INSTANCE) == TIM1) || \ |
14944 | ((INSTANCE) == TIM2) || \ |
| 14945 | ((INSTANCE) == TIM2) || \ |
14945 | ((INSTANCE) == TIM3) || \ |
| 14946 | ((INSTANCE) == TIM3) || \ |
14946 | ((INSTANCE) == TIM4) || \ |
| 14947 | ((INSTANCE) == TIM4) || \ |
14947 | ((INSTANCE) == TIM5)) |
| 14948 | ((INSTANCE) == TIM5)) |
14948 | |
| 14949 | 14949 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ |
|
| 14950 | #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\ |
14950 | (((INSTANCE) == TIM1) || \ |
| 14951 | (((INSTANCE) == TIM1) || \ |
14951 | ((INSTANCE) == TIM2) || \ |
| 14952 | ((INSTANCE) == TIM2) || \ |
14952 | ((INSTANCE) == TIM3) || \ |
| 14953 | ((INSTANCE) == TIM3) || \ |
14953 | ((INSTANCE) == TIM4) || \ |
| 14954 | ((INSTANCE) == TIM4) || \ |
14954 | ((INSTANCE) == TIM5)) |
| 14955 | ((INSTANCE) == TIM5)) |
14955 | |
| 14956 | 14956 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ |
|
| 14957 | #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\ |
14957 | (((INSTANCE) == TIM1) || \ |
| 14958 | (((INSTANCE) == TIM1) || \ |
14958 | ((INSTANCE) == TIM2) || \ |
| 14959 | ((INSTANCE) == TIM2) || \ |
14959 | ((INSTANCE) == TIM3) || \ |
| 14960 | ((INSTANCE) == TIM3) || \ |
14960 | ((INSTANCE) == TIM4) || \ |
| 14961 | ((INSTANCE) == TIM4) || \ |
14961 | ((INSTANCE) == TIM5)) |
| 14962 | ((INSTANCE) == TIM5)) |
14962 | |
| 14963 | 14963 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ |
|
| 14964 | #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\ |
14964 | (((INSTANCE) == TIM1) || \ |
| 14965 | (((INSTANCE) == TIM1) || \ |
14965 | ((INSTANCE) == TIM2) || \ |
| 14966 | ((INSTANCE) == TIM2) || \ |
14966 | ((INSTANCE) == TIM3) || \ |
| 14967 | ((INSTANCE) == TIM3) || \ |
14967 | ((INSTANCE) == TIM4) || \ |
| 14968 | ((INSTANCE) == TIM4) || \ |
14968 | ((INSTANCE) == TIM5)) |
| 14969 | ((INSTANCE) == TIM5)) |
14969 | |
| 14970 | 14970 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ |
|
| 14971 | #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\ |
14971 | (((INSTANCE) == TIM1) || \ |
| 14972 | (((INSTANCE) == TIM1) || \ |
14972 | ((INSTANCE) == TIM2) || \ |
| 14973 | ((INSTANCE) == TIM2) || \ |
14973 | ((INSTANCE) == TIM3) || \ |
| 14974 | ((INSTANCE) == TIM3) || \ |
14974 | ((INSTANCE) == TIM4) || \ |
| 14975 | ((INSTANCE) == TIM4) || \ |
14975 | ((INSTANCE) == TIM5)) |
| 14976 | ((INSTANCE) == TIM5)) |
14976 | |
| 14977 | 14977 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ |
|
| 14978 | #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\ |
14978 | (((INSTANCE) == TIM1) || \ |
| 14979 | (((INSTANCE) == TIM1) || \ |
14979 | ((INSTANCE) == TIM2) || \ |
| 14980 | ((INSTANCE) == TIM2) || \ |
14980 | ((INSTANCE) == TIM3) || \ |
| 14981 | ((INSTANCE) == TIM3) || \ |
14981 | ((INSTANCE) == TIM4) || \ |
| 14982 | ((INSTANCE) == TIM4) || \ |
14982 | ((INSTANCE) == TIM5)) |
| 14983 | ((INSTANCE) == TIM5)) |
14983 | |
| 14984 | 14984 | #define IS_TIM_XOR_INSTANCE(INSTANCE)\ |
|
| 14985 | #define IS_TIM_XOR_INSTANCE(INSTANCE)\ |
14985 | (((INSTANCE) == TIM1) || \ |
| 14986 | (((INSTANCE) == TIM1) || \ |
14986 | ((INSTANCE) == TIM2) || \ |
| 14987 | ((INSTANCE) == TIM2) || \ |
14987 | ((INSTANCE) == TIM3) || \ |
| 14988 | ((INSTANCE) == TIM3) || \ |
14988 | ((INSTANCE) == TIM4) || \ |
| 14989 | ((INSTANCE) == TIM4) || \ |
14989 | ((INSTANCE) == TIM5)) |
| 14990 | ((INSTANCE) == TIM5)) |
14990 | |
| 14991 | 14991 | #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ |
|
| 14992 | #define IS_TIM_MASTER_INSTANCE(INSTANCE)\ |
14992 | (((INSTANCE) == TIM1) || \ |
| 14993 | (((INSTANCE) == TIM1) || \ |
14993 | ((INSTANCE) == TIM2) || \ |
| 14994 | ((INSTANCE) == TIM2) || \ |
14994 | ((INSTANCE) == TIM3) || \ |
| 14995 | ((INSTANCE) == TIM3) || \ |
14995 | ((INSTANCE) == TIM4) || \ |
| 14996 | ((INSTANCE) == TIM4) || \ |
14996 | ((INSTANCE) == TIM5) || \ |
| 14997 | ((INSTANCE) == TIM5) || \ |
14997 | ((INSTANCE) == TIM6) || \ |
| 14998 | ((INSTANCE) == TIM6) || \ |
14998 | ((INSTANCE) == TIM7)) |
| 14999 | ((INSTANCE) == TIM7)) |
14999 | |
| 15000 | 15000 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ |
|
| 15001 | #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\ |
15001 | (((INSTANCE) == TIM1) || \ |
| 15002 | (((INSTANCE) == TIM1) || \ |
15002 | ((INSTANCE) == TIM2) || \ |
| 15003 | ((INSTANCE) == TIM2) || \ |
15003 | ((INSTANCE) == TIM3) || \ |
| 15004 | ((INSTANCE) == TIM3) || \ |
15004 | ((INSTANCE) == TIM4) || \ |
| 15005 | ((INSTANCE) == TIM4) || \ |
15005 | ((INSTANCE) == TIM5)) |
| 15006 | ((INSTANCE) == TIM5)) |
15006 | |
| 15007 | 15007 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ |
|
| 15008 | #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\ |
15008 | (((INSTANCE) == TIM1) || \ |
| 15009 | (((INSTANCE) == TIM1) || \ |
15009 | ((INSTANCE) == TIM2) || \ |
| 15010 | ((INSTANCE) == TIM2) || \ |
15010 | ((INSTANCE) == TIM3) || \ |
| 15011 | ((INSTANCE) == TIM3) || \ |
15011 | ((INSTANCE) == TIM4) || \ |
| 15012 | ((INSTANCE) == TIM4) || \ |
15012 | ((INSTANCE) == TIM5)) |
| 15013 | ((INSTANCE) == TIM5)) |
15013 | |
| 15014 | 15014 | #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ |
|
| 15015 | #define IS_TIM_BREAK_INSTANCE(INSTANCE)\ |
15015 | ((INSTANCE) == TIM1) |
| 15016 | ((INSTANCE) == TIM1) |
15016 | |
| 15017 | 15017 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
|
| 15018 | #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ |
15018 | ((((INSTANCE) == TIM1) && \ |
| 15019 | ((((INSTANCE) == TIM1) && \ |
15019 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| 15020 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
15020 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| 15021 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
15021 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| 15022 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
15022 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| 15023 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
15023 | || \ |
| 15024 | || \ |
15024 | (((INSTANCE) == TIM2) && \ |
| 15025 | (((INSTANCE) == TIM2) && \ |
15025 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| 15026 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
15026 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| 15027 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
15027 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| 15028 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
15028 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| 15029 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
15029 | || \ |
| 15030 | || \ |
15030 | (((INSTANCE) == TIM3) && \ |
| 15031 | (((INSTANCE) == TIM3) && \ |
15031 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| 15032 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
15032 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| 15033 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
15033 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| 15034 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
15034 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| 15035 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
15035 | || \ |
| 15036 | || \ |
15036 | (((INSTANCE) == TIM4) && \ |
| 15037 | (((INSTANCE) == TIM4) && \ |
15037 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| 15038 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
15038 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| 15039 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
15039 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| 15040 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
15040 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
| 15041 | ((CHANNEL) == TIM_CHANNEL_4))) \ |
15041 | || \ |
| 15042 | || \ |
15042 | (((INSTANCE) == TIM5) && \ |
| 15043 | (((INSTANCE) == TIM5) && \ |
15043 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| 15044 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
15044 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| 15045 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
15045 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
| 15046 | ((CHANNEL) == TIM_CHANNEL_3) || \ |
15046 | ((CHANNEL) == TIM_CHANNEL_4)))) |
| 15047 | ((CHANNEL) == TIM_CHANNEL_4)))) |
15047 | |
| 15048 | 15048 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ |
|
| 15049 | #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ |
15049 | (((INSTANCE) == TIM1) && \ |
| 15050 | (((INSTANCE) == TIM1) && \ |
15050 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
| 15051 | (((CHANNEL) == TIM_CHANNEL_1) || \ |
15051 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
| 15052 | ((CHANNEL) == TIM_CHANNEL_2) || \ |
15052 | ((CHANNEL) == TIM_CHANNEL_3))) |
| 15053 | ((CHANNEL) == TIM_CHANNEL_3))) |
15053 | |
| 15054 | 15054 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ |
|
| 15055 | #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\ |
15055 | (((INSTANCE) == TIM1) || \ |
| 15056 | (((INSTANCE) == TIM1) || \ |
15056 | ((INSTANCE) == TIM2) || \ |
| 15057 | ((INSTANCE) == TIM2) || \ |
15057 | ((INSTANCE) == TIM3) || \ |
| 15058 | ((INSTANCE) == TIM3) || \ |
15058 | ((INSTANCE) == TIM4) || \ |
| 15059 | ((INSTANCE) == TIM4) || \ |
15059 | ((INSTANCE) == TIM5)) |
| 15060 | ((INSTANCE) == TIM5)) |
15060 | |
| 15061 | 15061 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ |
|
| 15062 | #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\ |
15062 | ((INSTANCE) == TIM1) |
| 15063 | ((INSTANCE) == TIM1) |
15063 | |
| 15064 | 15064 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ |
|
| 15065 | #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\ |
15065 | (((INSTANCE) == TIM1) || \ |
| 15066 | (((INSTANCE) == TIM1) || \ |
15066 | ((INSTANCE) == TIM2) || \ |
| 15067 | ((INSTANCE) == TIM2) || \ |
15067 | ((INSTANCE) == TIM3) || \ |
| 15068 | ((INSTANCE) == TIM3) || \ |
15068 | ((INSTANCE) == TIM4) || \ |
| 15069 | ((INSTANCE) == TIM4) || \ |
15069 | ((INSTANCE) == TIM5)) |
| 15070 | ((INSTANCE) == TIM5)) |
15070 | |
| 15071 | 15071 | #define IS_TIM_DMA_INSTANCE(INSTANCE)\ |
|
| 15072 | #define IS_TIM_DMA_INSTANCE(INSTANCE)\ |
15072 | (((INSTANCE) == TIM1) || \ |
| 15073 | (((INSTANCE) == TIM1) || \ |
15073 | ((INSTANCE) == TIM2) || \ |
| 15074 | ((INSTANCE) == TIM2) || \ |
15074 | ((INSTANCE) == TIM3) || \ |
| 15075 | ((INSTANCE) == TIM3) || \ |
15075 | ((INSTANCE) == TIM4) || \ |
| 15076 | ((INSTANCE) == TIM4) || \ |
15076 | ((INSTANCE) == TIM5) || \ |
| 15077 | ((INSTANCE) == TIM5) || \ |
15077 | ((INSTANCE) == TIM6) || \ |
| 15078 | ((INSTANCE) == TIM6) || \ |
15078 | ((INSTANCE) == TIM7)) |
| 15079 | ((INSTANCE) == TIM7)) |
15079 | |
| 15080 | 15080 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ |
|
| 15081 | #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\ |
15081 | (((INSTANCE) == TIM1) || \ |
| 15082 | (((INSTANCE) == TIM1) || \ |
15082 | ((INSTANCE) == TIM2) || \ |
| 15083 | ((INSTANCE) == TIM2) || \ |
15083 | ((INSTANCE) == TIM3) || \ |
| 15084 | ((INSTANCE) == TIM3) || \ |
15084 | ((INSTANCE) == TIM4) || \ |
| 15085 | ((INSTANCE) == TIM4) || \ |
15085 | ((INSTANCE) == TIM5)) |
| 15086 | ((INSTANCE) == TIM5)) |
15086 | |
| 15087 | 15087 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ |
|
| 15088 | #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\ |
15088 | ((INSTANCE) == TIM1) |
| 15089 | ((INSTANCE) == TIM1) |
15089 | |
| 15090 | 15090 | #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
|
| 15091 | #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
15091 | ((INSTANCE) == TIM2) || \ |
| 15092 | ((INSTANCE) == TIM2) || \ |
15092 | ((INSTANCE) == TIM3) || \ |
| 15093 | ((INSTANCE) == TIM3) || \ |
15093 | ((INSTANCE) == TIM4) || \ |
| 15094 | ((INSTANCE) == TIM4) || \ |
15094 | ((INSTANCE) == TIM5)) |
| 15095 | ((INSTANCE) == TIM5)) |
15095 | |
| 15096 | 15096 | #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
|
| 15097 | #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \ |
15097 | ((INSTANCE) == TIM2) || \ |
| 15098 | ((INSTANCE) == TIM2) || \ |
15098 | ((INSTANCE) == TIM3) || \ |
| 15099 | ((INSTANCE) == TIM3) || \ |
15099 | ((INSTANCE) == TIM4) || \ |
| 15100 | ((INSTANCE) == TIM4) || \ |
15100 | ((INSTANCE) == TIM5)) |
| 15101 | ((INSTANCE) == TIM5)) |
15101 | |
| 15102 | 15102 | #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U |
|
| 15103 | #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U |
15103 | |
| 15104 | 15104 | /****************************** END TIM Instances *****************************/ |
|
| 15105 | /****************************** END TIM Instances *****************************/ |
15105 | |
| 15106 | 15106 | ||
| 15107 | 15107 | /******************** USART Instances : Synchronous mode **********************/ |
|
| 15108 | /******************** USART Instances : Synchronous mode **********************/ |
15108 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| 15109 | #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
15109 | ((INSTANCE) == USART2) || \ |
| 15110 | ((INSTANCE) == USART2) || \ |
15110 | ((INSTANCE) == USART3)) |
| 15111 | ((INSTANCE) == USART3)) |
15111 | |
| 15112 | 15112 | /******************** UART Instances : Asynchronous mode **********************/ |
|
| 15113 | /******************** UART Instances : Asynchronous mode **********************/ |
15113 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| 15114 | #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
15114 | ((INSTANCE) == USART2) || \ |
| 15115 | ((INSTANCE) == USART2) || \ |
15115 | ((INSTANCE) == USART3) || \ |
| 15116 | ((INSTANCE) == USART3) || \ |
15116 | ((INSTANCE) == UART4) || \ |
| 15117 | ((INSTANCE) == UART4) || \ |
15117 | ((INSTANCE) == UART5)) |
| 15118 | ((INSTANCE) == UART5)) |
15118 | |
| 15119 | 15119 | /******************** UART Instances : Half-Duplex mode **********************/ |
|
| 15120 | /******************** UART Instances : Half-Duplex mode **********************/ |
15120 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| 15121 | #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
15121 | ((INSTANCE) == USART2) || \ |
| 15122 | ((INSTANCE) == USART2) || \ |
15122 | ((INSTANCE) == USART3) || \ |
| 15123 | ((INSTANCE) == USART3) || \ |
15123 | ((INSTANCE) == UART4) || \ |
| 15124 | ((INSTANCE) == UART4) || \ |
15124 | ((INSTANCE) == UART5)) |
| 15125 | ((INSTANCE) == UART5)) |
15125 | |
| 15126 | 15126 | /******************** UART Instances : LIN mode **********************/ |
|
| 15127 | /******************** UART Instances : LIN mode **********************/ |
15127 | #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| 15128 | #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
15128 | ((INSTANCE) == USART2) || \ |
| 15129 | ((INSTANCE) == USART2) || \ |
15129 | ((INSTANCE) == USART3) || \ |
| 15130 | ((INSTANCE) == USART3) || \ |
15130 | ((INSTANCE) == UART4) || \ |
| 15131 | ((INSTANCE) == UART4) || \ |
15131 | ((INSTANCE) == UART5)) |
| 15132 | ((INSTANCE) == UART5)) |
15132 | |
| 15133 | 15133 | /****************** UART Instances : Hardware Flow control ********************/ |
|
| 15134 | /****************** UART Instances : Hardware Flow control ********************/ |
15134 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| 15135 | #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
15135 | ((INSTANCE) == USART2) || \ |
| 15136 | ((INSTANCE) == USART2) || \ |
15136 | ((INSTANCE) == USART3)) |
| 15137 | ((INSTANCE) == USART3)) |
15137 | |
| 15138 | 15138 | /********************* UART Instances : Smard card mode ***********************/ |
|
| 15139 | /********************* UART Instances : Smard card mode ***********************/ |
15139 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| 15140 | #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
15140 | ((INSTANCE) == USART2) || \ |
| 15141 | ((INSTANCE) == USART2) || \ |
15141 | ((INSTANCE) == USART3)) |
| 15142 | ((INSTANCE) == USART3)) |
15142 | |
| 15143 | 15143 | /*********************** UART Instances : IRDA mode ***************************/ |
|
| 15144 | /*********************** UART Instances : IRDA mode ***************************/ |
15144 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| 15145 | #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
15145 | ((INSTANCE) == USART2) || \ |
| 15146 | ((INSTANCE) == USART2) || \ |
15146 | ((INSTANCE) == USART3) || \ |
| 15147 | ((INSTANCE) == USART3) || \ |
15147 | ((INSTANCE) == UART4) || \ |
| 15148 | ((INSTANCE) == UART4) || \ |
15148 | ((INSTANCE) == UART5)) |
| 15149 | ((INSTANCE) == UART5)) |
15149 | |
| 15150 | 15150 | /***************** UART Instances : Multi-Processor mode **********************/ |
|
| 15151 | /***************** UART Instances : Multi-Processor mode **********************/ |
15151 | #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| 15152 | #define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
15152 | ((INSTANCE) == USART2) || \ |
| 15153 | ((INSTANCE) == USART2) || \ |
15153 | ((INSTANCE) == USART3) || \ |
| 15154 | ((INSTANCE) == USART3) || \ |
15154 | ((INSTANCE) == UART4) || \ |
| 15155 | ((INSTANCE) == UART4) || \ |
15155 | ((INSTANCE) == UART5)) |
| 15156 | ((INSTANCE) == UART5)) |
15156 | |
| 15157 | 15157 | /***************** UART Instances : DMA mode available **********************/ |
|
| 15158 | /***************** UART Instances : DMA mode available **********************/ |
15158 | #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
| 15159 | #define IS_UART_DMA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \ |
15159 | ((INSTANCE) == USART2) || \ |
| 15160 | ((INSTANCE) == USART2) || \ |
15160 | ((INSTANCE) == USART3) || \ |
| 15161 | ((INSTANCE) == USART3) || \ |
15161 | ((INSTANCE) == UART4)) |
| 15162 | ((INSTANCE) == UART4)) |
15162 | |
| 15163 | 15163 | /****************************** RTC Instances *********************************/ |
|
| 15164 | /****************************** RTC Instances *********************************/ |
15164 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
| 15165 | #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC) |
15165 | |
| 15166 | 15166 | /**************************** WWDG Instances *****************************/ |
|
| 15167 | /**************************** WWDG Instances *****************************/ |
15167 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
| 15168 | #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG) |
15168 | |
| 15169 | 15169 | ||
| 15170 | 15170 | /*********************** PCD Instances ****************************************/ |
|
| 15171 | /*********************** PCD Instances ****************************************/ |
15171 | #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS) |
| 15172 | #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS) |
15172 | |
| 15173 | 15173 | /*********************** HCD Instances ****************************************/ |
|
| 15174 | /*********************** HCD Instances ****************************************/ |
15174 | #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS) |
| 15175 | #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS) |
15175 | |
| 15176 | 15176 | /****************************** ETH Instances ********************************/ |
|
| 15177 | /****************************** ETH Instances ********************************/ |
15177 | #define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH) |
| 15178 | #define IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH) |
15178 | |
| 15179 | 15179 | #define RCC_HSE_MIN 3000000U |
|
| 15180 | #define RCC_HSE_MIN 3000000U |
15180 | #define RCC_HSE_MAX 25000000U |
| 15181 | #define RCC_HSE_MAX 25000000U |
15181 | |
| 15182 | 15182 | #define RCC_MAX_FREQUENCY 72000000U |
|
| 15183 | #define RCC_MAX_FREQUENCY 72000000U |
15183 | |
| 15184 | 15184 | /** |
|
| 15185 | /** |
15185 | * @} |
| 15186 | * @} |
15186 | */ |
| 15187 | */ |
15187 | /******************************************************************************/ |
| 15188 | /******************************************************************************/ |
15188 | /* For a painless codes migration between the STM32F1xx device product */ |
| 15189 | /* For a painless codes migration between the STM32F1xx device product */ |
15189 | /* lines, the aliases defined below are put in place to overcome the */ |
| 15190 | /* lines, the aliases defined below are put in place to overcome the */ |
15190 | /* differences in the interrupt handlers and IRQn definitions. */ |
| 15191 | /* differences in the interrupt handlers and IRQn definitions. */ |
15191 | /* No need to update developed interrupt code when moving across */ |
| 15192 | /* No need to update developed interrupt code when moving across */ |
15192 | /* product lines within the same STM32F1 Family */ |
| 15193 | /* product lines within the same STM32F1 Family */ |
15193 | /******************************************************************************/ |
| 15194 | /******************************************************************************/ |
15194 | |
| 15195 | 15195 | /* Aliases for __IRQn */ |
|
| 15196 | /* Aliases for __IRQn */ |
15196 | #define ADC1_IRQn ADC1_2_IRQn |
| 15197 | #define ADC1_IRQn ADC1_2_IRQn |
15197 | #define USB_LP_IRQn CAN1_RX0_IRQn |
| 15198 | #define USB_LP_IRQn CAN1_RX0_IRQn |
15198 | #define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn |
| 15199 | #define USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn |
15199 | #define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn |
| 15200 | #define USB_HP_IRQn CAN1_TX_IRQn |
15200 | #define USB_HP_IRQn CAN1_TX_IRQn |
| 15201 | #define USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn |
15201 | #define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn |
| 15202 | #define DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn |
15202 | #define USBWakeUp_IRQn OTG_FS_WKUP_IRQn |
| 15203 | #define USBWakeUp_IRQn OTG_FS_WKUP_IRQn |
15203 | #define CEC_IRQn OTG_FS_WKUP_IRQn |
| 15204 | #define CEC_IRQn OTG_FS_WKUP_IRQn |
15204 | #define TIM9_IRQn TIM1_BRK_IRQn |
| 15205 | #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
15205 | #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn |
| 15206 | #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn |
15206 | #define TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn |
| 15207 | #define TIM9_IRQn TIM1_BRK_IRQn |
15207 | #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
| 15208 | #define TIM11_IRQn TIM1_TRG_COM_IRQn |
15208 | #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn |
| 15209 | #define TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn |
15209 | #define TIM11_IRQn TIM1_TRG_COM_IRQn |
| 15210 | #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn |
15210 | #define TIM10_IRQn TIM1_UP_IRQn |
| 15211 | #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn |
15211 | #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
| 15212 | #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn |
15212 | #define TIM1_UP_TIM16_IRQn TIM1_UP_IRQn |
| 15213 | #define TIM10_IRQn TIM1_UP_IRQn |
15213 | #define TIM6_DAC_IRQn TIM6_IRQn |
| 15214 | #define TIM6_DAC_IRQn TIM6_IRQn |
15214 | |
| 15215 | 15215 | ||
| 15216 | 15216 | /* Aliases for __IRQHandler */ |
|
| 15217 | /* Aliases for __IRQHandler */ |
15217 | #define ADC1_IRQHandler ADC1_2_IRQHandler |
| 15218 | #define ADC1_IRQHandler ADC1_2_IRQHandler |
15218 | #define USB_LP_IRQHandler CAN1_RX0_IRQHandler |
| 15219 | #define USB_LP_IRQHandler CAN1_RX0_IRQHandler |
15219 | #define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler |
| 15220 | #define USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler |
15220 | #define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler |
| 15221 | #define USB_HP_IRQHandler CAN1_TX_IRQHandler |
15221 | #define USB_HP_IRQHandler CAN1_TX_IRQHandler |
| 15222 | #define USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler |
15222 | #define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler |
| 15223 | #define DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler |
15223 | #define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler |
| 15224 | #define USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler |
15224 | #define CEC_IRQHandler OTG_FS_WKUP_IRQHandler |
| 15225 | #define CEC_IRQHandler OTG_FS_WKUP_IRQHandler |
15225 | #define TIM9_IRQHandler TIM1_BRK_IRQHandler |
| 15226 | #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
15226 | #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler |
| 15227 | #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler |
15227 | #define TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler |
| 15228 | #define TIM9_IRQHandler TIM1_BRK_IRQHandler |
15228 | #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| 15229 | #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
15229 | #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler |
| 15230 | #define TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler |
15230 | #define TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
| 15231 | #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler |
15231 | #define TIM10_IRQHandler TIM1_UP_IRQHandler |
| 15232 | #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler |
15232 | #define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler |
| 15233 | #define TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler |
15233 | #define TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler |
| 15234 | #define TIM10_IRQHandler TIM1_UP_IRQHandler |
15234 | #define TIM6_DAC_IRQHandler TIM6_IRQHandler |
| 15235 | #define TIM6_DAC_IRQHandler TIM6_IRQHandler |
15235 | |
| 15236 | 15236 | ||
| 15237 | 15237 | /** |
|
| 15238 | /** |
15238 | * @} |
| 15239 | * @} |
15239 | */ |
| 15240 | */ |
15240 | |
| 15241 | 15241 | /** |
|
| 15242 | /** |
15242 | * @} |
| 15243 | * @} |
15243 | */ |
| 15244 | */ |
15244 | |
| 15245 | 15245 | ||
| 15246 | 15246 | #ifdef __cplusplus |
|
| 15247 | #ifdef __cplusplus |
15247 | } |
| 15248 | } |
15248 | #endif /* __cplusplus */ |
| 15249 | #endif /* __cplusplus */ |
15249 | |
| 15250 | 15250 | #endif /* __STM32F107xC_H */ |
|
| 15251 | #endif /* __STM32F107xC_H */ |
15251 | |
| 15252 | 15252 | ||
| 15253 | 15253 | ||
| 15254 | - | ||
| 15255 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |