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| 38 | 38 | ||
| 39 | #ifdef __cplusplus |
39 | #ifdef __cplusplus |
| 40 | extern "C" { |
40 | extern "C" { |
| 41 | #endif /* __cplusplus */ |
41 | #endif /* __cplusplus */ |
| 42 | 42 | ||
| 43 | /** @addtogroup Configuration_section_for_CMSIS |
43 | /** @addtogroup Configuration_section_for_CMSIS |
| 44 | * @{ |
44 | * @{ |
| 45 | */ |
45 | */ |
| 46 | /** |
46 | /** |
| 47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
| 48 | */ |
48 | */ |
| Line 62... | Line 62... | ||
| 62 | /** |
62 | /** |
| 63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
| 64 | * in @ref Library_configuration_section |
64 | * in @ref Library_configuration_section |
| 65 | */ |
65 | */ |
| 66 | 66 | ||
| 67 | /*!< Interrupt Number Definition */ |
67 | /*!< Interrupt Number Definition */ |
| 68 | typedef enum |
68 | typedef enum |
| 69 | { |
69 | { |
| 70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
| 71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| 72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
| Line 591... | Line 591... | ||
| 591 | 591 | ||
| 592 | /** @addtogroup Exported_constants |
592 | /** @addtogroup Exported_constants |
| 593 | * @{ |
593 | * @{ |
| 594 | */ |
594 | */ |
| 595 | 595 | ||
| - | 596 | /** @addtogroup Hardware_Constant_Definition |
|
| - | 597 | * @{ |
|
| - | 598 | */ |
|
| - | 599 | #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
|
| - | 600 | ||
| - | 601 | /** |
|
| - | 602 | * @} |
|
| - | 603 | */ |
|
| - | 604 | ||
| 596 | /** @addtogroup Peripheral_Registers_Bits_Definition |
605 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| 597 | * @{ |
606 | * @{ |
| 598 | */ |
607 | */ |
| 599 | 608 | ||
| 600 | /******************************************************************************/ |
609 | /******************************************************************************/ |
| 601 | /* Peripheral Registers Bits Definition */ |
610 | /* Peripheral Registers Bits Definition */ |
| Line 2393... | Line 2402... | ||
| 2393 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
2402 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
| 2394 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
2403 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
| 2395 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
2404 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
| 2396 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
2405 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
| 2397 | 2406 | ||
| 2398 | /* Legacy aliases */ |
2407 | /* Legacy aliases */ |
| 2399 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
2408 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
| 2400 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
2409 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
| 2401 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
2410 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
| 2402 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
2411 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
| 2403 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
2412 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
| Line 5788... | Line 5797... | ||
| 5788 | 5797 | ||
| 5789 | /** |
5798 | /** |
| 5790 | * @} |
5799 | * @} |
| 5791 | */ |
5800 | */ |
| 5792 | 5801 | ||
| 5793 | /** |
5802 | /** |
| 5794 | * @} |
5803 | * @} |
| 5795 | */ |
5804 | */ |
| 5796 | 5805 | ||
| 5797 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
5806 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |