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38 | 38 | ||
39 | #ifdef __cplusplus |
39 | #ifdef __cplusplus |
40 | extern "C" { |
40 | extern "C" { |
41 | #endif /* __cplusplus */ |
41 | #endif /* __cplusplus */ |
42 | 42 | ||
43 | /** @addtogroup Configuration_section_for_CMSIS |
43 | /** @addtogroup Configuration_section_for_CMSIS |
44 | * @{ |
44 | * @{ |
45 | */ |
45 | */ |
46 | /** |
46 | /** |
47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
48 | */ |
48 | */ |
Line 62... | Line 62... | ||
62 | /** |
62 | /** |
63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
64 | * in @ref Library_configuration_section |
64 | * in @ref Library_configuration_section |
65 | */ |
65 | */ |
66 | 66 | ||
67 | /*!< Interrupt Number Definition */ |
67 | /*!< Interrupt Number Definition */ |
68 | typedef enum |
68 | typedef enum |
69 | { |
69 | { |
70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
Line 568... | Line 568... | ||
568 | 568 | ||
569 | /** @addtogroup Exported_constants |
569 | /** @addtogroup Exported_constants |
570 | * @{ |
570 | * @{ |
571 | */ |
571 | */ |
572 | 572 | ||
- | 573 | /** @addtogroup Hardware_Constant_Definition |
|
- | 574 | * @{ |
|
- | 575 | */ |
|
- | 576 | #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
|
- | 577 | ||
- | 578 | /** |
|
- | 579 | * @} |
|
- | 580 | */ |
|
- | 581 | ||
573 | /** @addtogroup Peripheral_Registers_Bits_Definition |
582 | /** @addtogroup Peripheral_Registers_Bits_Definition |
574 | * @{ |
583 | * @{ |
575 | */ |
584 | */ |
576 | 585 | ||
577 | /******************************************************************************/ |
586 | /******************************************************************************/ |
578 | /* Peripheral Registers Bits Definition */ |
587 | /* Peripheral Registers Bits Definition */ |
Line 2313... | Line 2322... | ||
2313 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
2322 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
2314 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
2323 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
2315 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
2324 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
2316 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
2325 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
2317 | 2326 | ||
2318 | /* Legacy aliases */ |
2327 | /* Legacy aliases */ |
2319 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
2328 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
2320 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
2329 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
2321 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
2330 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
2322 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
2331 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
2323 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
2332 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
Line 5602... | Line 5611... | ||
5602 | 5611 | ||
5603 | /** |
5612 | /** |
5604 | * @} |
5613 | * @} |
5605 | */ |
5614 | */ |
5606 | 5615 | ||
5607 | /** |
5616 | /** |
5608 | * @} |
5617 | * @} |
5609 | */ |
5618 | */ |
5610 | 5619 | ||
5611 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
5620 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |