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| 38 | 38 | ||
| 39 | #ifdef __cplusplus |
39 | #ifdef __cplusplus |
| 40 | extern "C" { |
40 | extern "C" { |
| 41 | #endif /* __cplusplus */ |
41 | #endif /* __cplusplus */ |
| 42 | 42 | ||
| 43 | /** @addtogroup Configuration_section_for_CMSIS |
43 | /** @addtogroup Configuration_section_for_CMSIS |
| 44 | * @{ |
44 | * @{ |
| 45 | */ |
45 | */ |
| 46 | /** |
46 | /** |
| 47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
| 48 | */ |
48 | */ |
| Line 62... | Line 62... | ||
| 62 | /** |
62 | /** |
| 63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
| 64 | * in @ref Library_configuration_section |
64 | * in @ref Library_configuration_section |
| 65 | */ |
65 | */ |
| 66 | 66 | ||
| 67 | /*!< Interrupt Number Definition */ |
67 | /*!< Interrupt Number Definition */ |
| 68 | typedef enum |
68 | typedef enum |
| 69 | { |
69 | { |
| 70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
| 71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| 72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
| Line 638... | Line 638... | ||
| 638 | 638 | ||
| 639 | /** @addtogroup Exported_constants |
639 | /** @addtogroup Exported_constants |
| 640 | * @{ |
640 | * @{ |
| 641 | */ |
641 | */ |
| 642 | 642 | ||
| - | 643 | /** @addtogroup Hardware_Constant_Definition |
|
| - | 644 | * @{ |
|
| - | 645 | */ |
|
| - | 646 | #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
|
| - | 647 | ||
| - | 648 | /** |
|
| - | 649 | * @} |
|
| - | 650 | */ |
|
| - | 651 | ||
| 643 | /** @addtogroup Peripheral_Registers_Bits_Definition |
652 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| 644 | * @{ |
653 | * @{ |
| 645 | */ |
654 | */ |
| 646 | 655 | ||
| 647 | /******************************************************************************/ |
656 | /******************************************************************************/ |
| 648 | /* Peripheral Registers Bits Definition */ |
657 | /* Peripheral Registers Bits Definition */ |
| Line 2801... | Line 2810... | ||
| 2801 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
2810 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
| 2802 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
2811 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
| 2803 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
2812 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
| 2804 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
2813 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
| 2805 | 2814 | ||
| 2806 | /* Legacy aliases */ |
2815 | /* Legacy aliases */ |
| 2807 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
2816 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
| 2808 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
2817 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
| 2809 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
2818 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
| 2810 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
2819 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
| 2811 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
2820 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
| Line 6723... | Line 6732... | ||
| 6723 | 6732 | ||
| 6724 | /** |
6733 | /** |
| 6725 | * @} |
6734 | * @} |
| 6726 | */ |
6735 | */ |
| 6727 | 6736 | ||
| 6728 | /** |
6737 | /** |
| 6729 | * @} |
6738 | * @} |
| 6730 | */ |
6739 | */ |
| 6731 | 6740 | ||
| 6732 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
6741 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |