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| 38 | 38 | ||
| 39 | #ifdef __cplusplus |
39 | #ifdef __cplusplus |
| 40 | extern "C" { |
40 | extern "C" { |
| 41 | #endif /* __cplusplus */ |
41 | #endif /* __cplusplus */ |
| 42 | 42 | ||
| 43 | /** @addtogroup Configuration_section_for_CMSIS |
43 | /** @addtogroup Configuration_section_for_CMSIS |
| 44 | * @{ |
44 | * @{ |
| 45 | */ |
45 | */ |
| 46 | /** |
46 | /** |
| 47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
| 48 | */ |
48 | */ |
| Line 62... | Line 62... | ||
| 62 | /** |
62 | /** |
| 63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
| 64 | * in @ref Library_configuration_section |
64 | * in @ref Library_configuration_section |
| 65 | */ |
65 | */ |
| 66 | 66 | ||
| 67 | /*!< Interrupt Number Definition */ |
67 | /*!< Interrupt Number Definition */ |
| 68 | typedef enum |
68 | typedef enum |
| 69 | { |
69 | { |
| 70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
| 71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| 72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
| Line 532... | Line 532... | ||
| 532 | 532 | ||
| 533 | /** @addtogroup Exported_constants |
533 | /** @addtogroup Exported_constants |
| 534 | * @{ |
534 | * @{ |
| 535 | */ |
535 | */ |
| 536 | 536 | ||
| - | 537 | /** @addtogroup Hardware_Constant_Definition |
|
| - | 538 | * @{ |
|
| - | 539 | */ |
|
| - | 540 | #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
|
| - | 541 | ||
| - | 542 | /** |
|
| - | 543 | * @} |
|
| - | 544 | */ |
|
| - | 545 | ||
| 537 | /** @addtogroup Peripheral_Registers_Bits_Definition |
546 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| 538 | * @{ |
547 | * @{ |
| 539 | */ |
548 | */ |
| 540 | 549 | ||
| 541 | /******************************************************************************/ |
550 | /******************************************************************************/ |
| 542 | /* Peripheral Registers Bits Definition */ |
551 | /* Peripheral Registers Bits Definition */ |
| Line 2355... | Line 2364... | ||
| 2355 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
2364 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
| 2356 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
2365 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
| 2357 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
2366 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
| 2358 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
2367 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
| 2359 | 2368 | ||
| 2360 | /* Legacy aliases */ |
2369 | /* Legacy aliases */ |
| 2361 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
2370 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
| 2362 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
2371 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
| 2363 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
2372 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
| 2364 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
2373 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
| 2365 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
2374 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
| Line 5641... | Line 5650... | ||
| 5641 | 5650 | ||
| 5642 | /** |
5651 | /** |
| 5643 | * @} |
5652 | * @} |
| 5644 | */ |
5653 | */ |
| 5645 | 5654 | ||
| 5646 | /** |
5655 | /** |
| 5647 | * @} |
5656 | * @} |
| 5648 | */ |
5657 | */ |
| 5649 | 5658 | ||
| 5650 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
5659 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |