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38 | 38 | ||
39 | #ifdef __cplusplus |
39 | #ifdef __cplusplus |
40 | extern "C" { |
40 | extern "C" { |
41 | #endif /* __cplusplus */ |
41 | #endif /* __cplusplus */ |
42 | 42 | ||
43 | /** @addtogroup Configuration_section_for_CMSIS |
43 | /** @addtogroup Configuration_section_for_CMSIS |
44 | * @{ |
44 | * @{ |
45 | */ |
45 | */ |
46 | /** |
46 | /** |
47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
48 | */ |
48 | */ |
Line 62... | Line 62... | ||
62 | /** |
62 | /** |
63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
64 | * in @ref Library_configuration_section |
64 | * in @ref Library_configuration_section |
65 | */ |
65 | */ |
66 | 66 | ||
67 | /*!< Interrupt Number Definition */ |
67 | /*!< Interrupt Number Definition */ |
68 | typedef enum |
68 | typedef enum |
69 | { |
69 | { |
70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
Line 533... | Line 533... | ||
533 | 533 | ||
534 | /** @addtogroup Exported_constants |
534 | /** @addtogroup Exported_constants |
535 | * @{ |
535 | * @{ |
536 | */ |
536 | */ |
537 | 537 | ||
- | 538 | /** @addtogroup Hardware_Constant_Definition |
|
- | 539 | * @{ |
|
- | 540 | */ |
|
- | 541 | #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
|
- | 542 | ||
- | 543 | /** |
|
- | 544 | * @} |
|
- | 545 | */ |
|
- | 546 | ||
538 | /** @addtogroup Peripheral_Registers_Bits_Definition |
547 | /** @addtogroup Peripheral_Registers_Bits_Definition |
539 | * @{ |
548 | * @{ |
540 | */ |
549 | */ |
541 | 550 | ||
542 | /******************************************************************************/ |
551 | /******************************************************************************/ |
543 | /* Peripheral Registers Bits Definition */ |
552 | /* Peripheral Registers Bits Definition */ |
Line 2356... | Line 2365... | ||
2356 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
2365 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
2357 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
2366 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
2358 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
2367 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
2359 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
2368 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
2360 | 2369 | ||
2361 | /* Legacy aliases */ |
2370 | /* Legacy aliases */ |
2362 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
2371 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
2363 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
2372 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
2364 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
2373 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
2365 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
2374 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
2366 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
2375 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
Line 5676... | Line 5685... | ||
5676 | 5685 | ||
5677 | /** |
5686 | /** |
5678 | * @} |
5687 | * @} |
5679 | */ |
5688 | */ |
5680 | 5689 | ||
5681 | /** |
5690 | /** |
5682 | * @} |
5691 | * @} |
5683 | */ |
5692 | */ |
5684 | 5693 | ||
5685 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
5694 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |