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| 38 | 38 | ||
| 39 | #ifdef __cplusplus |
39 | #ifdef __cplusplus |
| 40 | extern "C" { |
40 | extern "C" { |
| 41 | #endif /* __cplusplus */ |
41 | #endif /* __cplusplus */ |
| 42 | 42 | ||
| 43 | /** @addtogroup Configuration_section_for_CMSIS |
43 | /** @addtogroup Configuration_section_for_CMSIS |
| 44 | * @{ |
44 | * @{ |
| 45 | */ |
45 | */ |
| 46 | /** |
46 | /** |
| 47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
| 48 | */ |
48 | */ |
| Line 62... | Line 62... | ||
| 62 | /** |
62 | /** |
| 63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
| 64 | * in @ref Library_configuration_section |
64 | * in @ref Library_configuration_section |
| 65 | */ |
65 | */ |
| 66 | 66 | ||
| 67 | /*!< Interrupt Number Definition */ |
67 | /*!< Interrupt Number Definition */ |
| 68 | typedef enum |
68 | typedef enum |
| 69 | { |
69 | { |
| 70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
| 71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| 72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
| Line 555... | Line 555... | ||
| 555 | 555 | ||
| 556 | /** @addtogroup Exported_constants |
556 | /** @addtogroup Exported_constants |
| 557 | * @{ |
557 | * @{ |
| 558 | */ |
558 | */ |
| 559 | 559 | ||
| - | 560 | /** @addtogroup Hardware_Constant_Definition |
|
| - | 561 | * @{ |
|
| - | 562 | */ |
|
| - | 563 | #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
|
| - | 564 | ||
| - | 565 | /** |
|
| - | 566 | * @} |
|
| - | 567 | */ |
|
| - | 568 | ||
| 560 | /** @addtogroup Peripheral_Registers_Bits_Definition |
569 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| 561 | * @{ |
570 | * @{ |
| 562 | */ |
571 | */ |
| 563 | 572 | ||
| 564 | /******************************************************************************/ |
573 | /******************************************************************************/ |
| 565 | /* Peripheral Registers Bits Definition */ |
574 | /* Peripheral Registers Bits Definition */ |
| Line 2541... | Line 2550... | ||
| 2541 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
2550 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
| 2542 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
2551 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
| 2543 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
2552 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
| 2544 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
2553 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
| 2545 | 2554 | ||
| 2546 | /* Legacy aliases */ |
2555 | /* Legacy aliases */ |
| 2547 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
2556 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
| 2548 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
2557 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
| 2549 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
2558 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
| 2550 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
2559 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
| 2551 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
2560 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
| Line 3129... | Line 3138... | ||
| 3129 | #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */ |
3138 | #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */ |
| 3130 | #define RCC_CFGR_PPRE_DIV16_Pos (8U) |
3139 | #define RCC_CFGR_PPRE_DIV16_Pos (8U) |
| 3131 | #define RCC_CFGR_PPRE_DIV16_Msk (0x7UL << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */ |
3140 | #define RCC_CFGR_PPRE_DIV16_Msk (0x7UL << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */ |
| 3132 | #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */ |
3141 | #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */ |
| 3133 | 3142 | ||
| 3134 | #define RCC_CFGR_PLLSRC_Pos (15U) |
3143 | #define RCC_CFGR_PLLSRC_Pos (16U) |
| 3135 | #define RCC_CFGR_PLLSRC_Msk (0x3UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00018000 */ |
3144 | #define RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */ |
| 3136 | #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ |
3145 | #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */ |
| 3137 | #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
3146 | #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */ |
| 3138 | #define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock selected as PLL entry clock source */ |
3147 | #define RCC_CFGR_PLLSRC_HSI_PREDIV (0x00008000U) /*!< HSI/PREDIV clock selected as PLL entry clock source */ |
| 3139 | #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */ |
3148 | #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */ |
| 3140 | 3149 | ||
| Line 5796... | Line 5805... | ||
| 5796 | 5805 | ||
| 5797 | /** |
5806 | /** |
| 5798 | * @} |
5807 | * @} |
| 5799 | */ |
5808 | */ |
| 5800 | 5809 | ||
| 5801 | /** |
5810 | /** |
| 5802 | * @} |
5811 | * @} |
| 5803 | */ |
5812 | */ |
| 5804 | 5813 | ||
| 5805 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
5814 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |