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38 | 38 | ||
39 | #ifdef __cplusplus |
39 | #ifdef __cplusplus |
40 | extern "C" { |
40 | extern "C" { |
41 | #endif /* __cplusplus */ |
41 | #endif /* __cplusplus */ |
42 | 42 | ||
43 | /** @addtogroup Configuration_section_for_CMSIS |
43 | /** @addtogroup Configuration_section_for_CMSIS |
44 | * @{ |
44 | * @{ |
45 | */ |
45 | */ |
46 | /** |
46 | /** |
47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
48 | */ |
48 | */ |
Line 62... | Line 62... | ||
62 | /** |
62 | /** |
63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
64 | * in @ref Library_configuration_section |
64 | * in @ref Library_configuration_section |
65 | */ |
65 | */ |
66 | 66 | ||
67 | /*!< Interrupt Number Definition */ |
67 | /*!< Interrupt Number Definition */ |
68 | typedef enum |
68 | typedef enum |
69 | { |
69 | { |
70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
Line 539... | Line 539... | ||
539 | 539 | ||
540 | /** @addtogroup Exported_constants |
540 | /** @addtogroup Exported_constants |
541 | * @{ |
541 | * @{ |
542 | */ |
542 | */ |
543 | 543 | ||
- | 544 | /** @addtogroup Hardware_Constant_Definition |
|
- | 545 | * @{ |
|
- | 546 | */ |
|
- | 547 | #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
|
- | 548 | ||
- | 549 | /** |
|
- | 550 | * @} |
|
- | 551 | */ |
|
- | 552 | ||
544 | /** @addtogroup Peripheral_Registers_Bits_Definition |
553 | /** @addtogroup Peripheral_Registers_Bits_Definition |
545 | * @{ |
554 | * @{ |
546 | */ |
555 | */ |
547 | 556 | ||
548 | /******************************************************************************/ |
557 | /******************************************************************************/ |
549 | /* Peripheral Registers Bits Definition */ |
558 | /* Peripheral Registers Bits Definition */ |
Line 2290... | Line 2299... | ||
2290 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
2299 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
2291 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
2300 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
2292 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
2301 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
2293 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
2302 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
2294 | 2303 | ||
2295 | /* Legacy aliases */ |
2304 | /* Legacy aliases */ |
2296 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
2305 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
2297 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
2306 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
2298 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
2307 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
2299 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
2308 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
2300 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
2309 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
Line 5417... | Line 5426... | ||
5417 | 5426 | ||
5418 | /** |
5427 | /** |
5419 | * @} |
5428 | * @} |
5420 | */ |
5429 | */ |
5421 | 5430 | ||
5422 | /** |
5431 | /** |
5423 | * @} |
5432 | * @} |
5424 | */ |
5433 | */ |
5425 | 5434 | ||
5426 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
5435 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |