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| 38 | 38 | ||
| 39 | #ifdef __cplusplus |
39 | #ifdef __cplusplus |
| 40 | extern "C" { |
40 | extern "C" { |
| 41 | #endif /* __cplusplus */ |
41 | #endif /* __cplusplus */ |
| 42 | 42 | ||
| 43 | /** @addtogroup Configuration_section_for_CMSIS |
43 | /** @addtogroup Configuration_section_for_CMSIS |
| 44 | * @{ |
44 | * @{ |
| 45 | */ |
45 | */ |
| 46 | /** |
46 | /** |
| 47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
47 | * @brief Configuration of the Cortex-M0 Processor and Core Peripherals |
| 48 | */ |
48 | */ |
| Line 62... | Line 62... | ||
| 62 | /** |
62 | /** |
| 63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
63 | * @brief STM32F0xx Interrupt Number Definition, according to the selected device |
| 64 | * in @ref Library_configuration_section |
64 | * in @ref Library_configuration_section |
| 65 | */ |
65 | */ |
| 66 | 66 | ||
| 67 | /*!< Interrupt Number Definition */ |
67 | /*!< Interrupt Number Definition */ |
| 68 | typedef enum |
68 | typedef enum |
| 69 | { |
69 | { |
| 70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
70 | /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/ |
| 71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
71 | NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ |
| 72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
72 | HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ |
| Line 523... | Line 523... | ||
| 523 | 523 | ||
| 524 | /** @addtogroup Exported_constants |
524 | /** @addtogroup Exported_constants |
| 525 | * @{ |
525 | * @{ |
| 526 | */ |
526 | */ |
| 527 | 527 | ||
| - | 528 | /** @addtogroup Hardware_Constant_Definition |
|
| - | 529 | * @{ |
|
| - | 530 | */ |
|
| - | 531 | #define LSI_STARTUP_TIME 85U /*!< LSI Maximum startup time in us */ |
|
| - | 532 | ||
| - | 533 | /** |
|
| - | 534 | * @} |
|
| - | 535 | */ |
|
| - | 536 | ||
| 528 | /** @addtogroup Peripheral_Registers_Bits_Definition |
537 | /** @addtogroup Peripheral_Registers_Bits_Definition |
| 529 | * @{ |
538 | * @{ |
| 530 | */ |
539 | */ |
| 531 | 540 | ||
| 532 | /******************************************************************************/ |
541 | /******************************************************************************/ |
| 533 | /* Peripheral Registers Bits Definition */ |
542 | /* Peripheral Registers Bits Definition */ |
| Line 2260... | Line 2269... | ||
| 2260 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
2269 | #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk |
| 2261 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
2270 | #define GPIO_AFRL_AFSEL7_Pos (28U) |
| 2262 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
2271 | #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ |
| 2263 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
2272 | #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk |
| 2264 | 2273 | ||
| 2265 | /* Legacy aliases */ |
2274 | /* Legacy aliases */ |
| 2266 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
2275 | #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos |
| 2267 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
2276 | #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk |
| 2268 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
2277 | #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0 |
| 2269 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
2278 | #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos |
| 2270 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
2279 | #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk |
| Line 5350... | Line 5359... | ||
| 5350 | 5359 | ||
| 5351 | /** |
5360 | /** |
| 5352 | * @} |
5361 | * @} |
| 5353 | */ |
5362 | */ |
| 5354 | 5363 | ||
| 5355 | /** |
5364 | /** |
| 5356 | * @} |
5365 | * @} |
| 5357 | */ |
5366 | */ |
| 5358 | 5367 | ||
| 5359 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
5368 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |