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ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 1
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ARM GAS  C:\Users\mike\AppData\Local\Temp\cc5OGnig.s 			page 1
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   1              		.cpu cortex-m3
 4 
   1              		.cpu cortex-m3
5 
   2              		.eabi_attribute 20, 1
 5 
   2              		.eabi_attribute 20, 1
6 
   3              		.eabi_attribute 21, 1
 6 
   3              		.eabi_attribute 21, 1
Line 56... Line 56...
56 
  28:Core/Src/system_stm32f1xx.c ****   *    the product used), refer to "HSE_VALUE".
56 
  28:Core/Src/system_stm32f1xx.c ****   *    the product used), refer to "HSE_VALUE".
57 
  29:Core/Src/system_stm32f1xx.c ****   *    When HSE is used as system clock source, directly or through PLL, and you
 57 
  29:Core/Src/system_stm32f1xx.c ****   *    When HSE is used as system clock source, directly or through PLL, and you
58 
  30:Core/Src/system_stm32f1xx.c ****   *    are using different crystal you have to adapt the HSE value to your own
 58 
  30:Core/Src/system_stm32f1xx.c ****   *    are using different crystal you have to adapt the HSE value to your own
59 
  31:Core/Src/system_stm32f1xx.c ****   *    configuration.
 59 
  31:Core/Src/system_stm32f1xx.c ****   *    configuration.
60 
  32:Core/Src/system_stm32f1xx.c ****   *
60 
  32:Core/Src/system_stm32f1xx.c ****   *
61 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 2
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  33:Core/Src/system_stm32f1xx.c ****   ******************************************************************************
 64 
  33:Core/Src/system_stm32f1xx.c ****   ******************************************************************************
65 
  34:Core/Src/system_stm32f1xx.c ****   * @attention
 65 
  34:Core/Src/system_stm32f1xx.c ****   * @attention
66 
  35:Core/Src/system_stm32f1xx.c ****   *
 66 
  35:Core/Src/system_stm32f1xx.c ****   *
Line 116... Line 116...
116 
  85:Core/Src/system_stm32f1xx.c **** #endif /* HSI_VALUE */
 116 
  85:Core/Src/system_stm32f1xx.c **** #endif /* HSI_VALUE */
117 
  86:Core/Src/system_stm32f1xx.c ****
117 
  86:Core/Src/system_stm32f1xx.c ****
118 
  87:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to use external SRAM  */
118 
  87:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to use external SRAM  */
119 
  88:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
 119 
  88:Core/Src/system_stm32f1xx.c **** #if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) ||
120 
  89:Core/Src/system_stm32f1xx.c **** /* #define DATA_IN_ExtSRAM */
 120 
  89:Core/Src/system_stm32f1xx.c **** /* #define DATA_IN_ExtSRAM */
121 
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124 
  90:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
 124 
  90:Core/Src/system_stm32f1xx.c **** #endif /* STM32F100xE || STM32F101xE || STM32F101xG || STM32F103xE || STM32F103xG */
125 
  91:Core/Src/system_stm32f1xx.c ****
125 
  91:Core/Src/system_stm32f1xx.c ****
126 
  92:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table in
 126 
  92:Core/Src/system_stm32f1xx.c **** /*!< Uncomment the following line if you need to relocate your vector Table in
Line 176... Line 176...
176 
 142:Core/Src/system_stm32f1xx.c ****   * @}
 176 
 142:Core/Src/system_stm32f1xx.c ****   * @}
177 
 143:Core/Src/system_stm32f1xx.c ****   */
 177 
 143:Core/Src/system_stm32f1xx.c ****   */
178 
 144:Core/Src/system_stm32f1xx.c ****
178 
 144:Core/Src/system_stm32f1xx.c ****
179 
 145:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Functions
 179 
 145:Core/Src/system_stm32f1xx.c **** /** @addtogroup STM32F1xx_System_Private_Functions
180 
 146:Core/Src/system_stm32f1xx.c ****   * @{
 180 
 146:Core/Src/system_stm32f1xx.c ****   * @{
181 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 4
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184 
 147:Core/Src/system_stm32f1xx.c ****   */
 184 
 147:Core/Src/system_stm32f1xx.c ****   */
185 
 148:Core/Src/system_stm32f1xx.c ****
185 
 148:Core/Src/system_stm32f1xx.c ****
186 
 149:Core/Src/system_stm32f1xx.c **** /**
 186 
 149:Core/Src/system_stm32f1xx.c **** /**
Line 236... Line 236...
236 
  51              		.loc 1 174 11 is_stmt 0 view .LVU8
 236 
  51              		.loc 1 174 11 is_stmt 0 view .LVU8
237 
  52 001e 1A68     		ldr	r2, [r3]
 237 
  52 001e 1A68     		ldr	r2, [r3]
238 
  53 0020 22F48022 		bic	r2, r2, #262144
 238 
  53 0020 22F48022 		bic	r2, r2, #262144
239 
  54 0024 1A60     		str	r2, [r3]
 239 
  54 0024 1A60     		str	r2, [r3]
240 
 175:Core/Src/system_stm32f1xx.c ****
240 
 175:Core/Src/system_stm32f1xx.c ****
241 
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ARM GAS  C:\Users\mike\AppData\Local\Temp\cc5OGnig.s 			page 5
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244 
 176:Core/Src/system_stm32f1xx.c ****   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
 244 
 176:Core/Src/system_stm32f1xx.c ****   /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
245 
 177:Core/Src/system_stm32f1xx.c ****   RCC->CFGR &= 0xFF80FFFFU;
 245 
 177:Core/Src/system_stm32f1xx.c ****   RCC->CFGR &= 0xFF80FFFFU;
246 
  55              		.loc 1 177 3 is_stmt 1 view .LVU9
 246 
  55              		.loc 1 177 3 is_stmt 1 view .LVU9
Line 296... Line 296...
296 
  72 003e 00BF     		.align	2
 296 
  72 003e 00BF     		.align	2
297 
  73              	.L2:
 297 
  73              	.L2:
298 
  74 0040 00100240 		.word	1073876992
 298 
  74 0040 00100240 		.word	1073876992
299 
  75 0044 0000FFF8 		.word	-117506048
 299 
  75 0044 0000FFF8 		.word	-117506048
300 
  76 0048 00ED00E0 		.word	-536810240
 300 
  76 0048 00ED00E0 		.word	-536810240
301 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 6
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304 
  77              		.cfi_endproc
 304 
  77              		.cfi_endproc
305 
  78              	.LFE65:
 305 
  78              	.LFE65:
306 
  80              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
 306 
  80              		.section	.text.SystemCoreClockUpdate,"ax",%progbits
Line 356... Line 356...
356 
  93              		@ frame_needed = 0, uses_anonymous_args = 0
 356 
  93              		@ frame_needed = 0, uses_anonymous_args = 0
357 
  94              		@ link register save eliminated.
 357 
  94              		@ link register save eliminated.
358 
 249:Core/Src/system_stm32f1xx.c ****   uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
 358 
 249:Core/Src/system_stm32f1xx.c ****   uint32_t tmp = 0U, pllmull = 0U, pllsource = 0U;
359 
  95              		.loc 1 249 3 view .LVU17
 359 
  95              		.loc 1 249 3 view .LVU17
360 
  96              	.LVL0:
 360 
  96              	.LVL0:
361 
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364 
 250:Core/Src/system_stm32f1xx.c ****
364 
 250:Core/Src/system_stm32f1xx.c ****
365 
 251:Core/Src/system_stm32f1xx.c **** #if defined(STM32F105xC) || defined(STM32F107xC)
 365 
 251:Core/Src/system_stm32f1xx.c **** #if defined(STM32F105xC) || defined(STM32F107xC)
366 
 252:Core/Src/system_stm32f1xx.c ****   uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
 366 
 252:Core/Src/system_stm32f1xx.c ****   uint32_t prediv1source = 0U, prediv1factor = 0U, prediv2factor = 0U, pll2mull = 0U;
Line 416... Line 416...
416 
 289:Core/Src/system_stm32f1xx.c ****        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
416 
 289:Core/Src/system_stm32f1xx.c ****        SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
417 
 290:Core/Src/system_stm32f1xx.c ****  #else
 417 
 290:Core/Src/system_stm32f1xx.c ****  #else
418 
 291:Core/Src/system_stm32f1xx.c ****         /* HSE selected as PLL clock entry */
 418 
 291:Core/Src/system_stm32f1xx.c ****         /* HSE selected as PLL clock entry */
419 
 292:Core/Src/system_stm32f1xx.c ****         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
 419 
 292:Core/Src/system_stm32f1xx.c ****         if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
420 
 293:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
 420 
 293:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
421 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 8
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 294:Core/Src/system_stm32f1xx.c ****           SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
 424 
 294:Core/Src/system_stm32f1xx.c ****           SystemCoreClock = (HSE_VALUE >> 1U) * pllmull;
425 
 295:Core/Src/system_stm32f1xx.c ****         }
 425 
 295:Core/Src/system_stm32f1xx.c ****         }
426 
 296:Core/Src/system_stm32f1xx.c ****         else
 426 
 296:Core/Src/system_stm32f1xx.c ****         else
Line 476... Line 476...
476 
 111              		.loc 1 344 23 is_stmt 0 view .LVU23
 476 
 111              		.loc 1 344 23 is_stmt 0 view .LVU23
477 
 112 0012 1C4B     		ldr	r3, .L12+4
 477 
 112 0012 1C4B     		ldr	r3, .L12+4
478 
 113              	.LVL2:
 478 
 113              	.LVL2:
479 
 114              		.loc 1 344 23 view .LVU24
 479 
 114              		.loc 1 344 23 view .LVU24
480 
 115 0014 1C4A     		ldr	r2, .L12+8
 480 
 115 0014 1C4A     		ldr	r2, .L12+8
481 
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483 
 
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484 
 116 0016 1A60     		str	r2, [r3]
 484 
 116 0016 1A60     		str	r2, [r3]
485 
 345:Core/Src/system_stm32f1xx.c ****       break;
 485 
 345:Core/Src/system_stm32f1xx.c ****       break;
486 
 117              		.loc 1 345 7 is_stmt 1 view .LVU25
 486 
 117              		.loc 1 345 7 is_stmt 1 view .LVU25
Line 536... Line 536...
536 
 153 0036 134B     		ldr	r3, .L12+4
 536 
 153 0036 134B     		ldr	r3, .L12+4
537 
 154              	.LVL8:
 537 
 154              	.LVL8:
538 
 268:Core/Src/system_stm32f1xx.c ****       break;
 538 
 268:Core/Src/system_stm32f1xx.c ****       break;
539 
 155              		.loc 1 268 23 view .LVU39
 539 
 155              		.loc 1 268 23 view .LVU39
540 
 156 0038 134A     		ldr	r2, .L12+8
 540 
 156 0038 134A     		ldr	r2, .L12+8
541 
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ARM GAS  C:\Users\mike\AppData\Local\Temp\cc5OGnig.s 			page 10
542 
 
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543 
 
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544 
 157 003a 1A60     		str	r2, [r3]
 544 
 157 003a 1A60     		str	r2, [r3]
545 
 269:Core/Src/system_stm32f1xx.c ****     case 0x08U:  /* PLL used as system clock */
 545 
 269:Core/Src/system_stm32f1xx.c ****     case 0x08U:  /* PLL used as system clock */
546 
 158              		.loc 1 269 7 is_stmt 1 view .LVU40
 546 
 158              		.loc 1 269 7 is_stmt 1 view .LVU40
Line 596... Line 596...
596 
 292:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
 596 
 292:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
597 
 195              		.loc 1 292 9 is_stmt 1 view .LVU54
 597 
 195              		.loc 1 292 9 is_stmt 1 view .LVU54
598 
 292:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
 598 
 292:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
599 
 196              		.loc 1 292 17 is_stmt 0 view .LVU55
 599 
 196              		.loc 1 292 17 is_stmt 0 view .LVU55
600 
 197 005c 084A     		ldr	r2, .L12
 600 
 197 005c 084A     		ldr	r2, .L12
601 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 11
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602 
 
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603 
 
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604 
 198              	.LVL17:
 604 
 198              	.LVL17:
605 
 292:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
 605 
 292:Core/Src/system_stm32f1xx.c ****         {/* HSE oscillator clock divided by 2 */
606 
 199              		.loc 1 292 17 view .LVU56
 606 
 199              		.loc 1 292 17 view .LVU56
Line 656... Line 656...
656 
 245              		.section	.rodata.AHBPrescTable,"a"
 656 
 245              		.section	.rodata.AHBPrescTable,"a"
657 
 246              		.align	2
 657 
 246              		.align	2
658 
 247              		.set	.LANCHOR1,. + 0
 658 
 247              		.set	.LANCHOR1,. + 0
659 
 250              	AHBPrescTable:
 659 
 250              	AHBPrescTable:
660 
 251 0000 00       		.byte	0
 660 
 251 0000 00       		.byte	0
661 
ARM GAS  C:\Users\mike\AppData\Local\Temp\cccJB4yd.s 			page 12
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ARM GAS  C:\Users\mike\AppData\Local\Temp\cc5OGnig.s 			page 12
662 
 
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663 
 
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664 
 252 0001 00       		.byte	0
 664 
 252 0001 00       		.byte	0
665 
 253 0002 00       		.byte	0
 665 
 253 0002 00       		.byte	0
666 
 254 0003 00       		.byte	0
 666 
 254 0003 00       		.byte	0
Line 694... Line 694...
694 
 284              		.file 4 "Drivers/CMSIS/Include/core_cm3.h"
 694 
 284              		.file 4 "Drivers/CMSIS/Include/core_cm3.h"
695 
 285              		.file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
 695 
 285              		.file 5 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
696 
 286              		.file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
 696 
 286              		.file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
697 
 287              		.file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
 697 
 287              		.file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
698 
 288              		.file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
 698 
 288              		.file 8 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
699 
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ARM GAS  C:\Users\mike\AppData\Local\Temp\cc5OGnig.s 			page 13
700 
 
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701 
 
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702 
DEFINED SYMBOLS
 702 
DEFINED SYMBOLS
703 
                            *ABS*:0000000000000000 system_stm32f1xx.c
 703 
                            *ABS*:0000000000000000 system_stm32f1xx.c
704 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:16     .text.SystemInit:0000000000000000 $t
 704 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:16     .text.SystemInit:0000000000000000 $t
705 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:24     .text.SystemInit:0000000000000000 SystemInit
 705 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:24     .text.SystemInit:0000000000000000 SystemInit
706 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:74     .text.SystemInit:0000000000000040 $d
 706 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:74     .text.SystemInit:0000000000000040 $d
707 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:81     .text.SystemCoreClockUpdate:0000000000000000 $t
 707 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:81     .text.SystemCoreClockUpdate:0000000000000000 $t
708 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:88     .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
 708 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:88     .text.SystemCoreClockUpdate:0000000000000000 SystemCoreClockUpdate
709 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:227    .text.SystemCoreClockUpdate:0000000000000080 $d
 709 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:227    .text.SystemCoreClockUpdate:0000000000000080 $d
710 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:271    .rodata.APBPrescTable:0000000000000000 APBPrescTable
 710 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:271    .rodata.APBPrescTable:0000000000000000 APBPrescTable
711 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:250    .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
 711 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:250    .rodata.AHBPrescTable:0000000000000000 AHBPrescTable
712 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:243    .data.SystemCoreClock:0000000000000000 SystemCoreClock
 712 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:243    .data.SystemCoreClock:0000000000000000 SystemCoreClock
713 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:239    .data.SystemCoreClock:0000000000000000 $d
 713 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:239    .data.SystemCoreClock:0000000000000000 $d
714 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:246    .rodata.AHBPrescTable:0000000000000000 $d
 714 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:246    .rodata.AHBPrescTable:0000000000000000 $d
715 
C:\Users\mike\AppData\Local\Temp\cccJB4yd.s:268    .rodata.APBPrescTable:0000000000000000 $d
 715 
C:\Users\mike\AppData\Local\Temp\cc5OGnig.s:268    .rodata.APBPrescTable:0000000000000000 $d
716 
 
 716 
 
717 
NO UNDEFINED SYMBOLS
 717 
NO UNDEFINED SYMBOLS