WebSVN – dashGPS – Diff – /branches/dashGPS-bmp/build/stm32f1xx_hal_pwr.lst



ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 1
 
 
   1              		.cpu cortex-m3
   2              		.eabi_attribute 20, 1
   3              		.eabi_attribute 21, 1

  29:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @addtogroup STM32F1xx_HAL_Driver
  30:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @{
  31:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   */
  32:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
  33:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR PWR
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 2
 
 
  34:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @brief    PWR HAL module driver
  35:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @{
  36:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   */

  86:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** #define CR_PVDE_BB               ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_
  87:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
  88:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
  89:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @}
  90:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   */
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 3
 
 
  91:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
  92:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
  93:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @{

  48              		.align	1
  49              		.global	HAL_PWR_DeInit
  50              		.syntax unified
  51              		.thumb
  52              		.thumb_func
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 4
 
 
  53              		.fpu softvfp
  55              	HAL_PWR_DeInit:
  56              	.LFB66:

  68 000a 1A69     		ldr	r2, [r3, #16]
  69 000c 22F08052 		bic	r2, r2, #268435456
  70 0010 1A61     		str	r2, [r3, #16]
 160:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
  71              		.loc 1 160 1 is_stmt 0 view .LVU7
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 5
 
 
  72 0012 7047     		bx	lr
  73              	.L4:
  74              		.align	2

 114              		.thumb_func
 115              		.fpu softvfp
 117              	HAL_PWR_DisableBkUpAccess:
 118              	.LFB68:
 174:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 6
 
 
 175:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
 176:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @brief  Disables access to the backup domain (RTC registers, RTC
 177:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   *         backup data registers).

 199:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****      
 200:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****     *** PVD configuration ***
 201:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****     =========================
 202:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****     [..]
 203:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****       (+) The PVD is used to monitor the VDD power supply by comparing it to a
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 7
 
 
 204:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****           threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
 205:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
 206:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****       (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower

 256:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
 257:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****       (+) Entry:
 258:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****            The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_REGULATOR_VALUE, PWR_SLEEPE
 259:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****              function with:
 260:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****           (++) PWR_REGULATOR_VALUE= PWR_MAINREGULATOR_ON: Main regulator ON.
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 8
 
 
 261:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****           (++) PWR_REGULATOR_VALUE= PWR_LOWPOWERREGULATOR_ON: Low Power regulator ON.
 262:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****           (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
 263:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****           (++) PWR_SLEEPENTRY_WFx= PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction

 313:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   *         detection level.
 314:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @retval None
 315:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   */
 316:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD)
 317:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 9
 
 
 149              		.loc 1 317 1 is_stmt 1 view -0
 150              		.cfi_startproc
 151              		@ args = 0, pretend = 0, frame = 0

 333:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   {
 334:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****     __HAL_PWR_PVD_EXTI_ENABLE_IT();
 186              		.loc 1 334 5 is_stmt 1 view .LVU27
 187 0038 114A     		ldr	r2, .L16+4
 188 003a 1368     		ldr	r3, [r2]
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 10
 
 
 189 003c 43F48033 		orr	r3, r3, #65536
 190 0040 1360     		str	r3, [r2]
 191              	.L12:

 224 0070 D368     		ldr	r3, [r2, #12]
 225 0072 43F48033 		orr	r3, r3, #65536
 226 0076 D360     		str	r3, [r2, #12]
 227              	.L11:
 352:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   }
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 11
 
 
 353:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
 228              		.loc 1 353 1 is_stmt 0 view .LVU40
 229 0078 7047     		bx	lr

 272              		.thumb_func
 273              		.fpu softvfp
 275              	HAL_PWR_DisablePVD:
 276              	.LFB71:
 364:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 12
 
 
 365:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
 366:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @brief  Disables the Power Voltage Detector(PVD).
 367:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @retval None

 384:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   /* Check the parameter */
 385:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
 312              		.loc 1 385 3 view .LVU50
 386:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   /* Enable the EWUPx pin */
 387:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 13
 
 
 313              		.loc 1 387 3 view .LVU51
 314              	.LBB6:
 315              	.LBI6:

  49:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __STATIC_FORCEINLINE                 
  50:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __STATIC_FORCEINLINE                   __attribute__((always_inline)) static inline
  51:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif                                           
  52:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __NO_RETURN
  53:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __NO_RETURN                            __attribute__((__noreturn__))
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 14
 
 
  54:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
  55:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __USED
  56:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __USED                                 __attribute__((used))

 106:Drivers/CMSIS/Include/cmsis_gcc.h ****   __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
 107:Drivers/CMSIS/Include/cmsis_gcc.h ****   #pragma GCC diagnostic pop
 108:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(add
 109:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 110:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __ALIGNED
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 15
 
 
 111:Drivers/CMSIS/Include/cmsis_gcc.h ****   #define __ALIGNED(x)                           __attribute__((aligned(x)))
 112:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 113:Drivers/CMSIS/Include/cmsis_gcc.h **** #ifndef   __RESTRICT

 163:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the content of the non-secure Control Register when in secure mode.
 164:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               non-secure Control Register value
 165:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 166:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void)
 167:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 16
 
 
 168:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 169:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 170:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, control_ns" : "=r" (result) );

 220:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 221:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 222:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 223:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, apsr" : "=r" (result) );
 224:Drivers/CMSIS/Include/cmsis_gcc.h ****   return(result);
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 17
 
 
 225:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 226:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 227:Drivers/CMSIS/Include/cmsis_gcc.h **** 

 277:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack)
 278:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 279:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
 280:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 281:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 18
 
 
 282:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 283:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 284:Drivers/CMSIS/Include/cmsis_gcc.h **** /**

 334:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 335:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 336:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 337:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 338:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 19
 
 
 339:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer (non-secure)
 340:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
 341:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    topOfMainStack  Main Stack Pointer value to set

 391:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 392:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 393:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Get Priority Mask (non-secure)
 394:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current state of the non-secure priority mask bit from the Priority Mask Reg
 395:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               Priority Mask value
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 20
 
 
 396:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 397:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
 398:Drivers/CMSIS/Include/cmsis_gcc.h **** {

 448:Drivers/CMSIS/Include/cmsis_gcc.h ****            Can only be executed in Privileged modes.
 449:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 450:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __disable_fault_irq(void)
 451:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 452:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("cpsid f" : : : "memory");
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 21
 
 
 453:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 454:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 455:Drivers/CMSIS/Include/cmsis_gcc.h **** 

 505:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
 506:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 507:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 508:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 509:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 22
 
 
 510:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 511:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Base Priority with condition
 512:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the Base Priority register only if BASEPRI masking is disable

 562:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 563:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
 564:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 565:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Fault Mask (non-secure)
 566:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Assigns the given value to the non-secure Fault Mask register when in secure state.
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 23
 
 
 567:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    faultMask  Fault Mask value to set
 568:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 569:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)

 619:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 620:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 621:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("MRS %0, psplim_ns"  : "=r" (result) );
 622:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
 623:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 24
 
 
 624:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 625:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 626:Drivers/CMSIS/Include/cmsis_gcc.h **** 

 676:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
 677:Drivers/CMSIS/Include/cmsis_gcc.h ****   \return               MSPLIM Register value
 678:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 679:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
 680:Drivers/CMSIS/Include/cmsis_gcc.h **** {
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 25
 
 
 681:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
 682:Drivers/CMSIS/Include/cmsis_gcc.h ****     (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
 683:Drivers/CMSIS/Include/cmsis_gcc.h ****   // without main extensions, the non-secure MSPLIM is RAZ/WI

 733:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 734:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 735:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 736:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 737:Drivers/CMSIS/Include/cmsis_gcc.h **** #if (defined (__ARM_FEATURE_CMSE  ) && (__ARM_FEATURE_CMSE   == 3))
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 26
 
 
 738:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 739:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Set Main Stack Pointer Limit (non-secure)
 740:Drivers/CMSIS/Include/cmsis_gcc.h ****   Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure

 790:Drivers/CMSIS/Include/cmsis_gcc.h ****   \param [in]    fpscr  Floating Point Status/Control value to set
 791:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 792:Drivers/CMSIS/Include/cmsis_gcc.h **** __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
 793:Drivers/CMSIS/Include/cmsis_gcc.h **** {
 794:Drivers/CMSIS/Include/cmsis_gcc.h **** #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 27
 
 
 795:Drivers/CMSIS/Include/cmsis_gcc.h ****      (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
 796:Drivers/CMSIS/Include/cmsis_gcc.h **** #if __has_builtin(__builtin_arm_set_fpscr)
 797:Drivers/CMSIS/Include/cmsis_gcc.h **** // Re-enable using built-in when GCC has been fixed

 847:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Wait For Event is a hint instruction that permits the processor to enter
 848:Drivers/CMSIS/Include/cmsis_gcc.h ****            a low-power state until one of a number of events occurs.
 849:Drivers/CMSIS/Include/cmsis_gcc.h ****  */
 850:Drivers/CMSIS/Include/cmsis_gcc.h **** #define __WFE()                             __ASM volatile ("wfe")
 851:Drivers/CMSIS/Include/cmsis_gcc.h **** 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 28
 
 
 852:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 853:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
 854:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Send Event

 904:Drivers/CMSIS/Include/cmsis_gcc.h **** #else
 905:Drivers/CMSIS/Include/cmsis_gcc.h ****   uint32_t result;
 906:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 907:Drivers/CMSIS/Include/cmsis_gcc.h ****   __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
 908:Drivers/CMSIS/Include/cmsis_gcc.h ****   return result;
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 29
 
 
 909:Drivers/CMSIS/Include/cmsis_gcc.h **** #endif
 910:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 911:Drivers/CMSIS/Include/cmsis_gcc.h **** 

 961:Drivers/CMSIS/Include/cmsis_gcc.h ****   return (op1 >> op2) | (op1 << (32U - op2));
 962:Drivers/CMSIS/Include/cmsis_gcc.h **** }
 963:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 964:Drivers/CMSIS/Include/cmsis_gcc.h **** 
 965:Drivers/CMSIS/Include/cmsis_gcc.h **** /**
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 30
 
 
 966:Drivers/CMSIS/Include/cmsis_gcc.h ****   \brief   Breakpoint
 967:Drivers/CMSIS/Include/cmsis_gcc.h ****   \details Causes the processor to enter Debug state.
 968:Drivers/CMSIS/Include/cmsis_gcc.h ****            Debug tools can use this to investigate system state when the instruction at a particula

 333 0004 B0FA80F0 		clz	r0, r0
 334 0008 024B     		ldr	r3, .L25
 335 000a 0344     		add	r3, r3, r0
 336 000c 9B00     		lsls	r3, r3, #2
 337              		.loc 1 387 46 view .LVU58
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 31
 
 
 338 000e 0122     		movs	r2, #1
 339 0010 1A60     		str	r2, [r3]
 388:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }

 374              	@ 988 "Drivers/CMSIS/Include/cmsis_gcc.h" 1
 375 0000 90FAA0F0 		rbit r0, r0
 376              	@ 0 "" 2
 377              	.LVL4:
 378              		.loc 2 1001 3 view .LVU66
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 32
 
 
 379              		.loc 2 1001 3 is_stmt 0 view .LVU67
 380              		.thumb
 381              		.syntax unified

 419:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   /* Check the parameters */
 420:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   /* No check on Regulator because parameter not used in SLEEP mode */
 421:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   /* Prevent unused argument(s) compilation warning */
 422:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   UNUSED(Regulator);
 417              		.loc 1 422 3 view .LVU72
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 33
 
 
 423:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
 424:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
 418              		.loc 1 424 3 view .LVU73

 449 0016 30BF     		wfi
 450              	@ 0 "" 2
 451              		.thumb
 452              		.syntax unified
 453 0018 7047     		bx	lr
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 34
 
 
 454              	.L35:
 455 001a 00BF     		.align	2
 456              	.L34:

 483              		.loc 1 467 3 view .LVU85
 468:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
 469:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   /* Clear PDDS bit in PWR register to specify entering in STOP mode when CPU enter in Deepsleep */
 470:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   CLEAR_BIT(PWR->CR,  PWR_CR_PDDS);
 484              		.loc 1 470 3 view .LVU86
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 35
 
 
 485 0002 0F4A     		ldr	r2, .L40
 486 0004 1368     		ldr	r3, [r2]
 487 0006 23F00203 		bic	r3, r3, #2

 515 0026 074A     		ldr	r2, .L40+4
 516 0028 1369     		ldr	r3, [r2, #16]
 517 002a 23F00403 		bic	r3, r3, #4
 518 002e 1361     		str	r3, [r2, #16]
 493:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 36
 
 
 519              		.loc 1 493 1 is_stmt 0 view .LVU94
 520 0030 08BD     		pop	{r3, pc}
 521              	.LVL9:

 559              		@ link register save eliminated.
 505:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   /* Select Standby mode */
 506:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   SET_BIT(PWR->CR, PWR_CR_PDDS);
 560              		.loc 1 506 3 view .LVU99
 561 0000 054A     		ldr	r2, .L43
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 37
 
 
 562 0002 1368     		ldr	r3, [r2]
 563 0004 43F00203 		orr	r3, r3, #2
 564 0008 1360     		str	r3, [r2]

 526:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @retval None
 527:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   */
 528:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** void HAL_PWR_EnableSleepOnExit(void)
 529:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** {
 597              		.loc 1 529 1 is_stmt 1 view -0
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 38
 
 
 598              		.cfi_startproc
 599              		@ args = 0, pretend = 0, frame = 0
 600              		@ frame_needed = 0, uses_anonymous_args = 0

 636              		.loc 1 545 1 is_stmt 0 view .LVU108
 637 000a 7047     		bx	lr
 638              	.L50:
 639              		.align	2
 640              	.L49:
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 39
 
 
 641 000c 00ED00E0 		.word	-536810240
 642              		.cfi_endproc
 643              	.LFE78:

 559:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
 560:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
 561:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
 562:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @brief Disables CORTEX M3 SEVONPEND bit. 
 563:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @note Clears SEVONPEND bit of SCR register. When this bit is set, this causes 
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 40
 
 
 564:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   *       WFE to wake up when an interrupt moves from inactive to pended.         
 565:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @retval None
 566:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   */

 589:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****     __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
 590:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   }
 591:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** }
 592:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
 593:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** /**
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 41
 
 
 594:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @brief  PWR PVD interrupt callback
 595:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   * @retval None
 596:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   */

 586:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c **** 
 753              		.loc 1 586 5 is_stmt 1 view .LVU122
 754 000e FFF7FEFF 		bl	HAL_PWR_PVDCallback
 755              	.LVL12:
 589:Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_pwr.c ****   }
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 42
 
 
 756              		.loc 1 589 5 view .LVU123
 757 0012 024B     		ldr	r3, .L62
 758 0014 4FF48032 		mov	r2, #65536

 774              		.file 6 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h"
 775              		.file 7 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f103xb.h"
 776              		.file 8 "Drivers/CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h"
 777              		.file 9 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal_pwr.h"
 778              		.file 10 "Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_hal.h"
ARM GAS  C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s 			page 43
 
 
DEFINED SYMBOLS
                            *ABS*:0000000000000000 stm32f1xx_hal_pwr.c
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:16     .text.PWR_OverloadWfe:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:23     .text.PWR_OverloadWfe:0000000000000000 PWR_OverloadWfe
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:48     .text.HAL_PWR_DeInit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:55     .text.HAL_PWR_DeInit:0000000000000000 HAL_PWR_DeInit
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:76     .text.HAL_PWR_DeInit:0000000000000014 $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:81     .text.HAL_PWR_EnableBkUpAccess:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:88     .text.HAL_PWR_EnableBkUpAccess:0000000000000000 HAL_PWR_EnableBkUpAccess
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:105    .text.HAL_PWR_EnableBkUpAccess:0000000000000008 $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:110    .text.HAL_PWR_DisableBkUpAccess:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:117    .text.HAL_PWR_DisableBkUpAccess:0000000000000000 HAL_PWR_DisableBkUpAccess
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:134    .text.HAL_PWR_DisableBkUpAccess:0000000000000008 $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:139    .text.HAL_PWR_ConfigPVD:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:146    .text.HAL_PWR_ConfigPVD:0000000000000000 HAL_PWR_ConfigPVD
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:233    .text.HAL_PWR_ConfigPVD:000000000000007c $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:239    .text.HAL_PWR_EnablePVD:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:246    .text.HAL_PWR_EnablePVD:0000000000000000 HAL_PWR_EnablePVD
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:263    .text.HAL_PWR_EnablePVD:0000000000000008 $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:268    .text.HAL_PWR_DisablePVD:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:275    .text.HAL_PWR_DisablePVD:0000000000000000 HAL_PWR_DisablePVD
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:292    .text.HAL_PWR_DisablePVD:0000000000000008 $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:297    .text.HAL_PWR_EnableWakeUpPin:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:304    .text.HAL_PWR_EnableWakeUpPin:0000000000000000 HAL_PWR_EnableWakeUpPin
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:345    .text.HAL_PWR_EnableWakeUpPin:0000000000000014 $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:350    .text.HAL_PWR_DisableWakeUpPin:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:357    .text.HAL_PWR_DisableWakeUpPin:0000000000000000 HAL_PWR_DisableWakeUpPin
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:397    .text.HAL_PWR_DisableWakeUpPin:0000000000000014 $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:402    .text.HAL_PWR_EnterSLEEPMode:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:409    .text.HAL_PWR_EnterSLEEPMode:0000000000000000 HAL_PWR_EnterSLEEPMode
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:457    .text.HAL_PWR_EnterSLEEPMode:000000000000001c $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:462    .text.HAL_PWR_EnterSTOPMode:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:469    .text.HAL_PWR_EnterSTOPMode:0000000000000000 HAL_PWR_EnterSTOPMode
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:540    .text.HAL_PWR_EnterSTOPMode:0000000000000040 $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:546    .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:553    .text.HAL_PWR_EnterSTANDBYMode:0000000000000000 HAL_PWR_EnterSTANDBYMode
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:582    .text.HAL_PWR_EnterSTANDBYMode:0000000000000018 $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:588    .text.HAL_PWR_EnableSleepOnExit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:595    .text.HAL_PWR_EnableSleepOnExit:0000000000000000 HAL_PWR_EnableSleepOnExit
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:612    .text.HAL_PWR_EnableSleepOnExit:000000000000000c $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:617    .text.HAL_PWR_DisableSleepOnExit:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:624    .text.HAL_PWR_DisableSleepOnExit:0000000000000000 HAL_PWR_DisableSleepOnExit
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:641    .text.HAL_PWR_DisableSleepOnExit:000000000000000c $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:646    .text.HAL_PWR_EnableSEVOnPend:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:653    .text.HAL_PWR_EnableSEVOnPend:0000000000000000 HAL_PWR_EnableSEVOnPend
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:670    .text.HAL_PWR_EnableSEVOnPend:000000000000000c $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:675    .text.HAL_PWR_DisableSEVOnPend:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:682    .text.HAL_PWR_DisableSEVOnPend:0000000000000000 HAL_PWR_DisableSEVOnPend
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:699    .text.HAL_PWR_DisableSEVOnPend:000000000000000c $d
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:704    .text.HAL_PWR_PVDCallback:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:711    .text.HAL_PWR_PVDCallback:0000000000000000 HAL_PWR_PVDCallback
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:724    .text.HAL_PWR_PVD_IRQHandler:0000000000000000 $t
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:731    .text.HAL_PWR_PVD_IRQHandler:0000000000000000 HAL_PWR_PVD_IRQHandler
C:\Users\mike\AppData\Local\Temp\ccrpc8aj.s:765    .text.HAL_PWR_PVD_IRQHandler:000000000000001c $d
 
NO UNDEFINED SYMBOLS
Subversion Repositories dashGPS

(root)/branches/dashGPS-bmp/build/stm32f1xx_hal_pwr.lst – Rev 18 → 19
