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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32l1xx_ll_tim.c |
3 | * @file stm32l1xx_ll_tim.c |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief TIM LL module driver. |
5 | * @brief TIM LL module driver. |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | #if defined(USE_FULL_LL_DRIVER) |
| 19 | #if defined(USE_FULL_LL_DRIVER) |
19 | |
| 20 | 20 | /* Includes ------------------------------------------------------------------*/ |
|
| 21 | /* Includes ------------------------------------------------------------------*/ |
21 | #include "stm32l1xx_ll_tim.h" |
| 22 | #include "stm32l1xx_ll_tim.h" |
22 | #include "stm32l1xx_ll_bus.h" |
| 23 | #include "stm32l1xx_ll_bus.h" |
23 | |
| 24 | 24 | #ifdef USE_FULL_ASSERT |
|
| 25 | #ifdef USE_FULL_ASSERT |
25 | #include "stm32_assert.h" |
| 26 | #include "stm32_assert.h" |
26 | #else |
| 27 | #else |
27 | #define assert_param(expr) ((void)0U) |
| 28 | #define assert_param(expr) ((void)0U) |
28 | #endif /* USE_FULL_ASSERT */ |
| 29 | #endif /* USE_FULL_ASSERT */ |
29 | |
| 30 | 30 | /** @addtogroup STM32L1xx_LL_Driver |
|
| 31 | /** @addtogroup STM32L1xx_LL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | #if defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM6) || defined (TIM7) |
|
| 35 | #if defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM6) || defined (TIM7) |
35 | |
| 36 | 36 | /** @addtogroup TIM_LL |
|
| 37 | /** @addtogroup TIM_LL |
37 | * @{ |
| 38 | * @{ |
38 | */ |
| 39 | */ |
39 | |
| 40 | 40 | /* Private types -------------------------------------------------------------*/ |
|
| 41 | /* Private types -------------------------------------------------------------*/ |
41 | /* Private variables ---------------------------------------------------------*/ |
| 42 | /* Private variables ---------------------------------------------------------*/ |
42 | /* Private constants ---------------------------------------------------------*/ |
| 43 | /* Private constants ---------------------------------------------------------*/ |
43 | /* Private macros ------------------------------------------------------------*/ |
| 44 | /* Private macros ------------------------------------------------------------*/ |
44 | /** @addtogroup TIM_LL_Private_Macros |
| 45 | /** @addtogroup TIM_LL_Private_Macros |
45 | * @{ |
| 46 | * @{ |
46 | */ |
| 47 | */ |
47 | #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ |
| 48 | #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ |
48 | || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ |
| 49 | || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ |
49 | || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ |
| 50 | || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ |
50 | || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ |
| 51 | || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ |
51 | || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) |
| 52 | || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) |
52 | |
| 53 | 53 | #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ |
|
| 54 | #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ |
54 | || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ |
| 55 | || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ |
55 | || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) |
| 56 | || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) |
56 | |
| 57 | 57 | #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ |
|
| 58 | #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ |
58 | || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ |
| 59 | || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ |
59 | || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ |
| 60 | || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ |
60 | || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ |
| 61 | || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ |
61 | || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ |
| 62 | || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ |
62 | || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ |
| 63 | || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ |
63 | || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ |
| 64 | || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ |
64 | || ((__VALUE__) == LL_TIM_OCMODE_PWM2)) |
| 65 | || ((__VALUE__) == LL_TIM_OCMODE_PWM2)) |
65 | |
| 66 | 66 | #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ |
|
| 67 | #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ |
67 | || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) |
| 68 | || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) |
68 | |
| 69 | 69 | #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ |
|
| 70 | #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ |
70 | || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) |
| 71 | || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) |
71 | |
| 72 | 72 | #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ |
|
| 73 | #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ |
73 | || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ |
| 74 | || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ |
74 | || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) |
| 75 | || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) |
75 | |
| 76 | 76 | #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ |
|
| 77 | #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ |
77 | || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ |
| 78 | || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ |
78 | || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ |
| 79 | || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ |
79 | || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) |
| 80 | || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) |
80 | |
| 81 | 81 | #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ |
|
| 82 | #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ |
82 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ |
| 83 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ |
83 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ |
| 84 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ |
84 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ |
| 85 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ |
85 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ |
| 86 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ |
86 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ |
| 87 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ |
87 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ |
| 88 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ |
88 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ |
| 89 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ |
89 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ |
| 90 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ |
90 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ |
| 91 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ |
91 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ |
| 92 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ |
92 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ |
| 93 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ |
93 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ |
| 94 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ |
94 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ |
| 95 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ |
95 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ |
| 96 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ |
96 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) |
| 97 | || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) |
97 | |
| 98 | 98 | #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ |
|
| 99 | #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ |
99 | || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ |
| 100 | || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ |
100 | || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) |
| 101 | || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) |
101 | |
| 102 | 102 | #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ |
|
| 103 | #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ |
103 | || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ |
| 104 | || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ |
104 | || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) |
| 105 | || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) |
105 | |
| 106 | 106 | #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ |
|
| 107 | #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ |
107 | || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) |
| 108 | || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) |
108 | /** |
| 109 | /** |
109 | * @} |
| 110 | * @} |
110 | */ |
| 111 | */ |
111 | |
| 112 | 112 | ||
| 113 | 113 | /* Private function prototypes -----------------------------------------------*/ |
|
| 114 | /* Private function prototypes -----------------------------------------------*/ |
114 | /** @defgroup TIM_LL_Private_Functions TIM Private Functions |
| 115 | /** @defgroup TIM_LL_Private_Functions TIM Private Functions |
115 | * @{ |
| 116 | * @{ |
116 | */ |
| 117 | */ |
117 | static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); |
| 118 | static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); |
118 | static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); |
| 119 | static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); |
119 | static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); |
| 120 | static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); |
120 | static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); |
| 121 | static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); |
121 | static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
| 122 | static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
122 | static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
| 123 | static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
123 | static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
| 124 | static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
124 | static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
| 125 | static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); |
125 | /** |
| 126 | /** |
126 | * @} |
| 127 | * @} |
127 | */ |
| 128 | */ |
128 | |
| 129 | 129 | /* Exported functions --------------------------------------------------------*/ |
|
| 130 | /* Exported functions --------------------------------------------------------*/ |
130 | /** @addtogroup TIM_LL_Exported_Functions |
| 131 | /** @addtogroup TIM_LL_Exported_Functions |
131 | * @{ |
| 132 | * @{ |
132 | */ |
| 133 | */ |
133 | |
| 134 | 134 | /** @addtogroup TIM_LL_EF_Init |
|
| 135 | /** @addtogroup TIM_LL_EF_Init |
135 | * @{ |
| 136 | * @{ |
136 | */ |
| 137 | */ |
137 | |
| 138 | 138 | /** |
|
| 139 | /** |
139 | * @brief Set TIMx registers to their reset values. |
| 140 | * @brief Set TIMx registers to their reset values. |
140 | * @param TIMx Timer instance |
| 141 | * @param TIMx Timer instance |
141 | * @retval An ErrorStatus enumeration value: |
| 142 | * @retval An ErrorStatus enumeration value: |
142 | * - SUCCESS: TIMx registers are de-initialized |
| 143 | * - SUCCESS: TIMx registers are de-initialized |
143 | * - ERROR: invalid TIMx instance |
| 144 | * - ERROR: invalid TIMx instance |
144 | */ |
| 145 | */ |
145 | ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx) |
| 146 | ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) |
146 | { |
| 147 | { |
147 | ErrorStatus result = SUCCESS; |
| 148 | ErrorStatus result = SUCCESS; |
148 | |
| 149 | 149 | /* Check the parameters */ |
|
| 150 | /* Check the parameters */ |
150 | assert_param(IS_TIM_INSTANCE(TIMx)); |
| 151 | assert_param(IS_TIM_INSTANCE(TIMx)); |
151 | |
| 152 | 152 | if (TIMx == TIM2) |
|
| 153 | if (TIMx == TIM2) |
153 | { |
| 154 | { |
154 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); |
| 155 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); |
155 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); |
| 156 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); |
156 | } |
| 157 | } |
157 | #if defined(TIM3) |
| 158 | #if defined(TIM3) |
158 | else if (TIMx == TIM3) |
| 159 | else if (TIMx == TIM3) |
159 | { |
| 160 | { |
160 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); |
| 161 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); |
161 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); |
| 162 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); |
162 | } |
| 163 | } |
163 | #endif /* TIM3 */ |
| 164 | #endif /* TIM3 */ |
164 | #if defined(TIM4) |
| 165 | #if defined(TIM4) |
165 | else if (TIMx == TIM4) |
| 166 | else if (TIMx == TIM4) |
166 | { |
| 167 | { |
167 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); |
| 168 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); |
168 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); |
| 169 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); |
169 | } |
| 170 | } |
170 | #endif /* TIM4 */ |
| 171 | #endif /* TIM4 */ |
171 | #if defined(TIM5) |
| 172 | #if defined(TIM5) |
172 | else if (TIMx == TIM5) |
| 173 | else if (TIMx == TIM5) |
173 | { |
| 174 | { |
174 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); |
| 175 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); |
175 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); |
| 176 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); |
176 | } |
| 177 | } |
177 | #endif /* TIM5 */ |
| 178 | #endif /* TIM5 */ |
178 | #if defined(TIM6) |
| 179 | #if defined(TIM6) |
179 | else if (TIMx == TIM6) |
| 180 | else if (TIMx == TIM6) |
180 | { |
| 181 | { |
181 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); |
| 182 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); |
182 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); |
| 183 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); |
183 | } |
| 184 | } |
184 | #endif /* TIM6 */ |
| 185 | #endif /* TIM6 */ |
185 | #if defined(TIM7) |
| 186 | #if defined(TIM7) |
186 | else if (TIMx == TIM7) |
| 187 | else if (TIMx == TIM7) |
187 | { |
| 188 | { |
188 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); |
| 189 | LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); |
189 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); |
| 190 | LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); |
190 | } |
| 191 | } |
191 | #endif /* TIM7 */ |
| 192 | #endif /* TIM7 */ |
192 | #if defined(TIM9) |
| 193 | #if defined(TIM9) |
193 | else if (TIMx == TIM9) |
| 194 | else if (TIMx == TIM9) |
194 | { |
| 195 | { |
195 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9); |
| 196 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9); |
196 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9); |
| 197 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9); |
197 | } |
| 198 | } |
198 | #endif /* TIM9 */ |
| 199 | #endif /* TIM9 */ |
199 | #if defined(TIM10) |
| 200 | #if defined(TIM10) |
200 | else if (TIMx == TIM10) |
| 201 | else if (TIMx == TIM10) |
201 | { |
| 202 | { |
202 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10); |
| 203 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10); |
203 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10); |
| 204 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10); |
204 | } |
| 205 | } |
205 | #endif /* TIM10 */ |
| 206 | #endif /* TIM10 */ |
206 | #if defined(TIM11) |
| 207 | #if defined(TIM11) |
207 | else if (TIMx == TIM11) |
| 208 | else if (TIMx == TIM11) |
208 | { |
| 209 | { |
209 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11); |
| 210 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11); |
210 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11); |
| 211 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11); |
211 | } |
| 212 | } |
212 | #endif /* TIM11 */ |
| 213 | #endif /* TIM11 */ |
213 | else |
| 214 | else |
214 | { |
| 215 | { |
215 | result = ERROR; |
| 216 | result = ERROR; |
216 | } |
| 217 | } |
217 | |
| 218 | 218 | return result; |
|
| 219 | return result; |
219 | } |
| 220 | } |
220 | |
| 221 | 221 | /** |
|
| 222 | /** |
222 | * @brief Set the fields of the time base unit configuration data structure |
| 223 | * @brief Set the fields of the time base unit configuration data structure |
223 | * to their default values. |
| 224 | * to their default values. |
224 | * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) |
| 225 | * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) |
225 | * @retval None |
| 226 | * @retval None |
226 | */ |
| 227 | */ |
227 | void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) |
| 228 | void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) |
228 | { |
| 229 | { |
229 | /* Set the default configuration */ |
| 230 | /* Set the default configuration */ |
230 | TIM_InitStruct->Prescaler = (uint16_t)0x0000; |
| 231 | TIM_InitStruct->Prescaler = (uint16_t)0x0000; |
231 | TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; |
| 232 | TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; |
232 | TIM_InitStruct->Autoreload = 0xFFFFFFFFU; |
| 233 | TIM_InitStruct->Autoreload = 0xFFFFFFFFU; |
233 | TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; |
| 234 | TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; |
234 | } |
| 235 | } |
235 | |
| 236 | 236 | /** |
|
| 237 | /** |
237 | * @brief Configure the TIMx time base unit. |
| 238 | * @brief Configure the TIMx time base unit. |
238 | * @param TIMx Timer Instance |
| 239 | * @param TIMx Timer Instance |
239 | * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure |
| 240 | * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure |
240 | * (TIMx time base unit configuration data structure) |
| 241 | * (TIMx time base unit configuration data structure) |
241 | * @retval An ErrorStatus enumeration value: |
| 242 | * @retval An ErrorStatus enumeration value: |
242 | * - SUCCESS: TIMx registers are de-initialized |
| 243 | * - SUCCESS: TIMx registers are de-initialized |
243 | * - ERROR: not applicable |
| 244 | * - ERROR: not applicable |
244 | */ |
| 245 | */ |
245 | ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct) |
| 246 | ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) |
246 | { |
| 247 | { |
247 | uint32_t tmpcr1; |
| 248 | uint32_t tmpcr1; |
248 | |
| 249 | 249 | /* Check the parameters */ |
|
| 250 | /* Check the parameters */ |
250 | assert_param(IS_TIM_INSTANCE(TIMx)); |
| 251 | assert_param(IS_TIM_INSTANCE(TIMx)); |
251 | assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); |
| 252 | assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); |
252 | assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); |
| 253 | assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); |
253 | |
| 254 | 254 | tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); |
|
| 255 | tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); |
255 | |
| 256 | 256 | if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) |
|
| 257 | if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) |
257 | { |
| 258 | { |
258 | /* Select the Counter Mode */ |
| 259 | /* Select the Counter Mode */ |
259 | MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); |
| 260 | MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); |
260 | } |
| 261 | } |
261 | |
| 262 | 262 | if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) |
|
| 263 | if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) |
263 | { |
| 264 | { |
264 | /* Set the clock division */ |
| 265 | /* Set the clock division */ |
265 | MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); |
| 266 | MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); |
266 | } |
| 267 | } |
267 | |
| 268 | 268 | /* Write to TIMx CR1 */ |
|
| 269 | /* Write to TIMx CR1 */ |
269 | LL_TIM_WriteReg(TIMx, CR1, tmpcr1); |
| 270 | LL_TIM_WriteReg(TIMx, CR1, tmpcr1); |
270 | |
| 271 | 271 | /* Set the Autoreload value */ |
|
| 272 | /* Set the Autoreload value */ |
272 | LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); |
| 273 | LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); |
273 | |
| 274 | 274 | /* Set the Prescaler value */ |
|
| 275 | /* Set the Prescaler value */ |
275 | LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); |
| 276 | LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); |
276 | /* Generate an update event to reload the Prescaler |
| 277 | /* Generate an update event to reload the Prescaler |
277 | and the repetition counter value (if applicable) immediately */ |
| 278 | and the repetition counter value (if applicable) immediately */ |
278 | LL_TIM_GenerateEvent_UPDATE(TIMx); |
| 279 | LL_TIM_GenerateEvent_UPDATE(TIMx); |
279 | |
| 280 | 280 | return SUCCESS; |
|
| 281 | return SUCCESS; |
281 | } |
| 282 | } |
282 | |
| 283 | 283 | /** |
|
| 284 | /** |
284 | * @brief Set the fields of the TIMx output channel configuration data |
| 285 | * @brief Set the fields of the TIMx output channel configuration data |
285 | * structure to their default values. |
| 286 | * structure to their default values. |
286 | * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure |
| 287 | * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure |
287 | * (the output channel configuration data structure) |
| 288 | * (the output channel configuration data structure) |
288 | * @retval None |
| 289 | * @retval None |
289 | */ |
| 290 | */ |
290 | void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) |
| 291 | void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) |
291 | { |
| 292 | { |
292 | /* Set the default configuration */ |
| 293 | /* Set the default configuration */ |
293 | TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; |
| 294 | TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; |
294 | TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; |
| 295 | TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; |
295 | TIM_OC_InitStruct->CompareValue = 0x00000000U; |
| 296 | TIM_OC_InitStruct->CompareValue = 0x00000000U; |
296 | TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; |
| 297 | TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; |
297 | } |
| 298 | } |
298 | |
| 299 | 299 | /** |
|
| 300 | /** |
300 | * @brief Configure the TIMx output channel. |
| 301 | * @brief Configure the TIMx output channel. |
301 | * @param TIMx Timer Instance |
| 302 | * @param TIMx Timer Instance |
302 | * @param Channel This parameter can be one of the following values: |
| 303 | * @param Channel This parameter can be one of the following values: |
303 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 304 | * @arg @ref LL_TIM_CHANNEL_CH1 |
304 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 305 | * @arg @ref LL_TIM_CHANNEL_CH2 |
305 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 306 | * @arg @ref LL_TIM_CHANNEL_CH3 |
306 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 307 | * @arg @ref LL_TIM_CHANNEL_CH4 |
307 | * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration |
| 308 | * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration |
308 | * data structure) |
| 309 | * data structure) |
309 | * @retval An ErrorStatus enumeration value: |
| 310 | * @retval An ErrorStatus enumeration value: |
310 | * - SUCCESS: TIMx output channel is initialized |
| 311 | * - SUCCESS: TIMx output channel is initialized |
311 | * - ERROR: TIMx output channel is not initialized |
| 312 | * - ERROR: TIMx output channel is not initialized |
312 | */ |
| 313 | */ |
313 | ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) |
| 314 | ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) |
314 | { |
| 315 | { |
315 | ErrorStatus result = ERROR; |
| 316 | ErrorStatus result = ERROR; |
316 | |
| 317 | 317 | switch (Channel) |
|
| 318 | switch (Channel) |
318 | { |
| 319 | { |
319 | case LL_TIM_CHANNEL_CH1: |
| 320 | case LL_TIM_CHANNEL_CH1: |
320 | result = OC1Config(TIMx, TIM_OC_InitStruct); |
| 321 | result = OC1Config(TIMx, TIM_OC_InitStruct); |
321 | break; |
| 322 | break; |
322 | case LL_TIM_CHANNEL_CH2: |
| 323 | case LL_TIM_CHANNEL_CH2: |
323 | result = OC2Config(TIMx, TIM_OC_InitStruct); |
| 324 | result = OC2Config(TIMx, TIM_OC_InitStruct); |
324 | break; |
| 325 | break; |
325 | case LL_TIM_CHANNEL_CH3: |
| 326 | case LL_TIM_CHANNEL_CH3: |
326 | result = OC3Config(TIMx, TIM_OC_InitStruct); |
| 327 | result = OC3Config(TIMx, TIM_OC_InitStruct); |
327 | break; |
| 328 | break; |
328 | case LL_TIM_CHANNEL_CH4: |
| 329 | case LL_TIM_CHANNEL_CH4: |
329 | result = OC4Config(TIMx, TIM_OC_InitStruct); |
| 330 | result = OC4Config(TIMx, TIM_OC_InitStruct); |
330 | break; |
| 331 | break; |
331 | default: |
| 332 | default: |
332 | break; |
| 333 | break; |
333 | } |
| 334 | } |
334 | |
| 335 | 335 | return result; |
|
| 336 | return result; |
336 | } |
| 337 | } |
337 | |
| 338 | 338 | /** |
|
| 339 | /** |
339 | * @brief Set the fields of the TIMx input channel configuration data |
| 340 | * @brief Set the fields of the TIMx input channel configuration data |
340 | * structure to their default values. |
| 341 | * structure to their default values. |
341 | * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration |
| 342 | * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration |
342 | * data structure) |
| 343 | * data structure) |
343 | * @retval None |
| 344 | * @retval None |
344 | */ |
| 345 | */ |
345 | void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) |
| 346 | void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) |
346 | { |
| 347 | { |
347 | /* Set the default configuration */ |
| 348 | /* Set the default configuration */ |
348 | TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; |
| 349 | TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; |
349 | TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; |
| 350 | TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; |
350 | TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; |
| 351 | TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; |
351 | TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; |
| 352 | TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; |
352 | } |
| 353 | } |
353 | |
| 354 | 354 | /** |
|
| 355 | /** |
355 | * @brief Configure the TIMx input channel. |
| 356 | * @brief Configure the TIMx input channel. |
356 | * @param TIMx Timer Instance |
| 357 | * @param TIMx Timer Instance |
357 | * @param Channel This parameter can be one of the following values: |
| 358 | * @param Channel This parameter can be one of the following values: |
358 | * @arg @ref LL_TIM_CHANNEL_CH1 |
| 359 | * @arg @ref LL_TIM_CHANNEL_CH1 |
359 | * @arg @ref LL_TIM_CHANNEL_CH2 |
| 360 | * @arg @ref LL_TIM_CHANNEL_CH2 |
360 | * @arg @ref LL_TIM_CHANNEL_CH3 |
| 361 | * @arg @ref LL_TIM_CHANNEL_CH3 |
361 | * @arg @ref LL_TIM_CHANNEL_CH4 |
| 362 | * @arg @ref LL_TIM_CHANNEL_CH4 |
362 | * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data |
| 363 | * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data |
363 | * structure) |
| 364 | * structure) |
364 | * @retval An ErrorStatus enumeration value: |
| 365 | * @retval An ErrorStatus enumeration value: |
365 | * - SUCCESS: TIMx output channel is initialized |
| 366 | * - SUCCESS: TIMx output channel is initialized |
366 | * - ERROR: TIMx output channel is not initialized |
| 367 | * - ERROR: TIMx output channel is not initialized |
367 | */ |
| 368 | */ |
368 | ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) |
| 369 | ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) |
369 | { |
| 370 | { |
370 | ErrorStatus result = ERROR; |
| 371 | ErrorStatus result = ERROR; |
371 | |
| 372 | 372 | switch (Channel) |
|
| 373 | switch (Channel) |
373 | { |
| 374 | { |
374 | case LL_TIM_CHANNEL_CH1: |
| 375 | case LL_TIM_CHANNEL_CH1: |
375 | result = IC1Config(TIMx, TIM_IC_InitStruct); |
| 376 | result = IC1Config(TIMx, TIM_IC_InitStruct); |
376 | break; |
| 377 | break; |
377 | case LL_TIM_CHANNEL_CH2: |
| 378 | case LL_TIM_CHANNEL_CH2: |
378 | result = IC2Config(TIMx, TIM_IC_InitStruct); |
| 379 | result = IC2Config(TIMx, TIM_IC_InitStruct); |
379 | break; |
| 380 | break; |
380 | case LL_TIM_CHANNEL_CH3: |
| 381 | case LL_TIM_CHANNEL_CH3: |
381 | result = IC3Config(TIMx, TIM_IC_InitStruct); |
| 382 | result = IC3Config(TIMx, TIM_IC_InitStruct); |
382 | break; |
| 383 | break; |
383 | case LL_TIM_CHANNEL_CH4: |
| 384 | case LL_TIM_CHANNEL_CH4: |
384 | result = IC4Config(TIMx, TIM_IC_InitStruct); |
| 385 | result = IC4Config(TIMx, TIM_IC_InitStruct); |
385 | break; |
| 386 | break; |
386 | default: |
| 387 | default: |
387 | break; |
| 388 | break; |
388 | } |
| 389 | } |
389 | |
| 390 | 390 | return result; |
|
| 391 | return result; |
391 | } |
| 392 | } |
392 | |
| 393 | 393 | /** |
|
| 394 | /** |
394 | * @brief Fills each TIM_EncoderInitStruct field with its default value |
| 395 | * @brief Fills each TIM_EncoderInitStruct field with its default value |
395 | * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface |
| 396 | * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface |
396 | * configuration data structure) |
| 397 | * configuration data structure) |
397 | * @retval None |
| 398 | * @retval None |
398 | */ |
| 399 | */ |
399 | void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) |
| 400 | void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) |
400 | { |
| 401 | { |
401 | /* Set the default configuration */ |
| 402 | /* Set the default configuration */ |
402 | TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; |
| 403 | TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; |
403 | TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; |
| 404 | TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; |
404 | TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; |
| 405 | TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; |
405 | TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; |
| 406 | TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; |
406 | TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; |
| 407 | TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; |
407 | TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; |
| 408 | TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; |
408 | TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; |
| 409 | TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; |
409 | TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; |
| 410 | TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; |
410 | TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; |
| 411 | TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; |
411 | } |
| 412 | } |
412 | |
| 413 | 413 | /** |
|
| 414 | /** |
414 | * @brief Configure the encoder interface of the timer instance. |
| 415 | * @brief Configure the encoder interface of the timer instance. |
415 | * @param TIMx Timer Instance |
| 416 | * @param TIMx Timer Instance |
416 | * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface |
| 417 | * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface |
417 | * configuration data structure) |
| 418 | * configuration data structure) |
418 | * @retval An ErrorStatus enumeration value: |
| 419 | * @retval An ErrorStatus enumeration value: |
419 | * - SUCCESS: TIMx registers are de-initialized |
| 420 | * - SUCCESS: TIMx registers are de-initialized |
420 | * - ERROR: not applicable |
| 421 | * - ERROR: not applicable |
421 | */ |
| 422 | */ |
422 | ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) |
| 423 | ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) |
423 | { |
| 424 | { |
424 | uint32_t tmpccmr1; |
| 425 | uint32_t tmpccmr1; |
425 | uint32_t tmpccer; |
| 426 | uint32_t tmpccer; |
426 | |
| 427 | 427 | /* Check the parameters */ |
|
| 428 | /* Check the parameters */ |
428 | assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); |
| 429 | assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); |
429 | assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); |
| 430 | assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); |
430 | assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); |
| 431 | assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); |
431 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); |
| 432 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); |
432 | assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); |
| 433 | assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); |
433 | assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); |
| 434 | assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); |
434 | assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); |
| 435 | assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); |
435 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); |
| 436 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); |
436 | assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); |
| 437 | assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); |
437 | assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); |
| 438 | assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); |
438 | |
| 439 | 439 | /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ |
|
| 440 | /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ |
440 | TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); |
| 441 | TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); |
441 | |
| 442 | 442 | /* Get the TIMx CCMR1 register value */ |
|
| 443 | /* Get the TIMx CCMR1 register value */ |
443 | tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); |
| 444 | tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); |
444 | |
| 445 | 445 | /* Get the TIMx CCER register value */ |
|
| 446 | /* Get the TIMx CCER register value */ |
446 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| 447 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
447 | |
| 448 | 448 | /* Configure TI1 */ |
|
| 449 | /* Configure TI1 */ |
449 | tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); |
| 450 | tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); |
450 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); |
| 451 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); |
451 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); |
| 452 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); |
452 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); |
| 453 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); |
453 | |
| 454 | 454 | /* Configure TI2 */ |
|
| 455 | /* Configure TI2 */ |
455 | tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); |
| 456 | tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); |
456 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); |
| 457 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); |
457 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); |
| 458 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); |
458 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); |
| 459 | tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); |
459 | |
| 460 | 460 | /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ |
|
| 461 | /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ |
461 | tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); |
| 462 | tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); |
462 | tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); |
| 463 | tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); |
463 | tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); |
| 464 | tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); |
464 | tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); |
| 465 | tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); |
465 | |
| 466 | 466 | /* Set encoder mode */ |
|
| 467 | /* Set encoder mode */ |
467 | LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); |
| 468 | LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); |
468 | |
| 469 | 469 | /* Write to TIMx CCMR1 */ |
|
| 470 | /* Write to TIMx CCMR1 */ |
470 | LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); |
| 471 | LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); |
471 | |
| 472 | 472 | /* Write to TIMx CCER */ |
|
| 473 | /* Write to TIMx CCER */ |
473 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| 474 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
474 | |
| 475 | 475 | return SUCCESS; |
|
| 476 | return SUCCESS; |
476 | } |
| 477 | } |
477 | |
| 478 | 478 | /** |
|
| 479 | /** |
479 | * @} |
| 480 | * @} |
480 | */ |
| 481 | */ |
481 | |
| 482 | 482 | /** |
|
| 483 | /** |
483 | * @} |
| 484 | * @} |
484 | */ |
| 485 | */ |
485 | |
| 486 | 486 | /** @addtogroup TIM_LL_Private_Functions TIM Private Functions |
|
| 487 | /** @addtogroup TIM_LL_Private_Functions TIM Private Functions |
487 | * @brief Private functions |
| 488 | * @brief Private functions |
488 | * @{ |
| 489 | * @{ |
489 | */ |
| 490 | */ |
490 | /** |
| 491 | /** |
491 | * @brief Configure the TIMx output channel 1. |
| 492 | * @brief Configure the TIMx output channel 1. |
492 | * @param TIMx Timer Instance |
| 493 | * @param TIMx Timer Instance |
493 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure |
| 494 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure |
494 | * @retval An ErrorStatus enumeration value: |
| 495 | * @retval An ErrorStatus enumeration value: |
495 | * - SUCCESS: TIMx registers are de-initialized |
| 496 | * - SUCCESS: TIMx registers are de-initialized |
496 | * - ERROR: not applicable |
| 497 | * - ERROR: not applicable |
497 | */ |
| 498 | */ |
498 | static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) |
| 499 | static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) |
499 | { |
| 500 | { |
500 | uint32_t tmpccmr1; |
| 501 | uint32_t tmpccmr1; |
501 | uint32_t tmpccer; |
| 502 | uint32_t tmpccer; |
502 | uint32_t tmpcr2; |
| 503 | uint32_t tmpcr2; |
503 | |
| 504 | 504 | /* Check the parameters */ |
|
| 505 | /* Check the parameters */ |
505 | assert_param(IS_TIM_CC1_INSTANCE(TIMx)); |
| 506 | assert_param(IS_TIM_CC1_INSTANCE(TIMx)); |
506 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
| 507 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
507 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
| 508 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
508 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
| 509 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
509 | |
| 510 | 510 | /* Disable the Channel 1: Reset the CC1E Bit */ |
|
| 511 | /* Disable the Channel 1: Reset the CC1E Bit */ |
511 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); |
| 512 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); |
512 | |
| 513 | 513 | /* Get the TIMx CCER register value */ |
|
| 514 | /* Get the TIMx CCER register value */ |
514 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| 515 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
515 | |
| 516 | 516 | /* Get the TIMx CR2 register value */ |
|
| 517 | /* Get the TIMx CR2 register value */ |
517 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
| 518 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
518 | |
| 519 | 519 | /* Get the TIMx CCMR1 register value */ |
|
| 520 | /* Get the TIMx CCMR1 register value */ |
520 | tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); |
| 521 | tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); |
521 | |
| 522 | 522 | /* Reset Capture/Compare selection Bits */ |
|
| 523 | /* Reset Capture/Compare selection Bits */ |
523 | CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); |
| 524 | CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); |
524 | |
| 525 | 525 | /* Set the Output Compare Mode */ |
|
| 526 | /* Set the Output Compare Mode */ |
526 | MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); |
| 527 | MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); |
527 | |
| 528 | 528 | /* Set the Output Compare Polarity */ |
|
| 529 | /* Set the Output Compare Polarity */ |
529 | MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); |
| 530 | MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); |
530 | |
| 531 | 531 | /* Set the Output State */ |
|
| 532 | /* Set the Output State */ |
532 | MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); |
| 533 | MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); |
533 | |
| 534 | 534 | /* Write to TIMx CR2 */ |
|
| 535 | /* Write to TIMx CR2 */ |
535 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
| 536 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
536 | |
| 537 | 537 | /* Write to TIMx CCMR1 */ |
|
| 538 | /* Write to TIMx CCMR1 */ |
538 | LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); |
| 539 | LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); |
539 | |
| 540 | 540 | /* Set the Capture Compare Register value */ |
|
| 541 | /* Set the Capture Compare Register value */ |
541 | LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); |
| 542 | LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); |
542 | |
| 543 | 543 | /* Write to TIMx CCER */ |
|
| 544 | /* Write to TIMx CCER */ |
544 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| 545 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
545 | |
| 546 | 546 | return SUCCESS; |
|
| 547 | return SUCCESS; |
547 | } |
| 548 | } |
548 | |
| 549 | 549 | /** |
|
| 550 | /** |
550 | * @brief Configure the TIMx output channel 2. |
| 551 | * @brief Configure the TIMx output channel 2. |
551 | * @param TIMx Timer Instance |
| 552 | * @param TIMx Timer Instance |
552 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure |
| 553 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure |
553 | * @retval An ErrorStatus enumeration value: |
| 554 | * @retval An ErrorStatus enumeration value: |
554 | * - SUCCESS: TIMx registers are de-initialized |
| 555 | * - SUCCESS: TIMx registers are de-initialized |
555 | * - ERROR: not applicable |
| 556 | * - ERROR: not applicable |
556 | */ |
| 557 | */ |
557 | static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) |
| 558 | static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) |
558 | { |
| 559 | { |
559 | uint32_t tmpccmr1; |
| 560 | uint32_t tmpccmr1; |
560 | uint32_t tmpccer; |
| 561 | uint32_t tmpccer; |
561 | uint32_t tmpcr2; |
| 562 | uint32_t tmpcr2; |
562 | |
| 563 | 563 | /* Check the parameters */ |
|
| 564 | /* Check the parameters */ |
564 | assert_param(IS_TIM_CC2_INSTANCE(TIMx)); |
| 565 | assert_param(IS_TIM_CC2_INSTANCE(TIMx)); |
565 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
| 566 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
566 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
| 567 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
567 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
| 568 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
568 | |
| 569 | 569 | /* Disable the Channel 2: Reset the CC2E Bit */ |
|
| 570 | /* Disable the Channel 2: Reset the CC2E Bit */ |
570 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); |
| 571 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); |
571 | |
| 572 | 572 | /* Get the TIMx CCER register value */ |
|
| 573 | /* Get the TIMx CCER register value */ |
573 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| 574 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
574 | |
| 575 | 575 | /* Get the TIMx CR2 register value */ |
|
| 576 | /* Get the TIMx CR2 register value */ |
576 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
| 577 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
577 | |
| 578 | 578 | /* Get the TIMx CCMR1 register value */ |
|
| 579 | /* Get the TIMx CCMR1 register value */ |
579 | tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); |
| 580 | tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); |
580 | |
| 581 | 581 | /* Reset Capture/Compare selection Bits */ |
|
| 582 | /* Reset Capture/Compare selection Bits */ |
582 | CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); |
| 583 | CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); |
583 | |
| 584 | 584 | /* Select the Output Compare Mode */ |
|
| 585 | /* Select the Output Compare Mode */ |
585 | MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); |
| 586 | MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); |
586 | |
| 587 | 587 | /* Set the Output Compare Polarity */ |
|
| 588 | /* Set the Output Compare Polarity */ |
588 | MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); |
| 589 | MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); |
589 | |
| 590 | 590 | /* Set the Output State */ |
|
| 591 | /* Set the Output State */ |
591 | MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); |
| 592 | MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); |
592 | |
| 593 | 593 | /* Write to TIMx CR2 */ |
|
| 594 | /* Write to TIMx CR2 */ |
594 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
| 595 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
595 | |
| 596 | 596 | /* Write to TIMx CCMR1 */ |
|
| 597 | /* Write to TIMx CCMR1 */ |
597 | LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); |
| 598 | LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); |
598 | |
| 599 | 599 | /* Set the Capture Compare Register value */ |
|
| 600 | /* Set the Capture Compare Register value */ |
600 | LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); |
| 601 | LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); |
601 | |
| 602 | 602 | /* Write to TIMx CCER */ |
|
| 603 | /* Write to TIMx CCER */ |
603 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| 604 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
604 | |
| 605 | 605 | return SUCCESS; |
|
| 606 | return SUCCESS; |
606 | } |
| 607 | } |
607 | |
| 608 | 608 | /** |
|
| 609 | /** |
609 | * @brief Configure the TIMx output channel 3. |
| 610 | * @brief Configure the TIMx output channel 3. |
610 | * @param TIMx Timer Instance |
| 611 | * @param TIMx Timer Instance |
611 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure |
| 612 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure |
612 | * @retval An ErrorStatus enumeration value: |
| 613 | * @retval An ErrorStatus enumeration value: |
613 | * - SUCCESS: TIMx registers are de-initialized |
| 614 | * - SUCCESS: TIMx registers are de-initialized |
614 | * - ERROR: not applicable |
| 615 | * - ERROR: not applicable |
615 | */ |
| 616 | */ |
616 | static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) |
| 617 | static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) |
617 | { |
| 618 | { |
618 | uint32_t tmpccmr2; |
| 619 | uint32_t tmpccmr2; |
619 | uint32_t tmpccer; |
| 620 | uint32_t tmpccer; |
620 | uint32_t tmpcr2; |
| 621 | uint32_t tmpcr2; |
621 | |
| 622 | 622 | /* Check the parameters */ |
|
| 623 | /* Check the parameters */ |
623 | assert_param(IS_TIM_CC3_INSTANCE(TIMx)); |
| 624 | assert_param(IS_TIM_CC3_INSTANCE(TIMx)); |
624 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
| 625 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
625 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
| 626 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
626 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
| 627 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
627 | |
| 628 | 628 | /* Disable the Channel 3: Reset the CC3E Bit */ |
|
| 629 | /* Disable the Channel 3: Reset the CC3E Bit */ |
629 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); |
| 630 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); |
630 | |
| 631 | 631 | /* Get the TIMx CCER register value */ |
|
| 632 | /* Get the TIMx CCER register value */ |
632 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| 633 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
633 | |
| 634 | 634 | /* Get the TIMx CR2 register value */ |
|
| 635 | /* Get the TIMx CR2 register value */ |
635 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
| 636 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
636 | |
| 637 | 637 | /* Get the TIMx CCMR2 register value */ |
|
| 638 | /* Get the TIMx CCMR2 register value */ |
638 | tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); |
| 639 | tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); |
639 | |
| 640 | 640 | /* Reset Capture/Compare selection Bits */ |
|
| 641 | /* Reset Capture/Compare selection Bits */ |
641 | CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); |
| 642 | CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); |
642 | |
| 643 | 643 | /* Select the Output Compare Mode */ |
|
| 644 | /* Select the Output Compare Mode */ |
644 | MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); |
| 645 | MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); |
645 | |
| 646 | 646 | /* Set the Output Compare Polarity */ |
|
| 647 | /* Set the Output Compare Polarity */ |
647 | MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); |
| 648 | MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); |
648 | |
| 649 | 649 | /* Set the Output State */ |
|
| 650 | /* Set the Output State */ |
650 | MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); |
| 651 | MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); |
651 | |
| 652 | 652 | /* Write to TIMx CR2 */ |
|
| 653 | /* Write to TIMx CR2 */ |
653 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
| 654 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
654 | |
| 655 | 655 | /* Write to TIMx CCMR2 */ |
|
| 656 | /* Write to TIMx CCMR2 */ |
656 | LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); |
| 657 | LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); |
657 | |
| 658 | 658 | /* Set the Capture Compare Register value */ |
|
| 659 | /* Set the Capture Compare Register value */ |
659 | LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); |
| 660 | LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); |
660 | |
| 661 | 661 | /* Write to TIMx CCER */ |
|
| 662 | /* Write to TIMx CCER */ |
662 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| 663 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
663 | |
| 664 | 664 | return SUCCESS; |
|
| 665 | return SUCCESS; |
665 | } |
| 666 | } |
666 | |
| 667 | 667 | /** |
|
| 668 | /** |
668 | * @brief Configure the TIMx output channel 4. |
| 669 | * @brief Configure the TIMx output channel 4. |
669 | * @param TIMx Timer Instance |
| 670 | * @param TIMx Timer Instance |
670 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure |
| 671 | * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure |
671 | * @retval An ErrorStatus enumeration value: |
| 672 | * @retval An ErrorStatus enumeration value: |
672 | * - SUCCESS: TIMx registers are de-initialized |
| 673 | * - SUCCESS: TIMx registers are de-initialized |
673 | * - ERROR: not applicable |
| 674 | * - ERROR: not applicable |
674 | */ |
| 675 | */ |
675 | static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) |
| 676 | static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) |
676 | { |
| 677 | { |
677 | uint32_t tmpccmr2; |
| 678 | uint32_t tmpccmr2; |
678 | uint32_t tmpccer; |
| 679 | uint32_t tmpccer; |
679 | uint32_t tmpcr2; |
| 680 | uint32_t tmpcr2; |
680 | |
| 681 | 681 | /* Check the parameters */ |
|
| 682 | /* Check the parameters */ |
682 | assert_param(IS_TIM_CC4_INSTANCE(TIMx)); |
| 683 | assert_param(IS_TIM_CC4_INSTANCE(TIMx)); |
683 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
| 684 | assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); |
684 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
| 685 | assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); |
685 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
| 686 | assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); |
686 | |
| 687 | 687 | /* Disable the Channel 4: Reset the CC4E Bit */ |
|
| 688 | /* Disable the Channel 4: Reset the CC4E Bit */ |
688 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); |
| 689 | CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); |
689 | |
| 690 | 690 | /* Get the TIMx CCER register value */ |
|
| 691 | /* Get the TIMx CCER register value */ |
691 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
| 692 | tmpccer = LL_TIM_ReadReg(TIMx, CCER); |
692 | |
| 693 | 693 | /* Get the TIMx CR2 register value */ |
|
| 694 | /* Get the TIMx CR2 register value */ |
694 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
| 695 | tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); |
695 | |
| 696 | 696 | /* Get the TIMx CCMR2 register value */ |
|
| 697 | /* Get the TIMx CCMR2 register value */ |
697 | tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); |
| 698 | tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); |
698 | |
| 699 | 699 | /* Reset Capture/Compare selection Bits */ |
|
| 700 | /* Reset Capture/Compare selection Bits */ |
700 | CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); |
| 701 | CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); |
701 | |
| 702 | 702 | /* Select the Output Compare Mode */ |
|
| 703 | /* Select the Output Compare Mode */ |
703 | MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); |
| 704 | MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); |
704 | |
| 705 | 705 | /* Set the Output Compare Polarity */ |
|
| 706 | /* Set the Output Compare Polarity */ |
706 | MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); |
| 707 | MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); |
707 | |
| 708 | 708 | /* Set the Output State */ |
|
| 709 | /* Set the Output State */ |
709 | MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); |
| 710 | MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); |
710 | |
| 711 | 711 | /* Write to TIMx CR2 */ |
|
| 712 | /* Write to TIMx CR2 */ |
712 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
| 713 | LL_TIM_WriteReg(TIMx, CR2, tmpcr2); |
713 | |
| 714 | 714 | /* Write to TIMx CCMR2 */ |
|
| 715 | /* Write to TIMx CCMR2 */ |
715 | LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); |
| 716 | LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); |
716 | |
| 717 | 717 | /* Set the Capture Compare Register value */ |
|
| 718 | /* Set the Capture Compare Register value */ |
718 | LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); |
| 719 | LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); |
719 | |
| 720 | 720 | /* Write to TIMx CCER */ |
|
| 721 | /* Write to TIMx CCER */ |
721 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
| 722 | LL_TIM_WriteReg(TIMx, CCER, tmpccer); |
722 | |
| 723 | 723 | return SUCCESS; |
|
| 724 | return SUCCESS; |
724 | } |
| 725 | } |
725 | |
| 726 | 726 | ||
| 727 | 727 | /** |
|
| 728 | /** |
728 | * @brief Configure the TIMx input channel 1. |
| 729 | * @brief Configure the TIMx input channel 1. |
729 | * @param TIMx Timer Instance |
| 730 | * @param TIMx Timer Instance |
730 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure |
| 731 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure |
731 | * @retval An ErrorStatus enumeration value: |
| 732 | * @retval An ErrorStatus enumeration value: |
732 | * - SUCCESS: TIMx registers are de-initialized |
| 733 | * - SUCCESS: TIMx registers are de-initialized |
733 | * - ERROR: not applicable |
| 734 | * - ERROR: not applicable |
734 | */ |
| 735 | */ |
735 | static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) |
| 736 | static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) |
736 | { |
| 737 | { |
737 | /* Check the parameters */ |
| 738 | /* Check the parameters */ |
738 | assert_param(IS_TIM_CC1_INSTANCE(TIMx)); |
| 739 | assert_param(IS_TIM_CC1_INSTANCE(TIMx)); |
739 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
| 740 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
740 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
| 741 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
741 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
| 742 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
742 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
| 743 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
743 | |
| 744 | 744 | /* Disable the Channel 1: Reset the CC1E Bit */ |
|
| 745 | /* Disable the Channel 1: Reset the CC1E Bit */ |
745 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; |
| 746 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; |
746 | |
| 747 | 747 | /* Select the Input and set the filter and the prescaler value */ |
|
| 748 | /* Select the Input and set the filter and the prescaler value */ |
748 | MODIFY_REG(TIMx->CCMR1, |
| 749 | MODIFY_REG(TIMx->CCMR1, |
749 | (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), |
| 750 | (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), |
750 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); |
| 751 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); |
751 | |
| 752 | 752 | /* Select the Polarity and set the CC1E Bit */ |
|
| 753 | /* Select the Polarity and set the CC1E Bit */ |
753 | MODIFY_REG(TIMx->CCER, |
| 754 | MODIFY_REG(TIMx->CCER, |
754 | (TIM_CCER_CC1P | TIM_CCER_CC1NP), |
| 755 | (TIM_CCER_CC1P | TIM_CCER_CC1NP), |
755 | (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); |
| 756 | (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); |
756 | |
| 757 | 757 | return SUCCESS; |
|
| 758 | return SUCCESS; |
758 | } |
| 759 | } |
759 | |
| 760 | 760 | /** |
|
| 761 | /** |
761 | * @brief Configure the TIMx input channel 2. |
| 762 | * @brief Configure the TIMx input channel 2. |
762 | * @param TIMx Timer Instance |
| 763 | * @param TIMx Timer Instance |
763 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure |
| 764 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure |
764 | * @retval An ErrorStatus enumeration value: |
| 765 | * @retval An ErrorStatus enumeration value: |
765 | * - SUCCESS: TIMx registers are de-initialized |
| 766 | * - SUCCESS: TIMx registers are de-initialized |
766 | * - ERROR: not applicable |
| 767 | * - ERROR: not applicable |
767 | */ |
| 768 | */ |
768 | static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) |
| 769 | static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) |
769 | { |
| 770 | { |
770 | /* Check the parameters */ |
| 771 | /* Check the parameters */ |
771 | assert_param(IS_TIM_CC2_INSTANCE(TIMx)); |
| 772 | assert_param(IS_TIM_CC2_INSTANCE(TIMx)); |
772 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
| 773 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
773 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
| 774 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
774 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
| 775 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
775 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
| 776 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
776 | |
| 777 | 777 | /* Disable the Channel 2: Reset the CC2E Bit */ |
|
| 778 | /* Disable the Channel 2: Reset the CC2E Bit */ |
778 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; |
| 779 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; |
779 | |
| 780 | 780 | /* Select the Input and set the filter and the prescaler value */ |
|
| 781 | /* Select the Input and set the filter and the prescaler value */ |
781 | MODIFY_REG(TIMx->CCMR1, |
| 782 | MODIFY_REG(TIMx->CCMR1, |
782 | (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), |
| 783 | (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), |
783 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); |
| 784 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); |
784 | |
| 785 | 785 | /* Select the Polarity and set the CC2E Bit */ |
|
| 786 | /* Select the Polarity and set the CC2E Bit */ |
786 | MODIFY_REG(TIMx->CCER, |
| 787 | MODIFY_REG(TIMx->CCER, |
787 | (TIM_CCER_CC2P | TIM_CCER_CC2NP), |
| 788 | (TIM_CCER_CC2P | TIM_CCER_CC2NP), |
788 | ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); |
| 789 | ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); |
789 | |
| 790 | 790 | return SUCCESS; |
|
| 791 | return SUCCESS; |
791 | } |
| 792 | } |
792 | |
| 793 | 793 | /** |
|
| 794 | /** |
794 | * @brief Configure the TIMx input channel 3. |
| 795 | * @brief Configure the TIMx input channel 3. |
795 | * @param TIMx Timer Instance |
| 796 | * @param TIMx Timer Instance |
796 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure |
| 797 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure |
797 | * @retval An ErrorStatus enumeration value: |
| 798 | * @retval An ErrorStatus enumeration value: |
798 | * - SUCCESS: TIMx registers are de-initialized |
| 799 | * - SUCCESS: TIMx registers are de-initialized |
799 | * - ERROR: not applicable |
| 800 | * - ERROR: not applicable |
800 | */ |
| 801 | */ |
801 | static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) |
| 802 | static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) |
802 | { |
| 803 | { |
803 | /* Check the parameters */ |
| 804 | /* Check the parameters */ |
804 | assert_param(IS_TIM_CC3_INSTANCE(TIMx)); |
| 805 | assert_param(IS_TIM_CC3_INSTANCE(TIMx)); |
805 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
| 806 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
806 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
| 807 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
807 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
| 808 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
808 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
| 809 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
809 | |
| 810 | 810 | /* Disable the Channel 3: Reset the CC3E Bit */ |
|
| 811 | /* Disable the Channel 3: Reset the CC3E Bit */ |
811 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; |
| 812 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; |
812 | |
| 813 | 813 | /* Select the Input and set the filter and the prescaler value */ |
|
| 814 | /* Select the Input and set the filter and the prescaler value */ |
814 | MODIFY_REG(TIMx->CCMR2, |
| 815 | MODIFY_REG(TIMx->CCMR2, |
815 | (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), |
| 816 | (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), |
816 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); |
| 817 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); |
817 | |
| 818 | 818 | /* Select the Polarity and set the CC3E Bit */ |
|
| 819 | /* Select the Polarity and set the CC3E Bit */ |
819 | MODIFY_REG(TIMx->CCER, |
| 820 | MODIFY_REG(TIMx->CCER, |
820 | (TIM_CCER_CC3P | TIM_CCER_CC3NP), |
| 821 | (TIM_CCER_CC3P | TIM_CCER_CC3NP), |
821 | ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); |
| 822 | ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); |
822 | |
| 823 | 823 | return SUCCESS; |
|
| 824 | return SUCCESS; |
824 | } |
| 825 | } |
825 | |
| 826 | 826 | /** |
|
| 827 | /** |
827 | * @brief Configure the TIMx input channel 4. |
| 828 | * @brief Configure the TIMx input channel 4. |
828 | * @param TIMx Timer Instance |
| 829 | * @param TIMx Timer Instance |
829 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure |
| 830 | * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure |
830 | * @retval An ErrorStatus enumeration value: |
| 831 | * @retval An ErrorStatus enumeration value: |
831 | * - SUCCESS: TIMx registers are de-initialized |
| 832 | * - SUCCESS: TIMx registers are de-initialized |
832 | * - ERROR: not applicable |
| 833 | * - ERROR: not applicable |
833 | */ |
| 834 | */ |
834 | static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) |
| 835 | static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) |
835 | { |
| 836 | { |
836 | /* Check the parameters */ |
| 837 | /* Check the parameters */ |
837 | assert_param(IS_TIM_CC4_INSTANCE(TIMx)); |
| 838 | assert_param(IS_TIM_CC4_INSTANCE(TIMx)); |
838 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
| 839 | assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); |
839 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
| 840 | assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); |
840 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
| 841 | assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); |
841 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
| 842 | assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); |
842 | |
| 843 | 843 | /* Disable the Channel 4: Reset the CC4E Bit */ |
|
| 844 | /* Disable the Channel 4: Reset the CC4E Bit */ |
844 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; |
| 845 | TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; |
845 | |
| 846 | 846 | /* Select the Input and set the filter and the prescaler value */ |
|
| 847 | /* Select the Input and set the filter and the prescaler value */ |
847 | MODIFY_REG(TIMx->CCMR2, |
| 848 | MODIFY_REG(TIMx->CCMR2, |
848 | (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), |
| 849 | (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), |
849 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); |
| 850 | (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); |
850 | |
| 851 | 851 | /* Select the Polarity and set the CC2E Bit */ |
|
| 852 | /* Select the Polarity and set the CC2E Bit */ |
852 | MODIFY_REG(TIMx->CCER, |
| 853 | MODIFY_REG(TIMx->CCER, |
853 | (TIM_CCER_CC4P | TIM_CCER_CC4NP), |
| 854 | (TIM_CCER_CC4P | TIM_CCER_CC4NP), |
854 | ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); |
| 855 | ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); |
855 | |
| 856 | 856 | return SUCCESS; |
|
| 857 | return SUCCESS; |
857 | } |
| 858 | } |
858 | |
| 859 | 859 | ||
| 860 | 860 | /** |
|
| 861 | /** |
861 | * @} |
| 862 | * @} |
862 | */ |
| 863 | */ |
863 | |
| 864 | 864 | /** |
|
| 865 | /** |
865 | * @} |
| 866 | * @} |
866 | */ |
| 867 | */ |
867 | |
| 868 | 868 | #endif /* TIM2 || TIM3 || TIM4 || TIM5 || TIM9 || TIM10 || TIM11 TIM6 || TIM7 */ |
|
| 869 | #endif /* TIM2 || TIM3 || TIM4 || TIM5 || TIM9 || TIM10 || TIM11 TIM6 || TIM7 */ |
869 | |
| 870 | 870 | /** |
|
| 871 | /** |
871 | * @} |
| 872 | * @} |
872 | */ |
| 873 | */ |
873 | |
| 874 | 874 | #endif /* USE_FULL_LL_DRIVER */ |
|
| 875 | #endif /* USE_FULL_LL_DRIVER */ |
875 | |
| 876 | - | ||
| 877 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- | |