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| Rev 56 | Rev 61 | ||
|---|---|---|---|
| Line 647... | Line 647... | ||
| 647 | { |
647 | { |
| 648 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
648 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
| 649 | } |
649 | } |
| 650 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
650 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
| 651 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
651 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
| - | 652 | ||
| - | 653 | /* ADC group regular continuous mode and discontinuous mode */ |
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| - | 654 | /* can not be enabled simultenaeously */ |
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| - | 655 | assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) |
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| - | 656 | || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); |
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| 652 | 657 | ||
| 653 | /* Note: Hardware constraint (refer to description of this function): */ |
658 | /* Note: Hardware constraint (refer to description of this function): */ |
| 654 | /* ADC instance must be disabled. */ |
659 | /* ADC instance must be disabled. */ |
| 655 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
660 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| 656 | { |
661 | { |
| 657 | /* Configuration of ADC hierarchical scope: */ |
662 | /* Configuration of ADC hierarchical scope: */ |