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| 1 | /** |
1 | /** |
| 2 | ****************************************************************************** |
2 | ****************************************************************************** |
| 3 | * @file stm32l1xx_ll_adc.c |
3 | * @file stm32l1xx_ll_adc.c |
| 4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
| 5 | * @brief ADC LL module driver |
5 | * @brief ADC LL module driver |
| 6 | ****************************************************************************** |
6 | ****************************************************************************** |
| 7 | * @attention |
7 | * @attention |
| 8 | * |
8 | * |
| 9 | * <h2><center>© Copyright (c) 2017 STMicroelectronics. |
9 | * Copyright (c) 2016 STMicroelectronics. |
| 10 | * All rights reserved.</center></h2> |
10 | * All rights reserved. |
| 11 | * |
11 | * |
| 12 | * This software component is licensed by ST under BSD 3-Clause license, |
12 | * This software is licensed under terms that can be found in the LICENSE file |
| 13 | * the "License"; You may not use this file except in compliance with the |
13 | * in the root directory of this software component. |
| 14 | * License. You may obtain a copy of the License at: |
14 | * If no LICENSE file comes with this software, it is provided AS-IS. |
| 15 | * opensource.org/licenses/BSD-3-Clause |
15 | * |
| 16 | * |
16 | ****************************************************************************** |
| 17 | ****************************************************************************** |
17 | */ |
| 18 | */ |
18 | #if defined(USE_FULL_LL_DRIVER) |
| 19 | #if defined(USE_FULL_LL_DRIVER) |
19 | |
| 20 | 20 | /* Includes ------------------------------------------------------------------*/ |
|
| 21 | /* Includes ------------------------------------------------------------------*/ |
21 | #include "stm32l1xx_ll_adc.h" |
| 22 | #include "stm32l1xx_ll_adc.h" |
22 | #include "stm32l1xx_ll_bus.h" |
| 23 | #include "stm32l1xx_ll_bus.h" |
23 | |
| 24 | 24 | #ifdef USE_FULL_ASSERT |
|
| 25 | #ifdef USE_FULL_ASSERT |
25 | #include "stm32_assert.h" |
| 26 | #include "stm32_assert.h" |
26 | #else |
| 27 | #else |
27 | #define assert_param(expr) ((void)0U) |
| 28 | #define assert_param(expr) ((void)0U) |
28 | #endif |
| 29 | #endif |
29 | |
| 30 | 30 | /** @addtogroup STM32L1xx_LL_Driver |
|
| 31 | /** @addtogroup STM32L1xx_LL_Driver |
31 | * @{ |
| 32 | * @{ |
32 | */ |
| 33 | */ |
33 | |
| 34 | 34 | #if defined (ADC1) |
|
| 35 | #if defined (ADC1) |
35 | |
| 36 | 36 | /** @addtogroup ADC_LL ADC |
|
| 37 | /** @addtogroup ADC_LL ADC |
37 | * @{ |
| 38 | * @{ |
38 | */ |
| 39 | */ |
39 | |
| 40 | 40 | /* Private types -------------------------------------------------------------*/ |
|
| 41 | /* Private types -------------------------------------------------------------*/ |
41 | /* Private variables ---------------------------------------------------------*/ |
| 42 | /* Private variables ---------------------------------------------------------*/ |
42 | /* Private constants ---------------------------------------------------------*/ |
| 43 | /* Private constants ---------------------------------------------------------*/ |
43 | /* Private macros ------------------------------------------------------------*/ |
| 44 | /* Private macros ------------------------------------------------------------*/ |
44 | |
| 45 | 45 | /** @addtogroup ADC_LL_Private_Macros |
|
| 46 | /** @addtogroup ADC_LL_Private_Macros |
46 | * @{ |
| 47 | * @{ |
47 | */ |
| 48 | */ |
48 | |
| 49 | 49 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
|
| 50 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
50 | /* common to several ADC instances. */ |
| 51 | /* common to several ADC instances. */ |
51 | #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ |
| 52 | #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \ |
52 | ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ |
| 53 | ( ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \ |
53 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ |
| 54 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2) \ |
54 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ |
| 55 | || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4) \ |
55 | ) |
| 56 | ) |
56 | |
| 57 | 57 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
|
| 58 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
58 | /* ADC instance. */ |
| 59 | /* ADC instance. */ |
59 | #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ |
| 60 | #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ |
60 | ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ |
| 61 | ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ |
61 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ |
| 62 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ |
62 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ |
| 63 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ |
63 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ |
| 64 | || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ |
64 | ) |
| 65 | ) |
65 | |
| 66 | 66 | #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
|
| 67 | #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ |
67 | ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
| 68 | ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ |
68 | || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
| 69 | || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ |
69 | ) |
| 70 | ) |
70 | |
| 71 | 71 | #define IS_LL_ADC_LOW_POWER_AUTOWAIT(__LOW_POWER__) \ |
|
| 72 | #define IS_LL_ADC_LOW_POWER_AUTOWAIT(__LOW_POWER__) \ |
72 | ( ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_NONE) \ |
| 73 | ( ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_NONE) \ |
73 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ |
| 74 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ |
74 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES) \ |
| 75 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_7_APBCLOCKCYCLES) \ |
75 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES) \ |
| 76 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_15_APBCLOCKCYCLES) \ |
76 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES) \ |
| 77 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_31_APBCLOCKCYCLES) \ |
77 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES) \ |
| 78 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_63_APBCLOCKCYCLES) \ |
78 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES) \ |
| 79 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_127_APBCLOCKCYCLES) \ |
79 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES) \ |
| 80 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT_255_APBCLOCKCYCLES) \ |
80 | ) |
| 81 | ) |
81 | |
| 82 | 82 | #define IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(__LOW_POWER__) \ |
|
| 83 | #define IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(__LOW_POWER__) \ |
83 | ( ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_NONE) \ |
| 84 | ( ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_NONE) \ |
84 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE) \ |
| 85 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_PHASE) \ |
85 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE) \ |
| 86 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_AUTOWAIT_PHASE) \ |
86 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES) \ |
| 87 | || ((__LOW_POWER__) == LL_ADC_LP_AUTOPOWEROFF_IDLE_AUTOWAIT_PHASES) \ |
87 | ) |
| 88 | ) |
88 | |
| 89 | 89 | #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ |
|
| 90 | #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \ |
90 | ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
| 91 | ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
91 | || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
| 92 | || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
92 | ) |
| 93 | ) |
93 | |
| 94 | 94 | #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ |
|
| 95 | #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \ |
95 | ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
| 96 | ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \ |
96 | || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
| 97 | || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \ |
97 | ) |
| 98 | ) |
98 | |
| 99 | 99 | #define IS_LL_ADC_CHANNELS_BANK(__CHANNELS_BANK__) \ |
|
| 100 | #define IS_LL_ADC_CHANNELS_BANK(__CHANNELS_BANK__) \ |
100 | ( ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_A) \ |
| 101 | ( ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_A) \ |
101 | || ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_B) \ |
| 102 | || ((__CHANNELS_BANK__) == LL_ADC_CHANNELS_BANK_B) \ |
102 | ) |
| 103 | ) |
103 | |
| 104 | 104 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
|
| 105 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
105 | /* ADC group regular */ |
| 106 | /* ADC group regular */ |
106 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
| 107 | #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ |
107 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
| 108 | ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ |
108 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ |
| 109 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \ |
109 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ |
| 110 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3) \ |
110 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
| 111 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ |
111 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
| 112 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \ |
112 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ |
| 113 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1) \ |
113 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH3) \ |
| 114 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH3) \ |
114 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ |
| 115 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \ |
115 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
| 116 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \ |
116 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ |
| 117 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \ |
117 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_CH2) \ |
| 118 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_CH2) \ |
118 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_TRGO) \ |
| 119 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM9_TRGO) \ |
119 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
| 120 | || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \ |
120 | ) |
| 121 | ) |
121 | |
| 122 | 122 | #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
|
| 123 | #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ |
123 | ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
| 124 | ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ |
124 | || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
| 125 | || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ |
125 | ) |
| 126 | ) |
126 | |
| 127 | 127 | #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
|
| 128 | #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ |
128 | ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
| 129 | ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ |
129 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ |
| 130 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ |
130 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
| 131 | || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ |
131 | ) |
| 132 | ) |
132 | |
| 133 | 133 | #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ |
|
| 134 | #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \ |
134 | ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ |
| 135 | ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \ |
135 | || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ |
| 136 | || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \ |
136 | ) |
| 137 | ) |
137 | |
| 138 | 138 | #if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L151xDX) || defined (STM32L152xE) || defined (STM32L152xDX) || defined (STM32L162xE) || defined (STM32L162xDX) |
|
| 139 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
139 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
| 140 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
140 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
| 141 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
141 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
| 142 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
142 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
| 143 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
143 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
| 144 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
144 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
| 145 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
145 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
| 146 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
146 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
| 147 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
147 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
| 148 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
148 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
| 149 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
149 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
| 150 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
150 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
| 151 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
151 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
| 152 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
152 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
| 153 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
153 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
| 154 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
154 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
| 155 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
155 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
| 156 | ) |
156 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_17RANKS) \ |
| 157 | 157 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_18RANKS) \ |
|
| 158 | #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
158 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_19RANKS) \ |
| 159 | ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
159 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_20RANKS) \ |
| 160 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
160 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_21RANKS) \ |
| 161 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ |
161 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_22RANKS) \ |
| 162 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ |
162 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_23RANKS) \ |
| 163 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ |
163 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_24RANKS) \ |
| 164 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ |
164 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_25RANKS) \ |
| 165 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ |
165 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_26RANKS) \ |
| 166 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ |
166 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_27RANKS) \ |
| 167 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ |
167 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_28RANKS) \ |
| 168 | ) |
168 | ) |
| 169 | 169 | #else |
|
| 170 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
170 | #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \ |
| 171 | /* ADC group injected */ |
171 | ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \ |
| 172 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
172 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \ |
| 173 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
173 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \ |
| 174 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_CH1) \ |
174 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \ |
| 175 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_TRGO) \ |
175 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \ |
| 176 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
176 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \ |
| 177 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
177 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \ |
| 178 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
178 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \ |
| 179 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
179 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \ |
| 180 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ |
180 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \ |
| 181 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ |
181 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \ |
| 182 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ |
182 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \ |
| 183 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM10_CH1) \ |
183 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \ |
| 184 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ |
184 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \ |
| 185 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
185 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \ |
| 186 | ) |
186 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \ |
| 187 | 187 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_17RANKS) \ |
|
| 188 | #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ |
188 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_18RANKS) \ |
| 189 | ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ |
189 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_19RANKS) \ |
| 190 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ |
190 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_20RANKS) \ |
| 191 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ |
191 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_21RANKS) \ |
| 192 | ) |
192 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_22RANKS) \ |
| 193 | 193 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_23RANKS) \ |
|
| 194 | #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ |
194 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_24RANKS) \ |
| 195 | ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ |
195 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_25RANKS) \ |
| 196 | || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ |
196 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_26RANKS) \ |
| 197 | ) |
197 | || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_27RANKS) \ |
| 198 | 198 | ) |
|
| 199 | #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ |
199 | #endif /* STM32L100xC || STM32L151xC || STM32L152xC) || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L151xDX || STM32L152xE || STM32L152xDX || STM32L162xE || STM32L162xDX */ |
| 200 | ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ |
200 | |
| 201 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ |
201 | #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ |
| 202 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ |
202 | ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ |
| 203 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ |
203 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ |
| 204 | ) |
204 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \ |
| 205 | 205 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \ |
|
| 206 | #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ |
206 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \ |
| 207 | ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ |
207 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \ |
| 208 | || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ |
208 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \ |
| 209 | ) |
209 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \ |
| 210 | 210 | || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \ |
|
| 211 | /** |
211 | ) |
| 212 | * @} |
212 | |
| 213 | */ |
213 | /* Check of parameters for configuration of ADC hierarchical scope: */ |
| 214 | 214 | /* ADC group injected */ |
|
| 215 | 215 | #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \ |
|
| 216 | /* Private function prototypes -----------------------------------------------*/ |
216 | ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \ |
| 217 | 217 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_CH1) \ |
|
| 218 | /* Exported functions --------------------------------------------------------*/ |
218 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM9_TRGO) \ |
| 219 | /** @addtogroup ADC_LL_Exported_Functions |
219 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \ |
| 220 | * @{ |
220 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \ |
| 221 | */ |
221 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \ |
| 222 | 222 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \ |
|
| 223 | /** @addtogroup ADC_LL_EF_Init |
223 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH1) \ |
| 224 | * @{ |
224 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH2) \ |
| 225 | */ |
225 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3) \ |
| 226 | 226 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM10_CH1) \ |
|
| 227 | /** |
227 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO) \ |
| 228 | * @brief De-initialize registers of all ADC instances belonging to |
228 | || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \ |
| 229 | * the same ADC common instance to their default reset values. |
229 | ) |
| 230 | * @param ADCxy_COMMON ADC common instance |
230 | |
| 231 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
231 | #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \ |
| 232 | * @retval An ErrorStatus enumeration value: |
232 | ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \ |
| 233 | * - SUCCESS: ADC common registers are de-initialized |
233 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \ |
| 234 | * - ERROR: not applicable |
234 | || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \ |
| 235 | */ |
235 | ) |
| 236 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
236 | |
| 237 | { |
237 | #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \ |
| 238 | /* Check the parameters */ |
238 | ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \ |
| 239 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
239 | || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \ |
| 240 | 240 | ) |
|
| 241 | /* Force reset of ADC clock (core clock) */ |
241 | |
| 242 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1); |
242 | #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \ |
| 243 | 243 | ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \ |
|
| 244 | /* Release reset of ADC clock (core clock) */ |
244 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \ |
| 245 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1); |
245 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \ |
| 246 | 246 | || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \ |
|
| 247 | return SUCCESS; |
247 | ) |
| 248 | } |
248 | |
| 249 | 249 | #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \ |
|
| 250 | /** |
250 | ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \ |
| 251 | * @brief Initialize some features of ADC common parameters |
251 | || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \ |
| 252 | * (all ADC instances belonging to the same ADC common instance) |
252 | ) |
| 253 | * and multimode (for devices with several ADC instances available). |
253 | |
| 254 | * @note The setting of ADC common parameters is conditioned to |
254 | /** |
| 255 | * ADC instances state: |
255 | * @} |
| 256 | * All ADC instances belonging to the same ADC common instance |
256 | */ |
| 257 | * must be disabled. |
257 | |
| 258 | * @param ADCxy_COMMON ADC common instance |
258 | |
| 259 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
259 | /* Private function prototypes -----------------------------------------------*/ |
| 260 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
260 | |
| 261 | * @retval An ErrorStatus enumeration value: |
261 | /* Exported functions --------------------------------------------------------*/ |
| 262 | * - SUCCESS: ADC common registers are initialized |
262 | /** @addtogroup ADC_LL_Exported_Functions |
| 263 | * - ERROR: ADC common registers are not initialized |
263 | * @{ |
| 264 | */ |
264 | */ |
| 265 | ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
265 | |
| 266 | { |
266 | /** @addtogroup ADC_LL_EF_Init |
| 267 | ErrorStatus status = SUCCESS; |
267 | * @{ |
| 268 | 268 | */ |
|
| 269 | /* Check the parameters */ |
269 | |
| 270 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
270 | /** |
| 271 | assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); |
271 | * @brief De-initialize registers of all ADC instances belonging to |
| 272 | 272 | * the same ADC common instance to their default reset values. |
|
| 273 | /* Note: Hardware constraint (refer to description of functions */ |
273 | * @param ADCxy_COMMON ADC common instance |
| 274 | /* "LL_ADC_SetCommonXXX()": */ |
274 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
| 275 | /* On this STM32 serie, setting of these features is conditioned to */ |
275 | * @retval An ErrorStatus enumeration value: |
| 276 | /* ADC state: */ |
276 | * - SUCCESS: ADC common registers are de-initialized |
| 277 | /* All ADC instances of the ADC common group must be disabled. */ |
277 | * - ERROR: not applicable |
| 278 | if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) |
278 | */ |
| 279 | { |
279 | ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) |
| 280 | /* Configuration of ADC hierarchical scope: */ |
280 | { |
| 281 | /* - common to several ADC */ |
281 | /* Check the parameters */ |
| 282 | /* (all ADC instances belonging to the same ADC common instance) */ |
282 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
| 283 | /* - Set ADC clock (conversion clock) */ |
283 | |
| 284 | LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); |
284 | /* Force reset of ADC clock (core clock) */ |
| 285 | } |
285 | LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC1); |
| 286 | else |
286 | |
| 287 | { |
287 | /* Release reset of ADC clock (core clock) */ |
| 288 | /* Initialization error: One or several ADC instances belonging to */ |
288 | LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1); |
| 289 | /* the same ADC common instance are not disabled. */ |
289 | |
| 290 | status = ERROR; |
290 | return SUCCESS; |
| 291 | } |
291 | } |
| 292 | 292 | ||
| 293 | return status; |
293 | /** |
| 294 | } |
294 | * @brief Initialize some features of ADC common parameters |
| 295 | 295 | * (all ADC instances belonging to the same ADC common instance) |
|
| 296 | /** |
296 | * and multimode (for devices with several ADC instances available). |
| 297 | * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. |
297 | * @note The setting of ADC common parameters is conditioned to |
| 298 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
298 | * ADC instances state: |
| 299 | * whose fields will be set to default values. |
299 | * All ADC instances belonging to the same ADC common instance |
| 300 | * @retval None |
300 | * must be disabled. |
| 301 | */ |
301 | * @param ADCxy_COMMON ADC common instance |
| 302 | void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
302 | * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) |
| 303 | { |
303 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
| 304 | /* Set ADC_CommonInitStruct fields to default values */ |
304 | * @retval An ErrorStatus enumeration value: |
| 305 | /* Set fields of ADC common */ |
305 | * - SUCCESS: ADC common registers are initialized |
| 306 | /* (all ADC instances belonging to the same ADC common instance) */ |
306 | * - ERROR: ADC common registers are not initialized |
| 307 | ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; |
307 | */ |
| 308 | 308 | ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
|
| 309 | } |
309 | { |
| 310 | 310 | ErrorStatus status = SUCCESS; |
|
| 311 | /** |
311 | |
| 312 | * @brief De-initialize registers of the selected ADC instance |
312 | /* Check the parameters */ |
| 313 | * to their default reset values. |
313 | assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); |
| 314 | * @note To reset all ADC instances quickly (perform a hard reset), |
314 | assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock)); |
| 315 | * use function @ref LL_ADC_CommonDeInit(). |
315 | |
| 316 | * @param ADCx ADC instance |
316 | /* Note: Hardware constraint (refer to description of functions */ |
| 317 | * @retval An ErrorStatus enumeration value: |
317 | /* "LL_ADC_SetCommonXXX()": */ |
| 318 | * - SUCCESS: ADC registers are de-initialized |
318 | /* On this STM32 series, setting of these features is conditioned to */ |
| 319 | * - ERROR: ADC registers are not de-initialized |
319 | /* ADC state: */ |
| 320 | */ |
320 | /* All ADC instances of the ADC common group must be disabled. */ |
| 321 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
321 | if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U) |
| 322 | { |
322 | { |
| 323 | ErrorStatus status = SUCCESS; |
323 | /* Configuration of ADC hierarchical scope: */ |
| 324 | 324 | /* - common to several ADC */ |
|
| 325 | /* Check the parameters */ |
325 | /* (all ADC instances belonging to the same ADC common instance) */ |
| 326 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
326 | /* - Set ADC clock (conversion clock) */ |
| 327 | 327 | LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock); |
|
| 328 | /* Disable ADC instance if not already disabled. */ |
328 | } |
| 329 | if(LL_ADC_IsEnabled(ADCx) == 1U) |
329 | else |
| 330 | { |
330 | { |
| 331 | /* Set ADC group regular trigger source to SW start to ensure to not */ |
331 | /* Initialization error: One or several ADC instances belonging to */ |
| 332 | /* have an external trigger event occurring during the conversion stop */ |
332 | /* the same ADC common instance are not disabled. */ |
| 333 | /* ADC disable process. */ |
333 | status = ERROR; |
| 334 | LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
334 | } |
| 335 | 335 | ||
| 336 | /* Set ADC group injected trigger source to SW start to ensure to not */ |
336 | return status; |
| 337 | /* have an external trigger event occurring during the conversion stop */ |
337 | } |
| 338 | /* ADC disable process. */ |
338 | |
| 339 | LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); |
339 | /** |
| 340 | 340 | * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value. |
|
| 341 | /* Disable the ADC instance */ |
341 | * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure |
| 342 | LL_ADC_Disable(ADCx); |
342 | * whose fields will be set to default values. |
| 343 | } |
343 | * @retval None |
| 344 | 344 | */ |
|
| 345 | /* Check whether ADC state is compliant with expected state */ |
345 | void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct) |
| 346 | /* (hardware requirements of bits state to reset registers below) */ |
346 | { |
| 347 | if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) |
347 | /* Set ADC_CommonInitStruct fields to default values */ |
| 348 | { |
348 | /* Set fields of ADC common */ |
| 349 | /* ========== Reset ADC registers ========== */ |
349 | /* (all ADC instances belonging to the same ADC common instance) */ |
| 350 | /* Reset register SR */ |
350 | ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_ASYNC_DIV2; |
| 351 | CLEAR_BIT(ADCx->SR, |
351 | |
| 352 | ( LL_ADC_FLAG_STRT |
352 | } |
| 353 | | LL_ADC_FLAG_JSTRT |
353 | |
| 354 | | LL_ADC_FLAG_EOCS |
354 | /** |
| 355 | | LL_ADC_FLAG_OVR |
355 | * @brief De-initialize registers of the selected ADC instance |
| 356 | | LL_ADC_FLAG_JEOS |
356 | * to their default reset values. |
| 357 | | LL_ADC_FLAG_AWD1 ) |
357 | * @note To reset all ADC instances quickly (perform a hard reset), |
| 358 | ); |
358 | * use function @ref LL_ADC_CommonDeInit(). |
| 359 | 359 | * @param ADCx ADC instance |
|
| 360 | /* Reset register CR1 */ |
360 | * @retval An ErrorStatus enumeration value: |
| 361 | CLEAR_BIT(ADCx->CR1, |
361 | * - SUCCESS: ADC registers are de-initialized |
| 362 | ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN |
362 | * - ERROR: ADC registers are not de-initialized |
| 363 | | ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD |
363 | */ |
| 364 | | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
364 | ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) |
| 365 | | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
365 | { |
| 366 | | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
366 | ErrorStatus status = SUCCESS; |
| 367 | | ADC_CR1_AWDCH ) |
367 | |
| 368 | ); |
368 | /* Check the parameters */ |
| 369 | 369 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
|
| 370 | /* Reset register CR2 */ |
370 | |
| 371 | #if defined(ADC_CR2_CFG) |
371 | /* Disable ADC instance if not already disabled. */ |
| 372 | CLEAR_BIT(ADCx->CR2, |
372 | if(LL_ADC_IsEnabled(ADCx) == 1U) |
| 373 | ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
373 | { |
| 374 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
374 | /* Set ADC group regular trigger source to SW start to ensure to not */ |
| 375 | | ADC_CR2_ALIGN | ADC_CR2_EOCS |
375 | /* have an external trigger event occurring during the conversion stop */ |
| 376 | | ADC_CR2_DDS | ADC_CR2_DMA | ADC_CR2_DELS |
376 | /* ADC disable process. */ |
| 377 | | ADC_CR2_CFG | ADC_CR2_CONT | ADC_CR2_ADON ) |
377 | LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); |
| 378 | ); |
378 | |
| 379 | #else |
379 | /* Set ADC group injected trigger source to SW start to ensure to not */ |
| 380 | CLEAR_BIT(ADCx->CR2, |
380 | /* have an external trigger event occurring during the conversion stop */ |
| 381 | ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
381 | /* ADC disable process. */ |
| 382 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
382 | LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE); |
| 383 | | ADC_CR2_ALIGN | ADC_CR2_EOCS |
383 | |
| 384 | | ADC_CR2_DDS | ADC_CR2_DMA | ADC_CR2_DELS |
384 | /* Disable the ADC instance */ |
| 385 | | ADC_CR2_CONT | ADC_CR2_ADON ) |
385 | LL_ADC_Disable(ADCx); |
| 386 | ); |
386 | } |
| 387 | #endif /* ADC_CR2_CFG */ |
387 | |
| 388 | 388 | /* Check whether ADC state is compliant with expected state */ |
|
| 389 | /* Reset register SMPR1 */ |
389 | /* (hardware requirements of bits state to reset registers below) */ |
| 390 | /* Note: On STM32L1, ADC channels 27, 28, 29, 30, 31 are not available */ |
390 | if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U) |
| 391 | /* on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
391 | { |
| 392 | #if defined(ADC_SMPR0_SMP31) |
392 | /* ========== Reset ADC registers ========== */ |
| 393 | CLEAR_BIT(ADCx->SMPR1, |
393 | /* Reset register SR */ |
| 394 | ( ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 |
394 | CLEAR_BIT(ADCx->SR, |
| 395 | | ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |
395 | ( LL_ADC_FLAG_STRT |
| 396 | | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |
396 | | LL_ADC_FLAG_JSTRT |
| 397 | | ADC_SMPR1_SMP20 ) |
397 | | LL_ADC_FLAG_EOCS |
| 398 | ); |
398 | | LL_ADC_FLAG_OVR |
| 399 | #else |
399 | | LL_ADC_FLAG_JEOS |
| 400 | CLEAR_BIT(ADCx->SMPR1, |
400 | | LL_ADC_FLAG_AWD1 ) |
| 401 | ( ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |
401 | ); |
| 402 | | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |
402 | |
| 403 | | ADC_SMPR1_SMP20 ) |
403 | /* Reset register CR1 */ |
| 404 | ); |
404 | CLEAR_BIT(ADCx->CR1, |
| 405 | #endif /* ADC_SMPR0_SMP31 */ |
405 | ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN |
| 406 | 406 | | ADC_CR1_JAWDEN | ADC_CR1_PDI | ADC_CR1_PDD |
|
| 407 | /* Reset register SMPR2 */ |
407 | | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
| 408 | CLEAR_BIT(ADCx->SMPR2, |
408 | | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN |
| 409 | ( ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 |
409 | | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE |
| 410 | | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 |
410 | | ADC_CR1_AWDCH ) |
| 411 | | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 |
411 | ); |
| 412 | | ADC_SMPR2_SMP10 ) |
412 | |
| 413 | ); |
413 | /* Reset register CR2 */ |
| 414 | 414 | #if defined(ADC_CR2_CFG) |
|
| 415 | /* Reset register SMPR3 */ |
415 | CLEAR_BIT(ADCx->CR2, |
| 416 | CLEAR_BIT(ADCx->SMPR3, |
416 | ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
| 417 | ( ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 |
417 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
| 418 | | ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 |
418 | | ADC_CR2_ALIGN | ADC_CR2_EOCS |
| 419 | | ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 |
419 | | ADC_CR2_DDS | ADC_CR2_DMA | ADC_CR2_DELS |
| 420 | | ADC_SMPR3_SMP0 ) |
420 | | ADC_CR2_CFG | ADC_CR2_CONT | ADC_CR2_ADON ) |
| 421 | ); |
421 | ); |
| 422 | 422 | #else |
|
| 423 | #if defined(ADC_SMPR0_SMP31) |
423 | CLEAR_BIT(ADCx->CR2, |
| 424 | /* Reset register SMPR0 */ |
424 | ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL |
| 425 | CLEAR_BIT(ADCx->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30)); |
425 | | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |
| 426 | #endif /* ADC_SMPR0_SMP31 */ |
426 | | ADC_CR2_ALIGN | ADC_CR2_EOCS |
| 427 | 427 | | ADC_CR2_DDS | ADC_CR2_DMA | ADC_CR2_DELS |
|
| 428 | /* Reset register JOFR1 */ |
428 | | ADC_CR2_CONT | ADC_CR2_ADON ) |
| 429 | CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); |
429 | ); |
| 430 | /* Reset register JOFR2 */ |
430 | #endif /* ADC_CR2_CFG */ |
| 431 | CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); |
431 | |
| 432 | /* Reset register JOFR3 */ |
432 | /* Reset register SMPR1 */ |
| 433 | CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); |
433 | /* Note: On STM32L1, ADC channels 27, 28, 29, 30, 31 are not available */ |
| 434 | /* Reset register JOFR4 */ |
434 | /* on all devices: only on STM32L1 Cat.4 and Cat.5. */ |
| 435 | CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); |
435 | #if defined(ADC_SMPR0_SMP31) |
| 436 | 436 | CLEAR_BIT(ADCx->SMPR1, |
|
| 437 | /* Reset register HTR */ |
437 | ( ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 |
| 438 | SET_BIT(ADCx->HTR, ADC_HTR_HT); |
438 | | ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |
| 439 | /* Reset register LTR */ |
439 | | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |
| 440 | CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); |
440 | | ADC_SMPR1_SMP20 ) |
| 441 | 441 | ); |
|
| 442 | /* Reset register SQR1 */ |
442 | #else |
| 443 | CLEAR_BIT(ADCx->SQR1, |
443 | CLEAR_BIT(ADCx->SMPR1, |
| 444 | ( ADC_SQR1_L |
444 | ( ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 |
| 445 | #if defined(ADC_SQR1_SQ28) |
445 | | ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |
| 446 | | ADC_SQR1_SQ28 | ADC_SQR1_SQ27 |
446 | | ADC_SMPR1_SMP20 ) |
| 447 | #endif |
447 | ); |
| 448 | | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) |
448 | #endif /* ADC_SMPR0_SMP31 */ |
| 449 | ); |
449 | |
| 450 | 450 | /* Reset register SMPR2 */ |
|
| 451 | /* Reset register SQR2 */ |
451 | CLEAR_BIT(ADCx->SMPR2, |
| 452 | CLEAR_BIT(ADCx->SQR2, |
452 | ( ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 |
| 453 | ( ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 |
453 | | ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 |
| 454 | | ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19) |
454 | | ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 |
| 455 | ); |
455 | | ADC_SMPR2_SMP10 ) |
| 456 | 456 | ); |
|
| 457 | /* Reset register SQR3 */ |
457 | |
| 458 | CLEAR_BIT(ADCx->SQR3, |
458 | /* Reset register SMPR3 */ |
| 459 | ( ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 |
459 | CLEAR_BIT(ADCx->SMPR3, |
| 460 | | ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13) |
460 | ( ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 |
| 461 | ); |
461 | | ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 |
| 462 | 462 | | ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 |
|
| 463 | /* Reset register SQR4 */ |
463 | | ADC_SMPR3_SMP0 ) |
| 464 | CLEAR_BIT(ADCx->SQR4, |
464 | ); |
| 465 | ( ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 |
465 | |
| 466 | | ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 ) |
466 | #if defined(ADC_SMPR0_SMP31) |
| 467 | ); |
467 | /* Reset register SMPR0 */ |
| 468 | 468 | CLEAR_BIT(ADCx->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30)); |
|
| 469 | /* Reset register SQR5 */ |
469 | #endif /* ADC_SMPR0_SMP31 */ |
| 470 | CLEAR_BIT(ADCx->SQR5, |
470 | |
| 471 | ( ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 |
471 | /* Reset register JOFR1 */ |
| 472 | | ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 ) |
472 | CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1); |
| 473 | ); |
473 | /* Reset register JOFR2 */ |
| 474 | 474 | CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2); |
|
| 475 | 475 | /* Reset register JOFR3 */ |
|
| 476 | /* Reset register JSQR */ |
476 | CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3); |
| 477 | CLEAR_BIT(ADCx->JSQR, |
477 | /* Reset register JOFR4 */ |
| 478 | ( ADC_JSQR_JL |
478 | CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4); |
| 479 | | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
479 | |
| 480 | | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) |
480 | /* Reset register HTR */ |
| 481 | ); |
481 | SET_BIT(ADCx->HTR, ADC_HTR_HT); |
| 482 | 482 | /* Reset register LTR */ |
|
| 483 | /* Reset register DR */ |
483 | CLEAR_BIT(ADCx->LTR, ADC_LTR_LT); |
| 484 | /* bits in access mode read only, no direct reset applicable */ |
484 | |
| 485 | 485 | /* Reset register SQR1 */ |
|
| 486 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
486 | CLEAR_BIT(ADCx->SQR1, |
| 487 | /* bits in access mode read only, no direct reset applicable */ |
487 | ( ADC_SQR1_L |
| 488 | 488 | #if defined(ADC_SQR1_SQ28) |
|
| 489 | /* Reset register CCR */ |
489 | | ADC_SQR1_SQ28 | ADC_SQR1_SQ27 |
| 490 | CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); |
490 | #endif |
| 491 | } |
491 | | ADC_SQR1_SQ26 | ADC_SQR1_SQ25) |
| 492 | 492 | ); |
|
| 493 | return status; |
493 | |
| 494 | } |
494 | /* Reset register SQR2 */ |
| 495 | 495 | CLEAR_BIT(ADCx->SQR2, |
|
| 496 | /** |
496 | ( ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 |
| 497 | * @brief Initialize some features of ADC instance. |
497 | | ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19) |
| 498 | * @note These parameters have an impact on ADC scope: ADC instance. |
498 | ); |
| 499 | * Affects both group regular and group injected (availability |
499 | |
| 500 | * of ADC group injected depends on STM32 families). |
500 | /* Reset register SQR3 */ |
| 501 | * Refer to corresponding unitary functions into |
501 | CLEAR_BIT(ADCx->SQR3, |
| 502 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
502 | ( ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 |
| 503 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
503 | | ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13) |
| 504 | * is conditioned to ADC state: |
504 | ); |
| 505 | * ADC instance must be disabled. |
505 | |
| 506 | * This condition is applied to all ADC features, for efficiency |
506 | /* Reset register SQR4 */ |
| 507 | * and compatibility over all STM32 families. However, the different |
507 | CLEAR_BIT(ADCx->SQR4, |
| 508 | * features can be set under different ADC state conditions |
508 | ( ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 |
| 509 | * (setting possible with ADC enabled without conversion on going, |
509 | | ADC_SQR4_SQ9 | ADC_SQR4_SQ8 | ADC_SQR4_SQ7 ) |
| 510 | * ADC enabled with conversion on going, ...) |
510 | ); |
| 511 | * Each feature can be updated afterwards with a unitary function |
511 | |
| 512 | * and potentially with ADC in a different state than disabled, |
512 | /* Reset register SQR5 */ |
| 513 | * refer to description of each function for setting |
513 | CLEAR_BIT(ADCx->SQR5, |
| 514 | * conditioned to ADC state. |
514 | ( ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 |
| 515 | * @note After using this function, some other features must be configured |
515 | | ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1 ) |
| 516 | * using LL unitary functions. |
516 | ); |
| 517 | * The minimum configuration remaining to be done is: |
517 | |
| 518 | * - Set ADC group regular or group injected sequencer: |
518 | |
| 519 | * map channel on the selected sequencer rank. |
519 | /* Reset register JSQR */ |
| 520 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
520 | CLEAR_BIT(ADCx->JSQR, |
| 521 | * - Set ADC channel sampling time |
521 | ( ADC_JSQR_JL |
| 522 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
522 | | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 |
| 523 | * @param ADCx ADC instance |
523 | | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 ) |
| 524 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
524 | ); |
| 525 | * @retval An ErrorStatus enumeration value: |
525 | |
| 526 | * - SUCCESS: ADC registers are initialized |
526 | /* Reset register DR */ |
| 527 | * - ERROR: ADC registers are not initialized |
527 | /* bits in access mode read only, no direct reset applicable */ |
| 528 | */ |
528 | |
| 529 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
529 | /* Reset registers JDR1, JDR2, JDR3, JDR4 */ |
| 530 | { |
530 | /* bits in access mode read only, no direct reset applicable */ |
| 531 | ErrorStatus status = SUCCESS; |
531 | |
| 532 | 532 | /* Reset register CCR */ |
|
| 533 | /* Check the parameters */ |
533 | CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE); |
| 534 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
534 | } |
| 535 | 535 | ||
| 536 | assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); |
536 | return status; |
| 537 | assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
537 | } |
| 538 | /* Note: On STM32L1, low power feature is set by concatenating */ |
538 | |
| 539 | /* values of @ref ADC_LL_EC_LP_MODE_AUTOWAIT */ |
539 | /** |
| 540 | /* and @ref ADC_LL_EC_LP_MODE_AUTOPOWEROFF. */ |
540 | * @brief Initialize some features of ADC instance. |
| 541 | /* Check of the parameter is done for each of group of values, */ |
541 | * @note These parameters have an impact on ADC scope: ADC instance. |
| 542 | /* by excluding the other group of values. */ |
542 | * Affects both group regular and group injected (availability |
| 543 | assert_param(IS_LL_ADC_LOW_POWER_AUTOWAIT(ADC_InitStruct->LowPowerMode & ~(ADC_CR1_PDI | ADC_CR1_PDD))); |
543 | * of ADC group injected depends on STM32 families). |
| 544 | assert_param(IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(ADC_InitStruct->LowPowerMode & ~(ADC_CR2_DELS))); |
544 | * Refer to corresponding unitary functions into |
| 545 | assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); |
545 | * @ref ADC_LL_EF_Configuration_ADC_Instance . |
| 546 | 546 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
|
| 547 | /* Note: Hardware constraint (refer to description of this function): */ |
547 | * is conditioned to ADC state: |
| 548 | /* ADC instance must be disabled. */ |
548 | * ADC instance must be disabled. |
| 549 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
549 | * This condition is applied to all ADC features, for efficiency |
| 550 | { |
550 | * and compatibility over all STM32 families. However, the different |
| 551 | /* Configuration of ADC hierarchical scope: */ |
551 | * features can be set under different ADC state conditions |
| 552 | /* - ADC instance */ |
552 | * (setting possible with ADC enabled without conversion on going, |
| 553 | /* - Set ADC data resolution */ |
553 | * ADC enabled with conversion on going, ...) |
| 554 | /* - Set ADC conversion data alignment */ |
554 | * Each feature can be updated afterwards with a unitary function |
| 555 | /* - Set ADC low power mode */ |
555 | * and potentially with ADC in a different state than disabled, |
| 556 | MODIFY_REG(ADCx->CR1, |
556 | * refer to description of each function for setting |
| 557 | ADC_CR1_RES |
557 | * conditioned to ADC state. |
| 558 | | ADC_CR1_PDI |
558 | * @note After using this function, some other features must be configured |
| 559 | | ADC_CR1_PDD |
559 | * using LL unitary functions. |
| 560 | | ADC_CR1_SCAN |
560 | * The minimum configuration remaining to be done is: |
| 561 | , |
561 | * - Set ADC group regular or group injected sequencer: |
| 562 | ADC_InitStruct->Resolution |
562 | * map channel on the selected sequencer rank. |
| 563 | | (ADC_InitStruct->LowPowerMode & (ADC_CR1_PDI | ADC_CR1_PDD)) |
563 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
| 564 | | ADC_InitStruct->SequencersScanMode |
564 | * - Set ADC channel sampling time |
| 565 | ); |
565 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| 566 | 566 | * @param ADCx ADC instance |
|
| 567 | MODIFY_REG(ADCx->CR2, |
567 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| 568 | ADC_CR2_ALIGN |
568 | * @retval An ErrorStatus enumeration value: |
| 569 | | ADC_CR2_DELS |
569 | * - SUCCESS: ADC registers are initialized |
| 570 | , |
570 | * - ERROR: ADC registers are not initialized |
| 571 | ADC_InitStruct->DataAlignment |
571 | */ |
| 572 | | (ADC_InitStruct->LowPowerMode & ADC_CR2_DELS) |
572 | ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) |
| 573 | ); |
573 | { |
| 574 | 574 | ErrorStatus status = SUCCESS; |
|
| 575 | } |
575 | |
| 576 | else |
576 | /* Check the parameters */ |
| 577 | { |
577 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| 578 | /* Initialization error: ADC instance is not disabled. */ |
578 | |
| 579 | status = ERROR; |
579 | assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); |
| 580 | } |
580 | assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); |
| 581 | return status; |
581 | /* Note: On STM32L1, low power feature is set by concatenating */ |
| 582 | } |
582 | /* values of @ref ADC_LL_EC_LP_MODE_AUTOWAIT */ |
| 583 | 583 | /* and @ref ADC_LL_EC_LP_MODE_AUTOPOWEROFF. */ |
|
| 584 | /** |
584 | /* Check of the parameter is done for each of group of values, */ |
| 585 | * @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
585 | /* by excluding the other group of values. */ |
| 586 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
586 | assert_param(IS_LL_ADC_LOW_POWER_AUTOWAIT(ADC_InitStruct->LowPowerMode & ~(ADC_CR1_PDI | ADC_CR1_PDD))); |
| 587 | * whose fields will be set to default values. |
587 | assert_param(IS_LL_ADC_LOW_POWER_AUTOPOWEROFF(ADC_InitStruct->LowPowerMode & ~(ADC_CR2_DELS))); |
| 588 | * @retval None |
588 | assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode)); |
| 589 | */ |
589 | |
| 590 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
590 | /* Note: Hardware constraint (refer to description of this function): */ |
| 591 | { |
591 | /* ADC instance must be disabled. */ |
| 592 | /* Set ADC_InitStruct fields to default values */ |
592 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| 593 | /* Set fields of ADC instance */ |
593 | { |
| 594 | ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; |
594 | /* Configuration of ADC hierarchical scope: */ |
| 595 | ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
595 | /* - ADC instance */ |
| 596 | ADC_InitStruct->LowPowerMode = (LL_ADC_LP_AUTOWAIT_NONE | LL_ADC_LP_AUTOPOWEROFF_NONE); |
596 | /* - Set ADC data resolution */ |
| 597 | 597 | /* - Set ADC conversion data alignment */ |
|
| 598 | /* Enable scan mode to have a generic behavior with ADC of other */ |
598 | /* - Set ADC low power mode */ |
| 599 | /* STM32 families, without this setting available: */ |
599 | MODIFY_REG(ADCx->CR1, |
| 600 | /* ADC group regular sequencer and ADC group injected sequencer depend */ |
600 | ADC_CR1_RES |
| 601 | /* only of their own configuration. */ |
601 | | ADC_CR1_PDI |
| 602 | ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; |
602 | | ADC_CR1_PDD |
| 603 | 603 | | ADC_CR1_SCAN |
|
| 604 | } |
604 | , |
| 605 | 605 | ADC_InitStruct->Resolution |
|
| 606 | /** |
606 | | (ADC_InitStruct->LowPowerMode & (ADC_CR1_PDI | ADC_CR1_PDD)) |
| 607 | * @brief Initialize some features of ADC group regular. |
607 | | ADC_InitStruct->SequencersScanMode |
| 608 | * @note These parameters have an impact on ADC scope: ADC group regular. |
608 | ); |
| 609 | * Refer to corresponding unitary functions into |
609 | |
| 610 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
610 | MODIFY_REG(ADCx->CR2, |
| 611 | * (functions with prefix "REG"). |
611 | ADC_CR2_ALIGN |
| 612 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
612 | | ADC_CR2_DELS |
| 613 | * is conditioned to ADC state: |
613 | , |
| 614 | * ADC instance must be disabled. |
614 | ADC_InitStruct->DataAlignment |
| 615 | * This condition is applied to all ADC features, for efficiency |
615 | | (ADC_InitStruct->LowPowerMode & ADC_CR2_DELS) |
| 616 | * and compatibility over all STM32 families. However, the different |
616 | ); |
| 617 | * features can be set under different ADC state conditions |
617 | |
| 618 | * (setting possible with ADC enabled without conversion on going, |
618 | } |
| 619 | * ADC enabled with conversion on going, ...) |
619 | else |
| 620 | * Each feature can be updated afterwards with a unitary function |
620 | { |
| 621 | * and potentially with ADC in a different state than disabled, |
621 | /* Initialization error: ADC instance is not disabled. */ |
| 622 | * refer to description of each function for setting |
622 | status = ERROR; |
| 623 | * conditioned to ADC state. |
623 | } |
| 624 | * @note After using this function, other features must be configured |
624 | return status; |
| 625 | * using LL unitary functions. |
625 | } |
| 626 | * The minimum configuration remaining to be done is: |
626 | |
| 627 | * - Set ADC group regular or group injected sequencer: |
627 | /** |
| 628 | * map channel on the selected sequencer rank. |
628 | * @brief Set each @ref LL_ADC_InitTypeDef field to default value. |
| 629 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
629 | * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure |
| 630 | * - Set ADC channel sampling time |
630 | * whose fields will be set to default values. |
| 631 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
631 | * @retval None |
| 632 | * @param ADCx ADC instance |
632 | */ |
| 633 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
633 | void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) |
| 634 | * @retval An ErrorStatus enumeration value: |
634 | { |
| 635 | * - SUCCESS: ADC registers are initialized |
635 | /* Set ADC_InitStruct fields to default values */ |
| 636 | * - ERROR: ADC registers are not initialized |
636 | /* Set fields of ADC instance */ |
| 637 | */ |
637 | ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; |
| 638 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
638 | ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; |
| 639 | { |
639 | ADC_InitStruct->LowPowerMode = (LL_ADC_LP_AUTOWAIT_NONE | LL_ADC_LP_AUTOPOWEROFF_NONE); |
| 640 | ErrorStatus status = SUCCESS; |
640 | |
| 641 | 641 | /* Enable scan mode to have a generic behavior with ADC of other */ |
|
| 642 | /* Check the parameters */ |
642 | /* STM32 families, without this setting available: */ |
| 643 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
643 | /* ADC group regular sequencer and ADC group injected sequencer depend */ |
| 644 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
644 | /* only of their own configuration. */ |
| 645 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); |
645 | ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE; |
| 646 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
646 | |
| 647 | { |
647 | } |
| 648 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
648 | |
| 649 | } |
649 | /** |
| 650 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
650 | * @brief Initialize some features of ADC group regular. |
| 651 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
651 | * @note These parameters have an impact on ADC scope: ADC group regular. |
| 652 | 652 | * Refer to corresponding unitary functions into |
|
| 653 | /* ADC group regular continuous mode and discontinuous mode */ |
653 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
| 654 | /* can not be enabled simultenaeously */ |
654 | * (functions with prefix "REG"). |
| 655 | assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) |
655 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
| 656 | || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); |
656 | * is conditioned to ADC state: |
| 657 | 657 | * ADC instance must be disabled. |
|
| 658 | /* Note: Hardware constraint (refer to description of this function): */ |
658 | * This condition is applied to all ADC features, for efficiency |
| 659 | /* ADC instance must be disabled. */ |
659 | * and compatibility over all STM32 families. However, the different |
| 660 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
660 | * features can be set under different ADC state conditions |
| 661 | { |
661 | * (setting possible with ADC enabled without conversion on going, |
| 662 | /* Configuration of ADC hierarchical scope: */ |
662 | * ADC enabled with conversion on going, ...) |
| 663 | /* - ADC group regular */ |
663 | * Each feature can be updated afterwards with a unitary function |
| 664 | /* - Set ADC group regular trigger source */ |
664 | * and potentially with ADC in a different state than disabled, |
| 665 | /* - Set ADC group regular sequencer length */ |
665 | * refer to description of each function for setting |
| 666 | /* - Set ADC group regular sequencer discontinuous mode */ |
666 | * conditioned to ADC state. |
| 667 | /* - Set ADC group regular continuous mode */ |
667 | * @note After using this function, other features must be configured |
| 668 | /* - Set ADC group regular conversion data transfer: no transfer or */ |
668 | * using LL unitary functions. |
| 669 | /* transfer by DMA, and DMA requests mode */ |
669 | * The minimum configuration remaining to be done is: |
| 670 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
670 | * - Set ADC group regular or group injected sequencer: |
| 671 | /* ADC conversion. */ |
671 | * map channel on the selected sequencer rank. |
| 672 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
672 | * Refer to function @ref LL_ADC_REG_SetSequencerRanks(). |
| 673 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
673 | * - Set ADC channel sampling time |
| 674 | { |
674 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| 675 | MODIFY_REG(ADCx->CR1, |
675 | * @param ADCx ADC instance |
| 676 | ADC_CR1_DISCEN |
676 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| 677 | | ADC_CR1_DISCNUM |
677 | * @retval An ErrorStatus enumeration value: |
| 678 | , |
678 | * - SUCCESS: ADC registers are initialized |
| 679 | ADC_REG_InitStruct->SequencerLength |
679 | * - ERROR: ADC registers are not initialized |
| 680 | | ADC_REG_InitStruct->SequencerDiscont |
680 | */ |
| 681 | ); |
681 | ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
| 682 | } |
682 | { |
| 683 | else |
683 | ErrorStatus status = SUCCESS; |
| 684 | { |
684 | |
| 685 | MODIFY_REG(ADCx->CR1, |
685 | /* Check the parameters */ |
| 686 | ADC_CR1_DISCEN |
686 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
| 687 | | ADC_CR1_DISCNUM |
687 | assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); |
| 688 | , |
688 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength)); |
| 689 | ADC_REG_InitStruct->SequencerLength |
689 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
| 690 | | LL_ADC_REG_SEQ_DISCONT_DISABLE |
690 | { |
| 691 | ); |
691 | assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); |
| 692 | } |
692 | } |
| 693 | 693 | assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); |
|
| 694 | MODIFY_REG(ADCx->CR2, |
694 | assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); |
| 695 | ADC_CR2_EXTSEL |
695 | |
| 696 | | ADC_CR2_EXTEN |
696 | /* ADC group regular continuous mode and discontinuous mode */ |
| 697 | | ADC_CR2_CONT |
697 | /* can not be enabled simultenaeously */ |
| 698 | | ADC_CR2_DMA |
698 | assert_param((ADC_REG_InitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE) |
| 699 | | ADC_CR2_DDS |
699 | || (ADC_REG_InitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE)); |
| 700 | , |
700 | |
| 701 | (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) |
701 | /* Note: Hardware constraint (refer to description of this function): */ |
| 702 | | ADC_REG_InitStruct->ContinuousMode |
702 | /* ADC instance must be disabled. */ |
| 703 | | ADC_REG_InitStruct->DMATransfer |
703 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| 704 | ); |
704 | { |
| 705 | 705 | /* Configuration of ADC hierarchical scope: */ |
|
| 706 | /* Set ADC group regular sequencer length and scan direction */ |
706 | /* - ADC group regular */ |
| 707 | /* Note: Hardware constraint (refer to description of this function): */ |
707 | /* - Set ADC group regular trigger source */ |
| 708 | /* Note: If ADC instance feature scan mode is disabled */ |
708 | /* - Set ADC group regular sequencer length */ |
| 709 | /* (refer to ADC instance initialization structure */ |
709 | /* - Set ADC group regular sequencer discontinuous mode */ |
| 710 | /* parameter @ref SequencersScanMode */ |
710 | /* - Set ADC group regular continuous mode */ |
| 711 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
711 | /* - Set ADC group regular conversion data transfer: no transfer or */ |
| 712 | /* this parameter is discarded. */ |
712 | /* transfer by DMA, and DMA requests mode */ |
| 713 | LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); |
713 | /* Note: On this STM32 series, ADC trigger edge is set when starting */ |
| 714 | } |
714 | /* ADC conversion. */ |
| 715 | else |
715 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
| 716 | { |
716 | if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
| 717 | /* Initialization error: ADC instance is not disabled. */ |
717 | { |
| 718 | status = ERROR; |
718 | MODIFY_REG(ADCx->CR1, |
| 719 | } |
719 | ADC_CR1_DISCEN |
| 720 | return status; |
720 | | ADC_CR1_DISCNUM |
| 721 | } |
721 | , |
| 722 | 722 | ADC_REG_InitStruct->SequencerLength |
|
| 723 | /** |
723 | | ADC_REG_InitStruct->SequencerDiscont |
| 724 | * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
724 | ); |
| 725 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
725 | } |
| 726 | * whose fields will be set to default values. |
726 | else |
| 727 | * @retval None |
727 | { |
| 728 | */ |
728 | MODIFY_REG(ADCx->CR1, |
| 729 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
729 | ADC_CR1_DISCEN |
| 730 | { |
730 | | ADC_CR1_DISCNUM |
| 731 | /* Set ADC_REG_InitStruct fields to default values */ |
731 | , |
| 732 | /* Set fields of ADC group regular */ |
732 | ADC_REG_InitStruct->SequencerLength |
| 733 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
733 | | LL_ADC_REG_SEQ_DISCONT_DISABLE |
| 734 | /* ADC conversion. */ |
734 | ); |
| 735 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
735 | } |
| 736 | ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
736 | |
| 737 | ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; |
737 | MODIFY_REG(ADCx->CR2, |
| 738 | ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
738 | ADC_CR2_EXTSEL |
| 739 | ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
739 | | ADC_CR2_EXTEN |
| 740 | ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
740 | | ADC_CR2_CONT |
| 741 | } |
741 | | ADC_CR2_DMA |
| 742 | 742 | | ADC_CR2_DDS |
|
| 743 | /** |
743 | , |
| 744 | * @brief Initialize some features of ADC group injected. |
744 | (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL) |
| 745 | * @note These parameters have an impact on ADC scope: ADC group injected. |
745 | | ADC_REG_InitStruct->ContinuousMode |
| 746 | * Refer to corresponding unitary functions into |
746 | | ADC_REG_InitStruct->DMATransfer |
| 747 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
747 | ); |
| 748 | * (functions with prefix "INJ"). |
748 | |
| 749 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
749 | /* Set ADC group regular sequencer length and scan direction */ |
| 750 | * is conditioned to ADC state: |
750 | /* Note: Hardware constraint (refer to description of this function): */ |
| 751 | * ADC instance must be disabled. |
751 | /* Note: If ADC instance feature scan mode is disabled */ |
| 752 | * This condition is applied to all ADC features, for efficiency |
752 | /* (refer to ADC instance initialization structure */ |
| 753 | * and compatibility over all STM32 families. However, the different |
753 | /* parameter @ref SequencersScanMode */ |
| 754 | * features can be set under different ADC state conditions |
754 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
| 755 | * (setting possible with ADC enabled without conversion on going, |
755 | /* this parameter is discarded. */ |
| 756 | * ADC enabled with conversion on going, ...) |
756 | LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength); |
| 757 | * Each feature can be updated afterwards with a unitary function |
757 | } |
| 758 | * and potentially with ADC in a different state than disabled, |
758 | else |
| 759 | * refer to description of each function for setting |
759 | { |
| 760 | * conditioned to ADC state. |
760 | /* Initialization error: ADC instance is not disabled. */ |
| 761 | * @note After using this function, other features must be configured |
761 | status = ERROR; |
| 762 | * using LL unitary functions. |
762 | } |
| 763 | * The minimum configuration remaining to be done is: |
763 | return status; |
| 764 | * - Set ADC group injected sequencer: |
764 | } |
| 765 | * map channel on the selected sequencer rank. |
765 | |
| 766 | * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). |
766 | /** |
| 767 | * - Set ADC channel sampling time |
767 | * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. |
| 768 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
768 | * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure |
| 769 | * @param ADCx ADC instance |
769 | * whose fields will be set to default values. |
| 770 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
770 | * @retval None |
| 771 | * @retval An ErrorStatus enumeration value: |
771 | */ |
| 772 | * - SUCCESS: ADC registers are initialized |
772 | void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) |
| 773 | * - ERROR: ADC registers are not initialized |
773 | { |
| 774 | */ |
774 | /* Set ADC_REG_InitStruct fields to default values */ |
| 775 | ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
775 | /* Set fields of ADC group regular */ |
| 776 | { |
776 | /* Note: On this STM32 series, ADC trigger edge is set when starting */ |
| 777 | ErrorStatus status = SUCCESS; |
777 | /* ADC conversion. */ |
| 778 | 778 | /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */ |
|
| 779 | /* Check the parameters */ |
779 | ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; |
| 780 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
780 | ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE; |
| 781 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); |
781 | ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; |
| 782 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); |
782 | ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; |
| 783 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) |
783 | ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; |
| 784 | { |
784 | } |
| 785 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); |
785 | |
| 786 | } |
786 | /** |
| 787 | assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); |
787 | * @brief Initialize some features of ADC group injected. |
| 788 | 788 | * @note These parameters have an impact on ADC scope: ADC group injected. |
|
| 789 | /* Note: Hardware constraint (refer to description of this function): */ |
789 | * Refer to corresponding unitary functions into |
| 790 | /* ADC instance must be disabled. */ |
790 | * @ref ADC_LL_EF_Configuration_ADC_Group_Regular |
| 791 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
791 | * (functions with prefix "INJ"). |
| 792 | { |
792 | * @note The setting of these parameters by function @ref LL_ADC_Init() |
| 793 | /* Configuration of ADC hierarchical scope: */ |
793 | * is conditioned to ADC state: |
| 794 | /* - ADC group injected */ |
794 | * ADC instance must be disabled. |
| 795 | /* - Set ADC group injected trigger source */ |
795 | * This condition is applied to all ADC features, for efficiency |
| 796 | /* - Set ADC group injected sequencer length */ |
796 | * and compatibility over all STM32 families. However, the different |
| 797 | /* - Set ADC group injected sequencer discontinuous mode */ |
797 | * features can be set under different ADC state conditions |
| 798 | /* - Set ADC group injected conversion trigger: independent or */ |
798 | * (setting possible with ADC enabled without conversion on going, |
| 799 | /* from ADC group regular */ |
799 | * ADC enabled with conversion on going, ...) |
| 800 | /* Note: On this STM32 serie, ADC trigger edge is set when starting */ |
800 | * Each feature can be updated afterwards with a unitary function |
| 801 | /* ADC conversion. */ |
801 | * and potentially with ADC in a different state than disabled, |
| 802 | /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ |
802 | * refer to description of each function for setting |
| 803 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
803 | * conditioned to ADC state. |
| 804 | { |
804 | * @note After using this function, other features must be configured |
| 805 | MODIFY_REG(ADCx->CR1, |
805 | * using LL unitary functions. |
| 806 | ADC_CR1_JDISCEN |
806 | * The minimum configuration remaining to be done is: |
| 807 | | ADC_CR1_JAUTO |
807 | * - Set ADC group injected sequencer: |
| 808 | , |
808 | * map channel on the selected sequencer rank. |
| 809 | ADC_INJ_InitStruct->SequencerDiscont |
809 | * Refer to function @ref LL_ADC_INJ_SetSequencerRanks(). |
| 810 | | ADC_INJ_InitStruct->TrigAuto |
810 | * - Set ADC channel sampling time |
| 811 | ); |
811 | * Refer to function LL_ADC_SetChannelSamplingTime(); |
| 812 | } |
812 | * @param ADCx ADC instance |
| 813 | else |
813 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
| 814 | { |
814 | * @retval An ErrorStatus enumeration value: |
| 815 | MODIFY_REG(ADCx->CR1, |
815 | * - SUCCESS: ADC registers are initialized |
| 816 | ADC_CR1_JDISCEN |
816 | * - ERROR: ADC registers are not initialized |
| 817 | | ADC_CR1_JAUTO |
817 | */ |
| 818 | , |
818 | ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
| 819 | LL_ADC_REG_SEQ_DISCONT_DISABLE |
819 | { |
| 820 | | ADC_INJ_InitStruct->TrigAuto |
820 | ErrorStatus status = SUCCESS; |
| 821 | ); |
821 | |
| 822 | } |
822 | /* Check the parameters */ |
| 823 | 823 | assert_param(IS_ADC_ALL_INSTANCE(ADCx)); |
|
| 824 | MODIFY_REG(ADCx->CR2, |
824 | assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource)); |
| 825 | ADC_CR2_JEXTSEL |
825 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength)); |
| 826 | | ADC_CR2_JEXTEN |
826 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE) |
| 827 | , |
827 | { |
| 828 | (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) |
828 | assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont)); |
| 829 | ); |
829 | } |
| 830 | 830 | assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto)); |
|
| 831 | /* Note: Hardware constraint (refer to description of this function): */ |
831 | |
| 832 | /* Note: If ADC instance feature scan mode is disabled */ |
832 | /* Note: Hardware constraint (refer to description of this function): */ |
| 833 | /* (refer to ADC instance initialization structure */ |
833 | /* ADC instance must be disabled. */ |
| 834 | /* parameter @ref SequencersScanMode */ |
834 | if(LL_ADC_IsEnabled(ADCx) == 0U) |
| 835 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
835 | { |
| 836 | /* this parameter is discarded. */ |
836 | /* Configuration of ADC hierarchical scope: */ |
| 837 | LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); |
837 | /* - ADC group injected */ |
| 838 | } |
838 | /* - Set ADC group injected trigger source */ |
| 839 | else |
839 | /* - Set ADC group injected sequencer length */ |
| 840 | { |
840 | /* - Set ADC group injected sequencer discontinuous mode */ |
| 841 | /* Initialization error: ADC instance is not disabled. */ |
841 | /* - Set ADC group injected conversion trigger: independent or */ |
| 842 | status = ERROR; |
842 | /* from ADC group regular */ |
| 843 | } |
843 | /* Note: On this STM32 series, ADC trigger edge is set when starting */ |
| 844 | return status; |
844 | /* ADC conversion. */ |
| 845 | } |
845 | /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */ |
| 846 | 846 | if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE) |
|
| 847 | /** |
847 | { |
| 848 | * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. |
848 | MODIFY_REG(ADCx->CR1, |
| 849 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
849 | ADC_CR1_JDISCEN |
| 850 | * whose fields will be set to default values. |
850 | | ADC_CR1_JAUTO |
| 851 | * @retval None |
851 | , |
| 852 | */ |
852 | ADC_INJ_InitStruct->SequencerDiscont |
| 853 | void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
853 | | ADC_INJ_InitStruct->TrigAuto |
| 854 | { |
854 | ); |
| 855 | /* Set ADC_INJ_InitStruct fields to default values */ |
855 | } |
| 856 | /* Set fields of ADC group injected */ |
856 | else |
| 857 | ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; |
857 | { |
| 858 | ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; |
858 | MODIFY_REG(ADCx->CR1, |
| 859 | ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; |
859 | ADC_CR1_JDISCEN |
| 860 | ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; |
860 | | ADC_CR1_JAUTO |
| 861 | } |
861 | , |
| 862 | 862 | LL_ADC_REG_SEQ_DISCONT_DISABLE |
|
| 863 | /** |
863 | | ADC_INJ_InitStruct->TrigAuto |
| 864 | * @} |
864 | ); |
| 865 | */ |
865 | } |
| 866 | 866 | ||
| 867 | /** |
867 | MODIFY_REG(ADCx->CR2, |
| 868 | * @} |
868 | ADC_CR2_JEXTSEL |
| 869 | */ |
869 | | ADC_CR2_JEXTEN |
| 870 | 870 | , |
|
| 871 | /** |
871 | (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL) |
| 872 | * @} |
872 | ); |
| 873 | */ |
873 | |
| 874 | 874 | /* Note: Hardware constraint (refer to description of this function): */ |
|
| 875 | #endif /* ADC1 */ |
875 | /* Note: If ADC instance feature scan mode is disabled */ |
| 876 | 876 | /* (refer to ADC instance initialization structure */ |
|
| 877 | /** |
877 | /* parameter @ref SequencersScanMode */ |
| 878 | * @} |
878 | /* or function @ref LL_ADC_SetSequencersScanMode() ), */ |
| 879 | */ |
879 | /* this parameter is discarded. */ |
| 880 | 880 | LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength); |
|
| 881 | #endif /* USE_FULL_LL_DRIVER */ |
881 | } |
| 882 | 882 | else |
|
| 883 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
883 | { |
| - | 884 | /* Initialization error: ADC instance is not disabled. */ |
|
| - | 885 | status = ERROR; |
|
| - | 886 | } |
|
| - | 887 | return status; |
|
| - | 888 | } |
|
| - | 889 | ||
| - | 890 | /** |
|
| - | 891 | * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value. |
|
| - | 892 | * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure |
|
| - | 893 | * whose fields will be set to default values. |
|
| - | 894 | * @retval None |
|
| - | 895 | */ |
|
| - | 896 | void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct) |
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| - | 897 | { |
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| - | 898 | /* Set ADC_INJ_InitStruct fields to default values */ |
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| - | 899 | /* Set fields of ADC group injected */ |
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| - | 900 | ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE; |
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| - | 901 | ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE; |
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| - | 902 | ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE; |
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| - | 903 | ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT; |
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| - | 904 | } |
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| - | 905 | ||
| - | 906 | /** |
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| - | 907 | * @} |
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| - | 908 | */ |
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| - | 909 | ||
| - | 910 | /** |
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| - | 911 | * @} |
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| - | 912 | */ |
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| - | 913 | ||
| - | 914 | /** |
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| - | 915 | * @} |
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| - | 916 | */ |
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| - | 917 | ||
| - | 918 | #endif /* ADC1 */ |
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| - | 919 | ||
| - | 920 | /** |
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| - | 921 | * @} |
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| - | 922 | */ |
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| - | 923 | ||
| - | 924 | #endif /* USE_FULL_LL_DRIVER */ |
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