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1 | /** |
1 | /** |
2 | ****************************************************************************** |
2 | ****************************************************************************** |
3 | * @file stm32l1xx_hal_tim_ex.c |
3 | * @file stm32l1xx_hal_tim_ex.c |
4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
5 | * @brief TIM HAL module driver. |
5 | * @brief TIM HAL module driver. |
6 | * This file provides firmware functions to manage the following |
6 | * This file provides firmware functions to manage the following |
7 | * functionalities of the Timer Extended peripheral: |
7 | * functionalities of the Timer Extended peripheral: |
8 | * + Time Master and Slave synchronization configuration |
8 | * + Time Master and Slave synchronization configuration |
9 | * + Time OCRef clear configuration |
9 | * + Time OCRef clear configuration |
10 | * + Timer remapping capabilities configuration |
10 | * + Timer remapping capabilities configuration |
11 | @verbatim |
11 | ****************************************************************************** |
12 | ============================================================================== |
12 | * @attention |
13 | ##### TIMER Extended features ##### |
13 | * |
14 | ============================================================================== |
14 | * Copyright (c) 2016 STMicroelectronics. |
15 | [..] |
15 | * All rights reserved. |
16 | The Timer Extended features include: |
16 | * |
17 | (#) Synchronization circuit to control the timer with external signals and to |
17 | * This software is licensed under terms that can be found in the LICENSE file |
18 | interconnect several timers together. |
18 | * in the root directory of this software component. |
19 | 19 | * If no LICENSE file comes with this software, it is provided AS-IS. |
|
20 | @endverbatim |
20 | * |
21 | ****************************************************************************** |
21 | ****************************************************************************** |
22 | * @attention |
22 | @verbatim |
23 | * |
23 | ============================================================================== |
24 | * <h2><center>© Copyright (c) 2016 STMicroelectronics. |
24 | ##### TIMER Extended features ##### |
25 | * All rights reserved.</center></h2> |
25 | ============================================================================== |
26 | * |
26 | [..] |
27 | * This software component is licensed by ST under BSD 3-Clause license, |
27 | The Timer Extended features include: |
28 | * the "License"; You may not use this file except in compliance with the |
28 | (#) Synchronization circuit to control the timer with external signals and to |
29 | * License. You may obtain a copy of the License at: |
29 | interconnect several timers together. |
30 | * opensource.org/licenses/BSD-3-Clause |
30 | |
31 | * |
31 | @endverbatim |
32 | ****************************************************************************** |
32 | ****************************************************************************** |
33 | */ |
33 | */ |
34 | 34 | ||
35 | /* Includes ------------------------------------------------------------------*/ |
35 | /* Includes ------------------------------------------------------------------*/ |
36 | #include "stm32l1xx_hal.h" |
36 | #include "stm32l1xx_hal.h" |
37 | 37 | ||
38 | /** @addtogroup STM32L1xx_HAL_Driver |
38 | /** @addtogroup STM32L1xx_HAL_Driver |
39 | * @{ |
39 | * @{ |
40 | */ |
40 | */ |
41 | 41 | ||
42 | /** @defgroup TIMEx TIMEx |
42 | /** @defgroup TIMEx TIMEx |
43 | * @brief TIM Extended HAL module driver |
43 | * @brief TIM Extended HAL module driver |
44 | * @{ |
44 | * @{ |
45 | */ |
45 | */ |
46 | 46 | ||
47 | #ifdef HAL_TIM_MODULE_ENABLED |
47 | #ifdef HAL_TIM_MODULE_ENABLED |
48 | 48 | ||
49 | /* Private typedef -----------------------------------------------------------*/ |
49 | /* Private typedef -----------------------------------------------------------*/ |
50 | /* Private define ------------------------------------------------------------*/ |
50 | /* Private define ------------------------------------------------------------*/ |
51 | /* Private macros ------------------------------------------------------------*/ |
51 | /* Private macros ------------------------------------------------------------*/ |
52 | /* Private variables ---------------------------------------------------------*/ |
52 | /* Private variables ---------------------------------------------------------*/ |
53 | /* Private function prototypes -----------------------------------------------*/ |
53 | /* Private function prototypes -----------------------------------------------*/ |
54 | 54 | ||
55 | /* Exported functions --------------------------------------------------------*/ |
55 | /* Exported functions --------------------------------------------------------*/ |
56 | /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions |
56 | /** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions |
57 | * @{ |
57 | * @{ |
58 | */ |
58 | */ |
59 | /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions |
59 | /** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions |
60 | * @brief Peripheral Control functions |
60 | * @brief Peripheral Control functions |
61 | * |
61 | * |
62 | @verbatim |
62 | @verbatim |
63 | ============================================================================== |
63 | ============================================================================== |
64 | ##### Peripheral Control functions ##### |
64 | ##### Peripheral Control functions ##### |
65 | ============================================================================== |
65 | ============================================================================== |
66 | [..] |
66 | [..] |
67 | This section provides functions allowing to: |
67 | This section provides functions allowing to: |
68 | (+) Configure Master synchronization. |
68 | (+) Configure Master synchronization. |
69 | (+) Configure timer remapping capabilities. |
69 | (+) Configure timer remapping capabilities. |
70 | 70 | ||
71 | @endverbatim |
71 | @endverbatim |
72 | * @{ |
72 | * @{ |
73 | */ |
73 | */ |
74 | 74 | ||
75 | /** |
75 | /** |
76 | * @brief Configures the TIM in master mode. |
76 | * @brief Configures the TIM in master mode. |
77 | * @param htim TIM handle. |
77 | * @param htim TIM handle. |
78 | * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that |
78 | * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that |
79 | * contains the selected trigger output (TRGO) and the Master/Slave |
79 | * contains the selected trigger output (TRGO) and the Master/Slave |
80 | * mode. |
80 | * mode. |
81 | * @retval HAL status |
81 | * @retval HAL status |
82 | */ |
82 | */ |
83 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, |
83 | HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, |
84 | TIM_MasterConfigTypeDef *sMasterConfig) |
84 | const TIM_MasterConfigTypeDef *sMasterConfig) |
85 | { |
85 | { |
86 | uint32_t tmpcr2; |
86 | uint32_t tmpcr2; |
87 | uint32_t tmpsmcr; |
87 | uint32_t tmpsmcr; |
88 | 88 | ||
89 | /* Check the parameters */ |
89 | /* Check the parameters */ |
90 | assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); |
90 | assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); |
91 | assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); |
91 | assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); |
92 | assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); |
92 | assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); |
93 | 93 | ||
94 | /* Check input state */ |
94 | /* Check input state */ |
95 | __HAL_LOCK(htim); |
95 | __HAL_LOCK(htim); |
96 | 96 | ||
97 | /* Change the handler state */ |
97 | /* Change the handler state */ |
98 | htim->State = HAL_TIM_STATE_BUSY; |
98 | htim->State = HAL_TIM_STATE_BUSY; |
99 | 99 | ||
100 | /* Get the TIMx CR2 register value */ |
100 | /* Get the TIMx CR2 register value */ |
101 | tmpcr2 = htim->Instance->CR2; |
101 | tmpcr2 = htim->Instance->CR2; |
102 | 102 | ||
103 | /* Get the TIMx SMCR register value */ |
103 | /* Get the TIMx SMCR register value */ |
104 | tmpsmcr = htim->Instance->SMCR; |
104 | tmpsmcr = htim->Instance->SMCR; |
105 | 105 | ||
106 | /* Reset the MMS Bits */ |
106 | /* Reset the MMS Bits */ |
107 | tmpcr2 &= ~TIM_CR2_MMS; |
107 | tmpcr2 &= ~TIM_CR2_MMS; |
108 | /* Select the TRGO source */ |
108 | /* Select the TRGO source */ |
109 | tmpcr2 |= sMasterConfig->MasterOutputTrigger; |
109 | tmpcr2 |= sMasterConfig->MasterOutputTrigger; |
110 | 110 | ||
111 | /* Update TIMx CR2 */ |
111 | /* Update TIMx CR2 */ |
112 | htim->Instance->CR2 = tmpcr2; |
112 | htim->Instance->CR2 = tmpcr2; |
113 | 113 | ||
114 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
114 | if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) |
115 | { |
115 | { |
116 | /* Reset the MSM Bit */ |
116 | /* Reset the MSM Bit */ |
117 | tmpsmcr &= ~TIM_SMCR_MSM; |
117 | tmpsmcr &= ~TIM_SMCR_MSM; |
118 | /* Set master mode */ |
118 | /* Set master mode */ |
119 | tmpsmcr |= sMasterConfig->MasterSlaveMode; |
119 | tmpsmcr |= sMasterConfig->MasterSlaveMode; |
120 | 120 | ||
121 | /* Update TIMx SMCR */ |
121 | /* Update TIMx SMCR */ |
122 | htim->Instance->SMCR = tmpsmcr; |
122 | htim->Instance->SMCR = tmpsmcr; |
123 | } |
123 | } |
124 | 124 | ||
125 | /* Change the htim state */ |
125 | /* Change the htim state */ |
126 | htim->State = HAL_TIM_STATE_READY; |
126 | htim->State = HAL_TIM_STATE_READY; |
127 | 127 | ||
128 | __HAL_UNLOCK(htim); |
128 | __HAL_UNLOCK(htim); |
129 | 129 | ||
130 | return HAL_OK; |
130 | return HAL_OK; |
131 | } |
131 | } |
132 | 132 | ||
133 | /** |
133 | /** |
134 | * @brief Configures the TIMx Remapping input capabilities. |
134 | * @brief Configures the TIMx Remapping input capabilities. |
135 | * @param htim TIM handle. |
135 | * @param htim TIM handle. |
136 | * @param Remap specifies the TIM remapping source. |
136 | * @param Remap specifies the TIM remapping source. |
137 | * |
137 | * |
138 | * For TIM2, the parameter can have the following values:(see note) |
138 | * For TIM2, the parameter can have the following values:(see note) |
139 | * @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC |
139 | * @arg TIM_TIM2_ITR1_TIM10_OC: TIM2 ITR1 input is connected to TIM10 OC |
140 | * @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO |
140 | * @arg TIM_TIM2_ITR1_TIM5_TGO: TIM2 ITR1 input is connected to TIM5 TGO |
141 | * |
141 | * |
142 | * For TIM3, the parameter can have the following values:(see note) |
142 | * For TIM3, the parameter can have the following values:(see note) |
143 | * @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC |
143 | * @arg TIM_TIM3_ITR2_TIM11_OC: TIM3 ITR2 input is connected to TIM11 OC |
144 | * @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO |
144 | * @arg TIM_TIM3_ITR2_TIM5_TGO: TIM3 ITR2 input is connected to TIM5 TGO |
145 | * |
145 | * |
146 | * For TIM9, the parameter is a combination of 2 fields (field1 | field2): |
146 | * For TIM9, the parameter is a combination of 2 fields (field1 | field2): |
147 | * |
147 | * |
148 | * field1 can have the following values:(see note) |
148 | * field1 can have the following values:(see note) |
149 | * @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO |
149 | * @arg TIM_TIM9_ITR1_TIM3_TGO: TIM9 ITR1 input is connected to TIM3 TGO |
150 | * @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O |
150 | * @arg TIM_TIM9_ITR1_TS: TIM9 ITR1 input is connected to touch sensing I/O |
151 | * |
151 | * |
152 | * field2 can have the following values: |
152 | * field2 can have the following values: |
153 | * @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO |
153 | * @arg TIM_TIM9_GPIO: TIM9 Channel1 is connected to GPIO |
154 | * @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock |
154 | * @arg TIM_TIM9_LSE: TIM9 Channel1 is connected to LSE internal clock |
155 | * @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO |
155 | * @arg TIM_TIM9_GPIO1: TIM9 Channel1 is connected to GPIO |
156 | * @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO |
156 | * @arg TIM_TIM9_GPIO2: TIM9 Channel1 is connected to GPIO |
157 | * |
157 | * |
158 | * For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3): |
158 | * For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3): |
159 | * |
159 | * |
160 | * field1 can have the following values:(see note) |
160 | * field1 can have the following values:(see note) |
161 | * @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP |
161 | * @arg TIM_TIM10_TI1RMP: TIM10 Channel 1 depends on TI1_RMP |
162 | * @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI |
162 | * @arg TIM_TIM10_RI: TIM10 Channel 1 is connected to RI |
163 | * |
163 | * |
164 | * field2 can have the following values:(see note) |
164 | * field2 can have the following values:(see note) |
165 | * @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock |
165 | * @arg TIM_TIM10_ETR_LSE: TIM10 ETR input is connected to LSE clock |
166 | * @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO |
166 | * @arg TIM_TIM10_ETR_TIM9_TGO: TIM10 ETR input is connected to TIM9 TGO |
167 | * |
167 | * |
168 | * field3 can have the following values: |
168 | * field3 can have the following values: |
169 | * @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO |
169 | * @arg TIM_TIM10_GPIO: TIM10 Channel1 is connected to GPIO |
170 | * @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock |
170 | * @arg TIM_TIM10_LSI: TIM10 Channel1 is connected to LSI internal clock |
171 | * @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock |
171 | * @arg TIM_TIM10_LSE: TIM10 Channel1 is connected to LSE internal clock |
172 | * @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt |
172 | * @arg TIM_TIM10_RTC: TIM10 Channel1 is connected to RTC wakeup interrupt |
173 | * |
173 | * |
174 | * For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3): |
174 | * For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3): |
175 | * |
175 | * |
176 | * field1 can have the following values:(see note) |
176 | * field1 can have the following values:(see note) |
177 | * @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP |
177 | * @arg TIM_TIM11_TI1RMP: TIM11 Channel 1 depends on TI1_RMP |
178 | * @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI |
178 | * @arg TIM_TIM11_RI: TIM11 Channel 1 is connected to RI |
179 | * |
179 | * |
180 | * field2 can have the following values:(see note) |
180 | * field2 can have the following values:(see note) |
181 | * @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock |
181 | * @arg TIM_TIM11_ETR_LSE: TIM11 ETR input is connected to LSE clock |
182 | * @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO |
182 | * @arg TIM_TIM11_ETR_TIM9_TGO: TIM11 ETR input is connected to TIM9 TGO |
183 | * |
183 | * |
184 | * field3 can have the following values: |
184 | * field3 can have the following values: |
185 | * @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO |
185 | * @arg TIM_TIM11_GPIO: TIM11 Channel1 is connected to GPIO |
186 | * @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock |
186 | * @arg TIM_TIM11_MSI: TIM11 Channel1 is connected to MSI internal clock |
187 | * @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock |
187 | * @arg TIM_TIM11_HSE_RTC: TIM11 Channel1 is connected to HSE_RTC clock |
188 | * @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO |
188 | * @arg TIM_TIM11_GPIO1: TIM11 Channel1 is connected to GPIO |
189 | * |
189 | * |
190 | * @note Available only in Cat.3, Cat.4,Cat.5 and Cat.6 devices. |
190 | * @note Available only in Cat.3, Cat.4,Cat.5 and Cat.6 devices. |
191 | * |
191 | * |
192 | * @retval HAL status |
192 | * @retval HAL status |
193 | */ |
193 | */ |
194 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) |
194 | HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) |
195 | { |
195 | { |
196 | __HAL_LOCK(htim); |
196 | |
197 | 197 | /* Check parameters */ |
|
198 | /* Check parameters */ |
198 | assert_param(IS_TIM_REMAP(htim->Instance, Remap)); |
199 | assert_param(IS_TIM_REMAP(htim->Instance, Remap)); |
199 | |
200 | 200 | __HAL_LOCK(htim); |
|
201 | /* Set the Timer remapping configuration */ |
201 | |
202 | WRITE_REG(htim->Instance->OR, Remap); |
202 | /* Set the Timer remapping configuration */ |
203 | 203 | WRITE_REG(htim->Instance->OR, Remap); |
|
204 | __HAL_UNLOCK(htim); |
204 | |
205 | 205 | __HAL_UNLOCK(htim); |
|
206 | return HAL_OK; |
206 | |
207 | } |
207 | return HAL_OK; |
208 | 208 | } |
|
209 | /** |
209 | |
210 | * @} |
210 | /** |
211 | */ |
211 | * @} |
212 | 212 | */ |
|
213 | /** |
213 | |
214 | * @} |
214 | /** |
215 | */ |
215 | * @} |
216 | 216 | */ |
|
217 | 217 | ||
218 | #endif /* HAL_TIM_MODULE_ENABLED */ |
218 | |
219 | /** |
219 | #endif /* HAL_TIM_MODULE_ENABLED */ |
220 | * @} |
220 | /** |
221 | */ |
221 | * @} |
222 | 222 | */ |
|
223 | /** |
223 | |
224 | * @} |
224 | /** |
225 | */ |
225 | * @} |
226 | 226 | */ |
|
227 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
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