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Line 940... Line 940...
940 
  * @param  Timeout Timeout duration
 940 
  * @param  Timeout Timeout duration
941 
  * @retval HAL status
 941 
  * @retval HAL status
942 
  */
 942 
  */
943 
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 943 
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
944 
{
 944 
{
- 
 
 945 
#if (USE_SPI_CRC != 0U)
- 
 
 946 
  __IO uint32_t tmpreg = 0U;
- 
 
 947 
#endif /* USE_SPI_CRC */
945 
  uint32_t tickstart;
 948 
  uint32_t tickstart;
946 
  HAL_StatusTypeDef errorcode = HAL_OK;
 949 
  HAL_StatusTypeDef errorcode = HAL_OK;
947 
 
 950 
 
948 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
 951 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
949 
  {
 952 
  {
Line 1091... Line 1094...
1091 
      errorcode = HAL_TIMEOUT;
 1094 
      errorcode = HAL_TIMEOUT;
1092 
      goto error;
 1095 
      goto error;
1093 
    }
 1096 
    }
1094 
 
 1097 
 
1095 
    /* Read CRC to Flush DR and RXNE flag */
 1098 
    /* Read CRC to Flush DR and RXNE flag */
1096 
    READ_REG(hspi->Instance->DR);
 1099 
    tmpreg = READ_REG(hspi->Instance->DR);
- 
 
 1100 
    /* To avoid GCC warning */
- 
 
 1101 
    UNUSED(tmpreg);
1097 
  }
 1102 
  }
1098 
#endif /* USE_SPI_CRC */
 1103 
#endif /* USE_SPI_CRC */
1099 
 
 1104 
 
1100 
  /* Check the end of the transaction */
 1105 
  /* Check the end of the transaction */
1101 
  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
 1106 
  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
Line 1138... Line 1143...
1138 
{
 1143 
{
1139 
  uint16_t             initial_TxXferCount;
 1144 
  uint16_t             initial_TxXferCount;
1140 
  uint32_t             tmp_mode;
 1145 
  uint32_t             tmp_mode;
1141 
  HAL_SPI_StateTypeDef tmp_state;
 1146 
  HAL_SPI_StateTypeDef tmp_state;
1142 
  uint32_t             tickstart;
 1147 
  uint32_t             tickstart;
- 
 
 1148 
#if (USE_SPI_CRC != 0U)
- 
 
 1149 
  __IO uint32_t tmpreg = 0U;
- 
 
 1150 
#endif /* USE_SPI_CRC */
1143 
 
 1151 
 
1144 
  /* Variable used to alternate Rx and Tx during transfer */
 1152 
  /* Variable used to alternate Rx and Tx during transfer */
1145 
  uint32_t             txallowed = 1U;
 1153 
  uint32_t             txallowed = 1U;
1146 
  HAL_StatusTypeDef    errorcode = HAL_OK;
 1154 
  HAL_StatusTypeDef    errorcode = HAL_OK;
1147 
 
 1155 
 
Line 1308... Line 1316...
1308 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 1316 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1309 
      errorcode = HAL_TIMEOUT;
 1317 
      errorcode = HAL_TIMEOUT;
1310 
      goto error;
 1318 
      goto error;
1311 
    }
 1319 
    }
1312 
    /* Read CRC */
 1320 
    /* Read CRC */
1313 
    READ_REG(hspi->Instance->DR);
 1321 
    tmpreg = READ_REG(hspi->Instance->DR);
- 
 
 1322 
    /* To avoid GCC warning */
- 
 
 1323 
    UNUSED(tmpreg);
1314 
  }
 1324 
  }
1315 
 
 1325 
 
1316 
  /* Check if CRC error occurred */
 1326 
  /* Check if CRC error occurred */
1317 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
 1327 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1318 
  {
 1328 
  {
Line 2737... Line 2747...
2737 
  */
 2747 
  */
2738 
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 2748 
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
2739 
{
 2749 
{
2740 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2750 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2741 
  uint32_t tickstart;
 2751 
  uint32_t tickstart;
- 
 
 2752 
#if (USE_SPI_CRC != 0U)
- 
 
 2753 
  __IO uint32_t tmpreg = 0U;
- 
 
 2754 
#endif /* USE_SPI_CRC */
2742 
 
 2755 
 
2743 
  /* Init tickstart for timeout management*/
 2756 
  /* Init tickstart for timeout management*/
2744 
  tickstart = HAL_GetTick();
 2757 
  tickstart = HAL_GetTick();
2745 
 
 2758 
 
2746 
  /* DMA Normal Mode */
 2759 
  /* DMA Normal Mode */
Line 2758... Line 2771...
2758 
      {
 2771 
      {
2759 
        /* Error on the CRC reception */
 2772 
        /* Error on the CRC reception */
2760 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 2773 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2761 
      }
 2774 
      }
2762 
      /* Read CRC */
 2775 
      /* Read CRC */
2763 
      READ_REG(hspi->Instance->DR);
 2776 
      tmpreg = READ_REG(hspi->Instance->DR);
- 
 
 2777 
      /* To avoid GCC warning */
- 
 
 2778 
      UNUSED(tmpreg);
2764 
    }
 2779 
    }
2765 
#endif /* USE_SPI_CRC */
 2780 
#endif /* USE_SPI_CRC */
2766 
 
 2781 
 
2767 
    /* Check if we are in Master RX 2 line mode */
 2782 
    /* Check if we are in Master RX 2 line mode */
2768 
    if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
 2783 
    if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
Line 2821... Line 2836...
2821 
  */
 2836 
  */
2822 
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
 2837 
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2823 
{
 2838 
{
2824 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2839 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2825 
  uint32_t tickstart;
 2840 
  uint32_t tickstart;
- 
 
 2841 
#if (USE_SPI_CRC != 0U)
- 
 
 2842 
  __IO uint32_t tmpreg = 0U;
- 
 
 2843 
#endif /* USE_SPI_CRC */
2826 
 
 2844 
 
2827 
  /* Init tickstart for timeout management*/
 2845 
  /* Init tickstart for timeout management*/
2828 
  tickstart = HAL_GetTick();
 2846 
  tickstart = HAL_GetTick();
2829 
 
 2847 
 
2830 
  /* DMA Normal Mode */
 2848 
  /* DMA Normal Mode */
Line 2841... Line 2859...
2841 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2859 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2842 
      {
 2860 
      {
2843 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 2861 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2844 
      }
 2862 
      }
2845 
      /* Read CRC to Flush DR and RXNE flag */
 2863 
      /* Read CRC to Flush DR and RXNE flag */
2846 
      READ_REG(hspi->Instance->DR);
 2864 
      tmpreg = READ_REG(hspi->Instance->DR);
- 
 
 2865 
      /* To avoid GCC warning */
- 
 
 2866 
      UNUSED(tmpreg);
2847 
    }
 2867 
    }
2848 
#endif /* USE_SPI_CRC */
 2868 
#endif /* USE_SPI_CRC */
2849 
 
 2869 
 
2850 
    /* Check the end of the transaction */
 2870 
    /* Check the end of the transaction */
2851 
    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2871 
    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
Line 3156... Line 3176...
3156 
  *               the configuration information for SPI module.
 3176 
  *               the configuration information for SPI module.
3157 
  * @retval None
 3177 
  * @retval None
3158 
  */
 3178 
  */
3159 
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
 3179 
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3160 
{
 3180 
{
- 
 
 3181 
  __IO uint8_t  * ptmpreg8;
- 
 
 3182 
  __IO uint8_t  tmpreg8 = 0;
- 
 
 3183 
 
- 
 
 3184 
  /* Initialize the 8bit temporary pointer */
- 
 
 3185 
  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3161 
  /* Read 8bit CRC to flush Data Register */
 3186 
  /* Read 8bit CRC to flush Data Register */
- 
 
 3187 
  tmpreg8 = *ptmpreg8;
3162 
  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
 3188 
  /* To avoid GCC warning */
- 
 
 3189 
  UNUSED(tmpreg8);
3163 
 
 3190 
 
3164 
  /* Disable RXNE and ERR interrupt */
 3191 
  /* Disable RXNE and ERR interrupt */
3165 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 3192 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3166 
 
 3193 
 
3167 
  if (hspi->TxXferCount == 0U)
 3194 
  if (hspi->TxXferCount == 0U)
Line 3247... Line 3274...
3247 
  *               the configuration information for SPI module.
 3274 
  *               the configuration information for SPI module.
3248 
  * @retval None
 3275 
  * @retval None
3249 
  */
 3276 
  */
3250 
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
 3277 
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3251 
{
 3278 
{
- 
 
 3279 
  __IO uint32_t tmpreg = 0U;
- 
 
 3280 
 
3252 
  /* Read 16bit CRC to flush Data Register */
 3281 
  /* Read 16bit CRC to flush Data Register */
3253 
  READ_REG(hspi->Instance->DR);
 3282 
  tmpreg = READ_REG(hspi->Instance->DR);
- 
 
 3283 
  /* To avoid GCC warning */
- 
 
 3284 
  UNUSED(tmpreg);  
3254 
 
 3285 
 
3255 
  /* Disable RXNE interrupt */
 3286 
  /* Disable RXNE interrupt */
3256 
  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
 3287 
  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3257 
 
 3288 
 
3258 
  SPI_CloseRxTx_ISR(hspi);
 3289 
  SPI_CloseRxTx_ISR(hspi);
Line 3303... Line 3334...
3303 
  *               the configuration information for SPI module.
 3334 
  *               the configuration information for SPI module.
3304 
  * @retval None
 3335 
  * @retval None
3305 
  */
 3336 
  */
3306 
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
 3337 
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3307 
{
 3338 
{
- 
 
 3339 
  __IO uint8_t  * ptmpreg8;
- 
 
 3340 
  __IO uint8_t  tmpreg8 = 0;
- 
 
 3341 
 
- 
 
 3342 
  /* Initialize the 8bit temporary pointer */
- 
 
 3343 
  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3308 
  /* Read 8bit CRC to flush Data Register */
 3344 
  /* Read 8bit CRC to flush Data Register */
- 
 
 3345 
  tmpreg8 = *ptmpreg8;
3309 
  READ_REG(*(__IO uint8_t *)&hspi->Instance->DR);
 3346 
  /* To avoid GCC warning */
- 
 
 3347 
  UNUSED(tmpreg8);
3310 
 
 3348 
 
3311 
  SPI_CloseRx_ISR(hspi);
 3349 
  SPI_CloseRx_ISR(hspi);
3312 
}
 3350 
}
3313 
#endif /* USE_SPI_CRC */
 3351 
#endif /* USE_SPI_CRC */
3314 
 
 3352 
 
Line 3352... Line 3390...
3352 
  *               the configuration information for SPI module.
 3390 
  *               the configuration information for SPI module.
3353 
  * @retval None
 3391 
  * @retval None
3354 
  */
 3392 
  */
3355 
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
 3393 
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3356 
{
 3394 
{
- 
 
 3395 
  __IO uint32_t tmpreg = 0U;
- 
 
 3396 
 
3357 
  /* Read 16bit CRC to flush Data Register */
 3397 
  /* Read 16bit CRC to flush Data Register */
3358 
  READ_REG(hspi->Instance->DR);
 3398 
  tmpreg = READ_REG(hspi->Instance->DR);
- 
 
 3399 
  /* To avoid GCC warning */
- 
 
 3400 
  UNUSED(tmpreg);
3359 
 
 3401 
 
3360 
  /* Disable RXNE and ERR interrupt */
 3402 
  /* Disable RXNE and ERR interrupt */
3361 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 3403 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3362 
 
 3404 
 
3363 
  SPI_CloseRx_ISR(hspi);
 3405 
  SPI_CloseRx_ISR(hspi);
Line 3834... Line 3876...
3834 
  *               the configuration information for SPI module.
 3876 
  *               the configuration information for SPI module.
3835 
  * @retval None
 3877 
  * @retval None
3836 
  */
 3878 
  */
3837 
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
 3879 
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
3838 
{
 3880 
{
- 
 
 3881 
  __IO uint32_t tmpreg = 0U;
3839 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 3882 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3840 
 
 3883 
 
3841 
  /* Wait until TXE flag is set */
 3884 
  /* Wait until TXE flag is set */
3842 
  do
 3885 
  do
3843 
  {
 3886 
  {
Line 3853... Line 3896...
3853 
  __HAL_SPI_DISABLE(hspi);
 3896 
  __HAL_SPI_DISABLE(hspi);
3854 
 
 3897 
 
3855 
  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
 3898 
  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
3856 
  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
 3899 
  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
3857 
 
 3900 
 
3858 
  /* Read CRC to flush Data Register */
 3901 
  /* Flush Data Register by a blank read */
3859 
  READ_REG(hspi->Instance->DR);
 3902 
  tmpreg = READ_REG(hspi->Instance->DR);
- 
 
 3903 
  /* To avoid GCC warning */
- 
 
 3904 
  UNUSED(tmpreg);
3860 
 
 3905 
 
3861 
  hspi->State = HAL_SPI_STATE_ABORT;
 3906 
  hspi->State = HAL_SPI_STATE_ABORT;
3862 
}
 3907 
}
3863 
 
 3908 
 
3864 
/**
 3909 
/**