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/**
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/**
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  ******************************************************************************
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  ******************************************************************************
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  * @file    stm32l1xx_hal_spi.c
 3 
  * @file    stm32l1xx_hal_spi.c
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  * @author  MCD Application Team
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  * @author  MCD Application Team
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  * @brief   SPI HAL module driver.
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  * @brief   SPI HAL module driver.
6 
  *          This file provides firmware functions to manage the following
 6 
  *          This file provides firmware functions to manage the following
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  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
 7 
  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
8 
  *           + Initialization and de-initialization functions
 8 
  *           + Initialization and de-initialization functions
9 
  *           + IO operation functions
 9 
  *           + IO operation functions
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  *           + Peripheral Control functions
 10 
  *           + Peripheral Control functions
11 
  *           + Peripheral State functions
 11 
  *           + Peripheral State functions
12 
  *
 12 
  ******************************************************************************
13 
  @verbatim
 13 
  * @attention
14 
  ==============================================================================
 14 
  *
15 
                        ##### How to use this driver #####
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  * Copyright (c) 2016 STMicroelectronics.
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  ==============================================================================
 16 
  * All rights reserved.
17 
    [..]
 17 
  *
18 
      The SPI HAL driver can be used as follows:
 18 
  * This software is licensed under terms that can be found in the LICENSE file
19 
 
 19 
  * in the root directory of this software component.
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      (#) Declare a SPI_HandleTypeDef handle structure, for example:
 20 
  * If no LICENSE file comes with this software, it is provided AS-IS.
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          SPI_HandleTypeDef  hspi;
 21 
  *
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 22 
  ******************************************************************************
23 
      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
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  @verbatim
24 
          (##) Enable the SPIx interface clock
 24 
  ==============================================================================
25 
          (##) SPI pins configuration
 25 
                        ##### How to use this driver #####
26 
              (+++) Enable the clock for the SPI GPIOs
 26 
  ==============================================================================
27 
              (+++) Configure these SPI pins as alternate function push-pull
 27 
    [..]
28 
          (##) NVIC configuration if you need to use interrupt process
 28 
      The SPI HAL driver can be used as follows:
29 
              (+++) Configure the SPIx interrupt priority
 29 
 
30 
              (+++) Enable the NVIC SPI IRQ handle
 30 
      (#) Declare a SPI_HandleTypeDef handle structure, for example:
31 
          (##) DMA Configuration if you need to use DMA process
 31 
          SPI_HandleTypeDef  hspi;
32 
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
 32 
 
33 
              (+++) Enable the DMAx clock
 33 
      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API:
34 
              (+++) Configure the DMA handle parameters
 34 
          (##) Enable the SPIx interface clock
35 
              (+++) Configure the DMA Tx or Rx Stream/Channel
 35 
          (##) SPI pins configuration
36 
              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
 36 
              (+++) Enable the clock for the SPI GPIOs
37 
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
 37 
              (+++) Configure these SPI pins as alternate function push-pull
38 
 
 38 
          (##) NVIC configuration if you need to use interrupt process
39 
      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
 39 
              (+++) Configure the SPIx interrupt priority
40 
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
 40 
              (+++) Enable the NVIC SPI IRQ handle
41 
 
 41 
          (##) DMA Configuration if you need to use DMA process
42 
      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
 42 
              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel
43 
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
 43 
              (+++) Enable the DMAx clock
44 
              by calling the customized HAL_SPI_MspInit() API.
 44 
              (+++) Configure the DMA handle parameters
45 
     [..]
 45 
              (+++) Configure the DMA Tx or Rx Stream/Channel
46 
       Circular mode restriction:
 46 
              (+++) Associate the initialized hdma_tx(or _rx)  handle to the hspi DMA Tx or Rx handle
47 
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
 47 
              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel
48 
          (##) Master 2Lines RxOnly
 48 
 
49 
          (##) Master 1Line Rx
 49 
      (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS
50 
      (#) The CRC feature is not managed when the DMA circular mode is enabled
 50 
          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
51 
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
 51 
 
52 
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
 52 
      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
53 
     [..]
 53 
          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
54 
       Master Receive mode restriction:
 54 
              by calling the customized HAL_SPI_MspInit() API.
55 
      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
 55 
     [..]
56 
          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
 56 
       Circular mode restriction:
57 
          does not initiate a new transfer the following procedure has to be respected:
 57 
      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
58 
          (##) HAL_SPI_DeInit()
 58 
          (##) Master 2Lines RxOnly
59 
          (##) HAL_SPI_Init()
 59 
          (##) Master 1Line Rx
60 
     [..]
 60 
      (#) The CRC feature is not managed when the DMA circular mode is enabled
61 
       Callback registration:
 61 
      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs
62 
 
 62 
          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
63 
      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
 63 
     [..]
64 
          allows the user to configure dynamically the driver callbacks.
 64 
       Master Receive mode restriction:
65 
          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
 65 
      (#) In Master unidirectional receive-only mode (MSTR =1, BIDIMODE=0, RXONLY=1) or
66 
 
 66 
          bidirectional receive mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI
67 
          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
 67 
          does not initiate a new transfer the following procedure has to be respected:
68 
            (++) TxCpltCallback        : SPI Tx Completed callback
 68 
          (##) HAL_SPI_DeInit()
69 
            (++) RxCpltCallback        : SPI Rx Completed callback
 69 
          (##) HAL_SPI_Init()
70 
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
 70 
     [..]
71 
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
 71 
       Callback registration:
72 
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
 72 
 
73 
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
 73 
      (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1U
74 
            (++) ErrorCallback         : SPI Error callback
 74 
          allows the user to configure dynamically the driver callbacks.
75 
            (++) AbortCpltCallback     : SPI Abort callback
 75 
          Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
76 
            (++) MspInitCallback       : SPI Msp Init callback
 76 
 
77 
            (++) MspDeInitCallback     : SPI Msp DeInit callback
 77 
          Function HAL_SPI_RegisterCallback() allows to register following callbacks:
78 
          This function takes as parameters the HAL peripheral handle, the Callback ID
 78 
            (++) TxCpltCallback        : SPI Tx Completed callback
79 
          and a pointer to the user callback function.
 79 
            (++) RxCpltCallback        : SPI Rx Completed callback
80 
 
 80 
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
81 
 
 81 
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
82 
      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
 82 
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
83 
          weak function.
 83 
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
84 
          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
 84 
            (++) ErrorCallback         : SPI Error callback
85 
          and the Callback ID.
 85 
            (++) AbortCpltCallback     : SPI Abort callback
86 
          This function allows to reset following callbacks:
 86 
            (++) MspInitCallback       : SPI Msp Init callback
87 
            (++) TxCpltCallback        : SPI Tx Completed callback
 87 
            (++) MspDeInitCallback     : SPI Msp DeInit callback
88 
            (++) RxCpltCallback        : SPI Rx Completed callback
 88 
          This function takes as parameters the HAL peripheral handle, the Callback ID
89 
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
 89 
          and a pointer to the user callback function.
90 
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
 90 
 
91 
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
 91 
 
92 
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
 92 
      (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default
93 
            (++) ErrorCallback         : SPI Error callback
 93 
          weak function.
94 
            (++) AbortCpltCallback     : SPI Abort callback
 94 
          HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
95 
            (++) MspInitCallback       : SPI Msp Init callback
 95 
          and the Callback ID.
96 
            (++) MspDeInitCallback     : SPI Msp DeInit callback
 96 
          This function allows to reset following callbacks:
97 
 
 97 
            (++) TxCpltCallback        : SPI Tx Completed callback
98 
       [..]
 98 
            (++) RxCpltCallback        : SPI Rx Completed callback
99 
       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
 99 
            (++) TxRxCpltCallback      : SPI TxRx Completed callback
100 
       all callbacks are set to the corresponding weak functions:
 100 
            (++) TxHalfCpltCallback    : SPI Tx Half Completed callback
101 
       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
 101 
            (++) RxHalfCpltCallback    : SPI Rx Half Completed callback
102 
       Exception done for MspInit and MspDeInit functions that are
 102 
            (++) TxRxHalfCpltCallback  : SPI TxRx Half Completed callback
103 
       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
 103 
            (++) ErrorCallback         : SPI Error callback
104 
       these callbacks are null (not registered beforehand).
 104 
            (++) AbortCpltCallback     : SPI Abort callback
105 
       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
 105 
            (++) MspInitCallback       : SPI Msp Init callback
106 
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
 106 
            (++) MspDeInitCallback     : SPI Msp DeInit callback
107 
 
 107 
 
108 
       [..]
 108 
       [..]
109 
       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
 109 
       By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
110 
       Exception done MspInit/MspDeInit functions that can be registered/unregistered
 110 
       all callbacks are set to the corresponding weak functions:
111 
       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
 111 
       examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
112 
       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
 112 
       Exception done for MspInit and MspDeInit functions that are
113 
       Then, the user first registers the MspInit/MspDeInit user callbacks
 113 
       reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when
114 
       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
 114 
       these callbacks are null (not registered beforehand).
115 
       or HAL_SPI_Init() function.
 115 
       If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
116 
 
 116 
       keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
117 
       [..]
 117 
 
118 
       When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
 118 
       [..]
119 
       not defined, the callback registering feature is not available
 119 
       Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
120 
       and weak (surcharged) callbacks are used.
 120 
       Exception done MspInit/MspDeInit functions that can be registered/unregistered
121 
 
 121 
       in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
122 
     [..]
 122 
       thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
123 
       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
 123 
       Then, the user first registers the MspInit/MspDeInit user callbacks
124 
       the following table resume the max SPI frequency reached with data size 8bits/16bits,
 124 
       using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
125 
         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
 125 
       or HAL_SPI_Init() function.
126 
 
 126 
 
127 
  @endverbatim
 127 
       [..]
128 
 
 128 
       When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
129 
  Additional table :
 129 
       not defined, the callback registering feature is not available
130 
 
 130 
       and weak (surcharged) callbacks are used.
131 
       DataSize = SPI_DATASIZE_8BIT:
 131 
 
132 
       +----------------------------------------------------------------------------------------------+
 132 
     [..]
133 
       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
 133 
       Using the HAL it is not possible to reach all supported SPI frequency with the different SPI Modes,
134 
       | Process | Transfer mode  |---------------------|----------------------|----------------------|
 134 
       the following table resume the max SPI frequency reached with data size 8bits/16bits,
135 
       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
 135 
         according to frequency of the APBx Peripheral Clock (fPCLK) used by the SPI instance.
136 
       |==============================================================================================|
 136 
 
137 
       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
 137 
  @endverbatim
138 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 138 
 
139 
       |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
 139 
  Additional table :
140 
       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
 140 
 
141 
       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
 141 
       DataSize = SPI_DATASIZE_8BIT:
142 
       |=========|================|==========|==========|===========|==========|===========|==========|
 142 
       +----------------------------------------------------------------------------------------------+
143 
       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
 143 
       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
144 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
 144 
       | Process | Transfer mode  |---------------------|----------------------|----------------------|
145 
       |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
 145 
       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
146 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 146 
       |==============================================================================================|
147 
       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
 147 
       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
148 
       |=========|================|==========|==========|===========|==========|===========|==========|
 148 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
149 
       |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
 149 
       |    /    |     Interrupt  | Fpclk/4  | Fpclk/8  |    NA     |    NA    |    NA     |   NA     |
150 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
 150 
       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
151 
       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
 151 
       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
152 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 152 
       |=========|================|==========|==========|===========|==========|===========|==========|
153 
       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
 153 
       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
154 
       +----------------------------------------------------------------------------------------------+
 154 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
155 
 
 155 
       |    R    |     Interrupt  | Fpclk/8  | Fpclk/8  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
156 
       DataSize = SPI_DATASIZE_16BIT:
 156 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
157 
       +----------------------------------------------------------------------------------------------+
 157 
       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
158 
       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
 158 
       |=========|================|==========|==========|===========|==========|===========|==========|
159 
       | Process | Transfer mode  |---------------------|----------------------|----------------------|
 159 
       |         |     Polling    | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
160 
       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
 160 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
161 
       |==============================================================================================|
 161 
       |    T    |     Interrupt  | Fpclk/2  | Fpclk/4  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
162 
       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
 162 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
163 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 163 
       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
164 
       |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |
 164 
       +----------------------------------------------------------------------------------------------+
165 
       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
 165 
 
166 
       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
 166 
       DataSize = SPI_DATASIZE_16BIT:
167 
       |=========|================|==========|==========|===========|==========|===========|==========|
 167 
       +----------------------------------------------------------------------------------------------+
168 
       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |
 168 
       |         |                | 2Lines Fullduplex   |     2Lines RxOnly    |         1Line        |
169 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
 169 
       | Process | Transfer mode  |---------------------|----------------------|----------------------|
170 
       |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
 170 
       |         |                |  Master  |  Slave   |  Master   |  Slave   |  Master   |  Slave   |
171 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 171 
       |==============================================================================================|
172 
       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
 172 
       |    T    |     Polling    | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
173 
       |=========|================|==========|==========|===========|==========|===========|==========|
 173 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
174 
       |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |
 174 
       |    /    |     Interrupt  | Fpclk/4  | Fpclk/4  |    NA     |    NA    |    NA     |   NA     |
175 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
 175 
       |    R    |----------------|----------|----------|-----------|----------|-----------|----------|
176 
       |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
 176 
       |    X    |       DMA      | Fpclk/2  | Fpclk/2  |    NA     |    NA    |    NA     |   NA     |
177 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
 177 
       |=========|================|==========|==========|===========|==========|===========|==========|
178 
       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
 178 
       |         |     Polling    | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/32  | Fpclk/2  |
179 
       +----------------------------------------------------------------------------------------------+
 179 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
180 
       @note The max SPI frequency depend on SPI data size (8bits, 16bits),
 180 
       |    R    |     Interrupt  | Fpclk/4  | Fpclk/4  | Fpclk/64  | Fpclk/2  | Fpclk/64  | Fpclk/2  |
181 
             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
 181 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
182 
       @note
 182 
       |         |       DMA      | Fpclk/2  | Fpclk/2  | Fpclk/64  | Fpclk/2  | Fpclk/128 | Fpclk/2  |
183 
            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
 183 
       |=========|================|==========|==========|===========|==========|===========|==========|
184 
            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
 184 
       |         |     Polling    | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/32 |
185 
            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
 185 
       |         |----------------|----------|----------|-----------|----------|-----------|----------|
186 
 
 186 
       |    T    |     Interrupt  | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/64 |
187 
  ******************************************************************************
 187 
       |    X    |----------------|----------|----------|-----------|----------|-----------|----------|
188 
  * @attention
 188 
       |         |       DMA      | Fpclk/2  | Fpclk/2  |     NA    |    NA    | Fpclk/2   | Fpclk/128|
189 
  *
 189 
       +----------------------------------------------------------------------------------------------+
190 
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
 190 
       @note The max SPI frequency depend on SPI data size (8bits, 16bits),
191 
  * All rights reserved.</center></h2>
 191 
             SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA).
192 
  *
 192 
       @note
193 
  * This software component is licensed by ST under BSD 3-Clause license,
 193 
            (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA()
194 
  * the "License"; You may not use this file except in compliance with the
 194 
            (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA()
195 
  * License. You may obtain a copy of the License at:
 195 
            (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA()
196 
  *                        opensource.org/licenses/BSD-3-Clause
 196 
 
197 
  *
 197 
  */
198 
  ******************************************************************************
 198 
 
199 
  */
 199 
/* Includes ------------------------------------------------------------------*/
200 
 
 200 
#include "stm32l1xx_hal.h"
201 
/* Includes ------------------------------------------------------------------*/
 201 
 
202 
#include "stm32l1xx_hal.h"
 202 
/** @addtogroup STM32L1xx_HAL_Driver
203 
 
 203 
  * @{
204 
/** @addtogroup STM32L1xx_HAL_Driver
 204 
  */
205 
  * @{
 205 
 
206 
  */
 206 
/** @defgroup SPI SPI
207 
 
 207 
  * @brief SPI HAL module driver
208 
/** @defgroup SPI SPI
 208 
  * @{
209 
  * @brief SPI HAL module driver
 209 
  */
210 
  * @{
 210 
#ifdef HAL_SPI_MODULE_ENABLED
211 
  */
 211 
 
212 
#ifdef HAL_SPI_MODULE_ENABLED
 212 
/* Private typedef -----------------------------------------------------------*/
213 
 
 213 
/* Private defines -----------------------------------------------------------*/
214 
/* Private typedef -----------------------------------------------------------*/
 214 
/** @defgroup SPI_Private_Constants SPI Private Constants
215 
/* Private defines -----------------------------------------------------------*/
 215 
  * @{
216 
/** @defgroup SPI_Private_Constants SPI Private Constants
 216 
  */
217 
  * @{
 217 
#define SPI_DEFAULT_TIMEOUT 100U
218 
  */
 218 
#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs             */
219 
#define SPI_DEFAULT_TIMEOUT 100U
 219 
/**
220 
#define SPI_BSY_FLAG_WORKAROUND_TIMEOUT 1000U /*!< Timeout 1000 µs             */
 220 
  * @}
221 
/**
 221 
  */
222 
  * @}
 222 
 
223 
  */
 223 
/* Private macros ------------------------------------------------------------*/
224 
 
 224 
/* Private variables ---------------------------------------------------------*/
225 
/* Private macros ------------------------------------------------------------*/
 225 
/* Private function prototypes -----------------------------------------------*/
226 
/* Private variables ---------------------------------------------------------*/
 226 
/** @defgroup SPI_Private_Functions SPI Private Functions
227 
/* Private function prototypes -----------------------------------------------*/
 227 
  * @{
228 
/** @defgroup SPI_Private_Functions SPI Private Functions
 228 
  */
229 
  * @{
 229 
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
230 
  */
 230 
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
231 
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma);
 231 
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
232 
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
 232 
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
233 
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma);
 233 
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
234 
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma);
 234 
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
235 
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma);
 235 
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
236 
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma);
 236 
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
237 
static void SPI_DMAError(DMA_HandleTypeDef *hdma);
 237 
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
238 
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma);
 238 
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
239 
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
 239 
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
240 
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
 240 
                                                       uint32_t Timeout, uint32_t Tickstart);
241 
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
 241 
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
242 
                                                       uint32_t Timeout, uint32_t Tickstart);
 242 
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
243 
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
 243 
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
244 
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
 244 
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
245 
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
 245 
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
246 
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
 246 
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
247 
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
 247 
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
248 
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
 248 
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
249 
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
 249 
#if (USE_SPI_CRC != 0U)
250 
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
 250 
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
251 
#if (USE_SPI_CRC != 0U)
 251 
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
252 
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
 252 
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
253 
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
 253 
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
254 
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi);
 254 
#endif /* USE_SPI_CRC */
255 
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi);
 255 
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
256 
#endif /* USE_SPI_CRC */
 256 
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
257 
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi);
 257 
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
258 
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi);
 258 
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
259 
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi);
 259 
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
260 
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi);
 260 
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
261 
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi);
 261 
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
262 
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
 262 
/**
263 
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
 263 
  * @}
264 
/**
 264 
  */
265 
  * @}
 265 
 
266 
  */
 266 
/* Exported functions --------------------------------------------------------*/
267 
 
 267 
/** @defgroup SPI_Exported_Functions SPI Exported Functions
268 
/* Exported functions --------------------------------------------------------*/
 268 
  * @{
269 
/** @defgroup SPI_Exported_Functions SPI Exported Functions
 269 
  */
270 
  * @{
 270 
 
271 
  */
 271 
/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
272 
 
 272 
  *  @brief    Initialization and Configuration functions
273 
/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
 273 
  *
274 
  *  @brief    Initialization and Configuration functions
 274 
@verbatim
275 
  *
 275 
 ===============================================================================
276 
@verbatim
 276 
              ##### Initialization and de-initialization functions #####
277 
 ===============================================================================
 277 
 ===============================================================================
278 
              ##### Initialization and de-initialization functions #####
 278 
    [..]  This subsection provides a set of functions allowing to initialize and
279 
 ===============================================================================
 279 
          de-initialize the SPIx peripheral:
280 
    [..]  This subsection provides a set of functions allowing to initialize and
 280 
 
281 
          de-initialize the SPIx peripheral:
 281 
      (+) User must implement HAL_SPI_MspInit() function in which he configures
282 
 
 282 
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
283 
      (+) User must implement HAL_SPI_MspInit() function in which he configures
 283 
 
284 
          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
 284 
      (+) Call the function HAL_SPI_Init() to configure the selected device with
285 
 
 285 
          the selected configuration:
286 
      (+) Call the function HAL_SPI_Init() to configure the selected device with
 286 
        (++) Mode
287 
          the selected configuration:
 287 
        (++) Direction
288 
        (++) Mode
 288 
        (++) Data Size
289 
        (++) Direction
 289 
        (++) Clock Polarity and Phase
290 
        (++) Data Size
 290 
        (++) NSS Management
291 
        (++) Clock Polarity and Phase
 291 
        (++) BaudRate Prescaler
292 
        (++) NSS Management
 292 
        (++) FirstBit
293 
        (++) BaudRate Prescaler
 293 
        (++) TIMode
294 
        (++) FirstBit
 294 
        (++) CRC Calculation
295 
        (++) TIMode
 295 
        (++) CRC Polynomial if CRC enabled
296 
        (++) CRC Calculation
 296 
 
297 
        (++) CRC Polynomial if CRC enabled
 297 
      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
298 
 
 298 
          of the selected SPIx peripheral.
299 
      (+) Call the function HAL_SPI_DeInit() to restore the default configuration
 299 
 
300 
          of the selected SPIx peripheral.
 300 
@endverbatim
301 
 
 301 
  * @{
302 
@endverbatim
 302 
  */
303 
  * @{
 303 
 
304 
  */
 304 
/**
305 
 
 305 
  * @brief  Initialize the SPI according to the specified parameters
306 
/**
 306 
  *         in the SPI_InitTypeDef and initialize the associated handle.
307 
  * @brief  Initialize the SPI according to the specified parameters
 307 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
308 
  *         in the SPI_InitTypeDef and initialize the associated handle.
 308 
  *               the configuration information for SPI module.
309 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 309 
  * @retval HAL status
310 
  *               the configuration information for SPI module.
 310 
  */
311 
  * @retval HAL status
 311 
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
312 
  */
 312 
{
313 
HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
 313 
  /* Check the SPI handle allocation */
314 
{
 314 
  if (hspi == NULL)
315 
  /* Check the SPI handle allocation */
 315 
  {
316 
  if (hspi == NULL)
 316 
    return HAL_ERROR;
317 
  {
 317 
  }
318 
    return HAL_ERROR;
 318 
 
319 
  }
 319 
  /* Check the parameters */
320 
 
 320 
  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
321 
  /* Check the parameters */
 321 
  assert_param(IS_SPI_MODE(hspi->Init.Mode));
322 
  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
 322 
  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
323 
  assert_param(IS_SPI_MODE(hspi->Init.Mode));
 323 
  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
324 
  assert_param(IS_SPI_DIRECTION(hspi->Init.Direction));
 324 
  assert_param(IS_SPI_NSS(hspi->Init.NSS));
325 
  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
 325 
  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
326 
  assert_param(IS_SPI_NSS(hspi->Init.NSS));
 326 
  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
327 
  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
 327 
  /* TI mode is not supported on all devices in stm32l1xx series.
328 
  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
 328 
     TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */
329 
  /* TI mode is not supported on all devices in stm32l1xx serie.
 329 
  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
330 
     TIMode parameter is mandatory equal to SPI_TIMODE_DISABLE if TI mode is not supported */
 330 
  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
331 
  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
 331 
  {
332 
  if (hspi->Init.TIMode == SPI_TIMODE_DISABLE)
 332 
    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
333 
  {
 333 
    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
334 
    assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
 334 
 
335 
    assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
 335 
    if (hspi->Init.Mode == SPI_MODE_MASTER)
336 
 
 336 
    {
337 
    if (hspi->Init.Mode == SPI_MODE_MASTER)
 337 
      assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
338 
    {
 338 
    }
339 
      assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
 339 
    else
340 
    }
 340 
    {
341 
    else
 341 
      /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
342 
    {
 342 
      hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
343 
      /* Baudrate prescaler not use in Motoraola Slave mode. force to default value */
 343 
    }
344 
      hspi->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2;
 344 
  }
345 
    }
 345 
  else
346 
  }
 346 
  {
347 
  else
 347 
    assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
348 
  {
 348 
 
349 
    assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
 349 
    /* Force polarity and phase to TI protocaol requirements */
350 
 
 350 
    hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
351 
    /* Force polarity and phase to TI protocaol requirements */
 351 
    hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
352 
    hspi->Init.CLKPolarity = SPI_POLARITY_LOW;
 352 
  }
353 
    hspi->Init.CLKPhase    = SPI_PHASE_1EDGE;
 353 
#if (USE_SPI_CRC != 0U)
354 
  }
 354 
  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
355 
#if (USE_SPI_CRC != 0U)
 355 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
356 
  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
 356 
  {
357 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 357 
    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
358 
  {
 358 
  }
359 
    assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
 359 
#else
360 
  }
 360 
  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
361 
#else
 361 
#endif /* USE_SPI_CRC */
362 
  hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE;
 362 
 
363 
#endif /* USE_SPI_CRC */
 363 
  if (hspi->State == HAL_SPI_STATE_RESET)
364 
 
 364 
  {
365 
  if (hspi->State == HAL_SPI_STATE_RESET)
 365 
    /* Allocate lock resource and initialize it */
366 
  {
 366 
    hspi->Lock = HAL_UNLOCKED;
367 
    /* Allocate lock resource and initialize it */
 367 
 
368 
    hspi->Lock = HAL_UNLOCKED;
 368 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
369 
 
 369 
    /* Init the SPI Callback settings */
370 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 370 
    hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
371 
    /* Init the SPI Callback settings */
 371 
    hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
372 
    hspi->TxCpltCallback       = HAL_SPI_TxCpltCallback;       /* Legacy weak TxCpltCallback       */
 372 
    hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
373 
    hspi->RxCpltCallback       = HAL_SPI_RxCpltCallback;       /* Legacy weak RxCpltCallback       */
 373 
    hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
374 
    hspi->TxRxCpltCallback     = HAL_SPI_TxRxCpltCallback;     /* Legacy weak TxRxCpltCallback     */
 374 
    hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
375 
    hspi->TxHalfCpltCallback   = HAL_SPI_TxHalfCpltCallback;   /* Legacy weak TxHalfCpltCallback   */
 375 
    hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
376 
    hspi->RxHalfCpltCallback   = HAL_SPI_RxHalfCpltCallback;   /* Legacy weak RxHalfCpltCallback   */
 376 
    hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
377 
    hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
 377 
    hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
378 
    hspi->ErrorCallback        = HAL_SPI_ErrorCallback;        /* Legacy weak ErrorCallback        */
 378 
 
379 
    hspi->AbortCpltCallback    = HAL_SPI_AbortCpltCallback;    /* Legacy weak AbortCpltCallback    */
 379 
    if (hspi->MspInitCallback == NULL)
380 
 
 380 
    {
381 
    if (hspi->MspInitCallback == NULL)
 381 
      hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
382 
    {
 382 
    }
383 
      hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit  */
 383 
 
384 
    }
 384 
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
385 
 
 385 
    hspi->MspInitCallback(hspi);
386 
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
 386 
#else
387 
    hspi->MspInitCallback(hspi);
 387 
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
388 
#else
 388 
    HAL_SPI_MspInit(hspi);
389 
    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
 389 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
390 
    HAL_SPI_MspInit(hspi);
 390 
  }
391 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 391 
 
392 
  }
 392 
  hspi->State = HAL_SPI_STATE_BUSY;
393 
 
 393 
 
394 
  hspi->State = HAL_SPI_STATE_BUSY;
 394 
  /* Disable the selected SPI peripheral */
395 
 
 395 
  __HAL_SPI_DISABLE(hspi);
396 
  /* Disable the selected SPI peripheral */
 396 
 
397 
  __HAL_SPI_DISABLE(hspi);
 397 
  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
398 
 
 398 
  /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
399 
  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
 399 
  Communication speed, First bit and CRC calculation state */
400 
  /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
 400 
  WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
401 
  Communication speed, First bit and CRC calculation state */
 401 
                                  (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
402 
  WRITE_REG(hspi->Instance->CR1, ((hspi->Init.Mode & (SPI_CR1_MSTR | SPI_CR1_SSI)) |
 402 
                                  (hspi->Init.DataSize & SPI_CR1_DFF) |
403 
                                  (hspi->Init.Direction & (SPI_CR1_RXONLY | SPI_CR1_BIDIMODE)) |
 403 
                                  (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
404 
                                  (hspi->Init.DataSize & SPI_CR1_DFF) |
 404 
                                  (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
405 
                                  (hspi->Init.CLKPolarity & SPI_CR1_CPOL) |
 405 
                                  (hspi->Init.NSS & SPI_CR1_SSM) |
406 
                                  (hspi->Init.CLKPhase & SPI_CR1_CPHA) |
 406 
                                  (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
407 
                                  (hspi->Init.NSS & SPI_CR1_SSM) |
 407 
                                  (hspi->Init.FirstBit  & SPI_CR1_LSBFIRST) |
408 
                                  (hspi->Init.BaudRatePrescaler & SPI_CR1_BR_Msk) |
 408 
                                  (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
409 
                                  (hspi->Init.FirstBit  & SPI_CR1_LSBFIRST) |
 409 
 
410 
                                  (hspi->Init.CRCCalculation & SPI_CR1_CRCEN)));
 410 
#if defined(SPI_CR2_FRF)
411 
 
 411 
  /* Configure : NSS management, TI Mode */
412 
#if defined(SPI_CR2_FRF)
 412 
  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
413 
  /* Configure : NSS management, TI Mode */
 413 
#else
414 
  WRITE_REG(hspi->Instance->CR2, (((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE) | (hspi->Init.TIMode & SPI_CR2_FRF)));
 414 
  /* Configure : NSS management */
415 
#else
 415 
  WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
416 
  /* Configure : NSS management */
 416 
#endif /* SPI_CR2_FRF */
417 
  WRITE_REG(hspi->Instance->CR2, ((hspi->Init.NSS >> 16U) & SPI_CR2_SSOE));
 417 
 
418 
#endif
 418 
#if (USE_SPI_CRC != 0U)
419 
 
 419 
  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
420 
#if (USE_SPI_CRC != 0U)
 420 
  /* Configure : CRC Polynomial */
421 
  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
 421 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
422 
  /* Configure : CRC Polynomial */
 422 
  {
423 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 423 
    WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
424 
  {
 424 
  }
425 
    WRITE_REG(hspi->Instance->CRCPR, (hspi->Init.CRCPolynomial & SPI_CRCPR_CRCPOLY_Msk));
 425 
#endif /* USE_SPI_CRC */
426 
  }
 426 
 
427 
#endif /* USE_SPI_CRC */
 427 
#if defined(SPI_I2SCFGR_I2SMOD)
428 
 
 428 
  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
429 
#if defined(SPI_I2SCFGR_I2SMOD)
 429 
  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
430 
  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
 430 
#endif /* SPI_I2SCFGR_I2SMOD */
431 
  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
 431 
 
432 
#endif /* SPI_I2SCFGR_I2SMOD */
 432 
  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
433 
 
 433 
  hspi->State     = HAL_SPI_STATE_READY;
434 
  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 434 
 
435 
  hspi->State     = HAL_SPI_STATE_READY;
 435 
  return HAL_OK;
436 
 
 436 
}
437 
  return HAL_OK;
 437 
 
438 
}
 438 
/**
439 
 
 439 
  * @brief  De-Initialize the SPI peripheral.
440 
/**
 440 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
441 
  * @brief  De-Initialize the SPI peripheral.
 441 
  *               the configuration information for SPI module.
442 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 442 
  * @retval HAL status
443 
  *               the configuration information for SPI module.
 443 
  */
444 
  * @retval HAL status
 444 
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
445 
  */
 445 
{
446 
HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
 446 
  /* Check the SPI handle allocation */
447 
{
 447 
  if (hspi == NULL)
448 
  /* Check the SPI handle allocation */
 448 
  {
449 
  if (hspi == NULL)
 449 
    return HAL_ERROR;
450 
  {
 450 
  }
451 
    return HAL_ERROR;
 451 
 
452 
  }
 452 
  /* Check SPI Instance parameter */
453 
 
 453 
  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
454 
  /* Check SPI Instance parameter */
 454 
 
455 
  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
 455 
  hspi->State = HAL_SPI_STATE_BUSY;
456 
 
 456 
 
457 
  hspi->State = HAL_SPI_STATE_BUSY;
 457 
  /* Disable the SPI Peripheral Clock */
458 
 
 458 
  __HAL_SPI_DISABLE(hspi);
459 
  /* Disable the SPI Peripheral Clock */
 459 
 
460 
  __HAL_SPI_DISABLE(hspi);
 460 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
461 
 
 461 
  if (hspi->MspDeInitCallback == NULL)
462 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 462 
  {
463 
  if (hspi->MspDeInitCallback == NULL)
 463 
    hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
464 
  {
 464 
  }
465 
    hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit  */
 465 
 
466 
  }
 466 
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
467 
 
 467 
  hspi->MspDeInitCallback(hspi);
468 
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
 468 
#else
469 
  hspi->MspDeInitCallback(hspi);
 469 
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
470 
#else
 470 
  HAL_SPI_MspDeInit(hspi);
471 
  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
 471 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
472 
  HAL_SPI_MspDeInit(hspi);
 472 
 
473 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 473 
  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
474 
 
 474 
  hspi->State = HAL_SPI_STATE_RESET;
475 
  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 475 
 
476 
  hspi->State = HAL_SPI_STATE_RESET;
 476 
  /* Release Lock */
477 
 
 477 
  __HAL_UNLOCK(hspi);
478 
  /* Release Lock */
 478 
 
479 
  __HAL_UNLOCK(hspi);
 479 
  return HAL_OK;
480 
 
 480 
}
481 
  return HAL_OK;
 481 
 
482 
}
 482 
/**
483 
 
 483 
  * @brief  Initialize the SPI MSP.
484 
/**
 484 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
485 
  * @brief  Initialize the SPI MSP.
 485 
  *               the configuration information for SPI module.
486 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 486 
  * @retval None
487 
  *               the configuration information for SPI module.
 487 
  */
488 
  * @retval None
 488 
__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
489 
  */
 489 
{
490 
__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
 490 
  /* Prevent unused argument(s) compilation warning */
491 
{
 491 
  UNUSED(hspi);
492 
  /* Prevent unused argument(s) compilation warning */
 492 
 
493 
  UNUSED(hspi);
 493 
  /* NOTE : This function should not be modified, when the callback is needed,
494 
 
 494 
            the HAL_SPI_MspInit should be implemented in the user file
495 
  /* NOTE : This function should not be modified, when the callback is needed,
 495 
   */
496 
            the HAL_SPI_MspInit should be implemented in the user file
 496 
}
497 
   */
 497 
 
498 
}
 498 
/**
499 
 
 499 
  * @brief  De-Initialize the SPI MSP.
500 
/**
 500 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
501 
  * @brief  De-Initialize the SPI MSP.
 501 
  *               the configuration information for SPI module.
502 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 502 
  * @retval None
503 
  *               the configuration information for SPI module.
 503 
  */
504 
  * @retval None
 504 
__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
505 
  */
 505 
{
506 
__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
 506 
  /* Prevent unused argument(s) compilation warning */
507 
{
 507 
  UNUSED(hspi);
508 
  /* Prevent unused argument(s) compilation warning */
 508 
 
509 
  UNUSED(hspi);
 509 
  /* NOTE : This function should not be modified, when the callback is needed,
510 
 
 510 
            the HAL_SPI_MspDeInit should be implemented in the user file
511 
  /* NOTE : This function should not be modified, when the callback is needed,
 511 
   */
512 
            the HAL_SPI_MspDeInit should be implemented in the user file
 512 
}
513 
   */
 513 
 
514 
}
 514 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
515 
 
 515 
/**
516 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 516 
  * @brief  Register a User SPI Callback
517 
/**
 517 
  *         To be used instead of the weak predefined callback
518 
  * @brief  Register a User SPI Callback
 518 
  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
519 
  *         To be used instead of the weak predefined callback
 519 
  *                the configuration information for the specified SPI.
520 
  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
 520 
  * @param  CallbackID ID of the callback to be registered
521 
  *                the configuration information for the specified SPI.
 521 
  * @param  pCallback pointer to the Callback function
522 
  * @param  CallbackID ID of the callback to be registered
 522 
  * @retval HAL status
523 
  * @param  pCallback pointer to the Callback function
 523 
  */
524 
  * @retval HAL status
 524 
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
525 
  */
 525 
                                           pSPI_CallbackTypeDef pCallback)
526 
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
 526 
{
527 
                                           pSPI_CallbackTypeDef pCallback)
 527 
  HAL_StatusTypeDef status = HAL_OK;
528 
{
 528 
 
529 
  HAL_StatusTypeDef status = HAL_OK;
 529 
  if (pCallback == NULL)
530 
 
 530 
  {
531 
  if (pCallback == NULL)
 531 
    /* Update the error code */
532 
  {
 532 
    hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
533 
    /* Update the error code */
 533 
 
534 
    hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK;
 534 
    return HAL_ERROR;
535 
 
 535 
  }
536 
    return HAL_ERROR;
 536 
  /* Process locked */
537 
  }
 537 
  __HAL_LOCK(hspi);
538 
  /* Process locked */
 538 
 
539 
  __HAL_LOCK(hspi);
 539 
  if (HAL_SPI_STATE_READY == hspi->State)
540 
 
 540 
  {
541 
  if (HAL_SPI_STATE_READY == hspi->State)
 541 
    switch (CallbackID)
542 
  {
 542 
    {
543 
    switch (CallbackID)
 543 
      case HAL_SPI_TX_COMPLETE_CB_ID :
544 
    {
 544 
        hspi->TxCpltCallback = pCallback;
545 
      case HAL_SPI_TX_COMPLETE_CB_ID :
 545 
        break;
546 
        hspi->TxCpltCallback = pCallback;
 546 
 
547 
        break;
 547 
      case HAL_SPI_RX_COMPLETE_CB_ID :
548 
 
 548 
        hspi->RxCpltCallback = pCallback;
549 
      case HAL_SPI_RX_COMPLETE_CB_ID :
 549 
        break;
550 
        hspi->RxCpltCallback = pCallback;
 550 
 
551 
        break;
 551 
      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
552 
 
 552 
        hspi->TxRxCpltCallback = pCallback;
553 
      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
 553 
        break;
554 
        hspi->TxRxCpltCallback = pCallback;
 554 
 
555 
        break;
 555 
      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
556 
 
 556 
        hspi->TxHalfCpltCallback = pCallback;
557 
      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
 557 
        break;
558 
        hspi->TxHalfCpltCallback = pCallback;
 558 
 
559 
        break;
 559 
      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
560 
 
 560 
        hspi->RxHalfCpltCallback = pCallback;
561 
      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
 561 
        break;
562 
        hspi->RxHalfCpltCallback = pCallback;
 562 
 
563 
        break;
 563 
      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
564 
 
 564 
        hspi->TxRxHalfCpltCallback = pCallback;
565 
      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
 565 
        break;
566 
        hspi->TxRxHalfCpltCallback = pCallback;
 566 
 
567 
        break;
 567 
      case HAL_SPI_ERROR_CB_ID :
568 
 
 568 
        hspi->ErrorCallback = pCallback;
569 
      case HAL_SPI_ERROR_CB_ID :
 569 
        break;
570 
        hspi->ErrorCallback = pCallback;
 570 
 
571 
        break;
 571 
      case HAL_SPI_ABORT_CB_ID :
572 
 
 572 
        hspi->AbortCpltCallback = pCallback;
573 
      case HAL_SPI_ABORT_CB_ID :
 573 
        break;
574 
        hspi->AbortCpltCallback = pCallback;
 574 
 
575 
        break;
 575 
      case HAL_SPI_MSPINIT_CB_ID :
576 
 
 576 
        hspi->MspInitCallback = pCallback;
577 
      case HAL_SPI_MSPINIT_CB_ID :
 577 
        break;
578 
        hspi->MspInitCallback = pCallback;
 578 
 
579 
        break;
 579 
      case HAL_SPI_MSPDEINIT_CB_ID :
580 
 
 580 
        hspi->MspDeInitCallback = pCallback;
581 
      case HAL_SPI_MSPDEINIT_CB_ID :
 581 
        break;
582 
        hspi->MspDeInitCallback = pCallback;
 582 
 
583 
        break;
 583 
      default :
584 
 
 584 
        /* Update the error code */
585 
      default :
 585 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
586 
        /* Update the error code */
 586 
 
587 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 587 
        /* Return error status */
588 
 
 588 
        status =  HAL_ERROR;
589 
        /* Return error status */
 589 
        break;
590 
        status =  HAL_ERROR;
 590 
    }
591 
        break;
 591 
  }
592 
    }
 592 
  else if (HAL_SPI_STATE_RESET == hspi->State)
593 
  }
 593 
  {
594 
  else if (HAL_SPI_STATE_RESET == hspi->State)
 594 
    switch (CallbackID)
595 
  {
 595 
    {
596 
    switch (CallbackID)
 596 
      case HAL_SPI_MSPINIT_CB_ID :
597 
    {
 597 
        hspi->MspInitCallback = pCallback;
598 
      case HAL_SPI_MSPINIT_CB_ID :
 598 
        break;
599 
        hspi->MspInitCallback = pCallback;
 599 
 
600 
        break;
 600 
      case HAL_SPI_MSPDEINIT_CB_ID :
601 
 
 601 
        hspi->MspDeInitCallback = pCallback;
602 
      case HAL_SPI_MSPDEINIT_CB_ID :
 602 
        break;
603 
        hspi->MspDeInitCallback = pCallback;
 603 
 
604 
        break;
 604 
      default :
605 
 
 605 
        /* Update the error code */
606 
      default :
 606 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
607 
        /* Update the error code */
 607 
 
608 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 608 
        /* Return error status */
609 
 
 609 
        status =  HAL_ERROR;
610 
        /* Return error status */
 610 
        break;
611 
        status =  HAL_ERROR;
 611 
    }
612 
        break;
 612 
  }
613 
    }
 613 
  else
614 
  }
 614 
  {
615 
  else
 615 
    /* Update the error code */
616 
  {
 616 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
617 
    /* Update the error code */
 617 
 
618 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 618 
    /* Return error status */
619 
 
 619 
    status =  HAL_ERROR;
620 
    /* Return error status */
 620 
  }
621 
    status =  HAL_ERROR;
 621 
 
622 
  }
 622 
  /* Release Lock */
623 
 
 623 
  __HAL_UNLOCK(hspi);
624 
  /* Release Lock */
 624 
  return status;
625 
  __HAL_UNLOCK(hspi);
 625 
}
626 
  return status;
 626 
 
627 
}
 627 
/**
628 
 
 628 
  * @brief  Unregister an SPI Callback
629 
/**
 629 
  *         SPI callback is redirected to the weak predefined callback
630 
  * @brief  Unregister an SPI Callback
 630 
  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
631 
  *         SPI callback is redirected to the weak predefined callback
 631 
  *                the configuration information for the specified SPI.
632 
  * @param  hspi Pointer to a SPI_HandleTypeDef structure that contains
 632 
  * @param  CallbackID ID of the callback to be unregistered
633 
  *                the configuration information for the specified SPI.
 633 
  * @retval HAL status
634 
  * @param  CallbackID ID of the callback to be unregistered
 634 
  */
635 
  * @retval HAL status
 635 
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
636 
  */
 636 
{
637 
HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID)
 637 
  HAL_StatusTypeDef status = HAL_OK;
638 
{
 638 
 
639 
  HAL_StatusTypeDef status = HAL_OK;
 639 
  /* Process locked */
640 
 
 640 
  __HAL_LOCK(hspi);
641 
  /* Process locked */
 641 
 
642 
  __HAL_LOCK(hspi);
 642 
  if (HAL_SPI_STATE_READY == hspi->State)
643 
 
 643 
  {
644 
  if (HAL_SPI_STATE_READY == hspi->State)
 644 
    switch (CallbackID)
645 
  {
 645 
    {
646 
    switch (CallbackID)
 646 
      case HAL_SPI_TX_COMPLETE_CB_ID :
647 
    {
 647 
        hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
648 
      case HAL_SPI_TX_COMPLETE_CB_ID :
 648 
        break;
649 
        hspi->TxCpltCallback = HAL_SPI_TxCpltCallback;             /* Legacy weak TxCpltCallback       */
 649 
 
650 
        break;
 650 
      case HAL_SPI_RX_COMPLETE_CB_ID :
651 
 
 651 
        hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
652 
      case HAL_SPI_RX_COMPLETE_CB_ID :
 652 
        break;
653 
        hspi->RxCpltCallback = HAL_SPI_RxCpltCallback;             /* Legacy weak RxCpltCallback       */
 653 
 
654 
        break;
 654 
      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
655 
 
 655 
        hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
656 
      case HAL_SPI_TX_RX_COMPLETE_CB_ID :
 656 
        break;
657 
        hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback;         /* Legacy weak TxRxCpltCallback     */
 657 
 
658 
        break;
 658 
      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
659 
 
 659 
        hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
660 
      case HAL_SPI_TX_HALF_COMPLETE_CB_ID :
 660 
        break;
661 
        hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback;     /* Legacy weak TxHalfCpltCallback   */
 661 
 
662 
        break;
 662 
      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
663 
 
 663 
        hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
664 
      case HAL_SPI_RX_HALF_COMPLETE_CB_ID :
 664 
        break;
665 
        hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback;     /* Legacy weak RxHalfCpltCallback   */
 665 
 
666 
        break;
 666 
      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
667 
 
 667 
        hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
668 
      case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID :
 668 
        break;
669 
        hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */
 669 
 
670 
        break;
 670 
      case HAL_SPI_ERROR_CB_ID :
671 
 
 671 
        hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
672 
      case HAL_SPI_ERROR_CB_ID :
 672 
        break;
673 
        hspi->ErrorCallback = HAL_SPI_ErrorCallback;               /* Legacy weak ErrorCallback        */
 673 
 
674 
        break;
 674 
      case HAL_SPI_ABORT_CB_ID :
675 
 
 675 
        hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
676 
      case HAL_SPI_ABORT_CB_ID :
 676 
        break;
677 
        hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback;       /* Legacy weak AbortCpltCallback    */
 677 
 
678 
        break;
 678 
      case HAL_SPI_MSPINIT_CB_ID :
679 
 
 679 
        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
680 
      case HAL_SPI_MSPINIT_CB_ID :
 680 
        break;
681 
        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
 681 
 
682 
        break;
 682 
      case HAL_SPI_MSPDEINIT_CB_ID :
683 
 
 683 
        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
684 
      case HAL_SPI_MSPDEINIT_CB_ID :
 684 
        break;
685 
        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
 685 
 
686 
        break;
 686 
      default :
687 
 
 687 
        /* Update the error code */
688 
      default :
 688 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
689 
        /* Update the error code */
 689 
 
690 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 690 
        /* Return error status */
691 
 
 691 
        status =  HAL_ERROR;
692 
        /* Return error status */
 692 
        break;
693 
        status =  HAL_ERROR;
 693 
    }
694 
        break;
 694 
  }
695 
    }
 695 
  else if (HAL_SPI_STATE_RESET == hspi->State)
696 
  }
 696 
  {
697 
  else if (HAL_SPI_STATE_RESET == hspi->State)
 697 
    switch (CallbackID)
698 
  {
 698 
    {
699 
    switch (CallbackID)
 699 
      case HAL_SPI_MSPINIT_CB_ID :
700 
    {
 700 
        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
701 
      case HAL_SPI_MSPINIT_CB_ID :
 701 
        break;
702 
        hspi->MspInitCallback = HAL_SPI_MspInit;                   /* Legacy weak MspInit              */
 702 
 
703 
        break;
 703 
      case HAL_SPI_MSPDEINIT_CB_ID :
704 
 
 704 
        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
705 
      case HAL_SPI_MSPDEINIT_CB_ID :
 705 
        break;
706 
        hspi->MspDeInitCallback = HAL_SPI_MspDeInit;               /* Legacy weak MspDeInit            */
 706 
 
707 
        break;
 707 
      default :
708 
 
 708 
        /* Update the error code */
709 
      default :
 709 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
710 
        /* Update the error code */
 710 
 
711 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 711 
        /* Return error status */
712 
 
 712 
        status =  HAL_ERROR;
713 
        /* Return error status */
 713 
        break;
714 
        status =  HAL_ERROR;
 714 
    }
715 
        break;
 715 
  }
716 
    }
 716 
  else
717 
  }
 717 
  {
718 
  else
 718 
    /* Update the error code */
719 
  {
 719 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
720 
    /* Update the error code */
 720 
 
721 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK);
 721 
    /* Return error status */
722 
 
 722 
    status =  HAL_ERROR;
723 
    /* Return error status */
 723 
  }
724 
    status =  HAL_ERROR;
 724 
 
725 
  }
 725 
  /* Release Lock */
726 
 
 726 
  __HAL_UNLOCK(hspi);
727 
  /* Release Lock */
 727 
  return status;
728 
  __HAL_UNLOCK(hspi);
 728 
}
729 
  return status;
 729 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
730 
}
 730 
/**
731 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 731 
  * @}
732 
/**
 732 
  */
733 
  * @}
 733 
 
734 
  */
 734 
/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
735 
 
 735 
  *  @brief   Data transfers functions
736 
/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
 736 
  *
737 
  *  @brief   Data transfers functions
 737 
@verbatim
738 
  *
 738 
  ==============================================================================
739 
@verbatim
 739 
                      ##### IO operation functions #####
740 
  ==============================================================================
 740 
 ===============================================================================
741 
                      ##### IO operation functions #####
 741 
 [..]
742 
 ===============================================================================
 742 
    This subsection provides a set of functions allowing to manage the SPI
743 
 [..]
 743 
    data transfers.
744 
    This subsection provides a set of functions allowing to manage the SPI
 744 
 
745 
    data transfers.
 745 
    [..] The SPI supports master and slave mode :
746 
 
 746 
 
747 
    [..] The SPI supports master and slave mode :
 747 
    (#) There are two modes of transfer:
748 
 
 748 
       (++) Blocking mode: The communication is performed in polling mode.
749 
    (#) There are two modes of transfer:
 749 
            The HAL status of all data processing is returned by the same function
750 
       (++) Blocking mode: The communication is performed in polling mode.
 750 
            after finishing transfer.
751 
            The HAL status of all data processing is returned by the same function
 751 
       (++) No-Blocking mode: The communication is performed using Interrupts
752 
            after finishing transfer.
 752 
            or DMA, These APIs return the HAL status.
753 
       (++) No-Blocking mode: The communication is performed using Interrupts
 753 
            The end of the data processing will be indicated through the
754 
            or DMA, These APIs return the HAL status.
 754 
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
755 
            The end of the data processing will be indicated through the
 755 
            using DMA mode.
756 
            dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when
 756 
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
757 
            using DMA mode.
 757 
            will be executed respectively at the end of the transmit or Receive process
758 
            The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks
 758 
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
759 
            will be executed respectively at the end of the transmit or Receive process
 759 
 
760 
            The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
 760 
    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
761 
 
 761 
        exist for 1Line (simplex) and 2Lines (full duplex) modes.
762 
    (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA)
 762 
 
763 
        exist for 1Line (simplex) and 2Lines (full duplex) modes.
 763 
@endverbatim
764 
 
 764 
  * @{
765 
@endverbatim
 765 
  */
766 
  * @{
 766 
 
767 
  */
 767 
/**
768 
 
 768 
  * @brief  Transmit an amount of data in blocking mode.
769 
/**
 769 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
770 
  * @brief  Transmit an amount of data in blocking mode.
 770 
  *               the configuration information for SPI module.
771 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 771 
  * @param  pData pointer to data buffer
772 
  *               the configuration information for SPI module.
 772 
  * @param  Size amount of data to be sent
773 
  * @param  pData pointer to data buffer
 773 
  * @param  Timeout Timeout duration
774 
  * @param  Size amount of data to be sent
 774 
  * @retval HAL status
775 
  * @param  Timeout Timeout duration
 775 
  */
776 
  * @retval HAL status
 776 
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
777 
  */
 777 
{
778 
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 778 
  uint32_t tickstart;
779 
{
 779 
  HAL_StatusTypeDef errorcode = HAL_OK;
780 
  uint32_t tickstart;
 780 
  uint16_t initial_TxXferCount;
781 
  HAL_StatusTypeDef errorcode = HAL_OK;
 781 
 
782 
  uint16_t initial_TxXferCount;
 782 
  /* Check Direction parameter */
783 
 
 783 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
784 
  /* Check Direction parameter */
 784 
 
785 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 785 
  /* Process Locked */
786 
 
 786 
  __HAL_LOCK(hspi);
787 
  /* Process Locked */
 787 
 
788 
  __HAL_LOCK(hspi);
 788 
  /* Init tickstart for timeout management*/
789 
 
 789 
  tickstart = HAL_GetTick();
790 
  /* Init tickstart for timeout management*/
 790 
  initial_TxXferCount = Size;
791 
  tickstart = HAL_GetTick();
 791 
 
792 
  initial_TxXferCount = Size;
 792 
  if (hspi->State != HAL_SPI_STATE_READY)
793 
 
 793 
  {
794 
  if (hspi->State != HAL_SPI_STATE_READY)
 794 
    errorcode = HAL_BUSY;
795 
  {
 795 
    goto error;
796 
    errorcode = HAL_BUSY;
 796 
  }
797 
    goto error;
 797 
 
798 
  }
 798 
  if ((pData == NULL) || (Size == 0U))
799 
 
 799 
  {
800 
  if ((pData == NULL) || (Size == 0U))
 800 
    errorcode = HAL_ERROR;
801 
  {
 801 
    goto error;
802 
    errorcode = HAL_ERROR;
 802 
  }
803 
    goto error;
 803 
 
804 
  }
 804 
  /* Set the transaction information */
805 
 
 805 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
806 
  /* Set the transaction information */
 806 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
807 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
 807 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
808 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 808 
  hspi->TxXferSize  = Size;
809 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
 809 
  hspi->TxXferCount = Size;
810 
  hspi->TxXferSize  = Size;
 810 
 
811 
  hspi->TxXferCount = Size;
 811 
  /*Init field not used in handle to zero */
812 
 
 812 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
813 
  /*Init field not used in handle to zero */
 813 
  hspi->RxXferSize  = 0U;
814 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
 814 
  hspi->RxXferCount = 0U;
815 
  hspi->RxXferSize  = 0U;
 815 
  hspi->TxISR       = NULL;
816 
  hspi->RxXferCount = 0U;
 816 
  hspi->RxISR       = NULL;
817 
  hspi->TxISR       = NULL;
 817 
 
818 
  hspi->RxISR       = NULL;
 818 
  /* Configure communication direction : 1Line */
819 
 
 819 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
820 
  /* Configure communication direction : 1Line */
 820 
  {
821 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 821 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
822 
  {
 822 
    __HAL_SPI_DISABLE(hspi);
823 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 823 
    SPI_1LINE_TX(hspi);
824 
    __HAL_SPI_DISABLE(hspi);
 824 
  }
825 
    SPI_1LINE_TX(hspi);
 825 
 
826 
  }
 826 
#if (USE_SPI_CRC != 0U)
827 
 
 827 
  /* Reset CRC Calculation */
828 
#if (USE_SPI_CRC != 0U)
 828 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
829 
  /* Reset CRC Calculation */
 829 
  {
830 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 830 
    SPI_RESET_CRC(hspi);
831 
  {
 831 
  }
832 
    SPI_RESET_CRC(hspi);
 832 
#endif /* USE_SPI_CRC */
833 
  }
 833 
 
834 
#endif /* USE_SPI_CRC */
 834 
  /* Check if the SPI is already enabled */
835 
 
 835 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
836 
  /* Check if the SPI is already enabled */
 836 
  {
837 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 837 
    /* Enable SPI peripheral */
838 
  {
 838 
    __HAL_SPI_ENABLE(hspi);
839 
    /* Enable SPI peripheral */
 839 
  }
840 
    __HAL_SPI_ENABLE(hspi);
 840 
 
841 
  }
 841 
  /* Transmit data in 16 Bit mode */
842 
 
 842 
  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
843 
  /* Transmit data in 16 Bit mode */
 843 
  {
844 
  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
 844 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
845 
  {
 845 
    {
846 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
 846 
      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
847 
    {
 847 
      hspi->pTxBuffPtr += sizeof(uint16_t);
848 
      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 848 
      hspi->TxXferCount--;
849 
      hspi->pTxBuffPtr += sizeof(uint16_t);
 849 
    }
850 
      hspi->TxXferCount--;
 850 
    /* Transmit data in 16 Bit mode */
851 
    }
 851 
    while (hspi->TxXferCount > 0U)
852 
    /* Transmit data in 16 Bit mode */
 852 
    {
853 
    while (hspi->TxXferCount > 0U)
 853 
      /* Wait until TXE flag is set to send data */
854 
    {
 854 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
855 
      /* Wait until TXE flag is set to send data */
 855 
      {
856 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
 856 
        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
857 
      {
 857 
        hspi->pTxBuffPtr += sizeof(uint16_t);
858 
        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 858 
        hspi->TxXferCount--;
859 
        hspi->pTxBuffPtr += sizeof(uint16_t);
 859 
      }
860 
        hspi->TxXferCount--;
 860 
      else
861 
      }
 861 
      {
862 
      else
 862 
        /* Timeout management */
863 
      {
 863 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
864 
        /* Timeout management */
 864 
        {
865 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
 865 
          errorcode = HAL_TIMEOUT;
866 
        {
 866 
          hspi->State = HAL_SPI_STATE_READY;
867 
          errorcode = HAL_TIMEOUT;
 867 
          goto error;
868 
          goto error;
 868 
        }
869 
        }
 869 
      }
870 
      }
 870 
    }
871 
    }
 871 
  }
872 
  }
 872 
  /* Transmit data in 8 Bit mode */
873 
  /* Transmit data in 8 Bit mode */
 873 
  else
874 
  else
 874 
  {
875 
  {
 875 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
876 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
 876 
    {
877 
    {
 877 
      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
878 
      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
 878 
      hspi->pTxBuffPtr += sizeof(uint8_t);
879 
      hspi->pTxBuffPtr += sizeof(uint8_t);
 879 
      hspi->TxXferCount--;
880 
      hspi->TxXferCount--;
 880 
    }
881 
    }
 881 
    while (hspi->TxXferCount > 0U)
882 
    while (hspi->TxXferCount > 0U)
 882 
    {
883 
    {
 883 
      /* Wait until TXE flag is set to send data */
884 
      /* Wait until TXE flag is set to send data */
 884 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
885 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE))
 885 
      {
886 
      {
 886 
        *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
887 
        *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
 887 
        hspi->pTxBuffPtr += sizeof(uint8_t);
888 
        hspi->pTxBuffPtr += sizeof(uint8_t);
 888 
        hspi->TxXferCount--;
889 
        hspi->TxXferCount--;
 889 
      }
890 
      }
 890 
      else
891 
      else
 891 
      {
892 
      {
 892 
        /* Timeout management */
893 
        /* Timeout management */
 893 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
894 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
 894 
        {
895 
        {
 895 
          errorcode = HAL_TIMEOUT;
896 
          errorcode = HAL_TIMEOUT;
 896 
          hspi->State = HAL_SPI_STATE_READY;
897 
          goto error;
 897 
          goto error;
898 
        }
 898 
        }
899 
      }
 899 
      }
900 
    }
 900 
    }
901 
  }
 901 
  }
902 
#if (USE_SPI_CRC != 0U)
 902 
#if (USE_SPI_CRC != 0U)
903 
  /* Enable CRC Transmission */
 903 
  /* Enable CRC Transmission */
904 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 904 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
905 
  {
 905 
  {
906 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 906 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
907 
  }
 907 
  }
908 
#endif /* USE_SPI_CRC */
 908 
#endif /* USE_SPI_CRC */
909 
 
 909 
 
910 
  /* Check the end of the transaction */
 910 
  /* Check the end of the transaction */
911 
  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
 911 
  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
912 
  {
 912 
  {
913 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
 913 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
914 
  }
 914 
  }
915 
 
 915 
 
916 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
 916 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
917 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 917 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
918 
  {
 918 
  {
919 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 919 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
920 
  }
 920 
  }
921 
 
 921 
 
922 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 922 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
923 
  {
 923 
  {
924 
    errorcode = HAL_ERROR;
 924 
    errorcode = HAL_ERROR;
925 
  }
 925 
  }
926 
 
 926 
  else
927 
error:
 927 
  {
928 
  hspi->State = HAL_SPI_STATE_READY;
 928 
    hspi->State = HAL_SPI_STATE_READY;
929 
  /* Process Unlocked */
 929 
  }
930 
  __HAL_UNLOCK(hspi);
 930 
 
931 
  return errorcode;
 931 
error:
932 
}
 932 
  /* Process Unlocked */
933 
 
 933 
  __HAL_UNLOCK(hspi);
934 
/**
 934 
  return errorcode;
935 
  * @brief  Receive an amount of data in blocking mode.
 935 
}
936 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 936 
 
937 
  *               the configuration information for SPI module.
 937 
/**
938 
  * @param  pData pointer to data buffer
 938 
  * @brief  Receive an amount of data in blocking mode.
939 
  * @param  Size amount of data to be received
 939 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
940 
  * @param  Timeout Timeout duration
 940 
  *               the configuration information for SPI module.
941 
  * @retval HAL status
 941 
  * @param  pData pointer to data buffer
942 
  */
 942 
  * @param  Size amount of data to be received
943 
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
 943 
  * @param  Timeout Timeout duration
944 
{
 944 
  * @retval HAL status
945 
#if (USE_SPI_CRC != 0U)
 945 
  */
946 
  __IO uint32_t tmpreg = 0U;
 946 
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
947 
#endif /* USE_SPI_CRC */
 947 
{
948 
  uint32_t tickstart;
 948 
#if (USE_SPI_CRC != 0U)
949 
  HAL_StatusTypeDef errorcode = HAL_OK;
 949 
  __IO uint32_t tmpreg = 0U;
950 
 
 950 
#endif /* USE_SPI_CRC */
951 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
 951 
  uint32_t tickstart;
952 
  {
 952 
  HAL_StatusTypeDef errorcode = HAL_OK;
953 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
 953 
 
954 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
 954 
  if (hspi->State != HAL_SPI_STATE_READY)
955 
    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
 955 
  {
956 
  }
 956 
    errorcode = HAL_BUSY;
957 
 
 957 
    goto error;
958 
  /* Process Locked */
 958 
  }
959 
  __HAL_LOCK(hspi);
 959 
 
960 
 
 960 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
961 
  /* Init tickstart for timeout management*/
 961 
  {
962 
  tickstart = HAL_GetTick();
 962 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
963 
 
 963 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
964 
  if (hspi->State != HAL_SPI_STATE_READY)
 964 
    return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
965 
  {
 965 
  }
966 
    errorcode = HAL_BUSY;
 966 
 
967 
    goto error;
 967 
  /* Process Locked */
968 
  }
 968 
  __HAL_LOCK(hspi);
969 
 
 969 
 
970 
  if ((pData == NULL) || (Size == 0U))
 970 
  /* Init tickstart for timeout management*/
971 
  {
 971 
  tickstart = HAL_GetTick();
972 
    errorcode = HAL_ERROR;
 972 
 
973 
    goto error;
 973 
  if ((pData == NULL) || (Size == 0U))
974 
  }
 974 
  {
975 
 
 975 
    errorcode = HAL_ERROR;
976 
  /* Set the transaction information */
 976 
    goto error;
977 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
 977 
  }
978 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 978 
 
979 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
 979 
  /* Set the transaction information */
980 
  hspi->RxXferSize  = Size;
 980 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
981 
  hspi->RxXferCount = Size;
 981 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
982 
 
 982 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
983 
  /*Init field not used in handle to zero */
 983 
  hspi->RxXferSize  = Size;
984 
  hspi->pTxBuffPtr  = (uint8_t *)NULL;
 984 
  hspi->RxXferCount = Size;
985 
  hspi->TxXferSize  = 0U;
 985 
 
986 
  hspi->TxXferCount = 0U;
 986 
  /*Init field not used in handle to zero */
987 
  hspi->RxISR       = NULL;
 987 
  hspi->pTxBuffPtr  = (uint8_t *)NULL;
988 
  hspi->TxISR       = NULL;
 988 
  hspi->TxXferSize  = 0U;
989 
 
 989 
  hspi->TxXferCount = 0U;
990 
#if (USE_SPI_CRC != 0U)
 990 
  hspi->RxISR       = NULL;
991 
  /* Reset CRC Calculation */
 991 
  hspi->TxISR       = NULL;
992 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 992 
 
993 
  {
 993 
#if (USE_SPI_CRC != 0U)
994 
    SPI_RESET_CRC(hspi);
 994 
  /* Reset CRC Calculation */
995 
    /* this is done to handle the CRCNEXT before the latest data */
 995 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
996 
    hspi->RxXferCount--;
 996 
  {
997 
  }
 997 
    SPI_RESET_CRC(hspi);
998 
#endif /* USE_SPI_CRC */
 998 
    /* this is done to handle the CRCNEXT before the latest data */
999 
 
 999 
    hspi->RxXferCount--;
1000 
  /* Configure communication direction: 1Line */
 1000 
  }
1001 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 1001 
#endif /* USE_SPI_CRC */
1002 
  {
 1002 
 
1003 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 1003 
  /* Configure communication direction: 1Line */
1004 
    __HAL_SPI_DISABLE(hspi);
 1004 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1005 
    SPI_1LINE_RX(hspi);
 1005 
  {
1006 
  }
 1006 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1007 
 
 1007 
    __HAL_SPI_DISABLE(hspi);
1008 
  /* Check if the SPI is already enabled */
 1008 
    SPI_1LINE_RX(hspi);
1009 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1009 
  }
1010 
  {
 1010 
 
1011 
    /* Enable SPI peripheral */
 1011 
  /* Check if the SPI is already enabled */
1012 
    __HAL_SPI_ENABLE(hspi);
 1012 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1013 
  }
 1013 
  {
1014 
 
 1014 
    /* Enable SPI peripheral */
1015 
  /* Receive data in 8 Bit mode */
 1015 
    __HAL_SPI_ENABLE(hspi);
1016 
  if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
 1016 
  }
1017 
  {
 1017 
 
1018 
    /* Transfer loop */
 1018 
  /* Receive data in 8 Bit mode */
1019 
    while (hspi->RxXferCount > 0U)
 1019 
  if (hspi->Init.DataSize == SPI_DATASIZE_8BIT)
1020 
    {
 1020 
  {
1021 
      /* Check the RXNE flag */
 1021 
    /* Transfer loop */
1022 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
 1022 
    while (hspi->RxXferCount > 0U)
1023 
      {
 1023 
    {
1024 
        /* read the received data */
 1024 
      /* Check the RXNE flag */
1025 
        (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
 1025 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1026 
        hspi->pRxBuffPtr += sizeof(uint8_t);
 1026 
      {
1027 
        hspi->RxXferCount--;
 1027 
        /* read the received data */
1028 
      }
 1028 
        (* (uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1029 
      else
 1029 
        hspi->pRxBuffPtr += sizeof(uint8_t);
1030 
      {
 1030 
        hspi->RxXferCount--;
1031 
        /* Timeout management */
 1031 
      }
1032 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
 1032 
      else
1033 
        {
 1033 
      {
1034 
          errorcode = HAL_TIMEOUT;
 1034 
        /* Timeout management */
1035 
          goto error;
 1035 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1036 
        }
 1036 
        {
1037 
      }
 1037 
          errorcode = HAL_TIMEOUT;
1038 
    }
 1038 
          hspi->State = HAL_SPI_STATE_READY;
1039 
  }
 1039 
          goto error;
1040 
  else
 1040 
        }
1041 
  {
 1041 
      }
1042 
    /* Transfer loop */
 1042 
    }
1043 
    while (hspi->RxXferCount > 0U)
 1043 
  }
1044 
    {
 1044 
  else
1045 
      /* Check the RXNE flag */
 1045 
  {
1046 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
 1046 
    /* Transfer loop */
1047 
      {
 1047 
    while (hspi->RxXferCount > 0U)
1048 
        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
 1048 
    {
1049 
        hspi->pRxBuffPtr += sizeof(uint16_t);
 1049 
      /* Check the RXNE flag */
1050 
        hspi->RxXferCount--;
 1050 
      if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE))
1051 
      }
 1051 
      {
1052 
      else
 1052 
        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1053 
      {
 1053 
        hspi->pRxBuffPtr += sizeof(uint16_t);
1054 
        /* Timeout management */
 1054 
        hspi->RxXferCount--;
1055 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
 1055 
      }
1056 
        {
 1056 
      else
1057 
          errorcode = HAL_TIMEOUT;
 1057 
      {
1058 
          goto error;
 1058 
        /* Timeout management */
1059 
        }
 1059 
        if ((((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U))
1060 
      }
 1060 
        {
1061 
    }
 1061 
          errorcode = HAL_TIMEOUT;
1062 
  }
 1062 
          hspi->State = HAL_SPI_STATE_READY;
1063 
 
 1063 
          goto error;
1064 
#if (USE_SPI_CRC != 0U)
 1064 
        }
1065 
  /* Handle the CRC Transmission */
 1065 
      }
1066 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1066 
    }
1067 
  {
 1067 
  }
1068 
    /* freeze the CRC before the latest data */
 1068 
 
1069 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 1069 
#if (USE_SPI_CRC != 0U)
1070 
 
 1070 
  /* Handle the CRC Transmission */
1071 
    /* Read the latest data */
 1071 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1072 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
 1072 
  {
1073 
    {
 1073 
    /* freeze the CRC before the latest data */
1074 
      /* the latest data has not been received */
 1074 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1075 
      errorcode = HAL_TIMEOUT;
 1075 
 
1076 
      goto error;
 1076 
    /* Read the latest data */
1077 
    }
 1077 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1078 
 
 1078 
    {
1079 
    /* Receive last data in 16 Bit mode */
 1079 
      /* the latest data has not been received */
1080 
    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
 1080 
      errorcode = HAL_TIMEOUT;
1081 
    {
 1081 
      goto error;
1082 
      *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
 1082 
    }
1083 
    }
 1083 
 
1084 
    /* Receive last data in 8 Bit mode */
 1084 
    /* Receive last data in 16 Bit mode */
1085 
    else
 1085 
    if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1086 
    {
 1086 
    {
1087 
      (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
 1087 
      *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1088 
    }
 1088 
    }
1089 
 
 1089 
    /* Receive last data in 8 Bit mode */
1090 
    /* Wait the CRC data */
 1090 
    else
1091 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
 1091 
    {
1092 
    {
 1092 
      (*(uint8_t *)hspi->pRxBuffPtr) = *(__IO uint8_t *)&hspi->Instance->DR;
1093 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 1093 
    }
1094 
      errorcode = HAL_TIMEOUT;
 1094 
 
1095 
      goto error;
 1095 
    /* Wait the CRC data */
1096 
    }
 1096 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1097 
 
 1097 
    {
1098 
    /* Read CRC to Flush DR and RXNE flag */
 1098 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1099 
    tmpreg = READ_REG(hspi->Instance->DR);
 1099 
      errorcode = HAL_TIMEOUT;
1100 
    /* To avoid GCC warning */
 1100 
      goto error;
1101 
    UNUSED(tmpreg);
 1101 
    }
1102 
  }
 1102 
 
1103 
#endif /* USE_SPI_CRC */
 1103 
    /* Read CRC to Flush DR and RXNE flag */
1104 
 
 1104 
    tmpreg = READ_REG(hspi->Instance->DR);
1105 
  /* Check the end of the transaction */
 1105 
    /* To avoid GCC warning */
1106 
  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
 1106 
    UNUSED(tmpreg);
1107 
  {
 1107 
  }
1108 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
 1108 
#endif /* USE_SPI_CRC */
1109 
  }
 1109 
 
1110 
 
 1110 
  /* Check the end of the transaction */
1111 
#if (USE_SPI_CRC != 0U)
 1111 
  if (SPI_EndRxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1112 
  /* Check if CRC error occurred */
 1112 
  {
1113 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
 1113 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1114 
  {
 1114 
  }
1115 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 1115 
 
1116 
    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 1116 
#if (USE_SPI_CRC != 0U)
1117 
  }
 1117 
  /* Check if CRC error occurred */
1118 
#endif /* USE_SPI_CRC */
 1118 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1119 
 
 1119 
  {
1120 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 1120 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1121 
  {
 1121 
    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1122 
    errorcode = HAL_ERROR;
 1122 
  }
1123 
  }
 1123 
#endif /* USE_SPI_CRC */
1124 
 
 1124 
 
1125 
error :
 1125 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1126 
  hspi->State = HAL_SPI_STATE_READY;
 1126 
  {
1127 
  __HAL_UNLOCK(hspi);
 1127 
    errorcode = HAL_ERROR;
1128 
  return errorcode;
 1128 
  }
1129 
}
 1129 
  else
1130 
 
 1130 
  {
1131 
/**
 1131 
    hspi->State = HAL_SPI_STATE_READY;
1132 
  * @brief  Transmit and Receive an amount of data in blocking mode.
 1132 
  }
1133 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1133 
 
1134 
  *               the configuration information for SPI module.
 1134 
error :
1135 
  * @param  pTxData pointer to transmission data buffer
 1135 
  __HAL_UNLOCK(hspi);
1136 
  * @param  pRxData pointer to reception data buffer
 1136 
  return errorcode;
1137 
  * @param  Size amount of data to be sent and received
 1137 
}
1138 
  * @param  Timeout Timeout duration
 1138 
 
1139 
  * @retval HAL status
 1139 
/**
1140 
  */
 1140 
  * @brief  Transmit and Receive an amount of data in blocking mode.
1141 
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
 1141 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1142 
                                          uint32_t Timeout)
 1142 
  *               the configuration information for SPI module.
1143 
{
 1143 
  * @param  pTxData pointer to transmission data buffer
1144 
  uint16_t             initial_TxXferCount;
 1144 
  * @param  pRxData pointer to reception data buffer
1145 
  uint32_t             tmp_mode;
 1145 
  * @param  Size amount of data to be sent and received
1146 
  HAL_SPI_StateTypeDef tmp_state;
 1146 
  * @param  Timeout Timeout duration
1147 
  uint32_t             tickstart;
 1147 
  * @retval HAL status
1148 
#if (USE_SPI_CRC != 0U)
 1148 
  */
1149 
  __IO uint32_t tmpreg = 0U;
 1149 
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
1150 
#endif /* USE_SPI_CRC */
 1150 
                                          uint32_t Timeout)
1151 
 
 1151 
{
1152 
  /* Variable used to alternate Rx and Tx during transfer */
 1152 
  uint16_t             initial_TxXferCount;
1153 
  uint32_t             txallowed = 1U;
 1153 
  uint32_t             tmp_mode;
1154 
  HAL_StatusTypeDef    errorcode = HAL_OK;
 1154 
  HAL_SPI_StateTypeDef tmp_state;
1155 
 
 1155 
  uint32_t             tickstart;
1156 
  /* Check Direction parameter */
 1156 
#if (USE_SPI_CRC != 0U)
1157 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 1157 
  __IO uint32_t tmpreg = 0U;
1158 
 
 1158 
#endif /* USE_SPI_CRC */
1159 
  /* Process Locked */
 1159 
 
1160 
  __HAL_LOCK(hspi);
 1160 
  /* Variable used to alternate Rx and Tx during transfer */
1161 
 
 1161 
  uint32_t             txallowed = 1U;
1162 
  /* Init tickstart for timeout management*/
 1162 
  HAL_StatusTypeDef    errorcode = HAL_OK;
1163 
  tickstart = HAL_GetTick();
 1163 
 
1164 
 
 1164 
  /* Check Direction parameter */
1165 
  /* Init temporary variables */
 1165 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1166 
  tmp_state           = hspi->State;
 1166 
 
1167 
  tmp_mode            = hspi->Init.Mode;
 1167 
  /* Process Locked */
1168 
  initial_TxXferCount = Size;
 1168 
  __HAL_LOCK(hspi);
1169 
 
 1169 
 
1170 
  if (!((tmp_state == HAL_SPI_STATE_READY) || \
 1170 
  /* Init tickstart for timeout management*/
1171 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
 1171 
  tickstart = HAL_GetTick();
1172 
  {
 1172 
 
1173 
    errorcode = HAL_BUSY;
 1173 
  /* Init temporary variables */
1174 
    goto error;
 1174 
  tmp_state           = hspi->State;
1175 
  }
 1175 
  tmp_mode            = hspi->Init.Mode;
1176 
 
 1176 
  initial_TxXferCount = Size;
1177 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
 1177 
 
1178 
  {
 1178 
  if (!((tmp_state == HAL_SPI_STATE_READY) || \
1179 
    errorcode = HAL_ERROR;
 1179 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1180 
    goto error;
 1180 
  {
1181 
  }
 1181 
    errorcode = HAL_BUSY;
1182 
 
 1182 
    goto error;
1183 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
 1183 
  }
1184 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
 1184 
 
1185 
  {
 1185 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1186 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
 1186 
  {
1187 
  }
 1187 
    errorcode = HAL_ERROR;
1188 
 
 1188 
    goto error;
1189 
  /* Set the transaction information */
 1189 
  }
1190 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1190 
 
1191 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
 1191 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1192 
  hspi->RxXferCount = Size;
 1192 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1193 
  hspi->RxXferSize  = Size;
 1193 
  {
1194 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
 1194 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1195 
  hspi->TxXferCount = Size;
 1195 
  }
1196 
  hspi->TxXferSize  = Size;
 1196 
 
1197 
 
 1197 
  /* Set the transaction information */
1198 
  /*Init field not used in handle to zero */
 1198 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1199 
  hspi->RxISR       = NULL;
 1199 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
1200 
  hspi->TxISR       = NULL;
 1200 
  hspi->RxXferCount = Size;
1201 
 
 1201 
  hspi->RxXferSize  = Size;
1202 
#if (USE_SPI_CRC != 0U)
 1202 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
1203 
  /* Reset CRC Calculation */
 1203 
  hspi->TxXferCount = Size;
1204 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1204 
  hspi->TxXferSize  = Size;
1205 
  {
 1205 
 
1206 
    SPI_RESET_CRC(hspi);
 1206 
  /*Init field not used in handle to zero */
1207 
  }
 1207 
  hspi->RxISR       = NULL;
1208 
#endif /* USE_SPI_CRC */
 1208 
  hspi->TxISR       = NULL;
1209 
 
 1209 
 
1210 
  /* Check if the SPI is already enabled */
 1210 
#if (USE_SPI_CRC != 0U)
1211 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1211 
  /* Reset CRC Calculation */
1212 
  {
 1212 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1213 
    /* Enable SPI peripheral */
 1213 
  {
1214 
    __HAL_SPI_ENABLE(hspi);
 1214 
    SPI_RESET_CRC(hspi);
1215 
  }
 1215 
  }
1216 
 
 1216 
#endif /* USE_SPI_CRC */
1217 
  /* Transmit and Receive data in 16 Bit mode */
 1217 
 
1218 
  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
 1218 
  /* Check if the SPI is already enabled */
1219 
  {
 1219 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1220 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
 1220 
  {
1221 
    {
 1221 
    /* Enable SPI peripheral */
1222 
      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 1222 
    __HAL_SPI_ENABLE(hspi);
1223 
      hspi->pTxBuffPtr += sizeof(uint16_t);
 1223 
  }
1224 
      hspi->TxXferCount--;
 1224 
 
1225 
    }
 1225 
  /* Transmit and Receive data in 16 Bit mode */
1226 
    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
 1226 
  if (hspi->Init.DataSize == SPI_DATASIZE_16BIT)
1227 
    {
 1227 
  {
1228 
      /* Check TXE flag */
 1228 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1229 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
 1229 
    {
1230 
      {
 1230 
      hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1231 
        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 1231 
      hspi->pTxBuffPtr += sizeof(uint16_t);
1232 
        hspi->pTxBuffPtr += sizeof(uint16_t);
 1232 
      hspi->TxXferCount--;
1233 
        hspi->TxXferCount--;
 1233 
    }
1234 
        /* Next Data is a reception (Rx). Tx not allowed */
 1234 
    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1235 
        txallowed = 0U;
 1235 
    {
1236 
 
 1236 
      /* Check TXE flag */
1237 
#if (USE_SPI_CRC != 0U)
 1237 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1238 
        /* Enable CRC Transmission */
 1238 
      {
1239 
        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
 1239 
        hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
1240 
        {
 1240 
        hspi->pTxBuffPtr += sizeof(uint16_t);
1241 
          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 1241 
        hspi->TxXferCount--;
1242 
        }
 1242 
        /* Next Data is a reception (Rx). Tx not allowed */
1243 
#endif /* USE_SPI_CRC */
 1243 
        txallowed = 0U;
1244 
      }
 1244 
 
1245 
 
 1245 
#if (USE_SPI_CRC != 0U)
1246 
      /* Check RXNE flag */
 1246 
        /* Enable CRC Transmission */
1247 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
 1247 
        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1248 
      {
 1248 
        {
1249 
        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
 1249 
          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1250 
        hspi->pRxBuffPtr += sizeof(uint16_t);
 1250 
        }
1251 
        hspi->RxXferCount--;
 1251 
#endif /* USE_SPI_CRC */
1252 
        /* Next Data is a Transmission (Tx). Tx is allowed */
 1252 
      }
1253 
        txallowed = 1U;
 1253 
 
1254 
      }
 1254 
      /* Check RXNE flag */
1255 
      if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))
 1255 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1256 
      {
 1256 
      {
1257 
        errorcode = HAL_TIMEOUT;
 1257 
        *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)hspi->Instance->DR;
1258 
        goto error;
 1258 
        hspi->pRxBuffPtr += sizeof(uint16_t);
1259 
      }
 1259 
        hspi->RxXferCount--;
1260 
    }
 1260 
        /* Next Data is a Transmission (Tx). Tx is allowed */
1261 
  }
 1261 
        txallowed = 1U;
1262 
  /* Transmit and Receive data in 8 Bit mode */
 1262 
      }
1263 
  else
 1263 
      if (((HAL_GetTick() - tickstart) >=  Timeout) && (Timeout != HAL_MAX_DELAY))
1264 
  {
 1264 
      {
1265 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
 1265 
        errorcode = HAL_TIMEOUT;
1266 
    {
 1266 
        hspi->State = HAL_SPI_STATE_READY;
1267 
      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
 1267 
        goto error;
1268 
      hspi->pTxBuffPtr += sizeof(uint8_t);
 1268 
      }
1269 
      hspi->TxXferCount--;
 1269 
    }
1270 
    }
 1270 
  }
1271 
    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
 1271 
  /* Transmit and Receive data in 8 Bit mode */
1272 
    {
 1272 
  else
1273 
      /* Check TXE flag */
 1273 
  {
1274 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
 1274 
    if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U))
1275 
      {
 1275 
    {
1276 
        *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
 1276 
      *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr);
1277 
        hspi->pTxBuffPtr++;
 1277 
      hspi->pTxBuffPtr += sizeof(uint8_t);
1278 
        hspi->TxXferCount--;
 1278 
      hspi->TxXferCount--;
1279 
        /* Next Data is a reception (Rx). Tx not allowed */
 1279 
    }
1280 
        txallowed = 0U;
 1280 
    while ((hspi->TxXferCount > 0U) || (hspi->RxXferCount > 0U))
1281 
 
 1281 
    {
1282 
#if (USE_SPI_CRC != 0U)
 1282 
      /* Check TXE flag */
1283 
        /* Enable CRC Transmission */
 1283 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U))
1284 
        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
 1284 
      {
1285 
        {
 1285 
        *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
1286 
          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 1286 
        hspi->pTxBuffPtr++;
1287 
        }
 1287 
        hspi->TxXferCount--;
1288 
#endif /* USE_SPI_CRC */
 1288 
        /* Next Data is a reception (Rx). Tx not allowed */
1289 
      }
 1289 
        txallowed = 0U;
1290 
 
 1290 
 
1291 
      /* Wait until RXNE flag is reset */
 1291 
#if (USE_SPI_CRC != 0U)
1292 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
 1292 
        /* Enable CRC Transmission */
1293 
      {
 1293 
        if ((hspi->TxXferCount == 0U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
1294 
        (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
 1294 
        {
1295 
        hspi->pRxBuffPtr++;
 1295 
          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
1296 
        hspi->RxXferCount--;
 1296 
        }
1297 
        /* Next Data is a Transmission (Tx). Tx is allowed */
 1297 
#endif /* USE_SPI_CRC */
1298 
        txallowed = 1U;
 1298 
      }
1299 
      }
 1299 
 
1300 
      if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
 1300 
      /* Wait until RXNE flag is reset */
1301 
      {
 1301 
      if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE)) && (hspi->RxXferCount > 0U))
1302 
        errorcode = HAL_TIMEOUT;
 1302 
      {
1303 
        goto error;
 1303 
        (*(uint8_t *)hspi->pRxBuffPtr) = hspi->Instance->DR;
1304 
      }
 1304 
        hspi->pRxBuffPtr++;
1305 
    }
 1305 
        hspi->RxXferCount--;
1306 
  }
 1306 
        /* Next Data is a Transmission (Tx). Tx is allowed */
1307 
 
 1307 
        txallowed = 1U;
1308 
#if (USE_SPI_CRC != 0U)
 1308 
      }
1309 
  /* Read CRC from DR to close CRC calculation process */
 1309 
      if ((((HAL_GetTick() - tickstart) >=  Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U))
1310 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1310 
      {
1311 
  {
 1311 
        errorcode = HAL_TIMEOUT;
1312 
    /* Wait until TXE flag */
 1312 
        hspi->State = HAL_SPI_STATE_READY;
1313 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
 1313 
        goto error;
1314 
    {
 1314 
      }
1315 
      /* Error on the CRC reception */
 1315 
    }
1316 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 1316 
  }
1317 
      errorcode = HAL_TIMEOUT;
 1317 
 
1318 
      goto error;
 1318 
#if (USE_SPI_CRC != 0U)
1319 
    }
 1319 
  /* Read CRC from DR to close CRC calculation process */
1320 
    /* Read CRC */
 1320 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1321 
    tmpreg = READ_REG(hspi->Instance->DR);
 1321 
  {
1322 
    /* To avoid GCC warning */
 1322 
    /* Wait until TXE flag */
1323 
    UNUSED(tmpreg);
 1323 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK)
1324 
  }
 1324 
    {
1325 
 
 1325 
      /* Error on the CRC reception */
1326 
  /* Check if CRC error occurred */
 1326 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1327 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
 1327 
      errorcode = HAL_TIMEOUT;
1328 
  {
 1328 
      goto error;
1329 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 1329 
    }
1330 
    /* Clear CRC Flag */
 1330 
    /* Read CRC */
1331 
    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 1331 
    tmpreg = READ_REG(hspi->Instance->DR);
1332 
 
 1332 
    /* To avoid GCC warning */
1333 
    errorcode = HAL_ERROR;
 1333 
    UNUSED(tmpreg);
1334 
  }
 1334 
  }
1335 
#endif /* USE_SPI_CRC */
 1335 
 
1336 
 
 1336 
  /* Check if CRC error occurred */
1337 
  /* Check the end of the transaction */
 1337 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
1338 
  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
 1338 
  {
1339 
  {
 1339 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
1340 
    errorcode = HAL_ERROR;
 1340 
    /* Clear CRC Flag */
1341 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
 1341 
    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
1342 
    goto error;
 1342 
 
1343 
  }
 1343 
    errorcode = HAL_ERROR;
1344 
 
 1344 
  }
1345 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
 1345 
#endif /* USE_SPI_CRC */
1346 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 1346 
 
1347 
  {
 1347 
  /* Check the end of the transaction */
1348 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 1348 
  if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK)
1349 
  }
 1349 
  {
1350 
 
 1350 
    errorcode = HAL_ERROR;
1351 
error :
 1351 
    hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
1352 
  hspi->State = HAL_SPI_STATE_READY;
 1352 
    goto error;
1353 
  __HAL_UNLOCK(hspi);
 1353 
  }
1354 
  return errorcode;
 1354 
 
1355 
}
 1355 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
1356 
 
 1356 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
1357 
/**
 1357 
  {
1358 
  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
 1358 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
1359 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1359 
  }
1360 
  *               the configuration information for SPI module.
 1360 
 
1361 
  * @param  pData pointer to data buffer
 1361 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
1362 
  * @param  Size amount of data to be sent
 1362 
  {
1363 
  * @retval HAL status
 1363 
    errorcode = HAL_ERROR;
1364 
  */
 1364 
  }
1365 
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 1365 
  else
1366 
{
 1366 
  {
1367 
  HAL_StatusTypeDef errorcode = HAL_OK;
 1367 
    hspi->State = HAL_SPI_STATE_READY;
1368 
 
 1368 
  }
1369 
  /* Check Direction parameter */
 1369 
 
1370 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 1370 
error :
1371 
 
 1371 
  __HAL_UNLOCK(hspi);
1372 
  /* Process Locked */
 1372 
  return errorcode;
1373 
  __HAL_LOCK(hspi);
 1373 
}
1374 
 
 1374 
 
1375 
  if ((pData == NULL) || (Size == 0U))
 1375 
/**
1376 
  {
 1376 
  * @brief  Transmit an amount of data in non-blocking mode with Interrupt.
1377 
    errorcode = HAL_ERROR;
 1377 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1378 
    goto error;
 1378 
  *               the configuration information for SPI module.
1379 
  }
 1379 
  * @param  pData pointer to data buffer
1380 
 
 1380 
  * @param  Size amount of data to be sent
1381 
  if (hspi->State != HAL_SPI_STATE_READY)
 1381 
  * @retval HAL status
1382 
  {
 1382 
  */
1383 
    errorcode = HAL_BUSY;
 1383 
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1384 
    goto error;
 1384 
{
1385 
  }
 1385 
  HAL_StatusTypeDef errorcode = HAL_OK;
1386 
 
 1386 
 
1387 
  /* Set the transaction information */
 1387 
  /* Check Direction parameter */
1388 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
 1388 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1389 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1389 
 
1390 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
 1390 
  /* Process Locked */
1391 
  hspi->TxXferSize  = Size;
 1391 
  __HAL_LOCK(hspi);
1392 
  hspi->TxXferCount = Size;
 1392 
 
1393 
 
 1393 
  if ((pData == NULL) || (Size == 0U))
1394 
  /* Init field not used in handle to zero */
 1394 
  {
1395 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
 1395 
    errorcode = HAL_ERROR;
1396 
  hspi->RxXferSize  = 0U;
 1396 
    goto error;
1397 
  hspi->RxXferCount = 0U;
 1397 
  }
1398 
  hspi->RxISR       = NULL;
 1398 
 
1399 
 
 1399 
  if (hspi->State != HAL_SPI_STATE_READY)
1400 
  /* Set the function for IT treatment */
 1400 
  {
1401 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
 1401 
    errorcode = HAL_BUSY;
1402 
  {
 1402 
    goto error;
1403 
    hspi->TxISR = SPI_TxISR_16BIT;
 1403 
  }
1404 
  }
 1404 
 
1405 
  else
 1405 
  /* Set the transaction information */
1406 
  {
 1406 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
1407 
    hspi->TxISR = SPI_TxISR_8BIT;
 1407 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1408 
  }
 1408 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
1409 
 
 1409 
  hspi->TxXferSize  = Size;
1410 
  /* Configure communication direction : 1Line */
 1410 
  hspi->TxXferCount = Size;
1411 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 1411 
 
1412 
  {
 1412 
  /* Init field not used in handle to zero */
1413 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 1413 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
1414 
    __HAL_SPI_DISABLE(hspi);
 1414 
  hspi->RxXferSize  = 0U;
1415 
    SPI_1LINE_TX(hspi);
 1415 
  hspi->RxXferCount = 0U;
1416 
  }
 1416 
  hspi->RxISR       = NULL;
1417 
 
 1417 
 
1418 
#if (USE_SPI_CRC != 0U)
 1418 
  /* Set the function for IT treatment */
1419 
  /* Reset CRC Calculation */
 1419 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1420 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1420 
  {
1421 
  {
 1421 
    hspi->TxISR = SPI_TxISR_16BIT;
1422 
    SPI_RESET_CRC(hspi);
 1422 
  }
1423 
  }
 1423 
  else
1424 
#endif /* USE_SPI_CRC */
 1424 
  {
1425 
 
 1425 
    hspi->TxISR = SPI_TxISR_8BIT;
1426 
  /* Enable TXE and ERR interrupt */
 1426 
  }
1427 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
 1427 
 
1428 
 
 1428 
  /* Configure communication direction : 1Line */
1429 
 
 1429 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1430 
  /* Check if the SPI is already enabled */
 1430 
  {
1431 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1431 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1432 
  {
 1432 
    __HAL_SPI_DISABLE(hspi);
1433 
    /* Enable SPI peripheral */
 1433 
    SPI_1LINE_TX(hspi);
1434 
    __HAL_SPI_ENABLE(hspi);
 1434 
  }
1435 
  }
 1435 
 
1436 
 
 1436 
#if (USE_SPI_CRC != 0U)
1437 
error :
 1437 
  /* Reset CRC Calculation */
1438 
  __HAL_UNLOCK(hspi);
 1438 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1439 
  return errorcode;
 1439 
  {
1440 
}
 1440 
    SPI_RESET_CRC(hspi);
1441 
 
 1441 
  }
1442 
/**
 1442 
#endif /* USE_SPI_CRC */
1443 
  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
 1443 
 
1444 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1444 
  /* Enable TXE and ERR interrupt */
1445 
  *               the configuration information for SPI module.
 1445 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
1446 
  * @param  pData pointer to data buffer
 1446 
 
1447 
  * @param  Size amount of data to be sent
 1447 
 
1448 
  * @retval HAL status
 1448 
  /* Check if the SPI is already enabled */
1449 
  */
 1449 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1450 
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 1450 
  {
1451 
{
 1451 
    /* Enable SPI peripheral */
1452 
  HAL_StatusTypeDef errorcode = HAL_OK;
 1452 
    __HAL_SPI_ENABLE(hspi);
1453 
 
 1453 
  }
1454 
  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
 1454 
 
1455 
  {
 1455 
error :
1456 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
 1456 
  __HAL_UNLOCK(hspi);
1457 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
 1457 
  return errorcode;
1458 
    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
 1458 
}
1459 
  }
 1459 
 
1460 
 
 1460 
/**
1461 
  /* Process Locked */
 1461 
  * @brief  Receive an amount of data in non-blocking mode with Interrupt.
1462 
  __HAL_LOCK(hspi);
 1462 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1463 
 
 1463 
  *               the configuration information for SPI module.
1464 
  if (hspi->State != HAL_SPI_STATE_READY)
 1464 
  * @param  pData pointer to data buffer
1465 
  {
 1465 
  * @param  Size amount of data to be sent
1466 
    errorcode = HAL_BUSY;
 1466 
  * @retval HAL status
1467 
    goto error;
 1467 
  */
1468 
  }
 1468 
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1469 
 
 1469 
{
1470 
  if ((pData == NULL) || (Size == 0U))
 1470 
  HAL_StatusTypeDef errorcode = HAL_OK;
1471 
  {
 1471 
 
1472 
    errorcode = HAL_ERROR;
 1472 
 
1473 
    goto error;
 1473 
  if (hspi->State != HAL_SPI_STATE_READY)
1474 
  }
 1474 
  {
1475 
 
 1475 
    errorcode = HAL_BUSY;
1476 
  /* Set the transaction information */
 1476 
    goto error;
1477 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
 1477 
  }
1478 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1478 
 
1479 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
 1479 
  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1480 
  hspi->RxXferSize  = Size;
 1480 
  {
1481 
  hspi->RxXferCount = Size;
 1481 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
1482 
 
 1482 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1483 
  /* Init field not used in handle to zero */
 1483 
    return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
1484 
  hspi->pTxBuffPtr  = (uint8_t *)NULL;
 1484 
  }
1485 
  hspi->TxXferSize  = 0U;
 1485 
 
1486 
  hspi->TxXferCount = 0U;
 1486 
  /* Process Locked */
1487 
  hspi->TxISR       = NULL;
 1487 
  __HAL_LOCK(hspi);
1488 
 
 1488 
 
1489 
  /* Set the function for IT treatment */
 1489 
  if ((pData == NULL) || (Size == 0U))
1490 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
 1490 
  {
1491 
  {
 1491 
    errorcode = HAL_ERROR;
1492 
    hspi->RxISR = SPI_RxISR_16BIT;
 1492 
    goto error;
1493 
  }
 1493 
  }
1494 
  else
 1494 
 
1495 
  {
 1495 
  /* Set the transaction information */
1496 
    hspi->RxISR = SPI_RxISR_8BIT;
 1496 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
1497 
  }
 1497 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1498 
 
 1498 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
1499 
  /* Configure communication direction : 1Line */
 1499 
  hspi->RxXferSize  = Size;
1500 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 1500 
  hspi->RxXferCount = Size;
1501 
  {
 1501 
 
1502 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 1502 
  /* Init field not used in handle to zero */
1503 
    __HAL_SPI_DISABLE(hspi);
 1503 
  hspi->pTxBuffPtr  = (uint8_t *)NULL;
1504 
    SPI_1LINE_RX(hspi);
 1504 
  hspi->TxXferSize  = 0U;
1505 
  }
 1505 
  hspi->TxXferCount = 0U;
1506 
 
 1506 
  hspi->TxISR       = NULL;
1507 
#if (USE_SPI_CRC != 0U)
 1507 
 
1508 
  /* Reset CRC Calculation */
 1508 
  /* Set the function for IT treatment */
1509 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1509 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1510 
  {
 1510 
  {
1511 
    SPI_RESET_CRC(hspi);
 1511 
    hspi->RxISR = SPI_RxISR_16BIT;
1512 
  }
 1512 
  }
1513 
#endif /* USE_SPI_CRC */
 1513 
  else
1514 
 
 1514 
  {
1515 
  /* Enable TXE and ERR interrupt */
 1515 
    hspi->RxISR = SPI_RxISR_8BIT;
1516 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 1516 
  }
1517 
 
 1517 
 
1518 
  /* Note : The SPI must be enabled after unlocking current process
 1518 
  /* Configure communication direction : 1Line */
1519 
            to avoid the risk of SPI interrupt handle execution before current
 1519 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1520 
            process unlock */
 1520 
  {
1521 
 
 1521 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1522 
  /* Check if the SPI is already enabled */
 1522 
    __HAL_SPI_DISABLE(hspi);
1523 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1523 
    SPI_1LINE_RX(hspi);
1524 
  {
 1524 
  }
1525 
    /* Enable SPI peripheral */
 1525 
 
1526 
    __HAL_SPI_ENABLE(hspi);
 1526 
#if (USE_SPI_CRC != 0U)
1527 
  }
 1527 
  /* Reset CRC Calculation */
1528 
 
 1528 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1529 
error :
 1529 
  {
1530 
  /* Process Unlocked */
 1530 
    SPI_RESET_CRC(hspi);
1531 
  __HAL_UNLOCK(hspi);
 1531 
  }
1532 
  return errorcode;
 1532 
#endif /* USE_SPI_CRC */
1533 
}
 1533 
 
1534 
 
 1534 
  /* Enable TXE and ERR interrupt */
1535 
/**
 1535 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
1536 
  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
 1536 
 
1537 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1537 
  /* Note : The SPI must be enabled after unlocking current process
1538 
  *               the configuration information for SPI module.
 1538 
            to avoid the risk of SPI interrupt handle execution before current
1539 
  * @param  pTxData pointer to transmission data buffer
 1539 
            process unlock */
1540 
  * @param  pRxData pointer to reception data buffer
 1540 
 
1541 
  * @param  Size amount of data to be sent and received
 1541 
  /* Check if the SPI is already enabled */
1542 
  * @retval HAL status
 1542 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1543 
  */
 1543 
  {
1544 
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
 1544 
    /* Enable SPI peripheral */
1545 
{
 1545 
    __HAL_SPI_ENABLE(hspi);
1546 
  uint32_t             tmp_mode;
 1546 
  }
1547 
  HAL_SPI_StateTypeDef tmp_state;
 1547 
 
1548 
  HAL_StatusTypeDef    errorcode = HAL_OK;
 1548 
error :
1549 
 
 1549 
  /* Process Unlocked */
1550 
  /* Check Direction parameter */
 1550 
  __HAL_UNLOCK(hspi);
1551 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 1551 
  return errorcode;
1552 
 
 1552 
}
1553 
  /* Process locked */
 1553 
 
1554 
  __HAL_LOCK(hspi);
 1554 
/**
1555 
 
 1555 
  * @brief  Transmit and Receive an amount of data in non-blocking mode with Interrupt.
1556 
  /* Init temporary variables */
 1556 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1557 
  tmp_state           = hspi->State;
 1557 
  *               the configuration information for SPI module.
1558 
  tmp_mode            = hspi->Init.Mode;
 1558 
  * @param  pTxData pointer to transmission data buffer
1559 
 
 1559 
  * @param  pRxData pointer to reception data buffer
1560 
  if (!((tmp_state == HAL_SPI_STATE_READY) || \
 1560 
  * @param  Size amount of data to be sent and received
1561 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
 1561 
  * @retval HAL status
1562 
  {
 1562 
  */
1563 
    errorcode = HAL_BUSY;
 1563 
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
1564 
    goto error;
 1564 
{
1565 
  }
 1565 
  uint32_t             tmp_mode;
1566 
 
 1566 
  HAL_SPI_StateTypeDef tmp_state;
1567 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
 1567 
  HAL_StatusTypeDef    errorcode = HAL_OK;
1568 
  {
 1568 
 
1569 
    errorcode = HAL_ERROR;
 1569 
  /* Check Direction parameter */
1570 
    goto error;
 1570 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1571 
  }
 1571 
 
1572 
 
 1572 
  /* Process locked */
1573 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
 1573 
  __HAL_LOCK(hspi);
1574 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
 1574 
 
1575 
  {
 1575 
  /* Init temporary variables */
1576 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
 1576 
  tmp_state           = hspi->State;
1577 
  }
 1577 
  tmp_mode            = hspi->Init.Mode;
1578 
 
 1578 
 
1579 
  /* Set the transaction information */
 1579 
  if (!((tmp_state == HAL_SPI_STATE_READY) || \
1580 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1580 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1581 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
 1581 
  {
1582 
  hspi->TxXferSize  = Size;
 1582 
    errorcode = HAL_BUSY;
1583 
  hspi->TxXferCount = Size;
 1583 
    goto error;
1584 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
 1584 
  }
1585 
  hspi->RxXferSize  = Size;
 1585 
 
1586 
  hspi->RxXferCount = Size;
 1586 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1587 
 
 1587 
  {
1588 
  /* Set the function for IT treatment */
 1588 
    errorcode = HAL_ERROR;
1589 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
 1589 
    goto error;
1590 
  {
 1590 
  }
1591 
    hspi->RxISR     = SPI_2linesRxISR_16BIT;
 1591 
 
1592 
    hspi->TxISR     = SPI_2linesTxISR_16BIT;
 1592 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1593 
  }
 1593 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1594 
  else
 1594 
  {
1595 
  {
 1595 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1596 
    hspi->RxISR     = SPI_2linesRxISR_8BIT;
 1596 
  }
1597 
    hspi->TxISR     = SPI_2linesTxISR_8BIT;
 1597 
 
1598 
  }
 1598 
  /* Set the transaction information */
1599 
 
 1599 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1600 
#if (USE_SPI_CRC != 0U)
 1600 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
1601 
  /* Reset CRC Calculation */
 1601 
  hspi->TxXferSize  = Size;
1602 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1602 
  hspi->TxXferCount = Size;
1603 
  {
 1603 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
1604 
    SPI_RESET_CRC(hspi);
 1604 
  hspi->RxXferSize  = Size;
1605 
  }
 1605 
  hspi->RxXferCount = Size;
1606 
#endif /* USE_SPI_CRC */
 1606 
 
1607 
 
 1607 
  /* Set the function for IT treatment */
1608 
  /* Enable TXE, RXNE and ERR interrupt */
 1608 
  if (hspi->Init.DataSize > SPI_DATASIZE_8BIT)
1609 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
 1609 
  {
1610 
 
 1610 
    hspi->RxISR     = SPI_2linesRxISR_16BIT;
1611 
  /* Check if the SPI is already enabled */
 1611 
    hspi->TxISR     = SPI_2linesTxISR_16BIT;
1612 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1612 
  }
1613 
  {
 1613 
  else
1614 
    /* Enable SPI peripheral */
 1614 
  {
1615 
    __HAL_SPI_ENABLE(hspi);
 1615 
    hspi->RxISR     = SPI_2linesRxISR_8BIT;
1616 
  }
 1616 
    hspi->TxISR     = SPI_2linesTxISR_8BIT;
1617 
 
 1617 
  }
1618 
error :
 1618 
 
1619 
  /* Process Unlocked */
 1619 
#if (USE_SPI_CRC != 0U)
1620 
  __HAL_UNLOCK(hspi);
 1620 
  /* Reset CRC Calculation */
1621 
  return errorcode;
 1621 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1622 
}
 1622 
  {
1623 
 
 1623 
    SPI_RESET_CRC(hspi);
1624 
/**
 1624 
  }
1625 
  * @brief  Transmit an amount of data in non-blocking mode with DMA.
 1625 
#endif /* USE_SPI_CRC */
1626 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1626 
 
1627 
  *               the configuration information for SPI module.
 1627 
  /* Enable TXE, RXNE and ERR interrupt */
1628 
  * @param  pData pointer to data buffer
 1628 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
1629 
  * @param  Size amount of data to be sent
 1629 
 
1630 
  * @retval HAL status
 1630 
  /* Check if the SPI is already enabled */
1631 
  */
 1631 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1632 
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 1632 
  {
1633 
{
 1633 
    /* Enable SPI peripheral */
1634 
  HAL_StatusTypeDef errorcode = HAL_OK;
 1634 
    __HAL_SPI_ENABLE(hspi);
1635 
 
 1635 
  }
1636 
  /* Check tx dma handle */
 1636 
 
1637 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
 1637 
error :
1638 
 
 1638 
  /* Process Unlocked */
1639 
  /* Check Direction parameter */
 1639 
  __HAL_UNLOCK(hspi);
1640 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
 1640 
  return errorcode;
1641 
 
 1641 
}
1642 
  /* Process Locked */
 1642 
 
1643 
  __HAL_LOCK(hspi);
 1643 
/**
1644 
 
 1644 
  * @brief  Transmit an amount of data in non-blocking mode with DMA.
1645 
  if (hspi->State != HAL_SPI_STATE_READY)
 1645 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1646 
  {
 1646 
  *               the configuration information for SPI module.
1647 
    errorcode = HAL_BUSY;
 1647 
  * @param  pData pointer to data buffer
1648 
    goto error;
 1648 
  * @param  Size amount of data to be sent
1649 
  }
 1649 
  * @retval HAL status
1650 
 
 1650 
  */
1651 
  if ((pData == NULL) || (Size == 0U))
 1651 
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1652 
  {
 1652 
{
1653 
    errorcode = HAL_ERROR;
 1653 
  HAL_StatusTypeDef errorcode = HAL_OK;
1654 
    goto error;
 1654 
 
1655 
  }
 1655 
  /* Check tx dma handle */
1656 
 
 1656 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1657 
  /* Set the transaction information */
 1657 
 
1658 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
 1658 
  /* Check Direction parameter */
1659 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1659 
  assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
1660 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
 1660 
 
1661 
  hspi->TxXferSize  = Size;
 1661 
  /* Process Locked */
1662 
  hspi->TxXferCount = Size;
 1662 
  __HAL_LOCK(hspi);
1663 
 
 1663 
 
1664 
  /* Init field not used in handle to zero */
 1664 
  if (hspi->State != HAL_SPI_STATE_READY)
1665 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
 1665 
  {
1666 
  hspi->TxISR       = NULL;
 1666 
    errorcode = HAL_BUSY;
1667 
  hspi->RxISR       = NULL;
 1667 
    goto error;
1668 
  hspi->RxXferSize  = 0U;
 1668 
  }
1669 
  hspi->RxXferCount = 0U;
 1669 
 
1670 
 
 1670 
  if ((pData == NULL) || (Size == 0U))
1671 
  /* Configure communication direction : 1Line */
 1671 
  {
1672 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 1672 
    errorcode = HAL_ERROR;
1673 
  {
 1673 
    goto error;
1674 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 1674 
  }
1675 
    __HAL_SPI_DISABLE(hspi);
 1675 
 
1676 
    SPI_1LINE_TX(hspi);
 1676 
  /* Set the transaction information */
1677 
  }
 1677 
  hspi->State       = HAL_SPI_STATE_BUSY_TX;
1678 
 
 1678 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1679 
#if (USE_SPI_CRC != 0U)
 1679 
  hspi->pTxBuffPtr  = (uint8_t *)pData;
1680 
  /* Reset CRC Calculation */
 1680 
  hspi->TxXferSize  = Size;
1681 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1681 
  hspi->TxXferCount = Size;
1682 
  {
 1682 
 
1683 
    SPI_RESET_CRC(hspi);
 1683 
  /* Init field not used in handle to zero */
1684 
  }
 1684 
  hspi->pRxBuffPtr  = (uint8_t *)NULL;
1685 
#endif /* USE_SPI_CRC */
 1685 
  hspi->TxISR       = NULL;
1686 
 
 1686 
  hspi->RxISR       = NULL;
1687 
  /* Set the SPI TxDMA Half transfer complete callback */
 1687 
  hspi->RxXferSize  = 0U;
1688 
  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
 1688 
  hspi->RxXferCount = 0U;
1689 
 
 1689 
 
1690 
  /* Set the SPI TxDMA transfer complete callback */
 1690 
  /* Configure communication direction : 1Line */
1691 
  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
 1691 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1692 
 
 1692 
  {
1693 
  /* Set the DMA error callback */
 1693 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1694 
  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
 1694 
    __HAL_SPI_DISABLE(hspi);
1695 
 
 1695 
    SPI_1LINE_TX(hspi);
1696 
  /* Set the DMA AbortCpltCallback */
 1696 
  }
1697 
  hspi->hdmatx->XferAbortCallback = NULL;
 1697 
 
1698 
 
 1698 
#if (USE_SPI_CRC != 0U)
1699 
  /* Enable the Tx DMA Stream/Channel */
 1699 
  /* Reset CRC Calculation */
1700 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
 1700 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1701 
                                 hspi->TxXferCount))
 1701 
  {
1702 
  {
 1702 
    SPI_RESET_CRC(hspi);
1703 
    /* Update SPI error code */
 1703 
  }
1704 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 1704 
#endif /* USE_SPI_CRC */
1705 
    errorcode = HAL_ERROR;
 1705 
 
1706 
 
 1706 
  /* Set the SPI TxDMA Half transfer complete callback */
1707 
    hspi->State = HAL_SPI_STATE_READY;
 1707 
  hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
1708 
    goto error;
 1708 
 
1709 
  }
 1709 
  /* Set the SPI TxDMA transfer complete callback */
1710 
 
 1710 
  hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
1711 
  /* Check if the SPI is already enabled */
 1711 
 
1712 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1712 
  /* Set the DMA error callback */
1713 
  {
 1713 
  hspi->hdmatx->XferErrorCallback = SPI_DMAError;
1714 
    /* Enable SPI peripheral */
 1714 
 
1715 
    __HAL_SPI_ENABLE(hspi);
 1715 
  /* Set the DMA AbortCpltCallback */
1716 
  }
 1716 
  hspi->hdmatx->XferAbortCallback = NULL;
1717 
 
 1717 
 
1718 
  /* Enable the SPI Error Interrupt Bit */
 1718 
  /* Enable the Tx DMA Stream/Channel */
1719 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
 1719 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1720 
 
 1720 
                                 hspi->TxXferCount))
1721 
  /* Enable Tx DMA Request */
 1721 
  {
1722 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
 1722 
    /* Update SPI error code */
1723 
 
 1723 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1724 
error :
 1724 
    errorcode = HAL_ERROR;
1725 
  /* Process Unlocked */
 1725 
 
1726 
  __HAL_UNLOCK(hspi);
 1726 
    goto error;
1727 
  return errorcode;
 1727 
  }
1728 
}
 1728 
 
1729 
 
 1729 
  /* Check if the SPI is already enabled */
1730 
/**
 1730 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1731 
  * @brief  Receive an amount of data in non-blocking mode with DMA.
 1731 
  {
1732 
  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
 1732 
    /* Enable SPI peripheral */
1733 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1733 
    __HAL_SPI_ENABLE(hspi);
1734 
  *               the configuration information for SPI module.
 1734 
  }
1735 
  * @param  pData pointer to data buffer
 1735 
 
1736 
  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
 1736 
  /* Enable the SPI Error Interrupt Bit */
1737 
  * @param  Size amount of data to be sent
 1737 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1738 
  * @retval HAL status
 1738 
 
1739 
  */
 1739 
  /* Enable Tx DMA Request */
1740 
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
 1740 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1741 
{
 1741 
 
1742 
  HAL_StatusTypeDef errorcode = HAL_OK;
 1742 
error :
1743 
 
 1743 
  /* Process Unlocked */
1744 
  /* Check rx dma handle */
 1744 
  __HAL_UNLOCK(hspi);
1745 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
 1745 
  return errorcode;
1746 
 
 1746 
}
1747 
  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
 1747 
 
1748 
  {
 1748 
/**
1749 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
 1749 
  * @brief  Receive an amount of data in non-blocking mode with DMA.
1750 
 
 1750 
  * @note   In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined.
1751 
    /* Check tx dma handle */
 1751 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1752 
    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
 1752 
  *               the configuration information for SPI module.
1753 
 
 1753 
  * @param  pData pointer to data buffer
1754 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
 1754 
  * @note   When the CRC feature is enabled the pData Length must be Size + 1.
1755 
    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
 1755 
  * @param  Size amount of data to be sent
1756 
  }
 1756 
  * @retval HAL status
1757 
 
 1757 
  */
1758 
  /* Process Locked */
 1758 
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
1759 
  __HAL_LOCK(hspi);
 1759 
{
1760 
 
 1760 
  HAL_StatusTypeDef errorcode = HAL_OK;
1761 
  if (hspi->State != HAL_SPI_STATE_READY)
 1761 
 
1762 
  {
 1762 
  /* Check rx dma handle */
1763 
    errorcode = HAL_BUSY;
 1763 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1764 
    goto error;
 1764 
 
1765 
  }
 1765 
  if (hspi->State != HAL_SPI_STATE_READY)
1766 
 
 1766 
  {
1767 
  if ((pData == NULL) || (Size == 0U))
 1767 
    errorcode = HAL_BUSY;
1768 
  {
 1768 
    goto error;
1769 
    errorcode = HAL_ERROR;
 1769 
  }
1770 
    goto error;
 1770 
 
1771 
  }
 1771 
  if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
1772 
 
 1772 
  {
1773 
  /* Set the transaction information */
 1773 
    hspi->State = HAL_SPI_STATE_BUSY_RX;
1774 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
 1774 
 
1775 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1775 
    /* Check tx dma handle */
1776 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
 1776 
    assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1777 
  hspi->RxXferSize  = Size;
 1777 
 
1778 
  hspi->RxXferCount = Size;
 1778 
    /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
1779 
 
 1779 
    return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
1780 
  /*Init field not used in handle to zero */
 1780 
  }
1781 
  hspi->RxISR       = NULL;
 1781 
 
1782 
  hspi->TxISR       = NULL;
 1782 
  /* Process Locked */
1783 
  hspi->TxXferSize  = 0U;
 1783 
  __HAL_LOCK(hspi);
1784 
  hspi->TxXferCount = 0U;
 1784 
 
1785 
 
 1785 
  if ((pData == NULL) || (Size == 0U))
1786 
  /* Configure communication direction : 1Line */
 1786 
  {
1787 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
 1787 
    errorcode = HAL_ERROR;
1788 
  {
 1788 
    goto error;
1789 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
 1789 
  }
1790 
    __HAL_SPI_DISABLE(hspi);
 1790 
 
1791 
    SPI_1LINE_RX(hspi);
 1791 
  /* Set the transaction information */
1792 
  }
 1792 
  hspi->State       = HAL_SPI_STATE_BUSY_RX;
1793 
 
 1793 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1794 
#if (USE_SPI_CRC != 0U)
 1794 
  hspi->pRxBuffPtr  = (uint8_t *)pData;
1795 
  /* Reset CRC Calculation */
 1795 
  hspi->RxXferSize  = Size;
1796 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1796 
  hspi->RxXferCount = Size;
1797 
  {
 1797 
 
1798 
    SPI_RESET_CRC(hspi);
 1798 
  /*Init field not used in handle to zero */
1799 
  }
 1799 
  hspi->RxISR       = NULL;
1800 
#endif /* USE_SPI_CRC */
 1800 
  hspi->TxISR       = NULL;
1801 
 
 1801 
  hspi->TxXferSize  = 0U;
1802 
  /* Set the SPI RxDMA Half transfer complete callback */
 1802 
  hspi->TxXferCount = 0U;
1803 
  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
 1803 
 
1804 
 
 1804 
  /* Configure communication direction : 1Line */
1805 
  /* Set the SPI Rx DMA transfer complete callback */
 1805 
  if (hspi->Init.Direction == SPI_DIRECTION_1LINE)
1806 
  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
 1806 
  {
1807 
 
 1807 
    /* Disable SPI Peripheral before set 1Line direction (BIDIOE bit) */
1808 
  /* Set the DMA error callback */
 1808 
    __HAL_SPI_DISABLE(hspi);
1809 
  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
 1809 
    SPI_1LINE_RX(hspi);
1810 
 
 1810 
  }
1811 
  /* Set the DMA AbortCpltCallback */
 1811 
 
1812 
  hspi->hdmarx->XferAbortCallback = NULL;
 1812 
#if (USE_SPI_CRC != 0U)
1813 
 
 1813 
  /* Reset CRC Calculation */
1814 
  /* Enable the Rx DMA Stream/Channel  */
 1814 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1815 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
 1815 
  {
1816 
                                 hspi->RxXferCount))
 1816 
    SPI_RESET_CRC(hspi);
1817 
  {
 1817 
  }
1818 
    /* Update SPI error code */
 1818 
#endif /* USE_SPI_CRC */
1819 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 1819 
 
1820 
    errorcode = HAL_ERROR;
 1820 
  /* Set the SPI RxDMA Half transfer complete callback */
1821 
 
 1821 
  hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1822 
    hspi->State = HAL_SPI_STATE_READY;
 1822 
 
1823 
    goto error;
 1823 
  /* Set the SPI Rx DMA transfer complete callback */
1824 
  }
 1824 
  hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
1825 
 
 1825 
 
1826 
  /* Check if the SPI is already enabled */
 1826 
  /* Set the DMA error callback */
1827 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1827 
  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1828 
  {
 1828 
 
1829 
    /* Enable SPI peripheral */
 1829 
  /* Set the DMA AbortCpltCallback */
1830 
    __HAL_SPI_ENABLE(hspi);
 1830 
  hspi->hdmarx->XferAbortCallback = NULL;
1831 
  }
 1831 
 
1832 
 
 1832 
  /* Enable the Rx DMA Stream/Channel  */
1833 
  /* Enable the SPI Error Interrupt Bit */
 1833 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
1834 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
 1834 
                                 hspi->RxXferCount))
1835 
 
 1835 
  {
1836 
  /* Enable Rx DMA Request */
 1836 
    /* Update SPI error code */
1837 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
 1837 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1838 
 
 1838 
    errorcode = HAL_ERROR;
1839 
error:
 1839 
 
1840 
  /* Process Unlocked */
 1840 
    goto error;
1841 
  __HAL_UNLOCK(hspi);
 1841 
  }
1842 
  return errorcode;
 1842 
 
1843 
}
 1843 
  /* Check if the SPI is already enabled */
1844 
 
 1844 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1845 
/**
 1845 
  {
1846 
  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
 1846 
    /* Enable SPI peripheral */
1847 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 1847 
    __HAL_SPI_ENABLE(hspi);
1848 
  *               the configuration information for SPI module.
 1848 
  }
1849 
  * @param  pTxData pointer to transmission data buffer
 1849 
 
1850 
  * @param  pRxData pointer to reception data buffer
 1850 
  /* Enable the SPI Error Interrupt Bit */
1851 
  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
 1851 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1852 
  * @param  Size amount of data to be sent
 1852 
 
1853 
  * @retval HAL status
 1853 
  /* Enable Rx DMA Request */
1854 
  */
 1854 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1855 
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
 1855 
 
1856 
                                              uint16_t Size)
 1856 
error:
1857 
{
 1857 
  /* Process Unlocked */
1858 
  uint32_t             tmp_mode;
 1858 
  __HAL_UNLOCK(hspi);
1859 
  HAL_SPI_StateTypeDef tmp_state;
 1859 
  return errorcode;
1860 
  HAL_StatusTypeDef errorcode = HAL_OK;
 1860 
}
1861 
 
 1861 
 
1862 
  /* Check rx & tx dma handles */
 1862 
/**
1863 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
 1863 
  * @brief  Transmit and Receive an amount of data in non-blocking mode with DMA.
1864 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
 1864 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
1865 
 
 1865 
  *               the configuration information for SPI module.
1866 
  /* Check Direction parameter */
 1866 
  * @param  pTxData pointer to transmission data buffer
1867 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
 1867 
  * @param  pRxData pointer to reception data buffer
1868 
 
 1868 
  * @note   When the CRC feature is enabled the pRxData Length must be Size + 1
1869 
  /* Process locked */
 1869 
  * @param  Size amount of data to be sent
1870 
  __HAL_LOCK(hspi);
 1870 
  * @retval HAL status
1871 
 
 1871 
  */
1872 
  /* Init temporary variables */
 1872 
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
1873 
  tmp_state           = hspi->State;
 1873 
                                              uint16_t Size)
1874 
  tmp_mode            = hspi->Init.Mode;
 1874 
{
1875 
 
 1875 
  uint32_t             tmp_mode;
1876 
  if (!((tmp_state == HAL_SPI_STATE_READY) ||
 1876 
  HAL_SPI_StateTypeDef tmp_state;
1877 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
 1877 
  HAL_StatusTypeDef errorcode = HAL_OK;
1878 
  {
 1878 
 
1879 
    errorcode = HAL_BUSY;
 1879 
  /* Check rx & tx dma handles */
1880 
    goto error;
 1880 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx));
1881 
  }
 1881 
  assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx));
1882 
 
 1882 
 
1883 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
 1883 
  /* Check Direction parameter */
1884 
  {
 1884 
  assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
1885 
    errorcode = HAL_ERROR;
 1885 
 
1886 
    goto error;
 1886 
  /* Process locked */
1887 
  }
 1887 
  __HAL_LOCK(hspi);
1888 
 
 1888 
 
1889 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
 1889 
  /* Init temporary variables */
1890 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
 1890 
  tmp_state           = hspi->State;
1891 
  {
 1891 
  tmp_mode            = hspi->Init.Mode;
1892 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
 1892 
 
1893 
  }
 1893 
  if (!((tmp_state == HAL_SPI_STATE_READY) ||
1894 
 
 1894 
        ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX))))
1895 
  /* Set the transaction information */
 1895 
  {
1896 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
 1896 
    errorcode = HAL_BUSY;
1897 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
 1897 
    goto error;
1898 
  hspi->TxXferSize  = Size;
 1898 
  }
1899 
  hspi->TxXferCount = Size;
 1899 
 
1900 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
 1900 
  if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U))
1901 
  hspi->RxXferSize  = Size;
 1901 
  {
1902 
  hspi->RxXferCount = Size;
 1902 
    errorcode = HAL_ERROR;
1903 
 
 1903 
    goto error;
1904 
  /* Init field not used in handle to zero */
 1904 
  }
1905 
  hspi->RxISR       = NULL;
 1905 
 
1906 
  hspi->TxISR       = NULL;
 1906 
  /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
1907 
 
 1907 
  if (hspi->State != HAL_SPI_STATE_BUSY_RX)
1908 
#if (USE_SPI_CRC != 0U)
 1908 
  {
1909 
  /* Reset CRC Calculation */
 1909 
    hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
1910 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 1910 
  }
1911 
  {
 1911 
 
1912 
    SPI_RESET_CRC(hspi);
 1912 
  /* Set the transaction information */
1913 
  }
 1913 
  hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
1914 
#endif /* USE_SPI_CRC */
 1914 
  hspi->pTxBuffPtr  = (uint8_t *)pTxData;
1915 
 
 1915 
  hspi->TxXferSize  = Size;
1916 
  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
 1916 
  hspi->TxXferCount = Size;
1917 
  if (hspi->State == HAL_SPI_STATE_BUSY_RX)
 1917 
  hspi->pRxBuffPtr  = (uint8_t *)pRxData;
1918 
  {
 1918 
  hspi->RxXferSize  = Size;
1919 
    /* Set the SPI Rx DMA Half transfer complete callback */
 1919 
  hspi->RxXferCount = Size;
1920 
    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
 1920 
 
1921 
    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
 1921 
  /* Init field not used in handle to zero */
1922 
  }
 1922 
  hspi->RxISR       = NULL;
1923 
  else
 1923 
  hspi->TxISR       = NULL;
1924 
  {
 1924 
 
1925 
    /* Set the SPI Tx/Rx DMA Half transfer complete callback */
 1925 
#if (USE_SPI_CRC != 0U)
1926 
    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
 1926 
  /* Reset CRC Calculation */
1927 
    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
 1927 
  if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
1928 
  }
 1928 
  {
1929 
 
 1929 
    SPI_RESET_CRC(hspi);
1930 
  /* Set the DMA error callback */
 1930 
  }
1931 
  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
 1931 
#endif /* USE_SPI_CRC */
1932 
 
 1932 
 
1933 
  /* Set the DMA AbortCpltCallback */
 1933 
  /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
1934 
  hspi->hdmarx->XferAbortCallback = NULL;
 1934 
  if (hspi->State == HAL_SPI_STATE_BUSY_RX)
1935 
 
 1935 
  {
1936 
  /* Enable the Rx DMA Stream/Channel  */
 1936 
    /* Set the SPI Rx DMA Half transfer complete callback */
1937 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
 1937 
    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
1938 
                                 hspi->RxXferCount))
 1938 
    hspi->hdmarx->XferCpltCallback     = SPI_DMAReceiveCplt;
1939 
  {
 1939 
  }
1940 
    /* Update SPI error code */
 1940 
  else
1941 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 1941 
  {
1942 
    errorcode = HAL_ERROR;
 1942 
    /* Set the SPI Tx/Rx DMA Half transfer complete callback */
1943 
 
 1943 
    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
1944 
    hspi->State = HAL_SPI_STATE_READY;
 1944 
    hspi->hdmarx->XferCpltCallback     = SPI_DMATransmitReceiveCplt;
1945 
    goto error;
 1945 
  }
1946 
  }
 1946 
 
1947 
 
 1947 
  /* Set the DMA error callback */
1948 
  /* Enable Rx DMA Request */
 1948 
  hspi->hdmarx->XferErrorCallback = SPI_DMAError;
1949 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
 1949 
 
1950 
 
 1950 
  /* Set the DMA AbortCpltCallback */
1951 
  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
 1951 
  hspi->hdmarx->XferAbortCallback = NULL;
1952 
  is performed in DMA reception complete callback  */
 1952 
 
1953 
  hspi->hdmatx->XferHalfCpltCallback = NULL;
 1953 
  /* Enable the Rx DMA Stream/Channel  */
1954 
  hspi->hdmatx->XferCpltCallback     = NULL;
 1954 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
1955 
  hspi->hdmatx->XferErrorCallback    = NULL;
 1955 
                                 hspi->RxXferCount))
1956 
  hspi->hdmatx->XferAbortCallback    = NULL;
 1956 
  {
1957 
 
 1957 
    /* Update SPI error code */
1958 
  /* Enable the Tx DMA Stream/Channel  */
 1958 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1959 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
 1959 
    errorcode = HAL_ERROR;
1960 
                                 hspi->TxXferCount))
 1960 
 
1961 
  {
 1961 
    goto error;
1962 
    /* Update SPI error code */
 1962 
  }
1963 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 1963 
 
1964 
    errorcode = HAL_ERROR;
 1964 
  /* Enable Rx DMA Request */
1965 
 
 1965 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
1966 
    hspi->State = HAL_SPI_STATE_READY;
 1966 
 
1967 
    goto error;
 1967 
  /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing
1968 
  }
 1968 
  is performed in DMA reception complete callback  */
1969 
 
 1969 
  hspi->hdmatx->XferHalfCpltCallback = NULL;
1970 
  /* Check if the SPI is already enabled */
 1970 
  hspi->hdmatx->XferCpltCallback     = NULL;
1971 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
 1971 
  hspi->hdmatx->XferErrorCallback    = NULL;
1972 
  {
 1972 
  hspi->hdmatx->XferAbortCallback    = NULL;
1973 
    /* Enable SPI peripheral */
 1973 
 
1974 
    __HAL_SPI_ENABLE(hspi);
 1974 
  /* Enable the Tx DMA Stream/Channel  */
1975 
  }
 1975 
  if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
1976 
  /* Enable the SPI Error Interrupt Bit */
 1976 
                                 hspi->TxXferCount))
1977 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
 1977 
  {
1978 
 
 1978 
    /* Update SPI error code */
1979 
  /* Enable Tx DMA Request */
 1979 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
1980 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
 1980 
    errorcode = HAL_ERROR;
1981 
 
 1981 
 
1982 
error :
 1982 
    goto error;
1983 
  /* Process Unlocked */
 1983 
  }
1984 
  __HAL_UNLOCK(hspi);
 1984 
 
1985 
  return errorcode;
 1985 
  /* Check if the SPI is already enabled */
1986 
}
 1986 
  if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE)
1987 
 
 1987 
  {
1988 
/**
 1988 
    /* Enable SPI peripheral */
1989 
  * @brief  Abort ongoing transfer (blocking mode).
 1989 
    __HAL_SPI_ENABLE(hspi);
1990 
  * @param  hspi SPI handle.
 1990 
  }
1991 
  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
 1991 
  /* Enable the SPI Error Interrupt Bit */
1992 
  *         started in Interrupt or DMA mode.
 1992 
  __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR));
1993 
  *         This procedure performs following operations :
 1993 
 
1994 
  *           - Disable SPI Interrupts (depending of transfer direction)
 1994 
  /* Enable Tx DMA Request */
1995 
  *           - Disable the DMA transfer in the peripheral register (if enabled)
 1995 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
1996 
  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
 1996 
 
1997 
  *           - Set handle State to READY
 1997 
error :
1998 
  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
 1998 
  /* Process Unlocked */
1999 
  * @retval HAL status
 1999 
  __HAL_UNLOCK(hspi);
2000 
  */
 2000 
  return errorcode;
2001 
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
 2001 
}
2002 
{
 2002 
 
2003 
  HAL_StatusTypeDef errorcode;
 2003 
/**
2004 
  __IO uint32_t count;
 2004 
  * @brief  Abort ongoing transfer (blocking mode).
2005 
  __IO uint32_t resetcount;
 2005 
  * @param  hspi SPI handle.
2006 
 
 2006 
  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2007 
  /* Initialized local variable  */
 2007 
  *         started in Interrupt or DMA mode.
2008 
  errorcode = HAL_OK;
 2008 
  *         This procedure performs following operations :
2009 
  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 2009 
  *           - Disable SPI Interrupts (depending of transfer direction)
2010 
  count = resetcount;
 2010 
  *           - Disable the DMA transfer in the peripheral register (if enabled)
2011 
 
 2011 
  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
2012 
  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
 2012 
  *           - Set handle State to READY
2013 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
 2013 
  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
2014 
 
 2014 
  * @retval HAL status
2015 
  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
 2015 
  */
2016 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
 2016 
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
2017 
  {
 2017 
{
2018 
    hspi->TxISR = SPI_AbortTx_ISR;
 2018 
  HAL_StatusTypeDef errorcode;
2019 
    /* Wait HAL_SPI_STATE_ABORT state */
 2019 
  __IO uint32_t count;
2020 
    do
 2020 
  __IO uint32_t resetcount;
2021 
    {
 2021 
 
2022 
      if (count == 0U)
 2022 
  /* Initialized local variable  */
2023 
      {
 2023 
  errorcode = HAL_OK;
2024 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2024 
  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2025 
        break;
 2025 
  count = resetcount;
2026 
      }
 2026 
 
2027 
      count--;
 2027 
  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2028 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
 2028 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2029 
    /* Reset Timeout Counter */
 2029 
 
2030 
    count = resetcount;
 2030 
  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
2031 
  }
 2031 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2032 
 
 2032 
  {
2033 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
 2033 
    hspi->TxISR = SPI_AbortTx_ISR;
2034 
  {
 2034 
    /* Wait HAL_SPI_STATE_ABORT state */
2035 
    hspi->RxISR = SPI_AbortRx_ISR;
 2035 
    do
2036 
    /* Wait HAL_SPI_STATE_ABORT state */
 2036 
    {
2037 
    do
 2037 
      if (count == 0U)
2038 
    {
 2038 
      {
2039 
      if (count == 0U)
 2039 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2040 
      {
 2040 
        break;
2041 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2041 
      }
2042 
        break;
 2042 
      count--;
2043 
      }
 2043 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
2044 
      count--;
 2044 
    /* Reset Timeout Counter */
2045 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
 2045 
    count = resetcount;
2046 
    /* Reset Timeout Counter */
 2046 
  }
2047 
    count = resetcount;
 2047 
 
2048 
  }
 2048 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2049 
 
 2049 
  {
2050 
  /* Disable the SPI DMA Tx request if enabled */
 2050 
    hspi->RxISR = SPI_AbortRx_ISR;
2051 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
 2051 
    /* Wait HAL_SPI_STATE_ABORT state */
2052 
  {
 2052 
    do
2053 
    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
 2053 
    {
2054 
    if (hspi->hdmatx != NULL)
 2054 
      if (count == 0U)
2055 
    {
 2055 
      {
2056 
      /* Set the SPI DMA Abort callback :
 2056 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2057 
      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
 2057 
        break;
2058 
      hspi->hdmatx->XferAbortCallback = NULL;
 2058 
      }
2059 
 
 2059 
      count--;
2060 
      /* Abort DMA Tx Handle linked to SPI Peripheral */
 2060 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
2061 
      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
 2061 
    /* Reset Timeout Counter */
2062 
      {
 2062 
    count = resetcount;
2063 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
 2063 
  }
2064 
      }
 2064 
 
2065 
 
 2065 
  /* Disable the SPI DMA Tx request if enabled */
2066 
      /* Disable Tx DMA Request */
 2066 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2067 
      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
 2067 
  {
2068 
 
 2068 
    /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */
2069 
      /* Wait until TXE flag is set */
 2069 
    if (hspi->hdmatx != NULL)
2070 
      do
 2070 
    {
2071 
      {
 2071 
      /* Set the SPI DMA Abort callback :
2072 
        if (count == 0U)
 2072 
      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2073 
        {
 2073 
      hspi->hdmatx->XferAbortCallback = NULL;
2074 
          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2074 
 
2075 
          break;
 2075 
      /* Abort DMA Tx Handle linked to SPI Peripheral */
2076 
        }
 2076 
      if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK)
2077 
        count--;
 2077 
      {
2078 
      } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
 2078 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2079 
    }
 2079 
      }
2080 
  }
 2080 
 
2081 
 
 2081 
      /* Disable Tx DMA Request */
2082 
  /* Disable the SPI DMA Rx request if enabled */
 2082 
      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN));
2083 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
 2083 
 
2084 
  {
 2084 
      /* Wait until TXE flag is set */
2085 
    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
 2085 
      do
2086 
    if (hspi->hdmarx != NULL)
 2086 
      {
2087 
    {
 2087 
        if (count == 0U)
2088 
      /* Set the SPI DMA Abort callback :
 2088 
        {
2089 
      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
 2089 
          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2090 
      hspi->hdmarx->XferAbortCallback = NULL;
 2090 
          break;
2091 
 
 2091 
        }
2092 
      /* Abort DMA Rx Handle linked to SPI Peripheral */
 2092 
        count--;
2093 
      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
 2093 
      } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
2094 
      {
 2094 
    }
2095 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
 2095 
  }
2096 
      }
 2096 
 
2097 
 
 2097 
  /* Disable the SPI DMA Rx request if enabled */
2098 
      /* Disable peripheral */
 2098 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2099 
      __HAL_SPI_DISABLE(hspi);
 2099 
  {
2100 
 
 2100 
    /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */
2101 
      /* Disable Rx DMA Request */
 2101 
    if (hspi->hdmarx != NULL)
2102 
      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
 2102 
    {
2103 
    }
 2103 
      /* Set the SPI DMA Abort callback :
2104 
  }
 2104 
      will lead to call HAL_SPI_AbortCpltCallback() at end of DMA abort procedure */
2105 
  /* Reset Tx and Rx transfer counters */
 2105 
      hspi->hdmarx->XferAbortCallback = NULL;
2106 
  hspi->RxXferCount = 0U;
 2106 
 
2107 
  hspi->TxXferCount = 0U;
 2107 
      /* Abort DMA Rx Handle linked to SPI Peripheral */
2108 
 
 2108 
      if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK)
2109 
  /* Check error during Abort procedure */
 2109 
      {
2110 
  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
 2110 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2111 
  {
 2111 
      }
2112 
    /* return HAL_Error in case of error during Abort procedure */
 2112 
 
2113 
    errorcode = HAL_ERROR;
 2113 
      /* Disable peripheral */
2114 
  }
 2114 
      __HAL_SPI_DISABLE(hspi);
2115 
  else
 2115 
 
2116 
  {
 2116 
      /* Disable Rx DMA Request */
2117 
    /* Reset errorCode */
 2117 
      CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_RXDMAEN));
2118 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 2118 
    }
2119 
  }
 2119 
  }
2120 
 
 2120 
  /* Reset Tx and Rx transfer counters */
2121 
  /* Clear the Error flags in the SR register */
 2121 
  hspi->RxXferCount = 0U;
2122 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
 2122 
  hspi->TxXferCount = 0U;
2123 
#if defined(SPI_CR2_FRF)
 2123 
 
2124 
  __HAL_SPI_CLEAR_FREFLAG(hspi);
 2124 
  /* Check error during Abort procedure */
2125 
#endif
 2125 
  if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2126 
 
 2126 
  {
2127 
  /* Restore hspi->state to ready */
 2127 
    /* return HAL_Error in case of error during Abort procedure */
2128 
  hspi->State = HAL_SPI_STATE_READY;
 2128 
    errorcode = HAL_ERROR;
2129 
 
 2129 
  }
2130 
  return errorcode;
 2130 
  else
2131 
}
 2131 
  {
2132 
 
 2132 
    /* Reset errorCode */
2133 
/**
 2133 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2134 
  * @brief  Abort ongoing transfer (Interrupt mode).
 2134 
  }
2135 
  * @param  hspi SPI handle.
 2135 
 
2136 
  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
 2136 
  /* Clear the Error flags in the SR register */
2137 
  *         started in Interrupt or DMA mode.
 2137 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
2138 
  *         This procedure performs following operations :
 2138 
#if defined(SPI_CR2_FRF)
2139 
  *           - Disable SPI Interrupts (depending of transfer direction)
 2139 
  __HAL_SPI_CLEAR_FREFLAG(hspi);
2140 
  *           - Disable the DMA transfer in the peripheral register (if enabled)
 2140 
#endif /* SPI_CR2_FRF */
2141 
  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
 2141 
 
2142 
  *           - Set handle State to READY
 2142 
  /* Restore hspi->state to ready */
2143 
  *           - At abort completion, call user abort complete callback
 2143 
  hspi->State = HAL_SPI_STATE_READY;
2144 
  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
 2144 
 
2145 
  *         considered as completed only when user abort complete callback is executed (not when exiting function).
 2145 
  return errorcode;
2146 
  * @retval HAL status
 2146 
}
2147 
  */
 2147 
 
2148 
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
 2148 
/**
2149 
{
 2149 
  * @brief  Abort ongoing transfer (Interrupt mode).
2150 
  HAL_StatusTypeDef errorcode;
 2150 
  * @param  hspi SPI handle.
2151 
  uint32_t abortcplt ;
 2151 
  * @note   This procedure could be used for aborting any ongoing transfer (Tx and Rx),
2152 
  __IO uint32_t count;
 2152 
  *         started in Interrupt or DMA mode.
2153 
  __IO uint32_t resetcount;
 2153 
  *         This procedure performs following operations :
2154 
 
 2154 
  *           - Disable SPI Interrupts (depending of transfer direction)
2155 
  /* Initialized local variable  */
 2155 
  *           - Disable the DMA transfer in the peripheral register (if enabled)
2156 
  errorcode = HAL_OK;
 2156 
  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
2157 
  abortcplt = 1U;
 2157 
  *           - Set handle State to READY
2158 
  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 2158 
  *           - At abort completion, call user abort complete callback
2159 
  count = resetcount;
 2159 
  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
2160 
 
 2160 
  *         considered as completed only when user abort complete callback is executed (not when exiting function).
2161 
  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
 2161 
  * @retval HAL status
2162 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
 2162 
  */
2163 
 
 2163 
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
2164 
  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
 2164 
{
2165 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
 2165 
  HAL_StatusTypeDef errorcode;
2166 
  {
 2166 
  uint32_t abortcplt ;
2167 
    hspi->TxISR = SPI_AbortTx_ISR;
 2167 
  __IO uint32_t count;
2168 
    /* Wait HAL_SPI_STATE_ABORT state */
 2168 
  __IO uint32_t resetcount;
2169 
    do
 2169 
 
2170 
    {
 2170 
  /* Initialized local variable  */
2171 
      if (count == 0U)
 2171 
  errorcode = HAL_OK;
2172 
      {
 2172 
  abortcplt = 1U;
2173 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2173 
  resetcount = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
2174 
        break;
 2174 
  count = resetcount;
2175 
      }
 2175 
 
2176 
      count--;
 2176 
  /* Clear ERRIE interrupt to avoid error interrupts generation during Abort procedure */
2177 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
 2177 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_ERRIE);
2178 
    /* Reset Timeout Counter */
 2178 
 
2179 
    count = resetcount;
 2179 
  /* Change Rx and Tx Irq Handler to Disable TXEIE, RXNEIE and ERRIE interrupts */
2180 
  }
 2180 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE))
2181 
 
 2181 
  {
2182 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
 2182 
    hspi->TxISR = SPI_AbortTx_ISR;
2183 
  {
 2183 
    /* Wait HAL_SPI_STATE_ABORT state */
2184 
    hspi->RxISR = SPI_AbortRx_ISR;
 2184 
    do
2185 
    /* Wait HAL_SPI_STATE_ABORT state */
 2185 
    {
2186 
    do
 2186 
      if (count == 0U)
2187 
    {
 2187 
      {
2188 
      if (count == 0U)
 2188 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2189 
      {
 2189 
        break;
2190 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2190 
      }
2191 
        break;
 2191 
      count--;
2192 
      }
 2192 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
2193 
      count--;
 2193 
    /* Reset Timeout Counter */
2194 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
 2194 
    count = resetcount;
2195 
    /* Reset Timeout Counter */
 2195 
  }
2196 
    count = resetcount;
 2196 
 
2197 
  }
 2197 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE))
2198 
 
 2198 
  {
2199 
  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
 2199 
    hspi->RxISR = SPI_AbortRx_ISR;
2200 
     before any call to DMA Abort functions */
 2200 
    /* Wait HAL_SPI_STATE_ABORT state */
2201 
  /* DMA Tx Handle is valid */
 2201 
    do
2202 
  if (hspi->hdmatx != NULL)
 2202 
    {
2203 
  {
 2203 
      if (count == 0U)
2204 
    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
 2204 
      {
2205 
       Otherwise, set it to NULL */
 2205 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2206 
    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
 2206 
        break;
2207 
    {
 2207 
      }
2208 
      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
 2208 
      count--;
2209 
    }
 2209 
    } while (hspi->State != HAL_SPI_STATE_ABORT);
2210 
    else
 2210 
    /* Reset Timeout Counter */
2211 
    {
 2211 
    count = resetcount;
2212 
      hspi->hdmatx->XferAbortCallback = NULL;
 2212 
  }
2213 
    }
 2213 
 
2214 
  }
 2214 
  /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialised
2215 
  /* DMA Rx Handle is valid */
 2215 
     before any call to DMA Abort functions */
2216 
  if (hspi->hdmarx != NULL)
 2216 
  /* DMA Tx Handle is valid */
2217 
  {
 2217 
  if (hspi->hdmatx != NULL)
2218 
    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
 2218 
  {
2219 
       Otherwise, set it to NULL */
 2219 
    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
2220 
    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
 2220 
       Otherwise, set it to NULL */
2221 
    {
 2221 
    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2222 
      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
 2222 
    {
2223 
    }
 2223 
      hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback;
2224 
    else
 2224 
    }
2225 
    {
 2225 
    else
2226 
      hspi->hdmarx->XferAbortCallback = NULL;
 2226 
    {
2227 
    }
 2227 
      hspi->hdmatx->XferAbortCallback = NULL;
2228 
  }
 2228 
    }
2229 
 
 2229 
  }
2230 
  /* Disable the SPI DMA Tx request if enabled */
 2230 
  /* DMA Rx Handle is valid */
2231 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
 2231 
  if (hspi->hdmarx != NULL)
2232 
  {
 2232 
  {
2233 
    /* Abort the SPI DMA Tx Stream/Channel */
 2233 
    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
2234 
    if (hspi->hdmatx != NULL)
 2234 
       Otherwise, set it to NULL */
2235 
    {
 2235 
    if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2236 
      /* Abort DMA Tx Handle linked to SPI Peripheral */
 2236 
    {
2237 
      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
 2237 
      hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback;
2238 
      {
 2238 
    }
2239 
        hspi->hdmatx->XferAbortCallback = NULL;
 2239 
    else
2240 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
 2240 
    {
2241 
      }
 2241 
      hspi->hdmarx->XferAbortCallback = NULL;
2242 
      else
 2242 
    }
2243 
      {
 2243 
  }
2244 
        abortcplt = 0U;
 2244 
 
2245 
      }
 2245 
  /* Disable the SPI DMA Tx request if enabled */
2246 
    }
 2246 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXDMAEN))
2247 
  }
 2247 
  {
2248 
  /* Disable the SPI DMA Rx request if enabled */
 2248 
    /* Abort the SPI DMA Tx Stream/Channel */
2249 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
 2249 
    if (hspi->hdmatx != NULL)
2250 
  {
 2250 
    {
2251 
    /* Abort the SPI DMA Rx Stream/Channel */
 2251 
      /* Abort DMA Tx Handle linked to SPI Peripheral */
2252 
    if (hspi->hdmarx != NULL)
 2252 
      if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK)
2253 
    {
 2253 
      {
2254 
      /* Abort DMA Rx Handle linked to SPI Peripheral */
 2254 
        hspi->hdmatx->XferAbortCallback = NULL;
2255 
      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
 2255 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2256 
      {
 2256 
      }
2257 
        hspi->hdmarx->XferAbortCallback = NULL;
 2257 
      else
2258 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
 2258 
      {
2259 
      }
 2259 
        abortcplt = 0U;
2260 
      else
 2260 
      }
2261 
      {
 2261 
    }
2262 
        abortcplt = 0U;
 2262 
  }
2263 
      }
 2263 
  /* Disable the SPI DMA Rx request if enabled */
2264 
    }
 2264 
  if (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXDMAEN))
2265 
  }
 2265 
  {
2266 
 
 2266 
    /* Abort the SPI DMA Rx Stream/Channel */
2267 
  if (abortcplt == 1U)
 2267 
    if (hspi->hdmarx != NULL)
2268 
  {
 2268 
    {
2269 
    /* Reset Tx and Rx transfer counters */
 2269 
      /* Abort DMA Rx Handle linked to SPI Peripheral */
2270 
    hspi->RxXferCount = 0U;
 2270 
      if (HAL_DMA_Abort_IT(hspi->hdmarx) !=  HAL_OK)
2271 
    hspi->TxXferCount = 0U;
 2271 
      {
2272 
 
 2272 
        hspi->hdmarx->XferAbortCallback = NULL;
2273 
    /* Check error during Abort procedure */
 2273 
        hspi->ErrorCode = HAL_SPI_ERROR_ABORT;
2274 
    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
 2274 
      }
2275 
    {
 2275 
      else
2276 
      /* return HAL_Error in case of error during Abort procedure */
 2276 
      {
2277 
      errorcode = HAL_ERROR;
 2277 
        abortcplt = 0U;
2278 
    }
 2278 
      }
2279 
    else
 2279 
    }
2280 
    {
 2280 
  }
2281 
      /* Reset errorCode */
 2281 
 
2282 
      hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 2282 
  if (abortcplt == 1U)
2283 
    }
 2283 
  {
2284 
 
 2284 
    /* Reset Tx and Rx transfer counters */
2285 
    /* Clear the Error flags in the SR register */
 2285 
    hspi->RxXferCount = 0U;
2286 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 2286 
    hspi->TxXferCount = 0U;
2287 
#if defined(SPI_CR2_FRF)
 2287 
 
2288 
    __HAL_SPI_CLEAR_FREFLAG(hspi);
 2288 
    /* Check error during Abort procedure */
2289 
#endif
 2289 
    if (hspi->ErrorCode == HAL_SPI_ERROR_ABORT)
2290 
 
 2290 
    {
2291 
    /* Restore hspi->State to Ready */
 2291 
      /* return HAL_Error in case of error during Abort procedure */
2292 
    hspi->State = HAL_SPI_STATE_READY;
 2292 
      errorcode = HAL_ERROR;
2293 
 
 2293 
    }
2294 
    /* As no DMA to be aborted, call directly user Abort complete callback */
 2294 
    else
2295 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2295 
    {
2296 
    hspi->AbortCpltCallback(hspi);
 2296 
      /* Reset errorCode */
2297 
#else
 2297 
      hspi->ErrorCode = HAL_SPI_ERROR_NONE;
2298 
    HAL_SPI_AbortCpltCallback(hspi);
 2298 
    }
2299 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2299 
 
2300 
  }
 2300 
    /* Clear the Error flags in the SR register */
2301 
 
 2301 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
2302 
  return errorcode;
 2302 
#if defined(SPI_CR2_FRF)
2303 
}
 2303 
    __HAL_SPI_CLEAR_FREFLAG(hspi);
2304 
 
 2304 
#endif /* SPI_CR2_FRF */
2305 
/**
 2305 
 
2306 
  * @brief  Pause the DMA Transfer.
 2306 
    /* Restore hspi->State to Ready */
2307 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2307 
    hspi->State = HAL_SPI_STATE_READY;
2308 
  *               the configuration information for the specified SPI module.
 2308 
 
2309 
  * @retval HAL status
 2309 
    /* As no DMA to be aborted, call directly user Abort complete callback */
2310 
  */
 2310 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2311 
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
 2311 
    hspi->AbortCpltCallback(hspi);
2312 
{
 2312 
#else
2313 
  /* Process Locked */
 2313 
    HAL_SPI_AbortCpltCallback(hspi);
2314 
  __HAL_LOCK(hspi);
 2314 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2315 
 
 2315 
  }
2316 
  /* Disable the SPI DMA Tx & Rx requests */
 2316 
 
2317 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 2317 
  return errorcode;
2318 
 
 2318 
}
2319 
  /* Process Unlocked */
 2319 
 
2320 
  __HAL_UNLOCK(hspi);
 2320 
/**
2321 
 
 2321 
  * @brief  Pause the DMA Transfer.
2322 
  return HAL_OK;
 2322 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2323 
}
 2323 
  *               the configuration information for the specified SPI module.
2324 
 
 2324 
  * @retval HAL status
2325 
/**
 2325 
  */
2326 
  * @brief  Resume the DMA Transfer.
 2326 
HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
2327 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2327 
{
2328 
  *               the configuration information for the specified SPI module.
 2328 
  /* Process Locked */
2329 
  * @retval HAL status
 2329 
  __HAL_LOCK(hspi);
2330 
  */
 2330 
 
2331 
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
 2331 
  /* Disable the SPI DMA Tx & Rx requests */
2332 
{
 2332 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2333 
  /* Process Locked */
 2333 
 
2334 
  __HAL_LOCK(hspi);
 2334 
  /* Process Unlocked */
2335 
 
 2335 
  __HAL_UNLOCK(hspi);
2336 
  /* Enable the SPI DMA Tx & Rx requests */
 2336 
 
2337 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 2337 
  return HAL_OK;
2338 
 
 2338 
}
2339 
  /* Process Unlocked */
 2339 
 
2340 
  __HAL_UNLOCK(hspi);
 2340 
/**
2341 
 
 2341 
  * @brief  Resume the DMA Transfer.
2342 
  return HAL_OK;
 2342 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2343 
}
 2343 
  *               the configuration information for the specified SPI module.
2344 
 
 2344 
  * @retval HAL status
2345 
/**
 2345 
  */
2346 
  * @brief  Stop the DMA Transfer.
 2346 
HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
2347 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2347 
{
2348 
  *               the configuration information for the specified SPI module.
 2348 
  /* Process Locked */
2349 
  * @retval HAL status
 2349 
  __HAL_LOCK(hspi);
2350 
  */
 2350 
 
2351 
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
 2351 
  /* Enable the SPI DMA Tx & Rx requests */
2352 
{
 2352 
  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2353 
  HAL_StatusTypeDef errorcode = HAL_OK;
 2353 
 
2354 
  /* The Lock is not implemented on this API to allow the user application
 2354 
  /* Process Unlocked */
2355 
     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
 2355 
  __HAL_UNLOCK(hspi);
2356 
     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
 2356 
 
2357 
     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
 2357 
  return HAL_OK;
2358 
     */
 2358 
}
2359 
 
 2359 
 
2360 
  /* Abort the SPI DMA tx Stream/Channel  */
 2360 
/**
2361 
  if (hspi->hdmatx != NULL)
 2361 
  * @brief  Stop the DMA Transfer.
2362 
  {
 2362 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2363 
    if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
 2363 
  *               the configuration information for the specified SPI module.
2364 
    {
 2364 
  * @retval HAL status
2365 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 2365 
  */
2366 
      errorcode = HAL_ERROR;
 2366 
HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
2367 
    }
 2367 
{
2368 
  }
 2368 
  HAL_StatusTypeDef errorcode = HAL_OK;
2369 
  /* Abort the SPI DMA rx Stream/Channel  */
 2369 
  /* The Lock is not implemented on this API to allow the user application
2370 
  if (hspi->hdmarx != NULL)
 2370 
     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
2371 
  {
 2371 
     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
2372 
    if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
 2372 
     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
2373 
    {
 2373 
     */
2374 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 2374 
 
2375 
      errorcode = HAL_ERROR;
 2375 
  /* Abort the SPI DMA tx Stream/Channel  */
2376 
    }
 2376 
  if (hspi->hdmatx != NULL)
2377 
  }
 2377 
  {
2378 
 
 2378 
    if (HAL_OK != HAL_DMA_Abort(hspi->hdmatx))
2379 
  /* Disable the SPI DMA Tx & Rx requests */
 2379 
    {
2380 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 2380 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2381 
  hspi->State = HAL_SPI_STATE_READY;
 2381 
      errorcode = HAL_ERROR;
2382 
  return errorcode;
 2382 
    }
2383 
}
 2383 
  }
2384 
 
 2384 
  /* Abort the SPI DMA rx Stream/Channel  */
2385 
/**
 2385 
  if (hspi->hdmarx != NULL)
2386 
  * @brief  Handle SPI interrupt request.
 2386 
  {
2387 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2387 
    if (HAL_OK != HAL_DMA_Abort(hspi->hdmarx))
2388 
  *               the configuration information for the specified SPI module.
 2388 
    {
2389 
  * @retval None
 2389 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2390 
  */
 2390 
      errorcode = HAL_ERROR;
2391 
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
 2391 
    }
2392 
{
 2392 
  }
2393 
  uint32_t itsource = hspi->Instance->CR2;
 2393 
 
2394 
  uint32_t itflag   = hspi->Instance->SR;
 2394 
  /* Disable the SPI DMA Tx & Rx requests */
2395 
 
 2395 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2396 
  /* SPI in mode Receiver ----------------------------------------------------*/
 2396 
  hspi->State = HAL_SPI_STATE_READY;
2397 
  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
 2397 
  return errorcode;
2398 
      (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
 2398 
}
2399 
  {
 2399 
 
2400 
    hspi->RxISR(hspi);
 2400 
/**
2401 
    return;
 2401 
  * @brief  Handle SPI interrupt request.
2402 
  }
 2402 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2403 
 
 2403 
  *               the configuration information for the specified SPI module.
2404 
  /* SPI in mode Transmitter -------------------------------------------------*/
 2404 
  * @retval None
2405 
  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
 2405 
  */
2406 
  {
 2406 
void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
2407 
    hspi->TxISR(hspi);
 2407 
{
2408 
    return;
 2408 
  uint32_t itsource = hspi->Instance->CR2;
2409 
  }
 2409 
  uint32_t itflag   = hspi->Instance->SR;
2410 
 
 2410 
 
2411 
  /* SPI in Error Treatment --------------------------------------------------*/
 2411 
  /* SPI in mode Receiver ----------------------------------------------------*/
2412 
#if defined(SPI_CR2_FRF)
 2412 
  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) == RESET) &&
2413 
  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
 2413 
      (SPI_CHECK_FLAG(itflag, SPI_FLAG_RXNE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_RXNE) != RESET))
2414 
       || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
 2414 
  {
2415 
#else
 2415 
    hspi->RxISR(hspi);
2416 
  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET))
 2416 
    return;
2417 
      && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
 2417 
  }
2418 
#endif
 2418 
 
2419 
  {
 2419 
  /* SPI in mode Transmitter -------------------------------------------------*/
2420 
    /* SPI Overrun error interrupt occurred ----------------------------------*/
 2420 
  if ((SPI_CHECK_FLAG(itflag, SPI_FLAG_TXE) != RESET) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_TXE) != RESET))
2421 
    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
 2421 
  {
2422 
    {
 2422 
    hspi->TxISR(hspi);
2423 
      if (hspi->State != HAL_SPI_STATE_BUSY_TX)
 2423 
    return;
2424 
      {
 2424 
  }
2425 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
 2425 
 
2426 
        __HAL_SPI_CLEAR_OVRFLAG(hspi);
 2426 
  /* SPI in Error Treatment --------------------------------------------------*/
2427 
      }
 2427 
#if defined(SPI_CR2_FRF)
2428 
      else
 2428 
  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2429 
      {
 2429 
       || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2430 
        __HAL_SPI_CLEAR_OVRFLAG(hspi);
 2430 
#else
2431 
        return;
 2431 
  if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET))
2432 
      }
 2432 
      && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
2433 
    }
 2433 
#endif /* SPI_CR2_FRF */
2434 
 
 2434 
  {
2435 
    /* SPI Mode Fault error interrupt occurred -------------------------------*/
 2435 
    /* SPI Overrun error interrupt occurred ----------------------------------*/
2436 
    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
 2436 
    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
2437 
    {
 2437 
    {
2438 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
 2438 
      if (hspi->State != HAL_SPI_STATE_BUSY_TX)
2439 
      __HAL_SPI_CLEAR_MODFFLAG(hspi);
 2439 
      {
2440 
    }
 2440 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
2441 
 
 2441 
        __HAL_SPI_CLEAR_OVRFLAG(hspi);
2442 
    /* SPI Frame error interrupt occurred ------------------------------------*/
 2442 
      }
2443 
#if defined(SPI_CR2_FRF)
 2443 
      else
2444 
    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
 2444 
      {
2445 
    {
 2445 
        __HAL_SPI_CLEAR_OVRFLAG(hspi);
2446 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
 2446 
        return;
2447 
      __HAL_SPI_CLEAR_FREFLAG(hspi);
 2447 
      }
2448 
    }
 2448 
    }
2449 
#endif
 2449 
 
2450 
 
 2450 
    /* SPI Mode Fault error interrupt occurred -------------------------------*/
2451 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 2451 
    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET)
2452 
    {
 2452 
    {
2453 
      /* Disable all interrupts */
 2453 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
2454 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
 2454 
      __HAL_SPI_CLEAR_MODFFLAG(hspi);
2455 
 
 2455 
    }
2456 
      hspi->State = HAL_SPI_STATE_READY;
 2456 
 
2457 
      /* Disable the SPI DMA requests if enabled */
 2457 
    /* SPI Frame error interrupt occurred ------------------------------------*/
2458 
      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
 2458 
#if defined(SPI_CR2_FRF)
2459 
      {
 2459 
    if (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)
2460 
        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
 2460 
    {
2461 
 
 2461 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
2462 
        /* Abort the SPI DMA Rx channel */
 2462 
      __HAL_SPI_CLEAR_FREFLAG(hspi);
2463 
        if (hspi->hdmarx != NULL)
 2463 
    }
2464 
        {
 2464 
#endif /* SPI_CR2_FRF */
2465 
          /* Set the SPI DMA Abort callback :
 2465 
 
2466 
          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
 2466 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2467 
          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
 2467 
    {
2468 
          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
 2468 
      /* Disable all interrupts */
2469 
          {
 2469 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
2470 
            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2470 
 
2471 
          }
 2471 
      hspi->State = HAL_SPI_STATE_READY;
2472 
        }
 2472 
      /* Disable the SPI DMA requests if enabled */
2473 
        /* Abort the SPI DMA Tx channel */
 2473 
      if ((HAL_IS_BIT_SET(itsource, SPI_CR2_TXDMAEN)) || (HAL_IS_BIT_SET(itsource, SPI_CR2_RXDMAEN)))
2474 
        if (hspi->hdmatx != NULL)
 2474 
      {
2475 
        {
 2475 
        CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN));
2476 
          /* Set the SPI DMA Abort callback :
 2476 
 
2477 
          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
 2477 
        /* Abort the SPI DMA Rx channel */
2478 
          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
 2478 
        if (hspi->hdmarx != NULL)
2479 
          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
 2479 
        {
2480 
          {
 2480 
          /* Set the SPI DMA Abort callback :
2481 
            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 2481 
          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2482 
          }
 2482 
          hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError;
2483 
        }
 2483 
          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx))
2484 
      }
 2484 
          {
2485 
      else
 2485 
            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2486 
      {
 2486 
          }
2487 
        /* Call user error callback */
 2487 
        }
2488 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2488 
        /* Abort the SPI DMA Tx channel */
2489 
        hspi->ErrorCallback(hspi);
 2489 
        if (hspi->hdmatx != NULL)
2490 
#else
 2490 
        {
2491 
        HAL_SPI_ErrorCallback(hspi);
 2491 
          /* Set the SPI DMA Abort callback :
2492 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2492 
          will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */
2493 
      }
 2493 
          hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError;
2494 
    }
 2494 
          if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx))
2495 
    return;
 2495 
          {
2496 
  }
 2496 
            SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
2497 
}
 2497 
          }
2498 
 
 2498 
        }
2499 
/**
 2499 
      }
2500 
  * @brief  Tx Transfer completed callback.
 2500 
      else
2501 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2501 
      {
2502 
  *               the configuration information for SPI module.
 2502 
        /* Call user error callback */
2503 
  * @retval None
 2503 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2504 
  */
 2504 
        hspi->ErrorCallback(hspi);
2505 
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
 2505 
#else
2506 
{
 2506 
        HAL_SPI_ErrorCallback(hspi);
2507 
  /* Prevent unused argument(s) compilation warning */
 2507 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2508 
  UNUSED(hspi);
 2508 
      }
2509 
 
 2509 
    }
2510 
  /* NOTE : This function should not be modified, when the callback is needed,
 2510 
    return;
2511 
            the HAL_SPI_TxCpltCallback should be implemented in the user file
 2511 
  }
2512 
   */
 2512 
}
2513 
}
 2513 
 
2514 
 
 2514 
/**
2515 
/**
 2515 
  * @brief  Tx Transfer completed callback.
2516 
  * @brief  Rx Transfer completed callback.
 2516 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2517 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2517 
  *               the configuration information for SPI module.
2518 
  *               the configuration information for SPI module.
 2518 
  * @retval None
2519 
  * @retval None
 2519 
  */
2520 
  */
 2520 
__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
2521 
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
 2521 
{
2522 
{
 2522 
  /* Prevent unused argument(s) compilation warning */
2523 
  /* Prevent unused argument(s) compilation warning */
 2523 
  UNUSED(hspi);
2524 
  UNUSED(hspi);
 2524 
 
2525 
 
 2525 
  /* NOTE : This function should not be modified, when the callback is needed,
2526 
  /* NOTE : This function should not be modified, when the callback is needed,
 2526 
            the HAL_SPI_TxCpltCallback should be implemented in the user file
2527 
            the HAL_SPI_RxCpltCallback should be implemented in the user file
 2527 
   */
2528 
   */
 2528 
}
2529 
}
 2529 
 
2530 
 
 2530 
/**
2531 
/**
 2531 
  * @brief  Rx Transfer completed callback.
2532 
  * @brief  Tx and Rx Transfer completed callback.
 2532 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2533 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2533 
  *               the configuration information for SPI module.
2534 
  *               the configuration information for SPI module.
 2534 
  * @retval None
2535 
  * @retval None
 2535 
  */
2536 
  */
 2536 
__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
2537 
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
 2537 
{
2538 
{
 2538 
  /* Prevent unused argument(s) compilation warning */
2539 
  /* Prevent unused argument(s) compilation warning */
 2539 
  UNUSED(hspi);
2540 
  UNUSED(hspi);
 2540 
 
2541 
 
 2541 
  /* NOTE : This function should not be modified, when the callback is needed,
2542 
  /* NOTE : This function should not be modified, when the callback is needed,
 2542 
            the HAL_SPI_RxCpltCallback should be implemented in the user file
2543 
            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
 2543 
   */
2544 
   */
 2544 
}
2545 
}
 2545 
 
2546 
 
 2546 
/**
2547 
/**
 2547 
  * @brief  Tx and Rx Transfer completed callback.
2548 
  * @brief  Tx Half Transfer completed callback.
 2548 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2549 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2549 
  *               the configuration information for SPI module.
2550 
  *               the configuration information for SPI module.
 2550 
  * @retval None
2551 
  * @retval None
 2551 
  */
2552 
  */
 2552 
__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
2553 
__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 2553 
{
2554 
{
 2554 
  /* Prevent unused argument(s) compilation warning */
2555 
  /* Prevent unused argument(s) compilation warning */
 2555 
  UNUSED(hspi);
2556 
  UNUSED(hspi);
 2556 
 
2557 
 
 2557 
  /* NOTE : This function should not be modified, when the callback is needed,
2558 
  /* NOTE : This function should not be modified, when the callback is needed,
 2558 
            the HAL_SPI_TxRxCpltCallback should be implemented in the user file
2559 
            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
 2559 
   */
2560 
   */
 2560 
}
2561 
}
 2561 
 
2562 
 
 2562 
/**
2563 
/**
 2563 
  * @brief  Tx Half Transfer completed callback.
2564 
  * @brief  Rx Half Transfer completed callback.
 2564 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2565 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2565 
  *               the configuration information for SPI module.
2566 
  *               the configuration information for SPI module.
 2566 
  * @retval None
2567 
  * @retval None
 2567 
  */
2568 
  */
 2568 
__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2569 
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 2569 
{
2570 
{
 2570 
  /* Prevent unused argument(s) compilation warning */
2571 
  /* Prevent unused argument(s) compilation warning */
 2571 
  UNUSED(hspi);
2572 
  UNUSED(hspi);
 2572 
 
2573 
 
 2573 
  /* NOTE : This function should not be modified, when the callback is needed,
2574 
  /* NOTE : This function should not be modified, when the callback is needed,
 2574 
            the HAL_SPI_TxHalfCpltCallback should be implemented in the user file
2575 
            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
 2575 
   */
2576 
   */
 2576 
}
2577 
}
 2577 
 
2578 
 
 2578 
/**
2579 
/**
 2579 
  * @brief  Rx Half Transfer completed callback.
2580 
  * @brief  Tx and Rx Half Transfer callback.
 2580 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2581 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2581 
  *               the configuration information for SPI module.
2582 
  *               the configuration information for SPI module.
 2582 
  * @retval None
2583 
  * @retval None
 2583 
  */
2584 
  */
 2584 
__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2585 
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
 2585 
{
2586 
{
 2586 
  /* Prevent unused argument(s) compilation warning */
2587 
  /* Prevent unused argument(s) compilation warning */
 2587 
  UNUSED(hspi);
2588 
  UNUSED(hspi);
 2588 
 
2589 
 
 2589 
  /* NOTE : This function should not be modified, when the callback is needed,
2590 
  /* NOTE : This function should not be modified, when the callback is needed,
 2590 
            the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file
2591 
            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
 2591 
   */
2592 
   */
 2592 
}
2593 
}
 2593 
 
2594 
 
 2594 
/**
2595 
/**
 2595 
  * @brief  Tx and Rx Half Transfer callback.
2596 
  * @brief  SPI error callback.
 2596 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2597 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2597 
  *               the configuration information for SPI module.
2598 
  *               the configuration information for SPI module.
 2598 
  * @retval None
2599 
  * @retval None
 2599 
  */
2600 
  */
 2600 
__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
2601 
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
 2601 
{
2602 
{
 2602 
  /* Prevent unused argument(s) compilation warning */
2603 
  /* Prevent unused argument(s) compilation warning */
 2603 
  UNUSED(hspi);
2604 
  UNUSED(hspi);
 2604 
 
2605 
 
 2605 
  /* NOTE : This function should not be modified, when the callback is needed,
2606 
  /* NOTE : This function should not be modified, when the callback is needed,
 2606 
            the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file
2607 
            the HAL_SPI_ErrorCallback should be implemented in the user file
 2607 
   */
2608 
   */
 2608 
}
2609 
  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
 2609 
 
2610 
            and user can use HAL_SPI_GetError() API to check the latest error occurred
 2610 
/**
2611 
   */
 2611 
  * @brief  SPI error callback.
2612 
}
 2612 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2613 
 
 2613 
  *               the configuration information for SPI module.
2614 
/**
 2614 
  * @retval None
2615 
  * @brief  SPI Abort Complete callback.
 2615 
  */
2616 
  * @param  hspi SPI handle.
 2616 
__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
2617 
  * @retval None
 2617 
{
2618 
  */
 2618 
  /* Prevent unused argument(s) compilation warning */
2619 
__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
 2619 
  UNUSED(hspi);
2620 
{
 2620 
 
2621 
  /* Prevent unused argument(s) compilation warning */
 2621 
  /* NOTE : This function should not be modified, when the callback is needed,
2622 
  UNUSED(hspi);
 2622 
            the HAL_SPI_ErrorCallback should be implemented in the user file
2623 
 
 2623 
   */
2624 
  /* NOTE : This function should not be modified, when the callback is needed,
 2624 
  /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes
2625 
            the HAL_SPI_AbortCpltCallback can be implemented in the user file.
 2625 
            and user can use HAL_SPI_GetError() API to check the latest error occurred
2626 
   */
 2626 
   */
2627 
}
 2627 
}
2628 
 
 2628 
 
2629 
/**
 2629 
/**
2630 
  * @}
 2630 
  * @brief  SPI Abort Complete callback.
2631 
  */
 2631 
  * @param  hspi SPI handle.
2632 
 
 2632 
  * @retval None
2633 
/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
 2633 
  */
2634 
  * @brief   SPI control functions
 2634 
__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi)
2635 
  *
 2635 
{
2636 
@verbatim
 2636 
  /* Prevent unused argument(s) compilation warning */
2637 
 ===============================================================================
 2637 
  UNUSED(hspi);
2638 
                      ##### Peripheral State and Errors functions #####
 2638 
 
2639 
 ===============================================================================
 2639 
  /* NOTE : This function should not be modified, when the callback is needed,
2640 
    [..]
 2640 
            the HAL_SPI_AbortCpltCallback can be implemented in the user file.
2641 
    This subsection provides a set of functions allowing to control the SPI.
 2641 
   */
2642 
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
 2642 
}
2643 
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
 2643 
 
2644 
@endverbatim
 2644 
/**
2645 
  * @{
 2645 
  * @}
2646 
  */
 2646 
  */
2647 
 
 2647 
 
2648 
/**
 2648 
/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
2649 
  * @brief  Return the SPI handle state.
 2649 
  * @brief   SPI control functions
2650 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2650 
  *
2651 
  *               the configuration information for SPI module.
 2651 
@verbatim
2652 
  * @retval SPI state
 2652 
 ===============================================================================
2653 
  */
 2653 
                      ##### Peripheral State and Errors functions #####
2654 
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
 2654 
 ===============================================================================
2655 
{
 2655 
    [..]
2656 
  /* Return SPI handle state */
 2656 
    This subsection provides a set of functions allowing to control the SPI.
2657 
  return hspi->State;
 2657 
     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
2658 
}
 2658 
     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
2659 
 
 2659 
@endverbatim
2660 
/**
 2660 
  * @{
2661 
  * @brief  Return the SPI error code.
 2661 
  */
2662 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 2662 
 
2663 
  *               the configuration information for SPI module.
 2663 
/**
2664 
  * @retval SPI error code in bitmap format
 2664 
  * @brief  Return the SPI handle state.
2665 
  */
 2665 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2666 
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
 2666 
  *               the configuration information for SPI module.
2667 
{
 2667 
  * @retval SPI state
2668 
  /* Return SPI ErrorCode */
 2668 
  */
2669 
  return hspi->ErrorCode;
 2669 
HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
2670 
}
 2670 
{
2671 
 
 2671 
  /* Return SPI handle state */
2672 
/**
 2672 
  return hspi->State;
2673 
  * @}
 2673 
}
2674 
  */
 2674 
 
2675 
 
 2675 
/**
2676 
/**
 2676 
  * @brief  Return the SPI error code.
2677 
  * @}
 2677 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
2678 
  */
 2678 
  *               the configuration information for SPI module.
2679 
 
 2679 
  * @retval SPI error code in bitmap format
2680 
/** @addtogroup SPI_Private_Functions
 2680 
  */
2681 
  * @brief   Private functions
 2681 
uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
2682 
  * @{
 2682 
{
2683 
  */
 2683 
  /* Return SPI ErrorCode */
2684 
 
 2684 
  return hspi->ErrorCode;
2685 
/**
 2685 
}
2686 
  * @brief  DMA SPI transmit process complete callback.
 2686 
 
2687 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2687 
/**
2688 
  *               the configuration information for the specified DMA module.
 2688 
  * @}
2689 
  * @retval None
 2689 
  */
2690 
  */
 2690 
 
2691 
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
 2691 
/**
2692 
{
 2692 
  * @}
2693 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2693 
  */
2694 
  uint32_t tickstart;
 2694 
 
2695 
 
 2695 
/** @addtogroup SPI_Private_Functions
2696 
  /* Init tickstart for timeout management*/
 2696 
  * @brief   Private functions
2697 
  tickstart = HAL_GetTick();
 2697 
  * @{
2698 
 
 2698 
  */
2699 
  /* DMA Normal Mode */
 2699 
 
2700 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
 2700 
/**
2701 
  {
 2701 
  * @brief  DMA SPI transmit process complete callback.
2702 
    /* Disable ERR interrupt */
 2702 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2703 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
 2703 
  *               the configuration information for the specified DMA module.
2704 
 
 2704 
  * @retval None
2705 
    /* Disable Tx DMA Request */
 2705 
  */
2706 
    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
 2706 
static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma)
2707 
 
 2707 
{
2708 
    /* Check the end of the transaction */
 2708 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2709 
    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2709 
  uint32_t tickstart;
2710 
    {
 2710 
 
2711 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 2711 
  /* Init tickstart for timeout management*/
2712 
    }
 2712 
  tickstart = HAL_GetTick();
2713 
 
 2713 
 
2714 
    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
 2714 
  /* DMA Normal Mode */
2715 
    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 2715 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2716 
    {
 2716 
  {
2717 
      __HAL_SPI_CLEAR_OVRFLAG(hspi);
 2717 
    /* Disable ERR interrupt */
2718 
    }
 2718 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2719 
 
 2719 
 
2720 
    hspi->TxXferCount = 0U;
 2720 
    /* Disable Tx DMA Request */
2721 
    hspi->State = HAL_SPI_STATE_READY;
 2721 
    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
2722 
 
 2722 
 
2723 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 2723 
    /* Check the end of the transaction */
2724 
    {
 2724 
    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2725 
      /* Call user error callback */
 2725 
    {
2726 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2726 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2727 
      hspi->ErrorCallback(hspi);
 2727 
    }
2728 
#else
 2728 
 
2729 
      HAL_SPI_ErrorCallback(hspi);
 2729 
    /* Clear overrun flag in 2 Lines communication mode because received data is not read */
2730 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2730 
    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
2731 
      return;
 2731 
    {
2732 
    }
 2732 
      __HAL_SPI_CLEAR_OVRFLAG(hspi);
2733 
  }
 2733 
    }
2734 
  /* Call user Tx complete callback */
 2734 
 
2735 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2735 
    hspi->TxXferCount = 0U;
2736 
  hspi->TxCpltCallback(hspi);
 2736 
    hspi->State = HAL_SPI_STATE_READY;
2737 
#else
 2737 
 
2738 
  HAL_SPI_TxCpltCallback(hspi);
 2738 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2739 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2739 
    {
2740 
}
 2740 
      /* Call user error callback */
2741 
 
 2741 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2742 
/**
 2742 
      hspi->ErrorCallback(hspi);
2743 
  * @brief  DMA SPI receive process complete callback.
 2743 
#else
2744 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2744 
      HAL_SPI_ErrorCallback(hspi);
2745 
  *               the configuration information for the specified DMA module.
 2745 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2746 
  * @retval None
 2746 
      return;
2747 
  */
 2747 
    }
2748 
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 2748 
  }
2749 
{
 2749 
  /* Call user Tx complete callback */
2750 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2750 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2751 
  uint32_t tickstart;
 2751 
  hspi->TxCpltCallback(hspi);
2752 
#if (USE_SPI_CRC != 0U)
 2752 
#else
2753 
  __IO uint32_t tmpreg = 0U;
 2753 
  HAL_SPI_TxCpltCallback(hspi);
2754 
#endif /* USE_SPI_CRC */
 2754 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2755 
 
 2755 
}
2756 
  /* Init tickstart for timeout management*/
 2756 
 
2757 
  tickstart = HAL_GetTick();
 2757 
/**
2758 
 
 2758 
  * @brief  DMA SPI receive process complete callback.
2759 
  /* DMA Normal Mode */
 2759 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2760 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
 2760 
  *               the configuration information for the specified DMA module.
2761 
  {
 2761 
  * @retval None
2762 
    /* Disable ERR interrupt */
 2762 
  */
2763 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
 2763 
static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
2764 
 
 2764 
{
2765 
#if (USE_SPI_CRC != 0U)
 2765 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2766 
    /* CRC handling */
 2766 
  uint32_t tickstart;
2767 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 2767 
#if (USE_SPI_CRC != 0U)
2768 
    {
 2768 
  __IO uint32_t tmpreg = 0U;
2769 
      /* Wait until RXNE flag */
 2769 
#endif /* USE_SPI_CRC */
2770 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2770 
 
2771 
      {
 2771 
  /* Init tickstart for timeout management*/
2772 
        /* Error on the CRC reception */
 2772 
  tickstart = HAL_GetTick();
2773 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 2773 
 
2774 
      }
 2774 
  /* DMA Normal Mode */
2775 
      /* Read CRC */
 2775 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2776 
      tmpreg = READ_REG(hspi->Instance->DR);
 2776 
  {
2777 
      /* To avoid GCC warning */
 2777 
    /* Disable ERR interrupt */
2778 
      UNUSED(tmpreg);
 2778 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2779 
    }
 2779 
 
2780 
#endif /* USE_SPI_CRC */
 2780 
#if (USE_SPI_CRC != 0U)
2781 
 
 2781 
    /* CRC handling */
2782 
    /* Check if we are in Master RX 2 line mode */
 2782 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2783 
    if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
 2783 
    {
2784 
    {
 2784 
      /* Wait until RXNE flag */
2785 
      /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
 2785 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2786 
      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 2786 
      {
2787 
    }
 2787 
        /* Error on the CRC reception */
2788 
    else
 2788 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2789 
    {
 2789 
      }
2790 
      /* Normal case */
 2790 
      /* Read CRC */
2791 
      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
 2791 
      tmpreg = READ_REG(hspi->Instance->DR);
2792 
    }
 2792 
      /* To avoid GCC warning */
2793 
 
 2793 
      UNUSED(tmpreg);
2794 
    /* Check the end of the transaction */
 2794 
    }
2795 
    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2795 
#endif /* USE_SPI_CRC */
2796 
    {
 2796 
 
2797 
      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
 2797 
    /* Check if we are in Master RX 2 line mode */
2798 
    }
 2798 
    if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
2799 
 
 2799 
    {
2800 
    hspi->RxXferCount = 0U;
 2800 
      /* Disable Rx/Tx DMA Request (done by default to handle the case master rx direction 2 lines) */
2801 
    hspi->State = HAL_SPI_STATE_READY;
 2801 
      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2802 
 
 2802 
    }
2803 
#if (USE_SPI_CRC != 0U)
 2803 
    else
2804 
    /* Check if CRC error occurred */
 2804 
    {
2805 
    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
 2805 
      /* Normal case */
2806 
    {
 2806 
      CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
2807 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 2807 
    }
2808 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 2808 
 
2809 
    }
 2809 
    /* Check the end of the transaction */
2810 
#endif /* USE_SPI_CRC */
 2810 
    if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2811 
 
 2811 
    {
2812 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 2812 
      hspi->ErrorCode = HAL_SPI_ERROR_FLAG;
2813 
    {
 2813 
    }
2814 
      /* Call user error callback */
 2814 
 
2815 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2815 
    hspi->RxXferCount = 0U;
2816 
      hspi->ErrorCallback(hspi);
 2816 
    hspi->State = HAL_SPI_STATE_READY;
2817 
#else
 2817 
 
2818 
      HAL_SPI_ErrorCallback(hspi);
 2818 
#if (USE_SPI_CRC != 0U)
2819 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2819 
    /* Check if CRC error occurred */
2820 
      return;
 2820 
    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
2821 
    }
 2821 
    {
2822 
  }
 2822 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2823 
  /* Call user Rx complete callback */
 2823 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2824 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2824 
    }
2825 
  hspi->RxCpltCallback(hspi);
 2825 
#endif /* USE_SPI_CRC */
2826 
#else
 2826 
 
2827 
  HAL_SPI_RxCpltCallback(hspi);
 2827 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2828 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2828 
    {
2829 
}
 2829 
      /* Call user error callback */
2830 
 
 2830 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2831 
/**
 2831 
      hspi->ErrorCallback(hspi);
2832 
  * @brief  DMA SPI transmit receive process complete callback.
 2832 
#else
2833 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2833 
      HAL_SPI_ErrorCallback(hspi);
2834 
  *               the configuration information for the specified DMA module.
 2834 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2835 
  * @retval None
 2835 
      return;
2836 
  */
 2836 
    }
2837 
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
 2837 
  }
2838 
{
 2838 
  /* Call user Rx complete callback */
2839 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2839 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2840 
  uint32_t tickstart;
 2840 
  hspi->RxCpltCallback(hspi);
2841 
#if (USE_SPI_CRC != 0U)
 2841 
#else
2842 
  __IO uint32_t tmpreg = 0U;
 2842 
  HAL_SPI_RxCpltCallback(hspi);
2843 
#endif /* USE_SPI_CRC */
 2843 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2844 
 
 2844 
}
2845 
  /* Init tickstart for timeout management*/
 2845 
 
2846 
  tickstart = HAL_GetTick();
 2846 
/**
2847 
 
 2847 
  * @brief  DMA SPI transmit receive process complete callback.
2848 
  /* DMA Normal Mode */
 2848 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2849 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
 2849 
  *               the configuration information for the specified DMA module.
2850 
  {
 2850 
  * @retval None
2851 
    /* Disable ERR interrupt */
 2851 
  */
2852 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
 2852 
static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2853 
 
 2853 
{
2854 
#if (USE_SPI_CRC != 0U)
 2854 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2855 
    /* CRC handling */
 2855 
  uint32_t tickstart;
2856 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 2856 
#if (USE_SPI_CRC != 0U)
2857 
    {
 2857 
  __IO uint32_t tmpreg = 0U;
2858 
      /* Wait the CRC data */
 2858 
#endif /* USE_SPI_CRC */
2859 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2859 
 
2860 
      {
 2860 
  /* Init tickstart for timeout management*/
2861 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 2861 
  tickstart = HAL_GetTick();
2862 
      }
 2862 
 
2863 
      /* Read CRC to Flush DR and RXNE flag */
 2863 
  /* DMA Normal Mode */
2864 
      tmpreg = READ_REG(hspi->Instance->DR);
 2864 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != DMA_CCR_CIRC)
2865 
      /* To avoid GCC warning */
 2865 
  {
2866 
      UNUSED(tmpreg);
 2866 
    /* Disable ERR interrupt */
2867 
    }
 2867 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
2868 
#endif /* USE_SPI_CRC */
 2868 
 
2869 
 
 2869 
#if (USE_SPI_CRC != 0U)
2870 
    /* Check the end of the transaction */
 2870 
    /* CRC handling */
2871 
    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 2871 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
2872 
    {
 2872 
    {
2873 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 2873 
      /* Wait the CRC data */
2874 
    }
 2874 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2875 
 
 2875 
      {
2876 
    /* Disable Rx/Tx DMA Request */
 2876 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2877 
    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 2877 
      }
2878 
 
 2878 
      /* Read CRC to Flush DR and RXNE flag */
2879 
    hspi->TxXferCount = 0U;
 2879 
      tmpreg = READ_REG(hspi->Instance->DR);
2880 
    hspi->RxXferCount = 0U;
 2880 
      /* To avoid GCC warning */
2881 
    hspi->State = HAL_SPI_STATE_READY;
 2881 
      UNUSED(tmpreg);
2882 
 
 2882 
    }
2883 
#if (USE_SPI_CRC != 0U)
 2883 
#endif /* USE_SPI_CRC */
2884 
    /* Check if CRC error occurred */
 2884 
 
2885 
    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
 2885 
    /* Check the end of the transaction */
2886 
    {
 2886 
    if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
2887 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 2887 
    {
2888 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 2888 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
2889 
    }
 2889 
    }
2890 
#endif /* USE_SPI_CRC */
 2890 
 
2891 
 
 2891 
    /* Disable Rx/Tx DMA Request */
2892 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 2892 
    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2893 
    {
 2893 
 
2894 
      /* Call user error callback */
 2894 
    hspi->TxXferCount = 0U;
2895 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2895 
    hspi->RxXferCount = 0U;
2896 
      hspi->ErrorCallback(hspi);
 2896 
    hspi->State = HAL_SPI_STATE_READY;
2897 
#else
 2897 
 
2898 
      HAL_SPI_ErrorCallback(hspi);
 2898 
#if (USE_SPI_CRC != 0U)
2899 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2899 
    /* Check if CRC error occurred */
2900 
      return;
 2900 
    if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR))
2901 
    }
 2901 
    {
2902 
  }
 2902 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
2903 
  /* Call user TxRx complete callback */
 2903 
      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
2904 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2904 
    }
2905 
  hspi->TxRxCpltCallback(hspi);
 2905 
#endif /* USE_SPI_CRC */
2906 
#else
 2906 
 
2907 
  HAL_SPI_TxRxCpltCallback(hspi);
 2907 
    if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
2908 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2908 
    {
2909 
}
 2909 
      /* Call user error callback */
2910 
 
 2910 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2911 
/**
 2911 
      hspi->ErrorCallback(hspi);
2912 
  * @brief  DMA SPI half transmit process complete callback.
 2912 
#else
2913 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2913 
      HAL_SPI_ErrorCallback(hspi);
2914 
  *               the configuration information for the specified DMA module.
 2914 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2915 
  * @retval None
 2915 
      return;
2916 
  */
 2916 
    }
2917 
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
 2917 
  }
2918 
{
 2918 
  /* Call user TxRx complete callback */
2919 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2919 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2920 
 
 2920 
  hspi->TxRxCpltCallback(hspi);
2921 
  /* Call user Tx half complete callback */
 2921 
#else
2922 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2922 
  HAL_SPI_TxRxCpltCallback(hspi);
2923 
  hspi->TxHalfCpltCallback(hspi);
 2923 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2924 
#else
 2924 
}
2925 
  HAL_SPI_TxHalfCpltCallback(hspi);
 2925 
 
2926 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2926 
/**
2927 
}
 2927 
  * @brief  DMA SPI half transmit process complete callback.
2928 
 
 2928 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2929 
/**
 2929 
  *               the configuration information for the specified DMA module.
2930 
  * @brief  DMA SPI half receive process complete callback
 2930 
  * @retval None
2931 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2931 
  */
2932 
  *               the configuration information for the specified DMA module.
 2932 
static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma)
2933 
  * @retval None
 2933 
{
2934 
  */
 2934 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2935 
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
 2935 
 
2936 
{
 2936 
  /* Call user Tx half complete callback */
2937 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2937 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2938 
 
 2938 
  hspi->TxHalfCpltCallback(hspi);
2939 
  /* Call user Rx half complete callback */
 2939 
#else
2940 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2940 
  HAL_SPI_TxHalfCpltCallback(hspi);
2941 
  hspi->RxHalfCpltCallback(hspi);
 2941 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2942 
#else
 2942 
}
2943 
  HAL_SPI_RxHalfCpltCallback(hspi);
 2943 
 
2944 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2944 
/**
2945 
}
 2945 
  * @brief  DMA SPI half receive process complete callback
2946 
 
 2946 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2947 
/**
 2947 
  *               the configuration information for the specified DMA module.
2948 
  * @brief  DMA SPI half transmit receive process complete callback.
 2948 
  * @retval None
2949 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2949 
  */
2950 
  *               the configuration information for the specified DMA module.
 2950 
static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma)
2951 
  * @retval None
 2951 
{
2952 
  */
 2952 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2953 
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
 2953 
 
2954 
{
 2954 
  /* Call user Rx half complete callback */
2955 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2955 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2956 
 
 2956 
  hspi->RxHalfCpltCallback(hspi);
2957 
  /* Call user TxRx half complete callback */
 2957 
#else
2958 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2958 
  HAL_SPI_RxHalfCpltCallback(hspi);
2959 
  hspi->TxRxHalfCpltCallback(hspi);
 2959 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2960 
#else
 2960 
}
2961 
  HAL_SPI_TxRxHalfCpltCallback(hspi);
 2961 
 
2962 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2962 
/**
2963 
}
 2963 
  * @brief  DMA SPI half transmit receive process complete callback.
2964 
 
 2964 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2965 
/**
 2965 
  *               the configuration information for the specified DMA module.
2966 
  * @brief  DMA SPI communication error callback.
 2966 
  * @retval None
2967 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 2967 
  */
2968 
  *               the configuration information for the specified DMA module.
 2968 
static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma)
2969 
  * @retval None
 2969 
{
2970 
  */
 2970 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2971 
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
 2971 
 
2972 
{
 2972 
  /* Call user TxRx half complete callback */
2973 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2973 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2974 
 
 2974 
  hspi->TxRxHalfCpltCallback(hspi);
2975 
  /* Stop the disable DMA transfer on SPI side */
 2975 
#else
2976 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
 2976 
  HAL_SPI_TxRxHalfCpltCallback(hspi);
2977 
 
 2977 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
2978 
  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
 2978 
}
2979 
  hspi->State = HAL_SPI_STATE_READY;
 2979 
 
2980 
  /* Call user error callback */
 2980 
/**
2981 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 2981 
  * @brief  DMA SPI communication error callback.
2982 
  hspi->ErrorCallback(hspi);
 2982 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
2983 
#else
 2983 
  *               the configuration information for the specified DMA module.
2984 
  HAL_SPI_ErrorCallback(hspi);
 2984 
  * @retval None
2985 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 2985 
  */
2986 
}
 2986 
static void SPI_DMAError(DMA_HandleTypeDef *hdma)
2987 
 
 2987 
{
2988 
/**
 2988 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
2989 
  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
 2989 
 
2990 
  *         (To be called at end of DMA Abort procedure following error occurrence).
 2990 
  /* Stop the disable DMA transfer on SPI side */
2991 
  * @param  hdma DMA handle.
 2991 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN);
2992 
  * @retval None
 2992 
 
2993 
  */
 2993 
  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
2994 
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
 2994 
  hspi->State = HAL_SPI_STATE_READY;
2995 
{
 2995 
  /* Call user error callback */
2996 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 2996 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
2997 
  hspi->RxXferCount = 0U;
 2997 
  hspi->ErrorCallback(hspi);
2998 
  hspi->TxXferCount = 0U;
 2998 
#else
2999 
 
 2999 
  HAL_SPI_ErrorCallback(hspi);
3000 
  /* Call user error callback */
 3000 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3001 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3001 
}
3002 
  hspi->ErrorCallback(hspi);
 3002 
 
3003 
#else
 3003 
/**
3004 
  HAL_SPI_ErrorCallback(hspi);
 3004 
  * @brief  DMA SPI communication abort callback, when initiated by HAL services on Error
3005 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3005 
  *         (To be called at end of DMA Abort procedure following error occurrence).
3006 
}
 3006 
  * @param  hdma DMA handle.
3007 
 
 3007 
  * @retval None
3008 
/**
 3008 
  */
3009 
  * @brief  DMA SPI Tx communication abort callback, when initiated by user
 3009 
static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma)
3010 
  *         (To be called at end of DMA Tx Abort procedure following user abort request).
 3010 
{
3011 
  * @note   When this callback is executed, User Abort complete call back is called only if no
 3011 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3012 
  *         Abort still ongoing for Rx DMA Handle.
 3012 
  hspi->RxXferCount = 0U;
3013 
  * @param  hdma DMA handle.
 3013 
  hspi->TxXferCount = 0U;
3014 
  * @retval None
 3014 
 
3015 
  */
 3015 
  /* Call user error callback */
3016 
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
 3016 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3017 
{
 3017 
  hspi->ErrorCallback(hspi);
3018 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 3018 
#else
3019 
  __IO uint32_t count;
 3019 
  HAL_SPI_ErrorCallback(hspi);
3020 
 
 3020 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3021 
  hspi->hdmatx->XferAbortCallback = NULL;
 3021 
}
3022 
  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 3022 
 
3023 
 
 3023 
/**
3024 
  /* Disable Tx DMA Request */
 3024 
  * @brief  DMA SPI Tx communication abort callback, when initiated by user
3025 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
 3025 
  *         (To be called at end of DMA Tx Abort procedure following user abort request).
3026 
 
 3026 
  * @note   When this callback is executed, User Abort complete call back is called only if no
3027 
  /* Wait until TXE flag is set */
 3027 
  *         Abort still ongoing for Rx DMA Handle.
3028 
  do
 3028 
  * @param  hdma DMA handle.
3029 
  {
 3029 
  * @retval None
3030 
    if (count == 0U)
 3030 
  */
3031 
    {
 3031 
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
3032 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 3032 
{
3033 
      break;
 3033 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3034 
    }
 3034 
  __IO uint32_t count;
3035 
    count--;
 3035 
 
3036 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
 3036 
  hspi->hdmatx->XferAbortCallback = NULL;
3037 
 
 3037 
  count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3038 
  /* Check if an Abort process is still ongoing */
 3038 
 
3039 
  if (hspi->hdmarx != NULL)
 3039 
  /* Disable Tx DMA Request */
3040 
  {
 3040 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
3041 
    if (hspi->hdmarx->XferAbortCallback != NULL)
 3041 
 
3042 
    {
 3042 
  /* Wait until TXE flag is set */
3043 
      return;
 3043 
  do
3044 
    }
 3044 
  {
3045 
  }
 3045 
    if (count == 0U)
3046 
 
 3046 
    {
3047 
  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
 3047 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3048 
  hspi->RxXferCount = 0U;
 3048 
      break;
3049 
  hspi->TxXferCount = 0U;
 3049 
    }
3050 
 
 3050 
    count--;
3051 
  /* Check no error during Abort procedure */
 3051 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3052 
  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
 3052 
 
3053 
  {
 3053 
  /* Check if an Abort process is still ongoing */
3054 
    /* Reset errorCode */
 3054 
  if (hspi->hdmarx != NULL)
3055 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 3055 
  {
3056 
  }
 3056 
    if (hspi->hdmarx->XferAbortCallback != NULL)
3057 
 
 3057 
    {
3058 
  /* Clear the Error flags in the SR register */
 3058 
      return;
3059 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
 3059 
    }
3060 
#if defined(SPI_CR2_FRF)
 3060 
  }
3061 
  __HAL_SPI_CLEAR_FREFLAG(hspi);
 3061 
 
3062 
#endif
 3062 
  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3063 
 
 3063 
  hspi->RxXferCount = 0U;
3064 
  /* Restore hspi->State to Ready */
 3064 
  hspi->TxXferCount = 0U;
3065 
  hspi->State  = HAL_SPI_STATE_READY;
 3065 
 
3066 
 
 3066 
  /* Check no error during Abort procedure */
3067 
  /* Call user Abort complete callback */
 3067 
  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3068 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3068 
  {
3069 
  hspi->AbortCpltCallback(hspi);
 3069 
    /* Reset errorCode */
3070 
#else
 3070 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3071 
  HAL_SPI_AbortCpltCallback(hspi);
 3071 
  }
3072 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3072 
 
3073 
}
 3073 
  /* Clear the Error flags in the SR register */
3074 
 
 3074 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
3075 
/**
 3075 
#if defined(SPI_CR2_FRF)
3076 
  * @brief  DMA SPI Rx communication abort callback, when initiated by user
 3076 
  __HAL_SPI_CLEAR_FREFLAG(hspi);
3077 
  *         (To be called at end of DMA Rx Abort procedure following user abort request).
 3077 
#endif /* SPI_CR2_FRF */
3078 
  * @note   When this callback is executed, User Abort complete call back is called only if no
 3078 
 
3079 
  *         Abort still ongoing for Tx DMA Handle.
 3079 
  /* Restore hspi->State to Ready */
3080 
  * @param  hdma DMA handle.
 3080 
  hspi->State  = HAL_SPI_STATE_READY;
3081 
  * @retval None
 3081 
 
3082 
  */
 3082 
  /* Call user Abort complete callback */
3083 
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
 3083 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3084 
{
 3084 
  hspi->AbortCpltCallback(hspi);
3085 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
 3085 
#else
3086 
 
 3086 
  HAL_SPI_AbortCpltCallback(hspi);
3087 
  /* Disable SPI Peripheral */
 3087 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3088 
  __HAL_SPI_DISABLE(hspi);
 3088 
}
3089 
 
 3089 
 
3090 
  hspi->hdmarx->XferAbortCallback = NULL;
 3090 
/**
3091 
 
 3091 
  * @brief  DMA SPI Rx communication abort callback, when initiated by user
3092 
  /* Disable Rx DMA Request */
 3092 
  *         (To be called at end of DMA Rx Abort procedure following user abort request).
3093 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
 3093 
  * @note   When this callback is executed, User Abort complete call back is called only if no
3094 
 
 3094 
  *         Abort still ongoing for Tx DMA Handle.
3095 
  /* Check Busy flag */
 3095 
  * @param  hdma DMA handle.
3096 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
 3096 
  * @retval None
3097 
  {
 3097 
  */
3098 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 3098 
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
3099 
  }
 3099 
{
3100 
 
 3100 
  SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */
3101 
  /* Check if an Abort process is still ongoing */
 3101 
 
3102 
  if (hspi->hdmatx != NULL)
 3102 
  /* Disable SPI Peripheral */
3103 
  {
 3103 
  __HAL_SPI_DISABLE(hspi);
3104 
    if (hspi->hdmatx->XferAbortCallback != NULL)
 3104 
 
3105 
    {
 3105 
  hspi->hdmarx->XferAbortCallback = NULL;
3106 
      return;
 3106 
 
3107 
    }
 3107 
  /* Disable Rx DMA Request */
3108 
  }
 3108 
  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
3109 
 
 3109 
 
3110 
  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
 3110 
  /* Check Busy flag */
3111 
  hspi->RxXferCount = 0U;
 3111 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3112 
  hspi->TxXferCount = 0U;
 3112 
  {
3113 
 
 3113 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3114 
  /* Check no error during Abort procedure */
 3114 
  }
3115 
  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
 3115 
 
3116 
  {
 3116 
  /* Check if an Abort process is still ongoing */
3117 
    /* Reset errorCode */
 3117 
  if (hspi->hdmatx != NULL)
3118 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
 3118 
  {
3119 
  }
 3119 
    if (hspi->hdmatx->XferAbortCallback != NULL)
3120 
 
 3120 
    {
3121 
  /* Clear the Error flags in the SR register */
 3121 
      return;
3122 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
 3122 
    }
3123 
#if defined(SPI_CR2_FRF)
 3123 
  }
3124 
  __HAL_SPI_CLEAR_FREFLAG(hspi);
 3124 
 
3125 
#endif
 3125 
  /* No Abort process still ongoing : All DMA Stream/Channel are aborted, call user Abort Complete callback */
3126 
 
 3126 
  hspi->RxXferCount = 0U;
3127 
  /* Restore hspi->State to Ready */
 3127 
  hspi->TxXferCount = 0U;
3128 
  hspi->State  = HAL_SPI_STATE_READY;
 3128 
 
3129 
 
 3129 
  /* Check no error during Abort procedure */
3130 
  /* Call user Abort complete callback */
 3130 
  if (hspi->ErrorCode != HAL_SPI_ERROR_ABORT)
3131 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3131 
  {
3132 
  hspi->AbortCpltCallback(hspi);
 3132 
    /* Reset errorCode */
3133 
#else
 3133 
    hspi->ErrorCode = HAL_SPI_ERROR_NONE;
3134 
  HAL_SPI_AbortCpltCallback(hspi);
 3134 
  }
3135 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3135 
 
3136 
}
 3136 
  /* Clear the Error flags in the SR register */
3137 
 
 3137 
  __HAL_SPI_CLEAR_OVRFLAG(hspi);
3138 
/**
 3138 
#if defined(SPI_CR2_FRF)
3139 
  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
 3139 
  __HAL_SPI_CLEAR_FREFLAG(hspi);
3140 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3140 
#endif /* SPI_CR2_FRF */
3141 
  *               the configuration information for SPI module.
 3141 
 
3142 
  * @retval None
 3142 
  /* Restore hspi->State to Ready */
3143 
  */
 3143 
  hspi->State  = HAL_SPI_STATE_READY;
3144 
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 3144 
 
3145 
{
 3145 
  /* Call user Abort complete callback */
3146 
  /* Receive data in 8bit mode */
 3146 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3147 
  *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
 3147 
  hspi->AbortCpltCallback(hspi);
3148 
  hspi->pRxBuffPtr++;
 3148 
#else
3149 
  hspi->RxXferCount--;
 3149 
  HAL_SPI_AbortCpltCallback(hspi);
3150 
 
 3150 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3151 
  /* Check end of the reception */
 3151 
}
3152 
  if (hspi->RxXferCount == 0U)
 3152 
 
3153 
  {
 3153 
/**
3154 
#if (USE_SPI_CRC != 0U)
 3154 
  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3155 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3155 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3156 
    {
 3156 
  *               the configuration information for SPI module.
3157 
      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
 3157 
  * @retval None
3158 
      return;
 3158 
  */
3159 
    }
 3159 
static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3160 
#endif /* USE_SPI_CRC */
 3160 
{
3161 
 
 3161 
  /* Receive data in 8bit mode */
3162 
    /* Disable RXNE  and ERR interrupt */
 3162 
  *hspi->pRxBuffPtr = *((__IO uint8_t *)&hspi->Instance->DR);
3163 
    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 3163 
  hspi->pRxBuffPtr++;
3164 
 
 3164 
  hspi->RxXferCount--;
3165 
    if (hspi->TxXferCount == 0U)
 3165 
 
3166 
    {
 3166 
  /* Check end of the reception */
3167 
      SPI_CloseRxTx_ISR(hspi);
 3167 
  if (hspi->RxXferCount == 0U)
3168 
    }
 3168 
  {
3169 
  }
 3169 
#if (USE_SPI_CRC != 0U)
3170 
}
 3170 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3171 
 
 3171 
    {
3172 
#if (USE_SPI_CRC != 0U)
 3172 
      hspi->RxISR =  SPI_2linesRxISR_8BITCRC;
3173 
/**
 3173 
      return;
3174 
  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
 3174 
    }
3175 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3175 
#endif /* USE_SPI_CRC */
3176 
  *               the configuration information for SPI module.
 3176 
 
3177 
  * @retval None
 3177 
    /* Disable RXNE  and ERR interrupt */
3178 
  */
 3178 
    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3179 
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
 3179 
 
3180 
{
 3180 
    if (hspi->TxXferCount == 0U)
3181 
  __IO uint8_t  * ptmpreg8;
 3181 
    {
3182 
  __IO uint8_t  tmpreg8 = 0;
 3182 
      SPI_CloseRxTx_ISR(hspi);
3183 
 
 3183 
    }
3184 
  /* Initialize the 8bit temporary pointer */
 3184 
  }
3185 
  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
 3185 
}
3186 
  /* Read 8bit CRC to flush Data Register */
 3186 
 
3187 
  tmpreg8 = *ptmpreg8;
 3187 
#if (USE_SPI_CRC != 0U)
3188 
  /* To avoid GCC warning */
 3188 
/**
3189 
  UNUSED(tmpreg8);
 3189 
  * @brief  Rx 8-bit handler for Transmit and Receive in Interrupt mode.
3190 
 
 3190 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3191 
  /* Disable RXNE and ERR interrupt */
 3191 
  *               the configuration information for SPI module.
3192 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 3192 
  * @retval None
3193 
 
 3193 
  */
3194 
  if (hspi->TxXferCount == 0U)
 3194 
static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3195 
  {
 3195 
{
3196 
    SPI_CloseRxTx_ISR(hspi);
 3196 
  __IO uint8_t  *ptmpreg8;
3197 
  }
 3197 
  __IO uint8_t  tmpreg8 = 0;
3198 
}
 3198 
 
3199 
#endif /* USE_SPI_CRC */
 3199 
  /* Initialize the 8bit temporary pointer */
3200 
 
 3200 
  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3201 
/**
 3201 
  /* Read 8bit CRC to flush Data Register */
3202 
  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
 3202 
  tmpreg8 = *ptmpreg8;
3203 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3203 
  /* To avoid GCC warning */
3204 
  *               the configuration information for SPI module.
 3204 
  UNUSED(tmpreg8);
3205 
  * @retval None
 3205 
 
3206 
  */
 3206 
  /* Disable RXNE and ERR interrupt */
3207 
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 3207 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3208 
{
 3208 
 
3209 
  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
 3209 
  if (hspi->TxXferCount == 0U)
3210 
  hspi->pTxBuffPtr++;
 3210 
  {
3211 
  hspi->TxXferCount--;
 3211 
    SPI_CloseRxTx_ISR(hspi);
3212 
 
 3212 
  }
3213 
  /* Check the end of the transmission */
 3213 
}
3214 
  if (hspi->TxXferCount == 0U)
 3214 
#endif /* USE_SPI_CRC */
3215 
  {
 3215 
 
3216 
#if (USE_SPI_CRC != 0U)
 3216 
/**
3217 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3217 
  * @brief  Tx 8-bit handler for Transmit and Receive in Interrupt mode.
3218 
    {
 3218 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3219 
      /* Set CRC Next Bit to send CRC */
 3219 
  *               the configuration information for SPI module.
3220 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3220 
  * @retval None
3221 
      /* Disable TXE interrupt */
 3221 
  */
3222 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
 3222 
static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3223 
      return;
 3223 
{
3224 
    }
 3224 
  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3225 
#endif /* USE_SPI_CRC */
 3225 
  hspi->pTxBuffPtr++;
3226 
 
 3226 
  hspi->TxXferCount--;
3227 
    /* Disable TXE interrupt */
 3227 
 
3228 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
 3228 
  /* Check the end of the transmission */
3229 
 
 3229 
  if (hspi->TxXferCount == 0U)
3230 
    if (hspi->RxXferCount == 0U)
 3230 
  {
3231 
    {
 3231 
#if (USE_SPI_CRC != 0U)
3232 
      SPI_CloseRxTx_ISR(hspi);
 3232 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3233 
    }
 3233 
    {
3234 
  }
 3234 
      /* Set CRC Next Bit to send CRC */
3235 
}
 3235 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3236 
 
 3236 
      /* Disable TXE interrupt */
3237 
/**
 3237 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3238 
  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
 3238 
      return;
3239 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3239 
    }
3240 
  *               the configuration information for SPI module.
 3240 
#endif /* USE_SPI_CRC */
3241 
  * @retval None
 3241 
 
3242 
  */
 3242 
    /* Disable TXE interrupt */
3243 
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 3243 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3244 
{
 3244 
 
3245 
  /* Receive data in 16 Bit mode */
 3245 
    if (hspi->RxXferCount == 0U)
3246 
  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
 3246 
    {
3247 
  hspi->pRxBuffPtr += sizeof(uint16_t);
 3247 
      SPI_CloseRxTx_ISR(hspi);
3248 
  hspi->RxXferCount--;
 3248 
    }
3249 
 
 3249 
  }
3250 
  if (hspi->RxXferCount == 0U)
 3250 
}
3251 
  {
 3251 
 
3252 
#if (USE_SPI_CRC != 0U)
 3252 
/**
3253 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3253 
  * @brief  Rx 16-bit handler for Transmit and Receive in Interrupt mode.
3254 
    {
 3254 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3255 
      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
 3255 
  *               the configuration information for SPI module.
3256 
      return;
 3256 
  * @retval None
3257 
    }
 3257 
  */
3258 
#endif /* USE_SPI_CRC */
 3258 
static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3259 
 
 3259 
{
3260 
    /* Disable RXNE interrupt */
 3260 
  /* Receive data in 16 Bit mode */
3261 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
 3261 
  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3262 
 
 3262 
  hspi->pRxBuffPtr += sizeof(uint16_t);
3263 
    if (hspi->TxXferCount == 0U)
 3263 
  hspi->RxXferCount--;
3264 
    {
 3264 
 
3265 
      SPI_CloseRxTx_ISR(hspi);
 3265 
  if (hspi->RxXferCount == 0U)
3266 
    }
 3266 
  {
3267 
  }
 3267 
#if (USE_SPI_CRC != 0U)
3268 
}
 3268 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3269 
 
 3269 
    {
3270 
#if (USE_SPI_CRC != 0U)
 3270 
      hspi->RxISR =  SPI_2linesRxISR_16BITCRC;
3271 
/**
 3271 
      return;
3272 
  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
 3272 
    }
3273 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3273 
#endif /* USE_SPI_CRC */
3274 
  *               the configuration information for SPI module.
 3274 
 
3275 
  * @retval None
 3275 
    /* Disable RXNE interrupt */
3276 
  */
 3276 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3277 
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
 3277 
 
3278 
{
 3278 
    if (hspi->TxXferCount == 0U)
3279 
  __IO uint32_t tmpreg = 0U;
 3279 
    {
3280 
 
 3280 
      SPI_CloseRxTx_ISR(hspi);
3281 
  /* Read 16bit CRC to flush Data Register */
 3281 
    }
3282 
  tmpreg = READ_REG(hspi->Instance->DR);
 3282 
  }
3283 
  /* To avoid GCC warning */
 3283 
}
3284 
  UNUSED(tmpreg);  
 3284 
 
3285 
 
 3285 
#if (USE_SPI_CRC != 0U)
3286 
  /* Disable RXNE interrupt */
 3286 
/**
3287 
  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
 3287 
  * @brief  Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
3288 
 
 3288 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3289 
  SPI_CloseRxTx_ISR(hspi);
 3289 
  *               the configuration information for SPI module.
3290 
}
 3290 
  * @retval None
3291 
#endif /* USE_SPI_CRC */
 3291 
  */
3292 
 
 3292 
static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3293 
/**
 3293 
{
3294 
  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
 3294 
  __IO uint32_t tmpreg = 0U;
3295 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3295 
 
3296 
  *               the configuration information for SPI module.
 3296 
  /* Read 16bit CRC to flush Data Register */
3297 
  * @retval None
 3297 
  tmpreg = READ_REG(hspi->Instance->DR);
3298 
  */
 3298 
  /* To avoid GCC warning */
3299 
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 3299 
  UNUSED(tmpreg);
3300 
{
 3300 
 
3301 
  /* Transmit data in 16 Bit mode */
 3301 
  /* Disable RXNE interrupt */
3302 
  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 3302 
  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE);
3303 
  hspi->pTxBuffPtr += sizeof(uint16_t);
 3303 
 
3304 
  hspi->TxXferCount--;
 3304 
  SPI_CloseRxTx_ISR(hspi);
3305 
 
 3305 
}
3306 
  /* Enable CRC Transmission */
 3306 
#endif /* USE_SPI_CRC */
3307 
  if (hspi->TxXferCount == 0U)
 3307 
 
3308 
  {
 3308 
/**
3309 
#if (USE_SPI_CRC != 0U)
 3309 
  * @brief  Tx 16-bit handler for Transmit and Receive in Interrupt mode.
3310 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3310 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3311 
    {
 3311 
  *               the configuration information for SPI module.
3312 
      /* Set CRC Next Bit to send CRC */
 3312 
  * @retval None
3313 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3313 
  */
3314 
      /* Disable TXE interrupt */
 3314 
static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3315 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
 3315 
{
3316 
      return;
 3316 
  /* Transmit data in 16 Bit mode */
3317 
    }
 3317 
  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3318 
#endif /* USE_SPI_CRC */
 3318 
  hspi->pTxBuffPtr += sizeof(uint16_t);
3319 
 
 3319 
  hspi->TxXferCount--;
3320 
    /* Disable TXE interrupt */
 3320 
 
3321 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
 3321 
  /* Enable CRC Transmission */
3322 
 
 3322 
  if (hspi->TxXferCount == 0U)
3323 
    if (hspi->RxXferCount == 0U)
 3323 
  {
3324 
    {
 3324 
#if (USE_SPI_CRC != 0U)
3325 
      SPI_CloseRxTx_ISR(hspi);
 3325 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3326 
    }
 3326 
    {
3327 
  }
 3327 
      /* Set CRC Next Bit to send CRC */
3328 
}
 3328 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3329 
 
 3329 
      /* Disable TXE interrupt */
3330 
#if (USE_SPI_CRC != 0U)
 3330 
      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3331 
/**
 3331 
      return;
3332 
  * @brief  Manage the CRC 8-bit receive in Interrupt context.
 3332 
    }
3333 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3333 
#endif /* USE_SPI_CRC */
3334 
  *               the configuration information for SPI module.
 3334 
 
3335 
  * @retval None
 3335 
    /* Disable TXE interrupt */
3336 
  */
 3336 
    __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE);
3337 
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
 3337 
 
3338 
{
 3338 
    if (hspi->RxXferCount == 0U)
3339 
  __IO uint8_t  * ptmpreg8;
 3339 
    {
3340 
  __IO uint8_t  tmpreg8 = 0;
 3340 
      SPI_CloseRxTx_ISR(hspi);
3341 
 
 3341 
    }
3342 
  /* Initialize the 8bit temporary pointer */
 3342 
  }
3343 
  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
 3343 
}
3344 
  /* Read 8bit CRC to flush Data Register */
 3344 
 
3345 
  tmpreg8 = *ptmpreg8;
 3345 
#if (USE_SPI_CRC != 0U)
3346 
  /* To avoid GCC warning */
 3346 
/**
3347 
  UNUSED(tmpreg8);
 3347 
  * @brief  Manage the CRC 8-bit receive in Interrupt context.
3348 
 
 3348 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3349 
  SPI_CloseRx_ISR(hspi);
 3349 
  *               the configuration information for SPI module.
3350 
}
 3350 
  * @retval None
3351 
#endif /* USE_SPI_CRC */
 3351 
  */
3352 
 
 3352 
static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi)
3353 
/**
 3353 
{
3354 
  * @brief  Manage the receive 8-bit in Interrupt context.
 3354 
  __IO uint8_t  *ptmpreg8;
3355 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3355 
  __IO uint8_t  tmpreg8 = 0;
3356 
  *               the configuration information for SPI module.
 3356 
 
3357 
  * @retval None
 3357 
  /* Initialize the 8bit temporary pointer */
3358 
  */
 3358 
  ptmpreg8 = (__IO uint8_t *)&hspi->Instance->DR;
3359 
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 3359 
  /* Read 8bit CRC to flush Data Register */
3360 
{
 3360 
  tmpreg8 = *ptmpreg8;
3361 
  *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
 3361 
  /* To avoid GCC warning */
3362 
  hspi->pRxBuffPtr++;
 3362 
  UNUSED(tmpreg8);
3363 
  hspi->RxXferCount--;
 3363 
 
3364 
 
 3364 
  SPI_CloseRx_ISR(hspi);
3365 
#if (USE_SPI_CRC != 0U)
 3365 
}
3366 
  /* Enable CRC Transmission */
 3366 
#endif /* USE_SPI_CRC */
3367 
  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
 3367 
 
3368 
  {
 3368 
/**
3369 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3369 
  * @brief  Manage the receive 8-bit in Interrupt context.
3370 
  }
 3370 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3371 
#endif /* USE_SPI_CRC */
 3371 
  *               the configuration information for SPI module.
3372 
 
 3372 
  * @retval None
3373 
  if (hspi->RxXferCount == 0U)
 3373 
  */
3374 
  {
 3374 
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3375 
#if (USE_SPI_CRC != 0U)
 3375 
{
3376 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3376 
  *hspi->pRxBuffPtr = (*(__IO uint8_t *)&hspi->Instance->DR);
3377 
    {
 3377 
  hspi->pRxBuffPtr++;
3378 
      hspi->RxISR =  SPI_RxISR_8BITCRC;
 3378 
  hspi->RxXferCount--;
3379 
      return;
 3379 
 
3380 
    }
 3380 
#if (USE_SPI_CRC != 0U)
3381 
#endif /* USE_SPI_CRC */
 3381 
  /* Enable CRC Transmission */
3382 
    SPI_CloseRx_ISR(hspi);
 3382 
  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3383 
  }
 3383 
  {
3384 
}
 3384 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3385 
 
 3385 
  }
3386 
#if (USE_SPI_CRC != 0U)
 3386 
#endif /* USE_SPI_CRC */
3387 
/**
 3387 
 
3388 
  * @brief  Manage the CRC 16-bit receive in Interrupt context.
 3388 
  if (hspi->RxXferCount == 0U)
3389 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3389 
  {
3390 
  *               the configuration information for SPI module.
 3390 
#if (USE_SPI_CRC != 0U)
3391 
  * @retval None
 3391 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3392 
  */
 3392 
    {
3393 
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
 3393 
      hspi->RxISR =  SPI_RxISR_8BITCRC;
3394 
{
 3394 
      return;
3395 
  __IO uint32_t tmpreg = 0U;
 3395 
    }
3396 
 
 3396 
#endif /* USE_SPI_CRC */
3397 
  /* Read 16bit CRC to flush Data Register */
 3397 
    SPI_CloseRx_ISR(hspi);
3398 
  tmpreg = READ_REG(hspi->Instance->DR);
 3398 
  }
3399 
  /* To avoid GCC warning */
 3399 
}
3400 
  UNUSED(tmpreg);
 3400 
 
3401 
 
 3401 
#if (USE_SPI_CRC != 0U)
3402 
  /* Disable RXNE and ERR interrupt */
 3402 
/**
3403 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 3403 
  * @brief  Manage the CRC 16-bit receive in Interrupt context.
3404 
 
 3404 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3405 
  SPI_CloseRx_ISR(hspi);
 3405 
  *               the configuration information for SPI module.
3406 
}
 3406 
  * @retval None
3407 
#endif /* USE_SPI_CRC */
 3407 
  */
3408 
 
 3408 
static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi)
3409 
/**
 3409 
{
3410 
  * @brief  Manage the 16-bit receive in Interrupt context.
 3410 
  __IO uint32_t tmpreg = 0U;
3411 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3411 
 
3412 
  *               the configuration information for SPI module.
 3412 
  /* Read 16bit CRC to flush Data Register */
3413 
  * @retval None
 3413 
  tmpreg = READ_REG(hspi->Instance->DR);
3414 
  */
 3414 
  /* To avoid GCC warning */
3415 
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 3415 
  UNUSED(tmpreg);
3416 
{
 3416 
 
3417 
  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
 3417 
  /* Disable RXNE and ERR interrupt */
3418 
  hspi->pRxBuffPtr += sizeof(uint16_t);
 3418 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3419 
  hspi->RxXferCount--;
 3419 
 
3420 
 
 3420 
  SPI_CloseRx_ISR(hspi);
3421 
#if (USE_SPI_CRC != 0U)
 3421 
}
3422 
  /* Enable CRC Transmission */
 3422 
#endif /* USE_SPI_CRC */
3423 
  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
 3423 
 
3424 
  {
 3424 
/**
3425 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3425 
  * @brief  Manage the 16-bit receive in Interrupt context.
3426 
  }
 3426 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3427 
#endif /* USE_SPI_CRC */
 3427 
  *               the configuration information for SPI module.
3428 
 
 3428 
  * @retval None
3429 
  if (hspi->RxXferCount == 0U)
 3429 
  */
3430 
  {
 3430 
static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3431 
#if (USE_SPI_CRC != 0U)
 3431 
{
3432 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3432 
  *((uint16_t *)hspi->pRxBuffPtr) = (uint16_t)(hspi->Instance->DR);
3433 
    {
 3433 
  hspi->pRxBuffPtr += sizeof(uint16_t);
3434 
      hspi->RxISR = SPI_RxISR_16BITCRC;
 3434 
  hspi->RxXferCount--;
3435 
      return;
 3435 
 
3436 
    }
 3436 
#if (USE_SPI_CRC != 0U)
3437 
#endif /* USE_SPI_CRC */
 3437 
  /* Enable CRC Transmission */
3438 
    SPI_CloseRx_ISR(hspi);
 3438 
  if ((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE))
3439 
  }
 3439 
  {
3440 
}
 3440 
    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3441 
 
 3441 
  }
3442 
/**
 3442 
#endif /* USE_SPI_CRC */
3443 
  * @brief  Handle the data 8-bit transmit in Interrupt mode.
 3443 
 
3444 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3444 
  if (hspi->RxXferCount == 0U)
3445 
  *               the configuration information for SPI module.
 3445 
  {
3446 
  * @retval None
 3446 
#if (USE_SPI_CRC != 0U)
3447 
  */
 3447 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3448 
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
 3448 
    {
3449 
{
 3449 
      hspi->RxISR = SPI_RxISR_16BITCRC;
3450 
  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
 3450 
      return;
3451 
  hspi->pTxBuffPtr++;
 3451 
    }
3452 
  hspi->TxXferCount--;
 3452 
#endif /* USE_SPI_CRC */
3453 
 
 3453 
    SPI_CloseRx_ISR(hspi);
3454 
  if (hspi->TxXferCount == 0U)
 3454 
  }
3455 
  {
 3455 
}
3456 
#if (USE_SPI_CRC != 0U)
 3456 
 
3457 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3457 
/**
3458 
    {
 3458 
  * @brief  Handle the data 8-bit transmit in Interrupt mode.
3459 
      /* Enable CRC Transmission */
 3459 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3460 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3460 
  *               the configuration information for SPI module.
3461 
    }
 3461 
  * @retval None
3462 
#endif /* USE_SPI_CRC */
 3462 
  */
3463 
    SPI_CloseTx_ISR(hspi);
 3463 
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi)
3464 
  }
 3464 
{
3465 
}
 3465 
  *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr);
3466 
 
 3466 
  hspi->pTxBuffPtr++;
3467 
/**
 3467 
  hspi->TxXferCount--;
3468 
  * @brief  Handle the data 16-bit transmit in Interrupt mode.
 3468 
 
3469 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3469 
  if (hspi->TxXferCount == 0U)
3470 
  *               the configuration information for SPI module.
 3470 
  {
3471 
  * @retval None
 3471 
#if (USE_SPI_CRC != 0U)
3472 
  */
 3472 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3473 
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
 3473 
    {
3474 
{
 3474 
      /* Enable CRC Transmission */
3475 
  /* Transmit data in 16 Bit mode */
 3475 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3476 
  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
 3476 
    }
3477 
  hspi->pTxBuffPtr += sizeof(uint16_t);
 3477 
#endif /* USE_SPI_CRC */
3478 
  hspi->TxXferCount--;
 3478 
    SPI_CloseTx_ISR(hspi);
3479 
 
 3479 
  }
3480 
  if (hspi->TxXferCount == 0U)
 3480 
}
3481 
  {
 3481 
 
3482 
#if (USE_SPI_CRC != 0U)
 3482 
/**
3483 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3483 
  * @brief  Handle the data 16-bit transmit in Interrupt mode.
3484 
    {
 3484 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3485 
      /* Enable CRC Transmission */
 3485 
  *               the configuration information for SPI module.
3486 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
 3486 
  * @retval None
3487 
    }
 3487 
  */
3488 
#endif /* USE_SPI_CRC */
 3488 
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi)
3489 
    SPI_CloseTx_ISR(hspi);
 3489 
{
3490 
  }
 3490 
  /* Transmit data in 16 Bit mode */
3491 
}
 3491 
  hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr);
3492 
 
 3492 
  hspi->pTxBuffPtr += sizeof(uint16_t);
3493 
/**
 3493 
  hspi->TxXferCount--;
3494 
  * @brief  Handle SPI Communication Timeout.
 3494 
 
3495 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3495 
  if (hspi->TxXferCount == 0U)
3496 
  *              the configuration information for SPI module.
 3496 
  {
3497 
  * @param  Flag SPI flag to check
 3497 
#if (USE_SPI_CRC != 0U)
3498 
  * @param  State flag state to check
 3498 
    if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3499 
  * @param  Timeout Timeout duration
 3499 
    {
3500 
  * @param  Tickstart tick start value
 3500 
      /* Enable CRC Transmission */
3501 
  * @retval HAL status
 3501 
      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
3502 
  */
 3502 
    }
3503 
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
 3503 
#endif /* USE_SPI_CRC */
3504 
                                                       uint32_t Timeout, uint32_t Tickstart)
 3504 
    SPI_CloseTx_ISR(hspi);
3505 
{
 3505 
  }
3506 
  __IO uint32_t count;
 3506 
}
3507 
  uint32_t tmp_timeout;
 3507 
 
3508 
  uint32_t tmp_tickstart;
 3508 
/**
3509 
 
 3509 
  * @brief  Handle SPI Communication Timeout.
3510 
  /* Adjust Timeout value  in case of end of transfer */
 3510 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3511 
  tmp_timeout   = Timeout - (HAL_GetTick() - Tickstart);
 3511 
  *              the configuration information for SPI module.
3512 
  tmp_tickstart = HAL_GetTick();
 3512 
  * @param  Flag SPI flag to check
3513 
 
 3513 
  * @param  State flag state to check
3514 
  /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
 3514 
  * @param  Timeout Timeout duration
3515 
  count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
 3515 
  * @param  Tickstart tick start value
3516 
 
 3516 
  * @retval HAL status
3517 
  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
 3517 
  */
3518 
  {
 3518 
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus State,
3519 
    if (Timeout != HAL_MAX_DELAY)
 3519 
                                                       uint32_t Timeout, uint32_t Tickstart)
3520 
    {
 3520 
{
3521 
      if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
 3521 
  __IO uint32_t count;
3522 
      {
 3522 
  uint32_t tmp_timeout;
3523 
        /* Disable the SPI and reset the CRC: the CRC value should be cleared
 3523 
  uint32_t tmp_tickstart;
3524 
           on both master and slave sides in order to resynchronize the master
 3524 
 
3525 
           and slave for their respective CRC calculation */
 3525 
  /* Adjust Timeout value  in case of end of transfer */
3526 
 
 3526 
  tmp_timeout   = Timeout - (HAL_GetTick() - Tickstart);
3527 
        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
 3527 
  tmp_tickstart = HAL_GetTick();
3528 
        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
 3528 
 
3529 
 
 3529 
  /* Calculate Timeout based on a software loop to avoid blocking issue if Systick is disabled */
3530 
        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
 3530 
  count = tmp_timeout * ((SystemCoreClock * 32U) >> 20U);
3531 
                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
 3531 
 
3532 
        {
 3532 
  while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) != State)
3533 
          /* Disable SPI peripheral */
 3533 
  {
3534 
          __HAL_SPI_DISABLE(hspi);
 3534 
    if (Timeout != HAL_MAX_DELAY)
3535 
        }
 3535 
    {
3536 
 
 3536 
      if (((HAL_GetTick() - tmp_tickstart) >= tmp_timeout) || (tmp_timeout == 0U))
3537 
        /* Reset CRC Calculation */
 3537 
      {
3538 
        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
 3538 
        /* Disable the SPI and reset the CRC: the CRC value should be cleared
3539 
        {
 3539 
           on both master and slave sides in order to resynchronize the master
3540 
          SPI_RESET_CRC(hspi);
 3540 
           and slave for their respective CRC calculation */
3541 
        }
 3541 
 
3542 
 
 3542 
        /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
3543 
        hspi->State = HAL_SPI_STATE_READY;
 3543 
        __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
3544 
 
 3544 
 
3545 
        /* Process Unlocked */
 3545 
        if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3546 
        __HAL_UNLOCK(hspi);
 3546 
                                                     || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3547 
 
 3547 
        {
3548 
        return HAL_TIMEOUT;
 3548 
          /* Disable SPI peripheral */
3549 
      }
 3549 
          __HAL_SPI_DISABLE(hspi);
3550 
      /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
 3550 
        }
3551 
      if(count == 0U)
 3551 
 
3552 
      {
 3552 
        /* Reset CRC Calculation */
3553 
        tmp_timeout = 0U;
 3553 
        if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)
3554 
      }
 3554 
        {
3555 
      count--;
 3555 
          SPI_RESET_CRC(hspi);
3556 
    }
 3556 
        }
3557 
  }
 3557 
 
3558 
 
 3558 
        hspi->State = HAL_SPI_STATE_READY;
3559 
  return HAL_OK;
 3559 
 
3560 
}
 3560 
        /* Process Unlocked */
3561 
 
 3561 
        __HAL_UNLOCK(hspi);
3562 
/**
 3562 
 
3563 
  * @brief  Handle the check of the RX transaction complete.
 3563 
        return HAL_TIMEOUT;
3564 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3564 
      }
3565 
  *               the configuration information for SPI module.
 3565 
      /* If Systick is disabled or not incremented, deactivate timeout to go in disable loop procedure */
3566 
  * @param  Timeout Timeout duration
 3566 
      if (count == 0U)
3567 
  * @param  Tickstart tick start value
 3567 
      {
3568 
  * @retval HAL status
 3568 
        tmp_timeout = 0U;
3569 
  */
 3569 
      }
3570 
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
 3570 
      count--;
3571 
{
 3571 
    }
3572 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
 3572 
  }
3573 
                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
 3573 
 
3574 
  {
 3574 
  return HAL_OK;
3575 
    /* Disable SPI peripheral */
 3575 
}
3576 
    __HAL_SPI_DISABLE(hspi);
 3576 
 
3577 
  }
 3577 
/**
3578 
 
 3578 
  * @brief  Handle the check of the RX transaction complete.
3579 
  /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
 3579 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3580 
  if (hspi->Init.Mode == SPI_MODE_MASTER)
 3580 
  *               the configuration information for SPI module.
3581 
  {
 3581 
  * @param  Timeout Timeout duration
3582 
    if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY)
 3582 
  * @param  Tickstart tick start value
3583 
    {
 3583 
  * @retval HAL status
3584 
      /* Control the BSY flag */
 3584 
  */
3585 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
 3585 
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi,  uint32_t Timeout, uint32_t Tickstart)
3586 
      {
 3586 
{
3587 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3587 
  if ((hspi->Init.Mode == SPI_MODE_MASTER) && ((hspi->Init.Direction == SPI_DIRECTION_1LINE)
3588 
        return HAL_TIMEOUT;
 3588 
                                               || (hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
3589 
      }
 3589 
  {
3590 
    }
 3590 
    /* Disable SPI peripheral */
3591 
    else
 3591 
    __HAL_SPI_DISABLE(hspi);
3592 
    {
 3592 
  }
3593 
      /* Wait the RXNE reset */
 3593 
 
3594 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
 3594 
  /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
3595 
      {
 3595 
  if (hspi->Init.Mode == SPI_MODE_MASTER)
3596 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3596 
  {
3597 
        return HAL_TIMEOUT;
 3597 
    if (hspi->Init.Direction != SPI_DIRECTION_2LINES_RXONLY)
3598 
      }
 3598 
    {
3599 
    }
 3599 
      /* Control the BSY flag */
3600 
  }
 3600 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3601 
  else
 3601 
      {
3602 
  {
 3602 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3603 
    /* Wait the RXNE reset */
 3603 
        return HAL_TIMEOUT;
3604 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
 3604 
      }
3605 
    {
 3605 
    }
3606 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3606 
    else
3607 
      return HAL_TIMEOUT;
 3607 
    {
3608 
    }
 3608 
      /* Wait the RXNE reset */
3609 
  }
 3609 
      if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
3610 
  return HAL_OK;
 3610 
      {
3611 
}
 3611 
        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3612 
 
 3612 
        return HAL_TIMEOUT;
3613 
/**
 3613 
      }
3614 
  * @brief  Handle the check of the RXTX or TX transaction complete.
 3614 
    }
3615 
  * @param  hspi SPI handle
 3615 
  }
3616 
  * @param  Timeout Timeout duration
 3616 
  else
3617 
  * @param  Tickstart tick start value
 3617 
  {
3618 
  * @retval HAL status
 3618 
    /* Wait the RXNE reset */
3619 
  */
 3619 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout, Tickstart) != HAL_OK)
3620 
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
 3620 
    {
3621 
{
 3621 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3622 
  /* Timeout in µs */
 3622 
      return HAL_TIMEOUT;
3623 
  __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
 3623 
    }
3624 
  /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
 3624 
  }
3625 
  if (hspi->Init.Mode == SPI_MODE_MASTER)
 3625 
  return HAL_OK;
3626 
  {
 3626 
}
3627 
    /* Control the BSY flag */
 3627 
 
3628 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
 3628 
/**
3629 
    {
 3629 
  * @brief  Handle the check of the RXTX or TX transaction complete.
3630 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3630 
  * @param  hspi SPI handle
3631 
      return HAL_TIMEOUT;
 3631 
  * @param  Timeout Timeout duration
3632 
    }
 3632 
  * @param  Tickstart tick start value
3633 
  }
 3633 
  * @retval HAL status
3634 
  else
 3634 
  */
3635 
  {
 3635 
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
3636 
    /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer
 3636 
{
3637 
    * If Timeout is reached, the transfer is considered as finish.
 3637 
  /* Timeout in µs */
3638 
    * User have to calculate the timeout value to fit with the time of 1 byte transfer.
 3638 
  __IO uint32_t count = SPI_BSY_FLAG_WORKAROUND_TIMEOUT * (SystemCoreClock / 24U / 1000000U);
3639 
    * This time is directly link with the SPI clock from Master device.
 3639 
  /* Erratasheet: BSY bit may stay high at the end of a data transfer in Slave mode */
3640 
    */
 3640 
  if (hspi->Init.Mode == SPI_MODE_MASTER)
3641 
    do
 3641 
  {
3642 
    {
 3642 
    /* Control the BSY flag */
3643 
      if (count == 0U)
 3643 
    if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK)
3644 
      {
 3644 
    {
3645 
        break;
 3645 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3646 
      }
 3646 
      return HAL_TIMEOUT;
3647 
      count--;
 3647 
    }
3648 
    } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
 3648 
  }
3649 
  }
 3649 
  else
3650 
 
 3650 
  {
3651 
  return HAL_OK;
 3651 
    /* Wait BSY flag during 1 Byte time transfer in case of Full-Duplex and Tx transfer
3652 
}
 3652 
    * If Timeout is reached, the transfer is considered as finish.
3653 
 
 3653 
    * User have to calculate the timeout value to fit with the time of 1 byte transfer.
3654 
/**
 3654 
    * This time is directly link with the SPI clock from Master device.
3655 
  * @brief  Handle the end of the RXTX transaction.
 3655 
    */
3656 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3656 
    do
3657 
  *               the configuration information for SPI module.
 3657 
    {
3658 
  * @retval None
 3658 
      if (count == 0U)
3659 
  */
 3659 
      {
3660 
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
 3660 
        break;
3661 
{
 3661 
      }
3662 
  uint32_t tickstart;
 3662 
      count--;
3663 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 3663 
    } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_BSY) != RESET);
3664 
 
 3664 
  }
3665 
  /* Init tickstart for timeout management */
 3665 
 
3666 
  tickstart = HAL_GetTick();
 3666 
  return HAL_OK;
3667 
 
 3667 
}
3668 
  /* Disable ERR interrupt */
 3668 
 
3669 
  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
 3669 
/**
3670 
 
 3670 
  * @brief  Handle the end of the RXTX transaction.
3671 
  /* Wait until TXE flag is set */
 3671 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3672 
  do
 3672 
  *               the configuration information for SPI module.
3673 
  {
 3673 
  * @retval None
3674 
    if (count == 0U)
 3674 
  */
3675 
    {
 3675 
static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi)
3676 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3676 
{
3677 
      break;
 3677 
  uint32_t tickstart;
3678 
    }
 3678 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3679 
    count--;
 3679 
 
3680 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
 3680 
  /* Init tickstart for timeout management */
3681 
 
 3681 
  tickstart = HAL_GetTick();
3682 
  /* Check the end of the transaction */
 3682 
 
3683 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 3683 
  /* Disable ERR interrupt */
3684 
  {
 3684 
  __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR);
3685 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3685 
 
3686 
  }
 3686 
  /* Wait until TXE flag is set */
3687 
 
 3687 
  do
3688 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
 3688 
  {
3689 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 3689 
    if (count == 0U)
3690 
  {
 3690 
    {
3691 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 3691 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3692 
  }
 3692 
      break;
3693 
 
 3693 
    }
3694 
#if (USE_SPI_CRC != 0U)
 3694 
    count--;
3695 
  /* Check if CRC error occurred */
 3695 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3696 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
 3696 
 
3697 
  {
 3697 
  /* Check the end of the transaction */
3698 
    hspi->State = HAL_SPI_STATE_READY;
 3698 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3699 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 3699 
  {
3700 
    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 3700 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3701 
    /* Call user error callback */
 3701 
  }
3702 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3702 
 
3703 
    hspi->ErrorCallback(hspi);
 3703 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
3704 
#else
 3704 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3705 
    HAL_SPI_ErrorCallback(hspi);
 3705 
  {
3706 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3706 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
3707 
  }
 3707 
  }
3708 
  else
 3708 
 
3709 
  {
 3709 
#if (USE_SPI_CRC != 0U)
3710 
#endif /* USE_SPI_CRC */
 3710 
  /* Check if CRC error occurred */
3711 
    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
 3711 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3712 
    {
 3712 
  {
3713 
      if (hspi->State == HAL_SPI_STATE_BUSY_RX)
 3713 
    hspi->State = HAL_SPI_STATE_READY;
3714 
      {
 3714 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3715 
        hspi->State = HAL_SPI_STATE_READY;
 3715 
    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3716 
        /* Call user Rx complete callback */
 3716 
    /* Call user error callback */
3717 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3717 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3718 
        hspi->RxCpltCallback(hspi);
 3718 
    hspi->ErrorCallback(hspi);
3719 
#else
 3719 
#else
3720 
        HAL_SPI_RxCpltCallback(hspi);
 3720 
    HAL_SPI_ErrorCallback(hspi);
3721 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3721 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3722 
      }
 3722 
  }
3723 
      else
 3723 
  else
3724 
      {
 3724 
  {
3725 
        hspi->State = HAL_SPI_STATE_READY;
 3725 
#endif /* USE_SPI_CRC */
3726 
        /* Call user TxRx complete callback */
 3726 
    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3727 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3727 
    {
3728 
        hspi->TxRxCpltCallback(hspi);
 3728 
      if (hspi->State == HAL_SPI_STATE_BUSY_RX)
3729 
#else
 3729 
      {
3730 
        HAL_SPI_TxRxCpltCallback(hspi);
 3730 
        hspi->State = HAL_SPI_STATE_READY;
3731 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3731 
        /* Call user Rx complete callback */
3732 
      }
 3732 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3733 
    }
 3733 
        hspi->RxCpltCallback(hspi);
3734 
    else
 3734 
#else
3735 
    {
 3735 
        HAL_SPI_RxCpltCallback(hspi);
3736 
      hspi->State = HAL_SPI_STATE_READY;
 3736 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3737 
      /* Call user error callback */
 3737 
      }
3738 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3738 
      else
3739 
      hspi->ErrorCallback(hspi);
 3739 
      {
3740 
#else
 3740 
        hspi->State = HAL_SPI_STATE_READY;
3741 
      HAL_SPI_ErrorCallback(hspi);
 3741 
        /* Call user TxRx complete callback */
3742 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3742 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3743 
    }
 3743 
        hspi->TxRxCpltCallback(hspi);
3744 
#if (USE_SPI_CRC != 0U)
 3744 
#else
3745 
  }
 3745 
        HAL_SPI_TxRxCpltCallback(hspi);
3746 
#endif /* USE_SPI_CRC */
 3746 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3747 
}
 3747 
      }
3748 
 
 3748 
    }
3749 
/**
 3749 
    else
3750 
  * @brief  Handle the end of the RX transaction.
 3750 
    {
3751 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3751 
      hspi->State = HAL_SPI_STATE_READY;
3752 
  *               the configuration information for SPI module.
 3752 
      /* Call user error callback */
3753 
  * @retval None
 3753 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3754 
  */
 3754 
      hspi->ErrorCallback(hspi);
3755 
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
 3755 
#else
3756 
{
 3756 
      HAL_SPI_ErrorCallback(hspi);
3757 
  /* Disable RXNE and ERR interrupt */
 3757 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3758 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
 3758 
    }
3759 
 
 3759 
#if (USE_SPI_CRC != 0U)
3760 
  /* Check the end of the transaction */
 3760 
  }
3761 
  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
 3761 
#endif /* USE_SPI_CRC */
3762 
  {
 3762 
}
3763 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3763 
 
3764 
  }
 3764 
/**
3765 
 
 3765 
  * @brief  Handle the end of the RX transaction.
3766 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
 3766 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3767 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 3767 
  *               the configuration information for SPI module.
3768 
  {
 3768 
  * @retval None
3769 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 3769 
  */
3770 
  }
 3770 
static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi)
3771 
  hspi->State = HAL_SPI_STATE_READY;
 3771 
{
3772 
 
 3772 
  /* Disable RXNE and ERR interrupt */
3773 
#if (USE_SPI_CRC != 0U)
 3773 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
3774 
  /* Check if CRC error occurred */
 3774 
 
3775 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
 3775 
  /* Check the end of the transaction */
3776 
  {
 3776 
  if (SPI_EndRxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
3777 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
 3777 
  {
3778 
    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
 3778 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3779 
    /* Call user error callback */
 3779 
  }
3780 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3780 
 
3781 
    hspi->ErrorCallback(hspi);
 3781 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
3782 
#else
 3782 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3783 
    HAL_SPI_ErrorCallback(hspi);
 3783 
  {
3784 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3784 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
3785 
  }
 3785 
  }
3786 
  else
 3786 
  hspi->State = HAL_SPI_STATE_READY;
3787 
  {
 3787 
 
3788 
#endif /* USE_SPI_CRC */
 3788 
#if (USE_SPI_CRC != 0U)
3789 
    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
 3789 
  /* Check if CRC error occurred */
3790 
    {
 3790 
  if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
3791 
      /* Call user Rx complete callback */
 3791 
  {
3792 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3792 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
3793 
      hspi->RxCpltCallback(hspi);
 3793 
    __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
3794 
#else
 3794 
    /* Call user error callback */
3795 
      HAL_SPI_RxCpltCallback(hspi);
 3795 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3796 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3796 
    hspi->ErrorCallback(hspi);
3797 
    }
 3797 
#else
3798 
    else
 3798 
    HAL_SPI_ErrorCallback(hspi);
3799 
    {
 3799 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3800 
      /* Call user error callback */
 3800 
  }
3801 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3801 
  else
3802 
      hspi->ErrorCallback(hspi);
 3802 
  {
3803 
#else
 3803 
#endif /* USE_SPI_CRC */
3804 
      HAL_SPI_ErrorCallback(hspi);
 3804 
    if (hspi->ErrorCode == HAL_SPI_ERROR_NONE)
3805 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3805 
    {
3806 
    }
 3806 
      /* Call user Rx complete callback */
3807 
#if (USE_SPI_CRC != 0U)
 3807 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3808 
  }
 3808 
      hspi->RxCpltCallback(hspi);
3809 
#endif /* USE_SPI_CRC */
 3809 
#else
3810 
}
 3810 
      HAL_SPI_RxCpltCallback(hspi);
3811 
 
 3811 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3812 
/**
 3812 
    }
3813 
  * @brief  Handle the end of the TX transaction.
 3813 
    else
3814 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3814 
    {
3815 
  *               the configuration information for SPI module.
 3815 
      /* Call user error callback */
3816 
  * @retval None
 3816 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3817 
  */
 3817 
      hspi->ErrorCallback(hspi);
3818 
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
 3818 
#else
3819 
{
 3819 
      HAL_SPI_ErrorCallback(hspi);
3820 
  uint32_t tickstart;
 3820 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3821 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 3821 
    }
3822 
 
 3822 
#if (USE_SPI_CRC != 0U)
3823 
  /* Init tickstart for timeout management*/
 3823 
  }
3824 
  tickstart = HAL_GetTick();
 3824 
#endif /* USE_SPI_CRC */
3825 
 
 3825 
}
3826 
  /* Wait until TXE flag is set */
 3826 
 
3827 
  do
 3827 
/**
3828 
  {
 3828 
  * @brief  Handle the end of the TX transaction.
3829 
    if (count == 0U)
 3829 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3830 
    {
 3830 
  *               the configuration information for SPI module.
3831 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3831 
  * @retval None
3832 
      break;
 3832 
  */
3833 
    }
 3833 
static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi)
3834 
    count--;
 3834 
{
3835 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
 3835 
  uint32_t tickstart;
3836 
 
 3836 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3837 
  /* Disable TXE and ERR interrupt */
 3837 
 
3838 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
 3838 
  /* Init tickstart for timeout management*/
3839 
 
 3839 
  tickstart = HAL_GetTick();
3840 
  /* Check the end of the transaction */
 3840 
 
3841 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
 3841 
  /* Wait until TXE flag is set */
3842 
  {
 3842 
  do
3843 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
 3843 
  {
3844 
  }
 3844 
    if (count == 0U)
3845 
 
 3845 
    {
3846 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
 3846 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3847 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
 3847 
      break;
3848 
  {
 3848 
    }
3849 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
 3849 
    count--;
3850 
  }
 3850 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3851 
 
 3851 
 
3852 
  hspi->State = HAL_SPI_STATE_READY;
 3852 
  /* Disable TXE and ERR interrupt */
3853 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
 3853 
  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
3854 
  {
 3854 
 
3855 
    /* Call user error callback */
 3855 
  /* Check the end of the transaction */
3856 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3856 
  if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK)
3857 
    hspi->ErrorCallback(hspi);
 3857 
  {
3858 
#else
 3858 
    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
3859 
    HAL_SPI_ErrorCallback(hspi);
 3859 
  }
3860 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3860 
 
3861 
  }
 3861 
  /* Clear overrun flag in 2 Lines communication mode because received is not read */
3862 
  else
 3862 
  if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
3863 
  {
 3863 
  {
3864 
    /* Call user Rx complete callback */
 3864 
    __HAL_SPI_CLEAR_OVRFLAG(hspi);
3865 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
 3865 
  }
3866 
    hspi->TxCpltCallback(hspi);
 3866 
 
3867 
#else
 3867 
  hspi->State = HAL_SPI_STATE_READY;
3868 
    HAL_SPI_TxCpltCallback(hspi);
 3868 
  if (hspi->ErrorCode != HAL_SPI_ERROR_NONE)
3869 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
 3869 
  {
3870 
  }
 3870 
    /* Call user error callback */
3871 
}
 3871 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3872 
 
 3872 
    hspi->ErrorCallback(hspi);
3873 
/**
 3873 
#else
3874 
  * @brief  Handle abort a Rx transaction.
 3874 
    HAL_SPI_ErrorCallback(hspi);
3875 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3875 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3876 
  *               the configuration information for SPI module.
 3876 
  }
3877 
  * @retval None
 3877 
  else
3878 
  */
 3878 
  {
3879 
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
 3879 
    /* Call user Rx complete callback */
3880 
{
 3880 
#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)
3881 
  __IO uint32_t tmpreg = 0U;
 3881 
    hspi->TxCpltCallback(hspi);
3882 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
 3882 
#else
3883 
 
 3883 
    HAL_SPI_TxCpltCallback(hspi);
3884 
  /* Wait until TXE flag is set */
 3884 
#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
3885 
  do
 3885 
  }
3886 
  {
 3886 
}
3887 
    if (count == 0U)
 3887 
 
3888 
    {
 3888 
/**
3889 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
 3889 
  * @brief  Handle abort a Rx transaction.
3890 
      break;
 3890 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3891 
    }
 3891 
  *               the configuration information for SPI module.
3892 
    count--;
 3892 
  * @retval None
3893 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
 3893 
  */
3894 
 
 3894 
static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
3895 
  /* Disable SPI Peripheral */
 3895 
{
3896 
  __HAL_SPI_DISABLE(hspi);
 3896 
  __IO uint32_t tmpreg = 0U;
3897 
 
 3897 
  __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24U / 1000U);
3898 
  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
 3898 
 
3899 
  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
 3899 
  /* Wait until TXE flag is set */
3900 
 
 3900 
  do
3901 
  /* Flush Data Register by a blank read */
 3901 
  {
3902 
  tmpreg = READ_REG(hspi->Instance->DR);
 3902 
    if (count == 0U)
3903 
  /* To avoid GCC warning */
 3903 
    {
3904 
  UNUSED(tmpreg);
 3904 
      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT);
3905 
 
 3905 
      break;
3906 
  hspi->State = HAL_SPI_STATE_ABORT;
 3906 
    }
3907 
}
 3907 
    count--;
3908 
 
 3908 
  } while ((hspi->Instance->SR & SPI_FLAG_TXE) == RESET);
3909 
/**
 3909 
 
3910 
  * @brief  Handle abort a Tx or Rx/Tx transaction.
 3910 
  /* Disable SPI Peripheral */
3911 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
 3911 
  __HAL_SPI_DISABLE(hspi);
3912 
  *               the configuration information for SPI module.
 3912 
 
3913 
  * @retval None
 3913 
  /* Disable TXEIE, RXNEIE and ERRIE(mode fault event, overrun error, TI frame error) interrupts */
3914 
  */
 3914 
  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE | SPI_CR2_RXNEIE | SPI_CR2_ERRIE));
3915 
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
 3915 
 
3916 
{
 3916 
  /* Flush Data Register by a blank read */
3917 
  /* Disable TXEIE interrupt */
 3917 
  tmpreg = READ_REG(hspi->Instance->DR);
3918 
  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
 3918 
  /* To avoid GCC warning */
3919 
 
 3919 
  UNUSED(tmpreg);
3920 
  /* Disable SPI Peripheral */
 3920 
 
3921 
  __HAL_SPI_DISABLE(hspi);
 3921 
  hspi->State = HAL_SPI_STATE_ABORT;
3922 
 
 3922 
}
3923 
  hspi->State = HAL_SPI_STATE_ABORT;
 3923 
 
3924 
}
 3924 
/**
3925 
 
 3925 
  * @brief  Handle abort a Tx or Rx/Tx transaction.
3926 
/**
 3926 
  * @param  hspi pointer to a SPI_HandleTypeDef structure that contains
3927 
  * @}
 3927 
  *               the configuration information for SPI module.
3928 
  */
 3928 
  * @retval None
3929 
 
 3929 
  */
3930 
#endif /* HAL_SPI_MODULE_ENABLED */
 3930 
static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
3931 
 
 3931 
{
3932 
/**
 3932 
  /* Disable TXEIE interrupt */
3933 
  * @}
 3933 
  CLEAR_BIT(hspi->Instance->CR2, (SPI_CR2_TXEIE));
3934 
  */
 3934 
 
3935 
 
 3935 
  /* Disable SPI Peripheral */
3936 
/**
 3936 
  __HAL_SPI_DISABLE(hspi);
3937 
  * @}
 3937 
 
3938 
  */
 3938 
  hspi->State = HAL_SPI_STATE_ABORT;
3939 
 
 3939 
}
3940 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 3940 
 
- 
 
 3941 
/**
- 
 
 3942 
  * @}
- 
 
 3943 
  */
- 
 
 3944 
 
- 
 
 3945 
#endif /* HAL_SPI_MODULE_ENABLED */
- 
 
 3946 
 
- 
 
 3947 
/**
- 
 
 3948 
  * @}
- 
 
 3949 
  */
- 
 
 3950 
 
- 
 
 3951 
/**
- 
 
 3952 
  * @}
- 
 
 3953 
  */
- 
 
 3954