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1 | /** |
1 | /** |
2 | ****************************************************************************** |
2 | ****************************************************************************** |
3 | * @file stm32l1xx_hal_rcc_ex.c |
3 | * @file stm32l1xx_hal_rcc_ex.c |
4 | * @author MCD Application Team |
4 | * @author MCD Application Team |
5 | * @brief Extended RCC HAL module driver. |
5 | * @brief Extended RCC HAL module driver. |
6 | * This file provides firmware functions to manage the following |
6 | * This file provides firmware functions to manage the following |
7 | * functionalities RCC extension peripheral: |
7 | * functionalities RCC extension peripheral: |
8 | * + Extended Peripheral Control functions |
8 | * + Extended Peripheral Control functions |
9 | * |
9 | * |
10 | ****************************************************************************** |
10 | ****************************************************************************** |
11 | * @attention |
11 | * @attention |
12 | * |
12 | * |
13 | * <h2><center>© Copyright(c) 2017 STMicroelectronics. |
13 | * Copyright (c) 2017 STMicroelectronics. |
14 | * All rights reserved.</center></h2> |
14 | * All rights reserved. |
15 | * |
15 | * |
16 | * This software component is licensed by ST under BSD 3-Clause license, |
16 | * This software is licensed under terms that can be found in the LICENSE file in |
17 | * the "License"; You may not use this file except in compliance with the |
17 | * the root directory of this software component. |
18 | * License. You may obtain a copy of the License at: |
18 | * If no LICENSE file comes with this software, it is provided AS-IS. |
19 | * opensource.org/licenses/BSD-3-Clause |
19 | ****************************************************************************** |
20 | * |
20 | */ |
21 | ****************************************************************************** |
21 | |
22 | */ |
22 | /* Includes ------------------------------------------------------------------*/ |
23 | 23 | #include "stm32l1xx_hal.h" |
|
24 | /* Includes ------------------------------------------------------------------*/ |
24 | |
25 | #include "stm32l1xx_hal.h" |
25 | /** @addtogroup STM32L1xx_HAL_Driver |
26 | 26 | * @{ |
|
27 | /** @addtogroup STM32L1xx_HAL_Driver |
27 | */ |
28 | * @{ |
28 | |
29 | */ |
29 | #ifdef HAL_RCC_MODULE_ENABLED |
30 | 30 | ||
31 | #ifdef HAL_RCC_MODULE_ENABLED |
31 | /** @defgroup RCCEx RCCEx |
32 | 32 | * @brief RCC Extension HAL module driver |
|
33 | /** @defgroup RCCEx RCCEx |
33 | * @{ |
34 | * @brief RCC Extension HAL module driver |
34 | */ |
35 | * @{ |
35 | |
36 | */ |
36 | /* Private typedef -----------------------------------------------------------*/ |
37 | 37 | /* Private define ------------------------------------------------------------*/ |
|
38 | /* Private typedef -----------------------------------------------------------*/ |
38 | /** @defgroup RCCEx_Private_Constants RCCEx Private Constants |
39 | /* Private define ------------------------------------------------------------*/ |
39 | * @{ |
40 | /** @defgroup RCCEx_Private_Constants RCCEx Private Constants |
40 | */ |
41 | * @{ |
41 | /** |
42 | */ |
42 | * @} |
43 | /** |
43 | */ |
44 | * @} |
44 | |
45 | */ |
45 | /* Private macro -------------------------------------------------------------*/ |
46 | 46 | /** @defgroup RCCEx_Private_Macros RCCEx Private Macros |
|
47 | /* Private macro -------------------------------------------------------------*/ |
47 | * @{ |
48 | /** @defgroup RCCEx_Private_Macros RCCEx Private Macros |
48 | */ |
49 | * @{ |
49 | /** |
50 | */ |
50 | * @} |
51 | /** |
51 | */ |
52 | * @} |
52 | |
53 | */ |
53 | /* Private variables ---------------------------------------------------------*/ |
54 | 54 | /* Private function prototypes -----------------------------------------------*/ |
|
55 | /* Private variables ---------------------------------------------------------*/ |
55 | /* Private functions ---------------------------------------------------------*/ |
56 | /* Private function prototypes -----------------------------------------------*/ |
56 | |
57 | /* Private functions ---------------------------------------------------------*/ |
57 | /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions |
58 | 58 | * @{ |
|
59 | /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions |
59 | */ |
60 | * @{ |
60 | |
61 | */ |
61 | /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions |
62 | 62 | * @brief Extended Peripheral Control functions |
|
63 | /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions |
63 | * |
64 | * @brief Extended Peripheral Control functions |
64 | @verbatim |
65 | * |
65 | =============================================================================== |
66 | @verbatim |
66 | ##### Extended Peripheral Control functions ##### |
67 | =============================================================================== |
67 | =============================================================================== |
68 | ##### Extended Peripheral Control functions ##### |
68 | [..] |
69 | =============================================================================== |
69 | This subsection provides a set of functions allowing to control the RCC Clocks |
70 | [..] |
70 | frequencies. |
71 | This subsection provides a set of functions allowing to control the RCC Clocks |
71 | [..] |
72 | frequencies. |
72 | (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to |
73 | [..] |
73 | select the RTC clock source; in this case the Backup domain will be reset in |
74 | (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to |
74 | order to modify the RTC Clock source, as consequence RTC registers (including |
75 | select the RTC clock source; in this case the Backup domain will be reset in |
75 | the backup registers) are set to their reset values. |
76 | order to modify the RTC Clock source, as consequence RTC registers (including |
76 | |
77 | the backup registers) are set to their reset values. |
77 | @endverbatim |
78 | 78 | * @{ |
|
79 | @endverbatim |
79 | */ |
80 | * @{ |
80 | |
81 | */ |
81 | /** |
82 | 82 | * @brief Initializes the RCC extended peripherals clocks according to the specified |
|
83 | /** |
83 | * parameters in the RCC_PeriphCLKInitTypeDef. |
84 | * @brief Initializes the RCC extended peripherals clocks according to the specified |
84 | * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that |
85 | * parameters in the RCC_PeriphCLKInitTypeDef. |
85 | * contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock). |
86 | * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that |
86 | * @retval HAL status |
87 | * contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock). |
87 | * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig() |
88 | * @retval HAL status |
88 | * to possibly update HSE divider. |
89 | * @note If HAL_ERROR returned, first switch-OFF HSE clock oscillator with @ref HAL_RCC_OscConfig() |
89 | */ |
90 | * to possibly update HSE divider. |
90 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
91 | */ |
91 | { |
92 | HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
92 | uint32_t tickstart; |
93 | { |
93 | uint32_t temp_reg; |
94 | uint32_t tickstart; |
94 | |
95 | uint32_t temp_reg; |
95 | /* Check the parameters */ |
96 | 96 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
|
97 | /* Check the parameters */ |
97 | |
98 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); |
98 | /*------------------------------- RTC/LCD Configuration ------------------------*/ |
99 | 99 | if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) |
|
100 | /*------------------------------- RTC/LCD Configuration ------------------------*/ |
100 | #if defined(LCD) |
101 | if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) |
101 | || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) |
102 | #if defined(LCD) |
102 | #endif /* LCD */ |
103 | || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) |
103 | ) |
104 | #endif /* LCD */ |
104 | { |
105 | ) |
105 | /* check for RTC Parameters used to output RTCCLK */ |
106 | { |
106 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) |
107 | /* check for RTC Parameters used to output RTCCLK */ |
107 | { |
108 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) |
108 | assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); |
109 | { |
109 | } |
110 | assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); |
110 | |
111 | } |
111 | #if defined(LCD) |
112 | 112 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) |
|
113 | #if defined(LCD) |
113 | { |
114 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) |
114 | assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection)); |
115 | { |
115 | } |
116 | assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->LCDClockSelection)); |
116 | #endif /* LCD */ |
117 | } |
117 | |
118 | #endif /* LCD */ |
118 | FlagStatus pwrclkchanged = RESET; |
119 | 119 | ||
120 | FlagStatus pwrclkchanged = RESET; |
120 | /* As soon as function is called to change RTC clock source, activation of the |
121 | 121 | power domain is done. */ |
|
122 | /* As soon as function is called to change RTC clock source, activation of the |
122 | /* Requires to enable write access to Backup Domain of necessary */ |
123 | power domain is done. */ |
123 | if(__HAL_RCC_PWR_IS_CLK_DISABLED()) |
124 | /* Requires to enable write access to Backup Domain of necessary */ |
124 | { |
125 | if(__HAL_RCC_PWR_IS_CLK_DISABLED()) |
125 | __HAL_RCC_PWR_CLK_ENABLE(); |
126 | { |
126 | pwrclkchanged = SET; |
127 | __HAL_RCC_PWR_CLK_ENABLE(); |
127 | } |
128 | pwrclkchanged = SET; |
128 | |
129 | } |
129 | if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) |
130 | 130 | { |
|
131 | if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) |
131 | /* Enable write access to Backup domain */ |
132 | { |
132 | SET_BIT(PWR->CR, PWR_CR_DBP); |
133 | /* Enable write access to Backup domain */ |
133 | |
134 | SET_BIT(PWR->CR, PWR_CR_DBP); |
134 | /* Wait for Backup domain Write protection disable */ |
135 | 135 | tickstart = HAL_GetTick(); |
|
136 | /* Wait for Backup domain Write protection disable */ |
136 | |
137 | tickstart = HAL_GetTick(); |
137 | while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) |
138 | 138 | { |
|
139 | while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP)) |
139 | if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) |
140 | { |
140 | { |
141 | if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) |
141 | return HAL_TIMEOUT; |
142 | { |
142 | } |
143 | return HAL_TIMEOUT; |
143 | } |
144 | } |
144 | } |
145 | } |
145 | |
146 | } |
146 | /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */ |
147 | 147 | temp_reg = (RCC->CR & RCC_CR_RTCPRE); |
|
148 | /* Check if user wants to change HSE RTC prescaler whereas HSE is enabled */ |
148 | if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) |
149 | temp_reg = (RCC->CR & RCC_CR_RTCPRE); |
149 | #if defined (LCD) |
150 | if ((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CR_RTCPRE)) |
150 | || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE)) |
151 | #if defined (LCD) |
151 | #endif /* LCD */ |
152 | || (temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CR_RTCPRE)) |
152 | ) |
153 | #endif /* LCD */ |
153 | { /* Check HSE State */ |
154 | ) |
154 | if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) |
155 | { /* Check HSE State */ |
155 | { |
156 | if ((PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL) == RCC_CSR_RTCSEL_HSE) |
156 | if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) |
157 | { |
157 | { |
158 | if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) |
158 | /* To update HSE divider, first switch-OFF HSE clock oscillator*/ |
159 | { |
159 | return HAL_ERROR; |
160 | /* To update HSE divider, first switch-OFF HSE clock oscillator*/ |
160 | } |
161 | return HAL_ERROR; |
161 | } |
162 | } |
162 | } |
163 | } |
163 | |
164 | } |
164 | /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ |
165 | 165 | temp_reg = (RCC->CSR & RCC_CSR_RTCSEL); |
|
166 | /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */ |
166 | |
167 | temp_reg = (RCC->CSR & RCC_CSR_RTCSEL); |
167 | if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \ |
168 | 168 | && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
|
169 | if((temp_reg != 0x00000000U) && (((temp_reg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL)) \ |
169 | #if defined(LCD) |
170 | && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)) |
170 | || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \ |
171 | #if defined(LCD) |
171 | && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)) |
172 | || ((temp_reg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL)) \ |
172 | #endif /* LCD */ |
173 | && (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)) |
173 | )) |
174 | #endif /* LCD */ |
174 | { |
175 | )) |
175 | /* Store the content of CSR register before the reset of Backup Domain */ |
176 | { |
176 | temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); |
177 | /* Store the content of CSR register before the reset of Backup Domain */ |
177 | |
178 | temp_reg = (RCC->CSR & ~(RCC_CSR_RTCSEL)); |
178 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
179 | 179 | __HAL_RCC_BACKUPRESET_FORCE(); |
|
180 | /* RTC Clock selection can be changed only if the Backup Domain is reset */ |
180 | __HAL_RCC_BACKUPRESET_RELEASE(); |
181 | __HAL_RCC_BACKUPRESET_FORCE(); |
181 | |
182 | __HAL_RCC_BACKUPRESET_RELEASE(); |
182 | /* Restore the Content of CSR register */ |
183 | 183 | RCC->CSR = temp_reg; |
|
184 | /* Restore the Content of CSR register */ |
184 | |
185 | RCC->CSR = temp_reg; |
185 | /* Wait for LSERDY if LSE was enabled */ |
186 | 186 | if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON)) |
|
187 | /* Wait for LSERDY if LSE was enabled */ |
187 | { |
188 | if (HAL_IS_BIT_SET(temp_reg, RCC_CSR_LSEON)) |
188 | /* Get Start Tick */ |
189 | { |
189 | tickstart = HAL_GetTick(); |
190 | /* Get Start Tick */ |
190 | |
191 | tickstart = HAL_GetTick(); |
191 | /* Wait till LSE is ready */ |
192 | 192 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) |
|
193 | /* Wait till LSE is ready */ |
193 | { |
194 | while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == 0U) |
194 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
195 | { |
195 | { |
196 | if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE) |
196 | return HAL_TIMEOUT; |
197 | { |
197 | } |
198 | return HAL_TIMEOUT; |
198 | } |
199 | } |
199 | } |
200 | } |
200 | } |
201 | } |
201 | #if defined(LCD) |
202 | } |
202 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) |
203 | #if defined(LCD) |
203 | { |
204 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD) |
204 | __HAL_RCC_LCD_CONFIG(PeriphClkInit->LCDClockSelection); |
205 | { |
205 | } |
206 | __HAL_RCC_LCD_CONFIG(PeriphClkInit->LCDClockSelection); |
206 | #endif /* LCD */ |
207 | } |
207 | |
208 | #endif /* LCD */ |
208 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) |
209 | 209 | { |
|
210 | if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) |
210 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
211 | { |
211 | } |
212 | __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); |
212 | |
213 | } |
213 | /* Require to disable power clock if necessary */ |
214 | 214 | if(pwrclkchanged == SET) |
|
215 | /* Require to disable power clock if necessary */ |
215 | { |
216 | if(pwrclkchanged == SET) |
216 | __HAL_RCC_PWR_CLK_DISABLE(); |
217 | { |
217 | } |
218 | __HAL_RCC_PWR_CLK_DISABLE(); |
218 | } |
219 | } |
219 | |
220 | } |
220 | return HAL_OK; |
221 | 221 | } |
|
222 | return HAL_OK; |
222 | |
223 | } |
223 | /** |
224 | 224 | * @brief Get the PeriphClkInit according to the internal RCC configuration registers. |
|
225 | /** |
225 | * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that |
226 | * @brief Get the PeriphClkInit according to the internal RCC configuration registers. |
226 | * returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks). |
227 | * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that |
227 | * @retval None |
228 | * returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks). |
228 | */ |
229 | * @retval None |
229 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
230 | */ |
230 | { |
231 | void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) |
231 | uint32_t srcclk; |
232 | { |
232 | |
233 | uint32_t srcclk; |
233 | /* Set all possible values for the extended clock type parameter------------*/ |
234 | 234 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; |
|
235 | /* Set all possible values for the extended clock type parameter------------*/ |
235 | #if defined(LCD) |
236 | PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC; |
236 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD; |
237 | #if defined(LCD) |
237 | #endif /* LCD */ |
238 | PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD; |
238 | |
239 | #endif /* LCD */ |
239 | /* Get the RTC/LCD configuration -----------------------------------------------*/ |
240 | 240 | srcclk = __HAL_RCC_GET_RTC_SOURCE(); |
|
241 | /* Get the RTC/LCD configuration -----------------------------------------------*/ |
241 | if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2) |
242 | srcclk = __HAL_RCC_GET_RTC_SOURCE(); |
242 | { |
243 | if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2) |
243 | /* Source clock is LSE or LSI*/ |
244 | { |
244 | PeriphClkInit->RTCClockSelection = srcclk; |
245 | /* Source clock is LSE or LSI*/ |
245 | } |
246 | PeriphClkInit->RTCClockSelection = srcclk; |
246 | else |
247 | } |
247 | { |
248 | else |
248 | /* Source clock is HSE. Need to get the prescaler value*/ |
249 | { |
249 | PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE)); |
250 | /* Source clock is HSE. Need to get the prescaler value*/ |
250 | } |
251 | PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE)); |
251 | #if defined(LCD) |
252 | } |
252 | PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection; |
253 | #if defined(LCD) |
253 | #endif /* LCD */ |
254 | PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection; |
254 | } |
255 | #endif /* LCD */ |
255 | |
256 | } |
256 | /** |
257 | 257 | * @brief Return the peripheral clock frequency |
|
258 | /** |
258 | * @note Return 0 if peripheral clock is unknown |
259 | * @brief Return the peripheral clock frequency |
259 | * @param PeriphClk Peripheral clock identifier |
260 | * @note Return 0 if peripheral clock is unknown |
260 | * This parameter can be one of the following values: |
261 | * @param PeriphClk Peripheral clock identifier |
261 | * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock |
262 | * This parameter can be one of the following values: |
262 | * @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (*) |
263 | * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock |
263 | * @note (*) means that this peripheral is not present on all the devices |
264 | * @arg @ref RCC_PERIPHCLK_LCD LCD peripheral clock (*) |
264 | * @retval Frequency in Hz (0: means that no available frequency for the peripheral) |
265 | * @note (*) means that this peripheral is not present on all the devices |
265 | */ |
266 | * @retval Frequency in Hz (0: means that no available frequency for the peripheral) |
266 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) |
267 | */ |
267 | { |
268 | uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) |
268 | uint32_t frequency = 0; |
269 | { |
269 | uint32_t srcclk; |
270 | uint32_t frequency = 0; |
270 | |
271 | uint32_t srcclk; |
271 | /* Check the parameters */ |
272 | 272 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); |
|
273 | /* Check the parameters */ |
273 | |
274 | assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); |
274 | switch (PeriphClk) |
275 | 275 | { |
|
276 | switch (PeriphClk) |
276 | case RCC_PERIPHCLK_RTC: |
277 | { |
277 | #if defined(LCD) |
278 | case RCC_PERIPHCLK_RTC: |
278 | case RCC_PERIPHCLK_LCD: |
279 | #if defined(LCD) |
279 | #endif /* LCD */ |
280 | case RCC_PERIPHCLK_LCD: |
280 | { |
281 | #endif /* LCD */ |
281 | /* Get the current RTC source */ |
282 | { |
282 | srcclk = __HAL_RCC_GET_RTC_SOURCE(); |
283 | /* Get the current RTC source */ |
283 | |
284 | srcclk = __HAL_RCC_GET_RTC_SOURCE(); |
284 | /* Check if LSE is ready if RTC clock selection is LSE */ |
285 | 285 | if (srcclk == RCC_RTCCLKSOURCE_LSE) |
|
286 | /* Check if LSE is ready if RTC clock selection is LSE */ |
286 | { |
287 | if (srcclk == RCC_RTCCLKSOURCE_LSE) |
287 | if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)) |
288 | { |
288 | { |
289 | if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSERDY)) |
289 | frequency = LSE_VALUE; |
290 | { |
290 | } |
291 | frequency = LSE_VALUE; |
291 | } |
292 | } |
292 | /* Check if LSI is ready if RTC clock selection is LSI */ |
293 | } |
293 | else if (srcclk == RCC_RTCCLKSOURCE_LSI) |
294 | /* Check if LSI is ready if RTC clock selection is LSI */ |
294 | { |
295 | else if (srcclk == RCC_RTCCLKSOURCE_LSI) |
295 | if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) |
296 | { |
296 | { |
297 | if (HAL_IS_BIT_SET(RCC->CSR, RCC_CSR_LSIRDY)) |
297 | frequency = LSI_VALUE; |
298 | { |
298 | } |
299 | frequency = LSI_VALUE; |
299 | } |
300 | } |
300 | /* Check if HSE is ready and if RTC clock selection is HSE */ |
301 | } |
301 | else if (srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) |
302 | /* Check if HSE is ready and if RTC clock selection is HSE */ |
302 | { |
303 | else if (srcclk == RCC_RTCCLKSOURCE_HSE_DIVX) |
303 | if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) |
304 | { |
304 | { |
305 | if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) |
305 | /* Get the current HSE clock divider */ |
306 | { |
306 | switch (__HAL_RCC_GET_RTC_HSE_PRESCALER()) |
307 | /* Get the current HSE clock divider */ |
307 | { |
308 | switch (__HAL_RCC_GET_RTC_HSE_PRESCALER()) |
308 | case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */ |
309 | { |
309 | { |
310 | case RCC_RTC_HSE_DIV_16: /* HSE DIV16 has been selected */ |
310 | frequency = HSE_VALUE / 16U; |
311 | { |
311 | break; |
312 | frequency = HSE_VALUE / 16U; |
312 | } |
313 | break; |
313 | case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */ |
314 | } |
314 | { |
315 | case RCC_RTC_HSE_DIV_8: /* HSE DIV8 has been selected */ |
315 | frequency = HSE_VALUE / 8U; |
316 | { |
316 | break; |
317 | frequency = HSE_VALUE / 8U; |
317 | } |
318 | break; |
318 | case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */ |
319 | } |
319 | { |
320 | case RCC_RTC_HSE_DIV_4: /* HSE DIV4 has been selected */ |
320 | frequency = HSE_VALUE / 4U; |
321 | { |
321 | break; |
322 | frequency = HSE_VALUE / 4U; |
322 | } |
323 | break; |
323 | default: /* HSE DIV2 has been selected */ |
324 | } |
324 | { |
325 | default: /* HSE DIV2 has been selected */ |
325 | frequency = HSE_VALUE / 2U; |
326 | { |
326 | break; |
327 | frequency = HSE_VALUE / 2U; |
327 | } |
328 | break; |
328 | } |
329 | } |
329 | } |
330 | } |
330 | } |
331 | } |
331 | else |
332 | } |
332 | { |
333 | else |
333 | /* No clock source, frequency default init at 0 */ |
334 | { |
334 | } |
335 | /* No clock source, frequency default init at 0 */ |
335 | break; |
336 | } |
336 | } |
337 | break; |
337 | |
338 | } |
338 | default: |
339 | 339 | break; |
|
340 | default: |
340 | } |
341 | break; |
341 | |
342 | } |
342 | return(frequency); |
343 | 343 | } |
|
344 | return(frequency); |
344 | |
345 | } |
345 | #if defined(RCC_LSECSS_SUPPORT) |
346 | 346 | /** |
|
347 | #if defined(RCC_LSECSS_SUPPORT) |
347 | * @brief Enables the LSE Clock Security System. |
348 | /** |
348 | * @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied |
349 | * @brief Enables the LSE Clock Security System. |
349 | * to the RTC but no hardware action is made to the registers. |
350 | * @note If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied |
350 | * In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup |
351 | * to the RTC but no hardware action is made to the registers. |
351 | * the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104). |
352 | * In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup |
352 | * The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator |
353 | * the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104). |
353 | * (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with |
354 | * The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator |
354 | * RTCSEL), or take any required action to secure the application. |
355 | * (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with |
355 | * @note LSE CSS available only for high density and medium+ devices |
356 | * RTCSEL), or take any required action to secure the application. |
356 | * @retval None |
357 | * @note LSE CSS available only for high density and medium+ devices |
357 | */ |
358 | * @retval None |
358 | void HAL_RCCEx_EnableLSECSS(void) |
359 | */ |
359 | { |
360 | void HAL_RCCEx_EnableLSECSS(void) |
360 | *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE; |
361 | { |
361 | } |
362 | *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE; |
362 | |
363 | } |
363 | /** |
364 | 364 | * @brief Disables the LSE Clock Security System. |
|
365 | /** |
365 | * @note Once enabled this bit cannot be disabled, except after an LSE failure detection |
366 | * @brief Disables the LSE Clock Security System. |
366 | * (LSECSSD=1). In that case the software MUST disable the LSECSSON bit. |
367 | * @note Once enabled this bit cannot be disabled, except after an LSE failure detection |
367 | * Reset by power on reset and RTC software reset (RTCRST bit). |
368 | * (LSECSSD=1). In that case the software MUST disable the LSECSSON bit. |
368 | * @note LSE CSS available only for high density and medium+ devices |
369 | * Reset by power on reset and RTC software reset (RTCRST bit). |
369 | * @retval None |
370 | * @note LSE CSS available only for high density and medium+ devices |
370 | */ |
371 | * @retval None |
371 | void HAL_RCCEx_DisableLSECSS(void) |
372 | */ |
372 | { |
373 | void HAL_RCCEx_DisableLSECSS(void) |
373 | /* Disable LSE CSS */ |
374 | { |
374 | *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE; |
375 | /* Disable LSE CSS */ |
375 | |
376 | *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE; |
376 | /* Disable LSE CSS IT */ |
377 | 377 | __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); |
|
378 | /* Disable LSE CSS IT */ |
378 | } |
379 | __HAL_RCC_DISABLE_IT(RCC_IT_LSECSS); |
379 | |
380 | } |
380 | /** |
381 | 381 | * @brief Enable the LSE Clock Security System IT & corresponding EXTI line. |
|
382 | /** |
382 | * @note LSE Clock Security System IT is mapped on RTC EXTI line 19 |
383 | * @brief Enable the LSE Clock Security System IT & corresponding EXTI line. |
383 | * @retval None |
384 | * @note LSE Clock Security System IT is mapped on RTC EXTI line 19 |
384 | */ |
385 | * @retval None |
385 | void HAL_RCCEx_EnableLSECSS_IT(void) |
386 | */ |
386 | { |
387 | void HAL_RCCEx_EnableLSECSS_IT(void) |
387 | /* Enable LSE CSS */ |
388 | { |
388 | *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE; |
389 | /* Enable LSE CSS */ |
389 | |
390 | *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE; |
390 | /* Enable LSE CSS IT */ |
391 | 391 | __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); |
|
392 | /* Enable LSE CSS IT */ |
392 | |
393 | __HAL_RCC_ENABLE_IT(RCC_IT_LSECSS); |
393 | /* Enable IT on EXTI Line 19 */ |
394 | 394 | __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); |
|
395 | /* Enable IT on EXTI Line 19 */ |
395 | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); |
396 | __HAL_RCC_LSECSS_EXTI_ENABLE_IT(); |
396 | } |
397 | __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE(); |
397 | |
398 | } |
398 | /** |
399 | 399 | * @brief Handle the RCC LSE Clock Security System interrupt request. |
|
400 | /** |
400 | * @retval None |
401 | * @brief Handle the RCC LSE Clock Security System interrupt request. |
401 | */ |
402 | * @retval None |
402 | void HAL_RCCEx_LSECSS_IRQHandler(void) |
403 | */ |
403 | { |
404 | void HAL_RCCEx_LSECSS_IRQHandler(void) |
404 | /* Check RCC LSE CSSF flag */ |
405 | { |
405 | if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) |
406 | /* Check RCC LSE CSSF flag */ |
406 | { |
407 | if(__HAL_RCC_GET_IT(RCC_IT_LSECSS)) |
407 | /* RCC LSE Clock Security System interrupt user callback */ |
408 | { |
408 | HAL_RCCEx_LSECSS_Callback(); |
409 | /* RCC LSE Clock Security System interrupt user callback */ |
409 | |
410 | HAL_RCCEx_LSECSS_Callback(); |
410 | /* Clear RCC LSE CSS pending bit */ |
411 | 411 | __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); |
|
412 | /* Clear RCC LSE CSS pending bit */ |
412 | } |
413 | __HAL_RCC_CLEAR_IT(RCC_IT_LSECSS); |
413 | } |
414 | } |
414 | |
415 | } |
415 | /** |
416 | 416 | * @brief RCCEx LSE Clock Security System interrupt callback. |
|
417 | /** |
417 | * @retval none |
418 | * @brief RCCEx LSE Clock Security System interrupt callback. |
418 | */ |
419 | * @retval none |
419 | __weak void HAL_RCCEx_LSECSS_Callback(void) |
420 | */ |
420 | { |
421 | __weak void HAL_RCCEx_LSECSS_Callback(void) |
421 | /* NOTE : This function should not be modified, when the callback is needed, |
422 | { |
422 | the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file |
423 | /* NOTE : This function should not be modified, when the callback is needed, |
423 | */ |
424 | the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file |
424 | } |
425 | */ |
425 | #endif /* RCC_LSECSS_SUPPORT */ |
426 | } |
426 | |
427 | #endif /* RCC_LSECSS_SUPPORT */ |
427 | /** |
428 | 428 | * @} |
|
429 | /** |
429 | */ |
430 | * @} |
430 | |
431 | */ |
431 | /** |
432 | 432 | * @} |
|
433 | /** |
433 | */ |
434 | * @} |
434 | |
435 | */ |
435 | /** |
436 | 436 | * @} |
|
437 | /** |
437 | */ |
438 | * @} |
438 | |
439 | */ |
439 | /** |
440 | 440 | * @} |
|
441 | /** |
441 | */ |
442 | * @} |
442 | |
443 | */ |
443 | #endif /* HAL_RCC_MODULE_ENABLED */ |
444 | 444 | /** |
|
445 | #endif /* HAL_RCC_MODULE_ENABLED */ |
445 | * @} |
446 | /** |
446 | */ |
447 | * @} |
447 | |
448 | */ |
- | |
449 | - | ||
450 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
- |