WebSVN – DashDisplay – Diff – /branches/Dashboard_L152_v2/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_nor.c

 /**
   ******************************************************************************
   * @file    stm32l1xx_hal_nor.c
   * @author  MCD Application Team
   * @brief   NOR HAL module driver.
   *          This file provides a generic firmware to drive NOR memories mounted
   *          as external device.
   *
   @verbatim
   ==============================================================================
                      ##### How to use this driver #####
   ==============================================================================
     [..]
       This driver is a generic layered driver which contains a set of APIs used to
       control NOR flash memories. It uses the FSMC layer functions to interface
       with NOR devices. This driver is used as follows:
       (+) NOR flash memory configuration sequence using the function HAL_NOR_Init()
           with control and timing parameters for both normal and extended mode.
       (+) Read NOR flash memory manufacturer code and device IDs using the function
           HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef
           structure declared by the function caller.
       (+) Access NOR flash memory by read/write data unit operations using the functions
           HAL_NOR_Read(), HAL_NOR_Program().
       (+) Perform NOR flash erase block/chip operations using the functions
           HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
       (+) Read the NOR flash CFI (common flash interface) IDs using the function
           HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
           structure declared by the function caller.
       (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
           HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation
       (+) You can monitor the NOR device HAL state by calling the function
           HAL_NOR_GetState()
     [..]
      (@) This driver is a set of generic APIs which handle standard NOR flash operations.
          If a NOR flash device contains different operations and/or implementations,
          it should be implemented separately.
      *** NOR HAL driver macros list ***
      =============================================
      [..]
        Below the list of most used macros in NOR HAL driver.
       (+) NOR_WRITE : NOR memory write data to specified address
+    *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_NOR_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+      Use Functions @ref HAL_NOR_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+        (+) MspInitCallback    : NOR MspInit.
+        (+) MspDeInitCallback  : NOR MspDeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+      Use function @ref HAL_NOR_UnRegisterCallback() to reset a callback to the default
+      weak (surcharged) function. It allows to reset following callbacks:
+        (+) MspInitCallback    : NOR MspInit.
+        (+) MspDeInitCallback  : NOR MspDeInit.
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+      By default, after the @ref HAL_NOR_Init and if the state is HAL_NOR_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (surcharged) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (surcharged) functions in the @ref HAL_NOR_Init
+      and @ref  HAL_NOR_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the @ref HAL_NOR_Init and @ref HAL_NOR_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using @ref HAL_NOR_RegisterCallback before calling @ref HAL_NOR_DeInit
+      or @ref HAL_NOR_Init function.
+      When The compilation define USE_HAL_NOR_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (surcharged) callbacks are used.
   @endverbatim
   ******************************************************************************
   * @attention
+  *
-  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
+  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
   * All rights reserved.</center></h2>
+  *
   * This software component is licensed by ST under BSD 3-Clause license,
   * the "License"; You may not use this file except in compliance with the
   * License. You may obtain a copy of the License at:
-  *                        opensource.org/licenses/BSD-3-Clause
+  *                       opensource.org/licenses/BSD-3-Clause
+  *
   ******************************************************************************
   */
 /* Includes ------------------------------------------------------------------*/
 #include "stm32l1xx_hal.h"
+#if defined(FSMC_BANK1)
 /** @addtogroup STM32L1xx_HAL_Driver
   * @{
   */
 #ifdef HAL_NOR_MODULE_ENABLED
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
 /** @defgroup NOR NOR
   * @brief NOR driver modules
   * @{
   */
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
-/** @defgroup NOR_Private_Constants NOR Private Constants
+/** @defgroup NOR_Private_Defines NOR Private Defines
   * @{
   */
 /* Constants to define address to set to write a command */
 #define NOR_CMD_ADDRESS_FIRST                 (uint16_t)0x0555
 #define NOR_CMD_DATA_BUFFER_AND_PROG          (uint8_t)0x25
 #define NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM  (uint8_t)0x29
 #define NOR_CMD_DATA_BLOCK_ERASE              (uint8_t)0x30
+#define NOR_CMD_READ_ARRAY                    (uint16_t)0x00FF
+#define NOR_CMD_WORD_PROGRAM                  (uint16_t)0x0040
+#define NOR_CMD_BUFFERED_PROGRAM              (uint16_t)0x00E8
+#define NOR_CMD_CONFIRM                       (uint16_t)0x00D0
+#define NOR_CMD_BLOCK_ERASE                   (uint16_t)0x0020
+#define NOR_CMD_BLOCK_UNLOCK                  (uint16_t)0x0060
+#define NOR_CMD_READ_STATUS_REG               (uint16_t)0x0070
+#define NOR_CMD_CLEAR_STATUS_REG              (uint16_t)0x0050
 /* Mask on NOR STATUS REGISTER */
+#define NOR_MASK_STATUS_DQ4                   (uint16_t)0x0010
 #define NOR_MASK_STATUS_DQ5                   (uint16_t)0x0020
 #define NOR_MASK_STATUS_DQ6                   (uint16_t)0x0040
+#define NOR_MASK_STATUS_DQ7                   (uint16_t)0x0080
-/**
-  * @}
+/* Address of the primary command set */
-  */
+#define NOR_ADDRESS_COMMAND_SET               (uint16_t)0x0013
-/* Private macro -------------------------------------------------------------*/
+/* Command set code assignment (defined in JEDEC JEP137B version may 2004) */
+#define NOR_INTEL_SHARP_EXT_COMMAND_SET       (uint16_t)0x0001 /* Supported in this driver */
+#define NOR_AMD_FUJITSU_COMMAND_SET           (uint16_t)0x0002 /* Supported in this driver */
+#define NOR_INTEL_STANDARD_COMMAND_SET        (uint16_t)0x0003 /* Not Supported in this driver */
+#define NOR_AMD_FUJITSU_EXT_COMMAND_SET       (uint16_t)0x0004 /* Not Supported in this driver */
-/** @defgroup NOR_Private_Macros NOR Private Macros
+#define NOR_WINDBOND_STANDARD_COMMAND_SET     (uint16_t)0x0006 /* Not Supported in this driver */
-  * @{
-  */
+#define NOR_MITSUBISHI_STANDARD_COMMAND_SET   (uint16_t)0x0100 /* Not Supported in this driver */
+#define NOR_MITSUBISHI_EXT_COMMAND_SET        (uint16_t)0x0101 /* Not Supported in this driver */
+#define NOR_PAGE_WRITE_COMMAND_SET            (uint16_t)0x0102 /* Not Supported in this driver */
+#define NOR_INTEL_PERFORMANCE_COMMAND_SET     (uint16_t)0x0200 /* Not Supported in this driver */
+#define NOR_INTEL_DATA_COMMAND_SET            (uint16_t)0x0210 /* Not Supported in this driver */
 /**
   * @}
   */
+/* Private macro -------------------------------------------------------------*/
 /* Private variables ---------------------------------------------------------*/
 /** @defgroup NOR_Private_Variables NOR Private Variables
   * @{
   */
 static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
 /**
   * @}
   */
-/* Private function prototypes -----------------------------------------------*/
 /* Private functions ---------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
 /** @defgroup NOR_Exported_Functions NOR Exported Functions
   * @{
   */
 /** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
   * @brief    Initialization and Configuration functions
+  *
   @verbatim
   ==============================================================================
            ##### NOR Initialization and de_initialization functions #####
   ==============================================================================
   [..]
     This section provides functions allowing to initialize/de-initialize
     the NOR memory
 @endverbatim
   * @{
   */
 /**
   * @brief  Perform the NOR memory Initialization sequence
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @param  Timing pointer to NOR control timing structure
   * @param  ExtTiming pointer to NOR extended mode timing structure
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing,
+                               FSMC_NORSRAM_TimingTypeDef *ExtTiming)
+{
+  uint32_t deviceaddress;
   /* Check the NOR handle parameter */
-  if(hnor == NULL)
+  if (hnor == NULL)
+  {
-     return HAL_ERROR;
+    return HAL_ERROR;
+  }
-  if(hnor->State == HAL_NOR_STATE_RESET)
+  if (hnor->State == HAL_NOR_STATE_RESET)
+  {
     /* Allocate lock resource and initialize it */
     hnor->Lock = HAL_UNLOCKED;
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+    if (hnor->MspInitCallback == NULL)
+    {
+      hnor->MspInitCallback = HAL_NOR_MspInit;
+    }
+    /* Init the low level hardware */
+    hnor->MspInitCallback(hnor);
+#else
     /* Initialize the low level hardware (MSP) */
     HAL_NOR_MspInit(hnor);
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
+  }
   /* Initialize NOR control Interface */
-  FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
+  (void)FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
   /* Initialize NOR timing Interface */
-  FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
+  (void)FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank);
   /* Initialize NOR extended mode timing Interface */
-  FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
+  (void)FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
   /* Enable the NORSRAM device */
   __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
   /* Initialize NOR Memory Data Width*/
   if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
+  {
     uwNORMemoryDataWidth = NOR_MEMORY_8B;
   else
+  {
     uwNORMemoryDataWidth = NOR_MEMORY_16B;
+  }
-  /* Check the NOR controller state */
+  /* Initialize the NOR controller state */
   hnor->State = HAL_NOR_STATE_READY;
+  /* Select the NOR device address */
+  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS1;
+  }
+  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS2;
+  }
+  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  {
+    deviceaddress = NOR_MEMORY_ADRESS3;
+  }
+  else /* FSMC_NORSRAM_BANK4 */
+  {
+    deviceaddress = NOR_MEMORY_ADRESS4;
+  }
+  /* Get the value of the command set */
+  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+  hnor->CommandSet = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_ADDRESS_COMMAND_SET);
-  return HAL_OK;
+  return HAL_NOR_ReturnToReadMode(hnor);
+}
 /**
   * @brief  Perform NOR memory De-Initialization sequence
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
+{
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+  if (hnor->MspDeInitCallback == NULL)
+  {
+    hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  hnor->MspDeInitCallback(hnor);
+#else
   /* De-Initialize the low level hardware (MSP) */
   HAL_NOR_MspDeInit(hnor);
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
   /* Configure the NOR registers with their reset values */
-  FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
+  (void)FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
-  /* Update the NOR controller state */
+  /* Reset the NOR controller state */
   hnor->State = HAL_NOR_STATE_RESET;
   /* Release Lock */
   __HAL_UNLOCK(hnor);
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hnor);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NOR_MspInit could be implemented in the user file
    */
+}
 /**
   * @brief  NOR MSP DeInit
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   /* Prevent unused argument(s) compilation warning */
   UNUSED(hnor);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NOR_MspDeInit could be implemented in the user file
    */
+}
 /**
-  * @brief  NOR MSP Wait fro Ready/Busy signal
+  * @brief  NOR MSP Wait for Ready/Busy signal
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @param  Timeout Maximum timeout value
   * @retval None
   */
   UNUSED(hnor);
   UNUSED(Timeout);
   /* NOTE : This function Should not be modified, when the callback is needed,
             the HAL_NOR_MspWait could be implemented in the user file
    */
+}
 /**
   * @}
   */
 /** @defgroup NOR_Exported_Functions_Group2 Input and Output functions
   * @brief    Input Output and memory control functions
+  *
   @verbatim
   ==============================================================================
                 ##### NOR Input and Output functions #####
   ==============================================================================
   [..]
     This section provides functions allowing to use and control the NOR memory
 @endverbatim
   * @{
   */
 /**
   * @brief  Read NOR flash IDs
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @param  pNOR_ID  pointer to NOR ID structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
+{
-  uint32_t deviceaddress = 0;
+  uint32_t deviceaddress;
-  /* Process Locked */
+  HAL_NOR_StateTypeDef state;
-  __HAL_LOCK(hnor);
+  HAL_StatusTypeDef status = HAL_OK;
   /* Check the NOR controller state */
+  state = hnor->State;
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (state == HAL_NOR_STATE_BUSY)
+  {
-     return HAL_BUSY;
+    return HAL_BUSY;
+  }
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
-    deviceaddress = NOR_MEMORY_ADRESS1;
+      deviceaddress = NOR_MEMORY_ADRESS1;
-  }
+    }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-  {
+    {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+    /* Send read ID command */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE(deviceaddress, NOR_CMD_DATA_AUTO_SELECT);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+    if (status != HAL_ERROR)
+    {
+      /* Read the NOR IDs */
+      pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
+      pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+                                                                     DEVICE_CODE1_ADDR);
+      pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+                                                                     DEVICE_CODE2_ADDR);
+      pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth,
+                                                                     DEVICE_CODE3_ADDR);
+    }
+    /* Check the NOR controller state */
+    hnor->State = state;
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  else
+  {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
+  }
-  else /* FSMC_NORSRAM_BANK4 */
-  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  /* Send read ID command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
-  /* Read the NOR IDs */
-  pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
-  pNOR_ID->Device_Code1      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
-  pNOR_ID->Device_Code2      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
-  pNOR_ID->Device_Code3      = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  return HAL_OK;
+  return status;
+}
 /**
   * @brief  Returns the NOR memory to Read mode.
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
+{
-  uint32_t deviceaddress = 0;
+  uint32_t deviceaddress;
-  /* Process Locked */
+  HAL_NOR_StateTypeDef state;
-  __HAL_LOCK(hnor);
+  HAL_StatusTypeDef status = HAL_OK;
   /* Check the NOR controller state */
+  state = hnor->State;
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (state == HAL_NOR_STATE_BUSY)
+  {
-     return HAL_BUSY;
+    return HAL_BUSY;
+  }
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS1;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+    /* Check the NOR controller state */
+    hnor->State = state;
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  else
+  {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
+  }
-  else /* FSMC_NORSRAM_BANK4 */
-  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }
-  NOR_WRITE(deviceaddress, NOR_CMD_DATA_READ_RESET);
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  return HAL_OK;
+  return status;
+}
 /**
   * @brief  Read data from NOR memory
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @param  pAddress pointer to Device address
   * @param  pData  pointer to read data
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
-  uint32_t deviceaddress = 0;
+  uint32_t deviceaddress;
-  /* Process Locked */
+  HAL_NOR_StateTypeDef state;
-  __HAL_LOCK(hnor);
+  HAL_StatusTypeDef status = HAL_OK;
   /* Check the NOR controller state */
+  state = hnor->State;
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (state == HAL_NOR_STATE_BUSY)
+  {
-     return HAL_BUSY;
+    return HAL_BUSY;
+  }
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
-    deviceaddress = NOR_MEMORY_ADRESS1;
+      deviceaddress = NOR_MEMORY_ADRESS1;
-  }
+    }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-  {
+    {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+    /* Send read data command */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE(pAddress, NOR_CMD_READ_ARRAY);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+    if (status != HAL_ERROR)
+    {
+      /* Read the data */
+      *pData = (uint16_t)(*(__IO uint32_t *)pAddress);
+    }
+    /* Check the NOR controller state */
+    hnor->State = state;
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  else
+  {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
+  }
-  else /* FSMC_NORSRAM_BANK4 */
-  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  /* Send read data command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE((uint32_t)pAddress, NOR_CMD_DATA_READ_RESET);
-  /* Read the data */
-  *pData = *(__IO uint32_t *)(uint32_t)pAddress;
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  return HAL_OK;
+  return status;
+}
 /**
   * @brief  Program data to NOR memory
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @param  pAddress Device address
   * @param  pData  pointer to the data to write
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
+{
-  uint32_t deviceaddress = 0;
+  uint32_t deviceaddress;
-  /* Process Locked */
+  HAL_StatusTypeDef status = HAL_OK;
-  __HAL_LOCK(hnor);
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (hnor->State == HAL_NOR_STATE_BUSY)
+  {
-     return HAL_BUSY;
+    return HAL_BUSY;
+  }
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  else if (hnor->State == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
-    deviceaddress = NOR_MEMORY_ADRESS1;
+      deviceaddress = NOR_MEMORY_ADRESS1;
-  }
+    }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-  {
+    {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+    /* Send program data command */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE(pAddress, NOR_CMD_WORD_PROGRAM);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+    if (status != HAL_ERROR)
+    {
+      /* Write the data */
+      NOR_WRITE(pAddress, *pData);
+    }
+    /* Check the NOR controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  else
+  {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
+  }
-  else /* FSMC_NORSRAM_BANK4 */
-  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  /* Send program data command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
-  /* Write the data */
-  NOR_WRITE(pAddress, *pData);
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  return HAL_OK;
+  return status;
+}
 /**
-  * @brief  Reads a block of data from the FSMC NOR memory.
+  * @brief  Reads a half-word buffer from the NOR memory.
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to the NOR handle
-  *                the configuration information for NOR module.
   * @param  uwAddress NOR memory internal address to read from.
   * @param  pData pointer to the buffer that receives the data read from the
   *         NOR memory.
   * @param  uwBufferSize  number of Half word to read.
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+                                     uint32_t uwBufferSize)
+{
-  uint32_t deviceaddress = 0;
+  uint32_t deviceaddress;
+  uint32_t size = uwBufferSize;
-  /* Process Locked */
+  uint32_t address = uwAddress;
-  __HAL_LOCK(hnor);
+  uint16_t *data = pData;
+  HAL_NOR_StateTypeDef state;
+  HAL_StatusTypeDef status = HAL_OK;
   /* Check the NOR controller state */
+  state = hnor->State;
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (state == HAL_NOR_STATE_BUSY)
+  {
-     return HAL_BUSY;
+    return HAL_BUSY;
+  }
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
-    deviceaddress = NOR_MEMORY_ADRESS1;
+      deviceaddress = NOR_MEMORY_ADRESS1;
-  }
+    }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-  {
+    {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+    /* Send read data command */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE(deviceaddress, NOR_CMD_READ_ARRAY);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+    if (status != HAL_ERROR)
+    {
+      /* Read buffer */
+      while (size > 0U)
+      {
+        *data = *(__IO uint16_t *)address;
+        data++;
+        address += 2U;
+        size--;
+      }
+    }
+    /* Check the NOR controller state */
+    hnor->State = state;
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  else
+  {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
+  }
-  else /* FSMC_NORSRAM_BANK4 */
-  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  /* Send read data command */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(uwAddress, NOR_CMD_DATA_READ_RESET);
-  /* Read buffer */
-  while( uwBufferSize > 0)
-  {
-    *pData++ = *(__IO uint16_t *)uwAddress;
-    uwAddress += 2;
-    uwBufferSize--;
-  }
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  return HAL_OK;
+  return status;
+}
 /**
-  * @brief  Writes a half-word buffer to the FSMC NOR memory. This function
+  * @brief  Writes a half-word buffer to the NOR memory. This function must be used
-  *         must be used only with S29GL128P NOR memory.
+            only with S29GL128P NOR memory.
-  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to the NOR handle
-  *                the configuration information for NOR module.
-  * @param  uwAddress NOR memory internal address from which the data
+  * @param  uwAddress NOR memory internal start write address
-  * @note   Some NOR memory need Address aligned to xx bytes (can be aligned to
-  *          64 bytes boundary for example).
   * @param  pData pointer to source data buffer.
-  * @param  uwBufferSize number of Half words to write.
+  * @param  uwBufferSize Size of the buffer to write
-  * @note   The maximum buffer size allowed is NOR memory dependent
-  *         (can be 64 Bytes max for example).
   * @retval HAL status
   */
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData,
+                                        uint32_t uwBufferSize)
+{
-  uint16_t * p_currentaddress = (uint16_t *)NULL;
+  uint16_t *p_currentaddress;
-  uint16_t * p_endaddress = (uint16_t *)NULL;
+  const uint16_t *p_endaddress;
-  uint32_t lastloadedaddress = 0, deviceaddress = 0;
+  uint16_t *data = pData;
-  /* Process Locked */
+  uint32_t deviceaddress;
-  __HAL_LOCK(hnor);
+  HAL_StatusTypeDef status = HAL_OK;
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (hnor->State == HAL_NOR_STATE_BUSY)
+  {
-     return HAL_BUSY;
+    return HAL_BUSY;
+  }
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS1;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+  else if (hnor->State == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+      deviceaddress = NOR_MEMORY_ADRESS2;
-  }
+    }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-  {
+    {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+    /* Initialize variables */
+    p_currentaddress  = (uint16_t *)(deviceaddress + uwAddress);
+    p_endaddress      = (uint16_t *)(deviceaddress + uwAddress + (2U * (uwBufferSize - 1U)));
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      /* Issue unlock command sequence */
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+      /* Write Buffer Load Command */
+      NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
+      NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      /* Write Buffer Load Command */
+      NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_BUFFERED_PROGRAM);
+      NOR_WRITE((deviceaddress + uwAddress), (uint16_t)(uwBufferSize - 1U));
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+    if (status != HAL_ERROR)
+    {
+      /* Load Data into NOR Buffer */
+      while (p_currentaddress <= p_endaddress)
+      {
+        NOR_WRITE(p_currentaddress, *data);
+        data++;
+        p_currentaddress ++;
+      }
+      if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+      {
+        NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
+      }
+      else /* => hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET */
+      {
+        NOR_WRITE((deviceaddress + uwAddress), NOR_CMD_CONFIRM);
+      }
+    }
+    /* Check the NOR controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
-  else /* FSMC_NORSRAM_BANK4 */
+  else
+  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
-  }
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  /* Initialize variables */
-  p_currentaddress  = (uint16_t*)((uint32_t)(uwAddress));
-  p_endaddress      = p_currentaddress + (uwBufferSize-1);
-  lastloadedaddress = (uint32_t)(uwAddress);
-  /* Issue unlock command sequence */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  /* Write Buffer Load Command */
-  NOR_WRITE((uint32_t)(p_currentaddress), NOR_CMD_DATA_BUFFER_AND_PROG);
-  NOR_WRITE((uint32_t)(p_currentaddress), (uwBufferSize-1));
-  /* Load Data into NOR Buffer */
-  while(p_currentaddress <= p_endaddress)
-  {
-    /* Store last loaded address & data value (for polling) */
-    lastloadedaddress = (uint32_t)p_currentaddress;
-    NOR_WRITE(p_currentaddress, *pData++);
-    p_currentaddress++;
+    return HAL_ERROR;
+  }
-  NOR_WRITE((uint32_t)(lastloadedaddress), NOR_CMD_DATA_BUFFER_AND_PROG_CONFIRM);
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  return HAL_OK;
+  return status;
+}
 /**
   * @brief  Erase the specified block of the NOR memory
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @param  BlockAddress  Block to erase address
   * @param  Address Device address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
+{
-  uint32_t deviceaddress = 0;
+  uint32_t deviceaddress;
+  HAL_StatusTypeDef status = HAL_OK;
-  /* Process Locked */
-  __HAL_LOCK(hnor);
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (hnor->State == HAL_NOR_STATE_BUSY)
+  {
-     return HAL_BUSY;
+    return HAL_BUSY;
+  }
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  else if (hnor->State == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
-    deviceaddress = NOR_MEMORY_ADRESS1;
+      deviceaddress = NOR_MEMORY_ADRESS1;
-  }
+    }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
-  {
+    {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+      deviceaddress = NOR_MEMORY_ADRESS2;
-  }
+    }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-  {
+    {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+    /* Send block erase command sequence */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+      NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
+    }
+    else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+    {
+      NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_UNLOCK);
+      NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+      NOR_WRITE((BlockAddress + Address), NOR_CMD_BLOCK_ERASE);
+      NOR_WRITE((BlockAddress + Address), NOR_CMD_CONFIRM);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+    /* Check the NOR memory status and update the controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
-  else /* FSMC_NORSRAM_BANK4 */
+  else
+  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
+    return HAL_ERROR;
+  }
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  /* Send block erase command sequence */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
-  NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
-  /* Check the NOR memory status and update the controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  return HAL_OK;
+  return status;
+}
 /**
   * @brief  Erase the entire NOR chip.
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @param  Address  Device address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
+{
-  uint32_t deviceaddress = 0;
+  uint32_t deviceaddress;
-  /* Process Locked */
+  HAL_StatusTypeDef status = HAL_OK;
-  __HAL_LOCK(hnor);
+  UNUSED(Address);
   /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (hnor->State == HAL_NOR_STATE_BUSY)
+  {
-     return HAL_BUSY;
+    return HAL_BUSY;
+  }
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
-  {
-    deviceaddress = NOR_MEMORY_ADRESS1;
-  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+  else if (hnor->State == HAL_NOR_STATE_READY)
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+      deviceaddress = NOR_MEMORY_ADRESS2;
-  }
+    }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
-  {
+    {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+    /* Send NOR chip erase command sequence */
+    if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+    {
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD),
+                NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH),
+                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH),
+                NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
+      NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
+    }
+    else
+    {
+      /* Primary command set not supported by the driver */
+      status = HAL_ERROR;
+    }
+    /* Check the NOR memory status and update the controller state */
+    hnor->State = HAL_NOR_STATE_READY;
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
-  else /* FSMC_NORSRAM_BANK4 */
+  else
+  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
+    return HAL_ERROR;
+  }
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  /* Send NOR chip erase command sequence */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
-  /* Check the NOR memory status and update the controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  return HAL_OK;
+  return status;
+}
 /**
   * @brief  Read NOR flash CFI IDs
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @param  pNOR_CFI  pointer to NOR CFI IDs structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
+{
-  uint32_t deviceaddress = 0;
+  uint32_t deviceaddress;
-  /* Process Locked */
-  __HAL_LOCK(hnor);
+  HAL_NOR_StateTypeDef state;
   /* Check the NOR controller state */
+  state = hnor->State;
-  if(hnor->State == HAL_NOR_STATE_BUSY)
+  if (state == HAL_NOR_STATE_BUSY)
+  {
-     return HAL_BUSY;
+    return HAL_BUSY;
+  }
-  /* Select the NOR device address */
-  if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+  else if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_PROTECTED))
+  {
+    /* Process Locked */
+    __HAL_LOCK(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+    /* Select the NOR device address */
+    if (hnor->Init.NSBank == FSMC_NORSRAM_BANK1)
+    {
-    deviceaddress = NOR_MEMORY_ADRESS1;
+      deviceaddress = NOR_MEMORY_ADRESS1;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS2;
+    }
+    else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+    {
+      deviceaddress = NOR_MEMORY_ADRESS3;
+    }
+    else /* FSMC_NORSRAM_BANK4 */
+    {
+      deviceaddress = NOR_MEMORY_ADRESS4;
+    }
+    /* Send read CFI query command */
+    NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+    /* read the NOR CFI information */
+    pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
+    pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
+    pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
+    pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
+    /* Check the NOR controller state */
+    hnor->State = state;
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK2)
+  else
+  {
-    deviceaddress = NOR_MEMORY_ADRESS2;
+    return HAL_ERROR;
+  }
+  return HAL_OK;
+}
+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)
+/**
-  else if (hnor->Init.NSBank == FSMC_NORSRAM_BANK3)
+  * @brief  Register a User NOR Callback
+  *         To be used instead of the weak (surcharged) predefined callback
+  * @param hnor : NOR handle
+  * @param CallbackId : ID of the callback to be registered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
+  *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
+  * @param pCallback : pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId,
+                                           pNOR_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_NOR_StateTypeDef state;
+  if (pCallback == NULL)
+  {
-    deviceaddress = NOR_MEMORY_ADRESS3;
+    return HAL_ERROR;
+  }
-  else /* FSMC_NORSRAM_BANK4 */
+  /* Process locked */
+  __HAL_LOCK(hnor);
+  state = hnor->State;
+  if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+  {
-    deviceaddress = NOR_MEMORY_ADRESS4;
+    switch (CallbackId)
-  }
+    {
+      case HAL_NOR_MSP_INIT_CB_ID :
+        hnor->MspInitCallback = pCallback;
+        break;
+      case HAL_NOR_MSP_DEINIT_CB_ID :
+        hnor->MspDeInitCallback = pCallback;
+        break;
+      default :
-  /* Update the NOR controller state */
+        /* update return status */
-  hnor->State = HAL_NOR_STATE_BUSY;
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
-  /* Send read CFI query command */
+    /* update return status */
-  NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
+    status =  HAL_ERROR;
+  }
-  /* read the NOR CFI information */
+  /* Release Lock */
-  pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
+  __HAL_UNLOCK(hnor);
-  pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
+  return status;
-  pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
-  pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
+}
+/**
+  * @brief  Unregister a User NOR Callback
+  *         NOR Callback is redirected to the weak (surcharged) predefined callback
+  * @param hnor : NOR handle
+  * @param CallbackId : ID of the callback to be unregistered
+  *        This parameter can be one of the following values:
+  *          @arg @ref HAL_NOR_MSP_INIT_CB_ID       NOR MspInit callback ID
+  *          @arg @ref HAL_NOR_MSP_DEINIT_CB_ID     NOR MspDeInit callback ID
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  HAL_NOR_StateTypeDef state;
+  /* Process locked */
+  __HAL_LOCK(hnor);
+  state = hnor->State;
+  if ((state == HAL_NOR_STATE_READY) || (state == HAL_NOR_STATE_RESET) || (state == HAL_NOR_STATE_PROTECTED))
+  {
+    switch (CallbackId)
+    {
+      case HAL_NOR_MSP_INIT_CB_ID :
+        hnor->MspInitCallback = HAL_NOR_MspInit;
+        break;
+      case HAL_NOR_MSP_DEINIT_CB_ID :
+        hnor->MspDeInitCallback = HAL_NOR_MspDeInit;
+        break;
+      default :
-  /* Check the NOR controller state */
+        /* update return status */
-  hnor->State = HAL_NOR_STATE_READY;
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* update return status */
+    status =  HAL_ERROR;
+  }
-  /* Process unlocked */
+  /* Release Lock */
   __HAL_UNLOCK(hnor);
-  return HAL_OK;
+  return status;
+}
+#endif /* (USE_HAL_NOR_REGISTER_CALLBACKS) */
 /**
   * @}
   */
-/** @defgroup NOR_Exported_Functions_Group3 Control functions
+/** @defgroup NOR_Exported_Functions_Group3 NOR Control functions
- *  @brief   management functions
+  *  @brief   management functions
- *
+  *
 @verbatim
   ==============================================================================
                         ##### NOR Control functions #####
   ==============================================================================
   [..]
     This subsection provides a set of functions allowing to control dynamically
     the NOR interface.
 @endverbatim
   * @{
   */
 /**
   * @brief  Enables dynamically NOR write operation.
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
+{
+  /* Check the NOR controller state */
+  if (hnor->State == HAL_NOR_STATE_PROTECTED)
+  {
-  /* Process Locked */
+    /* Process Locked */
-  __HAL_LOCK(hnor);
+    __HAL_LOCK(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
-  /* Enable write operation */
+    /* Enable write operation */
-  FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
+    (void)FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank);
-  /* Update the NOR controller state */
+    /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
+    hnor->State = HAL_NOR_STATE_READY;
-  /* Process unlocked */
+    /* Process unlocked */
-  __HAL_UNLOCK(hnor);
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
   return HAL_OK;
+}
 /**
   * @brief  Disables dynamically NOR write operation.
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
+{
+  /* Check the NOR controller state */
+  if (hnor->State == HAL_NOR_STATE_READY)
+  {
-  /* Process Locked */
+    /* Process Locked */
-  __HAL_LOCK(hnor);
+    __HAL_LOCK(hnor);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_BUSY;
+    /* Disable write operation */
+    (void)FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
+    /* Update the NOR controller state */
+    hnor->State = HAL_NOR_STATE_PROTECTED;
+    /* Process unlocked */
+    __HAL_UNLOCK(hnor);
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
-  /* Update the SRAM controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  /* Disable write operation */
-  FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank);
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_PROTECTED;
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
   return HAL_OK;
+}
 /**
   * @}
   */
-/** @defgroup NOR_Exported_Functions_Group4 State functions
+/** @defgroup NOR_Exported_Functions_Group4 NOR State functions
- *  @brief   Peripheral State functions
+  *  @brief   Peripheral State functions
- *
+  *
 @verbatim
   ==============================================================================
                       ##### NOR State functions #####
   ==============================================================================
   [..]
     This subsection permits to get in run-time the status of the NOR controller
     and the data flow.
 @endverbatim
   * @{
   */
 /**
   * @brief  return the NOR controller state
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval NOR controller state
+}
 /**
   * @brief  Returns the NOR operation status.
   * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @param  Address Device address
-  * @param  Timeout NOR progamming Timeout
+  * @param  Timeout NOR programming Timeout
-  * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
+  * @retval NOR_Status The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
   *         or HAL_NOR_STATUS_TIMEOUT
   */
 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
 {
   HAL_NOR_StatusTypeDef status = HAL_NOR_STATUS_ONGOING;
+  uint16_t tmpsr1;
-  uint16_t tmp_sr1 = 0, tmp_sr2 = 0;
+  uint16_t tmpsr2;
-  uint32_t tickstart = 0;
+  uint32_t tickstart;
   /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
   HAL_NOR_MspWait(hnor, Timeout);
+  /* Get the NOR memory operation status -------------------------------------*/
   /* Get tick */
   tickstart = HAL_GetTick();
-  while((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
+  if (hnor->CommandSet == NOR_AMD_FUJITSU_COMMAND_SET)
+  {
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
+    while ((status != HAL_NOR_STATUS_SUCCESS) && (status != HAL_NOR_STATUS_TIMEOUT))
+    {
+      /* Check for the Timeout */
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
-        status = HAL_NOR_STATUS_TIMEOUT;
+          status = HAL_NOR_STATUS_TIMEOUT;
-      }
+        }
-    }
+      }
+      /* Read NOR status register (DQ6 and DQ5) */
+      tmpsr1 = *(__IO uint16_t *)Address;
+      tmpsr2 = *(__IO uint16_t *)Address;
-    /* Read NOR status register (DQ6 and DQ5) */
+      /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
-    tmp_sr1 = *(__IO uint16_t *)Address;
+      if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
+      {
-    tmp_sr2 = *(__IO uint16_t *)Address;
+        return HAL_NOR_STATUS_SUCCESS ;
+      }
+      if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+      {
+        status = HAL_NOR_STATUS_ONGOING;
+      }
+      tmpsr1 = *(__IO uint16_t *)Address;
+      tmpsr2 = *(__IO uint16_t *)Address;
-    /* If DQ6 did not toggle between the two reads then return NOR_Success */
+      /* If DQ6 did not toggle between the two reads then return HAL_NOR_STATUS_SUCCESS  */
-    if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
+      if ((tmpsr1 & NOR_MASK_STATUS_DQ6) == (tmpsr2 & NOR_MASK_STATUS_DQ6))
-    {
+      {
-      return HAL_NOR_STATUS_SUCCESS;
+        return HAL_NOR_STATUS_SUCCESS;
+      }
+      if ((tmpsr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+      {
+        return HAL_NOR_STATUS_ERROR;
+      }
+    }
+  }
-    if((tmp_sr1 & NOR_MASK_STATUS_DQ5) != NOR_MASK_STATUS_DQ5)
+  else if (hnor->CommandSet == NOR_INTEL_SHARP_EXT_COMMAND_SET)
+  {
+    do
+    {
-      status = HAL_NOR_STATUS_ONGOING;
+      NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
-    }
-    tmp_sr1 = *(__IO uint16_t *)Address;
-    tmp_sr2 = *(__IO uint16_t *)Address;
+      tmpsr2 = *(__IO uint16_t *)(Address);
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
-    /* If DQ6 did not toggle between the two reads then return NOR_Success */
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          return HAL_NOR_STATUS_TIMEOUT;
+        }
+      }
+    } while ((tmpsr2 & NOR_MASK_STATUS_DQ7) == 0U);
+    NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
+    tmpsr1 = *(__IO uint16_t *)(Address);
-    if((tmp_sr1 & NOR_MASK_STATUS_DQ6) == (tmp_sr2 & NOR_MASK_STATUS_DQ6))
+    if ((tmpsr1  & (NOR_MASK_STATUS_DQ5 | NOR_MASK_STATUS_DQ4)) != 0U)
+    {
+      /* Clear the Status Register  */
+      NOR_WRITE(Address, NOR_CMD_READ_STATUS_REG);
-      return HAL_NOR_STATUS_SUCCESS;
+      status = HAL_NOR_STATUS_ERROR;
+    }
-    else if((tmp_sr1 & NOR_MASK_STATUS_DQ5) == NOR_MASK_STATUS_DQ5)
+    else
+    {
-      return HAL_NOR_STATUS_ERROR;
+      status = HAL_NOR_STATUS_SUCCESS;
     }
+  }
+  else
+  {
+    /* Primary command set not supported by the driver */
+    status = HAL_NOR_STATUS_ERROR;
+  }
   /* Return the operation status */
   return status;
+}
   */
 /**
   * @}
   */
 /**
   * @}
   */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
 #endif /* HAL_NOR_MODULE_ENABLED */
 /**
   * @}
   */
+#endif /* FSMC_BANK1 */
 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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(root)/branches/Dashboard_L152_v2/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_nor.c – Rev 56 → 61