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/**
 1 
/**
2 
  ******************************************************************************
 2 
  ******************************************************************************
3 
  * @file    stm32l1xx_hal_dma.c
 3 
  * @file    stm32l1xx_hal_dma.c
4 
  * @author  MCD Application Team
 4 
  * @author  MCD Application Team
5 
  * @brief   DMA HAL module driver.
 5 
  * @brief   DMA HAL module driver.
6 
  *          This file provides firmware functions to manage the following
 6 
  *          This file provides firmware functions to manage the following
7 
  *          functionalities of the Direct Memory Access (DMA) peripheral:
 7 
  *          functionalities of the Direct Memory Access (DMA) peripheral:
8 
  *           + Initialization and de-initialization functions
 8 
  *           + Initialization and de-initialization functions
9 
  *           + IO operation functions
 9 
  *           + IO operation functions
10 
  *           + Peripheral State and errors functions
 10 
  *           + Peripheral State and errors functions
11 
  @verbatim
 11 
  *
12 
  ==============================================================================
 12 
  ******************************************************************************
13 
                        ##### How to use this driver #####
 13 
  * @attention
14 
  ==============================================================================
 14 
  *
15 
  [..]
 15 
  * Copyright (c) 2017 STMicroelectronics.
16 
   (#) Enable and configure the peripheral to be connected to the DMA Channel
 16 
  * All rights reserved.
17 
       (except for internal SRAM / FLASH memories: no initialization is
 17 
  *
18 
       necessary). Please refer to the Reference manual for connection between peripherals
 18 
  * This software is licensed under terms that can be found in the LICENSE file
19 
       and DMA requests.
 19 
  * in the root directory of this software component.
20 
 
 20 
  * If no LICENSE file comes with this software, it is provided AS-IS.
21 
   (#) For a given Channel, program the required configuration through the following parameters:
 21 
  *
22 
       Channel request, Transfer Direction, Source and Destination data formats,
 22 
  ******************************************************************************
23 
       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
 23 
  @verbatim
24 
       using HAL_DMA_Init() function.
 24 
  ==============================================================================
25 
 
 25 
                        ##### How to use this driver #####
26 
   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
 26 
  ==============================================================================
27 
       detection.
 27 
  [..]
28 
 
 28 
   (#) Enable and configure the peripheral to be connected to the DMA Channel
29 
   (#) Use HAL_DMA_Abort() function to abort the current transfer
 29 
       (except for internal SRAM / FLASH memories: no initialization is
30 
 
 30 
       necessary). Please refer to the Reference manual for connection between peripherals
31 
     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
 31 
       and DMA requests.
32 
     *** Polling mode IO operation ***
 32 
 
33 
     =================================
 33 
   (#) For a given Channel, program the required configuration through the following parameters:
34 
     [..]
 34 
       Channel request, Transfer Direction, Source and Destination data formats,
35 
       (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
 35 
       Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
36 
           address and destination address and the Length of data to be transferred
 36 
       using HAL_DMA_Init() function.
37 
       (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
 37 
 
38 
           case a fixed Timeout can be configured by User depending from his application.
 38 
   (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
39 
 
 39 
       detection.
40 
     *** Interrupt mode IO operation ***
 40 
 
41 
     ===================================
 41 
   (#) Use HAL_DMA_Abort() function to abort the current transfer
42 
     [..]
 42 
 
43 
       (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
 43 
     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
44 
       (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
 44 
     *** Polling mode IO operation ***
45 
       (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
 45 
     =================================
46 
           Source address and destination address and the Length of data to be transferred.
 46 
     [..]
47 
           In this case the DMA interrupt is configured
 47 
       (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source
48 
       (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
 48 
           address and destination address and the Length of data to be transferred
49 
       (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
 49 
       (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this
50 
              add his own function to register callbacks with HAL_DMA_RegisterCallback().
 50 
           case a fixed Timeout can be configured by User depending from his application.
51 
 
 51 
 
52 
     *** DMA HAL driver macros list ***
 52 
     *** Interrupt mode IO operation ***
53 
     =============================================
 53 
     ===================================
54 
     [..]
 54 
     [..]
55 
       Below the list of macros in DMA HAL driver.
 55 
       (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
56 
 
 56 
       (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
57 
       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
 57 
       (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
58 
       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
 58 
           Source address and destination address and the Length of data to be transferred.
59 
       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
 59 
           In this case the DMA interrupt is configured
60 
       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
 60 
       (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
61 
       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
 61 
       (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
62 
       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
 62 
              add his own function to register callbacks with HAL_DMA_RegisterCallback().
63 
       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
 63 
 
64 
 
 64 
     *** DMA HAL driver macros list ***
65 
     [..]
 65 
     =============================================
66 
      (@) You can refer to the DMA HAL driver header file for more useful macros
 66 
     [..]
67 
 
 67 
       Below the list of macros in DMA HAL driver.
68 
  @endverbatim
 68 
 
69 
  ******************************************************************************
 69 
       (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
70 
  * @attention
 70 
       (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
71 
  *
 71 
       (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
72 
  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
 72 
       (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
73 
  * All rights reserved.</center></h2>
 73 
       (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
74 
  *
 74 
       (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
75 
  * This software component is licensed by ST under BSD 3-Clause license,
 75 
       (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
76 
  * the "License"; You may not use this file except in compliance with the
 76 
 
77 
  * License. You may obtain a copy of the License at:
 77 
     [..]
78 
  *                        opensource.org/licenses/BSD-3-Clause
 78 
      (@) You can refer to the DMA HAL driver header file for more useful macros
79 
  *
 79 
 
80 
  ******************************************************************************
 80 
  @endverbatim
81 
  */
 81 
  ******************************************************************************
82 
 
 82 
  */
83 
/* Includes ------------------------------------------------------------------*/
 83 
 
84 
#include "stm32l1xx_hal.h"
 84 
/* Includes ------------------------------------------------------------------*/
85 
 
 85 
#include "stm32l1xx_hal.h"
86 
/** @addtogroup STM32L1xx_HAL_Driver
 86 
 
87 
  * @{
 87 
/** @addtogroup STM32L1xx_HAL_Driver
88 
  */
 88 
  * @{
89 
 
 89 
  */
90 
/** @defgroup DMA DMA
 90 
 
91 
  * @brief DMA HAL module driver
 91 
/** @defgroup DMA DMA
92 
  * @{
 92 
  * @brief DMA HAL module driver
93 
  */
 93 
  * @{
94 
 
 94 
  */
95 
#ifdef HAL_DMA_MODULE_ENABLED
 95 
 
96 
 
 96 
#ifdef HAL_DMA_MODULE_ENABLED
97 
/* Private typedef -----------------------------------------------------------*/
 97 
 
98 
/* Private define ------------------------------------------------------------*/
 98 
/* Private typedef -----------------------------------------------------------*/
99 
/* Private macro -------------------------------------------------------------*/
 99 
/* Private define ------------------------------------------------------------*/
100 
/* Private variables ---------------------------------------------------------*/
 100 
/* Private macro -------------------------------------------------------------*/
101 
/* Private function prototypes -----------------------------------------------*/
 101 
/* Private variables ---------------------------------------------------------*/
102 
/** @defgroup DMA_Private_Functions DMA Private Functions
 102 
/* Private function prototypes -----------------------------------------------*/
103 
  * @{
 103 
/** @defgroup DMA_Private_Functions DMA Private Functions
104 
  */
 104 
  * @{
105 
 
 105 
  */
106 
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
 106 
 
107 
/**
 107 
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
108 
  * @}
 108 
/**
109 
  */
 109 
  * @}
110 
 
 110 
  */
111 
/* Exported functions ---------------------------------------------------------*/
 111 
 
112 
 
 112 
/* Exported functions ---------------------------------------------------------*/
113 
/** @defgroup DMA_Exported_Functions DMA Exported Functions
 113 
 
114 
  * @{
 114 
/** @defgroup DMA_Exported_Functions DMA Exported Functions
115 
  */
 115 
  * @{
116 
 
 116 
  */
117 
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
 117 
 
118 
 *  @brief   Initialization and de-initialization functions
 118 
/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
119 
 *
 119 
 *  @brief   Initialization and de-initialization functions
120 
@verbatim
 120 
 *
121 
 ===============================================================================
 121 
@verbatim
122 
             ##### Initialization and de-initialization functions  #####
 122 
 ===============================================================================
123 
 ===============================================================================
 123 
             ##### Initialization and de-initialization functions  #####
124 
    [..]
 124 
 ===============================================================================
125 
    This section provides functions allowing to initialize the DMA Channel source
 125 
    [..]
126 
    and destination addresses, incrementation and data sizes, transfer direction,
 126 
    This section provides functions allowing to initialize the DMA Channel source
127 
    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
 127 
    and destination addresses, incrementation and data sizes, transfer direction,
128 
    [..]
 128 
    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
129 
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
 129 
    [..]
130 
    reference manual.
 130 
    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
131 
 
 131 
    reference manual.
132 
@endverbatim
 132 
 
133 
  * @{
 133 
@endverbatim
134 
  */
 134 
  * @{
135 
 
 135 
  */
136 
/**
 136 
 
137 
  * @brief  Initialize the DMA according to the specified
 137 
/**
138 
  *         parameters in the DMA_InitTypeDef and initialize the associated handle.
 138 
  * @brief  Initialize the DMA according to the specified
139 
  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
 139 
  *         parameters in the DMA_InitTypeDef and initialize the associated handle.
140 
  *               the configuration information for the specified DMA Channel.
 140 
  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
141 
  * @retval HAL status
 141 
  *               the configuration information for the specified DMA Channel.
142 
  */
 142 
  * @retval HAL status
143 
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
 143 
  */
144 
{
 144 
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
145 
  uint32_t tmp;
 145 
{
146 
 
 146 
  uint32_t tmp;
147 
  /* Check the DMA handle allocation */
 147 
 
148 
  if(hdma == NULL)
 148 
  /* Check the DMA handle allocation */
149 
  {
 149 
  if(hdma == NULL)
150 
    return HAL_ERROR;
 150 
  {
151 
  }
 151 
    return HAL_ERROR;
152 
 
 152 
  }
153 
  /* Check the parameters */
 153 
 
154 
  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
 154 
  /* Check the parameters */
155 
  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
 155 
  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
156 
  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
 156 
  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
157 
  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
 157 
  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
158 
  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
 158 
  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
159 
  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
 159 
  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
160 
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
 160 
  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
161 
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
 161 
  assert_param(IS_DMA_MODE(hdma->Init.Mode));
162 
 
 162 
  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
163 
#if defined (DMA2)
 163 
 
164 
  /* Compute the channel index */
 164 
#if defined (DMA2)
165 
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 165 
  /* Compute the channel index */
166 
  {
 166 
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
167 
    /* DMA1 */
 167 
  {
168 
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
 168 
    /* DMA1 */
169 
    hdma->DmaBaseAddress = DMA1;
 169 
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
170 
  }
 170 
    hdma->DmaBaseAddress = DMA1;
171 
  else
 171 
  }
172 
  {
 172 
  else
173 
    /* DMA2 */
 173 
  {
174 
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
 174 
    /* DMA2 */
175 
    hdma->DmaBaseAddress = DMA2;
 175 
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
176 
  }
 176 
    hdma->DmaBaseAddress = DMA2;
177 
#else
 177 
  }
178 
  /* calculation of the channel index */
 178 
#else
179 
  /* DMA1 */
 179 
  /* calculation of the channel index */
180 
  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
 180 
  /* DMA1 */
181 
  hdma->DmaBaseAddress = DMA1;
 181 
  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
182 
#endif
 182 
  hdma->DmaBaseAddress = DMA1;
183 
 
 183 
#endif
184 
  /* Change DMA peripheral state */
 184 
 
185 
  hdma->State = HAL_DMA_STATE_BUSY;
 185 
  /* Change DMA peripheral state */
186 
 
 186 
  hdma->State = HAL_DMA_STATE_BUSY;
187 
  /* Get the CR register value */
 187 
 
188 
  tmp = hdma->Instance->CCR;
 188 
  /* Get the CR register value */
189 
 
 189 
  tmp = hdma->Instance->CCR;
190 
  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
 190 
 
191 
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE   | DMA_CCR_PSIZE  |
 191 
  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
192 
                      DMA_CCR_MINC  | DMA_CCR_PINC    | DMA_CCR_CIRC   |
 192 
  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE   | DMA_CCR_PSIZE  |
193 
                      DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
 193 
                      DMA_CCR_MINC  | DMA_CCR_PINC    | DMA_CCR_CIRC   |
194 
 
 194 
                      DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
195 
  /* Prepare the DMA Channel configuration */
 195 
 
196 
  tmp |=  hdma->Init.Direction        |
 196 
  /* Prepare the DMA Channel configuration */
197 
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
 197 
  tmp |=  hdma->Init.Direction        |
198 
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
 198 
          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
199 
          hdma->Init.Mode                | hdma->Init.Priority;
 199 
          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
200 
 
 200 
          hdma->Init.Mode                | hdma->Init.Priority;
201 
  /* Write to DMA Channel CR register */
 201 
 
202 
  hdma->Instance->CCR = tmp;
 202 
  /* Write to DMA Channel CR register */
203 
 
 203 
  hdma->Instance->CCR = tmp;
204 
  /* Initialise the error code */
 204 
 
205 
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 205 
  /* Initialise the error code */
206 
 
 206 
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
207 
  /* Initialize the DMA state*/
 207 
 
208 
  hdma->State = HAL_DMA_STATE_READY;
 208 
  /* Initialize the DMA state*/
209 
 
 209 
  hdma->State = HAL_DMA_STATE_READY;
210 
  /* Allocate lock resource and initialize it */
 210 
 
211 
  hdma->Lock = HAL_UNLOCKED;
 211 
  /* Allocate lock resource and initialize it */
212 
 
 212 
  hdma->Lock = HAL_UNLOCKED;
213 
  return HAL_OK;
 213 
 
214 
}
 214 
  return HAL_OK;
215 
 
 215 
}
216 
/**
 216 
 
217 
  * @brief  DeInitialize the DMA peripheral.
 217 
/**
218 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 218 
  * @brief  DeInitialize the DMA peripheral.
219 
  *               the configuration information for the specified DMA Channel.
 219 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
220 
  * @retval HAL status
 220 
  *               the configuration information for the specified DMA Channel.
221 
  */
 221 
  * @retval HAL status
222 
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
 222 
  */
223 
{
 223 
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
224 
 
 224 
{
225 
  /* Check the DMA handle allocation */
 225 
 
226 
  if (NULL == hdma )
 226 
  /* Check the DMA handle allocation */
227 
  {
 227 
  if (NULL == hdma )
228 
    return HAL_ERROR;
 228 
  {
229 
  }
 229 
    return HAL_ERROR;
230 
 
 230 
  }
231 
  /* Check the parameters */
 231 
 
232 
  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
 232 
  /* Check the parameters */
233 
 
 233 
  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
234 
  /* Disable the selected DMA Channelx */
 234 
 
235 
  __HAL_DMA_DISABLE(hdma);
 235 
  /* Disable the selected DMA Channelx */
236 
 
 236 
  __HAL_DMA_DISABLE(hdma);
237 
#if defined (DMA2)
 237 
 
238 
  /* Compute the channel index */
 238 
#if defined (DMA2)
239 
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
 239 
  /* Compute the channel index */
240 
  {
 240 
  if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
241 
    /* DMA1 */
 241 
  {
242 
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
 242 
    /* DMA1 */
243 
    hdma->DmaBaseAddress = DMA1;
 243 
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
244 
  }
 244 
    hdma->DmaBaseAddress = DMA1;
245 
  else
 245 
  }
246 
  {
 246 
  else
247 
    /* DMA2 */
 247 
  {
248 
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
 248 
    /* DMA2 */
249 
    hdma->DmaBaseAddress = DMA2;
 249 
    hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
250 
  }
 250 
    hdma->DmaBaseAddress = DMA2;
251 
#else
 251 
  }
252 
  /* calculation of the channel index */
 252 
#else
253 
  /* DMA1 */
 253 
  /* calculation of the channel index */
254 
  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
 254 
  /* DMA1 */
255 
  hdma->DmaBaseAddress = DMA1;
 255 
  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
256 
#endif
 256 
  hdma->DmaBaseAddress = DMA1;
257 
 
 257 
#endif
258 
  /* Reset DMA Channel CR register */
 258 
 
259 
  hdma->Instance->CCR = 0U;
 259 
  /* Reset DMA Channel CR register */
260 
 
 260 
  hdma->Instance->CCR = 0U;
261 
  /* Clear all flags */
 261 
 
262 
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 262 
  /* Clear all flags */
263 
 
 263 
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
264 
  /* Clean callbacks */
 264 
 
265 
  hdma->XferCpltCallback = NULL;
 265 
  /* Clean callbacks */
266 
  hdma->XferHalfCpltCallback = NULL;
 266 
  hdma->XferCpltCallback = NULL;
267 
  hdma->XferErrorCallback = NULL;
 267 
  hdma->XferHalfCpltCallback = NULL;
268 
  hdma->XferAbortCallback = NULL;
 268 
  hdma->XferErrorCallback = NULL;
269 
 
 269 
  hdma->XferAbortCallback = NULL;
270 
  /* Initialise the error code */
 270 
 
271 
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 271 
  /* Initialise the error code */
272 
 
 272 
  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
273 
  /* Initialize the DMA state */
 273 
 
274 
  hdma->State = HAL_DMA_STATE_RESET;
 274 
  /* Initialize the DMA state */
275 
 
 275 
  hdma->State = HAL_DMA_STATE_RESET;
276 
  /* Release Lock */
 276 
 
277 
  __HAL_UNLOCK(hdma);
 277 
  /* Release Lock */
278 
 
 278 
  __HAL_UNLOCK(hdma);
279 
  return HAL_OK;
 279 
 
280 
}
 280 
  return HAL_OK;
281 
 
 281 
}
282 
/**
 282 
 
283 
  * @}
 283 
/**
284 
  */
 284 
  * @}
285 
 
 285 
  */
286 
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
 286 
 
287 
 *  @brief   Input and Output operation functions
 287 
/** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions
288 
 *
 288 
 *  @brief   Input and Output operation functions
289 
@verbatim
 289 
 *
290 
 ===============================================================================
 290 
@verbatim
291 
                      #####  IO operation functions  #####
 291 
 ===============================================================================
292 
 ===============================================================================
 292 
                      #####  IO operation functions  #####
293 
    [..]  This section provides functions allowing to:
 293 
 ===============================================================================
294 
      (+) Configure the source, destination address and data length and Start DMA transfer
 294 
    [..]  This section provides functions allowing to:
295 
      (+) Configure the source, destination address and data length and
 295 
      (+) Configure the source, destination address and data length and Start DMA transfer
296 
          Start DMA transfer with interrupt
 296 
      (+) Configure the source, destination address and data length and
297 
      (+) Abort DMA transfer
 297 
          Start DMA transfer with interrupt
298 
      (+) Poll for transfer complete
 298 
      (+) Abort DMA transfer
299 
      (+) Handle DMA interrupt request
 299 
      (+) Poll for transfer complete
300 
 
 300 
      (+) Handle DMA interrupt request
301 
@endverbatim
 301 
 
302 
  * @{
 302 
@endverbatim
303 
  */
 303 
  * @{
304 
 
 304 
  */
305 
/**
 305 
 
306 
  * @brief  Start the DMA Transfer.
 306 
/**
307 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 307 
  * @brief  Start the DMA Transfer.
308 
  *               the configuration information for the specified DMA Channel.
 308 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
309 
  * @param  SrcAddress The source memory Buffer address
 309 
  *               the configuration information for the specified DMA Channel.
310 
  * @param  DstAddress The destination memory Buffer address
 310 
  * @param  SrcAddress The source memory Buffer address
311 
  * @param  DataLength The length of data to be transferred from source to destination
 311 
  * @param  DstAddress The destination memory Buffer address
312 
  * @retval HAL status
 312 
  * @param  DataLength The length of data to be transferred from source to destination
313 
  */
 313 
  * @retval HAL status
314 
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 314 
  */
315 
{
 315 
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
316 
  HAL_StatusTypeDef status = HAL_OK;
 316 
{
317 
 
 317 
  HAL_StatusTypeDef status = HAL_OK;
318 
  /* Check the parameters */
 318 
 
319 
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
 319 
  /* Check the parameters */
320 
 
 320 
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
321 
  /* Process locked */
 321 
 
322 
  __HAL_LOCK(hdma);
 322 
  /* Process locked */
323 
 
 323 
  __HAL_LOCK(hdma);
324 
  if(HAL_DMA_STATE_READY == hdma->State)
 324 
 
325 
  {
 325 
  if(HAL_DMA_STATE_READY == hdma->State)
326 
    /* Change DMA peripheral state */
 326 
  {
327 
    hdma->State = HAL_DMA_STATE_BUSY;
 327 
    /* Change DMA peripheral state */
328 
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 328 
    hdma->State = HAL_DMA_STATE_BUSY;
329 
 
 329 
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
330 
    /* Disable the peripheral */
 330 
 
331 
    __HAL_DMA_DISABLE(hdma);
 331 
    /* Disable the peripheral */
332 
 
 332 
    __HAL_DMA_DISABLE(hdma);
333 
    /* Configure the source, destination address and the data length & clear flags*/
 333 
 
334 
    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 334 
    /* Configure the source, destination address and the data length & clear flags*/
335 
 
 335 
    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
336 
    /* Enable the Peripheral */
 336 
 
337 
    __HAL_DMA_ENABLE(hdma);
 337 
    /* Enable the Peripheral */
338 
  }
 338 
    __HAL_DMA_ENABLE(hdma);
339 
  else
 339 
  }
340 
  {
 340 
  else
341 
    /* Process Unlocked */
 341 
  {
342 
    __HAL_UNLOCK(hdma);
 342 
    /* Process Unlocked */
343 
    status = HAL_BUSY;
 343 
    __HAL_UNLOCK(hdma);
344 
  }
 344 
    status = HAL_BUSY;
345 
  return status;
 345 
  }
346 
}
 346 
  return status;
347 
 
 347 
}
348 
/**
 348 
 
349 
  * @brief  Start the DMA Transfer with interrupt enabled.
 349 
/**
350 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 350 
  * @brief  Start the DMA Transfer with interrupt enabled.
351 
  *               the configuration information for the specified DMA Channel.
 351 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
352 
  * @param  SrcAddress The source memory Buffer address
 352 
  *               the configuration information for the specified DMA Channel.
353 
  * @param  DstAddress The destination memory Buffer address
 353 
  * @param  SrcAddress The source memory Buffer address
354 
  * @param  DataLength The length of data to be transferred from source to destination
 354 
  * @param  DstAddress The destination memory Buffer address
355 
  * @retval HAL status
 355 
  * @param  DataLength The length of data to be transferred from source to destination
356 
  */
 356 
  * @retval HAL status
357 
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 357 
  */
358 
{
 358 
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
359 
  HAL_StatusTypeDef status = HAL_OK;
 359 
{
360 
 
 360 
  HAL_StatusTypeDef status = HAL_OK;
361 
  /* Check the parameters */
 361 
 
362 
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
 362 
  /* Check the parameters */
363 
 
 363 
  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
364 
  /* Process locked */
 364 
 
365 
  __HAL_LOCK(hdma);
 365 
  /* Process locked */
366 
 
 366 
  __HAL_LOCK(hdma);
367 
  if(HAL_DMA_STATE_READY == hdma->State)
 367 
 
368 
  {
 368 
  if(HAL_DMA_STATE_READY == hdma->State)
369 
    /* Change DMA peripheral state */
 369 
  {
370 
    hdma->State = HAL_DMA_STATE_BUSY;
 370 
    /* Change DMA peripheral state */
371 
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
 371 
    hdma->State = HAL_DMA_STATE_BUSY;
372 
 
 372 
    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
373 
    /* Disable the peripheral */
 373 
 
374 
    __HAL_DMA_DISABLE(hdma);
 374 
    /* Disable the peripheral */
375 
 
 375 
    __HAL_DMA_DISABLE(hdma);
376 
    /* Configure the source, destination address and the data length & clear flags*/
 376 
 
377 
    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
 377 
    /* Configure the source, destination address and the data length & clear flags*/
378 
 
 378 
    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
379 
    /* Enable the transfer complete interrupt */
 379 
 
380 
    /* Enable the transfer Error interrupt */
 380 
    /* Enable the transfer complete interrupt */
381 
    if(NULL != hdma->XferHalfCpltCallback )
 381 
    /* Enable the transfer Error interrupt */
382 
    {
 382 
    if(NULL != hdma->XferHalfCpltCallback )
383 
      /* Enable the Half transfer complete interrupt as well */
 383 
    {
384 
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 384 
      /* Enable the Half transfer complete interrupt as well */
385 
    }
 385 
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
386 
    else
 386 
    }
387 
    {
 387 
    else
388 
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 388 
    {
389 
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
 389 
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
390 
    }
 390 
      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
391 
 
 391 
    }
392 
    /* Enable the Peripheral */
 392 
 
393 
    __HAL_DMA_ENABLE(hdma);
 393 
    /* Enable the Peripheral */
394 
  }
 394 
    __HAL_DMA_ENABLE(hdma);
395 
  else
 395 
  }
396 
  {
 396 
  else
397 
    /* Process Unlocked */
 397 
  {
398 
    __HAL_UNLOCK(hdma);
 398 
    /* Process Unlocked */
399 
 
 399 
    __HAL_UNLOCK(hdma);
400 
    /* Remain BUSY */
 400 
 
401 
    status = HAL_BUSY;
 401 
    /* Remain BUSY */
402 
  }
 402 
    status = HAL_BUSY;
403 
  return status;
 403 
  }
404 
}
 404 
  return status;
405 
 
 405 
}
406 
/**
 406 
 
407 
  * @brief  Abort the DMA Transfer.
 407 
/**
408 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 408 
  * @brief  Abort the DMA Transfer.
409 
  *               the configuration information for the specified DMA Channel.
 409 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
410 
  * @retval HAL status
 410 
  *               the configuration information for the specified DMA Channel.
411 
  */
 411 
  * @retval HAL status
412 
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
 412 
  */
413 
{
 413 
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
414 
  HAL_StatusTypeDef status = HAL_OK;
 414 
{
415 
 
 415 
  HAL_StatusTypeDef status = HAL_OK;
416 
  /* Check the DMA peripheral state */
 416 
 
417 
  if(hdma->State != HAL_DMA_STATE_BUSY)
 417 
  /* Check the DMA peripheral state */
418 
  {
 418 
  if(hdma->State != HAL_DMA_STATE_BUSY)
419 
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 419 
  {
420 
 
 420 
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
421 
    /* Process Unlocked */
 421 
 
422 
    __HAL_UNLOCK(hdma);
 422 
    /* Process Unlocked */
423 
 
 423 
    __HAL_UNLOCK(hdma);
424 
    return HAL_ERROR;
 424 
 
425 
  }
 425 
    return HAL_ERROR;
426 
  else
 426 
  }
427 
  {
 427 
  else
428 
    /* Disable DMA IT */
 428 
  {
429 
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 429 
    /* Disable DMA IT */
430 
 
 430 
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
431 
    /* Disable the channel */
 431 
 
432 
    __HAL_DMA_DISABLE(hdma);
 432 
    /* Disable the channel */
433 
 
 433 
    __HAL_DMA_DISABLE(hdma);
434 
    /* Clear all flags */
 434 
 
435 
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 435 
    /* Clear all flags */
436 
 
 436 
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
437 
    /* Change the DMA state */
 437 
 
438 
    hdma->State = HAL_DMA_STATE_READY;
 438 
    /* Change the DMA state */
439 
 
 439 
    hdma->State = HAL_DMA_STATE_READY;
440 
    /* Process Unlocked */
 440 
 
441 
    __HAL_UNLOCK(hdma);
 441 
    /* Process Unlocked */
442 
 
 442 
    __HAL_UNLOCK(hdma);
443 
    return status;
 443 
 
444 
  }
 444 
    return status;
445 
}
 445 
  }
446 
 
 446 
}
447 
/**
 447 
 
448 
  * @brief  Aborts the DMA Transfer in Interrupt mode.
 448 
/**
449 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 449 
  * @brief  Aborts the DMA Transfer in Interrupt mode.
450 
  *                 the configuration information for the specified DMA Channel.
 450 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
451 
  * @retval HAL status
 451 
  *                 the configuration information for the specified DMA Channel.
452 
  */
 452 
  * @retval HAL status
453 
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
 453 
  */
454 
{
 454 
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
455 
  HAL_StatusTypeDef status = HAL_OK;
 455 
{
456 
 
 456 
  HAL_StatusTypeDef status = HAL_OK;
457 
  if(HAL_DMA_STATE_BUSY != hdma->State)
 457 
 
458 
  {
 458 
  if(HAL_DMA_STATE_BUSY != hdma->State)
459 
    /* no transfer ongoing */
 459 
  {
460 
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 460 
    /* no transfer ongoing */
461 
 
 461 
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
462 
    status = HAL_ERROR;
 462 
 
463 
  }
 463 
    status = HAL_ERROR;
464 
  else
 464 
  }
465 
  {
 465 
  else
466 
    /* Disable DMA IT */
 466 
  {
467 
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 467 
    /* Disable DMA IT */
468 
 
 468 
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
469 
    /* Disable the channel */
 469 
 
470 
    __HAL_DMA_DISABLE(hdma);
 470 
    /* Disable the channel */
471 
 
 471 
    __HAL_DMA_DISABLE(hdma);
472 
    /* Clear all flags */
 472 
 
473 
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 473 
    /* Clear all flags */
474 
 
 474 
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
475 
    /* Change the DMA state */
 475 
 
476 
    hdma->State = HAL_DMA_STATE_READY;
 476 
    /* Change the DMA state */
477 
 
 477 
    hdma->State = HAL_DMA_STATE_READY;
478 
    /* Process Unlocked */
 478 
 
479 
    __HAL_UNLOCK(hdma);
 479 
    /* Process Unlocked */
480 
 
 480 
    __HAL_UNLOCK(hdma);
481 
    /* Call User Abort callback */
 481 
 
482 
    if(hdma->XferAbortCallback != NULL)
 482 
    /* Call User Abort callback */
483 
    {
 483 
    if(hdma->XferAbortCallback != NULL)
484 
      hdma->XferAbortCallback(hdma);
 484 
    {
485 
    }
 485 
      hdma->XferAbortCallback(hdma);
486 
  }
 486 
    }
487 
  return status;
 487 
  }
488 
}
 488 
  return status;
489 
 
 489 
}
490 
/**
 490 
 
491 
  * @brief  Polling for transfer complete.
 491 
/**
492 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 492 
  * @brief  Polling for transfer complete.
493 
  *                  the configuration information for the specified DMA Channel.
 493 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
494 
  * @param  CompleteLevel Specifies the DMA level complete.
 494 
  *                  the configuration information for the specified DMA Channel.
495 
  * @param  Timeout       Timeout duration.
 495 
  * @param  CompleteLevel Specifies the DMA level complete.
496 
  * @retval HAL status
 496 
  * @param  Timeout       Timeout duration.
497 
  */
 497 
  * @retval HAL status
498 
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
 498 
  */
499 
{
 499 
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
500 
  uint32_t temp;
 500 
{
501 
  uint32_t tickstart;
 501 
  uint32_t temp;
502 
 
 502 
  uint32_t tickstart;
503 
  if(HAL_DMA_STATE_BUSY != hdma->State)
 503 
 
504 
  {
 504 
  if(HAL_DMA_STATE_BUSY != hdma->State)
505 
    /* no transfer ongoing */
 505 
  {
506 
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
 506 
    /* no transfer ongoing */
507 
    __HAL_UNLOCK(hdma);
 507 
    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
508 
    return HAL_ERROR;
 508 
    __HAL_UNLOCK(hdma);
509 
  }
 509 
    return HAL_ERROR;
510 
 
 510 
  }
511 
  /* Polling mode not supported in circular mode */
 511 
 
512 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
 512 
  /* Polling mode not supported in circular mode */
513 
  {
 513 
  if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
514 
    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
 514 
  {
515 
    return HAL_ERROR;
 515 
    hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
516 
  }
 516 
    return HAL_ERROR;
517 
 
 517 
  }
518 
  /* Get the level transfer complete flag */
 518 
 
519 
  if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
 519 
  /* Get the level transfer complete flag */
520 
  {
 520 
  if (HAL_DMA_FULL_TRANSFER == CompleteLevel)
521 
    /* Transfer Complete flag */
 521 
  {
522 
    temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);
 522 
    /* Transfer Complete flag */
523 
  }
 523 
    temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);
524 
  else
 524 
  }
525 
  {
 525 
  else
526 
    /* Half Transfer Complete flag */
 526 
  {
527 
    temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);
 527 
    /* Half Transfer Complete flag */
528 
  }
 528 
    temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);
529 
 
 529 
  }
530 
  /* Get tick */
 530 
 
531 
  tickstart = HAL_GetTick();
 531 
  /* Get tick */
532 
 
 532 
  tickstart = HAL_GetTick();
533 
  while((hdma->DmaBaseAddress->ISR & temp) == 0U)
 533 
 
534 
  {
 534 
  while((hdma->DmaBaseAddress->ISR & temp) == 0U)
535 
    if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)
 535 
  {
536 
    {
 536 
    if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)
537 
      /* When a DMA transfer error occurs */
 537 
    {
538 
      /* A hardware clear of its EN bits is performed */
 538 
      /* When a DMA transfer error occurs */
539 
      /* Clear all flags */
 539 
      /* A hardware clear of its EN bits is performed */
540 
      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 540 
      /* Clear all flags */
541 
 
 541 
      hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
542 
      /* Update error code */
 542 
 
543 
      hdma->ErrorCode = HAL_DMA_ERROR_TE;
 543 
      /* Update error code */
544 
 
 544 
      hdma->ErrorCode = HAL_DMA_ERROR_TE;
545 
      /* Change the DMA state */
 545 
 
546 
      hdma->State= HAL_DMA_STATE_READY;
 546 
      /* Change the DMA state */
547 
 
 547 
      hdma->State= HAL_DMA_STATE_READY;
548 
      /* Process Unlocked */
 548 
 
549 
      __HAL_UNLOCK(hdma);
 549 
      /* Process Unlocked */
550 
 
 550 
      __HAL_UNLOCK(hdma);
551 
      return HAL_ERROR;
 551 
 
552 
    }
 552 
      return HAL_ERROR;
553 
    /* Check for the Timeout */
 553 
    }
554 
    if(Timeout != HAL_MAX_DELAY)
 554 
    /* Check for the Timeout */
555 
    {
 555 
    if(Timeout != HAL_MAX_DELAY)
556 
      if(((HAL_GetTick() - tickstart) > Timeout) ||  (Timeout == 0U))
 556 
    {
557 
      {
 557 
      if(((HAL_GetTick() - tickstart) > Timeout) ||  (Timeout == 0U))
558 
        /* Update error code */
 558 
      {
559 
        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
 559 
        /* Update error code */
560 
 
 560 
        hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
561 
        /* Change the DMA state */
 561 
 
562 
        hdma->State = HAL_DMA_STATE_READY;
 562 
        /* Change the DMA state */
563 
 
 563 
        hdma->State = HAL_DMA_STATE_READY;
564 
        /* Process Unlocked */
 564 
 
565 
        __HAL_UNLOCK(hdma);
 565 
        /* Process Unlocked */
566 
 
 566 
        __HAL_UNLOCK(hdma);
567 
        return HAL_ERROR;
 567 
 
568 
      }
 568 
        return HAL_ERROR;
569 
    }
 569 
      }
570 
  }
 570 
    }
571 
 
 571 
  }
572 
  if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
 572 
 
573 
  {
 573 
  if(HAL_DMA_FULL_TRANSFER == CompleteLevel)
574 
    /* Clear the transfer complete flag */
 574 
  {
575 
    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));
 575 
    /* Clear the transfer complete flag */
576 
 
 576 
    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1CU));
577 
    /* The selected Channelx EN bit is cleared (DMA is disabled and
 577 
 
578 
    all transfers are complete) */
 578 
    /* The selected Channelx EN bit is cleared (DMA is disabled and
579 
    hdma->State = HAL_DMA_STATE_READY;
 579 
    all transfers are complete) */
580 
  }
 580 
    hdma->State = HAL_DMA_STATE_READY;
581 
  else
 581 
  }
582 
  {
 582 
  else
583 
    /* Clear the half transfer complete flag */
 583 
  {
584 
    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
 584 
    /* Clear the half transfer complete flag */
585 
  }
 585 
    hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
586 
 
 586 
  }
587 
  /* Process unlocked */
 587 
 
588 
  __HAL_UNLOCK(hdma);
 588 
  /* Process unlocked */
589 
 
 589 
  __HAL_UNLOCK(hdma);
590 
  return HAL_OK;
 590 
 
591 
}
 591 
  return HAL_OK;
592 
 
 592 
}
593 
/**
 593 
 
594 
  * @brief  Handle DMA interrupt request.
 594 
/**
595 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 595 
  * @brief  Handle DMA interrupt request.
596 
  *               the configuration information for the specified DMA Channel.
 596 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
597 
  * @retval None
 597 
  *               the configuration information for the specified DMA Channel.
598 
  */
 598 
  * @retval None
599 
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
 599 
  */
600 
{
 600 
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
601 
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
 601 
{
602 
  uint32_t source_it = hdma->Instance->CCR;
 602 
  uint32_t flag_it = hdma->DmaBaseAddress->ISR;
603 
 
 603 
  uint32_t source_it = hdma->Instance->CCR;
604 
  /* Half Transfer Complete Interrupt management ******************************/
 604 
 
605 
  if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
 605 
  /* Half Transfer Complete Interrupt management ******************************/
606 
  {
 606 
  if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
607 
    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
 607 
  {
608 
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 608 
    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
609 
    {
 609 
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
610 
      /* Disable the half transfer interrupt */
 610 
    {
611 
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
 611 
      /* Disable the half transfer interrupt */
612 
    }
 612 
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
613 
    /* Clear the half transfer complete flag */
 613 
    }
614 
    hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
 614 
    /* Clear the half transfer complete flag */
615 
 
 615 
    hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
616 
    /* DMA peripheral state is not updated in Half Transfer */
 616 
 
617 
    /* but in Transfer Complete case */
 617 
    /* DMA peripheral state is not updated in Half Transfer */
618 
 
 618 
    /* but in Transfer Complete case */
619 
    if(hdma->XferHalfCpltCallback != NULL)
 619 
 
620 
    {
 620 
    if(hdma->XferHalfCpltCallback != NULL)
621 
      /* Half transfer callback */
 621 
    {
622 
      hdma->XferHalfCpltCallback(hdma);
 622 
      /* Half transfer callback */
623 
    }
 623 
      hdma->XferHalfCpltCallback(hdma);
624 
  }
 624 
    }
625 
 
 625 
  }
626 
  /* Transfer Complete Interrupt management ***********************************/
 626 
 
627 
  else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
 627 
  /* Transfer Complete Interrupt management ***********************************/
628 
  {
 628 
  else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
629 
   
 629 
  {
630 
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
 630 
   
631 
    {
 631 
    if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
632 
      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
 632 
    {
633 
      /* Disable the transfer complete and error interrupt */
 633 
      /* Disable the transfer complete interrupt if the DMA mode is not CIRCULAR */
634 
      /* if the DMA mode is not CIRCULAR  */
 634 
      /* Disable the transfer complete and error interrupt */
635 
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
 635 
      /* if the DMA mode is not CIRCULAR  */
636 
 
 636 
      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
637 
      /* Change the DMA state */
 637 
 
638 
      hdma->State = HAL_DMA_STATE_READY;
 638 
      /* Change the DMA state */
639 
    }
 639 
      hdma->State = HAL_DMA_STATE_READY;
640 
    /* Clear the transfer complete flag */
 640 
    }
641 
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU));
 641 
    /* Clear the transfer complete flag */
642 
 
 642 
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1CU));
643 
    /* Process Unlocked */
 643 
 
644 
    __HAL_UNLOCK(hdma);
 644 
    /* Process Unlocked */
645 
 
 645 
    __HAL_UNLOCK(hdma);
646 
    if(hdma->XferCpltCallback != NULL)
 646 
 
647 
    {
 647 
    if(hdma->XferCpltCallback != NULL)
648 
      /* Transfer complete callback */
 648 
    {
649 
      hdma->XferCpltCallback(hdma);
 649 
      /* Transfer complete callback */
650 
    }
 650 
      hdma->XferCpltCallback(hdma);
651 
  }
 651 
    }
652 
 
 652 
  }
653 
  /* Transfer Error Interrupt management **************************************/
 653 
 
654 
  else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) !=  0U))
 654 
  /* Transfer Error Interrupt management **************************************/
655 
  {
 655 
  else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) !=  0U))
656 
    /* When a DMA transfer error occurs */
 656 
  {
657 
    /* A hardware clear of its EN bits is performed */
 657 
    /* When a DMA transfer error occurs */
658 
    /* Disable ALL DMA IT */
 658 
    /* A hardware clear of its EN bits is performed */
659 
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
 659 
    /* Disable ALL DMA IT */
660 
 
 660 
    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
661 
    /* Clear all flags */
 661 
 
662 
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 662 
    /* Clear all flags */
663 
 
 663 
    hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
664 
    /* Update error code */
 664 
 
665 
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
 665 
    /* Update error code */
666 
 
 666 
    hdma->ErrorCode = HAL_DMA_ERROR_TE;
667 
    /* Change the DMA state */
 667 
 
668 
    hdma->State = HAL_DMA_STATE_READY;
 668 
    /* Change the DMA state */
669 
 
 669 
    hdma->State = HAL_DMA_STATE_READY;
670 
    /* Process Unlocked */
 670 
 
671 
    __HAL_UNLOCK(hdma);
 671 
    /* Process Unlocked */
672 
 
 672 
    __HAL_UNLOCK(hdma);
673 
    if (hdma->XferErrorCallback != NULL)
 673 
 
674 
    {
 674 
    if (hdma->XferErrorCallback != NULL)
675 
      /* Transfer error callback */
 675 
    {
676 
      hdma->XferErrorCallback(hdma);
 676 
      /* Transfer error callback */
677 
    }
 677 
      hdma->XferErrorCallback(hdma);
678 
  }
 678 
    }
679 
  else
 679 
  }
680 
  {
 680 
  else
681 
    /* Nothing To Do */
 681 
  {
682 
  }
 682 
    /* Nothing To Do */
683 
  return;
 683 
  }
684 
}
 684 
  return;
685 
 
 685 
}
686 
/**
 686 
 
687 
  * @brief  Register callbacks
 687 
/**
688 
  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
 688 
  * @brief  Register callbacks
689 
  *                               the configuration information for the specified DMA Channel.
 689 
  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
690 
  * @param  CallbackID           User Callback identifer
 690 
  *                               the configuration information for the specified DMA Channel.
691 
  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
 691 
  * @param  CallbackID           User Callback identifier
692 
  * @param  pCallback            pointer to private callbacsk function which has pointer to
 692 
  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
693 
  *                               a DMA_HandleTypeDef structure as parameter.
 693 
  * @param  pCallback            pointer to private callback function which has pointer to
694 
  * @retval HAL status
 694 
  *                               a DMA_HandleTypeDef structure as parameter.
695 
  */
 695 
  * @retval HAL status
696 
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
 696 
  */
697 
{
 697 
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma))
698 
  HAL_StatusTypeDef status = HAL_OK;
 698 
{
699 
 
 699 
  HAL_StatusTypeDef status = HAL_OK;
700 
  /* Process locked */
 700 
 
701 
  __HAL_LOCK(hdma);
 701 
  /* Process locked */
702 
 
 702 
  __HAL_LOCK(hdma);
703 
  if(HAL_DMA_STATE_READY == hdma->State)
 703 
 
704 
  {
 704 
  if(HAL_DMA_STATE_READY == hdma->State)
705 
    switch (CallbackID)
 705 
  {
706 
    {
 706 
    switch (CallbackID)
707 
     case  HAL_DMA_XFER_CPLT_CB_ID:
 707 
    {
708 
           hdma->XferCpltCallback = pCallback;
 708 
     case  HAL_DMA_XFER_CPLT_CB_ID:
709 
           break;
 709 
           hdma->XferCpltCallback = pCallback;
710 
 
 710 
           break;
711 
     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
 711 
 
712 
           hdma->XferHalfCpltCallback = pCallback;
 712 
     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
713 
           break;
 713 
           hdma->XferHalfCpltCallback = pCallback;
714 
 
 714 
           break;
715 
     case  HAL_DMA_XFER_ERROR_CB_ID:
 715 
 
716 
           hdma->XferErrorCallback = pCallback;
 716 
     case  HAL_DMA_XFER_ERROR_CB_ID:
717 
           break;
 717 
           hdma->XferErrorCallback = pCallback;
718 
 
 718 
           break;
719 
     case  HAL_DMA_XFER_ABORT_CB_ID:
 719 
 
720 
           hdma->XferAbortCallback = pCallback;
 720 
     case  HAL_DMA_XFER_ABORT_CB_ID:
721 
           break;
 721 
           hdma->XferAbortCallback = pCallback;
722 
 
 722 
           break;
723 
     default:
 723 
 
724 
           status = HAL_ERROR;
 724 
     default:
725 
           break;
 725 
           status = HAL_ERROR;
726 
    }
 726 
           break;
727 
  }
 727 
    }
728 
  else
 728 
  }
729 
  {
 729 
  else
730 
    status = HAL_ERROR;
 730 
  {
731 
  }
 731 
    status = HAL_ERROR;
732 
 
 732 
  }
733 
  /* Release Lock */
 733 
 
734 
  __HAL_UNLOCK(hdma);
 734 
  /* Release Lock */
735 
 
 735 
  __HAL_UNLOCK(hdma);
736 
  return status;
 736 
 
737 
}
 737 
  return status;
738 
 
 738 
}
739 
/**
 739 
 
740 
  * @brief  UnRegister callbacks
 740 
/**
741 
  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
 741 
  * @brief  UnRegister callbacks
742 
  *                               the configuration information for the specified DMA Channel.
 742 
  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
743 
  * @param  CallbackID           User Callback identifer
 743 
  *                               the configuration information for the specified DMA Channel.
744 
  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
 744 
  * @param  CallbackID           User Callback identifier
745 
  * @retval HAL status
 745 
  *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
746 
  */
 746 
  * @retval HAL status
747 
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
 747 
  */
748 
{
 748 
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID)
749 
  HAL_StatusTypeDef status = HAL_OK;
 749 
{
750 
 
 750 
  HAL_StatusTypeDef status = HAL_OK;
751 
    /* Process locked */
 751 
 
752 
  __HAL_LOCK(hdma);
 752 
    /* Process locked */
753 
 
 753 
  __HAL_LOCK(hdma);
754 
  if(HAL_DMA_STATE_READY == hdma->State)
 754 
 
755 
  {
 755 
  if(HAL_DMA_STATE_READY == hdma->State)
756 
    switch (CallbackID)
 756 
  {
757 
    {
 757 
    switch (CallbackID)
758 
     case  HAL_DMA_XFER_CPLT_CB_ID:
 758 
    {
759 
           hdma->XferCpltCallback = NULL;
 759 
     case  HAL_DMA_XFER_CPLT_CB_ID:
760 
           break;
 760 
           hdma->XferCpltCallback = NULL;
761 
 
 761 
           break;
762 
     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
 762 
 
763 
           hdma->XferHalfCpltCallback = NULL;
 763 
     case  HAL_DMA_XFER_HALFCPLT_CB_ID:
764 
           break;
 764 
           hdma->XferHalfCpltCallback = NULL;
765 
 
 765 
           break;
766 
     case  HAL_DMA_XFER_ERROR_CB_ID:
 766 
 
767 
           hdma->XferErrorCallback = NULL;
 767 
     case  HAL_DMA_XFER_ERROR_CB_ID:
768 
           break;
 768 
           hdma->XferErrorCallback = NULL;
769 
 
 769 
           break;
770 
     case  HAL_DMA_XFER_ABORT_CB_ID:
 770 
 
771 
           hdma->XferAbortCallback = NULL;
 771 
     case  HAL_DMA_XFER_ABORT_CB_ID:
772 
           break;
 772 
           hdma->XferAbortCallback = NULL;
773 
 
 773 
           break;
774 
    case   HAL_DMA_XFER_ALL_CB_ID:
 774 
 
775 
           hdma->XferCpltCallback = NULL;
 775 
    case   HAL_DMA_XFER_ALL_CB_ID:
776 
           hdma->XferHalfCpltCallback = NULL;
 776 
           hdma->XferCpltCallback = NULL;
777 
           hdma->XferErrorCallback = NULL;
 777 
           hdma->XferHalfCpltCallback = NULL;
778 
           hdma->XferAbortCallback = NULL;
 778 
           hdma->XferErrorCallback = NULL;
779 
           break;
 779 
           hdma->XferAbortCallback = NULL;
780 
 
 780 
           break;
781 
    default:
 781 
 
782 
           status = HAL_ERROR;
 782 
    default:
783 
           break;
 783 
           status = HAL_ERROR;
784 
    }
 784 
           break;
785 
  }
 785 
    }
786 
  else
 786 
  }
787 
  {
 787 
  else
788 
    status = HAL_ERROR;
 788 
  {
789 
  }
 789 
    status = HAL_ERROR;
790 
 
 790 
  }
791 
  /* Release Lock */
 791 
 
792 
  __HAL_UNLOCK(hdma);
 792 
  /* Release Lock */
793 
 
 793 
  __HAL_UNLOCK(hdma);
794 
  return status;
 794 
 
795 
}
 795 
  return status;
796 
 
 796 
}
797 
/**
 797 
 
798 
  * @}
 798 
/**
799 
  */
 799 
  * @}
800 
 
 800 
  */
801 
 
 801 
 
802 
 
 802 
 
803 
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
 803 
 
804 
 *  @brief    Peripheral State and Errors functions
 804 
/** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions
805 
 *
 805 
 *  @brief    Peripheral State and Errors functions
806 
@verbatim
 806 
 *
807 
 ===============================================================================
 807 
@verbatim
808 
            ##### Peripheral State and Errors functions #####
 808 
 ===============================================================================
809 
 ===============================================================================
 809 
            ##### Peripheral State and Errors functions #####
810 
    [..]
 810 
 ===============================================================================
811 
    This subsection provides functions allowing to
 811 
    [..]
812 
      (+) Check the DMA state
 812 
    This subsection provides functions allowing to
813 
      (+) Get error code
 813 
      (+) Check the DMA state
814 
 
 814 
      (+) Get error code
815 
@endverbatim
 815 
 
816 
  * @{
 816 
@endverbatim
817 
  */
 817 
  * @{
818 
 
 818 
  */
819 
/**
 819 
 
820 
  * @brief  Return the DMA handle state.
 820 
/**
821 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 821 
  * @brief  Return the DMA handle state.
822 
  *               the configuration information for the specified DMA Channel.
 822 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
823 
  * @retval HAL state
 823 
  *               the configuration information for the specified DMA Channel.
824 
  */
 824 
  * @retval HAL state
825 
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
 825 
  */
826 
{
 826 
HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
827 
  /* Return DMA handle state */
 827 
{
828 
  return hdma->State;
 828 
  /* Return DMA handle state */
829 
}
 829 
  return hdma->State;
830 
 
 830 
}
831 
/**
 831 
 
832 
  * @brief  Return the DMA error code.
 832 
/**
833 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
 833 
  * @brief  Return the DMA error code.
834 
  *              the configuration information for the specified DMA Channel.
 834 
  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
835 
  * @retval DMA Error Code
 835 
  *              the configuration information for the specified DMA Channel.
836 
  */
 836 
  * @retval DMA Error Code
837 
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
 837 
  */
838 
{
 838 
uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
839 
  return hdma->ErrorCode;
 839 
{
840 
}
 840 
  return hdma->ErrorCode;
841 
 
 841 
}
842 
/**
 842 
 
843 
  * @}
 843 
/**
844 
  */
 844 
  * @}
845 
 
 845 
  */
846 
/**
 846 
 
847 
  * @}
 847 
/**
848 
  */
 848 
  * @}
849 
 
 849 
  */
850 
/** @addtogroup DMA_Private_Functions
 850 
 
851 
  * @{
 851 
/** @addtogroup DMA_Private_Functions
852 
  */
 852 
  * @{
853 
 
 853 
  */
854 
/**
 854 
 
855 
  * @brief  Sets the DMA Transfer parameter.
 855 
/**
856 
  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
 856 
  * @brief  Sets the DMA Transfer parameter.
857 
  *                     the configuration information for the specified DMA Channel.
 857 
  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
858 
  * @param  SrcAddress The source memory Buffer address
 858 
  *                     the configuration information for the specified DMA Channel.
859 
  * @param  DstAddress The destination memory Buffer address
 859 
  * @param  SrcAddress The source memory Buffer address
860 
  * @param  DataLength The length of data to be transferred from source to destination
 860 
  * @param  DstAddress The destination memory Buffer address
861 
  * @retval HAL status
 861 
  * @param  DataLength The length of data to be transferred from source to destination
862 
  */
 862 
  * @retval HAL status
863 
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 863 
  */
864 
{
 864 
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
865 
  /* Clear all flags */
 865 
{
866 
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
 866 
  /* Clear all flags */
867 
 
 867 
  hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
868 
  /* Configure DMA Channel data length */
 868 
 
869 
  hdma->Instance->CNDTR = DataLength;
 869 
  /* Configure DMA Channel data length */
870 
 
 870 
  hdma->Instance->CNDTR = DataLength;
871 
  /* Memory to Peripheral */
 871 
 
872 
  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
 872 
  /* Memory to Peripheral */
873 
  {
 873 
  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
874 
    /* Configure DMA Channel destination address */
 874 
  {
875 
    hdma->Instance->CPAR = DstAddress;
 875 
    /* Configure DMA Channel destination address */
876 
 
 876 
    hdma->Instance->CPAR = DstAddress;
877 
    /* Configure DMA Channel source address */
 877 
 
878 
    hdma->Instance->CMAR = SrcAddress;
 878 
    /* Configure DMA Channel source address */
879 
  }
 879 
    hdma->Instance->CMAR = SrcAddress;
880 
  /* Peripheral to Memory */
 880 
  }
881 
  else
 881 
  /* Peripheral to Memory */
882 
  {
 882 
  else
883 
    /* Configure DMA Channel source address */
 883 
  {
884 
    hdma->Instance->CPAR = SrcAddress;
 884 
    /* Configure DMA Channel source address */
885 
 
 885 
    hdma->Instance->CPAR = SrcAddress;
886 
    /* Configure DMA Channel destination address */
 886 
 
887 
    hdma->Instance->CMAR = DstAddress;
 887 
    /* Configure DMA Channel destination address */
888 
  }
 888 
    hdma->Instance->CMAR = DstAddress;
889 
}
 889 
  }
890 
 
 890 
}
891 
/**
 891 
 
892 
  * @}
 892 
/**
893 
  */
 893 
  * @}
894 
 
 894 
  */
895 
/**
 895 
 
896 
  * @}
 896 
/**
897 
  */
 897 
  * @}
898 
 
 898 
  */
899 
#endif /* HAL_DMA_MODULE_ENABLED */
 899 
 
900 
/**
 900 
#endif /* HAL_DMA_MODULE_ENABLED */
901 
  * @}
 901 
/**
902 
  */
 902 
  * @}
903 
 
 903 
  */
904 
/**
 904 
 
905 
  * @}
 905 
/**
906 
  */
 906 
  * @}
907 
 
 907 
  */
908 
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
 908 
 
- 
 
 909