WebSVN – DashDisplay – Diff – /branches/Dashboard_L152_v2/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac.c



      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
      [..]
      (@) Refer to the device datasheet for more details about output
          impedance value with and without output buffer.
 
 
 
 
 
 
 
 
      *** GPIO configurations guidelines ***
      =====================
      [..]
      When a DAC channel is used (ex channel1 on PA4) and the other is not
      (ex channel2 on PA5 is configured in Analog and disabled).

       by the following equation:
       [..]
       DAC_OUTx = VREF+ * DOR / 4095
       (+) with  DOR is the Data Output Register
       [..]
          VREF+ is the input voltage reference (refer to the device datasheet)
       [..]
        e.g. To set DAC_OUT1 to 0.7V, use
       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
 
       *** DMA requests ***
       =====================
       [..]
       A DMA request can be generated when an external trigger (but not a software trigger)
       occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
       DMA1 requests are mapped as following:
      (#) DAC channel1 mapped on (no request on STM32L1XX) / DMA1 channel2
      (#) DAC channel2 mapped on (no request on STM32L1XX) / DMA1 channel3
 
     [..]
    (@) For Dual mode and specific signal (Triangle and noise) generation please
        refer to Extended Features Driver description
 

 
      When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
      not defined, the callback registering feature is not available
      and weak (surcharged) callbacks are used.
 
 
 
     *** DAC HAL driver macros list ***
     =============================================
     [..]
       Below the list of most used macros in DAC HAL driver.
 

      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
 
     [..]
      (@) You can refer to the DAC HAL driver header file for more useful macros
 
@endverbatim
  ******************************************************************************
  * @attention
  *
  * <h2><center>&copy; Copyright (c) 2016 STMicroelectronics.
  * All rights reserved.</center></h2>

    {
      /* Enable the selected DAC software conversion */
      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
    }
  }
 
  else
  {
    /* Check if software trigger enabled */
    if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
    {
      /* Enable the selected DAC software conversion*/
      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
    }
  }
 
 
  /* Change DAC state */
  hdac->State = HAL_DAC_STATE_READY;
 
  /* Process unlocked */
  __HAL_UNLOCK(hdac);

  *         the configuration information for the specified DAC.
  * @param  Channel The selected DAC channel.
  *          This parameter can be one of the following values:
  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
  * @param  pData The source Buffer address.
  * @param  Length The length of data to be transferred from memory to DAC peripheral
  * @param  Alignment Specifies the data alignment for DAC channel.
  *          This parameter can be one of the following values:
  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected

        break;
      default:
        break;
    }
  }
 
  else
  {
    /* Set the DMA transfer complete callback for channel2 */
    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
 

      default:
        break;
    }
  }
 
 
  /* Enable the DMA channel */
  if (Channel == DAC_CHANNEL_1)
  {
    /* Enable the DAC DMA underrun interrupt */
    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
 
    /* Enable the DMA channel */
    status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
  }
 
  else
  {
    /* Enable the DAC DMA underrun interrupt */
    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
 
    /* Enable the DMA channel */
    status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
  }
 
 
  /* Process Unlocked */
  __HAL_UNLOCK(hdac);
 
  if (status == HAL_OK)
  {

  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
 
 
  /* Check the parameters */
  assert_param(IS_DAC_CHANNEL(Channel));
 
  /* Disable the selected DAC channel DMA request */
  hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));

 
  /* Channel1 is used */
  if (Channel == DAC_CHANNEL_1)
  {
    /* Disable the DMA channel */
    (void)HAL_DMA_Abort(hdac->DMA_Handle1);
 
    /* Disable the DAC DMA underrun interrupt */
    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
  }
 
  else /* Channel2 is used for */
  {
    /* Disable the DMA channel */
    (void)HAL_DMA_Abort(hdac->DMA_Handle2);
 
    /* Disable the DAC DMA underrun interrupt */
    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
  }
 
 
 
 
 
 
 
 
 
  /* Change DAC state */
  hdac->State = HAL_DAC_STATE_READY;
 
 
  /* Return function status */
  return HAL_OK;
}
 
/**
  * @brief  Handles DAC interrupt request
  *         This function uses the interruption of DMA

    if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
    {
      /* Change DAC state to error state */
      hdac->State = HAL_DAC_STATE_ERROR;
 
      /* Set DAC error code to channel1 DMA underrun error */
      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
 
      /* Clear the underrun flag */
      __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
 

      HAL_DAC_DMAUnderrunCallbackCh1(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
    }
  }
 
 
  if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
  {
    /* Check underrun flag of DAC channel 2 */
    if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
    {

#else
      HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
    }
  }
 
}
 
/**
  * @brief  Set the specified data holding register value for DAC channel.
  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains

  * @param  Data Data to be loaded in the selected data holding register.
  * @retval HAL status
  */
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
  __IO uint32_t tmp = 0UL;
 
  /* Check the parameters */
  assert_param(IS_DAC_CHANNEL(Channel));
  assert_param(IS_DAC_ALIGN(Alignment));
  assert_param(IS_DAC_DATA(Data));

  tmp = (uint32_t)hdac->Instance;
  if (Channel == DAC_CHANNEL_1)
  {
    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
  }
 
  else
  {
    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
  }
 
 
  /* Set the DAC channel selected data holding register */
  *(__IO uint32_t *) tmp = Data;
 
  /* Return function status */
  return HAL_OK;

  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
  * @retval The selected DAC channel data output value.
  */
uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
  uint32_t result;
 
  /* Check the parameters */
  assert_param(IS_DAC_CHANNEL(Channel));
 
 
  if (Channel == DAC_CHANNEL_1)
  {
    result = hdac->Instance->DOR1;
  }
 
  else
  {
    result = hdac->Instance->DOR2;
  }
 
  /* Returns the DAC channel data output register value */
  return result;
}
 
/**
  * @brief  Configures the selected DAC channel.
  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains

  hdac->State = HAL_DAC_STATE_BUSY;
 
  /* Get the DAC CR value */
  tmpreg1 = hdac->Instance->CR;
  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << (Channel & 0x10UL));
  /* Configure for the selected DAC channel: buffer output, trigger */
  /* Set TSELx and TENx bits according to DAC_Trigger value */
  /* Set BOFFx bit according to DAC_OutputBuffer value */
  tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
  /* Calculate CR register value depending on DAC_Channel */
  tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
  /* Write to DAC CR */
  hdac->Instance->CR = tmpreg1;
  /* Disable wave generation */
  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
 
 
 
  /* Change DAC state */
  hdac->State = HAL_DAC_STATE_READY;
 
  /* Process unlocked */

        hdac->ErrorCallbackCh1 = pCallback;
        break;
      case HAL_DAC_CH1_UNDERRUN_CB_ID :
        hdac->DMAUnderrunCallbackCh1 = pCallback;
        break;
 
      case HAL_DAC_CH2_COMPLETE_CB_ID :
        hdac->ConvCpltCallbackCh2 = pCallback;
        break;
      case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
        hdac->ConvHalfCpltCallbackCh2 = pCallback;

        hdac->ErrorCallbackCh2 = pCallback;
        break;
      case HAL_DAC_CH2_UNDERRUN_CB_ID :
        hdac->DMAUnderrunCallbackCh2 = pCallback;
        break;
 
      case HAL_DAC_MSPINIT_CB_ID :
        hdac->MspInitCallback = pCallback;
        break;
      case HAL_DAC_MSPDEINIT_CB_ID :
        hdac->MspDeInitCallback = pCallback;

  * @brief  Unregister a User DAC Callback
  *         DAC Callback is redirected to the weak (surcharged) predefined callback
  * @param  hdac DAC handle
  * @param  CallbackID ID of the callback to be unregistered
  *         This parameter can be one of the following values:
  *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID          DAC CH1 transfer Complete Callback ID
  *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID     DAC CH1 Half Complete Callback ID
  *          @arg @ref HAL_DAC_CH1_ERROR_ID                DAC CH1 Error Callback ID
  *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID          DAC CH1 UnderRun Callback ID
  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID          DAC CH2 Complete Callback ID
  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID     DAC CH2 Half Complete Callback ID

        hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
        break;
      case HAL_DAC_CH1_UNDERRUN_CB_ID :
        hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
        break;
 
      case HAL_DAC_CH2_COMPLETE_CB_ID :
        hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
        break;
      case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
        hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;

        hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
        break;
      case HAL_DAC_CH2_UNDERRUN_CB_ID :
        hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
        break;
 
      case HAL_DAC_MSPINIT_CB_ID :
        hdac->MspInitCallback = HAL_DAC_MspInit;
        break;
      case HAL_DAC_MSPDEINIT_CB_ID :
        hdac->MspDeInitCallback = HAL_DAC_MspDeInit;

      case HAL_DAC_ALL_CB_ID :
        hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
        hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
        hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
        hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
 
        hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
        hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
        hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
        hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
 
        hdac->MspInitCallback = HAL_DAC_MspInit;
        hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
        break;
      default :
        /* Update the error code */

Rev 56	Rev 61
Line 53...	Line 53...
53	sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;	53	sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
54	[..]	54	[..]
55	(@) Refer to the device datasheet for more details about output	55	(@) Refer to the device datasheet for more details about output
56	impedance value with and without output buffer.	56	impedance value with and without output buffer.
57		57
58	* DAC connect feature *	-
59	===============================	-
60	[..]	-
61	Each DAC channel can be connected internally.	-
62	To connect, use	-
63	sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE;	-
64		-
65	* GPIO configurations guidelines *	58	* GPIO configurations guidelines *
66	=====================	59	=====================
67	[..]	60	[..]
68	When a DAC channel is used (ex channel1 on PA4) and the other is not	61	When a DAC channel is used (ex channel1 on PA4) and the other is not
69	(ex channel2 on PA5 is configured in Analog and disabled).	62	(ex channel2 on PA5 is configured in Analog and disabled).
Line 95...	Line 88...
95	by the following equation:	88	by the following equation:
96	[..]	89	[..]
97	DAC_OUTx = VREF+ * DOR / 4095	90	DAC_OUTx = VREF+ * DOR / 4095
98	(+) with DOR is the Data Output Register	91	(+) with DOR is the Data Output Register
99	[..]	92	[..]
100	VEF+ is the input voltage reference (refer to the device datasheet)	93	VREF+ is the input voltage reference (refer to the device datasheet)
101	[..]	94	[..]
102	e.g. To set DAC_OUT1 to 0.7V, use	95	e.g. To set DAC_OUT1 to 0.7V, use
103	(+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V	96	(+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
104		97
105	* DMA requests *	98	* DMA requests *
106	=====================	99	=====================
107	[..]	100	[..]
108	A DMA1 request can be generated when an external trigger (but not a software trigger)	101	A DMA request can be generated when an external trigger (but not a software trigger)
109	occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().	102	occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA().
110	DMA1 requests are mapped as following:	103	DMA1 requests are mapped as following:
111	(#) DAC channel1 mapped on DMA1 channel2	104	(#) DAC channel1 mapped on (no request on STM32L1XX) / DMA1 channel2
112	(#) DAC channel2 mapped on DMA1 channel3	105	(#) DAC channel2 mapped on (no request on STM32L1XX) / DMA1 channel3
113		106
114	[..]	107	[..]
115	(@) For Dual mode and specific signal (Triangle and noise) generation please	108	(@) For Dual mode and specific signal (Triangle and noise) generation please
116	refer to Extended Features Driver description	109	refer to Extended Features Driver description
117		110
Line 207...	Line 200...
207		200
208	When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or	201	When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
209	not defined, the callback registering feature is not available	202	not defined, the callback registering feature is not available
210	and weak (surcharged) callbacks are used.	203	and weak (surcharged) callbacks are used.
211		204
212		-
213		-
214	* DAC HAL driver macros list *	205	* DAC HAL driver macros list *
215	=============================================	206	=============================================
216	[..]	207	[..]
217	Below the list of most used macros in DAC HAL driver.	208	Below the list of most used macros in DAC HAL driver.
218		209
Line 222...	Line 213...
222	(+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status	213	(+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
223		214
224	[..]	215	[..]
225	(@) You can refer to the DAC HAL driver header file for more useful macros	216	(@) You can refer to the DAC HAL driver header file for more useful macros
226		217
227	@endverbatim	218	@endverbatim
228	******************************************************************************	219	******************************************************************************
229	* @attention	220	* @attention
230	*	221	*
231	* <h2><center>© Copyright (c) 2016 STMicroelectronics.	222	* <h2><center>© Copyright (c) 2016 STMicroelectronics.
232	* All rights reserved.</center></h2>	223	* All rights reserved.</center></h2>
Line 473...	Line 464...
473	{	464	{
474	/* Enable the selected DAC software conversion */	465	/* Enable the selected DAC software conversion */
475	SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);	466	SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
476	}	467	}
477	}	468	}
-		469
478	else	470	else
479	{	471	{
480	/* Check if software trigger enabled */	472	/* Check if software trigger enabled */
481	if ((hdac->Instance->CR & (DAC_CR_TEN2 \| DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << Channel))	473	if ((hdac->Instance->CR & (DAC_CR_TEN2 \| DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
482	{	474	{
483	/* Enable the selected DAC software conversion*/	475	/* Enable the selected DAC software conversion*/
484	SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);	476	SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
485	}	477	}
486	}	478	}
487		479
-		480
488	/* Change DAC state */	481	/* Change DAC state */
489	hdac->State = HAL_DAC_STATE_READY;	482	hdac->State = HAL_DAC_STATE_READY;
490		483
491	/* Process unlocked */	484	/* Process unlocked */
492	__HAL_UNLOCK(hdac);	485	__HAL_UNLOCK(hdac);
Line 526...	Line 519...
526	* the configuration information for the specified DAC.	519	* the configuration information for the specified DAC.
527	* @param Channel The selected DAC channel.	520	* @param Channel The selected DAC channel.
528	* This parameter can be one of the following values:	521	* This parameter can be one of the following values:
529	* @arg DAC_CHANNEL_1: DAC Channel1 selected	522	* @arg DAC_CHANNEL_1: DAC Channel1 selected
530	* @arg DAC_CHANNEL_2: DAC Channel2 selected	523	* @arg DAC_CHANNEL_2: DAC Channel2 selected
531	* @param pData The destination peripheral Buffer address.	524	* @param pData The source Buffer address.
532	* @param Length The length of data to be transferred from memory to DAC peripheral	525	* @param Length The length of data to be transferred from memory to DAC peripheral
533	* @param Alignment Specifies the data alignment for DAC channel.	526	* @param Alignment Specifies the data alignment for DAC channel.
534	* This parameter can be one of the following values:	527	* This parameter can be one of the following values:
535	* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected	528	* @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
536	* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected	529	* @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
Line 584...	Line 577...
584	break;	577	break;
585	default:	578	default:
586	break;	579	break;
587	}	580	}
588	}	581	}
-		582
589	else	583	else
590	{	584	{
591	/* Set the DMA transfer complete callback for channel2 */	585	/* Set the DMA transfer complete callback for channel2 */
592	hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;	586	hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
593		587
Line 618...	Line 612...
618	default:	612	default:
619	break;	613	break;
620	}	614	}
621	}	615	}
622		616
-		617
623	/* Enable the DMA channel */	618	/* Enable the DMA channel */
624	if (Channel == DAC_CHANNEL_1)	619	if (Channel == DAC_CHANNEL_1)
625	{	620	{
626	/* Enable the DAC DMA underrun interrupt */	621	/* Enable the DAC DMA underrun interrupt */
627	__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);	622	__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
628		623
629	/* Enable the DMA channel */	624	/* Enable the DMA channel */
630	status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);	625	status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
631	}	626	}
-		627
632	else	628	else
633	{	629	{
634	/* Enable the DAC DMA underrun interrupt */	630	/* Enable the DAC DMA underrun interrupt */
635	__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);	631	__HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
636		632
637	/* Enable the DMA channel */	633	/* Enable the DMA channel */
638	status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);	634	status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
639	}	635	}
640		636
-		637
641	/* Process Unlocked */	638	/* Process Unlocked */
642	__HAL_UNLOCK(hdac);	639	__HAL_UNLOCK(hdac);
643		640
644	if (status == HAL_OK)	641	if (status == HAL_OK)
645	{	642	{
Line 665...	Line 662...
665	* @arg DAC_CHANNEL_2: DAC Channel2 selected	662	* @arg DAC_CHANNEL_2: DAC Channel2 selected
666	* @retval HAL status	663	* @retval HAL status
667	*/	664	*/
668	HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)	665	HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
669	{	666	{
670	HAL_StatusTypeDef status;	-
671		-
672	/* Check the parameters */	667	/* Check the parameters */
673	assert_param(IS_DAC_CHANNEL(Channel));	668	assert_param(IS_DAC_CHANNEL(Channel));
674		669
675	/* Disable the selected DAC channel DMA request */	670	/* Disable the selected DAC channel DMA request */
676	hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));	671	hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
Line 682...	Line 677...
682		677
683	/* Channel1 is used */	678	/* Channel1 is used */
684	if (Channel == DAC_CHANNEL_1)	679	if (Channel == DAC_CHANNEL_1)
685	{	680	{
686	/* Disable the DMA channel */	681	/* Disable the DMA channel */
687	status = HAL_DMA_Abort(hdac->DMA_Handle1);	682	(void)HAL_DMA_Abort(hdac->DMA_Handle1);
688		683
689	/* Disable the DAC DMA underrun interrupt */	684	/* Disable the DAC DMA underrun interrupt */
690	__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);	685	__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
691	}	686	}
-		687
692	else /* Channel2 is used for */	688	else /* Channel2 is used for */
693	{	689	{
694	/* Disable the DMA channel */	690	/* Disable the DMA channel */
695	status = HAL_DMA_Abort(hdac->DMA_Handle2);	691	(void)HAL_DMA_Abort(hdac->DMA_Handle2);
696		692
697	/* Disable the DAC DMA underrun interrupt */	693	/* Disable the DAC DMA underrun interrupt */
698	__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);	694	__HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
699	}	695	}
700		696
701	/* Check if DMA Channel effectively disabled */	-
702	if (status != HAL_OK)	-
703	{	-
704	/* Update DAC state machine to error */	-
705	hdac->State = HAL_DAC_STATE_ERROR;	-
706	}	697
707	else	-
708	{	-
709	/* Change DAC state */	698	/* Change DAC state */
710	hdac->State = HAL_DAC_STATE_READY;	699	hdac->State = HAL_DAC_STATE_READY;
711	}	-
712		700
713	/* Return function status */	701	/* Return function status */
714	return status;	702	return HAL_OK;
715	}	703	}
716		704
717	/**	705	/**
718	* @brief Handles DAC interrupt request	706	* @brief Handles DAC interrupt request
719	* This function uses the interruption of DMA	707	* This function uses the interruption of DMA
Line 730...	Line 718...
730	if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))	718	if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
731	{	719	{
732	/* Change DAC state to error state */	720	/* Change DAC state to error state */
733	hdac->State = HAL_DAC_STATE_ERROR;	721	hdac->State = HAL_DAC_STATE_ERROR;
734		722
735	/* Set DAC error code to chanel1 DMA underrun error */	723	/* Set DAC error code to channel1 DMA underrun error */
736	SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);	724	SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
737		725
738	/* Clear the underrun flag */	726	/* Clear the underrun flag */
739	__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);	727	__HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
740		728
Line 748...	Line 736...
748	HAL_DAC_DMAUnderrunCallbackCh1(hdac);	736	HAL_DAC_DMAUnderrunCallbackCh1(hdac);
749	#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */	737	#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
750	}	738	}
751	}	739	}
752		740
-		741
753	if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))	742	if (__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2))
754	{	743	{
755	/* Check underrun flag of DAC channel 2 */	744	/* Check underrun flag of DAC channel 2 */
756	if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))	745	if (__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
757	{	746	{
Line 773...	Line 762...
773	#else	762	#else
774	HAL_DACEx_DMAUnderrunCallbackCh2(hdac);	763	HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
775	#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */	764	#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
776	}	765	}
777	}	766	}
-		767
778	}	768	}
779		769
780	/**	770	/**
781	* @brief Set the specified data holding register value for DAC channel.	771	* @brief Set the specified data holding register value for DAC channel.
782	* @param hdac pointer to a DAC_HandleTypeDef structure that contains	772	* @param hdac pointer to a DAC_HandleTypeDef structure that contains
Line 793...	Line 783...
793	* @param Data Data to be loaded in the selected data holding register.	783	* @param Data Data to be loaded in the selected data holding register.
794	* @retval HAL status	784	* @retval HAL status
795	*/	785	*/
796	HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)	786	HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
797	{	787	{
798	__IO uint32_t tmp = 0;	788	__IO uint32_t tmp = 0UL;
799		789
800	/* Check the parameters */	790	/* Check the parameters */
801	assert_param(IS_DAC_CHANNEL(Channel));	791	assert_param(IS_DAC_CHANNEL(Channel));
802	assert_param(IS_DAC_ALIGN(Alignment));	792	assert_param(IS_DAC_ALIGN(Alignment));
803	assert_param(IS_DAC_DATA(Data));	793	assert_param(IS_DAC_DATA(Data));
Line 805...	Line 795...
805	tmp = (uint32_t)hdac->Instance;	795	tmp = (uint32_t)hdac->Instance;
806	if (Channel == DAC_CHANNEL_1)	796	if (Channel == DAC_CHANNEL_1)
807	{	797	{
808	tmp += DAC_DHR12R1_ALIGNMENT(Alignment);	798	tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
809	}	799	}
-		800
810	else	801	else
811	{	802	{
812	tmp += DAC_DHR12R2_ALIGNMENT(Alignment);	803	tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
813	}	804	}
814		805
-		806
815	/* Set the DAC channel selected data holding register */	807	/* Set the DAC channel selected data holding register */
816	(__IO uint32_t ) tmp = Data;	808	(__IO uint32_t ) tmp = Data;
817		809
818	/* Return function status */	810	/* Return function status */
819	return HAL_OK;	811	return HAL_OK;
Line 912...	Line 904...
912	* @arg DAC_CHANNEL_2: DAC Channel2 selected	904	* @arg DAC_CHANNEL_2: DAC Channel2 selected
913	* @retval The selected DAC channel data output value.	905	* @retval The selected DAC channel data output value.
914	*/	906	*/
915	uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)	907	uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel)
916	{	908	{
-		909	uint32_t result;
-		910
917	/* Check the parameters */	911	/* Check the parameters */
918	assert_param(IS_DAC_CHANNEL(Channel));	912	assert_param(IS_DAC_CHANNEL(Channel));
919		913
920	/* Returns the DAC channel data output register value */	-
921	if (Channel == DAC_CHANNEL_1)	914	if (Channel == DAC_CHANNEL_1)
922	{	915	{
923	return hdac->Instance->DOR1;	916	result = hdac->Instance->DOR1;
924	}	917	}
-		918
925	else	919	else
926	{	920	{
927	return hdac->Instance->DOR2;	921	result = hdac->Instance->DOR2;
928	}	922	}
-		923
-		924	/* Returns the DAC channel data output register value */
-		925	return result;
929	}	926	}
930		927
931	/**	928	/**
932	* @brief Configures the selected DAC channel.	929	* @brief Configures the selected DAC channel.
933	* @param hdac pointer to a DAC_HandleTypeDef structure that contains	930	* @param hdac pointer to a DAC_HandleTypeDef structure that contains
Line 956...	Line 953...
956	hdac->State = HAL_DAC_STATE_BUSY;	953	hdac->State = HAL_DAC_STATE_BUSY;
957		954
958	/* Get the DAC CR value */	955	/* Get the DAC CR value */
959	tmpreg1 = hdac->Instance->CR;	956	tmpreg1 = hdac->Instance->CR;
960	/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */	957	/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
961	tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 \| DAC_CR_WAVE1 \| DAC_CR_TSEL1 \| DAC_CR_TEN1 \| DAC_CR_BOFF1)) << Channel);	958	tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 \| DAC_CR_WAVE1 \| DAC_CR_TSEL1 \| DAC_CR_TEN1 \| DAC_CR_BOFF1)) << (Channel & 0x10UL));
962	/* Configure for the selected DAC channel: buffer output, trigger */	959	/* Configure for the selected DAC channel: buffer output, trigger */
963	/* Set TSELx and TENx bits according to DAC_Trigger value */	960	/* Set TSELx and TENx bits according to DAC_Trigger value */
964	/* Set BOFFx bit according to DAC_OutputBuffer value */	961	/* Set BOFFx bit according to DAC_OutputBuffer value */
965	tmpreg2 = (sConfig->DAC_Trigger \| sConfig->DAC_OutputBuffer);	962	tmpreg2 = (sConfig->DAC_Trigger \| sConfig->DAC_OutputBuffer);
966	/* Calculate CR register value depending on DAC_Channel */	963	/* Calculate CR register value depending on DAC_Channel */
967	tmpreg1 \|= tmpreg2 << Channel;	964	tmpreg1 \|= tmpreg2 << (Channel & 0x10UL);
968	/* Write to DAC CR */	965	/* Write to DAC CR */
969	hdac->Instance->CR = tmpreg1;	966	hdac->Instance->CR = tmpreg1;
970	/* Disable wave generation */	967	/* Disable wave generation */
971	CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << Channel));	968	CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
972	/* Disable wave generation */	-
973	hdac->Instance->CR &= ~(DAC_CR_WAVE1 << (Channel & 0x10UL));	-
974		969
975	/* Change DAC state */	970	/* Change DAC state */
976	hdac->State = HAL_DAC_STATE_READY;	971	hdac->State = HAL_DAC_STATE_READY;
977		972
978	/* Process unlocked */	973	/* Process unlocked */
Line 1092...	Line 1087...
1092	hdac->ErrorCallbackCh1 = pCallback;	1087	hdac->ErrorCallbackCh1 = pCallback;
1093	break;	1088	break;
1094	case HAL_DAC_CH1_UNDERRUN_CB_ID :	1089	case HAL_DAC_CH1_UNDERRUN_CB_ID :
1095	hdac->DMAUnderrunCallbackCh1 = pCallback;	1090	hdac->DMAUnderrunCallbackCh1 = pCallback;
1096	break;	1091	break;
-		1092
1097	case HAL_DAC_CH2_COMPLETE_CB_ID :	1093	case HAL_DAC_CH2_COMPLETE_CB_ID :
1098	hdac->ConvCpltCallbackCh2 = pCallback;	1094	hdac->ConvCpltCallbackCh2 = pCallback;
1099	break;	1095	break;
1100	case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :	1096	case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
1101	hdac->ConvHalfCpltCallbackCh2 = pCallback;	1097	hdac->ConvHalfCpltCallbackCh2 = pCallback;
Line 1104...	Line 1100...
1104	hdac->ErrorCallbackCh2 = pCallback;	1100	hdac->ErrorCallbackCh2 = pCallback;
1105	break;	1101	break;
1106	case HAL_DAC_CH2_UNDERRUN_CB_ID :	1102	case HAL_DAC_CH2_UNDERRUN_CB_ID :
1107	hdac->DMAUnderrunCallbackCh2 = pCallback;	1103	hdac->DMAUnderrunCallbackCh2 = pCallback;
1108	break;	1104	break;
-		1105
1109	case HAL_DAC_MSPINIT_CB_ID :	1106	case HAL_DAC_MSPINIT_CB_ID :
1110	hdac->MspInitCallback = pCallback;	1107	hdac->MspInitCallback = pCallback;
1111	break;	1108	break;
1112	case HAL_DAC_MSPDEINIT_CB_ID :	1109	case HAL_DAC_MSPDEINIT_CB_ID :
1113	hdac->MspDeInitCallback = pCallback;	1110	hdac->MspDeInitCallback = pCallback;
Line 1155...	Line 1152...
1155	* @brief Unregister a User DAC Callback	1152	* @brief Unregister a User DAC Callback
1156	* DAC Callback is redirected to the weak (surcharged) predefined callback	1153	* DAC Callback is redirected to the weak (surcharged) predefined callback
1157	* @param hdac DAC handle	1154	* @param hdac DAC handle
1158	* @param CallbackID ID of the callback to be unregistered	1155	* @param CallbackID ID of the callback to be unregistered
1159	* This parameter can be one of the following values:	1156	* This parameter can be one of the following values:
1160	* @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID	1157	* @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 transfer Complete Callback ID
1161	* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID	1158	* @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID
1162	* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID	1159	* @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID
1163	* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID	1160	* @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID
1164	* @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID	1161	* @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID
1165	* @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID	1162	* @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID
Line 1191...	Line 1188...
1191	hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;	1188	hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
1192	break;	1189	break;
1193	case HAL_DAC_CH1_UNDERRUN_CB_ID :	1190	case HAL_DAC_CH1_UNDERRUN_CB_ID :
1194	hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;	1191	hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
1195	break;	1192	break;
-		1193
1196	case HAL_DAC_CH2_COMPLETE_CB_ID :	1194	case HAL_DAC_CH2_COMPLETE_CB_ID :
1197	hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;	1195	hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
1198	break;	1196	break;
1199	case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :	1197	case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
1200	hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;	1198	hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
Line 1203...	Line 1201...
1203	hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;	1201	hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
1204	break;	1202	break;
1205	case HAL_DAC_CH2_UNDERRUN_CB_ID :	1203	case HAL_DAC_CH2_UNDERRUN_CB_ID :
1206	hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;	1204	hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
1207	break;	1205	break;
-		1206
1208	case HAL_DAC_MSPINIT_CB_ID :	1207	case HAL_DAC_MSPINIT_CB_ID :
1209	hdac->MspInitCallback = HAL_DAC_MspInit;	1208	hdac->MspInitCallback = HAL_DAC_MspInit;
1210	break;	1209	break;
1211	case HAL_DAC_MSPDEINIT_CB_ID :	1210	case HAL_DAC_MSPDEINIT_CB_ID :
1212	hdac->MspDeInitCallback = HAL_DAC_MspDeInit;	1211	hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
Line 1214...	Line 1213...
1214	case HAL_DAC_ALL_CB_ID :	1213	case HAL_DAC_ALL_CB_ID :
1215	hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;	1214	hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
1216	hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;	1215	hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
1217	hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;	1216	hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
1218	hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;	1217	hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
-		1218
1219	hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;	1219	hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
1220	hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;	1220	hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
1221	hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;	1221	hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
1222	hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;	1222	hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
-		1223
1223	hdac->MspInitCallback = HAL_DAC_MspInit;	1224	hdac->MspInitCallback = HAL_DAC_MspInit;
1224	hdac->MspDeInitCallback = HAL_DAC_MspDeInit;	1225	hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
1225	break;	1226	break;
1226	default :	1227	default :
1227	/* Update the error code */	1228	/* Update the error code */

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(root)/branches/Dashboard_L152_v2/Drivers/STM32L1xx_HAL_Driver/Src/stm32l1xx_hal_dac.c – Rev 56 → 61